-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Tue Nov 16 19:36:55 2021
-- Host        : hog-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_full_aurora/ila_full_aurora_sim_netlist.vhdl
-- Design      : ila_full_aurora
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx550tffg1927-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper";
end ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper is
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"11111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 5) => Q(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"11111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\,
      CLKBWRCLK => s_dclk_o,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
      DOBDO(31 downto 24) => D(34 downto 27),
      DOBDO(23 downto 16) => D(25 downto 18),
      DOBDO(15 downto 8) => D(16 downto 9),
      DOBDO(7 downto 0) => D(7 downto 0),
      DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
      DOPBDOP(3) => D(35),
      DOPBDOP(2) => D(26),
      DOPBDOP(1) => D(17),
      DOPBDOP(0) => D(8),
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \out\,
      ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0\ is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0\ is
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"11111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 5) => Q(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"11111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\,
      CLKBWRCLK => s_dclk_o,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(31 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3 downto 0),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
      DOBDO(31 downto 24) => D(34 downto 27),
      DOBDO(23 downto 16) => D(25 downto 18),
      DOBDO(15 downto 8) => D(16 downto 9),
      DOBDO(7 downto 0) => D(7 downto 0),
      DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
      DOPBDOP(3) => D(35),
      DOPBDOP(2) => D(26),
      DOPBDOP(1) => D(17),
      DOPBDOP(0) => D(8),
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \out\,
      ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1\ is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1\ is
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"11111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 5) => Q(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"11111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\,
      CLKBWRCLK => s_dclk_o,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(31 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3 downto 0),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
      DOBDO(31 downto 24) => D(34 downto 27),
      DOBDO(23 downto 16) => D(25 downto 18),
      DOBDO(15 downto 8) => D(16 downto 9),
      DOBDO(7 downto 0) => D(7 downto 0),
      DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
      DOPBDOP(3) => D(35),
      DOPBDOP(2) => D(26),
      DOPBDOP(1) => D(17),
      DOPBDOP(0) => D(8),
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \out\,
      ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2\ is
  port (
    D : out STD_LOGIC_VECTOR ( 30 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2\ is
  signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_36\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74\ : STD_LOGIC;
  signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 1,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      RSTREG_PRIORITY_A => "REGCE",
      RSTREG_PRIORITY_B => "REGCE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0),
      ADDRARDADDR(4 downto 0) => B"11111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 5) => Q(9 downto 0),
      ADDRBWRADDR(4 downto 0) => B"11111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\,
      CLKBWRCLK => s_dclk_o,
      DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(30 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 0) => B"0000",
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
      DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_36\,
      DOBDO(30 downto 0) => D(30 downto 0),
      DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
      DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72\,
      DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73\,
      DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74\,
      DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75\,
      ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => \out\,
      ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice is
  port (
    SRL_D_I : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DOUT_O : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => DOUT_O,
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_D_I,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_10 is
  port (
    srl_q_0 : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_10 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_10;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_10 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CO(0),
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => srl_q_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_12 is
  port (
    srl_q_0 : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_dly1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    all_dly2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_12 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_12;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_12 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CO(0),
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => srl_q_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_dly1(0),
      I1 => all_dly2(0),
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_15 is
  port (
    srl_q_0 : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_dly1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    all_dly2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_15 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_15;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_15 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CO(0),
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => srl_q_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_dly1(0),
      I1 => all_dly2(0),
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_23 is
  port (
    SRL_D_I : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DOUT_O : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_23 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_23;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_23 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => DOUT_O,
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_D_I,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_25 is
  port (
    srl_q_0 : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    tc_config_cs_serial_output : in STD_LOGIC;
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_25 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_25;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_25 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1\(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CO(0),
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => srl_q_0,
      CE => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\(0),
      CLK => s_dclk_o,
      I0 => D(0),
      I1 => Q(0),
      I2 => D(1),
      I3 => Q(1),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\(0),
      CLK => s_dclk_o,
      I0 => D(2),
      I1 => Q(2),
      I2 => D(3),
      I3 => Q(3),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\(0),
      CLK => s_dclk_o,
      I0 => D(4),
      I1 => Q(4),
      I2 => D(5),
      I3 => Q(5),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => tc_config_cs_serial_output,
      CDO => cfg_data_2,
      CE => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_9 is
  port (
    SRL_D_I : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DOUT_O : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_9 : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_9;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_9 is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal muxcy_lo : STD_LOGIC_VECTOR ( 3 to 3 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      CE => '1',
      D => muxcy_lo(3),
      Q => \out\,
      R => Q(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => DOUT_O,
      CO(3) => muxcy_lo(3),
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_D_I,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => mu_config_cs_serial_output(0),
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_16\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_16\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_16\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_16\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_17\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_17\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_17\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_17\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_18\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_18\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_18\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_18\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_19\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_19\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_19\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_19\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_2\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_2\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_2\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_2\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_20\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_20\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_20\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_20\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_21\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_21\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_21\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_21\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_22\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_22\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_22\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_22\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_3\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_3\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_3\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_3\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_6\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_6\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_6\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_6\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_7\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_7\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_7\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_7\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_8\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_8\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_8\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_8\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(0),
      I1 => all_in(1),
      I2 => all_in(2),
      I3 => all_in(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(4),
      I1 => all_in(5),
      I2 => all_in(6),
      I3 => all_in(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(8),
      I1 => all_in(9),
      I2 => all_in(10),
      I3 => all_in(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      I0 => all_in(12),
      I1 => all_in(13),
      I2 => all_in(14),
      I3 => all_in(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(4),
      I1 => PROBES_I(5),
      I2 => PROBES_I(6),
      I3 => PROBES_I(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(8),
      I1 => PROBES_I(9),
      I2 => PROBES_I(10),
      I3 => PROBES_I(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(12),
      I1 => PROBES_I(13),
      I2 => PROBES_I(14),
      I3 => PROBES_I(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_52\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_52\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_52\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_52\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(4),
      I1 => PROBES_I(5),
      I2 => PROBES_I(6),
      I3 => PROBES_I(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(8),
      I1 => PROBES_I(9),
      I2 => PROBES_I(10),
      I3 => PROBES_I(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(12),
      I1 => PROBES_I(13),
      I2 => PROBES_I(14),
      I3 => PROBES_I(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_60\ is
  port (
    shift_en_reg : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : in STD_LOGIC;
    u_carry4_inst_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_60\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_60\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_60\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => shift_en_reg,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(4),
      I1 => PROBES_I(5),
      I2 => PROBES_I(6),
      I3 => PROBES_I(7),
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(8),
      I1 => PROBES_I(9),
      I2 => PROBES_I(10),
      I3 => PROBES_I(11),
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_Q_O,
      CDO => cfg_data_2,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(12),
      I1 => PROBES_I(13),
      I2 => PROBES_I(14),
      I3 => PROBES_I(15),
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => shift_en_reg,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_53\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_53\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_53\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_53\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => shift_en_reg,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => E(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_61\ is
  port (
    SRL_Q_O : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    SRL_D_I : in STD_LOGIC;
    u_carry4_inst_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
    CI_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_61\ : entity is "ltlib_v1_0_0_all_typeA_slice";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_61\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_61\ is
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal mux_di : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlA : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlB : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlC : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srlD : label is "PRIMITIVE";
begin
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => CI_I,
      CO(3) => DOUT_O,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => mux_di(3 downto 0),
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 0) => sel(3 downto 0)
    );
u_srlA: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_0,
      CDO => SRL_Q_O,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => PROBES_I(0),
      I1 => PROBES_I(1),
      I2 => PROBES_I(2),
      I3 => PROBES_I(3),
      I4 => '1',
      O5 => mux_di(0),
      O6 => sel(0)
    );
u_srlB: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_1,
      CDO => cfg_data_0,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(1),
      O6 => sel(1)
    );
u_srlC: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => cfg_data_2,
      CDO => cfg_data_1,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(2),
      O6 => sel(2)
    );
u_srlD: unisim.vcomponents.CFGLUT5
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      CDI => SRL_D_I,
      CDO => cfg_data_2,
      CE => u_carry4_inst_0(0),
      CLK => s_dclk_o,
      I0 => '1',
      I1 => '1',
      I2 => '1',
      I3 => '1',
      I4 => '1',
      O5 => mux_di(3),
      O6 => sel(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_async_edge_xfer is
  port (
    \out\ : out STD_LOGIC;
    dout_reg1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    dout_reg0_reg_0 : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    arm_ctrl : in STD_LOGIC;
    last_din : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_full_aurora_ltlib_v1_0_0_async_edge_xfer;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer is
  signal din_reg : STD_LOGIC;
  attribute shreg_extract : string;
  attribute shreg_extract of din_reg : signal is "no";
  signal \din_reg_i_1__0_n_0\ : STD_LOGIC;
  signal dout_reg0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of dout_reg0 : signal is "true";
  attribute shreg_extract of dout_reg0 : signal is "no";
  signal dout_reg1 : STD_LOGIC;
  attribute async_reg of dout_reg1 : signal is "true";
  attribute shreg_extract of dout_reg1 : signal is "no";
  signal temp_reg0 : STD_LOGIC;
  attribute async_reg of temp_reg0 : signal is "true";
  signal temp_reg1 : STD_LOGIC;
  attribute async_reg of temp_reg1 : signal is "true";
  attribute SHREG_EXTRACT of din_reg_reg : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of dout_reg0_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of dout_reg0_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg0_reg : label is "no";
  attribute ASYNC_REG_boolean of dout_reg1_reg : label is std.standard.true;
  attribute KEEP of dout_reg1_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg1_reg : label is "no";
  attribute ASYNC_REG_boolean of temp_reg0_reg : label is std.standard.true;
  attribute KEEP of temp_reg0_reg : label is "yes";
  attribute ASYNC_REG_boolean of temp_reg1_reg : label is std.standard.true;
  attribute KEEP of temp_reg1_reg : label is "yes";
begin
  \out\ <= dout_reg1;
\din_reg_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => arm_ctrl,
      I1 => temp_reg1,
      I2 => din_reg,
      I3 => din_reg,
      O => \din_reg_i_1__0_n_0\
    );
din_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \din_reg_i_1__0_n_0\,
      Q => din_reg,
      R => '0'
    );
\dout_pulse[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dout_reg1,
      I1 => last_din,
      O => dout_reg1_reg_0(0)
    );
dout_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dout_reg0_reg_0,
      CE => '1',
      D => din_reg,
      Q => dout_reg0,
      R => '0'
    );
dout_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dout_reg0_reg_0,
      CE => '1',
      D => dout_reg0,
      Q => dout_reg1,
      R => '0'
    );
temp_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => dout_reg1,
      Q => temp_reg0,
      R => '0'
    );
temp_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => temp_reg0,
      Q => temp_reg1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_26 is
  port (
    dout_reg1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    temp_reg1_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_26 : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_26;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_26 is
  signal din_reg : STD_LOGIC;
  attribute shreg_extract : string;
  attribute shreg_extract of din_reg : signal is "no";
  signal \din_reg_i_1__1_n_0\ : STD_LOGIC;
  signal dout_reg0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of dout_reg0 : signal is "true";
  attribute shreg_extract of dout_reg0 : signal is "no";
  signal dout_reg1 : STD_LOGIC;
  attribute async_reg of dout_reg1 : signal is "true";
  attribute shreg_extract of dout_reg1 : signal is "no";
  signal temp_reg0 : STD_LOGIC;
  attribute async_reg of temp_reg0 : signal is "true";
  signal temp_reg1 : STD_LOGIC;
  attribute async_reg of temp_reg1 : signal is "true";
  attribute SHREG_EXTRACT of din_reg_reg : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of dout_reg0_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of dout_reg0_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg0_reg : label is "no";
  attribute ASYNC_REG_boolean of dout_reg1_reg : label is std.standard.true;
  attribute KEEP of dout_reg1_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg1_reg : label is "no";
  attribute ASYNC_REG_boolean of temp_reg0_reg : label is std.standard.true;
  attribute KEEP of temp_reg0_reg : label is "yes";
  attribute ASYNC_REG_boolean of temp_reg1_reg : label is std.standard.true;
  attribute KEEP of temp_reg1_reg : label is "yes";
begin
  dout_reg1_reg_0(0) <= dout_reg1;
\din_reg_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7D41"
    )
        port map (
      I0 => Q(0),
      I1 => temp_reg1,
      I2 => din_reg,
      I3 => din_reg,
      O => \din_reg_i_1__1_n_0\
    );
din_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg1_reg_0,
      CE => '1',
      D => \din_reg_i_1__1_n_0\,
      Q => din_reg,
      R => '0'
    );
dout_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => din_reg,
      Q => dout_reg0,
      R => '0'
    );
dout_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => dout_reg0,
      Q => dout_reg1,
      R => '0'
    );
temp_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg1_reg_0,
      CE => '1',
      D => dout_reg1,
      Q => temp_reg0,
      R => '0'
    );
temp_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg1_reg_0,
      CE => '1',
      D => temp_reg0,
      Q => temp_reg1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_27 is
  port (
    \out\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    dout_reg0_reg_0 : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    halt_ctrl : in STD_LOGIC;
    last_din : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_27 : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_27;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_27 is
  signal din_reg : STD_LOGIC;
  attribute shreg_extract : string;
  attribute shreg_extract of din_reg : signal is "no";
  signal din_reg_i_1_n_0 : STD_LOGIC;
  signal dout_reg0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of dout_reg0 : signal is "true";
  attribute shreg_extract of dout_reg0 : signal is "no";
  signal dout_reg1 : STD_LOGIC;
  attribute async_reg of dout_reg1 : signal is "true";
  attribute shreg_extract of dout_reg1 : signal is "no";
  signal temp_reg0 : STD_LOGIC;
  attribute async_reg of temp_reg0 : signal is "true";
  signal temp_reg1 : STD_LOGIC;
  attribute async_reg of temp_reg1 : signal is "true";
  attribute SHREG_EXTRACT of din_reg_reg : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of dout_reg0_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of dout_reg0_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg0_reg : label is "no";
  attribute ASYNC_REG_boolean of dout_reg1_reg : label is std.standard.true;
  attribute KEEP of dout_reg1_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg1_reg : label is "no";
  attribute ASYNC_REG_boolean of temp_reg0_reg : label is std.standard.true;
  attribute KEEP of temp_reg0_reg : label is "yes";
  attribute ASYNC_REG_boolean of temp_reg1_reg : label is std.standard.true;
  attribute KEEP of temp_reg1_reg : label is "yes";
begin
  \out\ <= dout_reg1;
din_reg_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => halt_ctrl,
      I1 => temp_reg1,
      I2 => din_reg,
      I3 => din_reg,
      O => din_reg_i_1_n_0
    );
din_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => din_reg_i_1_n_0,
      Q => din_reg,
      R => '0'
    );
\dout_pulse[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dout_reg1,
      I1 => last_din,
      O => D(0)
    );
dout_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dout_reg0_reg_0,
      CE => '1',
      D => din_reg,
      Q => dout_reg0,
      R => '0'
    );
dout_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => dout_reg0_reg_0,
      CE => '1',
      D => dout_reg0,
      Q => dout_reg1,
      R => '0'
    );
temp_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => dout_reg1,
      Q => temp_reg0,
      R => '0'
    );
temp_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => temp_reg0,
      Q => temp_reg1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_28 is
  port (
    dout_reg1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    temp_reg0_reg_0 : in STD_LOGIC;
    halt_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_28 : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_28;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_28 is
  signal din_reg : STD_LOGIC;
  attribute shreg_extract : string;
  attribute shreg_extract of din_reg : signal is "no";
  signal \din_reg_i_1__2_n_0\ : STD_LOGIC;
  signal dout_reg0 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of dout_reg0 : signal is "true";
  attribute shreg_extract of dout_reg0 : signal is "no";
  signal dout_reg1 : STD_LOGIC;
  attribute async_reg of dout_reg1 : signal is "true";
  attribute shreg_extract of dout_reg1 : signal is "no";
  signal temp_reg0 : STD_LOGIC;
  attribute async_reg of temp_reg0 : signal is "true";
  signal temp_reg1 : STD_LOGIC;
  attribute async_reg of temp_reg1 : signal is "true";
  attribute SHREG_EXTRACT of din_reg_reg : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of dout_reg0_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of dout_reg0_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg0_reg : label is "no";
  attribute ASYNC_REG_boolean of dout_reg1_reg : label is std.standard.true;
  attribute KEEP of dout_reg1_reg : label is "yes";
  attribute SHREG_EXTRACT of dout_reg1_reg : label is "no";
  attribute ASYNC_REG_boolean of temp_reg0_reg : label is std.standard.true;
  attribute KEEP of temp_reg0_reg : label is "yes";
  attribute ASYNC_REG_boolean of temp_reg1_reg : label is std.standard.true;
  attribute KEEP of temp_reg1_reg : label is "yes";
begin
  dout_reg1_reg_0(0) <= dout_reg1;
\din_reg_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BE82"
    )
        port map (
      I0 => halt_out,
      I1 => temp_reg1,
      I2 => din_reg,
      I3 => din_reg,
      O => \din_reg_i_1__2_n_0\
    );
din_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg0_reg_0,
      CE => '1',
      D => \din_reg_i_1__2_n_0\,
      Q => din_reg,
      R => '0'
    );
dout_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => din_reg,
      Q => dout_reg0,
      R => '0'
    );
dout_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => dout_reg0,
      Q => dout_reg1,
      R => '0'
    );
temp_reg0_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg0_reg_0,
      CE => '1',
      D => dout_reg1,
      Q => temp_reg0,
      R => '0'
    );
temp_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => temp_reg0_reg_0,
      CE => '1',
      D => temp_reg0,
      Q => temp_reg1,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut4 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : out STD_LOGIC;
    \iwcnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    SRL_Q_O : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut4 : entity is "ltlib_v1_0_0_cfglut4";
end ila_full_aurora_ltlib_v1_0_0_cfglut4;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut4 is
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRLC16E\ : label is "PRIMITIVE";
begin
\I_YESLUT6.U_SRLC16E\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => A(0),
      A1 => A(1),
      A2 => A(2),
      A3 => A(3),
      CE => \iwcnt_reg[0]\(0),
      CLK => s_dclk_o,
      D => SRL_Q_O,
      Q => E(0),
      Q15 => cfg_data_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut4_54 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : out STD_LOGIC;
    \iscnt_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_1 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut4_54 : entity is "ltlib_v1_0_0_cfglut4";
end ila_full_aurora_ltlib_v1_0_0_cfglut4_54;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut4_54 is
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRLC16E\ : label is "PRIMITIVE";
begin
\I_YESLUT6.U_SRLC16E\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => A(0),
      A1 => A(1),
      A2 => A(2),
      A3 => A(3),
      CE => \iscnt_reg[9]\(0),
      CLK => s_dclk_o,
      D => cfg_data_1,
      Q => E(0),
      Q15 => cfg_data_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut5 is
  port (
    wcnt_hcmp_ce : out STD_LOGIC;
    SRL_D_I : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    SRL_Q_O : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut5 : entity is "ltlib_v1_0_0_cfglut5";
end ila_full_aurora_ltlib_v1_0_0_cfglut5;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut5 is
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 ";
begin
\I_YESLUT6.U_SRL32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => SRL_Q_O,
      Q => wcnt_hcmp_ce,
      Q31 => SRL_D_I
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut5_48 is
  port (
    wcnt_lcmp_ce : out STD_LOGIC;
    SRL_D_I : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut5_48 : entity is "ltlib_v1_0_0_cfglut5";
end ila_full_aurora_ltlib_v1_0_0_cfglut5_48;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut5_48 is
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 ";
begin
\I_YESLUT6.U_SRL32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => cfg_data_0,
      Q => wcnt_lcmp_ce,
      Q31 => SRL_D_I
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut5_55 is
  port (
    scnt_cmp_ce : out STD_LOGIC;
    cfg_data_1_0 : out STD_LOGIC;
    u_scnt_cmp_q : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut5_55 : entity is "ltlib_v1_0_0_cfglut5";
end ila_full_aurora_ltlib_v1_0_0_cfglut5_55;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut5_55 is
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 ";
begin
\I_YESLUT6.U_SRL32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => u_scnt_cmp_q(0),
      CLK => s_dclk_o,
      D => cfg_data_0,
      Q => scnt_cmp_ce,
      Q31 => cfg_data_1_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut6 is
  port (
    cfg_data_1 : out STD_LOGIC;
    cmp_reset : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC;
    u_wcnt_hcmp_q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut6 : entity is "ltlib_v1_0_0_cfglut6";
end ila_full_aurora_ltlib_v1_0_0_cfglut6;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut6 is
  signal \I_YESLUT6.SRL_Q31\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_1\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_A\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32_A\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_B\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_B\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B ";
begin
\I_YESLUT6.U_SRL32_A\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31\,
      Q => \I_YESLUT6.SRL_Q_1\,
      Q31 => cfg_data_1
    );
\I_YESLUT6.U_SRL32_B\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => cfg_data_0,
      Q => \I_YESLUT6.SRL_Q_0\,
      Q31 => \I_YESLUT6.SRL_Q31\
    );
u_scnt_cmp_q_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \I_YESLUT6.SRL_Q_1\,
      I1 => u_wcnt_hcmp_q(0),
      I2 => \I_YESLUT6.SRL_Q_0\,
      O => cmp_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut6_56 is
  port (
    \capture_qual_ctrl_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SRL_D_I : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \iscnt_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_1_0 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_dclk_o : in STD_LOGIC;
    u_scnt_cmp_q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    basic_trigger : in STD_LOGIC;
    u_scnt_cmp_q_0 : in STD_LOGIC;
    \iscnt_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut6_56 : entity is "ltlib_v1_0_0_cfglut6";
end ila_full_aurora_ltlib_v1_0_0_cfglut6_56;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut6_56 is
  signal \I_YESLUT6.SRL_Q31\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_1\ : STD_LOGIC;
  signal \^capture_qual_ctrl_reg[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_A\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32_A\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_B\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_B\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B ";
begin
  \capture_qual_ctrl_reg[0]\(1 downto 0) <= \^capture_qual_ctrl_reg[0]\(1 downto 0);
\I_YESLUT6.U_SRL32_A\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4) => A(2),
      A(3 downto 2) => \^capture_qual_ctrl_reg[0]\(1 downto 0),
      A(1 downto 0) => A(1 downto 0),
      CE => \iscnt_reg[9]\(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31\,
      Q => \I_YESLUT6.SRL_Q_1\,
      Q31 => SRL_D_I
    );
\I_YESLUT6.U_SRL32_B\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4) => A(2),
      A(3 downto 2) => \^capture_qual_ctrl_reg[0]\(1 downto 0),
      A(1 downto 0) => A(1 downto 0),
      CE => \iscnt_reg[9]\(0),
      CLK => s_dclk_o,
      D => cfg_data_1_0,
      Q => \I_YESLUT6.SRL_Q_0\,
      Q31 => \I_YESLUT6.SRL_Q31\
    );
\I_YESLUT6.U_SRL32_D_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => u_scnt_cmp_q(0),
      I1 => u_scnt_cmp_q(1),
      O => \^capture_qual_ctrl_reg[0]\(1)
    );
\I_YESLUT6.U_SRL32_D_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => basic_trigger,
      I1 => u_scnt_cmp_q_0,
      O => \^capture_qual_ctrl_reg[0]\(0)
    );
\iscnt[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \I_YESLUT6.SRL_Q_1\,
      I1 => \iscnt_reg[9]_0\(0),
      I2 => \I_YESLUT6.SRL_Q_0\,
      O => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_cfglut6__parameterized0\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    CAP_DONE_O_reg : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    SRL_Q_O : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC;
    \I_YESLUT6.I_YES_OREG.O_reg_reg_0\ : in STD_LOGIC;
    CAP_DONE_O_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wcnt_hcmp : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_cfglut6__parameterized0\ : entity is "ltlib_v1_0_0_cfglut6";
end \ila_full_aurora_ltlib_v1_0_0_cfglut6__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_cfglut6__parameterized0\ is
  signal \I_YESLUT6.SRL_MUX\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_1\ : STD_LOGIC;
  signal cap_done_i : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_A\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32_A\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_B\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_B\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B ";
begin
CAP_DONE_O_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A0AE"
    )
        port map (
      I0 => CAP_DONE_O_reg_0(0),
      I1 => cap_done_i,
      I2 => Q(0),
      I3 => Q(1),
      O => CAP_DONE_O_reg
    );
\I_YESLUT6.I_YES_OREG.O_reg_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \I_YESLUT6.SRL_Q_1\,
      I1 => wcnt_hcmp,
      I2 => \I_YESLUT6.SRL_Q_0\,
      O => \I_YESLUT6.SRL_MUX\
    );
\I_YESLUT6.I_YES_OREG.O_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_YESLUT6.I_YES_OREG.O_reg_reg_0\,
      CE => '1',
      D => \I_YESLUT6.SRL_MUX\,
      Q => cap_done_i,
      R => '0'
    );
\I_YESLUT6.U_SRL32_A\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31\,
      Q => \I_YESLUT6.SRL_Q_1\,
      Q31 => D(0)
    );
\I_YESLUT6.U_SRL32_B\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => A(4 downto 0),
      CE => E(0),
      CLK => s_dclk_o,
      D => SRL_Q_O,
      Q => \I_YESLUT6.SRL_Q_0\,
      Q31 => \I_YESLUT6.SRL_Q31\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut7 is
  port (
    \I_YESLUT6.I_YES_OREG.O_reg_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_YESLUT6.I_YES_OREG.O_reg_reg_1\ : in STD_LOGIC;
    wcnt_hcmp : in STD_LOGIC;
    \I_YESLUT6.I_YES_OREG.O_reg_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut7 : entity is "ltlib_v1_0_0_cfglut7";
end ila_full_aurora_ltlib_v1_0_0_cfglut7;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut7 is
  signal \^i_yeslut6.i_yes_oreg.o_reg_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \I_YESLUT6.SRL_MUX8_n_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_1\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_2\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_1\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_2\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_3\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_A\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32_A\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_B\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_B\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_C\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_C\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_D\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_D\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D ";
begin
  \I_YESLUT6.I_YES_OREG.O_reg_reg_0\(0) <= \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0);
\I_YESLUT6.I_YES_OREG.O_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\,
      CE => '1',
      D => \I_YESLUT6.SRL_MUX8_n_0\,
      Q => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      R => Q(0)
    );
\I_YESLUT6.SRL_MUX8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \I_YESLUT6.SRL_Q_3\,
      I1 => \I_YESLUT6.SRL_Q_2\,
      I2 => wcnt_hcmp,
      I3 => \I_YESLUT6.SRL_Q_1\,
      I4 => \I_YESLUT6.I_YES_OREG.O_reg_reg_2\(0),
      I5 => \I_YESLUT6.SRL_Q_0\,
      O => \I_YESLUT6.SRL_MUX8_n_0\
    );
\I_YESLUT6.U_SRL32_A\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 1) => A(3 downto 0),
      A(0) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_2\,
      Q => \I_YESLUT6.SRL_Q_3\,
      Q31 => in0(0)
    );
\I_YESLUT6.U_SRL32_B\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 1) => A(3 downto 0),
      A(0) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_1\,
      Q => \I_YESLUT6.SRL_Q_2\,
      Q31 => \I_YESLUT6.SRL_Q31_2\
    );
\I_YESLUT6.U_SRL32_C\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 1) => A(3 downto 0),
      A(0) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_0\,
      Q => \I_YESLUT6.SRL_Q_1\,
      Q31 => \I_YESLUT6.SRL_Q31_1\
    );
\I_YESLUT6.U_SRL32_D\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 1) => A(3 downto 0),
      A(0) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => cfg_data_0,
      Q => \I_YESLUT6.SRL_Q_0\,
      Q31 => \I_YESLUT6.SRL_Q31_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_cfglut7_47 is
  port (
    \I_YESLUT6.I_YES_OREG.O_reg_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_0 : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    capture_ctrl_config_serial_output : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \I_YESLUT6.I_YES_OREG.O_reg_reg_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_YESLUT6.I_YES_OREG.O_reg_reg_2\ : in STD_LOGIC;
    wcnt_hcmp : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_cfglut7_47 : entity is "ltlib_v1_0_0_cfglut7";
end ila_full_aurora_ltlib_v1_0_0_cfglut7_47;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_cfglut7_47 is
  signal \^i_yeslut6.i_yes_oreg.o_reg_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \I_YESLUT6.SRL_MUX8__0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_1\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q31_2\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_0\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_1\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_2\ : STD_LOGIC;
  signal \I_YESLUT6.SRL_Q_3\ : STD_LOGIC;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_A\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \I_YESLUT6.U_SRL32_A\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_B\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_B\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_C\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_C\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C ";
  attribute BOX_TYPE of \I_YESLUT6.U_SRL32_D\ : label is "PRIMITIVE";
  attribute srl_name of \I_YESLUT6.U_SRL32_D\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D ";
begin
  \I_YESLUT6.I_YES_OREG.O_reg_reg_0\(0) <= \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0);
\I_YESLUT6.I_YES_OREG.O_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_YESLUT6.I_YES_OREG.O_reg_reg_2\,
      CE => '1',
      D => \I_YESLUT6.SRL_MUX8__0\,
      Q => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      R => Q(0)
    );
\I_YESLUT6.SRL_MUX8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \I_YESLUT6.SRL_Q_3\,
      I1 => \I_YESLUT6.SRL_Q_2\,
      I2 => wcnt_hcmp,
      I3 => \I_YESLUT6.SRL_Q_1\,
      I4 => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(1),
      I5 => \I_YESLUT6.SRL_Q_0\,
      O => \I_YESLUT6.SRL_MUX8__0\
    );
\I_YESLUT6.U_SRL32_A\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 2) => A(2 downto 0),
      A(1) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      A(0) => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_2\,
      Q => \I_YESLUT6.SRL_Q_3\,
      Q31 => cfg_data_0
    );
\I_YESLUT6.U_SRL32_B\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 2) => A(2 downto 0),
      A(1) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      A(0) => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_1\,
      Q => \I_YESLUT6.SRL_Q_2\,
      Q31 => \I_YESLUT6.SRL_Q31_2\
    );
\I_YESLUT6.U_SRL32_C\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 2) => A(2 downto 0),
      A(1) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      A(0) => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => \I_YESLUT6.SRL_Q31_0\,
      Q => \I_YESLUT6.SRL_Q_1\,
      Q31 => \I_YESLUT6.SRL_Q31_1\
    );
\I_YESLUT6.U_SRL32_D\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 2) => A(2 downto 0),
      A(1) => \^i_yeslut6.i_yes_oreg.o_reg_reg_0\(0),
      A(0) => \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(0),
      CE => E(0),
      CLK => s_dclk_o,
      D => capture_ctrl_config_serial_output,
      Q => \I_YESLUT6.SRL_Q_0\,
      Q31 => \I_YESLUT6.SRL_Q31_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_generic_memrd is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \current_state_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \current_state_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \curr_read_block_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \current_state_reg[3]_0\ : out STD_LOGIC;
    \current_state_reg[4]_0\ : out STD_LOGIC;
    \curr_read_block_reg[3]_0\ : out STD_LOGIC;
    \curr_read_block_reg[3]_1\ : out STD_LOGIC;
    \curr_read_block_reg[2]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    \current_state_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    read_data_en : in STD_LOGIC;
    read_en_reg_0 : in STD_LOGIC;
    read_reset_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \current_state_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \input_data_reg[138]_0\ : in STD_LOGIC_VECTOR ( 138 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \curr_read_block_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_generic_memrd : entity is "ltlib_v1_0_0_generic_memrd";
end ila_full_aurora_ltlib_v1_0_0_generic_memrd;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_generic_memrd is
  signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal curr_read_block : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \curr_read_block[1]_i_1_n_0\ : STD_LOGIC;
  signal \curr_read_block[2]_i_1_n_0\ : STD_LOGIC;
  signal \curr_read_block[3]_i_2_n_0\ : STD_LOGIC;
  signal \curr_read_block[3]_i_3_n_0\ : STD_LOGIC;
  signal curr_read_block_0 : STD_LOGIC;
  signal \^curr_read_block_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal current_state : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \current_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \current_state[0]_i_3_n_0\ : STD_LOGIC;
  signal \current_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_2__7_n_0\ : STD_LOGIC;
  signal \current_state[4]_i_3_n_0\ : STD_LOGIC;
  signal \^current_state_reg[0]_0\ : STD_LOGIC;
  signal \^current_state_reg[5]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal data1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data3 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data4 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data5 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data6 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data7 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data8 : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal data_out_en : STD_LOGIC;
  signal data_out_en_i_1_n_0 : STD_LOGIC;
  signal \input_data_reg_n_0_[0]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[10]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[11]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[12]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[13]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[14]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[15]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[1]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[2]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[3]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[4]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[5]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[6]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[7]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[8]\ : STD_LOGIC;
  signal \input_data_reg_n_0_[9]\ : STD_LOGIC;
  signal \multiple_enable_latency.enable_out_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal \multiple_read_latency.read_enable_out_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal read_addr : STD_LOGIC;
  signal \read_addr[0]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[1]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[2]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[3]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[4]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[4]_i_2_n_0\ : STD_LOGIC;
  signal \read_addr[5]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[5]_i_2_n_0\ : STD_LOGIC;
  signal \read_addr[6]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[7]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[8]_i_1_n_0\ : STD_LOGIC;
  signal \read_addr[8]_i_2_n_0\ : STD_LOGIC;
  signal \read_addr[9]_i_2_n_0\ : STD_LOGIC;
  signal \read_addr[9]_i_3_n_0\ : STD_LOGIC;
  signal read_en : STD_LOGIC;
  signal read_en_1 : STD_LOGIC;
  signal read_en_i_1_n_0 : STD_LOGIC;
  signal read_en_i_4_n_0 : STD_LOGIC;
  signal read_en_i_7_n_0 : STD_LOGIC;
  signal read_en_temp : STD_LOGIC;
  signal \xsdb_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[10]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[11]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[12]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[12]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[13]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[13]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[14]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[14]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_3__1_n_0\ : STD_LOGIC;
  signal \xsdb_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[2]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[4]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[5]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[6]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[7]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[8]_i_3_n_0\ : STD_LOGIC;
  signal \xsdb_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[9]_i_3_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \curr_read_block[2]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \curr_read_block[3]_i_2\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \current_state[0]_i_2\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \current_state[0]_i_3\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \current_state[1]_i_1__6\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \current_state[3]_i_1__7\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \current_state[4]_i_3\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \current_state[5]_i_2\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \current_state[6]_i_3\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of data_out_en_i_1 : label is "soft_lutpair89";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \multiple_enable_latency.enable_out_reg[2]_srl2\ : label is "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg ";
  attribute srl_name : string;
  attribute srl_name of \multiple_enable_latency.enable_out_reg[2]_srl2\ : label is "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[2]_srl2 ";
  attribute srl_bus_name of \multiple_read_latency.read_enable_out_reg[2]_srl2\ : label is "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg ";
  attribute srl_name of \multiple_read_latency.read_enable_out_reg[2]_srl2\ : label is "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[2]_srl2 ";
  attribute SOFT_HLUTNM of \read_addr[0]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \read_addr[1]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \read_addr[4]_i_2\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \read_addr[5]_i_2\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \read_addr[7]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \read_addr[9]_i_3\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of read_en_i_1 : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of read_en_i_7 : label is "soft_lutpair86";
begin
  Q(9 downto 0) <= \^q\(9 downto 0);
  \curr_read_block_reg[0]_0\(0) <= \^curr_read_block_reg[0]_0\(0);
  \current_state_reg[0]_0\ <= \^current_state_reg[0]_0\;
  \current_state_reg[5]_0\(0) <= \^current_state_reg[5]_0\(0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => read_en_temp,
      O => D(0)
    );
\curr_read_block[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \current_state_reg[6]_0\(0),
      I1 => \^curr_read_block_reg[0]_0\(0),
      I2 => curr_read_block(1),
      O => \curr_read_block[1]_i_1_n_0\
    );
\curr_read_block[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => \current_state_reg[6]_0\(0),
      I1 => \^curr_read_block_reg[0]_0\(0),
      I2 => curr_read_block(1),
      I3 => curr_read_block(2),
      O => \curr_read_block[2]_i_1_n_0\
    );
\curr_read_block[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010100"
    )
        port map (
      I0 => \^current_state_reg[5]_0\(0),
      I1 => \curr_read_block[3]_i_3_n_0\,
      I2 => next_state(4),
      I3 => \current_state_reg[6]_0\(1),
      I4 => \current_state_reg[6]_0\(0),
      I5 => next_state(0),
      O => curr_read_block_0
    );
\curr_read_block[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \current_state_reg[6]_0\(0),
      I1 => curr_read_block(1),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(2),
      I4 => curr_read_block(3),
      O => \curr_read_block[3]_i_2_n_0\
    );
\curr_read_block[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => next_state(2),
      I1 => next_state(1),
      O => \curr_read_block[3]_i_3_n_0\
    );
\curr_read_block_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => curr_read_block_0,
      D => \curr_read_block_reg[0]_1\(0),
      Q => \^curr_read_block_reg[0]_0\(0),
      R => '0'
    );
\curr_read_block_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => curr_read_block_0,
      D => \curr_read_block[1]_i_1_n_0\,
      Q => curr_read_block(1),
      R => '0'
    );
\curr_read_block_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => curr_read_block_0,
      D => \curr_read_block[2]_i_1_n_0\,
      Q => curr_read_block(2),
      R => '0'
    );
\curr_read_block_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => curr_read_block_0,
      D => \curr_read_block[3]_i_2_n_0\,
      Q => curr_read_block(3),
      R => '0'
    );
\current_state[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFDFC03"
    )
        port map (
      I0 => read_data_en,
      I1 => current_state(2),
      I2 => \current_state[0]_i_2_n_0\,
      I3 => current_state(1),
      I4 => current_state(0),
      I5 => \current_state[0]_i_3_n_0\,
      O => next_state(0)
    );
\current_state[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(4),
      I2 => current_state(6),
      I3 => current_state(5),
      O => \current_state[0]_i_2_n_0\
    );
\current_state[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(4),
      I3 => current_state(6),
      I4 => current_state(5),
      O => \current_state[0]_i_3_n_0\
    );
\current_state[1]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2C00"
    )
        port map (
      I0 => read_data_en,
      I1 => current_state(6),
      I2 => current_state(0),
      I3 => \current_state[1]_i_2_n_0\,
      O => next_state(1)
    );
\current_state[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => current_state(5),
      I1 => current_state(4),
      I2 => current_state(3),
      I3 => current_state(2),
      I4 => current_state(1),
      O => \current_state[1]_i_2_n_0\
    );
\current_state[2]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100030000"
    )
        port map (
      I0 => \current_state_reg[2]_0\(0),
      I1 => \current_state[4]_i_3_n_0\,
      I2 => current_state(3),
      I3 => current_state(4),
      I4 => current_state(1),
      I5 => current_state(2),
      O => next_state(2)
    );
\current_state[3]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2088"
    )
        port map (
      I0 => \current_state[3]_i_2__7_n_0\,
      I1 => current_state(5),
      I2 => \current_state_reg[2]_0\(0),
      I3 => current_state(2),
      O => \^current_state_reg[5]_0\(0)
    );
\current_state[3]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(6),
      I3 => current_state(3),
      I4 => current_state(4),
      O => \current_state[3]_i_2__7_n_0\
    );
\current_state[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100030000"
    )
        port map (
      I0 => read_data_en,
      I1 => \current_state[4]_i_3_n_0\,
      I2 => current_state(2),
      I3 => current_state(1),
      I4 => current_state(3),
      I5 => current_state(4),
      O => next_state(4)
    );
\current_state[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => current_state(6),
      I1 => current_state(5),
      I2 => current_state(0),
      O => \current_state[4]_i_3_n_0\
    );
\current_state[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => curr_read_block(3),
      I1 => current_state(4),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \curr_read_block_reg[3]_0\
    );
\current_state[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(5),
      I2 => current_state(6),
      I3 => current_state(1),
      O => \^current_state_reg[0]_0\
    );
\current_state[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => curr_read_block(3),
      I1 => current_state(4),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \curr_read_block_reg[3]_1\
    );
\current_state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      S => SR(0)
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => SR(0)
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => SR(0)
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \^current_state_reg[5]_0\(0),
      Q => current_state(3),
      R => SR(0)
    );
\current_state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(4),
      Q => current_state(4),
      R => SR(0)
    );
\current_state_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \current_state_reg[6]_0\(0),
      Q => current_state(5),
      R => SR(0)
    );
\current_state_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \current_state_reg[6]_0\(1),
      Q => current_state(6),
      R => SR(0)
    );
data_out_en_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^current_state_reg[5]_0\(0),
      I1 => read_en_1,
      I2 => data_out_en,
      O => data_out_en_i_1_n_0
    );
data_out_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => data_out_en_i_1_n_0,
      Q => data_out_en,
      R => '0'
    );
\input_data_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(0),
      Q => \input_data_reg_n_0_[0]\,
      R => '0'
    );
\input_data_reg[100]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(100),
      Q => data6(4),
      R => '0'
    );
\input_data_reg[101]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(101),
      Q => data6(5),
      R => '0'
    );
\input_data_reg[102]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(102),
      Q => data6(6),
      R => '0'
    );
\input_data_reg[103]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(103),
      Q => data6(7),
      R => '0'
    );
\input_data_reg[104]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(104),
      Q => data6(8),
      R => '0'
    );
\input_data_reg[105]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(105),
      Q => data6(9),
      R => '0'
    );
\input_data_reg[106]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(106),
      Q => data6(10),
      R => '0'
    );
\input_data_reg[107]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(107),
      Q => data6(11),
      R => '0'
    );
\input_data_reg[108]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(108),
      Q => data6(12),
      R => '0'
    );
\input_data_reg[109]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(109),
      Q => data6(13),
      R => '0'
    );
\input_data_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(10),
      Q => \input_data_reg_n_0_[10]\,
      R => '0'
    );
\input_data_reg[110]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(110),
      Q => data6(14),
      R => '0'
    );
\input_data_reg[111]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(111),
      Q => data6(15),
      R => '0'
    );
\input_data_reg[112]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(112),
      Q => data7(0),
      R => '0'
    );
\input_data_reg[113]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(113),
      Q => data7(1),
      R => '0'
    );
\input_data_reg[114]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(114),
      Q => data7(2),
      R => '0'
    );
\input_data_reg[115]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(115),
      Q => data7(3),
      R => '0'
    );
\input_data_reg[116]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(116),
      Q => data7(4),
      R => '0'
    );
\input_data_reg[117]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(117),
      Q => data7(5),
      R => '0'
    );
\input_data_reg[118]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(118),
      Q => data7(6),
      R => '0'
    );
\input_data_reg[119]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(119),
      Q => data7(7),
      R => '0'
    );
\input_data_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(11),
      Q => \input_data_reg_n_0_[11]\,
      R => '0'
    );
\input_data_reg[120]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(120),
      Q => data7(8),
      R => '0'
    );
\input_data_reg[121]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(121),
      Q => data7(9),
      R => '0'
    );
\input_data_reg[122]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(122),
      Q => data7(10),
      R => '0'
    );
\input_data_reg[123]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(123),
      Q => data7(11),
      R => '0'
    );
\input_data_reg[124]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(124),
      Q => data7(12),
      R => '0'
    );
\input_data_reg[125]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(125),
      Q => data7(13),
      R => '0'
    );
\input_data_reg[126]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(126),
      Q => data7(14),
      R => '0'
    );
\input_data_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(127),
      Q => data7(15),
      R => '0'
    );
\input_data_reg[128]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(128),
      Q => data8(0),
      R => '0'
    );
\input_data_reg[129]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(129),
      Q => data8(1),
      R => '0'
    );
\input_data_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(12),
      Q => \input_data_reg_n_0_[12]\,
      R => '0'
    );
\input_data_reg[130]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(130),
      Q => data8(2),
      R => '0'
    );
\input_data_reg[131]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(131),
      Q => data8(3),
      R => '0'
    );
\input_data_reg[132]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(132),
      Q => data8(4),
      R => '0'
    );
\input_data_reg[133]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(133),
      Q => data8(5),
      R => '0'
    );
\input_data_reg[134]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(134),
      Q => data8(6),
      R => '0'
    );
\input_data_reg[135]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(135),
      Q => data8(7),
      R => '0'
    );
\input_data_reg[136]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(136),
      Q => data8(8),
      R => '0'
    );
\input_data_reg[137]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(137),
      Q => data8(9),
      R => '0'
    );
\input_data_reg[138]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(138),
      Q => data8(10),
      R => '0'
    );
\input_data_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(13),
      Q => \input_data_reg_n_0_[13]\,
      R => '0'
    );
\input_data_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(14),
      Q => \input_data_reg_n_0_[14]\,
      R => '0'
    );
\input_data_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(15),
      Q => \input_data_reg_n_0_[15]\,
      R => '0'
    );
\input_data_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(16),
      Q => data1(0),
      R => '0'
    );
\input_data_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(17),
      Q => data1(1),
      R => '0'
    );
\input_data_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(18),
      Q => data1(2),
      R => '0'
    );
\input_data_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(19),
      Q => data1(3),
      R => '0'
    );
\input_data_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(1),
      Q => \input_data_reg_n_0_[1]\,
      R => '0'
    );
\input_data_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(20),
      Q => data1(4),
      R => '0'
    );
\input_data_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(21),
      Q => data1(5),
      R => '0'
    );
\input_data_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(22),
      Q => data1(6),
      R => '0'
    );
\input_data_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(23),
      Q => data1(7),
      R => '0'
    );
\input_data_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(24),
      Q => data1(8),
      R => '0'
    );
\input_data_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(25),
      Q => data1(9),
      R => '0'
    );
\input_data_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(26),
      Q => data1(10),
      R => '0'
    );
\input_data_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(27),
      Q => data1(11),
      R => '0'
    );
\input_data_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(28),
      Q => data1(12),
      R => '0'
    );
\input_data_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(29),
      Q => data1(13),
      R => '0'
    );
\input_data_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(2),
      Q => \input_data_reg_n_0_[2]\,
      R => '0'
    );
\input_data_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(30),
      Q => data1(14),
      R => '0'
    );
\input_data_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(31),
      Q => data1(15),
      R => '0'
    );
\input_data_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(32),
      Q => data2(0),
      R => '0'
    );
\input_data_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(33),
      Q => data2(1),
      R => '0'
    );
\input_data_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(34),
      Q => data2(2),
      R => '0'
    );
\input_data_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(35),
      Q => data2(3),
      R => '0'
    );
\input_data_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(36),
      Q => data2(4),
      R => '0'
    );
\input_data_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(37),
      Q => data2(5),
      R => '0'
    );
\input_data_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(38),
      Q => data2(6),
      R => '0'
    );
\input_data_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(39),
      Q => data2(7),
      R => '0'
    );
\input_data_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(3),
      Q => \input_data_reg_n_0_[3]\,
      R => '0'
    );
\input_data_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(40),
      Q => data2(8),
      R => '0'
    );
\input_data_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(41),
      Q => data2(9),
      R => '0'
    );
\input_data_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(42),
      Q => data2(10),
      R => '0'
    );
\input_data_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(43),
      Q => data2(11),
      R => '0'
    );
\input_data_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(44),
      Q => data2(12),
      R => '0'
    );
\input_data_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(45),
      Q => data2(13),
      R => '0'
    );
\input_data_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(46),
      Q => data2(14),
      R => '0'
    );
\input_data_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(47),
      Q => data2(15),
      R => '0'
    );
\input_data_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(48),
      Q => data3(0),
      R => '0'
    );
\input_data_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(49),
      Q => data3(1),
      R => '0'
    );
\input_data_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(4),
      Q => \input_data_reg_n_0_[4]\,
      R => '0'
    );
\input_data_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(50),
      Q => data3(2),
      R => '0'
    );
\input_data_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(51),
      Q => data3(3),
      R => '0'
    );
\input_data_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(52),
      Q => data3(4),
      R => '0'
    );
\input_data_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(53),
      Q => data3(5),
      R => '0'
    );
\input_data_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(54),
      Q => data3(6),
      R => '0'
    );
\input_data_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(55),
      Q => data3(7),
      R => '0'
    );
\input_data_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(56),
      Q => data3(8),
      R => '0'
    );
\input_data_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(57),
      Q => data3(9),
      R => '0'
    );
\input_data_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(58),
      Q => data3(10),
      R => '0'
    );
\input_data_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(59),
      Q => data3(11),
      R => '0'
    );
\input_data_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(5),
      Q => \input_data_reg_n_0_[5]\,
      R => '0'
    );
\input_data_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(60),
      Q => data3(12),
      R => '0'
    );
\input_data_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(61),
      Q => data3(13),
      R => '0'
    );
\input_data_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(62),
      Q => data3(14),
      R => '0'
    );
\input_data_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(63),
      Q => data3(15),
      R => '0'
    );
\input_data_reg[64]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(64),
      Q => data4(0),
      R => '0'
    );
\input_data_reg[65]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(65),
      Q => data4(1),
      R => '0'
    );
\input_data_reg[66]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(66),
      Q => data4(2),
      R => '0'
    );
\input_data_reg[67]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(67),
      Q => data4(3),
      R => '0'
    );
\input_data_reg[68]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(68),
      Q => data4(4),
      R => '0'
    );
\input_data_reg[69]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(69),
      Q => data4(5),
      R => '0'
    );
\input_data_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(6),
      Q => \input_data_reg_n_0_[6]\,
      R => '0'
    );
\input_data_reg[70]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(70),
      Q => data4(6),
      R => '0'
    );
\input_data_reg[71]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(71),
      Q => data4(7),
      R => '0'
    );
\input_data_reg[72]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(72),
      Q => data4(8),
      R => '0'
    );
\input_data_reg[73]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(73),
      Q => data4(9),
      R => '0'
    );
\input_data_reg[74]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(74),
      Q => data4(10),
      R => '0'
    );
\input_data_reg[75]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(75),
      Q => data4(11),
      R => '0'
    );
\input_data_reg[76]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(76),
      Q => data4(12),
      R => '0'
    );
\input_data_reg[77]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(77),
      Q => data4(13),
      R => '0'
    );
\input_data_reg[78]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(78),
      Q => data4(14),
      R => '0'
    );
\input_data_reg[79]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(79),
      Q => data4(15),
      R => '0'
    );
\input_data_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(7),
      Q => \input_data_reg_n_0_[7]\,
      R => '0'
    );
\input_data_reg[80]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(80),
      Q => data5(0),
      R => '0'
    );
\input_data_reg[81]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(81),
      Q => data5(1),
      R => '0'
    );
\input_data_reg[82]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(82),
      Q => data5(2),
      R => '0'
    );
\input_data_reg[83]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(83),
      Q => data5(3),
      R => '0'
    );
\input_data_reg[84]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(84),
      Q => data5(4),
      R => '0'
    );
\input_data_reg[85]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(85),
      Q => data5(5),
      R => '0'
    );
\input_data_reg[86]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(86),
      Q => data5(6),
      R => '0'
    );
\input_data_reg[87]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(87),
      Q => data5(7),
      R => '0'
    );
\input_data_reg[88]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(88),
      Q => data5(8),
      R => '0'
    );
\input_data_reg[89]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(89),
      Q => data5(9),
      R => '0'
    );
\input_data_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(8),
      Q => \input_data_reg_n_0_[8]\,
      R => '0'
    );
\input_data_reg[90]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(90),
      Q => data5(10),
      R => '0'
    );
\input_data_reg[91]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(91),
      Q => data5(11),
      R => '0'
    );
\input_data_reg[92]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(92),
      Q => data5(12),
      R => '0'
    );
\input_data_reg[93]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(93),
      Q => data5(13),
      R => '0'
    );
\input_data_reg[94]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(94),
      Q => data5(14),
      R => '0'
    );
\input_data_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(95),
      Q => data5(15),
      R => '0'
    );
\input_data_reg[96]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(96),
      Q => data6(0),
      R => '0'
    );
\input_data_reg[97]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(97),
      Q => data6(1),
      R => '0'
    );
\input_data_reg[98]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(98),
      Q => data6(2),
      R => '0'
    );
\input_data_reg[99]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(99),
      Q => data6(3),
      R => '0'
    );
\input_data_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \input_data_reg[138]_0\(9),
      Q => \input_data_reg_n_0_[9]\,
      R => '0'
    );
\multiple_enable_latency.enable_out_reg[2]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => s_dclk_o,
      D => data_out_en,
      Q => \multiple_enable_latency.enable_out_reg[2]_srl2_n_0\
    );
\multiple_enable_latency.enable_out_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \multiple_enable_latency.enable_out_reg[2]_srl2_n_0\,
      Q => E(0),
      R => '0'
    );
\multiple_read_latency.read_en_temp_reg\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => p_0_in,
      Q => read_en_temp,
      R => '0'
    );
\multiple_read_latency.read_enable_out_reg[2]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => s_dclk_o,
      D => read_en,
      Q => \multiple_read_latency.read_enable_out_reg[2]_srl2_n_0\
    );
\multiple_read_latency.read_enable_out_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \multiple_read_latency.read_enable_out_reg[2]_srl2_n_0\,
      Q => p_0_in,
      R => '0'
    );
\read_addr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => read_reset_addr(0),
      I1 => next_state(0),
      I2 => \^q\(0),
      O => \read_addr[0]_i_1_n_0\
    );
\read_addr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F606"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => next_state(0),
      I3 => read_reset_addr(1),
      O => \read_addr[1]_i_1_n_0\
    );
\read_addr[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6A006A"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => next_state(0),
      I4 => read_reset_addr(2),
      O => \read_addr[2]_i_1_n_0\
    );
\read_addr[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6AAA00006AAA"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => next_state(0),
      I5 => read_reset_addr(3),
      O => \read_addr[3]_i_1_n_0\
    );
\read_addr[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F606"
    )
        port map (
      I0 => \^q\(4),
      I1 => \read_addr[4]_i_2_n_0\,
      I2 => next_state(0),
      I3 => read_reset_addr(4),
      O => \read_addr[4]_i_1_n_0\
    );
\read_addr[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => \read_addr[4]_i_2_n_0\
    );
\read_addr[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F606"
    )
        port map (
      I0 => \^q\(5),
      I1 => \read_addr[5]_i_2_n_0\,
      I2 => next_state(0),
      I3 => read_reset_addr(5),
      O => \read_addr[5]_i_1_n_0\
    );
\read_addr[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \read_addr[5]_i_2_n_0\
    );
\read_addr[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F606"
    )
        port map (
      I0 => \^q\(6),
      I1 => \read_addr[8]_i_2_n_0\,
      I2 => next_state(0),
      I3 => read_reset_addr(6),
      O => \read_addr[6]_i_1_n_0\
    );
\read_addr[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6A006A"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(6),
      I2 => \read_addr[8]_i_2_n_0\,
      I3 => next_state(0),
      I4 => read_reset_addr(7),
      O => \read_addr[7]_i_1_n_0\
    );
\read_addr[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF6AAA00006AAA"
    )
        port map (
      I0 => \^q\(8),
      I1 => \^q\(7),
      I2 => \read_addr[8]_i_2_n_0\,
      I3 => \^q\(6),
      I4 => next_state(0),
      I5 => read_reset_addr(8),
      O => \read_addr[8]_i_1_n_0\
    );
\read_addr[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(4),
      O => \read_addr[8]_i_2_n_0\
    );
\read_addr[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010000"
    )
        port map (
      I0 => \current_state_reg[6]_0\(0),
      I1 => next_state(4),
      I2 => \curr_read_block[3]_i_3_n_0\,
      I3 => \^current_state_reg[5]_0\(0),
      I4 => next_state(0),
      I5 => \current_state_reg[6]_0\(1),
      O => read_addr
    );
\read_addr[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF6A006A"
    )
        port map (
      I0 => \^q\(9),
      I1 => \^q\(8),
      I2 => \read_addr[9]_i_3_n_0\,
      I3 => next_state(0),
      I4 => read_reset_addr(9),
      O => \read_addr[9]_i_2_n_0\
    );
\read_addr[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^q\(7),
      I1 => \read_addr[8]_i_2_n_0\,
      I2 => \^q\(6),
      O => \read_addr[9]_i_3_n_0\
    );
\read_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[0]_i_1_n_0\,
      Q => \^q\(0),
      R => '0'
    );
\read_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[1]_i_1_n_0\,
      Q => \^q\(1),
      R => '0'
    );
\read_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[2]_i_1_n_0\,
      Q => \^q\(2),
      R => '0'
    );
\read_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[3]_i_1_n_0\,
      Q => \^q\(3),
      R => '0'
    );
\read_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[4]_i_1_n_0\,
      Q => \^q\(4),
      R => '0'
    );
\read_addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[5]_i_1_n_0\,
      Q => \^q\(5),
      R => '0'
    );
\read_addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[6]_i_1_n_0\,
      Q => \^q\(6),
      R => '0'
    );
\read_addr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[7]_i_1_n_0\,
      Q => \^q\(7),
      R => '0'
    );
\read_addr_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[8]_i_1_n_0\,
      Q => \^q\(8),
      R => '0'
    );
\read_addr_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => read_addr,
      D => \read_addr[9]_i_2_n_0\,
      Q => \^q\(9),
      R => '0'
    );
read_en_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => next_state(1),
      I1 => read_en_1,
      I2 => read_en,
      O => read_en_i_1_n_0
    );
read_en_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000030003002E22"
    )
        port map (
      I0 => read_en_reg_0,
      I1 => next_state(0),
      I2 => next_state(4),
      I3 => read_en_i_4_n_0,
      I4 => next_state(1),
      I5 => next_state(2),
      O => read_en_1
    );
read_en_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFFFFFF"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => \^current_state_reg[0]_0\,
      I3 => current_state(4),
      I4 => read_data_en,
      I5 => \^current_state_reg[5]_0\(0),
      O => read_en_i_4_n_0
    );
read_en_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(4),
      I2 => current_state(1),
      I3 => current_state(2),
      I4 => read_en_i_7_n_0,
      I5 => current_state(0),
      O => \current_state_reg[3]_0\
    );
read_en_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => current_state(4),
      I1 => current_state(3),
      I2 => current_state(1),
      I3 => current_state(2),
      I4 => read_en_i_7_n_0,
      I5 => current_state(0),
      O => \current_state_reg[4]_0\
    );
read_en_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => current_state(5),
      I1 => current_state(6),
      O => read_en_i_7_n_0
    );
read_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => read_en_i_1_n_0,
      Q => read_en,
      R => '0'
    );
\xsdb_reg[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[0]_i_2_n_0\,
      I2 => \xsdb_reg[0]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(0),
      O => \curr_read_block_reg[2]_0\(0)
    );
\xsdb_reg[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(0),
      I1 => data3(0),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[0]\,
      I5 => data2(0),
      O => \xsdb_reg[0]_i_2_n_0\
    );
\xsdb_reg[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(0),
      I1 => data7(0),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(0),
      I5 => data6(0),
      O => \xsdb_reg[0]_i_3_n_0\
    );
\xsdb_reg[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[10]_i_2_n_0\,
      I2 => \xsdb_reg[10]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(10),
      O => \curr_read_block_reg[2]_0\(10)
    );
\xsdb_reg[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(10),
      I1 => data3(10),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[10]\,
      I5 => data2(10),
      O => \xsdb_reg[10]_i_2_n_0\
    );
\xsdb_reg[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(10),
      I1 => data7(10),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(10),
      I5 => data6(10),
      O => \xsdb_reg[10]_i_3_n_0\
    );
\xsdb_reg[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \xsdb_reg[11]_i_2_n_0\,
      I1 => \xsdb_reg[11]_i_3_n_0\,
      I2 => curr_read_block(2),
      I3 => curr_read_block(3),
      O => \curr_read_block_reg[2]_0\(11)
    );
\xsdb_reg[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(11),
      I1 => data7(11),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(11),
      I5 => data6(11),
      O => \xsdb_reg[11]_i_2_n_0\
    );
\xsdb_reg[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(11),
      I1 => data3(11),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[11]\,
      I5 => data2(11),
      O => \xsdb_reg[11]_i_3_n_0\
    );
\xsdb_reg[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \xsdb_reg[12]_i_2_n_0\,
      I1 => \xsdb_reg[12]_i_3_n_0\,
      I2 => curr_read_block(2),
      I3 => curr_read_block(3),
      O => \curr_read_block_reg[2]_0\(12)
    );
\xsdb_reg[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(12),
      I1 => data7(12),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(12),
      I5 => data6(12),
      O => \xsdb_reg[12]_i_2_n_0\
    );
\xsdb_reg[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(12),
      I1 => data3(12),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[12]\,
      I5 => data2(12),
      O => \xsdb_reg[12]_i_3_n_0\
    );
\xsdb_reg[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \xsdb_reg[13]_i_2_n_0\,
      I1 => \xsdb_reg[13]_i_3_n_0\,
      I2 => curr_read_block(2),
      I3 => curr_read_block(3),
      O => \curr_read_block_reg[2]_0\(13)
    );
\xsdb_reg[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(13),
      I1 => data7(13),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(13),
      I5 => data6(13),
      O => \xsdb_reg[13]_i_2_n_0\
    );
\xsdb_reg[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(13),
      I1 => data3(13),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[13]\,
      I5 => data2(13),
      O => \xsdb_reg[13]_i_3_n_0\
    );
\xsdb_reg[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \xsdb_reg[14]_i_2_n_0\,
      I1 => \xsdb_reg[14]_i_3_n_0\,
      I2 => curr_read_block(2),
      I3 => curr_read_block(3),
      O => \curr_read_block_reg[2]_0\(14)
    );
\xsdb_reg[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(14),
      I1 => data7(14),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(14),
      I5 => data6(14),
      O => \xsdb_reg[14]_i_2_n_0\
    );
\xsdb_reg[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(14),
      I1 => data3(14),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[14]\,
      I5 => data2(14),
      O => \xsdb_reg[14]_i_3_n_0\
    );
\xsdb_reg[15]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => \xsdb_reg[15]_i_2__2_n_0\,
      I1 => \xsdb_reg[15]_i_3__1_n_0\,
      I2 => curr_read_block(2),
      I3 => curr_read_block(3),
      O => \curr_read_block_reg[2]_0\(15)
    );
\xsdb_reg[15]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(15),
      I1 => data7(15),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(15),
      I5 => data6(15),
      O => \xsdb_reg[15]_i_2__2_n_0\
    );
\xsdb_reg[15]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(15),
      I1 => data3(15),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[15]\,
      I5 => data2(15),
      O => \xsdb_reg[15]_i_3__1_n_0\
    );
\xsdb_reg[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[1]_i_2_n_0\,
      I2 => \xsdb_reg[1]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(1),
      O => \curr_read_block_reg[2]_0\(1)
    );
\xsdb_reg[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(1),
      I1 => data3(1),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[1]\,
      I5 => data2(1),
      O => \xsdb_reg[1]_i_2_n_0\
    );
\xsdb_reg[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(1),
      I1 => data7(1),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(1),
      I5 => data6(1),
      O => \xsdb_reg[1]_i_3_n_0\
    );
\xsdb_reg[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[2]_i_2_n_0\,
      I2 => \xsdb_reg[2]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(2),
      O => \curr_read_block_reg[2]_0\(2)
    );
\xsdb_reg[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(2),
      I1 => data3(2),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[2]\,
      I5 => data2(2),
      O => \xsdb_reg[2]_i_2_n_0\
    );
\xsdb_reg[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(2),
      I1 => data7(2),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(2),
      I5 => data6(2),
      O => \xsdb_reg[2]_i_3_n_0\
    );
\xsdb_reg[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[3]_i_2_n_0\,
      I2 => \xsdb_reg[3]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(3),
      O => \curr_read_block_reg[2]_0\(3)
    );
\xsdb_reg[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(3),
      I1 => data3(3),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[3]\,
      I5 => data2(3),
      O => \xsdb_reg[3]_i_2_n_0\
    );
\xsdb_reg[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(3),
      I1 => data7(3),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(3),
      I5 => data6(3),
      O => \xsdb_reg[3]_i_3_n_0\
    );
\xsdb_reg[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[4]_i_2_n_0\,
      I2 => \xsdb_reg[4]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(4),
      O => \curr_read_block_reg[2]_0\(4)
    );
\xsdb_reg[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(4),
      I1 => data3(4),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[4]\,
      I5 => data2(4),
      O => \xsdb_reg[4]_i_2_n_0\
    );
\xsdb_reg[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(4),
      I1 => data7(4),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(4),
      I5 => data6(4),
      O => \xsdb_reg[4]_i_3_n_0\
    );
\xsdb_reg[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[5]_i_2_n_0\,
      I2 => \xsdb_reg[5]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(5),
      O => \curr_read_block_reg[2]_0\(5)
    );
\xsdb_reg[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(5),
      I1 => data3(5),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[5]\,
      I5 => data2(5),
      O => \xsdb_reg[5]_i_2_n_0\
    );
\xsdb_reg[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(5),
      I1 => data7(5),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(5),
      I5 => data6(5),
      O => \xsdb_reg[5]_i_3_n_0\
    );
\xsdb_reg[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[6]_i_2_n_0\,
      I2 => \xsdb_reg[6]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(6),
      O => \curr_read_block_reg[2]_0\(6)
    );
\xsdb_reg[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(6),
      I1 => data3(6),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[6]\,
      I5 => data2(6),
      O => \xsdb_reg[6]_i_2_n_0\
    );
\xsdb_reg[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(6),
      I1 => data7(6),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(6),
      I5 => data6(6),
      O => \xsdb_reg[6]_i_3_n_0\
    );
\xsdb_reg[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[7]_i_2_n_0\,
      I2 => \xsdb_reg[7]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(7),
      O => \curr_read_block_reg[2]_0\(7)
    );
\xsdb_reg[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(7),
      I1 => data3(7),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[7]\,
      I5 => data2(7),
      O => \xsdb_reg[7]_i_2_n_0\
    );
\xsdb_reg[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(7),
      I1 => data7(7),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(7),
      I5 => data6(7),
      O => \xsdb_reg[7]_i_3_n_0\
    );
\xsdb_reg[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[8]_i_2_n_0\,
      I2 => \xsdb_reg[8]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(8),
      O => \curr_read_block_reg[2]_0\(8)
    );
\xsdb_reg[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(8),
      I1 => data3(8),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[8]\,
      I5 => data2(8),
      O => \xsdb_reg[8]_i_2_n_0\
    );
\xsdb_reg[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(8),
      I1 => data7(8),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(8),
      I5 => data6(8),
      O => \xsdb_reg[8]_i_3_n_0\
    );
\xsdb_reg[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE400E4"
    )
        port map (
      I0 => curr_read_block(2),
      I1 => \xsdb_reg[9]_i_2_n_0\,
      I2 => \xsdb_reg[9]_i_3_n_0\,
      I3 => curr_read_block(3),
      I4 => data8(9),
      O => \curr_read_block_reg[2]_0\(9)
    );
\xsdb_reg[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data1(9),
      I1 => data3(9),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => \input_data_reg_n_0_[9]\,
      I5 => data2(9),
      O => \xsdb_reg[9]_i_2_n_0\
    );
\xsdb_reg[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => data5(9),
      I1 => data7(9),
      I2 => \^curr_read_block_reg[0]_0\(0),
      I3 => curr_read_block(1),
      I4 => data4(9),
      I5 => data6(9),
      O => \xsdb_reg[9]_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_rising_edge_detection is
  port (
    last_din : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dout_pulse_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    last_din_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dout_pulse_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_rising_edge_detection : entity is "ltlib_v1_0_0_rising_edge_detection";
end ila_full_aurora_ltlib_v1_0_0_rising_edge_detection;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_rising_edge_detection is
  signal \dout_pulse[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^dout_pulse_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^last_din\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
begin
  \dout_pulse_reg[1]_0\(0) <= \^dout_pulse_reg[1]_0\(0);
  last_din <= \^last_din\;
\dout_pulse[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \^last_din\,
      I1 => \out\,
      I2 => p_0_in(1),
      O => \dout_pulse[1]_i_1__0_n_0\
    );
\dout_pulse_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => \dout_pulse_reg[0]_0\(0),
      Q => p_0_in(1),
      R => '0'
    );
\dout_pulse_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => \dout_pulse[1]_i_1__0_n_0\,
      Q => \^dout_pulse_reg[1]_0\(0),
      R => '0'
    );
last_din_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => \out\,
      Q => \^last_din\,
      R => '0'
    );
\reset_out[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Q(0),
      I1 => \^dout_pulse_reg[1]_0\(0),
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_rising_edge_detection_29 is
  port (
    last_din : out STD_LOGIC;
    halt_out_reg : out STD_LOGIC;
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    last_din_reg_0 : in STD_LOGIC;
    halt_out : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    halt_out_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    prev_cap_done : in STD_LOGIC;
    \reset_out_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_rising_edge_detection_29 : entity is "ltlib_v1_0_0_rising_edge_detection";
end ila_full_aurora_ltlib_v1_0_0_rising_edge_detection_29;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_rising_edge_detection_29 is
  signal \dout_pulse[1]_i_1_n_0\ : STD_LOGIC;
  signal halt_in_detection : STD_LOGIC;
  signal \^last_din\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
begin
  last_din <= \^last_din\;
\dout_pulse[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \^last_din\,
      I1 => \out\,
      I2 => p_0_in(1),
      O => \dout_pulse[1]_i_1_n_0\
    );
\dout_pulse_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => D(0),
      Q => p_0_in(1),
      R => '0'
    );
\dout_pulse_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => \dout_pulse[1]_i_1_n_0\,
      Q => halt_in_detection,
      R => '0'
    );
halt_out_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => halt_out,
      I1 => halt_in_detection,
      I2 => Q(0),
      I3 => halt_out_reg_0(0),
      O => halt_out_reg
    );
last_din_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg_0,
      CE => '1',
      D => \out\,
      Q => \^last_din\,
      R => '0'
    );
\reset_out[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => halt_in_detection,
      I1 => prev_cap_done,
      I2 => \reset_out_reg[0]\(0),
      O => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl is
  port (
    \slaveRegDo_ffa_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_ffa_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_1\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_den_o : in STD_LOGIC;
    slaveRegDo_ffa : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \slaveRegDo_mux_3_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[5]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl is
  signal \xsdb_reg[15]_i_1__13_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_5_n_0\ : STD_LOGIC;
  signal \^xsdb_reg_reg[15]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
  \xsdb_reg_reg[15]_0\(15 downto 0) <= \^xsdb_reg_reg[15]_0\(15 downto 0);
\slaveRegDo_mux_3[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F000CCAA"
    )
        port map (
      I0 => slaveRegDo_ffa(0),
      I1 => \^xsdb_reg_reg[15]_0\(0),
      I2 => Q(0),
      I3 => \slaveRegDo_mux_3_reg[5]\,
      I4 => \slaveRegDo_mux_3_reg[5]_0\,
      O => \slaveRegDo_ffa_reg[5]\
    );
\slaveRegDo_mux_3[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[15]\,
      I1 => \^xsdb_reg_reg[15]_0\(10),
      I2 => \slaveRegDo_mux_3_reg[15]_0\,
      I3 => Q(3),
      I4 => \slaveRegDo_mux_3_reg[10]\,
      O => \xsdb_reg_reg[10]_0\
    );
\slaveRegDo_mux_3[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[15]\,
      I1 => \^xsdb_reg_reg[15]_0\(15),
      I2 => \slaveRegDo_mux_3_reg[15]_0\,
      I3 => Q(4),
      I4 => \slaveRegDo_mux_3_reg[15]_1\,
      O => \xsdb_reg_reg[15]_1\
    );
\slaveRegDo_mux_3[5]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F000CCAA"
    )
        port map (
      I0 => slaveRegDo_ffa(0),
      I1 => \^xsdb_reg_reg[15]_0\(5),
      I2 => Q(1),
      I3 => \slaveRegDo_mux_3_reg[5]\,
      I4 => \slaveRegDo_mux_3_reg[5]_0\,
      O => \slaveRegDo_ffa_reg[5]_0\
    );
\slaveRegDo_mux_3[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[15]\,
      I1 => \^xsdb_reg_reg[15]_0\(7),
      I2 => \slaveRegDo_mux_3_reg[15]_0\,
      I3 => Q(2),
      I4 => \slaveRegDo_mux_3_reg[7]\,
      O => \xsdb_reg_reg[7]_0\
    );
\xsdb_reg[15]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F00000000000000"
    )
        port map (
      I0 => s_daddr_o(1),
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(2),
      I3 => \xsdb_reg[15]_i_2__1_n_0\,
      I4 => \xsdb_reg_reg[0]_0\,
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__13_n_0\
    );
\xsdb_reg[15]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => s_daddr_o(2),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(4),
      I4 => s_daddr_o(5),
      I5 => \xsdb_reg[15]_i_5_n_0\,
      O => \xsdb_reg[15]_i_2__1_n_0\
    );
\xsdb_reg[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => s_dwe_o,
      I1 => s_den_o,
      O => \xsdb_reg[15]_i_5_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(0),
      Q => \^xsdb_reg_reg[15]_0\(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(10),
      Q => \^xsdb_reg_reg[15]_0\(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(11),
      Q => \^xsdb_reg_reg[15]_0\(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(12),
      Q => \^xsdb_reg_reg[15]_0\(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(13),
      Q => \^xsdb_reg_reg[15]_0\(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(14),
      Q => \^xsdb_reg_reg[15]_0\(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(15),
      Q => \^xsdb_reg_reg[15]_0\(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(1),
      Q => \^xsdb_reg_reg[15]_0\(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(2),
      Q => \^xsdb_reg_reg[15]_0\(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(3),
      Q => \^xsdb_reg_reg[15]_0\(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(4),
      Q => \^xsdb_reg_reg[15]_0\(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(5),
      Q => \^xsdb_reg_reg[15]_0\(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(6),
      Q => \^xsdb_reg_reg[15]_0\(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(7),
      Q => \^xsdb_reg_reg[15]_0\(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(8),
      Q => \^xsdb_reg_reg[15]_0\(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__13_n_0\,
      D => s_di_o(9),
      Q => \^xsdb_reg_reg[15]_0\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_33 is
  port (
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_33 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_33;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_33 is
  signal \xsdb_reg[15]_i_1_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[3]_0\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[4]_0\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[5]_0\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg[6]_0\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[7]_0\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[8]_0\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[9]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_34 is
  port (
    slaveRegDo_84 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_34 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_34;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_34 is
  signal \xsdb_reg[15]_i_1__0_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__0_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(0),
      Q => slaveRegDo_84(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(10),
      Q => slaveRegDo_84(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(11),
      Q => slaveRegDo_84(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(12),
      Q => slaveRegDo_84(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(13),
      Q => slaveRegDo_84(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(14),
      Q => slaveRegDo_84(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(15),
      Q => slaveRegDo_84(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(1),
      Q => slaveRegDo_84(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(2),
      Q => slaveRegDo_84(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(3),
      Q => slaveRegDo_84(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(4),
      Q => slaveRegDo_84(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(5),
      Q => slaveRegDo_84(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(6),
      Q => slaveRegDo_84(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(7),
      Q => slaveRegDo_84(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(8),
      Q => slaveRegDo_84(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__0_n_0\,
      D => s_di_o(9),
      Q => slaveRegDo_84(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_35 is
  port (
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_35 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_35;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_35 is
  signal \xsdb_reg[15]_i_1__1_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__1_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[3]_0\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[4]_0\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[5]_0\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg[6]_0\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[7]_0\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[8]_0\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__1_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[9]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_36 is
  port (
    D : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_3\ : in STD_LOGIC;
    slaveRegDo_84 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_0_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0[15]_i_2_0\ : in STD_LOGIC;
    slaveRegDo_80 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    slaveRegDo_82 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_0[14]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[13]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[12]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[11]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[10]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[9]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[8]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[7]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[4]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_3_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_36 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_36;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_36 is
  signal slaveRegDo_81 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_mux_0[0]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[10]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[10]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[11]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[11]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[12]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[12]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[13]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[13]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[14]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[14]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[1]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[2]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[3]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[4]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[4]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[5]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[6]_i_9_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[7]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[7]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[8]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[8]_i_6_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[9]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[9]_i_6_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_1__3_n_0\ : STD_LOGIC;
begin
\slaveRegDo_mux_0[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[0]_i_8_n_0\,
      I1 => slaveRegDo_84(0),
      I2 => \slaveRegDo_mux_0_reg[0]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[0]_0\
    );
\slaveRegDo_mux_0[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(0),
      I1 => \slaveRegDo_mux_0[0]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(0),
      I5 => slaveRegDo_82(0),
      O => \slaveRegDo_mux_0[0]_i_8_n_0\
    );
\slaveRegDo_mux_0[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[10]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[10]\,
      I3 => \slaveRegDo_mux_0_reg[10]_0\,
      I4 => \slaveRegDo_mux_0_reg[10]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(4)
    );
\slaveRegDo_mux_0[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[10]_i_6_n_0\,
      I1 => slaveRegDo_84(10),
      I2 => \slaveRegDo_mux_0_reg[10]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[10]_i_2_n_0\
    );
\slaveRegDo_mux_0[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(10),
      I1 => \slaveRegDo_mux_0[10]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(10),
      I5 => slaveRegDo_82(10),
      O => \slaveRegDo_mux_0[10]_i_6_n_0\
    );
\slaveRegDo_mux_0[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[11]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[11]\,
      I3 => \slaveRegDo_mux_0_reg[11]_0\,
      I4 => \slaveRegDo_mux_0_reg[11]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(5)
    );
\slaveRegDo_mux_0[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[11]_i_6_n_0\,
      I1 => slaveRegDo_84(11),
      I2 => \slaveRegDo_mux_0_reg[11]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[11]_i_2_n_0\
    );
\slaveRegDo_mux_0[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(11),
      I1 => \slaveRegDo_mux_0[11]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(11),
      I5 => slaveRegDo_82(11),
      O => \slaveRegDo_mux_0[11]_i_6_n_0\
    );
\slaveRegDo_mux_0[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[12]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[12]\,
      I3 => \slaveRegDo_mux_0_reg[12]_0\,
      I4 => \slaveRegDo_mux_0_reg[12]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(6)
    );
\slaveRegDo_mux_0[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[12]_i_6_n_0\,
      I1 => slaveRegDo_84(12),
      I2 => \slaveRegDo_mux_0_reg[12]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[12]_i_2_n_0\
    );
\slaveRegDo_mux_0[12]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(12),
      I1 => \slaveRegDo_mux_0[12]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(12),
      I5 => slaveRegDo_82(12),
      O => \slaveRegDo_mux_0[12]_i_6_n_0\
    );
\slaveRegDo_mux_0[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[13]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[13]\,
      I3 => \slaveRegDo_mux_0_reg[13]_0\,
      I4 => \slaveRegDo_mux_0_reg[13]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(7)
    );
\slaveRegDo_mux_0[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[13]_i_6_n_0\,
      I1 => slaveRegDo_84(13),
      I2 => \slaveRegDo_mux_0_reg[13]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[13]_i_2_n_0\
    );
\slaveRegDo_mux_0[13]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(13),
      I1 => \slaveRegDo_mux_0[13]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(13),
      I5 => slaveRegDo_82(13),
      O => \slaveRegDo_mux_0[13]_i_6_n_0\
    );
\slaveRegDo_mux_0[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[14]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[14]\,
      I3 => \slaveRegDo_mux_0_reg[14]_0\,
      I4 => \slaveRegDo_mux_0_reg[14]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(8)
    );
\slaveRegDo_mux_0[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[14]_i_6_n_0\,
      I1 => slaveRegDo_84(14),
      I2 => \slaveRegDo_mux_0_reg[14]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[14]_i_2_n_0\
    );
\slaveRegDo_mux_0[14]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(14),
      I1 => \slaveRegDo_mux_0[14]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(14),
      I5 => slaveRegDo_82(14),
      O => \slaveRegDo_mux_0[14]_i_6_n_0\
    );
\slaveRegDo_mux_0[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[15]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[15]_1\,
      I3 => \slaveRegDo_mux_0_reg[15]_2\,
      I4 => \slaveRegDo_mux_0_reg[15]_3\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(9)
    );
\slaveRegDo_mux_0[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[15]_i_8_n_0\,
      I1 => slaveRegDo_84(15),
      I2 => \slaveRegDo_mux_0_reg[15]_5\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[15]_i_2_n_0\
    );
\slaveRegDo_mux_0[15]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(15),
      I1 => \slaveRegDo_mux_0[15]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(15),
      I5 => slaveRegDo_82(15),
      O => \slaveRegDo_mux_0[15]_i_8_n_0\
    );
\slaveRegDo_mux_0[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[1]_i_7_n_0\,
      I1 => slaveRegDo_84(1),
      I2 => \slaveRegDo_mux_0_reg[1]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[1]_0\
    );
\slaveRegDo_mux_0[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(1),
      I1 => \slaveRegDo_mux_0[1]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(1),
      I5 => slaveRegDo_82(1),
      O => \slaveRegDo_mux_0[1]_i_7_n_0\
    );
\slaveRegDo_mux_0[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[2]_i_7_n_0\,
      I1 => slaveRegDo_84(2),
      I2 => \slaveRegDo_mux_0_reg[2]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[2]_0\
    );
\slaveRegDo_mux_0[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(2),
      I1 => \slaveRegDo_mux_0[2]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(2),
      I5 => slaveRegDo_82(2),
      O => \slaveRegDo_mux_0[2]_i_7_n_0\
    );
\slaveRegDo_mux_0[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[3]_i_7_n_0\,
      I1 => slaveRegDo_84(3),
      I2 => \slaveRegDo_mux_0_reg[3]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[3]_0\
    );
\slaveRegDo_mux_0[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(3),
      I1 => \slaveRegDo_mux_0[3]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(3),
      I5 => slaveRegDo_82(3),
      O => \slaveRegDo_mux_0[3]_i_7_n_0\
    );
\slaveRegDo_mux_0[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[4]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[4]\,
      I3 => \slaveRegDo_mux_0_reg[4]_0\,
      I4 => \slaveRegDo_mux_0_reg[4]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(0)
    );
\slaveRegDo_mux_0[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[4]_i_6_n_0\,
      I1 => slaveRegDo_84(4),
      I2 => \slaveRegDo_mux_0_reg[4]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[4]_i_2_n_0\
    );
\slaveRegDo_mux_0[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(4),
      I1 => \slaveRegDo_mux_0[4]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(4),
      I5 => slaveRegDo_82(4),
      O => \slaveRegDo_mux_0[4]_i_6_n_0\
    );
\slaveRegDo_mux_0[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[5]_i_7_n_0\,
      I1 => slaveRegDo_84(5),
      I2 => \slaveRegDo_mux_0_reg[5]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[5]_0\
    );
\slaveRegDo_mux_0[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(5),
      I1 => \slaveRegDo_mux_0[5]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(5),
      I5 => slaveRegDo_82(5),
      O => \slaveRegDo_mux_0[5]_i_7_n_0\
    );
\slaveRegDo_mux_0[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[6]_i_9_n_0\,
      I1 => slaveRegDo_84(6),
      I2 => \slaveRegDo_mux_0_reg[6]\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \xsdb_reg_reg[6]_0\
    );
\slaveRegDo_mux_0[6]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(6),
      I1 => \slaveRegDo_mux_0[6]_i_3_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(6),
      I5 => slaveRegDo_82(6),
      O => \slaveRegDo_mux_0[6]_i_9_n_0\
    );
\slaveRegDo_mux_0[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[7]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[7]\,
      I3 => \slaveRegDo_mux_0_reg[7]_0\,
      I4 => \slaveRegDo_mux_0_reg[7]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(1)
    );
\slaveRegDo_mux_0[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[7]_i_6_n_0\,
      I1 => slaveRegDo_84(7),
      I2 => \slaveRegDo_mux_0_reg[7]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[7]_i_2_n_0\
    );
\slaveRegDo_mux_0[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(7),
      I1 => \slaveRegDo_mux_0[7]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(7),
      I5 => slaveRegDo_82(7),
      O => \slaveRegDo_mux_0[7]_i_6_n_0\
    );
\slaveRegDo_mux_0[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[8]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[8]\,
      I3 => \slaveRegDo_mux_0_reg[8]_0\,
      I4 => \slaveRegDo_mux_0_reg[8]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(2)
    );
\slaveRegDo_mux_0[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[8]_i_6_n_0\,
      I1 => slaveRegDo_84(8),
      I2 => \slaveRegDo_mux_0_reg[8]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[8]_i_2_n_0\
    );
\slaveRegDo_mux_0[8]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(8),
      I1 => \slaveRegDo_mux_0[8]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(8),
      I5 => slaveRegDo_82(8),
      O => \slaveRegDo_mux_0[8]_i_6_n_0\
    );
\slaveRegDo_mux_0[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF888888888"
    )
        port map (
      I0 => \slaveRegDo_mux_0[9]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[15]\,
      I2 => \slaveRegDo_mux_0_reg[9]\,
      I3 => \slaveRegDo_mux_0_reg[9]_0\,
      I4 => \slaveRegDo_mux_0_reg[9]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => D(3)
    );
\slaveRegDo_mux_0[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[9]_i_6_n_0\,
      I1 => slaveRegDo_84(9),
      I2 => \slaveRegDo_mux_0_reg[9]_2\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0_reg[15]_4\,
      O => \slaveRegDo_mux_0[9]_i_2_n_0\
    );
\slaveRegDo_mux_0[9]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => slaveRegDo_81(9),
      I1 => \slaveRegDo_mux_0[9]_i_2_0\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => slaveRegDo_80(9),
      I5 => slaveRegDo_82(9),
      O => \slaveRegDo_mux_0[9]_i_6_n_0\
    );
\xsdb_reg[15]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__3_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(0),
      Q => slaveRegDo_81(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(10),
      Q => slaveRegDo_81(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(11),
      Q => slaveRegDo_81(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(12),
      Q => slaveRegDo_81(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(13),
      Q => slaveRegDo_81(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(14),
      Q => slaveRegDo_81(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(15),
      Q => slaveRegDo_81(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(1),
      Q => slaveRegDo_81(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(2),
      Q => slaveRegDo_81(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(3),
      Q => slaveRegDo_81(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(4),
      Q => slaveRegDo_81(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(5),
      Q => slaveRegDo_81(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(6),
      Q => slaveRegDo_81(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(7),
      Q => slaveRegDo_81(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(8),
      Q => slaveRegDo_81(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__3_n_0\,
      D => s_di_o(9),
      Q => slaveRegDo_81(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_39 is
  port (
    \G_1PIPE_IFACE.s_den_r_reg\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 8 downto 0 );
    s_den_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_39 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_39;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_39 is
  signal \^g_1pipe_iface.s_den_r_reg\ : STD_LOGIC;
  signal slaveRegDo_6 : STD_LOGIC_VECTOR ( 6 to 6 );
  signal \xsdb_reg[15]_i_1__12_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_3__0_n_0\ : STD_LOGIC;
begin
  \G_1PIPE_IFACE.s_den_r_reg\ <= \^g_1pipe_iface.s_den_r_reg\;
\slaveRegDo_mux_0[6]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000A0000C0000"
    )
        port map (
      I0 => slaveRegDo_6(6),
      I1 => Q(0),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(3),
      I5 => s_daddr_o(2),
      O => \xsdb_reg_reg[6]_0\
    );
\xsdb_reg[15]_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(3),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \^g_1pipe_iface.s_den_r_reg\,
      O => \xsdb_reg[15]_i_1__12_n_0\
    );
\xsdb_reg[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => s_den_o,
      I1 => s_dwe_o,
      I2 => s_daddr_o(8),
      I3 => s_daddr_o(5),
      I4 => \xsdb_reg[15]_i_3__0_n_0\,
      I5 => \xsdb_reg_reg[0]_1\,
      O => \^g_1pipe_iface.s_den_r_reg\
    );
\xsdb_reg[15]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_daddr_o(7),
      I1 => s_daddr_o(6),
      O => \xsdb_reg[15]_i_3__0_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[15]_0\(6),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[15]_0\(7),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[15]_0\(8),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[15]_0\(9),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[15]_0\(10),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\(11),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[15]_0\(0),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[15]_0\(1),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[15]_0\(2),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(6),
      Q => slaveRegDo_6(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[15]_0\(3),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[15]_0\(4),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__12_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[15]_0\(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_41 is
  port (
    \G_1PIPE_IFACE.s_daddr_r_reg[1]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_41 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_41;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_41 is
  signal \xsdb_reg[15]_i_1__6_n_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[9]\ : STD_LOGIC;
begin
\slaveRegDo_mux_0[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[0]\,
      I4 => \slaveRegDo_mux_0[0]_i_2\,
      I5 => \slaveRegDo_mux_0[0]_i_2_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\
    );
\slaveRegDo_mux_0[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[10]\,
      I4 => \slaveRegDo_mux_0_reg[10]\,
      I5 => \slaveRegDo_mux_0_reg[10]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\
    );
\slaveRegDo_mux_0[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[11]\,
      I4 => \slaveRegDo_mux_0_reg[11]\,
      I5 => \slaveRegDo_mux_0_reg[11]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\
    );
\slaveRegDo_mux_0[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[12]\,
      I4 => \slaveRegDo_mux_0_reg[12]\,
      I5 => \slaveRegDo_mux_0_reg[12]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\
    );
\slaveRegDo_mux_0[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[13]\,
      I4 => \slaveRegDo_mux_0_reg[13]\,
      I5 => \slaveRegDo_mux_0_reg[13]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\
    );
\slaveRegDo_mux_0[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[14]\,
      I4 => \slaveRegDo_mux_0_reg[14]\,
      I5 => \slaveRegDo_mux_0_reg[14]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\
    );
\slaveRegDo_mux_0[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[15]\,
      I4 => \slaveRegDo_mux_0_reg[15]\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]\
    );
\slaveRegDo_mux_0[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[4]\,
      I4 => \slaveRegDo_mux_0_reg[4]_0\,
      I5 => \slaveRegDo_mux_0_reg[4]_1\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\
    );
\slaveRegDo_mux_0[5]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[5]\,
      I4 => \slaveRegDo_mux_0[5]_i_2\,
      I5 => \slaveRegDo_mux_0[5]_i_2_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\
    );
\slaveRegDo_mux_0[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[6]\,
      I4 => \slaveRegDo_mux_0[6]_i_2\,
      I5 => \slaveRegDo_mux_0[6]_i_2_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\
    );
\slaveRegDo_mux_0[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[8]\,
      I4 => \slaveRegDo_mux_0_reg[8]\,
      I5 => \slaveRegDo_mux_0_reg[8]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\
    );
\slaveRegDo_mux_0[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A0A220228082000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[4]\,
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(0),
      I3 => \xsdb_reg_reg_n_0_[9]\,
      I4 => \slaveRegDo_mux_0_reg[9]\,
      I5 => \slaveRegDo_mux_0_reg[9]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\
    );
\xsdb_reg[15]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__6_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg_n_0_[0]\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg_n_0_[10]\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg_n_0_[11]\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg_n_0_[12]\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg_n_0_[13]\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg_n_0_[14]\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg_n_0_[15]\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[3]_0\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg_n_0_[4]\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg_n_0_[5]\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg_n_0_[6]\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[7]_0\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg_n_0_[8]\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__6_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_42 is
  port (
    \G_1PIPE_IFACE.s_daddr_r_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_0[7]_i_3_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[7]_i_3_1\ : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_0[2]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_42 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_42;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_42 is
  signal \slaveRegDo_mux_0[7]_i_7_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_1__7_n_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[7]\ : STD_LOGIC;
begin
\slaveRegDo_mux_0[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00CCF0AA"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[1]\,
      I1 => \slaveRegDo_mux_0[2]_i_2\(0),
      I2 => \slaveRegDo_mux_0[1]_i_2\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      O => \xsdb_reg_reg[1]_0\
    );
\slaveRegDo_mux_0[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00CCF0AA"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[2]\,
      I1 => \slaveRegDo_mux_0[2]_i_2\(1),
      I2 => \slaveRegDo_mux_0[2]_i_2_0\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      O => \xsdb_reg_reg[2]_0\
    );
\slaveRegDo_mux_0[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00CCF0AA"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[3]\,
      I1 => in0,
      I2 => \slaveRegDo_mux_0[3]_i_2\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      O => \xsdb_reg_reg[3]_0\
    );
\slaveRegDo_mux_0[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B00080008000800"
    )
        port map (
      I0 => \slaveRegDo_mux_0[7]_i_7_n_0\,
      I1 => \slaveRegDo_mux_0_reg[7]\,
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(3),
      I4 => \slaveRegDo_mux_0_reg[7]_0\,
      I5 => Q(0),
      O => \G_1PIPE_IFACE.s_daddr_r_reg[2]\
    );
\slaveRegDo_mux_0[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00CCF0AA"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[7]\,
      I1 => \slaveRegDo_mux_0[7]_i_3_0\,
      I2 => \slaveRegDo_mux_0[7]_i_3_1\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      O => \slaveRegDo_mux_0[7]_i_7_n_0\
    );
\xsdb_reg[15]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__7_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg_n_0_[1]\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg_n_0_[2]\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg_n_0_[3]\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[4]_0\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[5]_0\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg[6]_0\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg_n_0_[7]\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[8]_0\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__7_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[9]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_43 is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_01__6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    read_reset_addr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_43 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_43;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_43 is
  signal \slaveRegDo_mux_0[0]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[0]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[6]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[6]_i_5_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_1__8_n_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[9]\ : STD_LOGIC;
begin
\slaveRegDo_mux_0[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[0]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[6]\,
      I2 => \slaveRegDo_mux_0_reg[0]\,
      I3 => \slaveRegDo_mux_0_reg[6]_0\(0),
      I4 => \slaveRegDo_mux_01__6\,
      O => D(0)
    );
\slaveRegDo_mux_0[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAA8AAA8AAA8A8"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[6]_2\,
      I1 => \slaveRegDo_mux_0[0]_i_4_n_0\,
      I2 => \slaveRegDo_mux_0_reg[0]_0\,
      I3 => \slaveRegDo_mux_0_reg[6]_3\,
      I4 => \slaveRegDo_mux_0_reg[0]_1\,
      I5 => \slaveRegDo_mux_0_reg[0]_2\,
      O => \slaveRegDo_mux_0[0]_i_2_n_0\
    );
\slaveRegDo_mux_0[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[0]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => SR(0),
      I5 => read_reset_addr(0),
      O => \slaveRegDo_mux_0[0]_i_4_n_0\
    );
\slaveRegDo_mux_0[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[10]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[10]\,
      I5 => \slaveRegDo_mux_0_reg[10]_0\,
      O => \xsdb_reg_reg[10]_0\
    );
\slaveRegDo_mux_0[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[11]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[11]\,
      I5 => \slaveRegDo_mux_0_reg[11]_0\,
      O => \xsdb_reg_reg[11]_0\
    );
\slaveRegDo_mux_0[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[12]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[12]\,
      I5 => \slaveRegDo_mux_0_reg[12]_0\,
      O => \xsdb_reg_reg[12]_0\
    );
\slaveRegDo_mux_0[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[13]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[13]\,
      I5 => \slaveRegDo_mux_0_reg[13]_0\,
      O => \xsdb_reg_reg[13]_0\
    );
\slaveRegDo_mux_0[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[14]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[14]\,
      I5 => \slaveRegDo_mux_0_reg[14]_0\,
      O => \xsdb_reg_reg[14]_0\
    );
\slaveRegDo_mux_0[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[15]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_0\,
      I5 => \slaveRegDo_mux_0_reg[15]_1\,
      O => \xsdb_reg_reg[15]_0\
    );
\slaveRegDo_mux_0[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[4]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[4]\,
      I5 => read_reset_addr(1),
      O => \xsdb_reg_reg[4]_0\
    );
\slaveRegDo_mux_0[5]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[5]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0[5]_i_2\,
      I5 => read_reset_addr(2),
      O => \xsdb_reg_reg[5]_0\
    );
\slaveRegDo_mux_0[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[6]_i_2_n_0\,
      I1 => \slaveRegDo_mux_0_reg[6]\,
      I2 => \slaveRegDo_mux_0_reg[6]_1\,
      I3 => \slaveRegDo_mux_0_reg[6]_0\(1),
      I4 => \slaveRegDo_mux_01__6\,
      O => D(1)
    );
\slaveRegDo_mux_0[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAA8AAA8AAA8A8"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[6]_2\,
      I1 => \slaveRegDo_mux_0[6]_i_5_n_0\,
      I2 => \slaveRegDo_mux_0_reg[6]_4\,
      I3 => \slaveRegDo_mux_0_reg[6]_3\,
      I4 => \slaveRegDo_mux_0_reg[6]_5\,
      I5 => \slaveRegDo_mux_0_reg[6]_6\,
      O => \slaveRegDo_mux_0[6]_i_2_n_0\
    );
\slaveRegDo_mux_0[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[6]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0[6]_i_2_0\,
      I5 => read_reset_addr(3),
      O => \slaveRegDo_mux_0[6]_i_5_n_0\
    );
\slaveRegDo_mux_0[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[7]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[7]\,
      I5 => read_reset_addr(4),
      O => \xsdb_reg_reg[7]_0\
    );
\slaveRegDo_mux_0[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[8]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[8]\,
      I5 => read_reset_addr(5),
      O => \xsdb_reg_reg[8]_0\
    );
\slaveRegDo_mux_0[9]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AA080A08A008000"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[15]\,
      I1 => \xsdb_reg_reg_n_0_[9]\,
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[9]\,
      I5 => read_reset_addr(6),
      O => \xsdb_reg_reg[9]_0\
    );
\xsdb_reg[15]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(3),
      I2 => s_daddr_o(4),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(1),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__8_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg_n_0_[0]\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg_n_0_[10]\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg_n_0_[11]\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg_n_0_[12]\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg_n_0_[13]\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg_n_0_[14]\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg_n_0_[15]\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[3]_0\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg_n_0_[4]\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg_n_0_[5]\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg_n_0_[6]\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg_n_0_[7]\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg_n_0_[8]\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__8_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_44 is
  port (
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    read_reset_addr : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_44 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_44;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_44 is
  signal \^read_reset_addr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \xsdb_reg[15]_i_1__9_n_0\ : STD_LOGIC;
begin
  read_reset_addr(9 downto 0) <= \^read_reset_addr\(9 downto 0);
\slaveRegDo_mux_0[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAC00AC0"
    )
        port map (
      I0 => \^read_reset_addr\(1),
      I1 => \slaveRegDo_mux_0[1]_i_2\,
      I2 => s_daddr_o(0),
      I3 => s_daddr_o(1),
      I4 => \slaveRegDo_mux_0[1]_i_2_0\,
      O => \xsdb_reg_reg[1]_0\
    );
\slaveRegDo_mux_0[2]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAC00AC0"
    )
        port map (
      I0 => \^read_reset_addr\(2),
      I1 => \slaveRegDo_mux_0[2]_i_2\,
      I2 => s_daddr_o(0),
      I3 => s_daddr_o(1),
      I4 => \slaveRegDo_mux_0[2]_i_2_0\,
      O => \xsdb_reg_reg[2]_0\
    );
\slaveRegDo_mux_0[3]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAC00AC0"
    )
        port map (
      I0 => \^read_reset_addr\(3),
      I1 => \slaveRegDo_mux_0[3]_i_2\,
      I2 => s_daddr_o(0),
      I3 => s_daddr_o(1),
      I4 => \slaveRegDo_mux_0[3]_i_2_0\,
      O => \xsdb_reg_reg[3]_0\
    );
\xsdb_reg[15]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(3),
      I2 => s_daddr_o(4),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(1),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__9_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(0),
      Q => \^read_reset_addr\(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(1),
      Q => \^read_reset_addr\(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(2),
      Q => \^read_reset_addr\(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(3),
      Q => \^read_reset_addr\(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(4),
      Q => \^read_reset_addr\(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(5),
      Q => \^read_reset_addr\(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(6),
      Q => \^read_reset_addr\(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(7),
      Q => \^read_reset_addr\(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(8),
      Q => \^read_reset_addr\(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__9_n_0\,
      D => s_di_o(9),
      Q => \^read_reset_addr\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_ctl_45 is
  port (
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_45 : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_full_aurora_xsdbs_v1_0_2_reg_ctl_45;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_ctl_45 is
  signal \xsdb_reg[15]_i_1__10_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000000000000"
    )
        port map (
      I0 => s_daddr_o(2),
      I1 => s_daddr_o(3),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__10_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(0),
      Q => SR(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[1]_0\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg[3]_0\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[4]_0\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[5]_0\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg[6]_0\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[7]_0\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[8]_0\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__10_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[9]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized0\ is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \G_1PIPE_IFACE.s_daddr_r_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[0]\ : out STD_LOGIC;
    halt_ctrl : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\ : out STD_LOGIC;
    scnt_cmp_temp : out STD_LOGIC;
    wcnt_lcmp_temp : out STD_LOGIC;
    wcnt_hcmp_temp : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \slaveRegDo_mux_01__6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \slaveRegDo_mux_0[3]_i_2_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \slaveRegDo_mux_0[1]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_4_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_4_0\ : in STD_LOGIC;
    DOUT_O : in STD_LOGIC;
    u_wcnt_lcmp_q : in STD_LOGIC;
    u_wcnt_hcmp_q : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized0\ : entity is "xsdbs_v1_0_2_reg_ctl";
end \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized0\ is
  signal \^halt_ctrl\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[1]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[1]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[1]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[2]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[2]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[2]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[3]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[3]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[3]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[5]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_1__11_n_0\ : STD_LOGIC;
  signal \^xsdb_reg_reg[0]_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of u_scnt_cmp_q_i_2 : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of u_wcnt_lcmp_q_i_1 : label is "soft_lutpair48";
begin
  halt_ctrl <= \^halt_ctrl\;
  \xsdb_reg_reg[0]_0\ <= \^xsdb_reg_reg[0]_0\;
\slaveRegDo_mux_0[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000444440000044"
    )
        port map (
      I0 => s_daddr_o(3),
      I1 => s_daddr_o(2),
      I2 => \^xsdb_reg_reg[0]_0\,
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0[0]_i_2\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[3]\
    );
\slaveRegDo_mux_0[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A008200880080008"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[7]\,
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(2),
      I4 => \xsdb_reg_reg_n_0_[10]\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\(2),
      O => \G_1PIPE_IFACE.s_daddr_r_reg[0]\
    );
\slaveRegDo_mux_0[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A0C00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[11]\,
      I1 => \slaveRegDo_mux_0_reg[15]_0\(3),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \xsdb_reg_reg[11]_0\
    );
\slaveRegDo_mux_0[12]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A0C00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[12]\,
      I1 => \slaveRegDo_mux_0_reg[15]_0\(4),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \xsdb_reg_reg[12]_0\
    );
\slaveRegDo_mux_0[13]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A0C00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[13]\,
      I1 => \slaveRegDo_mux_0_reg[15]_0\(5),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \xsdb_reg_reg[13]_0\
    );
\slaveRegDo_mux_0[14]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A0C00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[14]\,
      I1 => \slaveRegDo_mux_0_reg[15]_0\(6),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \xsdb_reg_reg[14]_0\
    );
\slaveRegDo_mux_0[15]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A0C00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[15]\,
      I1 => \slaveRegDo_mux_0_reg[15]_0\(7),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_0_reg[15]_1\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \xsdb_reg_reg[15]_0\
    );
\slaveRegDo_mux_0[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[5]\,
      I1 => \slaveRegDo_mux_0[1]_i_2_n_0\,
      I2 => \slaveRegDo_mux_0_reg[5]_0\,
      I3 => \slaveRegDo_mux_0_reg[1]\,
      I4 => \slaveRegDo_mux_0_reg[5]_1\(0),
      I5 => \slaveRegDo_mux_01__6\,
      O => D(0)
    );
\slaveRegDo_mux_0[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0CC00AAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[1]_i_4_n_0\,
      I1 => \slaveRegDo_mux_0_reg[1]_0\,
      I2 => \slaveRegDo_mux_0_reg[1]_1\,
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(2),
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \slaveRegDo_mux_0[1]_i_2_n_0\
    );
\slaveRegDo_mux_0[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAFAAAEE"
    )
        port map (
      I0 => \slaveRegDo_mux_0[1]_i_8_n_0\,
      I1 => \slaveRegDo_mux_0[3]_i_2_0\(0),
      I2 => Q(0),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0[1]_i_2_0\,
      O => \slaveRegDo_mux_0[1]_i_4_n_0\
    );
\slaveRegDo_mux_0[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E161C141"
    )
        port map (
      I0 => s_daddr_o(2),
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(1),
      I3 => \^halt_ctrl\,
      I4 => \slaveRegDo_mux_0[1]_i_4_0\,
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_0[1]_i_8_n_0\
    );
\slaveRegDo_mux_0[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[5]\,
      I1 => \slaveRegDo_mux_0[2]_i_2_n_0\,
      I2 => \slaveRegDo_mux_0_reg[5]_0\,
      I3 => \slaveRegDo_mux_0_reg[2]\,
      I4 => \slaveRegDo_mux_0_reg[5]_1\(1),
      I5 => \slaveRegDo_mux_01__6\,
      O => D(1)
    );
\slaveRegDo_mux_0[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0CC00AAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[2]_i_4_n_0\,
      I1 => \slaveRegDo_mux_0_reg[2]_0\,
      I2 => \slaveRegDo_mux_0_reg[2]_1\,
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(2),
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \slaveRegDo_mux_0[2]_i_2_n_0\
    );
\slaveRegDo_mux_0[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAFAAAEE"
    )
        port map (
      I0 => \slaveRegDo_mux_0[2]_i_8_n_0\,
      I1 => \slaveRegDo_mux_0[3]_i_2_0\(1),
      I2 => Q(1),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0[1]_i_2_0\,
      O => \slaveRegDo_mux_0[2]_i_4_n_0\
    );
\slaveRegDo_mux_0[2]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000C8488808"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => \xsdb_reg_reg_n_0_[2]\,
      I4 => \slaveRegDo_mux_0[2]_i_4_0\,
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_0[2]_i_8_n_0\
    );
\slaveRegDo_mux_0[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[5]\,
      I1 => \slaveRegDo_mux_0[3]_i_2_n_0\,
      I2 => \slaveRegDo_mux_0_reg[5]_0\,
      I3 => \slaveRegDo_mux_0_reg[3]\,
      I4 => \slaveRegDo_mux_0_reg[5]_1\(2),
      I5 => \slaveRegDo_mux_01__6\,
      O => D(2)
    );
\slaveRegDo_mux_0[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0CC00AAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_0[3]_i_4_n_0\,
      I1 => \slaveRegDo_mux_0_reg[3]_0\,
      I2 => \slaveRegDo_mux_0_reg[3]_1\,
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(2),
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \slaveRegDo_mux_0[3]_i_2_n_0\
    );
\slaveRegDo_mux_0[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAFAAAEE"
    )
        port map (
      I0 => \slaveRegDo_mux_0[3]_i_8_n_0\,
      I1 => \slaveRegDo_mux_0[3]_i_2_0\(2),
      I2 => Q(2),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \slaveRegDo_mux_0[1]_i_2_0\,
      O => \slaveRegDo_mux_0[3]_i_4_n_0\
    );
\slaveRegDo_mux_0[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000C1418101"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => \xsdb_reg_reg_n_0_[3]\,
      I4 => \slaveRegDo_mux_0_reg[15]_0\(0),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_0[3]_i_8_n_0\
    );
\slaveRegDo_mux_0[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0400"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[9]\,
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(3),
      I3 => \xsdb_reg_reg_n_0_[4]\,
      I4 => \slaveRegDo_mux_0_reg[4]\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[2]\
    );
\slaveRegDo_mux_0[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[5]\,
      I1 => \slaveRegDo_mux_0[5]_i_2_n_0\,
      I2 => \slaveRegDo_mux_01__6\,
      I3 => \slaveRegDo_mux_0_reg[5]_1\(3),
      I4 => \slaveRegDo_mux_0_reg[5]_2\,
      I5 => \slaveRegDo_mux_0_reg[5]_0\,
      O => D(3)
    );
\slaveRegDo_mux_0[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF00F8"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[5]_3\,
      I1 => \xsdb_reg_reg_n_0_[5]\,
      I2 => \slaveRegDo_mux_0_reg[5]_4\,
      I3 => \slaveRegDo_mux_0_reg[15]\,
      I4 => \slaveRegDo_mux_0_reg[5]_5\,
      I5 => \slaveRegDo_mux_0_reg[5]_6\,
      O => \slaveRegDo_mux_0[5]_i_2_n_0\
    );
\slaveRegDo_mux_0[6]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000A0000C000000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[6]\,
      I1 => Q(3),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(3),
      I5 => s_daddr_o(2),
      O => \xsdb_reg_reg[6]_0\
    );
\slaveRegDo_mux_0[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A002200280020002"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[7]\,
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(2),
      I4 => \xsdb_reg_reg_n_0_[7]\,
      I5 => \slaveRegDo_mux_0_reg[15]_0\(1),
      O => \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\
    );
\slaveRegDo_mux_0[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0400"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[9]\,
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(3),
      I3 => \xsdb_reg_reg_n_0_[8]\,
      I4 => \slaveRegDo_mux_0_reg[8]\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\
    );
\slaveRegDo_mux_0[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0400"
    )
        port map (
      I0 => \slaveRegDo_mux_0_reg[9]\,
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(3),
      I3 => \xsdb_reg_reg_n_0_[9]\,
      I4 => \slaveRegDo_mux_0_reg[9]_0\,
      I5 => \slaveRegDo_mux_0_reg[15]\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\
    );
u_scnt_cmp_q_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^xsdb_reg_reg[0]_0\,
      I1 => DOUT_O,
      O => scnt_cmp_temp
    );
u_wcnt_hcmp_q_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^xsdb_reg_reg[0]_0\,
      I1 => u_wcnt_hcmp_q,
      O => wcnt_hcmp_temp
    );
u_wcnt_lcmp_q_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^xsdb_reg_reg[0]_0\,
      I1 => u_wcnt_lcmp_q,
      O => wcnt_lcmp_temp
    );
\xsdb_reg[15]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(3),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(0),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__11_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(0),
      Q => \^xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg_n_0_[10]\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg_n_0_[11]\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg_n_0_[12]\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg_n_0_[13]\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg_n_0_[14]\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg_n_0_[15]\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(1),
      Q => \^halt_ctrl\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg_n_0_[2]\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(3),
      Q => \xsdb_reg_reg_n_0_[3]\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg_n_0_[4]\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg_n_0_[5]\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg_n_0_[6]\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg_n_0_[7]\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg_n_0_[8]\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__11_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1\ is
  port (
    slaveRegDo_82 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1\ : entity is "xsdbs_v1_0_2_reg_ctl";
end \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1\ is
  signal \xsdb_reg[15]_i_1__2_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \xsdb_reg_reg[0]_0\,
      O => \xsdb_reg[15]_i_1__2_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(0),
      Q => slaveRegDo_82(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(10),
      Q => slaveRegDo_82(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(11),
      Q => slaveRegDo_82(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(12),
      Q => slaveRegDo_82(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(13),
      Q => slaveRegDo_82(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(14),
      Q => slaveRegDo_82(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(15),
      Q => slaveRegDo_82(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(1),
      Q => slaveRegDo_82(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(2),
      Q => slaveRegDo_82(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(3),
      Q => slaveRegDo_82(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(4),
      Q => slaveRegDo_82(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(5),
      Q => slaveRegDo_82(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(6),
      Q => slaveRegDo_82(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(7),
      Q => slaveRegDo_82(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(8),
      Q => slaveRegDo_82(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__2_n_0\,
      D => s_di_o(9),
      Q => slaveRegDo_82(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_37\ is
  port (
    \G_1PIPE_IFACE.s_den_r_reg\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[6]\ : out STD_LOGIC;
    slaveRegDo_80 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_den_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_37\ : entity is "xsdbs_v1_0_2_reg_ctl";
end \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_37\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_37\ is
  signal \^g_1pipe_iface.s_daddr_r_reg[6]\ : STD_LOGIC;
  signal \^g_1pipe_iface.s_den_r_reg\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_1__4_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_3_n_0\ : STD_LOGIC;
begin
  \G_1PIPE_IFACE.s_daddr_r_reg[6]\ <= \^g_1pipe_iface.s_daddr_r_reg[6]\;
  \G_1PIPE_IFACE.s_den_r_reg\ <= \^g_1pipe_iface.s_den_r_reg\;
\xsdb_reg[15]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^g_1pipe_iface.s_den_r_reg\,
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => s_daddr_o(0),
      O => \xsdb_reg[15]_i_1__4_n_0\
    );
\xsdb_reg[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => s_den_o,
      I1 => s_dwe_o,
      I2 => \xsdb_reg[15]_i_3_n_0\,
      I3 => s_daddr_o(7),
      I4 => s_daddr_o(8),
      I5 => \^g_1pipe_iface.s_daddr_r_reg[6]\,
      O => \^g_1pipe_iface.s_den_r_reg\
    );
\xsdb_reg[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => s_daddr_o(12),
      I1 => s_daddr_o(9),
      I2 => s_daddr_o(10),
      I3 => s_daddr_o(11),
      O => \xsdb_reg[15]_i_3_n_0\
    );
\xsdb_reg[15]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_daddr_o(6),
      I1 => s_daddr_o(5),
      O => \^g_1pipe_iface.s_daddr_r_reg[6]\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(0),
      Q => slaveRegDo_80(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(10),
      Q => slaveRegDo_80(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(11),
      Q => slaveRegDo_80(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(12),
      Q => slaveRegDo_80(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(13),
      Q => slaveRegDo_80(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(14),
      Q => slaveRegDo_80(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(15),
      Q => slaveRegDo_80(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(1),
      Q => slaveRegDo_80(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(2),
      Q => slaveRegDo_80(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(3),
      Q => slaveRegDo_80(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(4),
      Q => slaveRegDo_80(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(5),
      Q => slaveRegDo_80(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(6),
      Q => slaveRegDo_80(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(7),
      Q => slaveRegDo_80(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(8),
      Q => slaveRegDo_80(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__4_n_0\,
      D => s_di_o(9),
      Q => slaveRegDo_80(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_40\ is
  port (
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[14]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[13]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[12]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[11]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[10]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[6]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    in0 : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_40\ : entity is "xsdbs_v1_0_2_reg_ctl";
end \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_40\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_40\ is
  signal \xsdb_reg[15]_i_1__5_n_0\ : STD_LOGIC;
begin
\xsdb_reg[15]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => s_daddr_o(1),
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(4),
      I4 => s_daddr_o(2),
      I5 => \xsdb_reg_reg[0]_1\,
      O => \xsdb_reg[15]_i_1__5_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(0),
      Q => \xsdb_reg_reg[0]_0\,
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(10),
      Q => \xsdb_reg_reg[10]_0\,
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(11),
      Q => \xsdb_reg_reg[11]_0\,
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(12),
      Q => \xsdb_reg_reg[12]_0\,
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(13),
      Q => \xsdb_reg_reg[13]_0\,
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(14),
      Q => \xsdb_reg_reg[14]_0\,
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(15),
      Q => \xsdb_reg_reg[15]_0\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(1),
      Q => \xsdb_reg_reg[2]_0\(0),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(2),
      Q => \xsdb_reg_reg[2]_0\(1),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(3),
      Q => in0,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(4),
      Q => \xsdb_reg_reg[4]_0\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(5),
      Q => \xsdb_reg_reg[5]_0\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(6),
      Q => \xsdb_reg_reg[6]_0\,
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(7),
      Q => \xsdb_reg_reg[7]_0\,
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(8),
      Q => \xsdb_reg_reg[8]_0\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => \xsdb_reg[15]_i_1__5_n_0\,
      D => s_di_o(9),
      Q => \xsdb_reg_reg[9]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_p2s is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    \G_1PIPE_IFACE.s_den_r_reg\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 10 downto 0 );
    s_den_o : in STD_LOGIC;
    \current_state[3]_i_2__3\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_p2s : entity is "xsdbs_v1_0_2_reg_p2s";
end ila_full_aurora_xsdbs_v1_0_2_reg_p2s;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_p2s is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^g_1pipe_iface.s_den_r_reg\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__0_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_5_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__0_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shadow[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__0_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__0\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__0\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__0\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__0\ : label is "soft_lutpair21";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__0\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \shadow[15]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \shift_en_i_1__0\ : label is "soft_lutpair23";
begin
  E(0) <= \^e\(0);
  \G_1PIPE_IFACE.s_den_r_reg\ <= \^g_1pipe_iface.s_den_r_reg\;
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__2\(0)
    );
\cnt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__2\(1)
    );
\cnt[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__0_n_0\
    );
\cnt[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__0_n_0\
    );
\cnt[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__2\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__0_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__0_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__0_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__0_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__0_n_0\
    );
\current_state[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__0_n_0\,
      I4 => \current_state[3]_i_2__4_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__4_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__0_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__4_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__0_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^g_1pipe_iface.s_den_r_reg\,
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => s_daddr_o(0),
      O => \current_state[3]_i_2__4_n_0\
    );
\current_state[3]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__0_n_0\
    );
\current_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => s_den_o,
      I1 => s_daddr_o(6),
      I2 => s_daddr_o(5),
      I3 => \current_state[3]_i_2__3\,
      I4 => s_daddr_o(7),
      I5 => \current_state[3]_i_5_n_0\,
      O => \^g_1pipe_iface.s_den_r_reg\
    );
\current_state[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => s_daddr_o(8),
      I1 => s_daddr_o(9),
      I2 => s_daddr_o(10),
      O => \current_state[3]_i_5_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__0_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__0_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__0_n_0\
    );
\shadow[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__0_n_0\
    );
\shadow[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__0_n_0\
    );
\shadow[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__0_n_0\
    );
\shadow[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__0_n_0\
    );
\shadow[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__0_n_0\
    );
\shadow[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1_n_0\
    );
\shadow[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__0_n_0\
    );
\shadow[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__0_n_0\
    );
\shadow[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__0_n_0\
    );
\shadow[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__0_n_0\
    );
\shadow[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__0_n_0\
    );
\shadow[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__0_n_0\
    );
\shadow[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__0_n_0\
    );
\shadow[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__0_n_0\
    );
\shadow[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__0_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__0_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__0_n_0\,
      Q => \^e\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized0\ is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \current_state_reg[3]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_4_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_4_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_4_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_4_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized0\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized0\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \cnt[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__1_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__1_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \parallel_dout_reg_n_0_[0]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[10]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[11]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[12]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[13]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[14]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[15]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[1]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[2]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[3]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[4]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[5]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[6]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[7]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[8]\ : STD_LOGIC;
  signal \parallel_dout_reg_n_0_[9]\ : STD_LOGIC;
  signal \shadow[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[0]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[10]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[11]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[12]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[13]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[14]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[15]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[1]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[2]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[3]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[4]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[5]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[6]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[7]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[8]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_4[9]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__1\ : label is "soft_lutpair26";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \shadow[15]_i_1__0\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \shift_en_i_1__1\ : label is "soft_lutpair27";
begin
  E(0) <= \^e\(0);
\cnt[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__3\(0)
    );
\cnt[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__3\(1)
    );
\cnt[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__1_n_0\
    );
\cnt[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__1_n_0\
    );
\cnt[3]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__3\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__3\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__1_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__3\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__1_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__1_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__1_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__3\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__1_n_0\
    );
\current_state[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__1_n_0\,
      I4 => \current_state[3]_i_2__3_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__3_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__1_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__3_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__1_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \current_state_reg[3]_0\,
      O => \current_state[3]_i_2__3_n_0\
    );
\current_state[3]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__1_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__1_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__1_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[1]\,
      Q => \parallel_dout_reg_n_0_[0]\,
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[11]\,
      Q => \parallel_dout_reg_n_0_[10]\,
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[12]\,
      Q => \parallel_dout_reg_n_0_[11]\,
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[13]\,
      Q => \parallel_dout_reg_n_0_[12]\,
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[14]\,
      Q => \parallel_dout_reg_n_0_[13]\,
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[15]\,
      Q => \parallel_dout_reg_n_0_[14]\,
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \parallel_dout_reg_n_0_[15]\,
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[2]\,
      Q => \parallel_dout_reg_n_0_[1]\,
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[3]\,
      Q => \parallel_dout_reg_n_0_[2]\,
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[4]\,
      Q => \parallel_dout_reg_n_0_[3]\,
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[5]\,
      Q => \parallel_dout_reg_n_0_[4]\,
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[6]\,
      Q => \parallel_dout_reg_n_0_[5]\,
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[7]\,
      Q => \parallel_dout_reg_n_0_[6]\,
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[8]\,
      Q => \parallel_dout_reg_n_0_[7]\,
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[9]\,
      Q => \parallel_dout_reg_n_0_[8]\,
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg_n_0_[10]\,
      Q => \parallel_dout_reg_n_0_[9]\,
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__1_n_0\
    );
\shadow[10]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__1_n_0\
    );
\shadow[11]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__1_n_0\
    );
\shadow[12]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__1_n_0\
    );
\shadow[13]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__1_n_0\
    );
\shadow[14]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__1_n_0\
    );
\shadow[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__0_n_0\
    );
\shadow[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__1_n_0\
    );
\shadow[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__1_n_0\
    );
\shadow[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__1_n_0\
    );
\shadow[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__1_n_0\
    );
\shadow[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__1_n_0\
    );
\shadow[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__1_n_0\
    );
\shadow[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__1_n_0\
    );
\shadow[8]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__1_n_0\
    );
\shadow[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__1_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__0_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__1_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__1_n_0\,
      Q => \^e\(0),
      R => '0'
    );
\slaveRegDo_mux_4[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[0]_i_2_n_0\,
      I1 => Q(0),
      I2 => \slaveRegDo_mux_4_reg[15]\(0),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(0)
    );
\slaveRegDo_mux_4[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[0]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(0),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(0),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(0),
      O => \slaveRegDo_mux_4[0]_i_2_n_0\
    );
\slaveRegDo_mux_4[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[10]_i_2_n_0\,
      I1 => Q(10),
      I2 => \slaveRegDo_mux_4_reg[15]\(10),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(10)
    );
\slaveRegDo_mux_4[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[10]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(10),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(10),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(10),
      O => \slaveRegDo_mux_4[10]_i_2_n_0\
    );
\slaveRegDo_mux_4[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[11]_i_2_n_0\,
      I1 => Q(11),
      I2 => \slaveRegDo_mux_4_reg[15]\(11),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(11)
    );
\slaveRegDo_mux_4[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[11]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(11),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(11),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(11),
      O => \slaveRegDo_mux_4[11]_i_2_n_0\
    );
\slaveRegDo_mux_4[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[12]_i_2_n_0\,
      I1 => Q(12),
      I2 => \slaveRegDo_mux_4_reg[15]\(12),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(12)
    );
\slaveRegDo_mux_4[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[12]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(12),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(12),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(12),
      O => \slaveRegDo_mux_4[12]_i_2_n_0\
    );
\slaveRegDo_mux_4[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[13]_i_2_n_0\,
      I1 => Q(13),
      I2 => \slaveRegDo_mux_4_reg[15]\(13),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(13)
    );
\slaveRegDo_mux_4[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[13]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(13),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(13),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(13),
      O => \slaveRegDo_mux_4[13]_i_2_n_0\
    );
\slaveRegDo_mux_4[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[14]_i_2_n_0\,
      I1 => Q(14),
      I2 => \slaveRegDo_mux_4_reg[15]\(14),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(14)
    );
\slaveRegDo_mux_4[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[14]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(14),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(14),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(14),
      O => \slaveRegDo_mux_4[14]_i_2_n_0\
    );
\slaveRegDo_mux_4[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[15]_i_2_n_0\,
      I1 => Q(15),
      I2 => \slaveRegDo_mux_4_reg[15]\(15),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(15)
    );
\slaveRegDo_mux_4[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[15]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(15),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(15),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(15),
      O => \slaveRegDo_mux_4[15]_i_2_n_0\
    );
\slaveRegDo_mux_4[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[1]_i_2_n_0\,
      I1 => Q(1),
      I2 => \slaveRegDo_mux_4_reg[15]\(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(1)
    );
\slaveRegDo_mux_4[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[1]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(1),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(1),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(1),
      O => \slaveRegDo_mux_4[1]_i_2_n_0\
    );
\slaveRegDo_mux_4[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[2]_i_2_n_0\,
      I1 => Q(2),
      I2 => \slaveRegDo_mux_4_reg[15]\(2),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(2)
    );
\slaveRegDo_mux_4[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[2]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(2),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(2),
      O => \slaveRegDo_mux_4[2]_i_2_n_0\
    );
\slaveRegDo_mux_4[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[3]_i_2_n_0\,
      I1 => Q(3),
      I2 => \slaveRegDo_mux_4_reg[15]\(3),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(3)
    );
\slaveRegDo_mux_4[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[3]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(3),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(3),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(3),
      O => \slaveRegDo_mux_4[3]_i_2_n_0\
    );
\slaveRegDo_mux_4[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[4]_i_2_n_0\,
      I1 => Q(4),
      I2 => \slaveRegDo_mux_4_reg[15]\(4),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(4)
    );
\slaveRegDo_mux_4[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[4]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(4),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(4),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(4),
      O => \slaveRegDo_mux_4[4]_i_2_n_0\
    );
\slaveRegDo_mux_4[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[5]_i_2_n_0\,
      I1 => Q(5),
      I2 => \slaveRegDo_mux_4_reg[15]\(5),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(5)
    );
\slaveRegDo_mux_4[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[5]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(5),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(5),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(5),
      O => \slaveRegDo_mux_4[5]_i_2_n_0\
    );
\slaveRegDo_mux_4[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[6]_i_2_n_0\,
      I1 => Q(6),
      I2 => \slaveRegDo_mux_4_reg[15]\(6),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(6)
    );
\slaveRegDo_mux_4[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[6]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(6),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(6),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(6),
      O => \slaveRegDo_mux_4[6]_i_2_n_0\
    );
\slaveRegDo_mux_4[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[7]_i_2_n_0\,
      I1 => Q(7),
      I2 => \slaveRegDo_mux_4_reg[15]\(7),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(7)
    );
\slaveRegDo_mux_4[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[7]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(7),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(7),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(7),
      O => \slaveRegDo_mux_4[7]_i_2_n_0\
    );
\slaveRegDo_mux_4[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[8]_i_2_n_0\,
      I1 => Q(8),
      I2 => \slaveRegDo_mux_4_reg[15]\(8),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(8)
    );
\slaveRegDo_mux_4[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[8]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(8),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(8),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(8),
      O => \slaveRegDo_mux_4[8]_i_2_n_0\
    );
\slaveRegDo_mux_4[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0CCAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux_4[9]_i_2_n_0\,
      I1 => Q(9),
      I2 => \slaveRegDo_mux_4_reg[15]\(9),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      O => D(9)
    );
\slaveRegDo_mux_4[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => \parallel_dout_reg_n_0_[9]\,
      I1 => \slaveRegDo_mux_4_reg[15]_0\(9),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => \slaveRegDo_mux_4_reg[15]_1\(9),
      I5 => \slaveRegDo_mux_4_reg[15]_2\(9),
      O => \slaveRegDo_mux_4[9]_i_2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized1\ is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \current_state_reg[3]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized1\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized1\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__2_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__2_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shadow[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__2\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__2\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__2\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__2\ : label is "soft_lutpair29";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__2\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \shadow[15]_i_1__1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \shift_en_i_1__2\ : label is "soft_lutpair31";
begin
  E(0) <= \^e\(0);
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__4\(0)
    );
\cnt[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__4\(1)
    );
\cnt[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__2_n_0\
    );
\cnt[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__2_n_0\
    );
\cnt[3]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__4\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__2_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__2_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__2_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__2_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__4\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__2_n_0\
    );
\current_state[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__2_n_0\,
      I4 => \current_state[3]_i_2__2_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__2_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__2_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__2_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__2_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \current_state_reg[3]_0\,
      O => \current_state[3]_i_2__2_n_0\
    );
\current_state[3]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__2_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__2_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__2_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__2_n_0\
    );
\shadow[10]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__2_n_0\
    );
\shadow[11]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__2_n_0\
    );
\shadow[12]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__2_n_0\
    );
\shadow[13]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__2_n_0\
    );
\shadow[14]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__2_n_0\
    );
\shadow[15]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__1_n_0\
    );
\shadow[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__2_n_0\
    );
\shadow[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__2_n_0\
    );
\shadow[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__2_n_0\
    );
\shadow[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__2_n_0\
    );
\shadow[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__2_n_0\
    );
\shadow[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__2_n_0\
    );
\shadow[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__2_n_0\
    );
\shadow[8]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__2_n_0\
    );
\shadow[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__2_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__1_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__2_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__2_n_0\,
      Q => \^e\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized2\ is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \current_state_reg[3]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized2\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized2\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__3_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__3_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__3_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shadow[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__3_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__3\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__3\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__3\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__3\ : label is "soft_lutpair33";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__3\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \shadow[15]_i_1__2\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \shift_en_i_1__3\ : label is "soft_lutpair35";
begin
  E(0) <= \^e\(0);
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__5\(0)
    );
\cnt[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__5\(1)
    );
\cnt[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__3_n_0\
    );
\cnt[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__3_n_0\
    );
\cnt[3]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__5\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__5\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__3_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__5\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__3_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__3_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__3_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__5\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__3_n_0\
    );
\current_state[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__3_n_0\,
      I4 => \current_state[3]_i_2__1_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__1_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__3_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__1_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__3_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(2),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \current_state_reg[3]_0\,
      O => \current_state[3]_i_2__1_n_0\
    );
\current_state[3]_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__3_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__3_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__3_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__3_n_0\
    );
\shadow[10]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__3_n_0\
    );
\shadow[11]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__3_n_0\
    );
\shadow[12]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__3_n_0\
    );
\shadow[13]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__3_n_0\
    );
\shadow[14]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__3_n_0\
    );
\shadow[15]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__2_n_0\
    );
\shadow[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__3_n_0\
    );
\shadow[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__3_n_0\
    );
\shadow[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__3_n_0\
    );
\shadow[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__3_n_0\
    );
\shadow[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__3_n_0\
    );
\shadow[6]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__3_n_0\
    );
\shadow[7]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__3_n_0\
    );
\shadow[8]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__3_n_0\
    );
\shadow[9]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__3_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__2_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__3_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__3_n_0\,
      Q => \^e\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized3\ is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \current_state_reg[3]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized3\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized3\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized3\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__4_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__4_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__4_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shadow[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__3_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__4_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__4\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__4\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__4\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__4\ : label is "soft_lutpair37";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__4\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \shadow[15]_i_1__3\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \shift_en_i_1__4\ : label is "soft_lutpair39";
begin
  E(0) <= \^e\(0);
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__6\(0)
    );
\cnt[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__6\(1)
    );
\cnt[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__4_n_0\
    );
\cnt[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__4_n_0\
    );
\cnt[3]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__6\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__6\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__4_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__6\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__4_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__4_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__4_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__6\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__4_n_0\
    );
\current_state[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__4_n_0\,
      I4 => \current_state[3]_i_2__0_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__0_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__4_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__0_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__4_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \current_state_reg[3]_0\,
      O => \current_state[3]_i_2__0_n_0\
    );
\current_state[3]_i_3__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__4_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__4_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__4_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__4_n_0\
    );
\shadow[10]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__4_n_0\
    );
\shadow[11]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__4_n_0\
    );
\shadow[12]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__4_n_0\
    );
\shadow[13]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__4_n_0\
    );
\shadow[14]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__4_n_0\
    );
\shadow[15]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__3_n_0\
    );
\shadow[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__4_n_0\
    );
\shadow[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__4_n_0\
    );
\shadow[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__4_n_0\
    );
\shadow[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__4_n_0\
    );
\shadow[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__4_n_0\
    );
\shadow[6]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__4_n_0\
    );
\shadow[7]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__4_n_0\
    );
\shadow[8]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__4_n_0\
    );
\shadow[9]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__4_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__3_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__4_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__4_n_0\,
      Q => \^e\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized4\ is
  port (
    serial_dout_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    data_out_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \current_state_reg[3]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized4\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized4\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized4\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__5_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__5_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__5_n_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shadow[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__4_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__5_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__5\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__5\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__5\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__5\ : label is "soft_lutpair41";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \data_out_sel_i_1__5\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \shadow[15]_i_1__4\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \shift_en_i_1__5\ : label is "soft_lutpair43";
begin
  E(0) <= \^e\(0);
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__7\(0)
    );
\cnt[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__7\(1)
    );
\cnt[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__5_n_0\
    );
\cnt[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__5_n_0\
    );
\cnt[3]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__7\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__7\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__5_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__7\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__5_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__5_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__5_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__7\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__5_n_0\
    );
\current_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__5_n_0\,
      I4 => \current_state[3]_i_2_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__5_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__5_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(2),
      I3 => s_daddr_o(3),
      I4 => s_daddr_o(4),
      I5 => \current_state_reg[3]_0\,
      O => \current_state[3]_i_2_n_0\
    );
\current_state[3]_i_3__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__5_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__5_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__5_n_0\,
      Q => data_out_sel_reg_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => mu_config_cs_serial_input(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_0,
      R => '0'
    );
\shadow[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__5_n_0\
    );
\shadow[10]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__5_n_0\
    );
\shadow[11]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__5_n_0\
    );
\shadow[12]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__5_n_0\
    );
\shadow[13]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__5_n_0\
    );
\shadow[14]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__5_n_0\
    );
\shadow[15]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__4_n_0\
    );
\shadow[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__5_n_0\
    );
\shadow[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__5_n_0\
    );
\shadow[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__5_n_0\
    );
\shadow[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__5_n_0\
    );
\shadow[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__5_n_0\
    );
\shadow[6]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__5_n_0\
    );
\shadow[7]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__5_n_0\
    );
\shadow[8]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__5_n_0\
    );
\shadow[9]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__5_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__4_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__5_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__5_n_0\,
      Q => \^e\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized5\ is
  port (
    tc_config_cs_serial_output : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \G_1PIPE_IFACE.s_daddr_r_reg[8]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \parallel_dout_reg[15]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_den_o : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \shadow_reg[15]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized5\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized5\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized5\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^g_1pipe_iface.s_daddr_r_reg[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \cnt[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \cnt[3]_i_1__6_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_3__6_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \data_out_sel_i_1__6_n_0\ : STD_LOGIC;
  signal data_out_sel_reg_n_0 : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__2/i__n_0\ : STD_LOGIC;
  signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal serial_dout_reg_n_0 : STD_LOGIC;
  signal \shadow[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[10]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[11]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[12]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[13]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[14]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[15]_i_1__5_n_0\ : STD_LOGIC;
  signal \shadow[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow[9]_i_1__6_n_0\ : STD_LOGIC;
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal \shift_en_i_1__6_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1__6\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \cnt[2]_i_1__6\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \cnt[3]_i_2__6\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \current_state[3]_i_3__6\ : label is "soft_lutpair45";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of \next_state_inferred__2/i_\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \shift_en_i_1__6\ : label is "soft_lutpair46";
begin
  E(0) <= \^e\(0);
  \G_1PIPE_IFACE.s_daddr_r_reg[8]\ <= \^g_1pipe_iface.s_daddr_r_reg[8]\;
  Q(15 downto 0) <= \^q\(15 downto 0);
\cnt[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__8\(0)
    );
\cnt[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__8\(1)
    );
\cnt[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1__6_n_0\
    );
\cnt[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => \cnt[3]_i_1__6_n_0\
    );
\cnt[3]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__8\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__8\(0),
      Q => cnt_reg(0),
      R => \cnt[3]_i_1__6_n_0\
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__8\(1),
      Q => cnt_reg(1),
      R => \cnt[3]_i_1__6_n_0\
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1__6_n_0\,
      Q => cnt_reg(2),
      R => \cnt[3]_i_1__6_n_0\
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__8\(3),
      Q => cnt_reg(3),
      R => \cnt[3]_i_1__6_n_0\
    );
\current_state[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => \current_state[3]_i_3__6_n_0\,
      I4 => \current_state[3]_i_2__5_n_0\,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__2/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => \current_state[3]_i_2__5_n_0\,
      O => next_state(1)
    );
\current_state[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => \current_state[3]_i_3__6_n_0\,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__2/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => \current_state[3]_i_2__5_n_0\,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => \current_state[3]_i_3__6_n_0\,
      I4 => \next_state_inferred__2/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \current_state[3]_i_4__1_n_0\,
      I1 => s_daddr_o(9),
      I2 => s_den_o,
      I3 => \^g_1pipe_iface.s_daddr_r_reg[8]\,
      I4 => \current_state[3]_i_5__0_n_0\,
      O => \current_state[3]_i_2__5_n_0\
    );
\current_state[3]_i_3__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \current_state[3]_i_3__6_n_0\
    );
\current_state[3]_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => s_daddr_o(11),
      I1 => s_daddr_o(10),
      I2 => s_daddr_o(12),
      O => \current_state[3]_i_4__1_n_0\
    );
\current_state[3]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => s_daddr_o(0),
      I1 => s_daddr_o(4),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(1),
      I4 => s_daddr_o(2),
      O => \current_state[3]_i_5__0_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
\data_out_sel_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \data_out_sel_i_1__6_n_0\
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \data_out_sel_i_1__6_n_0\,
      Q => data_out_sel_reg_n_0,
      R => '0'
    );
\next_state_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__2/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(1),
      Q => \^q\(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(11),
      Q => \^q\(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(12),
      Q => \^q\(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(13),
      Q => \^q\(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(14),
      Q => \^q\(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(15),
      Q => \^q\(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \parallel_dout_reg[15]_0\(0),
      Q => \^q\(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(2),
      Q => \^q\(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(3),
      Q => \^q\(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(4),
      Q => \^q\(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(5),
      Q => \^q\(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(6),
      Q => \^q\(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(7),
      Q => \^q\(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(8),
      Q => \^q\(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(9),
      Q => \^q\(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => \^q\(10),
      Q => \^q\(9),
      R => '0'
    );
serial_data_o: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => serial_dout_reg_n_0,
      I1 => \parallel_dout_reg[15]_0\(0),
      I2 => data_out_sel_reg_n_0,
      O => tc_config_cs_serial_output
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout_reg_n_0,
      R => '0'
    );
\shadow[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => \shadow[0]_i_1__6_n_0\
    );
\shadow[10]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => \shadow[10]_i_1__6_n_0\
    );
\shadow[11]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => \shadow[11]_i_1__6_n_0\
    );
\shadow[12]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => \shadow[12]_i_1__6_n_0\
    );
\shadow[13]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => \shadow[13]_i_1__6_n_0\
    );
\shadow[14]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => \shadow[14]_i_1__6_n_0\
    );
\shadow[15]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shadow[15]_i_1__5_n_0\
    );
\shadow[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => \shadow[1]_i_1__6_n_0\
    );
\shadow[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => \shadow[2]_i_1__6_n_0\
    );
\shadow[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => \shadow[3]_i_1__6_n_0\
    );
\shadow[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => \shadow[4]_i_1__6_n_0\
    );
\shadow[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => \shadow[5]_i_1__6_n_0\
    );
\shadow[6]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => \shadow[6]_i_1__6_n_0\
    );
\shadow[7]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => \shadow[7]_i_1__6_n_0\
    );
\shadow[8]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => \shadow[8]_i_1__6_n_0\
    );
\shadow[9]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => \shadow[9]_i_1__6_n_0\
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[0]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[10]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[11]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[12]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[13]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[14]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[15]_i_1__5_n_0\,
      Q => \shadow_reg_n_0_[15]\,
      R => \shadow_reg[15]_0\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[1]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[2]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[3]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[4]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[5]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[6]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[7]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[8]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow[9]_i_1__6_n_0\,
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
\shift_en_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => \shift_en_i_1__6_n_0\
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shift_en_i_1__6_n_0\,
      Q => \^e\(0),
      R => '0'
    );
\xsdb_reg[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => s_daddr_o(8),
      I1 => s_daddr_o(7),
      I2 => s_daddr_o(5),
      I3 => s_daddr_o(6),
      O => \^g_1pipe_iface.s_daddr_r_reg[8]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized6\ is
  port (
    capture_ctrl_config_serial_output : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \G_1PIPE_IFACE.s_daddr_r_reg[3]\ : out STD_LOGIC;
    \parallel_dout_reg[1]_0\ : out STD_LOGIC;
    \parallel_dout_reg[2]_0\ : out STD_LOGIC;
    \parallel_dout_reg[3]_0\ : out STD_LOGIC;
    \parallel_dout_reg[4]_0\ : out STD_LOGIC;
    \parallel_dout_reg[5]_0\ : out STD_LOGIC;
    \parallel_dout_reg[6]_0\ : out STD_LOGIC;
    \parallel_dout_reg[8]_0\ : out STD_LOGIC;
    \parallel_dout_reg[9]_0\ : out STD_LOGIC;
    \parallel_dout_reg[11]_0\ : out STD_LOGIC;
    \parallel_dout_reg[12]_0\ : out STD_LOGIC;
    \parallel_dout_reg[13]_0\ : out STD_LOGIC;
    \parallel_dout_reg[14]_0\ : out STD_LOGIC;
    \slaveRegDo_ff8_reg[15]\ : out STD_LOGIC;
    \slaveRegDo_ff8_reg[15]_0\ : out STD_LOGIC;
    \slaveRegDo_ff8_reg[15]_1\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_di_r_reg[15]\ : out STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_den_o : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[0]_0\ : in STD_LOGIC;
    slaveRegDo_ff9 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_3_reg[1]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[1]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[1]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[2]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[3]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[5]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[5]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[6]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[14]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \slaveRegDo_mux_3_reg[6]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[10]\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized6\ : entity is "xsdbs_v1_0_2_reg_p2s";
end \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized6\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized6\ is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^g_1pipe_iface.s_di_r_reg[15]\ : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal current_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \current_state[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \current_state[3]_i_7_n_0\ : STD_LOGIC;
  signal data_out_sel_i_1_n_0 : STD_LOGIC;
  signal data_out_sel_reg_n_0 : STD_LOGIC;
  signal in2 : STD_LOGIC;
  signal in4 : STD_LOGIC;
  signal next_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \next_state_inferred__3/i__n_0\ : STD_LOGIC;
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal parallel_dout : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal serial_dout : STD_LOGIC;
  signal shadow : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal \shadow_reg_n_0_[0]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[10]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[11]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[12]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[13]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[14]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[15]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[1]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[2]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[3]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[4]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[5]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[6]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[7]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[8]\ : STD_LOGIC;
  signal \shadow_reg_n_0_[9]\ : STD_LOGIC;
  signal shift_en : STD_LOGIC;
  signal shift_en_i_1_n_0 : STD_LOGIC;
  signal \slaveRegDo_mux_3[0]_i_2_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cnt[1]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \cnt[2]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \cnt[3]_i_2\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \current_state[3]_i_3\ : label is "soft_lutpair50";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \current_state_reg[0]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[1]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[2]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute FSM_ENCODED_STATES of \current_state_reg[3]\ : label is "REG:0010,P2S:0100,IDLE:0001,S2P:1000";
  attribute SOFT_HLUTNM of data_out_sel_i_1 : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \next_state_inferred__3/i_\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \shadow[15]_i_2\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of shift_en_i_1 : label is "soft_lutpair51";
begin
  E(0) <= \^e\(0);
  \G_1PIPE_IFACE.s_di_r_reg[15]\ <= \^g_1pipe_iface.s_di_r_reg[15]\;
\cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cnt_reg(0),
      O => \p_0_in__1\(0)
    );
\cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      O => \p_0_in__1\(1)
    );
\cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      O => \cnt[2]_i_1_n_0\
    );
\cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => current_state(1),
      I1 => current_state(0),
      I2 => current_state(3),
      I3 => current_state(2),
      O => clear
    );
\cnt[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => cnt_reg(0),
      I1 => cnt_reg(1),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => \p_0_in__1\(3)
    );
\cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => cnt_reg(0),
      R => clear
    );
\cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => cnt_reg(1),
      R => clear
    );
\cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \cnt[2]_i_1_n_0\,
      Q => cnt_reg(2),
      R => clear
    );
\cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => cnt_reg(3),
      R => clear
    );
\current_state[0]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55FDFFFF55FD55FD"
    )
        port map (
      I0 => \next_state_inferred__3/i__n_0\,
      I1 => current_state(3),
      I2 => current_state(2),
      I3 => in4,
      I4 => in2,
      I5 => current_state(0),
      O => next_state(0)
    );
\current_state[1]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \next_state_inferred__3/i__n_0\,
      I1 => current_state(0),
      I2 => s_dwe_o,
      I3 => in2,
      O => next_state(1)
    );
\current_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F800"
    )
        port map (
      I0 => in4,
      I1 => current_state(2),
      I2 => current_state(1),
      I3 => \next_state_inferred__3/i__n_0\,
      O => next_state(2)
    );
\current_state[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF20000020200000"
    )
        port map (
      I0 => in2,
      I1 => s_dwe_o,
      I2 => current_state(0),
      I3 => in4,
      I4 => \next_state_inferred__3/i__n_0\,
      I5 => current_state(3),
      O => next_state(3)
    );
\current_state[3]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \current_state[3]_i_4__0_n_0\,
      I1 => s_daddr_o(0),
      I2 => s_daddr_o(11),
      I3 => s_daddr_o(8),
      I4 => s_daddr_o(5),
      I5 => \current_state[3]_i_5__1_n_0\,
      O => in2
    );
\current_state[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => cnt_reg(1),
      I1 => cnt_reg(0),
      I2 => cnt_reg(2),
      I3 => cnt_reg(3),
      O => in4
    );
\current_state[3]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => s_daddr_o(1),
      I1 => s_daddr_o(2),
      O => \current_state[3]_i_4__0_n_0\
    );
\current_state[3]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \current_state[3]_i_6_n_0\,
      I1 => s_daddr_o(9),
      I2 => s_daddr_o(10),
      I3 => s_den_o,
      I4 => s_daddr_o(12),
      I5 => \current_state[3]_i_7_n_0\,
      O => \current_state[3]_i_5__1_n_0\
    );
\current_state[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => s_daddr_o(7),
      I1 => s_daddr_o(6),
      O => \current_state[3]_i_6_n_0\
    );
\current_state[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(3),
      O => \current_state[3]_i_7_n_0\
    );
\current_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(0),
      Q => current_state(0),
      R => '0'
    );
\current_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(1),
      Q => current_state(1),
      R => '0'
    );
\current_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(2),
      Q => current_state(2),
      R => '0'
    );
\current_state_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => next_state(3),
      Q => current_state(3),
      R => '0'
    );
data_out_sel_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => current_state(3),
      I1 => current_state(2),
      I2 => current_state(0),
      I3 => current_state(1),
      O => data_out_sel_i_1_n_0
    );
data_out_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => data_out_sel_i_1_n_0,
      Q => data_out_sel_reg_n_0,
      R => '0'
    );
\next_state_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => current_state(0),
      I1 => current_state(1),
      I2 => current_state(2),
      I3 => current_state(3),
      O => \next_state_inferred__3/i__n_0\
    );
\parallel_dout_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(1),
      Q => parallel_dout(0),
      R => '0'
    );
\parallel_dout_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(11),
      Q => parallel_dout(10),
      R => '0'
    );
\parallel_dout_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(12),
      Q => parallel_dout(11),
      R => '0'
    );
\parallel_dout_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(13),
      Q => parallel_dout(12),
      R => '0'
    );
\parallel_dout_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(14),
      Q => parallel_dout(13),
      R => '0'
    );
\parallel_dout_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(15),
      Q => parallel_dout(14),
      R => '0'
    );
\parallel_dout_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => D(0),
      Q => parallel_dout(15),
      R => '0'
    );
\parallel_dout_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(2),
      Q => parallel_dout(1),
      R => '0'
    );
\parallel_dout_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(3),
      Q => parallel_dout(2),
      R => '0'
    );
\parallel_dout_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(4),
      Q => parallel_dout(3),
      R => '0'
    );
\parallel_dout_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(5),
      Q => parallel_dout(4),
      R => '0'
    );
\parallel_dout_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(6),
      Q => parallel_dout(5),
      R => '0'
    );
\parallel_dout_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(7),
      Q => parallel_dout(6),
      R => '0'
    );
\parallel_dout_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(8),
      Q => parallel_dout(7),
      R => '0'
    );
\parallel_dout_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(9),
      Q => parallel_dout(8),
      R => '0'
    );
\parallel_dout_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => \^e\(0),
      D => parallel_dout(10),
      Q => parallel_dout(9),
      R => '0'
    );
serial_data_o: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => serial_dout,
      I1 => D(0),
      I2 => data_out_sel_reg_n_0,
      O => capture_ctrl_config_serial_output
    );
serial_dout_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => \shadow_reg_n_0_[0]\,
      Q => serial_dout,
      R => '0'
    );
\shadow[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[1]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(0),
      O => shadow(0)
    );
\shadow[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[11]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(10),
      O => shadow(10)
    );
\shadow[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[12]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(11),
      O => shadow(11)
    );
\shadow[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[13]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(12),
      O => shadow(12)
    );
\shadow[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[14]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(13),
      O => shadow(13)
    );
\shadow[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[15]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(14),
      O => shadow(14)
    );
\shadow[15]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_di_o(15),
      O => \^g_1pipe_iface.s_di_r_reg[15]\
    );
\shadow[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => shift_en
    );
\shadow[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[2]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(1),
      O => shadow(1)
    );
\shadow[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[3]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(2),
      O => shadow(2)
    );
\shadow[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[4]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(3),
      O => shadow(3)
    );
\shadow[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[5]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(4),
      O => shadow(4)
    );
\shadow[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[6]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(5),
      O => shadow(5)
    );
\shadow[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[7]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(6),
      O => shadow(6)
    );
\shadow[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[8]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(7),
      O => shadow(7)
    );
\shadow[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[9]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(8),
      O => shadow(8)
    );
\shadow[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002000C00020000"
    )
        port map (
      I0 => \shadow_reg_n_0_[10]\,
      I1 => current_state(1),
      I2 => current_state(0),
      I3 => current_state(3),
      I4 => current_state(2),
      I5 => s_di_o(9),
      O => shadow(9)
    );
\shadow_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(0),
      Q => \shadow_reg_n_0_[0]\,
      R => '0'
    );
\shadow_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(10),
      Q => \shadow_reg_n_0_[10]\,
      R => '0'
    );
\shadow_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(11),
      Q => \shadow_reg_n_0_[11]\,
      R => '0'
    );
\shadow_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(12),
      Q => \shadow_reg_n_0_[12]\,
      R => '0'
    );
\shadow_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(13),
      Q => \shadow_reg_n_0_[13]\,
      R => '0'
    );
\shadow_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(14),
      Q => \shadow_reg_n_0_[14]\,
      R => '0'
    );
\shadow_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shift_en,
      Q => \shadow_reg_n_0_[15]\,
      R => \^g_1pipe_iface.s_di_r_reg[15]\
    );
\shadow_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(1),
      Q => \shadow_reg_n_0_[1]\,
      R => '0'
    );
\shadow_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(2),
      Q => \shadow_reg_n_0_[2]\,
      R => '0'
    );
\shadow_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(3),
      Q => \shadow_reg_n_0_[3]\,
      R => '0'
    );
\shadow_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(4),
      Q => \shadow_reg_n_0_[4]\,
      R => '0'
    );
\shadow_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(5),
      Q => \shadow_reg_n_0_[5]\,
      R => '0'
    );
\shadow_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(6),
      Q => \shadow_reg_n_0_[6]\,
      R => '0'
    );
\shadow_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(7),
      Q => \shadow_reg_n_0_[7]\,
      R => '0'
    );
\shadow_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(8),
      Q => \shadow_reg_n_0_[8]\,
      R => '0'
    );
\shadow_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => s_dclk_o,
      CE => '1',
      D => shadow(9),
      Q => \shadow_reg_n_0_[9]\,
      R => '0'
    );
shift_en_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => current_state(2),
      I1 => current_state(3),
      I2 => current_state(0),
      I3 => current_state(1),
      O => shift_en_i_1_n_0
    );
shift_en_reg: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => '1',
      D => shift_en_i_1_n_0,
      Q => \^e\(0),
      R => '0'
    );
\slaveRegDo_mux_3[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8FFFFF8F8FCF3F8F"
    )
        port map (
      I0 => parallel_dout(0),
      I1 => s_daddr_o(1),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(0),
      I5 => slaveRegDo_ff9(0),
      O => \slaveRegDo_mux_3[0]_i_2_n_0\
    );
\slaveRegDo_mux_3[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000A00000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[10]\,
      I1 => parallel_dout(10),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_ff8_reg[15]\
    );
\slaveRegDo_mux_3[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(11),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(3),
      I4 => Q(3),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[11]_0\
    );
\slaveRegDo_mux_3[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(12),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(4),
      I4 => Q(4),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[12]_0\
    );
\slaveRegDo_mux_3[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(13),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(5),
      I4 => Q(5),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[13]_0\
    );
\slaveRegDo_mux_3[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(14),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(6),
      I4 => Q(6),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[14]_0\
    );
\slaveRegDo_mux_3[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000A00000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[10]\,
      I1 => parallel_dout(15),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_ff8_reg[15]_1\
    );
\slaveRegDo_mux_3[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]\,
      I1 => \slaveRegDo_mux_3_reg[1]_0\,
      I2 => parallel_dout(1),
      I3 => \slaveRegDo_mux_3_reg[1]_1\,
      O => \parallel_dout_reg[1]_0\
    );
\slaveRegDo_mux_3[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]\,
      I1 => \slaveRegDo_mux_3_reg[1]_0\,
      I2 => parallel_dout(2),
      I3 => \slaveRegDo_mux_3_reg[2]\,
      O => \parallel_dout_reg[2]_0\
    );
\slaveRegDo_mux_3[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]\,
      I1 => \slaveRegDo_mux_3_reg[1]_0\,
      I2 => parallel_dout(3),
      I3 => \slaveRegDo_mux_3_reg[3]\,
      O => \parallel_dout_reg[3]_0\
    );
\slaveRegDo_mux_3[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]\,
      I1 => \slaveRegDo_mux_3_reg[1]_0\,
      I2 => parallel_dout(4),
      I3 => \slaveRegDo_mux_3_reg[4]\,
      O => \parallel_dout_reg[4]_0\
    );
\slaveRegDo_mux_3[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF981000009810"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[5]\,
      I1 => \slaveRegDo_mux_3_reg[5]_0\,
      I2 => parallel_dout(5),
      I3 => slaveRegDo_ff9(0),
      I4 => \slaveRegDo_mux_3_reg[0]\,
      I5 => \slaveRegDo_mux_3_reg[5]_1\,
      O => \parallel_dout_reg[5]_0\
    );
\slaveRegDo_mux_3[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(6),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(0),
      I4 => Q(0),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[6]_0\
    );
\slaveRegDo_mux_3[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000A00000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[10]\,
      I1 => parallel_dout(7),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(2),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_ff8_reg[15]_0\
    );
\slaveRegDo_mux_3[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(8),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(1),
      I4 => Q(1),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[8]_0\
    );
\slaveRegDo_mux_3[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[1]_0\,
      I1 => parallel_dout(9),
      I2 => \slaveRegDo_mux_3_reg[6]\,
      I3 => \slaveRegDo_mux_3_reg[14]\(2),
      I4 => Q(2),
      I5 => \slaveRegDo_mux_3_reg[6]_0\,
      O => \parallel_dout_reg[9]_0\
    );
\slaveRegDo_mux_3_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \slaveRegDo_mux_3[0]_i_2_n_0\,
      I1 => \slaveRegDo_mux_3_reg[0]_0\,
      O => \G_1PIPE_IFACE.s_daddr_r_reg[3]\,
      S => \slaveRegDo_mux_3_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat is
  port (
    \xsdb_reg_reg[1]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[2]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[3]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \slaveRegDo_mux_3_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[4]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    slaveRegDo_ffa : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_3_reg[4]_2\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \xsdb_reg_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat is
  signal \xsdb_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[4]\ : STD_LOGIC;
begin
\slaveRegDo_mux_3[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D591C48000000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[4]\,
      I1 => \slaveRegDo_mux_3_reg[4]_0\,
      I2 => \xsdb_reg_reg_n_0_[1]\,
      I3 => \slaveRegDo_mux_3_reg[4]_1\(0),
      I4 => slaveRegDo_ffa(0),
      I5 => \slaveRegDo_mux_3_reg[4]_2\,
      O => \xsdb_reg_reg[1]_0\
    );
\slaveRegDo_mux_3[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D591C48000000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[4]\,
      I1 => \slaveRegDo_mux_3_reg[4]_0\,
      I2 => \xsdb_reg_reg_n_0_[2]\,
      I3 => \slaveRegDo_mux_3_reg[4]_1\(1),
      I4 => slaveRegDo_ffa(0),
      I5 => \slaveRegDo_mux_3_reg[4]_2\,
      O => \xsdb_reg_reg[2]_0\
    );
\slaveRegDo_mux_3[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D591C48000000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[4]\,
      I1 => \slaveRegDo_mux_3_reg[4]_0\,
      I2 => \xsdb_reg_reg_n_0_[3]\,
      I3 => \slaveRegDo_mux_3_reg[4]_1\(2),
      I4 => slaveRegDo_ffa(0),
      I5 => \slaveRegDo_mux_3_reg[4]_2\,
      O => \xsdb_reg_reg[3]_0\
    );
\slaveRegDo_mux_3[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D591C48000000000"
    )
        port map (
      I0 => \slaveRegDo_mux_3_reg[4]\,
      I1 => \slaveRegDo_mux_3_reg[4]_0\,
      I2 => \xsdb_reg_reg_n_0_[4]\,
      I3 => \slaveRegDo_mux_3_reg[4]_1\(3),
      I4 => slaveRegDo_ffa(0),
      I5 => \slaveRegDo_mux_3_reg[4]_2\,
      O => \xsdb_reg_reg[4]_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(0),
      Q => Q(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(10),
      Q => Q(6),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(11),
      Q => Q(7),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(12),
      Q => Q(8),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(13),
      Q => Q(9),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(14),
      Q => Q(10),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(15),
      Q => Q(11),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(1),
      Q => \xsdb_reg_reg_n_0_[1]\,
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(2),
      Q => \xsdb_reg_reg_n_0_[2]\,
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(3),
      Q => \xsdb_reg_reg_n_0_[3]\,
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(4),
      Q => \xsdb_reg_reg_n_0_[4]\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(5),
      Q => Q(1),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(6),
      Q => Q(2),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(7),
      Q => Q(3),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(8),
      Q => Q(4),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => \xsdb_reg_reg[15]_0\(9),
      Q => Q(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat_30 is
  port (
    \xsdb_reg_reg[4]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[8]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \slaveRegDo_mux_0[9]_i_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_den_o : in STD_LOGIC;
    \xsdb_reg_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat_30 : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat_30;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat_30 is
  signal \xsdb_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[9]\ : STD_LOGIC;
begin
\slaveRegDo_mux_0[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000A0C0000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[0]\,
      I1 => Q(0),
      I2 => s_daddr_o(1),
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(3),
      I5 => s_daddr_o(2),
      O => \xsdb_reg_reg[0]_0\
    );
\slaveRegDo_mux_0[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C0000A00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[4]\,
      I1 => \slaveRegDo_mux_0[9]_i_3\(0),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(0),
      I5 => s_daddr_o(1),
      O => \xsdb_reg_reg[4]_0\
    );
\slaveRegDo_mux_0[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C0000A00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[5]\,
      I1 => \slaveRegDo_mux_0[9]_i_3\(1),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(0),
      I5 => s_daddr_o(1),
      O => \xsdb_reg_reg[5]_0\
    );
\slaveRegDo_mux_0[8]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C0000A00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[8]\,
      I1 => \slaveRegDo_mux_0[9]_i_3\(2),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(0),
      I5 => s_daddr_o(1),
      O => \xsdb_reg_reg[8]_0\
    );
\slaveRegDo_mux_0[9]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C0000A00000"
    )
        port map (
      I0 => \xsdb_reg_reg_n_0_[9]\,
      I1 => \slaveRegDo_mux_0[9]_i_3\(3),
      I2 => s_daddr_o(3),
      I3 => s_daddr_o(2),
      I4 => s_daddr_o(0),
      I5 => s_daddr_o(1),
      O => \xsdb_reg_reg[9]_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(0),
      Q => \xsdb_reg_reg_n_0_[0]\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(1),
      Q => \xsdb_reg_reg[7]_0\(0),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(2),
      Q => \xsdb_reg_reg[7]_0\(1),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(3),
      Q => \xsdb_reg_reg[7]_0\(2),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(4),
      Q => \xsdb_reg_reg_n_0_[4]\,
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(5),
      Q => \xsdb_reg_reg_n_0_[5]\,
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(6),
      Q => \xsdb_reg_reg[7]_0\(3),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(7),
      Q => \xsdb_reg_reg[7]_0\(4),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(8),
      Q => \xsdb_reg_reg_n_0_[8]\,
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[9]_1\(9),
      Q => \xsdb_reg_reg_n_0_[9]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat_31 is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_2_reg[1]\ : in STD_LOGIC;
    s_do_o : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_2_reg[1]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    slaveRegDo_mux_211_in : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_den_o : in STD_LOGIC;
    \xsdb_reg_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat_31 : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat_31;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat_31 is
  signal \slaveRegDo_mux_2[0]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[1]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[1]\ : STD_LOGIC;
begin
\slaveRegDo_mux_2[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_2_reg[1]\,
      I1 => s_do_o(0),
      I2 => \slaveRegDo_mux_2[0]_i_2_n_0\,
      I3 => \slaveRegDo_mux_2_reg[1]_0\,
      I4 => \slaveRegDo_mux_2_reg[1]_1\(0),
      I5 => slaveRegDo_mux_211_in,
      O => D(0)
    );
\slaveRegDo_mux_2[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(2),
      I2 => \xsdb_reg_reg_n_0_[0]\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_2[0]_i_2_n_0\
    );
\slaveRegDo_mux_2[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_2_reg[1]\,
      I1 => s_do_o(1),
      I2 => \slaveRegDo_mux_2[1]_i_2_n_0\,
      I3 => \slaveRegDo_mux_2_reg[1]_0\,
      I4 => \slaveRegDo_mux_2_reg[1]_1\(1),
      I5 => slaveRegDo_mux_211_in,
      O => D(1)
    );
\slaveRegDo_mux_2[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(2),
      I2 => \xsdb_reg_reg_n_0_[1]\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_2[1]_i_2_n_0\
    );
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[1]_0\(0),
      Q => \xsdb_reg_reg_n_0_[0]\,
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \xsdb_reg_reg[1]_0\(1),
      Q => \xsdb_reg_reg_n_0_[1]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat_32 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_den_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[3]\ : in STD_LOGIC;
    s_do_o : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_2_reg[3]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    slaveRegDo_mux_211_in : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat_32 : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat_32;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat_32 is
  signal \slaveRegDo_mux_2[3]_i_2_n_0\ : STD_LOGIC;
  signal \xsdb_reg_reg_n_0_[3]\ : STD_LOGIC;
begin
\slaveRegDo_mux_2[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \slaveRegDo_mux_2_reg[3]\,
      I1 => s_do_o(0),
      I2 => \slaveRegDo_mux_2[3]_i_2_n_0\,
      I3 => \slaveRegDo_mux_2_reg[3]_0\,
      I4 => \slaveRegDo_mux_2_reg[3]_1\(0),
      I5 => slaveRegDo_mux_211_in,
      O => D(0)
    );
\slaveRegDo_mux_2[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => s_daddr_o(4),
      I1 => s_daddr_o(2),
      I2 => \xsdb_reg_reg_n_0_[3]\,
      I3 => s_daddr_o(0),
      I4 => s_daddr_o(1),
      I5 => s_daddr_o(3),
      O => \slaveRegDo_mux_2[3]_i_2_n_0\
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => \out\,
      Q => \xsdb_reg_reg_n_0_[3]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat_38 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    s_den_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat_38 : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat_38;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat_38 is
begin
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => s_den_o,
      D => D(4),
      Q => Q(4),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stat_46 is
  port (
    s_do_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_den_i : in STD_LOGIC;
    din_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stat_46 : entity is "xsdbs_v1_0_2_reg_stat";
end ila_full_aurora_xsdbs_v1_0_2_reg_stat_46;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stat_46 is
begin
\xsdb_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(0),
      Q => s_do_o(0),
      R => '0'
    );
\xsdb_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(10),
      Q => s_do_o(10),
      R => '0'
    );
\xsdb_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(11),
      Q => s_do_o(11),
      R => '0'
    );
\xsdb_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(12),
      Q => s_do_o(12),
      R => '0'
    );
\xsdb_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(13),
      Q => s_do_o(13),
      R => '0'
    );
\xsdb_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(14),
      Q => s_do_o(14),
      R => '0'
    );
\xsdb_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(15),
      Q => s_do_o(15),
      R => '0'
    );
\xsdb_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(1),
      Q => s_do_o(1),
      R => '0'
    );
\xsdb_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(2),
      Q => s_do_o(2),
      R => '0'
    );
\xsdb_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(3),
      Q => s_do_o(3),
      R => '0'
    );
\xsdb_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(4),
      Q => s_do_o(4),
      R => '0'
    );
\xsdb_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(5),
      Q => s_do_o(5),
      R => '0'
    );
\xsdb_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(6),
      Q => s_do_o(6),
      R => '0'
    );
\xsdb_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(7),
      Q => s_do_o(7),
      R => '0'
    );
\xsdb_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(8),
      Q => s_do_o(8),
      R => '0'
    );
\xsdb_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_i,
      CE => s_den_i,
      D => din_i(9),
      Q => s_do_o(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_xsdbs is
  port (
    s_rst_o : out STD_LOGIC;
    s_dclk_o : out STD_LOGIC;
    s_den_o : out STD_LOGIC;
    s_dwe_o : out STD_LOGIC;
    s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
    s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
    sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
    s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
    sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
    s_drdy_i : in STD_LOGIC
  );
  attribute C_BUILD_REVISION : integer;
  attribute C_BUILD_REVISION of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 0;
  attribute C_CORE_INFO1 : integer;
  attribute C_CORE_INFO1 of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 0;
  attribute C_CORE_INFO2 : integer;
  attribute C_CORE_INFO2 of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 0;
  attribute C_CORE_MAJOR_VER : integer;
  attribute C_CORE_MAJOR_VER of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 6;
  attribute C_CORE_MINOR_VER : integer;
  attribute C_CORE_MINOR_VER of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 2;
  attribute C_CORE_TYPE : integer;
  attribute C_CORE_TYPE of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 1;
  attribute C_CSE_DRV_VER : integer;
  attribute C_CSE_DRV_VER of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 2;
  attribute C_MAJOR_VERSION : integer;
  attribute C_MAJOR_VERSION of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 2019;
  attribute C_MINOR_VERSION : integer;
  attribute C_MINOR_VERSION of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 2;
  attribute C_NEXT_SLAVE : integer;
  attribute C_NEXT_SLAVE of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 0;
  attribute C_PIPE_IFACE : integer;
  attribute C_PIPE_IFACE of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 1;
  attribute C_USE_TEST_REG : integer;
  attribute C_USE_TEST_REG of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is "virtex7";
  attribute C_XSDB_SLAVE_TYPE : integer;
  attribute C_XSDB_SLAVE_TYPE of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is 17;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
  attribute dont_touch : string;
  attribute dont_touch of ila_full_aurora_xsdbs_v1_0_2_xsdbs : entity is "true";
end ila_full_aurora_xsdbs_v1_0_2_xsdbs;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_xsdbs is
  signal \G_1PIPE_IFACE.s_den_r0\ : STD_LOGIC;
  signal \G_1PIPE_IFACE.s_den_r_i_2_n_0\ : STD_LOGIC;
  signal \G_1PIPE_IFACE.s_drdy_r_i_1_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal reg_do : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \reg_do[0]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[0]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[0]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[0]_i_5_n_0\ : STD_LOGIC;
  signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[10]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[10]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[10]_i_5_n_0\ : STD_LOGIC;
  signal \reg_do[11]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[11]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[12]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[12]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[13]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[13]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[14]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[14]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[15]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[15]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[15]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[15]_i_5_n_0\ : STD_LOGIC;
  signal \reg_do[15]_i_6_n_0\ : STD_LOGIC;
  signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[1]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[1]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[2]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[2]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[3]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[3]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_5_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_6_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_7_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_8_n_0\ : STD_LOGIC;
  signal \reg_do[4]_i_9_n_0\ : STD_LOGIC;
  signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[5]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[5]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[6]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[6]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[6]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[7]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[7]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[7]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[8]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[8]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do[8]_i_5_n_0\ : STD_LOGIC;
  signal \reg_do[9]_i_2_n_0\ : STD_LOGIC;
  signal \reg_do[9]_i_3_n_0\ : STD_LOGIC;
  signal \reg_do[9]_i_4_n_0\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
  signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
  signal reg_drdy : STD_LOGIC;
  signal reg_drdy0 : STD_LOGIC;
  signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal reg_test0 : STD_LOGIC;
  signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
  signal uuid_stamp : STD_LOGIC_VECTOR ( 127 downto 0 );
  attribute DONT_TOUCH_boolean : boolean;
  attribute DONT_TOUCH_boolean of uuid_stamp : signal is std.standard.true;
  attribute UUID : string;
  attribute UUID of uuid_stamp : signal is "1";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_den_r_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[0]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[10]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[11]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[12]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[13]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[14]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[15]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[1]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[2]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[3]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[4]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[5]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[6]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[7]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[8]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \G_1PIPE_IFACE.s_do_r[9]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \reg_do[10]_i_5\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \reg_do[15]_i_6\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \reg_do[4]_i_6\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \reg_do[4]_i_8\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \reg_do[4]_i_9\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \reg_do[5]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of reg_drdy_i_1 : label is "soft_lutpair10";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \uuid_stamp_reg[0]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[0]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[100]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[100]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[100]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[101]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[101]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[101]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[102]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[102]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[102]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[103]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[103]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[103]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[104]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[104]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[104]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[105]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[105]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[105]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[106]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[106]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[106]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[107]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[107]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[107]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[108]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[108]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[108]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[109]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[109]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[109]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[10]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[10]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[10]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[110]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[110]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[110]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[111]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[111]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[111]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[112]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[112]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[112]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[113]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[113]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[113]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[114]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[114]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[114]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[115]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[115]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[115]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[116]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[116]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[116]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[117]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[117]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[117]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[118]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[118]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[118]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[119]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[119]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[119]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[11]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[11]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[11]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[120]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[120]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[120]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[121]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[121]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[121]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[122]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[122]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[122]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[123]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[123]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[123]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[124]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[124]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[124]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[125]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[125]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[125]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[126]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[126]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[126]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[127]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[127]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[127]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[12]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[12]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[12]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[13]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[13]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[13]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[14]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[14]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[14]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[15]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[15]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[15]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[16]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[16]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[16]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[17]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[17]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[17]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[18]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[18]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[18]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[19]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[19]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[19]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[1]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[1]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[1]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[20]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[20]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[20]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[21]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[21]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[21]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[22]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[22]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[22]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[23]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[23]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[23]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[24]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[24]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[24]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[25]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[25]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[25]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[26]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[26]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[26]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[27]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[27]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[27]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[28]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[28]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[28]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[29]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[29]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[29]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[2]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[2]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[2]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[30]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[30]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[30]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[31]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[31]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[31]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[32]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[32]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[32]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[33]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[33]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[33]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[34]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[34]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[34]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[35]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[35]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[35]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[36]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[36]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[36]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[37]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[37]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[37]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[38]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[38]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[38]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[39]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[39]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[39]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[3]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[3]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[3]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[40]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[40]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[40]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[41]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[41]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[41]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[42]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[42]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[42]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[43]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[43]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[43]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[44]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[44]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[44]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[45]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[45]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[45]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[46]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[46]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[46]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[47]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[47]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[47]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[48]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[48]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[48]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[49]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[49]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[49]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[4]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[4]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[4]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[50]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[50]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[50]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[51]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[51]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[51]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[52]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[52]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[52]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[53]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[53]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[53]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[54]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[54]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[54]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[55]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[55]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[55]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[56]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[56]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[56]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[57]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[57]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[57]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[58]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[58]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[58]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[59]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[59]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[59]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[5]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[5]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[5]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[60]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[60]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[60]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[61]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[61]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[61]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[62]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[62]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[62]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[63]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[63]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[63]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[64]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[64]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[64]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[65]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[65]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[65]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[66]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[66]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[66]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[67]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[67]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[67]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[68]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[68]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[68]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[69]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[69]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[69]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[6]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[6]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[6]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[70]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[70]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[70]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[71]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[71]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[71]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[72]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[72]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[72]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[73]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[73]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[73]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[74]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[74]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[74]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[75]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[75]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[75]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[76]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[76]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[76]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[77]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[77]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[77]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[78]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[78]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[78]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[79]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[79]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[79]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[7]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[7]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[7]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[80]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[80]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[80]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[81]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[81]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[81]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[82]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[82]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[82]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[83]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[83]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[83]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[84]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[84]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[84]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[85]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[85]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[85]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[86]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[86]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[86]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[87]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[87]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[87]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[88]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[88]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[88]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[89]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[89]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[89]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[8]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[8]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[8]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[90]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[90]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[90]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[91]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[91]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[91]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[92]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[92]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[92]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[93]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[93]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[93]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[94]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[94]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[94]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[95]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[95]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[95]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[96]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[96]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[96]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[97]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[97]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[97]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[98]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[98]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[98]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[99]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[99]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[99]\ : label is "1";
  attribute DONT_TOUCH_boolean of \uuid_stamp_reg[9]\ : label is std.standard.true;
  attribute KEEP of \uuid_stamp_reg[9]\ : label is "yes";
  attribute UUID of \uuid_stamp_reg[9]\ : label is "1";
begin
  \^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
  s_dclk_o <= \^sl_iport_i\(1);
  s_rst_o <= \^sl_iport_i\(0);
\G_1PIPE_IFACE.s_daddr_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(4),
      Q => s_daddr_o(0),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(14),
      Q => s_daddr_o(10),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(15),
      Q => s_daddr_o(11),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(16),
      Q => s_daddr_o(12),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(17),
      Q => s_daddr_o(13),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(18),
      Q => s_daddr_o(14),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(19),
      Q => s_daddr_o(15),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(20),
      Q => s_daddr_o(16),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(5),
      Q => s_daddr_o(1),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(6),
      Q => s_daddr_o(2),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(7),
      Q => s_daddr_o(3),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(8),
      Q => s_daddr_o(4),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(9),
      Q => s_daddr_o(5),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(10),
      Q => s_daddr_o(6),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(11),
      Q => s_daddr_o(7),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(12),
      Q => s_daddr_o(8),
      R => '0'
    );
\G_1PIPE_IFACE.s_daddr_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(13),
      Q => s_daddr_o(9),
      R => '0'
    );
\G_1PIPE_IFACE.s_den_r_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0000"
    )
        port map (
      I0 => \G_1PIPE_IFACE.s_den_r_i_2_n_0\,
      I1 => \^sl_iport_i\(12),
      I2 => \^sl_iport_i\(13),
      I3 => \^sl_iport_i\(14),
      I4 => \^sl_iport_i\(2),
      O => \G_1PIPE_IFACE.s_den_r0\
    );
\G_1PIPE_IFACE.s_den_r_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^sl_iport_i\(15),
      I1 => \^sl_iport_i\(16),
      I2 => \^sl_iport_i\(17),
      I3 => \^sl_iport_i\(18),
      I4 => \^sl_iport_i\(20),
      I5 => \^sl_iport_i\(19),
      O => \G_1PIPE_IFACE.s_den_r_i_2_n_0\
    );
\G_1PIPE_IFACE.s_den_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \G_1PIPE_IFACE.s_den_r0\,
      Q => s_den_o,
      R => \^sl_iport_i\(0)
    );
\G_1PIPE_IFACE.s_di_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(21),
      Q => s_di_o(0),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(31),
      Q => s_di_o(10),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(32),
      Q => s_di_o(11),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(33),
      Q => s_di_o(12),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(34),
      Q => s_di_o(13),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(35),
      Q => s_di_o(14),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(36),
      Q => s_di_o(15),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(22),
      Q => s_di_o(1),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(23),
      Q => s_di_o(2),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(24),
      Q => s_di_o(3),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(25),
      Q => s_di_o(4),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(26),
      Q => s_di_o(5),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(27),
      Q => s_di_o(6),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(28),
      Q => s_di_o(7),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(29),
      Q => s_di_o(8),
      R => '0'
    );
\G_1PIPE_IFACE.s_di_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(30),
      Q => s_di_o(9),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[0]\,
      I1 => s_do_i(0),
      I2 => reg_drdy,
      O => p_0_in(0)
    );
\G_1PIPE_IFACE.s_do_r[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[10]\,
      I1 => s_do_i(10),
      I2 => reg_drdy,
      O => p_0_in(10)
    );
\G_1PIPE_IFACE.s_do_r[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[11]\,
      I1 => s_do_i(11),
      I2 => reg_drdy,
      O => p_0_in(11)
    );
\G_1PIPE_IFACE.s_do_r[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[12]\,
      I1 => s_do_i(12),
      I2 => reg_drdy,
      O => p_0_in(12)
    );
\G_1PIPE_IFACE.s_do_r[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[13]\,
      I1 => s_do_i(13),
      I2 => reg_drdy,
      O => p_0_in(13)
    );
\G_1PIPE_IFACE.s_do_r[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[14]\,
      I1 => s_do_i(14),
      I2 => reg_drdy,
      O => p_0_in(14)
    );
\G_1PIPE_IFACE.s_do_r[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[15]\,
      I1 => s_do_i(15),
      I2 => reg_drdy,
      O => p_0_in(15)
    );
\G_1PIPE_IFACE.s_do_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[1]\,
      I1 => s_do_i(1),
      I2 => reg_drdy,
      O => p_0_in(1)
    );
\G_1PIPE_IFACE.s_do_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[2]\,
      I1 => s_do_i(2),
      I2 => reg_drdy,
      O => p_0_in(2)
    );
\G_1PIPE_IFACE.s_do_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[3]\,
      I1 => s_do_i(3),
      I2 => reg_drdy,
      O => p_0_in(3)
    );
\G_1PIPE_IFACE.s_do_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[4]\,
      I1 => s_do_i(4),
      I2 => reg_drdy,
      O => p_0_in(4)
    );
\G_1PIPE_IFACE.s_do_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[5]\,
      I1 => s_do_i(5),
      I2 => reg_drdy,
      O => p_0_in(5)
    );
\G_1PIPE_IFACE.s_do_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[6]\,
      I1 => s_do_i(6),
      I2 => reg_drdy,
      O => p_0_in(6)
    );
\G_1PIPE_IFACE.s_do_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[7]\,
      I1 => s_do_i(7),
      I2 => reg_drdy,
      O => p_0_in(7)
    );
\G_1PIPE_IFACE.s_do_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[8]\,
      I1 => s_do_i(8),
      I2 => reg_drdy,
      O => p_0_in(8)
    );
\G_1PIPE_IFACE.s_do_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \reg_do_reg_n_0_[9]\,
      I1 => s_do_i(9),
      I2 => reg_drdy,
      O => p_0_in(9)
    );
\G_1PIPE_IFACE.s_do_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(0),
      Q => sl_oport_o(1),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(10),
      Q => sl_oport_o(11),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(11),
      Q => sl_oport_o(12),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(12),
      Q => sl_oport_o(13),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(13),
      Q => sl_oport_o(14),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(14),
      Q => sl_oport_o(15),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(15),
      Q => sl_oport_o(16),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(1),
      Q => sl_oport_o(2),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(2),
      Q => sl_oport_o(3),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(3),
      Q => sl_oport_o(4),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(4),
      Q => sl_oport_o(5),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(5),
      Q => sl_oport_o(6),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(6),
      Q => sl_oport_o(7),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(7),
      Q => sl_oport_o(8),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(8),
      Q => sl_oport_o(9),
      R => '0'
    );
\G_1PIPE_IFACE.s_do_r_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => p_0_in(9),
      Q => sl_oport_o(10),
      R => '0'
    );
\G_1PIPE_IFACE.s_drdy_r_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_drdy_i,
      I1 => reg_drdy,
      O => \G_1PIPE_IFACE.s_drdy_r_i_1_n_0\
    );
\G_1PIPE_IFACE.s_drdy_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \G_1PIPE_IFACE.s_drdy_r_i_1_n_0\,
      Q => sl_oport_o(0),
      R => \^sl_iport_i\(0)
    );
\G_1PIPE_IFACE.s_dwe_r_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => \^sl_iport_i\(3),
      Q => s_dwe_o,
      R => \^sl_iport_i\(0)
    );
\reg_do[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFCFEFEFDFC"
    )
        port map (
      I0 => \reg_do[4]_i_4_n_0\,
      I1 => \^sl_iport_i\(9),
      I2 => \^sl_iport_i\(10),
      I3 => \reg_do[0]_i_4_n_0\,
      I4 => \reg_do[4]_i_6_n_0\,
      I5 => \reg_do[0]_i_5_n_0\,
      O => \reg_do[0]_i_2_n_0\
    );
\reg_do[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F5F0F8FF"
    )
        port map (
      I0 => \^sl_iport_i\(5),
      I1 => reg_test(0),
      I2 => \reg_do[4]_i_8_n_0\,
      I3 => \reg_do[4]_i_9_n_0\,
      I4 => \^sl_iport_i\(4),
      O => \reg_do[0]_i_3_n_0\
    );
\reg_do[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(16),
      I1 => uuid_stamp(48),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(0),
      I5 => uuid_stamp(32),
      O => \reg_do[0]_i_4_n_0\
    );
\reg_do[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(80),
      I1 => uuid_stamp(112),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(64),
      I5 => uuid_stamp(96),
      O => \reg_do[0]_i_5_n_0\
    );
\reg_do[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[10]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[10]_i_3_n_0\,
      I4 => \reg_do[10]_i_4_n_0\,
      I5 => \reg_do[10]_i_5_n_0\,
      O => reg_do(10)
    );
\reg_do[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(26),
      I1 => uuid_stamp(58),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(10),
      I5 => uuid_stamp(42),
      O => \reg_do[10]_i_2_n_0\
    );
\reg_do[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(90),
      I1 => uuid_stamp(122),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(74),
      I5 => uuid_stamp(106),
      O => \reg_do[10]_i_3_n_0\
    );
\reg_do[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C02CC02C2C2CC02C"
    )
        port map (
      I0 => reg_test(10),
      I1 => \^sl_iport_i\(4),
      I2 => \^sl_iport_i\(5),
      I3 => \^sl_iport_i\(8),
      I4 => \^sl_iport_i\(6),
      I5 => \^sl_iport_i\(7),
      O => \reg_do[10]_i_4_n_0\
    );
\reg_do[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \^sl_iport_i\(11),
      I1 => \^sl_iport_i\(10),
      I2 => \^sl_iport_i\(8),
      I3 => \^sl_iport_i\(7),
      I4 => \^sl_iport_i\(9),
      O => \reg_do[10]_i_5_n_0\
    );
\reg_do[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[11]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[11]_i_3_n_0\,
      I4 => reg_test(11),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(11)
    );
\reg_do[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(27),
      I1 => uuid_stamp(59),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(11),
      I5 => uuid_stamp(43),
      O => \reg_do[11]_i_2_n_0\
    );
\reg_do[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(91),
      I1 => uuid_stamp(123),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(75),
      I5 => uuid_stamp(107),
      O => \reg_do[11]_i_3_n_0\
    );
\reg_do[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[12]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[12]_i_3_n_0\,
      I4 => reg_test(12),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(12)
    );
\reg_do[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(28),
      I1 => uuid_stamp(60),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(12),
      I5 => uuid_stamp(44),
      O => \reg_do[12]_i_2_n_0\
    );
\reg_do[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(92),
      I1 => uuid_stamp(124),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(76),
      I5 => uuid_stamp(108),
      O => \reg_do[12]_i_3_n_0\
    );
\reg_do[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[13]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[13]_i_3_n_0\,
      I4 => reg_test(13),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(13)
    );
\reg_do[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(29),
      I1 => uuid_stamp(61),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(13),
      I5 => uuid_stamp(45),
      O => \reg_do[13]_i_2_n_0\
    );
\reg_do[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(93),
      I1 => uuid_stamp(125),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(77),
      I5 => uuid_stamp(109),
      O => \reg_do[13]_i_3_n_0\
    );
\reg_do[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[14]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[14]_i_3_n_0\,
      I4 => reg_test(14),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(14)
    );
\reg_do[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(30),
      I1 => uuid_stamp(62),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(14),
      I5 => uuid_stamp(46),
      O => \reg_do[14]_i_2_n_0\
    );
\reg_do[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(94),
      I1 => uuid_stamp(126),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(78),
      I5 => uuid_stamp(110),
      O => \reg_do[14]_i_3_n_0\
    );
\reg_do[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[15]_i_3_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[15]_i_5_n_0\,
      I4 => reg_test(15),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(15)
    );
\reg_do[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^sl_iport_i\(10),
      I1 => \^sl_iport_i\(9),
      I2 => \^sl_iport_i\(11),
      I3 => \^sl_iport_i\(8),
      I4 => \^sl_iport_i\(6),
      I5 => \^sl_iport_i\(7),
      O => \reg_do[15]_i_2_n_0\
    );
\reg_do[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(31),
      I1 => uuid_stamp(63),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(15),
      I5 => uuid_stamp(47),
      O => \reg_do[15]_i_3_n_0\
    );
\reg_do[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^sl_iport_i\(10),
      I1 => \^sl_iport_i\(9),
      I2 => \^sl_iport_i\(11),
      I3 => \^sl_iport_i\(8),
      I4 => \^sl_iport_i\(6),
      I5 => \^sl_iport_i\(7),
      O => \reg_do[15]_i_4_n_0\
    );
\reg_do[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(95),
      I1 => uuid_stamp(127),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(79),
      I5 => uuid_stamp(111),
      O => \reg_do[15]_i_5_n_0\
    );
\reg_do[15]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \reg_do[8]_i_2_n_0\,
      I1 => \^sl_iport_i\(4),
      I2 => \^sl_iport_i\(5),
      O => \reg_do[15]_i_6_n_0\
    );
\reg_do[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[1]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[1]_i_3_n_0\,
      I4 => \reg_do[1]_i_4_n_0\,
      I5 => \reg_do[10]_i_5_n_0\,
      O => reg_do(1)
    );
\reg_do[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(17),
      I1 => uuid_stamp(49),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(1),
      I5 => uuid_stamp(33),
      O => \reg_do[1]_i_2_n_0\
    );
\reg_do[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(81),
      I1 => uuid_stamp(113),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(65),
      I5 => uuid_stamp(97),
      O => \reg_do[1]_i_3_n_0\
    );
\reg_do[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DF55DF5530FF1055"
    )
        port map (
      I0 => \^sl_iport_i\(5),
      I1 => \^sl_iport_i\(7),
      I2 => \^sl_iport_i\(6),
      I3 => \^sl_iport_i\(8),
      I4 => reg_test(1),
      I5 => \^sl_iport_i\(4),
      O => \reg_do[1]_i_4_n_0\
    );
\reg_do[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[2]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[2]_i_3_n_0\,
      I4 => reg_test(2),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(2)
    );
\reg_do[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(18),
      I1 => uuid_stamp(50),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(2),
      I5 => uuid_stamp(34),
      O => \reg_do[2]_i_2_n_0\
    );
\reg_do[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(82),
      I1 => uuid_stamp(114),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(66),
      I5 => uuid_stamp(98),
      O => \reg_do[2]_i_3_n_0\
    );
\reg_do[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[3]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[3]_i_3_n_0\,
      I4 => reg_test(3),
      I5 => \reg_do[15]_i_6_n_0\,
      O => reg_do(3)
    );
\reg_do[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(19),
      I1 => uuid_stamp(51),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(3),
      I5 => uuid_stamp(35),
      O => \reg_do[3]_i_2_n_0\
    );
\reg_do[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(83),
      I1 => uuid_stamp(115),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(67),
      I5 => uuid_stamp(99),
      O => \reg_do[3]_i_3_n_0\
    );
\reg_do[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFCFEFEFDFC"
    )
        port map (
      I0 => \reg_do[4]_i_4_n_0\,
      I1 => \^sl_iport_i\(9),
      I2 => \^sl_iport_i\(10),
      I3 => \reg_do[4]_i_5_n_0\,
      I4 => \reg_do[4]_i_6_n_0\,
      I5 => \reg_do[4]_i_7_n_0\,
      O => \reg_do[4]_i_2_n_0\
    );
\reg_do[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABAAAB"
    )
        port map (
      I0 => \reg_do[4]_i_8_n_0\,
      I1 => \reg_do[4]_i_9_n_0\,
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => reg_test(4),
      O => \reg_do[4]_i_3_n_0\
    );
\reg_do[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^sl_iport_i\(7),
      I1 => \^sl_iport_i\(8),
      O => \reg_do[4]_i_4_n_0\
    );
\reg_do[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(20),
      I1 => uuid_stamp(52),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(4),
      I5 => uuid_stamp(36),
      O => \reg_do[4]_i_5_n_0\
    );
\reg_do[4]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \^sl_iport_i\(7),
      I1 => \^sl_iport_i\(6),
      I2 => \^sl_iport_i\(8),
      O => \reg_do[4]_i_6_n_0\
    );
\reg_do[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(84),
      I1 => uuid_stamp(116),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(68),
      I5 => uuid_stamp(100),
      O => \reg_do[4]_i_7_n_0\
    );
\reg_do[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \^sl_iport_i\(9),
      I1 => \^sl_iport_i\(7),
      I2 => \^sl_iport_i\(8),
      I3 => \^sl_iport_i\(10),
      O => \reg_do[4]_i_8_n_0\
    );
\reg_do[4]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \^sl_iport_i\(7),
      I1 => \^sl_iport_i\(6),
      I2 => \^sl_iport_i\(8),
      O => \reg_do[4]_i_9_n_0\
    );
\reg_do[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6040"
    )
        port map (
      I0 => \^sl_iport_i\(5),
      I1 => \^sl_iport_i\(4),
      I2 => \reg_do[8]_i_2_n_0\,
      I3 => reg_test(5),
      I4 => \reg_do[5]_i_2_n_0\,
      O => reg_do(5)
    );
\reg_do[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \reg_do[5]_i_3_n_0\,
      I1 => \reg_do[15]_i_4_n_0\,
      I2 => \reg_do[5]_i_4_n_0\,
      I3 => \reg_do[15]_i_2_n_0\,
      O => \reg_do[5]_i_2_n_0\
    );
\reg_do[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(85),
      I1 => uuid_stamp(117),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(69),
      I5 => uuid_stamp(101),
      O => \reg_do[5]_i_3_n_0\
    );
\reg_do[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(21),
      I1 => uuid_stamp(53),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(5),
      I5 => uuid_stamp(37),
      O => \reg_do[5]_i_4_n_0\
    );
\reg_do[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6040"
    )
        port map (
      I0 => \^sl_iport_i\(5),
      I1 => \^sl_iport_i\(4),
      I2 => \reg_do[8]_i_2_n_0\,
      I3 => reg_test(6),
      I4 => \reg_do[6]_i_2_n_0\,
      O => reg_do(6)
    );
\reg_do[6]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \reg_do[6]_i_3_n_0\,
      I1 => \reg_do[15]_i_4_n_0\,
      I2 => \reg_do[6]_i_4_n_0\,
      I3 => \reg_do[15]_i_2_n_0\,
      O => \reg_do[6]_i_2_n_0\
    );
\reg_do[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(86),
      I1 => uuid_stamp(118),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(70),
      I5 => uuid_stamp(102),
      O => \reg_do[6]_i_3_n_0\
    );
\reg_do[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(22),
      I1 => uuid_stamp(54),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(6),
      I5 => uuid_stamp(38),
      O => \reg_do[6]_i_4_n_0\
    );
\reg_do[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6040"
    )
        port map (
      I0 => \^sl_iport_i\(5),
      I1 => \^sl_iport_i\(4),
      I2 => \reg_do[8]_i_2_n_0\,
      I3 => reg_test(7),
      I4 => \reg_do[7]_i_2_n_0\,
      O => reg_do(7)
    );
\reg_do[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \reg_do[7]_i_3_n_0\,
      I1 => \reg_do[15]_i_4_n_0\,
      I2 => \reg_do[7]_i_4_n_0\,
      I3 => \reg_do[15]_i_2_n_0\,
      O => \reg_do[7]_i_2_n_0\
    );
\reg_do[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(87),
      I1 => uuid_stamp(119),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(71),
      I5 => uuid_stamp(103),
      O => \reg_do[7]_i_3_n_0\
    );
\reg_do[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(23),
      I1 => uuid_stamp(55),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(7),
      I5 => uuid_stamp(39),
      O => \reg_do[7]_i_4_n_0\
    );
\reg_do[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2A22"
    )
        port map (
      I0 => \reg_do[8]_i_2_n_0\,
      I1 => \^sl_iport_i\(5),
      I2 => \^sl_iport_i\(4),
      I3 => reg_test(8),
      I4 => \reg_do[8]_i_3_n_0\,
      O => reg_do(8)
    );
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \^sl_iport_i\(9),
      I1 => \^sl_iport_i\(10),
      I2 => \^sl_iport_i\(11),
      I3 => \^sl_iport_i\(8),
      I4 => \^sl_iport_i\(6),
      I5 => \^sl_iport_i\(7),
      O => \reg_do[8]_i_2_n_0\
    );
\reg_do[8]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \reg_do[8]_i_4_n_0\,
      I1 => \reg_do[15]_i_4_n_0\,
      I2 => \reg_do[8]_i_5_n_0\,
      I3 => \reg_do[15]_i_2_n_0\,
      O => \reg_do[8]_i_3_n_0\
    );
\reg_do[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(88),
      I1 => uuid_stamp(120),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(72),
      I5 => uuid_stamp(104),
      O => \reg_do[8]_i_4_n_0\
    );
\reg_do[8]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(24),
      I1 => uuid_stamp(56),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(8),
      I5 => uuid_stamp(40),
      O => \reg_do[8]_i_5_n_0\
    );
\reg_do[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reg_do[15]_i_2_n_0\,
      I1 => \reg_do[9]_i_2_n_0\,
      I2 => \reg_do[15]_i_4_n_0\,
      I3 => \reg_do[9]_i_3_n_0\,
      I4 => \reg_do[9]_i_4_n_0\,
      I5 => \reg_do[10]_i_5_n_0\,
      O => reg_do(9)
    );
\reg_do[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(25),
      I1 => uuid_stamp(57),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(9),
      I5 => uuid_stamp(41),
      O => \reg_do[9]_i_2_n_0\
    );
\reg_do[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFAFCFA0C0AFC0A0"
    )
        port map (
      I0 => uuid_stamp(89),
      I1 => uuid_stamp(121),
      I2 => \^sl_iport_i\(4),
      I3 => \^sl_iport_i\(5),
      I4 => uuid_stamp(73),
      I5 => uuid_stamp(105),
      O => \reg_do[9]_i_3_n_0\
    );
\reg_do[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C02CC02C2C2CC02C"
    )
        port map (
      I0 => reg_test(9),
      I1 => \^sl_iport_i\(4),
      I2 => \^sl_iport_i\(5),
      I3 => \^sl_iport_i\(8),
      I4 => \^sl_iport_i\(6),
      I5 => \^sl_iport_i\(7),
      O => \reg_do[9]_i_4_n_0\
    );
\reg_do_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(0),
      Q => \reg_do_reg_n_0_[0]\,
      R => '0'
    );
\reg_do_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \reg_do[0]_i_2_n_0\,
      I1 => \reg_do[0]_i_3_n_0\,
      O => reg_do(0),
      S => \^sl_iport_i\(11)
    );
\reg_do_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(10),
      Q => \reg_do_reg_n_0_[10]\,
      R => '0'
    );
\reg_do_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(11),
      Q => \reg_do_reg_n_0_[11]\,
      R => '0'
    );
\reg_do_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(12),
      Q => \reg_do_reg_n_0_[12]\,
      R => '0'
    );
\reg_do_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(13),
      Q => \reg_do_reg_n_0_[13]\,
      R => '0'
    );
\reg_do_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(14),
      Q => \reg_do_reg_n_0_[14]\,
      R => '0'
    );
\reg_do_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(15),
      Q => \reg_do_reg_n_0_[15]\,
      R => '0'
    );
\reg_do_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(1),
      Q => \reg_do_reg_n_0_[1]\,
      R => '0'
    );
\reg_do_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(2),
      Q => \reg_do_reg_n_0_[2]\,
      R => '0'
    );
\reg_do_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(3),
      Q => \reg_do_reg_n_0_[3]\,
      R => '0'
    );
\reg_do_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(4),
      Q => \reg_do_reg_n_0_[4]\,
      R => '0'
    );
\reg_do_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \reg_do[4]_i_2_n_0\,
      I1 => \reg_do[4]_i_3_n_0\,
      O => reg_do(4),
      S => \^sl_iport_i\(11)
    );
\reg_do_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(5),
      Q => \reg_do_reg_n_0_[5]\,
      R => '0'
    );
\reg_do_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(6),
      Q => \reg_do_reg_n_0_[6]\,
      R => '0'
    );
\reg_do_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(7),
      Q => \reg_do_reg_n_0_[7]\,
      R => '0'
    );
\reg_do_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(8),
      Q => \reg_do_reg_n_0_[8]\,
      R => '0'
    );
\reg_do_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_do(9),
      Q => \reg_do_reg_n_0_[9]\,
      R => '0'
    );
reg_drdy_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \G_1PIPE_IFACE.s_den_r_i_2_n_0\,
      I1 => \^sl_iport_i\(12),
      I2 => \^sl_iport_i\(13),
      I3 => \^sl_iport_i\(14),
      I4 => \^sl_iport_i\(2),
      O => reg_drdy0
    );
reg_drdy_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => reg_drdy0,
      Q => reg_drdy,
      R => \^sl_iport_i\(0)
    );
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \G_1PIPE_IFACE.s_den_r_i_2_n_0\,
      I1 => \^sl_iport_i\(12),
      I2 => \^sl_iport_i\(13),
      I3 => \^sl_iport_i\(14),
      I4 => \^sl_iport_i\(3),
      I5 => \^sl_iport_i\(2),
      O => reg_test0
    );
\reg_test_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(21),
      Q => reg_test(0),
      R => '0'
    );
\reg_test_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(31),
      Q => reg_test(10),
      R => '0'
    );
\reg_test_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(32),
      Q => reg_test(11),
      R => '0'
    );
\reg_test_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(33),
      Q => reg_test(12),
      R => '0'
    );
\reg_test_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(34),
      Q => reg_test(13),
      R => '0'
    );
\reg_test_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(35),
      Q => reg_test(14),
      R => '0'
    );
\reg_test_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(36),
      Q => reg_test(15),
      R => '0'
    );
\reg_test_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(22),
      Q => reg_test(1),
      R => '0'
    );
\reg_test_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(23),
      Q => reg_test(2),
      R => '0'
    );
\reg_test_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(24),
      Q => reg_test(3),
      R => '0'
    );
\reg_test_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(25),
      Q => reg_test(4),
      R => '0'
    );
\reg_test_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(26),
      Q => reg_test(5),
      R => '0'
    );
\reg_test_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(27),
      Q => reg_test(6),
      R => '0'
    );
\reg_test_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(28),
      Q => reg_test(7),
      R => '0'
    );
\reg_test_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(29),
      Q => reg_test(8),
      R => '0'
    );
\reg_test_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^sl_iport_i\(1),
      CE => reg_test0,
      D => \^sl_iport_i\(30),
      Q => reg_test(9),
      R => '0'
    );
\uuid_stamp_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(0),
      Q => uuid_stamp(0),
      R => '0'
    );
\uuid_stamp_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(100),
      Q => uuid_stamp(100),
      R => '0'
    );
\uuid_stamp_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(101),
      Q => uuid_stamp(101),
      R => '0'
    );
\uuid_stamp_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(102),
      Q => uuid_stamp(102),
      R => '0'
    );
\uuid_stamp_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(103),
      Q => uuid_stamp(103),
      R => '0'
    );
\uuid_stamp_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(104),
      Q => uuid_stamp(104),
      R => '0'
    );
\uuid_stamp_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(105),
      Q => uuid_stamp(105),
      R => '0'
    );
\uuid_stamp_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(106),
      Q => uuid_stamp(106),
      R => '0'
    );
\uuid_stamp_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(107),
      Q => uuid_stamp(107),
      R => '0'
    );
\uuid_stamp_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(108),
      Q => uuid_stamp(108),
      R => '0'
    );
\uuid_stamp_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(109),
      Q => uuid_stamp(109),
      R => '0'
    );
\uuid_stamp_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(10),
      Q => uuid_stamp(10),
      R => '0'
    );
\uuid_stamp_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(110),
      Q => uuid_stamp(110),
      R => '0'
    );
\uuid_stamp_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(111),
      Q => uuid_stamp(111),
      R => '0'
    );
\uuid_stamp_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(112),
      Q => uuid_stamp(112),
      R => '0'
    );
\uuid_stamp_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(113),
      Q => uuid_stamp(113),
      R => '0'
    );
\uuid_stamp_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(114),
      Q => uuid_stamp(114),
      R => '0'
    );
\uuid_stamp_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(115),
      Q => uuid_stamp(115),
      R => '0'
    );
\uuid_stamp_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(116),
      Q => uuid_stamp(116),
      R => '0'
    );
\uuid_stamp_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(117),
      Q => uuid_stamp(117),
      R => '0'
    );
\uuid_stamp_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(118),
      Q => uuid_stamp(118),
      R => '0'
    );
\uuid_stamp_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(119),
      Q => uuid_stamp(119),
      R => '0'
    );
\uuid_stamp_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(11),
      Q => uuid_stamp(11),
      R => '0'
    );
\uuid_stamp_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(120),
      Q => uuid_stamp(120),
      R => '0'
    );
\uuid_stamp_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(121),
      Q => uuid_stamp(121),
      R => '0'
    );
\uuid_stamp_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(122),
      Q => uuid_stamp(122),
      R => '0'
    );
\uuid_stamp_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(123),
      Q => uuid_stamp(123),
      R => '0'
    );
\uuid_stamp_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(124),
      Q => uuid_stamp(124),
      R => '0'
    );
\uuid_stamp_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(125),
      Q => uuid_stamp(125),
      R => '0'
    );
\uuid_stamp_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(126),
      Q => uuid_stamp(126),
      R => '0'
    );
\uuid_stamp_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(127),
      Q => uuid_stamp(127),
      R => '0'
    );
\uuid_stamp_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(12),
      Q => uuid_stamp(12),
      R => '0'
    );
\uuid_stamp_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(13),
      Q => uuid_stamp(13),
      R => '0'
    );
\uuid_stamp_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(14),
      Q => uuid_stamp(14),
      R => '0'
    );
\uuid_stamp_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(15),
      Q => uuid_stamp(15),
      R => '0'
    );
\uuid_stamp_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(16),
      Q => uuid_stamp(16),
      R => '0'
    );
\uuid_stamp_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(17),
      Q => uuid_stamp(17),
      R => '0'
    );
\uuid_stamp_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(18),
      Q => uuid_stamp(18),
      R => '0'
    );
\uuid_stamp_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(19),
      Q => uuid_stamp(19),
      R => '0'
    );
\uuid_stamp_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(1),
      Q => uuid_stamp(1),
      R => '0'
    );
\uuid_stamp_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(20),
      Q => uuid_stamp(20),
      R => '0'
    );
\uuid_stamp_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(21),
      Q => uuid_stamp(21),
      R => '0'
    );
\uuid_stamp_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(22),
      Q => uuid_stamp(22),
      R => '0'
    );
\uuid_stamp_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(23),
      Q => uuid_stamp(23),
      R => '0'
    );
\uuid_stamp_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(24),
      Q => uuid_stamp(24),
      R => '0'
    );
\uuid_stamp_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(25),
      Q => uuid_stamp(25),
      R => '0'
    );
\uuid_stamp_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(26),
      Q => uuid_stamp(26),
      R => '0'
    );
\uuid_stamp_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(27),
      Q => uuid_stamp(27),
      R => '0'
    );
\uuid_stamp_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(28),
      Q => uuid_stamp(28),
      R => '0'
    );
\uuid_stamp_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(29),
      Q => uuid_stamp(29),
      R => '0'
    );
\uuid_stamp_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(2),
      Q => uuid_stamp(2),
      R => '0'
    );
\uuid_stamp_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(30),
      Q => uuid_stamp(30),
      R => '0'
    );
\uuid_stamp_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(31),
      Q => uuid_stamp(31),
      R => '0'
    );
\uuid_stamp_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(32),
      Q => uuid_stamp(32),
      R => '0'
    );
\uuid_stamp_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(33),
      Q => uuid_stamp(33),
      R => '0'
    );
\uuid_stamp_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(34),
      Q => uuid_stamp(34),
      R => '0'
    );
\uuid_stamp_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(35),
      Q => uuid_stamp(35),
      R => '0'
    );
\uuid_stamp_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(36),
      Q => uuid_stamp(36),
      R => '0'
    );
\uuid_stamp_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(37),
      Q => uuid_stamp(37),
      R => '0'
    );
\uuid_stamp_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(38),
      Q => uuid_stamp(38),
      R => '0'
    );
\uuid_stamp_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(39),
      Q => uuid_stamp(39),
      R => '0'
    );
\uuid_stamp_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(3),
      Q => uuid_stamp(3),
      R => '0'
    );
\uuid_stamp_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(40),
      Q => uuid_stamp(40),
      R => '0'
    );
\uuid_stamp_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(41),
      Q => uuid_stamp(41),
      R => '0'
    );
\uuid_stamp_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(42),
      Q => uuid_stamp(42),
      R => '0'
    );
\uuid_stamp_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(43),
      Q => uuid_stamp(43),
      R => '0'
    );
\uuid_stamp_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(44),
      Q => uuid_stamp(44),
      R => '0'
    );
\uuid_stamp_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(45),
      Q => uuid_stamp(45),
      R => '0'
    );
\uuid_stamp_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(46),
      Q => uuid_stamp(46),
      R => '0'
    );
\uuid_stamp_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(47),
      Q => uuid_stamp(47),
      R => '0'
    );
\uuid_stamp_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(48),
      Q => uuid_stamp(48),
      R => '0'
    );
\uuid_stamp_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(49),
      Q => uuid_stamp(49),
      R => '0'
    );
\uuid_stamp_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(4),
      Q => uuid_stamp(4),
      R => '0'
    );
\uuid_stamp_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(50),
      Q => uuid_stamp(50),
      R => '0'
    );
\uuid_stamp_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(51),
      Q => uuid_stamp(51),
      R => '0'
    );
\uuid_stamp_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(52),
      Q => uuid_stamp(52),
      R => '0'
    );
\uuid_stamp_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(53),
      Q => uuid_stamp(53),
      R => '0'
    );
\uuid_stamp_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(54),
      Q => uuid_stamp(54),
      R => '0'
    );
\uuid_stamp_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(55),
      Q => uuid_stamp(55),
      R => '0'
    );
\uuid_stamp_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(56),
      Q => uuid_stamp(56),
      R => '0'
    );
\uuid_stamp_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(57),
      Q => uuid_stamp(57),
      R => '0'
    );
\uuid_stamp_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(58),
      Q => uuid_stamp(58),
      R => '0'
    );
\uuid_stamp_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(59),
      Q => uuid_stamp(59),
      R => '0'
    );
\uuid_stamp_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(5),
      Q => uuid_stamp(5),
      R => '0'
    );
\uuid_stamp_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(60),
      Q => uuid_stamp(60),
      R => '0'
    );
\uuid_stamp_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(61),
      Q => uuid_stamp(61),
      R => '0'
    );
\uuid_stamp_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(62),
      Q => uuid_stamp(62),
      R => '0'
    );
\uuid_stamp_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(63),
      Q => uuid_stamp(63),
      R => '0'
    );
\uuid_stamp_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(64),
      Q => uuid_stamp(64),
      R => '0'
    );
\uuid_stamp_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(65),
      Q => uuid_stamp(65),
      R => '0'
    );
\uuid_stamp_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(66),
      Q => uuid_stamp(66),
      R => '0'
    );
\uuid_stamp_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(67),
      Q => uuid_stamp(67),
      R => '0'
    );
\uuid_stamp_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(68),
      Q => uuid_stamp(68),
      R => '0'
    );
\uuid_stamp_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(69),
      Q => uuid_stamp(69),
      R => '0'
    );
\uuid_stamp_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(6),
      Q => uuid_stamp(6),
      R => '0'
    );
\uuid_stamp_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(70),
      Q => uuid_stamp(70),
      R => '0'
    );
\uuid_stamp_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(71),
      Q => uuid_stamp(71),
      R => '0'
    );
\uuid_stamp_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(72),
      Q => uuid_stamp(72),
      R => '0'
    );
\uuid_stamp_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(73),
      Q => uuid_stamp(73),
      R => '0'
    );
\uuid_stamp_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(74),
      Q => uuid_stamp(74),
      R => '0'
    );
\uuid_stamp_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(75),
      Q => uuid_stamp(75),
      R => '0'
    );
\uuid_stamp_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(76),
      Q => uuid_stamp(76),
      R => '0'
    );
\uuid_stamp_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(77),
      Q => uuid_stamp(77),
      R => '0'
    );
\uuid_stamp_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(78),
      Q => uuid_stamp(78),
      R => '0'
    );
\uuid_stamp_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(79),
      Q => uuid_stamp(79),
      R => '0'
    );
\uuid_stamp_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(7),
      Q => uuid_stamp(7),
      R => '0'
    );
\uuid_stamp_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(80),
      Q => uuid_stamp(80),
      R => '0'
    );
\uuid_stamp_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(81),
      Q => uuid_stamp(81),
      R => '0'
    );
\uuid_stamp_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(82),
      Q => uuid_stamp(82),
      R => '0'
    );
\uuid_stamp_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(83),
      Q => uuid_stamp(83),
      R => '0'
    );
\uuid_stamp_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(84),
      Q => uuid_stamp(84),
      R => '0'
    );
\uuid_stamp_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(85),
      Q => uuid_stamp(85),
      R => '0'
    );
\uuid_stamp_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(86),
      Q => uuid_stamp(86),
      R => '0'
    );
\uuid_stamp_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(87),
      Q => uuid_stamp(87),
      R => '0'
    );
\uuid_stamp_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(88),
      Q => uuid_stamp(88),
      R => '0'
    );
\uuid_stamp_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(89),
      Q => uuid_stamp(89),
      R => '0'
    );
\uuid_stamp_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(8),
      Q => uuid_stamp(8),
      R => '0'
    );
\uuid_stamp_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(90),
      Q => uuid_stamp(90),
      R => '0'
    );
\uuid_stamp_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(91),
      Q => uuid_stamp(91),
      R => '0'
    );
\uuid_stamp_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(92),
      Q => uuid_stamp(92),
      R => '0'
    );
\uuid_stamp_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(93),
      Q => uuid_stamp(93),
      R => '0'
    );
\uuid_stamp_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(94),
      Q => uuid_stamp(94),
      R => '0'
    );
\uuid_stamp_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(95),
      Q => uuid_stamp(95),
      R => '0'
    );
\uuid_stamp_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(96),
      Q => uuid_stamp(96),
      R => '0'
    );
\uuid_stamp_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(97),
      Q => uuid_stamp(97),
      R => '0'
    );
\uuid_stamp_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(98),
      Q => uuid_stamp(98),
      R => '0'
    );
\uuid_stamp_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(99),
      Q => uuid_stamp(99),
      R => '0'
    );
\uuid_stamp_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^sl_iport_i\(1),
      CE => '1',
      D => uuid_stamp(9),
      Q => uuid_stamp(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_width";
end ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper
     port map (
      D(35 downto 0) => D(35 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0\ is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_width";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized0\
     port map (
      D(35 downto 0) => D(35 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1\ is
  port (
    D : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_width";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized1\
     port map (
      D(35 downto 0) => D(35 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2\ is
  port (
    D : out STD_LOGIC_VECTOR ( 30 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_prim_width";
end \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_wrapper__parameterized2\
     port map (
      D(30 downto 0) => D(30 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(30 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_reset_ctrl is
  port (
    dout_reg1_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \reset_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    last_din_reg : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    prev_cap_done_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    halt_ctrl : in STD_LOGIC;
    arm_ctrl : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_reset_ctrl : entity is "ila_v6_2_10_ila_reset_ctrl";
end ila_full_aurora_ila_v6_2_10_ila_reset_ctrl;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_reset_ctrl is
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal arm_in_detection : STD_LOGIC;
  signal arm_in_transferred : STD_LOGIC;
  signal \asyncrounous_transfer.arm_in_transfer_inst_n_1\ : STD_LOGIC;
  signal \asyncrounous_transfer.halt_in_transfer_inst_n_1\ : STD_LOGIC;
  signal halt_detection_inst_n_1 : STD_LOGIC;
  signal halt_detection_inst_n_2 : STD_LOGIC;
  signal halt_in_transferred : STD_LOGIC;
  signal halt_out : STD_LOGIC;
  signal last_din : STD_LOGIC;
  signal last_din_0 : STD_LOGIC;
  signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prev_cap_done : STD_LOGIC;
  signal reset : STD_LOGIC_VECTOR ( 4 downto 2 );
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
arm_detection_inst: entity work.ila_full_aurora_ltlib_v1_0_0_rising_edge_detection
     port map (
      D(0) => p_0_out(0),
      Q(0) => \^q\(1),
      \dout_pulse_reg[0]_0\(0) => \asyncrounous_transfer.arm_in_transfer_inst_n_1\,
      \dout_pulse_reg[1]_0\(0) => arm_in_detection,
      last_din => last_din,
      last_din_reg_0 => last_din_reg,
      \out\ => arm_in_transferred
    );
\asyncrounous_transfer.arm_in_transfer_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_async_edge_xfer
     port map (
      arm_ctrl => arm_ctrl,
      dout_reg0_reg_0 => last_din_reg,
      dout_reg1_reg_0(0) => \asyncrounous_transfer.arm_in_transfer_inst_n_1\,
      last_din => last_din,
      \out\ => arm_in_transferred,
      s_dclk_o => s_dclk_o
    );
\asyncrounous_transfer.arm_out_transfer_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_26
     port map (
      Q(0) => \^q\(0),
      dout_reg1_reg_0(0) => dout_reg1_reg(0),
      s_dclk_o => s_dclk_o,
      temp_reg1_reg_0 => last_din_reg
    );
\asyncrounous_transfer.halt_in_transfer_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_27
     port map (
      D(0) => \asyncrounous_transfer.halt_in_transfer_inst_n_1\,
      dout_reg0_reg_0 => last_din_reg,
      halt_ctrl => halt_ctrl,
      last_din => last_din_0,
      \out\ => halt_in_transferred,
      s_dclk_o => s_dclk_o
    );
\asyncrounous_transfer.halt_out_transfer_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_async_edge_xfer_28
     port map (
      dout_reg1_reg_0(0) => dout_reg1_reg(1),
      halt_out => halt_out,
      s_dclk_o => s_dclk_o,
      temp_reg0_reg_0 => last_din_reg
    );
\captured_samples[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \reset_out_reg[0]_0\(0)
    );
halt_detection_inst: entity work.ila_full_aurora_ltlib_v1_0_0_rising_edge_detection_29
     port map (
      D(0) => \asyncrounous_transfer.halt_in_transfer_inst_n_1\,
      Q(0) => \^q\(0),
      SS(0) => halt_detection_inst_n_2,
      halt_out => halt_out,
      halt_out_reg => halt_detection_inst_n_1,
      halt_out_reg_0(0) => arm_in_detection,
      last_din => last_din_0,
      last_din_reg_0 => last_din_reg,
      \out\ => halt_in_transferred,
      prev_cap_done => prev_cap_done,
      \reset_out_reg[0]\(0) => prev_cap_done_reg_0(0)
    );
halt_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => halt_detection_inst_n_1,
      Q => halt_out,
      R => '0'
    );
prev_cap_done_reg: unisim.vcomponents.FDRE
     port map (
      C => last_din_reg,
      CE => '1',
      D => prev_cap_done_reg_0(0),
      Q => prev_cap_done,
      R => '0'
    );
\reset_out_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => p_0_out(0),
      Q => \^q\(0),
      S => halt_detection_inst_n_2
    );
\reset_out_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => \^q\(0),
      Q => \^q\(1),
      S => halt_detection_inst_n_2
    );
\reset_out_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => \^q\(1),
      Q => reset(2),
      S => halt_detection_inst_n_2
    );
\reset_out_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => reset(2),
      Q => \^q\(2),
      S => halt_detection_inst_n_2
    );
\reset_out_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => \^q\(2),
      Q => reset(4),
      S => halt_detection_inst_n_2
    );
\reset_out_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => last_din_reg,
      CE => '1',
      D => reset(4),
      Q => \^q\(3),
      S => halt_detection_inst_n_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA : entity is "ltlib_v1_0_0_all_typeA";
end ila_full_aurora_ltlib_v1_0_0_all_typeA;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA is
  signal all_carry_0 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_10
     port map (
      CO(0) => all_carry_0,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_in(15 downto 0) => all_in(15 downto 0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o,
      srl_q_0 => srl_q_0
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_11 is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_dly1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    all_dly2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_11 : entity is "ltlib_v1_0_0_all_typeA";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_11;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_11 is
  signal all_carry_0 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_12
     port map (
      CO(0) => all_carry_0,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_dly1(0) => all_dly1(0),
      all_dly2(0) => all_dly2(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o,
      srl_q_0 => srl_q_0
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_14 is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_dly1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    all_dly2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_14 : entity is "ltlib_v1_0_0_all_typeA";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_14;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_14 is
  signal all_carry_0 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_15
     port map (
      CO(0) => all_carry_0,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_dly1(0) => all_dly1(0),
      all_dly2(0) => all_dly2(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o,
      srl_q_0 => srl_q_0
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_all_typeA_24 is
  port (
    \out\ : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    tc_config_cs_serial_output : in STD_LOGIC;
    \parallel_dout_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_all_typeA_24 : entity is "ltlib_v1_0_0_all_typeA";
end ila_full_aurora_ltlib_v1_0_0_all_typeA_24;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_all_typeA_24 is
  signal all_carry_0 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_25
     port map (
      CO(0) => all_carry_0,
      D(5 downto 0) => D(5 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\(0) => \parallel_dout_reg[15]\(0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1\(0) => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\(0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\,
      Q(5 downto 0) => Q(5 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o,
      srl_q_0 => srl_q_0,
      tc_config_cs_serial_output => tc_config_cs_serial_output
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => \parallel_dout_reg[15]\(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => shift_en_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized0\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 127 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized0\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized0\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal all_carry_2 : STD_LOGIC;
  signal all_carry_3 : STD_LOGIC;
  signal all_carry_4 : STD_LOGIC;
  signal all_carry_5 : STD_LOGIC;
  signal all_carry_6 : STD_LOGIC;
  signal all_carry_7 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal srl_q_2 : STD_LOGIC;
  signal srl_q_3 : STD_LOGIC;
  signal srl_q_4 : STD_LOGIC;
  signal srl_q_5 : STD_LOGIC;
  signal srl_q_6 : STD_LOGIC;
  signal srl_q_7 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_16\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      SRL_Q_O => srl_q_1,
      all_in(15 downto 0) => all_in(15 downto 0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_17\
     port map (
      CI_I => all_carry_1,
      DOUT_O => all_carry_2,
      SRL_Q_O => srl_q_2,
      all_in(15 downto 0) => all_in(31 downto 16),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_1
    );
\I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_18\
     port map (
      CI_I => all_carry_2,
      DOUT_O => all_carry_3,
      SRL_Q_O => srl_q_3,
      all_in(15 downto 0) => all_in(47 downto 32),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_2
    );
\I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_19\
     port map (
      CI_I => all_carry_3,
      DOUT_O => all_carry_4,
      SRL_Q_O => srl_q_4,
      all_in(15 downto 0) => all_in(63 downto 48),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_3
    );
\I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_20\
     port map (
      CI_I => all_carry_4,
      DOUT_O => all_carry_5,
      SRL_Q_O => srl_q_5,
      all_in(15 downto 0) => all_in(79 downto 64),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_4
    );
\I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_21\
     port map (
      CI_I => all_carry_5,
      DOUT_O => all_carry_6,
      SRL_Q_O => srl_q_6,
      all_in(15 downto 0) => all_in(95 downto 80),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_5
    );
\I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_22\
     port map (
      CI_I => all_carry_6,
      DOUT_O => all_carry_7,
      SRL_D_I => srl_q_7,
      SRL_Q_O => srl_q_6,
      all_in(15 downto 0) => all_in(111 downto 96),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o
    );
\I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_23
     port map (
      DOUT_O => all_carry_7,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      SRL_D_I => srl_q_7,
      all_in(15 downto 0) => all_in(127 downto 112),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal all_carry_2 : STD_LOGIC;
  signal all_carry_3 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal srl_q_2 : STD_LOGIC;
  signal srl_q_3 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      SRL_Q_O => srl_q_1,
      all_in(15 downto 0) => all_in(15 downto 0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_2\
     port map (
      CI_I => all_carry_1,
      DOUT_O => all_carry_2,
      SRL_Q_O => srl_q_2,
      all_in(15 downto 0) => all_in(31 downto 16),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_1
    );
\I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_3\
     port map (
      CI_I => all_carry_2,
      DOUT_O => all_carry_3,
      SRL_D_I => srl_q_3,
      SRL_Q_O => srl_q_2,
      all_in(15 downto 0) => all_in(47 downto 32),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o
    );
\I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice
     port map (
      DOUT_O => all_carry_3,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      SRL_D_I => srl_q_3,
      all_in(15 downto 0) => all_in(63 downto 48),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1_5\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    all_in : in STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1_5\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1_5\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1_5\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal all_carry_2 : STD_LOGIC;
  signal all_carry_3 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal srl_q_2 : STD_LOGIC;
  signal srl_q_3 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_6\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      SRL_Q_O => srl_q_1,
      all_in(15 downto 0) => all_in(15 downto 0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_7\
     port map (
      CI_I => all_carry_1,
      DOUT_O => all_carry_2,
      SRL_Q_O => srl_q_2,
      all_in(15 downto 0) => all_in(31 downto 16),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_1
    );
\I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized0_8\
     port map (
      CI_I => all_carry_2,
      DOUT_O => all_carry_3,
      SRL_D_I => srl_q_3,
      SRL_Q_O => srl_q_2,
      all_in(15 downto 0) => all_in(47 downto 32),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      s_dclk_o => s_dclk_o
    );
\I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE\: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_slice_9
     port map (
      DOUT_O => all_carry_3,
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      SRL_D_I => srl_q_3,
      all_in(15 downto 0) => all_in(63 downto 48),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => mu_config_cs_shift_en(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => mu_config_cs_serial_input(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2\ is
  port (
    shift_en_reg : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
    SRL_D_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      E(0) => E(0),
      PROBES_I(15 downto 0) => PROBES_I(15 downto 0),
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2\
     port map (
      CI_I => all_carry_1,
      E(0) => E(0),
      PROBES_I(3 downto 0) => PROBES_I(19 downto 16),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => E(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => SRL_Q_O
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_51\ is
  port (
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
    SRL_D_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_51\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_51\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_51\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_52\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      E(0) => E(0),
      PROBES_I(15 downto 0) => PROBES_I(15 downto 0),
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_53\
     port map (
      CI_I => all_carry_1,
      E(0) => E(0),
      PROBES_I(3 downto 0) => PROBES_I(19 downto 16),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => E(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => shift_en_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_59\ is
  port (
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    \iwcnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
    SRL_D_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_59\ : entity is "ltlib_v1_0_0_all_typeA";
end \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_59\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_59\ is
  signal all_carry_0 : STD_LOGIC;
  signal all_carry_1 : STD_LOGIC;
  signal drive_ci : STD_LOGIC;
  signal srl_q_0 : STD_LOGIC;
  signal srl_q_1 : STD_LOGIC;
  signal NLW_u_carry4_inst_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_u_carry4_inst_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_carry4_inst : label is "PRIMITIVE";
  attribute BOX_TYPE of u_srl_drive : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of u_srl_drive : label is "CFGLUT5";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of u_srl_drive : label is "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31";
begin
\I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized1_60\
     port map (
      CI_I => all_carry_0,
      DOUT_O => all_carry_1,
      PROBES_I(15 downto 0) => PROBES_I(15 downto 0),
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      shift_en_reg => srl_q_0,
      u_carry4_inst_0(0) => \iwcnt_reg[0]\(0)
    );
\I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE\: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA_slice__parameterized2_61\
     port map (
      CI_I => all_carry_1,
      DOUT_O => DOUT_O,
      PROBES_I(3 downto 0) => PROBES_I(19 downto 16),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => srl_q_1,
      s_dclk_o => s_dclk_o,
      u_carry4_inst_0(0) => \iwcnt_reg[0]\(0)
    );
u_carry4_inst: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => all_carry_0,
      CO(2 downto 0) => NLW_u_carry4_inst_CO_UNCONNECTED(2 downto 0),
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_u_carry4_inst_O_UNCONNECTED(3 downto 0),
      S(3 downto 1) => B"111",
      S(0) => drive_ci
    );
u_srl_drive: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => \iwcnt_reg[0]\(0),
      CLK => s_dclk_o,
      D => srl_q_0,
      Q => drive_ci,
      Q31 => SRL_Q_O
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized21\ is
  port (
    \G_1PIPE_IFACE.s_den_r_reg\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 8 downto 0 );
    s_den_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized21\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized21\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized21\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_39
     port map (
      \G_1PIPE_IFACE.s_den_r_reg\ => \G_1PIPE_IFACE.s_den_r_reg\,
      Q(0) => Q(0),
      s_daddr_o(8 downto 0) => s_daddr_o(8 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      s_dwe_o => s_dwe_o,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[15]_0\(11 downto 0) => \xsdb_reg_reg[15]\(11 downto 0),
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized22\ is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \G_1PIPE_IFACE.s_daddr_r_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[0]\ : out STD_LOGIC;
    halt_ctrl : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\ : out STD_LOGIC;
    scnt_cmp_temp : out STD_LOGIC;
    wcnt_lcmp_temp : out STD_LOGIC;
    wcnt_hcmp_temp : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \slaveRegDo_mux_01__6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]_6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \slaveRegDo_mux_0[3]_i_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \slaveRegDo_mux_0[1]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_4\ : in STD_LOGIC;
    DOUT_O : in STD_LOGIC;
    u_wcnt_lcmp_q : in STD_LOGIC;
    u_wcnt_hcmp_q : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized22\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized22\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized22\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized0\
     port map (
      D(3 downto 0) => D(3 downto 0),
      DOUT_O => DOUT_O,
      \G_1PIPE_IFACE.s_daddr_r_reg[0]\ => \G_1PIPE_IFACE.s_daddr_r_reg[0]\,
      \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\ => \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]\ => \G_1PIPE_IFACE.s_daddr_r_reg[2]\,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\ => \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\ => \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\,
      \G_1PIPE_IFACE.s_daddr_r_reg[3]\ => \G_1PIPE_IFACE.s_daddr_r_reg[3]\,
      Q(3 downto 0) => Q(3 downto 0),
      halt_ctrl => halt_ctrl,
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      scnt_cmp_temp => scnt_cmp_temp,
      \slaveRegDo_mux_01__6\ => \slaveRegDo_mux_01__6\,
      \slaveRegDo_mux_0[0]_i_2\ => \slaveRegDo_mux_0[0]_i_2\,
      \slaveRegDo_mux_0[1]_i_2_0\ => \slaveRegDo_mux_0[1]_i_2\,
      \slaveRegDo_mux_0[1]_i_4_0\ => \slaveRegDo_mux_0[1]_i_4\,
      \slaveRegDo_mux_0[2]_i_4_0\ => \slaveRegDo_mux_0[2]_i_4\,
      \slaveRegDo_mux_0[3]_i_2_0\(2 downto 0) => \slaveRegDo_mux_0[3]_i_2\(2 downto 0),
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0_reg[15]\,
      \slaveRegDo_mux_0_reg[15]_0\(7 downto 0) => \slaveRegDo_mux_0_reg[15]_0\(7 downto 0),
      \slaveRegDo_mux_0_reg[15]_1\ => \slaveRegDo_mux_0_reg[15]_1\,
      \slaveRegDo_mux_0_reg[1]\ => \slaveRegDo_mux_0_reg[1]\,
      \slaveRegDo_mux_0_reg[1]_0\ => \slaveRegDo_mux_0_reg[1]_0\,
      \slaveRegDo_mux_0_reg[1]_1\ => \slaveRegDo_mux_0_reg[1]_1\,
      \slaveRegDo_mux_0_reg[2]\ => \slaveRegDo_mux_0_reg[2]\,
      \slaveRegDo_mux_0_reg[2]_0\ => \slaveRegDo_mux_0_reg[2]_0\,
      \slaveRegDo_mux_0_reg[2]_1\ => \slaveRegDo_mux_0_reg[2]_1\,
      \slaveRegDo_mux_0_reg[3]\ => \slaveRegDo_mux_0_reg[3]\,
      \slaveRegDo_mux_0_reg[3]_0\ => \slaveRegDo_mux_0_reg[3]_0\,
      \slaveRegDo_mux_0_reg[3]_1\ => \slaveRegDo_mux_0_reg[3]_1\,
      \slaveRegDo_mux_0_reg[4]\ => \slaveRegDo_mux_0_reg[4]\,
      \slaveRegDo_mux_0_reg[5]\ => \slaveRegDo_mux_0_reg[5]\,
      \slaveRegDo_mux_0_reg[5]_0\ => \slaveRegDo_mux_0_reg[5]_0\,
      \slaveRegDo_mux_0_reg[5]_1\(3 downto 0) => \slaveRegDo_mux_0_reg[5]_1\(3 downto 0),
      \slaveRegDo_mux_0_reg[5]_2\ => \slaveRegDo_mux_0_reg[5]_2\,
      \slaveRegDo_mux_0_reg[5]_3\ => \slaveRegDo_mux_0_reg[5]_3\,
      \slaveRegDo_mux_0_reg[5]_4\ => \slaveRegDo_mux_0_reg[5]_4\,
      \slaveRegDo_mux_0_reg[5]_5\ => \slaveRegDo_mux_0_reg[5]_5\,
      \slaveRegDo_mux_0_reg[5]_6\ => \slaveRegDo_mux_0_reg[5]_6\,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0_reg[7]\,
      \slaveRegDo_mux_0_reg[8]\ => \slaveRegDo_mux_0_reg[8]\,
      \slaveRegDo_mux_0_reg[9]\ => \slaveRegDo_mux_0_reg[9]\,
      \slaveRegDo_mux_0_reg[9]_0\ => \slaveRegDo_mux_0_reg[9]_0\,
      u_wcnt_hcmp_q => u_wcnt_hcmp_q,
      u_wcnt_lcmp_q => u_wcnt_lcmp_q,
      wcnt_hcmp_temp => wcnt_hcmp_temp,
      wcnt_lcmp_temp => wcnt_lcmp_temp,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized23\ is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    s_den_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized23\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized23\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized23\ is
begin
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat_38
     port map (
      D(4 downto 0) => D(4 downto 0),
      Q(4 downto 0) => Q(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized24\ is
  port (
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \slaveRegDo_mux_0[9]_i_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_den_o : in STD_LOGIC;
    \xsdb_reg_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized24\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized24\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized24\ is
begin
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat_30
     port map (
      Q(0) => Q(0),
      s_daddr_o(3 downto 0) => s_daddr_o(3 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      \slaveRegDo_mux_0[9]_i_3\(3 downto 0) => \slaveRegDo_mux_0[9]_i_3\(3 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[7]_0\(4 downto 0) => \xsdb_reg_reg[7]\(4 downto 0),
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\,
      \xsdb_reg_reg[9]_1\(9 downto 0) => \xsdb_reg_reg[9]_0\(9 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized36\ is
  port (
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized36\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized36\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized36\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_45
     port map (
      SR(0) => SR(0),
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized37\ is
  port (
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    read_reset_addr : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized37\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized37\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized37\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_44
     port map (
      read_reset_addr(9 downto 0) => read_reset_addr(9 downto 0),
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \slaveRegDo_mux_0[1]_i_2\ => \slaveRegDo_mux_0[1]_i_2\,
      \slaveRegDo_mux_0[1]_i_2_0\ => \slaveRegDo_mux_0[1]_i_2_0\,
      \slaveRegDo_mux_0[2]_i_2\ => \slaveRegDo_mux_0[2]_i_2\,
      \slaveRegDo_mux_0[2]_i_2_0\ => \slaveRegDo_mux_0[2]_i_2_0\,
      \slaveRegDo_mux_0[3]_i_2\ => \slaveRegDo_mux_0[3]_i_2\,
      \slaveRegDo_mux_0[3]_i_2_0\ => \slaveRegDo_mux_0[3]_i_2_0\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized38\ is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_01__6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[0]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]_6\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    read_reset_addr : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized38\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized38\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized38\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_43
     port map (
      D(1 downto 0) => D(1 downto 0),
      SR(0) => SR(0),
      read_reset_addr(6 downto 0) => read_reset_addr(6 downto 0),
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \slaveRegDo_mux_01__6\ => \slaveRegDo_mux_01__6\,
      \slaveRegDo_mux_0[5]_i_2\ => \slaveRegDo_mux_0[5]_i_2\,
      \slaveRegDo_mux_0[6]_i_2_0\ => \slaveRegDo_mux_0[6]_i_2\,
      \slaveRegDo_mux_0_reg[0]\ => \slaveRegDo_mux_0_reg[0]\,
      \slaveRegDo_mux_0_reg[0]_0\ => \slaveRegDo_mux_0_reg[0]_0\,
      \slaveRegDo_mux_0_reg[0]_1\ => \slaveRegDo_mux_0_reg[0]_1\,
      \slaveRegDo_mux_0_reg[0]_2\ => \slaveRegDo_mux_0_reg[0]_2\,
      \slaveRegDo_mux_0_reg[10]\ => \slaveRegDo_mux_0_reg[10]\,
      \slaveRegDo_mux_0_reg[10]_0\ => \slaveRegDo_mux_0_reg[10]_0\,
      \slaveRegDo_mux_0_reg[11]\ => \slaveRegDo_mux_0_reg[11]\,
      \slaveRegDo_mux_0_reg[11]_0\ => \slaveRegDo_mux_0_reg[11]_0\,
      \slaveRegDo_mux_0_reg[12]\ => \slaveRegDo_mux_0_reg[12]\,
      \slaveRegDo_mux_0_reg[12]_0\ => \slaveRegDo_mux_0_reg[12]_0\,
      \slaveRegDo_mux_0_reg[13]\ => \slaveRegDo_mux_0_reg[13]\,
      \slaveRegDo_mux_0_reg[13]_0\ => \slaveRegDo_mux_0_reg[13]_0\,
      \slaveRegDo_mux_0_reg[14]\ => \slaveRegDo_mux_0_reg[14]\,
      \slaveRegDo_mux_0_reg[14]_0\ => \slaveRegDo_mux_0_reg[14]_0\,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0_reg[15]\,
      \slaveRegDo_mux_0_reg[15]_0\ => \slaveRegDo_mux_0_reg[15]_0\,
      \slaveRegDo_mux_0_reg[15]_1\ => \slaveRegDo_mux_0_reg[15]_1\,
      \slaveRegDo_mux_0_reg[4]\ => \slaveRegDo_mux_0_reg[4]\,
      \slaveRegDo_mux_0_reg[6]\ => \slaveRegDo_mux_0_reg[6]\,
      \slaveRegDo_mux_0_reg[6]_0\(1 downto 0) => \slaveRegDo_mux_0_reg[6]_0\(1 downto 0),
      \slaveRegDo_mux_0_reg[6]_1\ => \slaveRegDo_mux_0_reg[6]_1\,
      \slaveRegDo_mux_0_reg[6]_2\ => \slaveRegDo_mux_0_reg[6]_2\,
      \slaveRegDo_mux_0_reg[6]_3\ => \slaveRegDo_mux_0_reg[6]_3\,
      \slaveRegDo_mux_0_reg[6]_4\ => \slaveRegDo_mux_0_reg[6]_4\,
      \slaveRegDo_mux_0_reg[6]_5\ => \slaveRegDo_mux_0_reg[6]_5\,
      \slaveRegDo_mux_0_reg[6]_6\ => \slaveRegDo_mux_0_reg[6]_6\,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0_reg[7]\,
      \slaveRegDo_mux_0_reg[8]\ => \slaveRegDo_mux_0_reg[8]\,
      \slaveRegDo_mux_0_reg[9]\ => \slaveRegDo_mux_0_reg[9]\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized39\ is
  port (
    \G_1PIPE_IFACE.s_daddr_r_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_0[7]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[7]_i_3_0\ : in STD_LOGIC;
    in0 : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_0[2]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_2\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized39\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized39\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized39\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_42
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[2]\ => \G_1PIPE_IFACE.s_daddr_r_reg[2]\,
      Q(0) => Q(0),
      in0 => in0,
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \slaveRegDo_mux_0[1]_i_2\ => \slaveRegDo_mux_0[1]_i_2\,
      \slaveRegDo_mux_0[2]_i_2\(1 downto 0) => \slaveRegDo_mux_0[2]_i_2\(1 downto 0),
      \slaveRegDo_mux_0[2]_i_2_0\ => \slaveRegDo_mux_0[2]_i_2_0\,
      \slaveRegDo_mux_0[3]_i_2\ => \slaveRegDo_mux_0[3]_i_2\,
      \slaveRegDo_mux_0[7]_i_3_0\ => \slaveRegDo_mux_0[7]_i_3\,
      \slaveRegDo_mux_0[7]_i_3_1\ => \slaveRegDo_mux_0[7]_i_3_0\,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0_reg[7]\,
      \slaveRegDo_mux_0_reg[7]_0\ => \slaveRegDo_mux_0_reg[7]_0\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized40\ is
  port (
    \G_1PIPE_IFACE.s_daddr_r_reg[1]\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_2_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_2_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized40\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized40\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized40\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_41
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[1]\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\ => \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\,
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \slaveRegDo_mux_0[0]_i_2\ => \slaveRegDo_mux_0[0]_i_2\,
      \slaveRegDo_mux_0[0]_i_2_0\ => \slaveRegDo_mux_0[0]_i_2_0\,
      \slaveRegDo_mux_0[5]_i_2\ => \slaveRegDo_mux_0[5]_i_2\,
      \slaveRegDo_mux_0[5]_i_2_0\ => \slaveRegDo_mux_0[5]_i_2_0\,
      \slaveRegDo_mux_0[6]_i_2\ => \slaveRegDo_mux_0[6]_i_2\,
      \slaveRegDo_mux_0[6]_i_2_0\ => \slaveRegDo_mux_0[6]_i_2_0\,
      \slaveRegDo_mux_0_reg[10]\ => \slaveRegDo_mux_0_reg[10]\,
      \slaveRegDo_mux_0_reg[10]_0\ => \slaveRegDo_mux_0_reg[10]_0\,
      \slaveRegDo_mux_0_reg[11]\ => \slaveRegDo_mux_0_reg[11]\,
      \slaveRegDo_mux_0_reg[11]_0\ => \slaveRegDo_mux_0_reg[11]_0\,
      \slaveRegDo_mux_0_reg[12]\ => \slaveRegDo_mux_0_reg[12]\,
      \slaveRegDo_mux_0_reg[12]_0\ => \slaveRegDo_mux_0_reg[12]_0\,
      \slaveRegDo_mux_0_reg[13]\ => \slaveRegDo_mux_0_reg[13]\,
      \slaveRegDo_mux_0_reg[13]_0\ => \slaveRegDo_mux_0_reg[13]_0\,
      \slaveRegDo_mux_0_reg[14]\ => \slaveRegDo_mux_0_reg[14]\,
      \slaveRegDo_mux_0_reg[14]_0\ => \slaveRegDo_mux_0_reg[14]_0\,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0_reg[15]\,
      \slaveRegDo_mux_0_reg[15]_0\ => \slaveRegDo_mux_0_reg[15]_0\,
      \slaveRegDo_mux_0_reg[4]\ => \slaveRegDo_mux_0_reg[4]\,
      \slaveRegDo_mux_0_reg[4]_0\ => \slaveRegDo_mux_0_reg[4]_0\,
      \slaveRegDo_mux_0_reg[4]_1\ => \slaveRegDo_mux_0_reg[4]_1\,
      \slaveRegDo_mux_0_reg[8]\ => \slaveRegDo_mux_0_reg[8]\,
      \slaveRegDo_mux_0_reg[8]_0\ => \slaveRegDo_mux_0_reg[8]_0\,
      \slaveRegDo_mux_0_reg[9]\ => \slaveRegDo_mux_0_reg[9]\,
      \slaveRegDo_mux_0_reg[9]_0\ => \slaveRegDo_mux_0_reg[9]_0\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized41\ is
  port (
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    in0 : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized41\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized41\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized41\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_40\
     port map (
      in0 => in0,
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[2]_0\(1 downto 0) => \xsdb_reg_reg[2]\(1 downto 0),
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized42\ is
  port (
    \G_1PIPE_IFACE.s_den_r_reg\ : out STD_LOGIC;
    \G_1PIPE_IFACE.s_daddr_r_reg[6]\ : out STD_LOGIC;
    slaveRegDo_80 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_den_o : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized42\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized42\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized42\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1_37\
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[6]\ => \G_1PIPE_IFACE.s_daddr_r_reg[6]\,
      \G_1PIPE_IFACE.s_den_r_reg\ => \G_1PIPE_IFACE.s_den_r_reg\,
      s_daddr_o(12 downto 0) => s_daddr_o(12 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      s_dwe_o => s_dwe_o,
      slaveRegDo_80(15 downto 0) => slaveRegDo_80(15 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized43\ is
  port (
    D : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_1\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_3\ : in STD_LOGIC;
    slaveRegDo_84 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_0_reg[0]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_4\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[1]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[2]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[3]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[4]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[6]\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[7]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[8]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[9]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[10]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[11]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[12]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[13]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[14]_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0_reg[15]_5\ : in STD_LOGIC;
    \slaveRegDo_mux_0[15]_i_2\ : in STD_LOGIC;
    slaveRegDo_80 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    slaveRegDo_82 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_mux_0[14]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[13]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[12]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[11]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[10]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[9]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[8]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[7]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[6]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[5]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[4]_i_2\ : in STD_LOGIC;
    \slaveRegDo_mux_0[3]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[2]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[1]_i_3\ : in STD_LOGIC;
    \slaveRegDo_mux_0[0]_i_3\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized43\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized43\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized43\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_36
     port map (
      D(9 downto 0) => D(9 downto 0),
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      slaveRegDo_80(15 downto 0) => slaveRegDo_80(15 downto 0),
      slaveRegDo_82(15 downto 0) => slaveRegDo_82(15 downto 0),
      slaveRegDo_84(15 downto 0) => slaveRegDo_84(15 downto 0),
      \slaveRegDo_mux_0[0]_i_3_0\ => \slaveRegDo_mux_0[0]_i_3\,
      \slaveRegDo_mux_0[10]_i_2_0\ => \slaveRegDo_mux_0[10]_i_2\,
      \slaveRegDo_mux_0[11]_i_2_0\ => \slaveRegDo_mux_0[11]_i_2\,
      \slaveRegDo_mux_0[12]_i_2_0\ => \slaveRegDo_mux_0[12]_i_2\,
      \slaveRegDo_mux_0[13]_i_2_0\ => \slaveRegDo_mux_0[13]_i_2\,
      \slaveRegDo_mux_0[14]_i_2_0\ => \slaveRegDo_mux_0[14]_i_2\,
      \slaveRegDo_mux_0[15]_i_2_0\ => \slaveRegDo_mux_0[15]_i_2\,
      \slaveRegDo_mux_0[1]_i_3_0\ => \slaveRegDo_mux_0[1]_i_3\,
      \slaveRegDo_mux_0[2]_i_3_0\ => \slaveRegDo_mux_0[2]_i_3\,
      \slaveRegDo_mux_0[3]_i_3_0\ => \slaveRegDo_mux_0[3]_i_3\,
      \slaveRegDo_mux_0[4]_i_2_0\ => \slaveRegDo_mux_0[4]_i_2\,
      \slaveRegDo_mux_0[5]_i_3_0\ => \slaveRegDo_mux_0[5]_i_3\,
      \slaveRegDo_mux_0[6]_i_3_0\ => \slaveRegDo_mux_0[6]_i_3\,
      \slaveRegDo_mux_0[7]_i_2_0\ => \slaveRegDo_mux_0[7]_i_2\,
      \slaveRegDo_mux_0[8]_i_2_0\ => \slaveRegDo_mux_0[8]_i_2\,
      \slaveRegDo_mux_0[9]_i_2_0\ => \slaveRegDo_mux_0[9]_i_2\,
      \slaveRegDo_mux_0_reg[0]\ => \slaveRegDo_mux_0_reg[0]\,
      \slaveRegDo_mux_0_reg[10]\ => \slaveRegDo_mux_0_reg[10]\,
      \slaveRegDo_mux_0_reg[10]_0\ => \slaveRegDo_mux_0_reg[10]_0\,
      \slaveRegDo_mux_0_reg[10]_1\ => \slaveRegDo_mux_0_reg[10]_1\,
      \slaveRegDo_mux_0_reg[10]_2\ => \slaveRegDo_mux_0_reg[10]_2\,
      \slaveRegDo_mux_0_reg[11]\ => \slaveRegDo_mux_0_reg[11]\,
      \slaveRegDo_mux_0_reg[11]_0\ => \slaveRegDo_mux_0_reg[11]_0\,
      \slaveRegDo_mux_0_reg[11]_1\ => \slaveRegDo_mux_0_reg[11]_1\,
      \slaveRegDo_mux_0_reg[11]_2\ => \slaveRegDo_mux_0_reg[11]_2\,
      \slaveRegDo_mux_0_reg[12]\ => \slaveRegDo_mux_0_reg[12]\,
      \slaveRegDo_mux_0_reg[12]_0\ => \slaveRegDo_mux_0_reg[12]_0\,
      \slaveRegDo_mux_0_reg[12]_1\ => \slaveRegDo_mux_0_reg[12]_1\,
      \slaveRegDo_mux_0_reg[12]_2\ => \slaveRegDo_mux_0_reg[12]_2\,
      \slaveRegDo_mux_0_reg[13]\ => \slaveRegDo_mux_0_reg[13]\,
      \slaveRegDo_mux_0_reg[13]_0\ => \slaveRegDo_mux_0_reg[13]_0\,
      \slaveRegDo_mux_0_reg[13]_1\ => \slaveRegDo_mux_0_reg[13]_1\,
      \slaveRegDo_mux_0_reg[13]_2\ => \slaveRegDo_mux_0_reg[13]_2\,
      \slaveRegDo_mux_0_reg[14]\ => \slaveRegDo_mux_0_reg[14]\,
      \slaveRegDo_mux_0_reg[14]_0\ => \slaveRegDo_mux_0_reg[14]_0\,
      \slaveRegDo_mux_0_reg[14]_1\ => \slaveRegDo_mux_0_reg[14]_1\,
      \slaveRegDo_mux_0_reg[14]_2\ => \slaveRegDo_mux_0_reg[14]_2\,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0_reg[15]\,
      \slaveRegDo_mux_0_reg[15]_0\ => \slaveRegDo_mux_0_reg[15]_0\,
      \slaveRegDo_mux_0_reg[15]_1\ => \slaveRegDo_mux_0_reg[15]_1\,
      \slaveRegDo_mux_0_reg[15]_2\ => \slaveRegDo_mux_0_reg[15]_2\,
      \slaveRegDo_mux_0_reg[15]_3\ => \slaveRegDo_mux_0_reg[15]_3\,
      \slaveRegDo_mux_0_reg[15]_4\ => \slaveRegDo_mux_0_reg[15]_4\,
      \slaveRegDo_mux_0_reg[15]_5\ => \slaveRegDo_mux_0_reg[15]_5\,
      \slaveRegDo_mux_0_reg[1]\ => \slaveRegDo_mux_0_reg[1]\,
      \slaveRegDo_mux_0_reg[2]\ => \slaveRegDo_mux_0_reg[2]\,
      \slaveRegDo_mux_0_reg[3]\ => \slaveRegDo_mux_0_reg[3]\,
      \slaveRegDo_mux_0_reg[4]\ => \slaveRegDo_mux_0_reg[4]\,
      \slaveRegDo_mux_0_reg[4]_0\ => \slaveRegDo_mux_0_reg[4]_0\,
      \slaveRegDo_mux_0_reg[4]_1\ => \slaveRegDo_mux_0_reg[4]_1\,
      \slaveRegDo_mux_0_reg[4]_2\ => \slaveRegDo_mux_0_reg[4]_2\,
      \slaveRegDo_mux_0_reg[5]\ => \slaveRegDo_mux_0_reg[5]\,
      \slaveRegDo_mux_0_reg[6]\ => \slaveRegDo_mux_0_reg[6]\,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0_reg[7]\,
      \slaveRegDo_mux_0_reg[7]_0\ => \slaveRegDo_mux_0_reg[7]_0\,
      \slaveRegDo_mux_0_reg[7]_1\ => \slaveRegDo_mux_0_reg[7]_1\,
      \slaveRegDo_mux_0_reg[7]_2\ => \slaveRegDo_mux_0_reg[7]_2\,
      \slaveRegDo_mux_0_reg[8]\ => \slaveRegDo_mux_0_reg[8]\,
      \slaveRegDo_mux_0_reg[8]_0\ => \slaveRegDo_mux_0_reg[8]_0\,
      \slaveRegDo_mux_0_reg[8]_1\ => \slaveRegDo_mux_0_reg[8]_1\,
      \slaveRegDo_mux_0_reg[8]_2\ => \slaveRegDo_mux_0_reg[8]_2\,
      \slaveRegDo_mux_0_reg[9]\ => \slaveRegDo_mux_0_reg[9]\,
      \slaveRegDo_mux_0_reg[9]_0\ => \slaveRegDo_mux_0_reg[9]_0\,
      \slaveRegDo_mux_0_reg[9]_1\ => \slaveRegDo_mux_0_reg[9]_1\,
      \slaveRegDo_mux_0_reg[9]_2\ => \slaveRegDo_mux_0_reg[9]_2\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized44\ is
  port (
    slaveRegDo_82 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized44\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized44\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized44\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_ctl__parameterized1\
     port map (
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      slaveRegDo_82(15 downto 0) => slaveRegDo_82(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized45\ is
  port (
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized45\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized45\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized45\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_35
     port map (
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized46\ is
  port (
    slaveRegDo_84 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized46\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized46\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized46\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_34
     port map (
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      slaveRegDo_84(15 downto 0) => slaveRegDo_84(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized47\ is
  port (
    \xsdb_reg_reg[15]\ : out STD_LOGIC;
    \xsdb_reg_reg[14]\ : out STD_LOGIC;
    \xsdb_reg_reg[13]\ : out STD_LOGIC;
    \xsdb_reg_reg[12]\ : out STD_LOGIC;
    \xsdb_reg_reg[11]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[9]\ : out STD_LOGIC;
    \xsdb_reg_reg[8]\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[6]\ : out STD_LOGIC;
    \xsdb_reg_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[0]\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized47\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized47\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized47\ is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl_33
     port map (
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[11]_0\ => \xsdb_reg_reg[11]\,
      \xsdb_reg_reg[12]_0\ => \xsdb_reg_reg[12]\,
      \xsdb_reg_reg[13]_0\ => \xsdb_reg_reg[13]\,
      \xsdb_reg_reg[14]_0\ => \xsdb_reg_reg[14]\,
      \xsdb_reg_reg[15]_0\ => \xsdb_reg_reg[15]\,
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\,
      \xsdb_reg_reg[5]_0\ => \xsdb_reg_reg[5]\,
      \xsdb_reg_reg[6]_0\ => \xsdb_reg_reg[6]\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\,
      \xsdb_reg_reg[8]_0\ => \xsdb_reg_reg[8]\,
      \xsdb_reg_reg[9]_0\ => \xsdb_reg_reg[9]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized49\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_den_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[3]\ : in STD_LOGIC;
    s_do_o : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_2_reg[3]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    slaveRegDo_mux_211_in : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized49\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized49\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized49\ is
begin
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat_32
     port map (
      D(0) => D(0),
      \out\ => \out\,
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      s_do_o(0) => s_do_o(0),
      slaveRegDo_mux_211_in => slaveRegDo_mux_211_in,
      \slaveRegDo_mux_2_reg[3]\ => \slaveRegDo_mux_2_reg[3]\,
      \slaveRegDo_mux_2_reg[3]_0\ => \slaveRegDo_mux_2_reg[3]_0\,
      \slaveRegDo_mux_2_reg[3]_1\(0) => \slaveRegDo_mux_2_reg[3]_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized51\ is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_2_reg[1]\ : in STD_LOGIC;
    s_do_o : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \slaveRegDo_mux_2_reg[1]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_2_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    slaveRegDo_mux_211_in : in STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    s_den_o : in STD_LOGIC;
    \xsdb_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized51\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized51\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized51\ is
begin
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat_31
     port map (
      D(1 downto 0) => D(1 downto 0),
      s_daddr_o(4 downto 0) => s_daddr_o(4 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      s_do_o(1 downto 0) => s_do_o(1 downto 0),
      slaveRegDo_mux_211_in => slaveRegDo_mux_211_in,
      \slaveRegDo_mux_2_reg[1]\ => \slaveRegDo_mux_2_reg[1]\,
      \slaveRegDo_mux_2_reg[1]_0\ => \slaveRegDo_mux_2_reg[1]_0\,
      \slaveRegDo_mux_2_reg[1]_1\(1 downto 0) => \slaveRegDo_mux_2_reg[1]_1\(1 downto 0),
      \xsdb_reg_reg[1]_0\(1 downto 0) => \xsdb_reg_reg[1]\(1 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ is
  port (
    s_do_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
    dout_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_reg_i : in STD_LOGIC;
    din_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_daddr_i : in STD_LOGIC_VECTOR ( 12 downto 0 );
    s_di_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_den_i : in STD_LOGIC;
    s_dwe_i : in STD_LOGIC;
    s_dclk_i : in STD_LOGIC
  );
  attribute C_ADDR_W : integer;
  attribute C_ADDR_W of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is 13;
  attribute C_CTLRST_VAL : string;
  attribute C_CTLRST_VAL of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is "47'b00000000000000000000000000000000000000000000000";
  attribute C_DATA_W : integer;
  attribute C_DATA_W of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is 16;
  attribute C_EN_CTL : integer;
  attribute C_EN_CTL of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is 0;
  attribute C_EN_STAT : integer;
  attribute C_EN_STAT of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is 1;
  attribute C_REG_ADDR : string;
  attribute C_REG_ADDR of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is "13'b0100010010000";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ : entity is "xsdbs_v1_0_2_reg";
end \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\ is
  signal \<const0>\ : STD_LOGIC;
begin
  dout_o(15) <= \<const0>\;
  dout_o(14) <= \<const0>\;
  dout_o(13) <= \<const0>\;
  dout_o(12) <= \<const0>\;
  dout_o(11) <= \<const0>\;
  dout_o(10) <= \<const0>\;
  dout_o(9) <= \<const0>\;
  dout_o(8) <= \<const0>\;
  dout_o(7) <= \<const0>\;
  dout_o(6) <= \<const0>\;
  dout_o(5) <= \<const0>\;
  dout_o(4) <= \<const0>\;
  dout_o(3) <= \<const0>\;
  dout_o(2) <= \<const0>\;
  dout_o(1) <= \<const0>\;
  dout_o(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat_46
     port map (
      din_i(15 downto 0) => din_i(15 downto 0),
      s_dclk_i => s_dclk_i,
      s_den_i => s_den_i,
      s_do_o(15 downto 0) => s_do_o(15 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_xsdbs_v1_0_2_reg_stream is
  port (
    \slaveRegDo_ffa_reg[5]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \slaveRegDo_ffa_reg[5]_0\ : out STD_LOGIC;
    \xsdb_reg_reg[7]\ : out STD_LOGIC;
    \xsdb_reg_reg[10]\ : out STD_LOGIC;
    \xsdb_reg_reg[15]_0\ : out STD_LOGIC;
    s_daddr_o : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \xsdb_reg_reg[0]\ : in STD_LOGIC;
    \xsdb_reg_reg[0]_0\ : in STD_LOGIC;
    s_dwe_o : in STD_LOGIC;
    s_den_o : in STD_LOGIC;
    slaveRegDo_ffa : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \slaveRegDo_mux_3_reg[5]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[5]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[7]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[10]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[15]_1\ : in STD_LOGIC;
    s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_xsdbs_v1_0_2_reg_stream : entity is "xsdbs_v1_0_2_reg_stream";
end ila_full_aurora_xsdbs_v1_0_2_reg_stream;

architecture STRUCTURE of ila_full_aurora_xsdbs_v1_0_2_reg_stream is
begin
\I_EN_CTL_EQ1.U_CTL\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_ctl
     port map (
      Q(4 downto 0) => Q(4 downto 0),
      s_daddr_o(5 downto 0) => s_daddr_o(5 downto 0),
      s_dclk_o => s_dclk_o,
      s_den_o => s_den_o,
      s_di_o(15 downto 0) => s_di_o(15 downto 0),
      s_dwe_o => s_dwe_o,
      slaveRegDo_ffa(0) => slaveRegDo_ffa(0),
      \slaveRegDo_ffa_reg[5]\ => \slaveRegDo_ffa_reg[5]\,
      \slaveRegDo_ffa_reg[5]_0\ => \slaveRegDo_ffa_reg[5]_0\,
      \slaveRegDo_mux_3_reg[10]\ => \slaveRegDo_mux_3_reg[10]\,
      \slaveRegDo_mux_3_reg[15]\ => \slaveRegDo_mux_3_reg[15]\,
      \slaveRegDo_mux_3_reg[15]_0\ => \slaveRegDo_mux_3_reg[15]_0\,
      \slaveRegDo_mux_3_reg[15]_1\ => \slaveRegDo_mux_3_reg[15]_1\,
      \slaveRegDo_mux_3_reg[5]\ => \slaveRegDo_mux_3_reg[5]\,
      \slaveRegDo_mux_3_reg[5]_0\ => \slaveRegDo_mux_3_reg[5]_0\,
      \slaveRegDo_mux_3_reg[7]\ => \slaveRegDo_mux_3_reg[7]\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg_reg[0]\,
      \xsdb_reg_reg[0]_1\ => \xsdb_reg_reg[0]_0\,
      \xsdb_reg_reg[10]_0\ => \xsdb_reg_reg[10]\,
      \xsdb_reg_reg[15]_0\(15 downto 0) => \xsdb_reg_reg[15]\(15 downto 0),
      \xsdb_reg_reg[15]_1\ => \xsdb_reg_reg[15]_0\,
      \xsdb_reg_reg[7]_0\ => \xsdb_reg_reg[7]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_xsdbs_v1_0_2_reg_stream__parameterized0\ is
  port (
    \xsdb_reg_reg[1]\ : out STD_LOGIC;
    \xsdb_reg_reg[2]\ : out STD_LOGIC;
    \xsdb_reg_reg[3]\ : out STD_LOGIC;
    \xsdb_reg_reg[4]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \slaveRegDo_mux_3_reg[4]\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[4]_0\ : in STD_LOGIC;
    \slaveRegDo_mux_3_reg[4]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    slaveRegDo_ffa : in STD_LOGIC_VECTOR ( 0 to 0 );
    \slaveRegDo_mux_3_reg[4]_2\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \xsdb_reg_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_dclk_o : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_xsdbs_v1_0_2_reg_stream__parameterized0\ : entity is "xsdbs_v1_0_2_reg_stream";
end \ila_full_aurora_xsdbs_v1_0_2_reg_stream__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_xsdbs_v1_0_2_reg_stream__parameterized0\ is
begin
\I_EN_STAT_EQ1.U_STAT\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stat
     port map (
      E(0) => E(0),
      Q(11 downto 0) => Q(11 downto 0),
      s_dclk_o => s_dclk_o,
      slaveRegDo_ffa(0) => slaveRegDo_ffa(0),
      \slaveRegDo_mux_3_reg[4]\ => \slaveRegDo_mux_3_reg[4]\,
      \slaveRegDo_mux_3_reg[4]_0\ => \slaveRegDo_mux_3_reg[4]_0\,
      \slaveRegDo_mux_3_reg[4]_1\(3 downto 0) => \slaveRegDo_mux_3_reg[4]_1\(3 downto 0),
      \slaveRegDo_mux_3_reg[4]_2\ => \slaveRegDo_mux_3_reg[4]_2\,
      \xsdb_reg_reg[15]_0\(15 downto 0) => \xsdb_reg_reg[15]\(15 downto 0),
      \xsdb_reg_reg[1]_0\ => \xsdb_reg_reg[1]\,
      \xsdb_reg_reg[2]_0\ => \xsdb_reg_reg[2]\,
      \xsdb_reg_reg[3]_0\ => \xsdb_reg_reg[3]\,
      \xsdb_reg_reg[4]_0\ => \xsdb_reg_reg[4]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr is
  port (
    D : out STD_LOGIC_VECTOR ( 138 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr";
end ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width
     port map (
      D(35 downto 0) => D(35 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\ramloop[1].ram.r\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized0\
     port map (
      D(35 downto 0) => D(71 downto 36),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\ramloop[2].ram.r\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized1\
     port map (
      D(35 downto 0) => D(107 downto 72),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\ramloop[3].ram.r\: entity work.\ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_prim_width__parameterized2\
     port map (
      D(30 downto 0) => D(138 downto 108),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_register is
  port (
    s_dclk_o : out STD_LOGIC;
    sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
    capture_ctrl_config_serial_output : out STD_LOGIC;
    tc_config_cs_serial_output : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : out STD_LOGIC_VECTOR ( 5 downto 0 );
    shift_en_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \G_1PIPE_IFACE.s_daddr_r_reg[5]\ : out STD_LOGIC;
    read_data_en : out STD_LOGIC;
    next_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \curr_read_block_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    arm_ctrl : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    read_reset_addr : out STD_LOGIC_VECTOR ( 9 downto 0 );
    in0 : out STD_LOGIC;
    use_probe_debug_circuit_1 : out STD_LOGIC;
    capture_qual_ctrl_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    halt_ctrl : out STD_LOGIC;
    debug_data_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
    scnt_cmp_temp : out STD_LOGIC;
    wcnt_lcmp_temp : out STD_LOGIC;
    wcnt_hcmp_temp : out STD_LOGIC;
    mu_config_cs_serial_output : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \out\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \parallel_dout_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ila_clk_flag_reg_0 : in STD_LOGIC;
    dummy_temp1_reg_0 : in STD_LOGIC;
    read_en_i_2 : in STD_LOGIC;
    read_en_i_2_0 : in STD_LOGIC;
    read_en_i_2_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \current_state_reg[5]\ : in STD_LOGIC;
    \current_state_reg[5]_0\ : in STD_LOGIC;
    \current_state_reg[6]\ : in STD_LOGIC;
    DOUT_O : in STD_LOGIC;
    u_wcnt_lcmp_q : in STD_LOGIC;
    u_wcnt_hcmp_q : in STD_LOGIC;
    mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \xsdb_reg_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \xsdb_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \xsdb_reg_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \xsdb_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_register : entity is "ila_v6_2_10_ila_register";
end ila_full_aurora_ila_v6_2_10_ila_register;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_register is
  signal \MU_SRL[0].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_19\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[0].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[1].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[2].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[3].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[4].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_0\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_10\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_11\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_12\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_13\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_14\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_15\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_16\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_17\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_18\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_2\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_3\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_4\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_5\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_6\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_7\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_8\ : STD_LOGIC;
  signal \MU_SRL[5].mu_srl_reg_n_9\ : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \TC_SRL[0].tc_srl_reg_n_10\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_11\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_12\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_13\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_14\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_15\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_16\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_17\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_18\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_2\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_3\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_4\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_5\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_6\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_7\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_8\ : STD_LOGIC;
  signal \TC_SRL[0].tc_srl_reg_n_9\ : STD_LOGIC;
  signal adv_drdy : STD_LOGIC;
  signal adv_drdy_i_1_n_0 : STD_LOGIC;
  signal adv_drdy_i_2_n_0 : STD_LOGIC;
  signal adv_rb_drdy3_reg_srl4_n_0 : STD_LOGIC;
  signal adv_rb_drdy4 : STD_LOGIC;
  signal \^capture_qual_ctrl_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal clk_lost : STD_LOGIC;
  signal \clk_lost_cnt[8]_i_1_n_0\ : STD_LOGIC;
  signal \clk_lost_cnt[8]_i_2_n_0\ : STD_LOGIC;
  signal \clk_lost_cnt[8]_i_4_n_0\ : STD_LOGIC;
  signal clk_lost_cnt_reg : STD_LOGIC_VECTOR ( 8 to 8 );
  signal \clk_lost_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \clk_lost_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal clk_lost_i_1_n_0 : STD_LOGIC;
  signal \count0[6]_i_1_n_0\ : STD_LOGIC;
  signal count0_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \count1[6]_i_1_n_0\ : STD_LOGIC;
  signal count1_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal count_tt : STD_LOGIC;
  signal count_tt_i_1_n_0 : STD_LOGIC;
  signal \current_state[6]_i_4_n_0\ : STD_LOGIC;
  signal \current_state[6]_i_5_n_0\ : STD_LOGIC;
  signal \^debug_data_in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drdyCount0 : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \drdyCount1__4\ : STD_LOGIC;
  signal \drdyCount[0]_i_1_n_0\ : STD_LOGIC;
  signal \drdyCount[4]_i_1_n_0\ : STD_LOGIC;
  signal \drdyCount[4]_i_2_n_0\ : STD_LOGIC;
  signal \drdyCount[4]_i_4_n_0\ : STD_LOGIC;
  signal \drdyCount[5]_i_1_n_0\ : STD_LOGIC;
  signal \drdyCount[5]_i_5_n_0\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[0]\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[1]\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[2]\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[3]\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[4]\ : STD_LOGIC;
  signal \drdyCount_reg_n_0_[5]\ : STD_LOGIC;
  signal drdy_ff7 : STD_LOGIC;
  signal drdy_ff7_i_2_n_0 : STD_LOGIC;
  signal drdy_ff8 : STD_LOGIC;
  signal drdy_ff8_i_2_n_0 : STD_LOGIC;
  signal drdy_ff9 : STD_LOGIC;
  signal drdy_ff9_i_2_n_0 : STD_LOGIC;
  signal drdy_ff9_i_3_n_0 : STD_LOGIC;
  signal drdy_ffa : STD_LOGIC;
  signal drdy_ffa_i_1_n_0 : STD_LOGIC;
  signal drdy_ffa_i_2_n_0 : STD_LOGIC;
  signal drdy_mux_ff : STD_LOGIC;
  signal drdy_mux_ff1 : STD_LOGIC;
  signal drdy_mux_ff_i_1_n_0 : STD_LOGIC;
  signal dummy_temp : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of dummy_temp : signal is std.standard.true;
  signal dummy_temp1 : STD_LOGIC;
  attribute DONT_TOUCH of dummy_temp1 : signal is std.standard.true;
  signal ila_clk_flag : STD_LOGIC;
  signal ila_clk_flag_i_1_n_0 : STD_LOGIC;
  signal ila_clk_flag_sync1 : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of ila_clk_flag_sync1 : signal is "true";
  signal ila_clk_flag_sync2 : STD_LOGIC;
  attribute async_reg of ila_clk_flag_sync2 : signal is "true";
  signal \^in0\ : STD_LOGIC;
  signal \isSRLAddress__0\ : STD_LOGIC;
  signal \^next_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal next_state_ila : STD_LOGIC;
  signal next_state_xsdb : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_0_in1_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC_VECTOR ( 5 to 5 );
  signal \^read_data_en\ : STD_LOGIC;
  signal \^read_reset_addr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal regAck_reg : STD_LOGIC;
  signal \regAck_reg_n_0_[1]\ : STD_LOGIC;
  signal regAck_temp : STD_LOGIC;
  signal regAck_temp_reg : STD_LOGIC;
  signal regDrdy_i_1_n_0 : STD_LOGIC;
  signal regDrdy_i_2_n_0 : STD_LOGIC;
  signal regDrdy_i_4_n_0 : STD_LOGIC;
  signal regDrdy_i_5_n_0 : STD_LOGIC;
  signal regDrdy_i_6_n_0 : STD_LOGIC;
  signal regDrdy_reg_n_0 : STD_LOGIC;
  signal reg_15_n_0 : STD_LOGIC;
  signal reg_15_n_1 : STD_LOGIC;
  signal reg_15_n_10 : STD_LOGIC;
  signal reg_15_n_11 : STD_LOGIC;
  signal reg_15_n_12 : STD_LOGIC;
  signal reg_15_n_14 : STD_LOGIC;
  signal reg_15_n_2 : STD_LOGIC;
  signal reg_15_n_3 : STD_LOGIC;
  signal reg_15_n_4 : STD_LOGIC;
  signal reg_15_n_5 : STD_LOGIC;
  signal reg_15_n_6 : STD_LOGIC;
  signal reg_15_n_7 : STD_LOGIC;
  signal reg_15_n_8 : STD_LOGIC;
  signal reg_15_n_9 : STD_LOGIC;
  signal reg_16_n_0 : STD_LOGIC;
  signal reg_16_n_11 : STD_LOGIC;
  signal reg_16_n_12 : STD_LOGIC;
  signal reg_16_n_13 : STD_LOGIC;
  signal reg_16_n_14 : STD_LOGIC;
  signal reg_16_n_15 : STD_LOGIC;
  signal reg_16_n_16 : STD_LOGIC;
  signal reg_16_n_17 : STD_LOGIC;
  signal reg_16_n_18 : STD_LOGIC;
  signal reg_17_n_0 : STD_LOGIC;
  signal reg_17_n_1 : STD_LOGIC;
  signal reg_17_n_10 : STD_LOGIC;
  signal reg_17_n_11 : STD_LOGIC;
  signal reg_17_n_12 : STD_LOGIC;
  signal reg_17_n_13 : STD_LOGIC;
  signal reg_17_n_14 : STD_LOGIC;
  signal reg_17_n_15 : STD_LOGIC;
  signal reg_17_n_2 : STD_LOGIC;
  signal reg_17_n_3 : STD_LOGIC;
  signal reg_17_n_4 : STD_LOGIC;
  signal reg_17_n_5 : STD_LOGIC;
  signal reg_17_n_6 : STD_LOGIC;
  signal reg_17_n_7 : STD_LOGIC;
  signal reg_17_n_8 : STD_LOGIC;
  signal reg_17_n_9 : STD_LOGIC;
  signal reg_18_n_0 : STD_LOGIC;
  signal reg_18_n_1 : STD_LOGIC;
  signal reg_18_n_10 : STD_LOGIC;
  signal reg_18_n_11 : STD_LOGIC;
  signal reg_18_n_12 : STD_LOGIC;
  signal reg_18_n_13 : STD_LOGIC;
  signal reg_18_n_14 : STD_LOGIC;
  signal reg_18_n_15 : STD_LOGIC;
  signal reg_18_n_2 : STD_LOGIC;
  signal reg_18_n_3 : STD_LOGIC;
  signal reg_18_n_4 : STD_LOGIC;
  signal reg_18_n_5 : STD_LOGIC;
  signal reg_18_n_6 : STD_LOGIC;
  signal reg_18_n_7 : STD_LOGIC;
  signal reg_18_n_8 : STD_LOGIC;
  signal reg_18_n_9 : STD_LOGIC;
  signal reg_19_n_0 : STD_LOGIC;
  signal reg_19_n_1 : STD_LOGIC;
  signal reg_19_n_10 : STD_LOGIC;
  signal reg_19_n_11 : STD_LOGIC;
  signal reg_19_n_12 : STD_LOGIC;
  signal reg_19_n_13 : STD_LOGIC;
  signal reg_19_n_14 : STD_LOGIC;
  signal reg_19_n_15 : STD_LOGIC;
  signal reg_19_n_2 : STD_LOGIC;
  signal reg_19_n_3 : STD_LOGIC;
  signal reg_19_n_4 : STD_LOGIC;
  signal reg_19_n_5 : STD_LOGIC;
  signal reg_19_n_6 : STD_LOGIC;
  signal reg_19_n_7 : STD_LOGIC;
  signal reg_19_n_8 : STD_LOGIC;
  signal reg_19_n_9 : STD_LOGIC;
  signal reg_1a_n_0 : STD_LOGIC;
  signal reg_1a_n_1 : STD_LOGIC;
  signal reg_1a_n_10 : STD_LOGIC;
  signal reg_1a_n_11 : STD_LOGIC;
  signal reg_1a_n_15 : STD_LOGIC;
  signal reg_1a_n_2 : STD_LOGIC;
  signal reg_1a_n_3 : STD_LOGIC;
  signal reg_1a_n_4 : STD_LOGIC;
  signal reg_1a_n_5 : STD_LOGIC;
  signal reg_1a_n_6 : STD_LOGIC;
  signal reg_1a_n_7 : STD_LOGIC;
  signal reg_1a_n_8 : STD_LOGIC;
  signal reg_1a_n_9 : STD_LOGIC;
  signal reg_6_n_0 : STD_LOGIC;
  signal reg_6_n_1 : STD_LOGIC;
  signal reg_6_n_14 : STD_LOGIC;
  signal reg_6_n_15 : STD_LOGIC;
  signal reg_6_n_16 : STD_LOGIC;
  signal reg_7_n_0 : STD_LOGIC;
  signal reg_7_n_1 : STD_LOGIC;
  signal reg_7_n_10 : STD_LOGIC;
  signal reg_7_n_11 : STD_LOGIC;
  signal reg_7_n_12 : STD_LOGIC;
  signal reg_7_n_13 : STD_LOGIC;
  signal reg_7_n_14 : STD_LOGIC;
  signal reg_7_n_15 : STD_LOGIC;
  signal reg_7_n_17 : STD_LOGIC;
  signal reg_7_n_2 : STD_LOGIC;
  signal reg_7_n_3 : STD_LOGIC;
  signal reg_7_n_4 : STD_LOGIC;
  signal reg_7_n_6 : STD_LOGIC;
  signal reg_7_n_7 : STD_LOGIC;
  signal reg_7_n_8 : STD_LOGIC;
  signal reg_7_n_9 : STD_LOGIC;
  signal reg_80_n_0 : STD_LOGIC;
  signal reg_80_n_1 : STD_LOGIC;
  signal reg_81_n_0 : STD_LOGIC;
  signal reg_81_n_1 : STD_LOGIC;
  signal reg_81_n_10 : STD_LOGIC;
  signal reg_81_n_11 : STD_LOGIC;
  signal reg_81_n_12 : STD_LOGIC;
  signal reg_81_n_13 : STD_LOGIC;
  signal reg_81_n_14 : STD_LOGIC;
  signal reg_81_n_15 : STD_LOGIC;
  signal reg_81_n_2 : STD_LOGIC;
  signal reg_81_n_3 : STD_LOGIC;
  signal reg_81_n_4 : STD_LOGIC;
  signal reg_81_n_5 : STD_LOGIC;
  signal reg_81_n_6 : STD_LOGIC;
  signal reg_81_n_7 : STD_LOGIC;
  signal reg_81_n_8 : STD_LOGIC;
  signal reg_81_n_9 : STD_LOGIC;
  signal reg_83_n_0 : STD_LOGIC;
  signal reg_83_n_1 : STD_LOGIC;
  signal reg_83_n_10 : STD_LOGIC;
  signal reg_83_n_11 : STD_LOGIC;
  signal reg_83_n_12 : STD_LOGIC;
  signal reg_83_n_13 : STD_LOGIC;
  signal reg_83_n_14 : STD_LOGIC;
  signal reg_83_n_15 : STD_LOGIC;
  signal reg_83_n_2 : STD_LOGIC;
  signal reg_83_n_3 : STD_LOGIC;
  signal reg_83_n_4 : STD_LOGIC;
  signal reg_83_n_5 : STD_LOGIC;
  signal reg_83_n_6 : STD_LOGIC;
  signal reg_83_n_7 : STD_LOGIC;
  signal reg_83_n_8 : STD_LOGIC;
  signal reg_83_n_9 : STD_LOGIC;
  signal reg_85_n_0 : STD_LOGIC;
  signal reg_85_n_1 : STD_LOGIC;
  signal reg_85_n_10 : STD_LOGIC;
  signal reg_85_n_11 : STD_LOGIC;
  signal reg_85_n_12 : STD_LOGIC;
  signal reg_85_n_13 : STD_LOGIC;
  signal reg_85_n_14 : STD_LOGIC;
  signal reg_85_n_15 : STD_LOGIC;
  signal reg_85_n_2 : STD_LOGIC;
  signal reg_85_n_3 : STD_LOGIC;
  signal reg_85_n_4 : STD_LOGIC;
  signal reg_85_n_5 : STD_LOGIC;
  signal reg_85_n_6 : STD_LOGIC;
  signal reg_85_n_7 : STD_LOGIC;
  signal reg_85_n_8 : STD_LOGIC;
  signal reg_85_n_9 : STD_LOGIC;
  signal reg_887_n_0 : STD_LOGIC;
  signal reg_88d_n_0 : STD_LOGIC;
  signal reg_88d_n_1 : STD_LOGIC;
  signal reg_8_n_0 : STD_LOGIC;
  signal reg_8_n_1 : STD_LOGIC;
  signal reg_8_n_2 : STD_LOGIC;
  signal reg_8_n_3 : STD_LOGIC;
  signal reg_8_n_4 : STD_LOGIC;
  signal reg_9_n_0 : STD_LOGIC;
  signal reg_9_n_1 : STD_LOGIC;
  signal reg_9_n_2 : STD_LOGIC;
  signal reg_9_n_3 : STD_LOGIC;
  signal reg_9_n_4 : STD_LOGIC;
  signal reg_9_n_5 : STD_LOGIC;
  signal reg_9_n_6 : STD_LOGIC;
  signal reg_9_n_7 : STD_LOGIC;
  signal reg_9_n_8 : STD_LOGIC;
  signal reg_9_n_9 : STD_LOGIC;
  signal reg_srl_fff_n_10 : STD_LOGIC;
  signal reg_srl_fff_n_11 : STD_LOGIC;
  signal reg_srl_fff_n_12 : STD_LOGIC;
  signal reg_srl_fff_n_13 : STD_LOGIC;
  signal reg_srl_fff_n_14 : STD_LOGIC;
  signal reg_srl_fff_n_15 : STD_LOGIC;
  signal reg_srl_fff_n_16 : STD_LOGIC;
  signal reg_srl_fff_n_17 : STD_LOGIC;
  signal reg_srl_fff_n_18 : STD_LOGIC;
  signal reg_srl_fff_n_2 : STD_LOGIC;
  signal reg_srl_fff_n_3 : STD_LOGIC;
  signal reg_srl_fff_n_4 : STD_LOGIC;
  signal reg_srl_fff_n_5 : STD_LOGIC;
  signal reg_srl_fff_n_6 : STD_LOGIC;
  signal reg_srl_fff_n_7 : STD_LOGIC;
  signal reg_srl_fff_n_8 : STD_LOGIC;
  signal reg_srl_fff_n_9 : STD_LOGIC;
  signal reg_stream_ffd_n_0 : STD_LOGIC;
  signal reg_stream_ffd_n_17 : STD_LOGIC;
  signal reg_stream_ffd_n_18 : STD_LOGIC;
  signal reg_stream_ffd_n_19 : STD_LOGIC;
  signal reg_stream_ffd_n_20 : STD_LOGIC;
  signal reg_stream_ffe_n_0 : STD_LOGIC;
  signal reg_stream_ffe_n_1 : STD_LOGIC;
  signal reg_stream_ffe_n_10 : STD_LOGIC;
  signal reg_stream_ffe_n_11 : STD_LOGIC;
  signal reg_stream_ffe_n_12 : STD_LOGIC;
  signal reg_stream_ffe_n_13 : STD_LOGIC;
  signal reg_stream_ffe_n_14 : STD_LOGIC;
  signal reg_stream_ffe_n_15 : STD_LOGIC;
  signal reg_stream_ffe_n_2 : STD_LOGIC;
  signal reg_stream_ffe_n_3 : STD_LOGIC;
  signal reg_stream_ffe_n_4 : STD_LOGIC;
  signal reg_stream_ffe_n_5 : STD_LOGIC;
  signal reg_stream_ffe_n_6 : STD_LOGIC;
  signal reg_stream_ffe_n_7 : STD_LOGIC;
  signal reg_stream_ffe_n_8 : STD_LOGIC;
  signal reg_stream_ffe_n_9 : STD_LOGIC;
  signal s_daddr : STD_LOGIC_VECTOR ( 16 downto 0 );
  signal s_dclk_flag : STD_LOGIC;
  signal s_dclk_flag_i_1_n_0 : STD_LOGIC;
  signal s_dclk_flag_sync1 : STD_LOGIC;
  attribute async_reg of s_dclk_flag_sync1 : signal is "true";
  signal s_dclk_flag_sync2 : STD_LOGIC;
  attribute async_reg of s_dclk_flag_sync2 : signal is "true";
  signal \^s_dclk_o\ : STD_LOGIC;
  signal s_den : STD_LOGIC;
  signal s_di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal s_dwe : STD_LOGIC;
  signal s_rst : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal \shift_reg0[5]_i_1_n_0\ : STD_LOGIC;
  signal \shift_reg0[5]_i_2_n_0\ : STD_LOGIC;
  signal \shift_reg0[5]_i_3_n_0\ : STD_LOGIC;
  signal \shift_reg0_reg_n_0_[5]\ : STD_LOGIC;
  signal \shift_reg1[5]_i_1_n_0\ : STD_LOGIC;
  signal \shift_reg1[5]_i_2_n_0\ : STD_LOGIC;
  signal \shift_reg1[5]_i_3_n_0\ : STD_LOGIC;
  signal \shift_reg1_reg_n_0_[5]\ : STD_LOGIC;
  signal slaveRegDo_6 : STD_LOGIC_VECTOR ( 15 downto 3 );
  signal slaveRegDo_80 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal slaveRegDo_82 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal slaveRegDo_84 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal slaveRegDo_890 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_ff8[15]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_ff8[4]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_ff8_reg_n_0_[15]\ : STD_LOGIC;
  signal \slaveRegDo_ff8_reg_n_0_[4]\ : STD_LOGIC;
  signal slaveRegDo_ff9 : STD_LOGIC_VECTOR ( 5 to 5 );
  signal slaveRegDo_ffa : STD_LOGIC_VECTOR ( 5 to 5 );
  signal slaveRegDo_mux : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_mux[0]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[10]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[11]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[12]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[13]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[14]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[15]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[1]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[2]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[3]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[4]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[5]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[6]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[7]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[8]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux[9]_i_2_n_0\ : STD_LOGIC;
  signal slaveRegDo_mux_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_mux_01__6\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[10]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_10_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_11_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_12_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_13_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_14_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_3_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_7_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[15]_i_9_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[3]_i_9_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[6]_i_10_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[7]_i_8_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_0[9]_i_7_n_0\ : STD_LOGIC;
  signal slaveRegDo_mux_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \slaveRegDo_mux_1[0]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_1[1]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_1[2]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_1[3]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_1[5]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_1[6]_i_1_n_0\ : STD_LOGIC;
  signal slaveRegDo_mux_2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal slaveRegDo_mux_211_in : STD_LOGIC;
  signal \slaveRegDo_mux_2[15]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[2]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[3]_i_3_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[3]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[5]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[6]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[6]_i_3_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_2[6]_i_4_n_0\ : STD_LOGIC;
  signal slaveRegDo_mux_3 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_mux_3[14]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[15]_i_1_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[15]_i_3_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[15]_i_4_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[4]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[5]_i_2_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[5]_i_3_n_0\ : STD_LOGIC;
  signal \slaveRegDo_mux_3[5]_i_4_n_0\ : STD_LOGIC;
  signal slaveRegDo_mux_4 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal slaveRegDo_mux_5 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \slaveRegDo_mux_reg_n_0_[0]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[10]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[11]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[12]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[13]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[14]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[15]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[1]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[2]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[3]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[4]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[5]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[6]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[7]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[8]\ : STD_LOGIC;
  signal \slaveRegDo_mux_reg_n_0_[9]\ : STD_LOGIC;
  signal \^use_probe_debug_circuit_1\ : STD_LOGIC;
  signal xsdb_rden_ff7 : STD_LOGIC;
  signal xsdb_rden_ff8 : STD_LOGIC;
  signal \xsdb_reg[15]_i_3__2_n_0\ : STD_LOGIC;
  signal \xsdb_reg[15]_i_4__1_n_0\ : STD_LOGIC;
  signal NLW_reg_890_dout_o_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute C_BUILD_REVISION : integer;
  attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
  attribute C_CORE_INFO1 : integer;
  attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is 0;
  attribute C_CORE_INFO2 : integer;
  attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is 0;
  attribute C_CORE_MAJOR_VER : integer;
  attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 6;
  attribute C_CORE_MINOR_VER : integer;
  attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 2;
  attribute C_CORE_TYPE : integer;
  attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 1;
  attribute C_CSE_DRV_VER : integer;
  attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 2;
  attribute C_MAJOR_VERSION : integer;
  attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2019;
  attribute C_MINOR_VERSION : integer;
  attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 2;
  attribute C_NEXT_SLAVE : integer;
  attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
  attribute C_PIPE_IFACE : integer;
  attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 1;
  attribute C_USE_TEST_REG : integer;
  attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "virtex7";
  attribute C_XSDB_SLAVE_TYPE : integer;
  attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 17;
  attribute DONT_TOUCH of U_XSDB_SLAVE : label is std.standard.true;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of adv_drdy_i_2 : label is "soft_lutpair78";
  attribute srl_name : string;
  attribute srl_name of adv_rb_drdy3_reg_srl4 : label is "U0/\ila_core_inst/u_ila_regs/adv_rb_drdy3_reg_srl4 ";
  attribute SOFT_HLUTNM of \clk_lost_cnt[1]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \clk_lost_cnt[2]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \clk_lost_cnt[3]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \clk_lost_cnt[4]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \clk_lost_cnt[7]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \clk_lost_cnt[8]_i_3\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \count0[0]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \count0[1]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \count0[2]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \count0[3]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \count0[4]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \count1[0]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \count1[1]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \count1[2]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \count1[3]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \count1[4]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of count_tt_i_1 : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \current_state[6]_i_5\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \drdyCount[1]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \drdyCount[2]_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \drdyCount[3]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \drdyCount[4]_i_2\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \drdyCount[4]_i_4\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of drdy_ff7_i_2 : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of drdy_ff8_i_2 : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of drdy_ff9_i_2 : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of drdy_ffa_i_2 : label is "soft_lutpair61";
  attribute DONT_TOUCH of dummy_temp1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of dummy_temp1_reg : label is "yes";
  attribute DONT_TOUCH of dummy_temp_reg : label is std.standard.true;
  attribute KEEP of dummy_temp_reg : label is "yes";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of ila_clk_flag_sync1_reg : label is std.standard.true;
  attribute KEEP of ila_clk_flag_sync1_reg : label is "yes";
  attribute ASYNC_REG_boolean of ila_clk_flag_sync2_reg : label is std.standard.true;
  attribute KEEP of ila_clk_flag_sync2_reg : label is "yes";
  attribute SOFT_HLUTNM of regDrdy_i_4 : label is "soft_lutpair65";
  attribute C_ADDR_W : integer;
  attribute C_ADDR_W of reg_890 : label is 13;
  attribute C_CTLRST_VAL : string;
  attribute C_CTLRST_VAL of reg_890 : label is "47'b00000000000000000000000000000000000000000000000";
  attribute C_DATA_W : integer;
  attribute C_DATA_W of reg_890 : label is 16;
  attribute C_EN_CTL : integer;
  attribute C_EN_CTL of reg_890 : label is 0;
  attribute C_EN_STAT : integer;
  attribute C_EN_STAT of reg_890 : label is 1;
  attribute C_REG_ADDR : string;
  attribute C_REG_ADDR of reg_890 : label is "13'b0100010010000";
  attribute DONT_TOUCH of reg_890 : label is std.standard.true;
  attribute ASYNC_REG_boolean of s_dclk_flag_sync1_reg : label is std.standard.true;
  attribute KEEP of s_dclk_flag_sync1_reg : label is "yes";
  attribute ASYNC_REG_boolean of s_dclk_flag_sync2_reg : label is std.standard.true;
  attribute KEEP of s_dclk_flag_sync2_reg : label is "yes";
  attribute SOFT_HLUTNM of \shift_reg0[5]_i_3\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \shift_reg1[5]_i_3\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \slaveRegDo_ff8[15]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[10]_i_7\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_11\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_12\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_13\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_14\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_3\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[15]_i_9\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[6]_i_10\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_0[7]_i_8\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[0]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[1]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[2]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[3]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[5]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_1[6]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_2[3]_i_3\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_2[6]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_2[6]_i_4\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_3[14]_i_2\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_3[15]_i_3\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_3[15]_i_4\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_3[5]_i_2\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \slaveRegDo_mux_3[5]_i_3\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \xsdb_reg[15]_i_3__2\ : label is "soft_lutpair63";
begin
  SR(0) <= \^sr\(0);
  capture_qual_ctrl_1(1 downto 0) <= \^capture_qual_ctrl_1\(1 downto 0);
  debug_data_in(15 downto 0) <= \^debug_data_in\(15 downto 0);
  in0 <= \^in0\;
  next_state(1 downto 0) <= \^next_state\(1 downto 0);
  read_data_en <= \^read_data_en\;
  read_reset_addr(9 downto 0) <= \^read_reset_addr\(9 downto 0);
  s_dclk_o <= \^s_dclk_o\;
  use_probe_debug_circuit_1 <= \^use_probe_debug_circuit_1\;
\MU_SRL[0].mu_srl_reg\: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_p2s
     port map (
      E(0) => mu_config_cs_shift_en(0),
      \G_1PIPE_IFACE.s_den_r_reg\ => \MU_SRL[0].mu_srl_reg_n_3\,
      Q(15) => \MU_SRL[0].mu_srl_reg_n_4\,
      Q(14) => \MU_SRL[0].mu_srl_reg_n_5\,
      Q(13) => \MU_SRL[0].mu_srl_reg_n_6\,
      Q(12) => \MU_SRL[0].mu_srl_reg_n_7\,
      Q(11) => \MU_SRL[0].mu_srl_reg_n_8\,
      Q(10) => \MU_SRL[0].mu_srl_reg_n_9\,
      Q(9) => \MU_SRL[0].mu_srl_reg_n_10\,
      Q(8) => \MU_SRL[0].mu_srl_reg_n_11\,
      Q(7) => \MU_SRL[0].mu_srl_reg_n_12\,
      Q(6) => \MU_SRL[0].mu_srl_reg_n_13\,
      Q(5) => \MU_SRL[0].mu_srl_reg_n_14\,
      Q(4) => \MU_SRL[0].mu_srl_reg_n_15\,
      Q(3) => \MU_SRL[0].mu_srl_reg_n_16\,
      Q(2) => \MU_SRL[0].mu_srl_reg_n_17\,
      Q(1) => \MU_SRL[0].mu_srl_reg_n_18\,
      Q(0) => \MU_SRL[0].mu_srl_reg_n_19\,
      \current_state[3]_i_2__3\ => reg_80_n_1,
      data_out_sel_reg_0 => \MU_SRL[0].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      s_daddr_o(10 downto 5) => s_daddr(12 downto 7),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[0].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18
    );
\MU_SRL[1].mu_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized0\
     port map (
      D(15) => \MU_SRL[1].mu_srl_reg_n_3\,
      D(14) => \MU_SRL[1].mu_srl_reg_n_4\,
      D(13) => \MU_SRL[1].mu_srl_reg_n_5\,
      D(12) => \MU_SRL[1].mu_srl_reg_n_6\,
      D(11) => \MU_SRL[1].mu_srl_reg_n_7\,
      D(10) => \MU_SRL[1].mu_srl_reg_n_8\,
      D(9) => \MU_SRL[1].mu_srl_reg_n_9\,
      D(8) => \MU_SRL[1].mu_srl_reg_n_10\,
      D(7) => \MU_SRL[1].mu_srl_reg_n_11\,
      D(6) => \MU_SRL[1].mu_srl_reg_n_12\,
      D(5) => \MU_SRL[1].mu_srl_reg_n_13\,
      D(4) => \MU_SRL[1].mu_srl_reg_n_14\,
      D(3) => \MU_SRL[1].mu_srl_reg_n_15\,
      D(2) => \MU_SRL[1].mu_srl_reg_n_16\,
      D(1) => \MU_SRL[1].mu_srl_reg_n_17\,
      D(0) => \MU_SRL[1].mu_srl_reg_n_18\,
      E(0) => mu_config_cs_shift_en(1),
      Q(15) => \MU_SRL[4].mu_srl_reg_n_3\,
      Q(14) => \MU_SRL[4].mu_srl_reg_n_4\,
      Q(13) => \MU_SRL[4].mu_srl_reg_n_5\,
      Q(12) => \MU_SRL[4].mu_srl_reg_n_6\,
      Q(11) => \MU_SRL[4].mu_srl_reg_n_7\,
      Q(10) => \MU_SRL[4].mu_srl_reg_n_8\,
      Q(9) => \MU_SRL[4].mu_srl_reg_n_9\,
      Q(8) => \MU_SRL[4].mu_srl_reg_n_10\,
      Q(7) => \MU_SRL[4].mu_srl_reg_n_11\,
      Q(6) => \MU_SRL[4].mu_srl_reg_n_12\,
      Q(5) => \MU_SRL[4].mu_srl_reg_n_13\,
      Q(4) => \MU_SRL[4].mu_srl_reg_n_14\,
      Q(3) => \MU_SRL[4].mu_srl_reg_n_15\,
      Q(2) => \MU_SRL[4].mu_srl_reg_n_16\,
      Q(1) => \MU_SRL[4].mu_srl_reg_n_17\,
      Q(0) => \MU_SRL[4].mu_srl_reg_n_18\,
      \current_state_reg[3]_0\ => \MU_SRL[0].mu_srl_reg_n_3\,
      data_out_sel_reg_0 => \MU_SRL[1].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(1),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[1].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18,
      \slaveRegDo_mux_4_reg[15]\(15) => \MU_SRL[5].mu_srl_reg_n_3\,
      \slaveRegDo_mux_4_reg[15]\(14) => \MU_SRL[5].mu_srl_reg_n_4\,
      \slaveRegDo_mux_4_reg[15]\(13) => \MU_SRL[5].mu_srl_reg_n_5\,
      \slaveRegDo_mux_4_reg[15]\(12) => \MU_SRL[5].mu_srl_reg_n_6\,
      \slaveRegDo_mux_4_reg[15]\(11) => \MU_SRL[5].mu_srl_reg_n_7\,
      \slaveRegDo_mux_4_reg[15]\(10) => \MU_SRL[5].mu_srl_reg_n_8\,
      \slaveRegDo_mux_4_reg[15]\(9) => \MU_SRL[5].mu_srl_reg_n_9\,
      \slaveRegDo_mux_4_reg[15]\(8) => \MU_SRL[5].mu_srl_reg_n_10\,
      \slaveRegDo_mux_4_reg[15]\(7) => \MU_SRL[5].mu_srl_reg_n_11\,
      \slaveRegDo_mux_4_reg[15]\(6) => \MU_SRL[5].mu_srl_reg_n_12\,
      \slaveRegDo_mux_4_reg[15]\(5) => \MU_SRL[5].mu_srl_reg_n_13\,
      \slaveRegDo_mux_4_reg[15]\(4) => \MU_SRL[5].mu_srl_reg_n_14\,
      \slaveRegDo_mux_4_reg[15]\(3) => \MU_SRL[5].mu_srl_reg_n_15\,
      \slaveRegDo_mux_4_reg[15]\(2) => \MU_SRL[5].mu_srl_reg_n_16\,
      \slaveRegDo_mux_4_reg[15]\(1) => \MU_SRL[5].mu_srl_reg_n_17\,
      \slaveRegDo_mux_4_reg[15]\(0) => \MU_SRL[5].mu_srl_reg_n_18\,
      \slaveRegDo_mux_4_reg[15]_0\(15) => \MU_SRL[3].mu_srl_reg_n_3\,
      \slaveRegDo_mux_4_reg[15]_0\(14) => \MU_SRL[3].mu_srl_reg_n_4\,
      \slaveRegDo_mux_4_reg[15]_0\(13) => \MU_SRL[3].mu_srl_reg_n_5\,
      \slaveRegDo_mux_4_reg[15]_0\(12) => \MU_SRL[3].mu_srl_reg_n_6\,
      \slaveRegDo_mux_4_reg[15]_0\(11) => \MU_SRL[3].mu_srl_reg_n_7\,
      \slaveRegDo_mux_4_reg[15]_0\(10) => \MU_SRL[3].mu_srl_reg_n_8\,
      \slaveRegDo_mux_4_reg[15]_0\(9) => \MU_SRL[3].mu_srl_reg_n_9\,
      \slaveRegDo_mux_4_reg[15]_0\(8) => \MU_SRL[3].mu_srl_reg_n_10\,
      \slaveRegDo_mux_4_reg[15]_0\(7) => \MU_SRL[3].mu_srl_reg_n_11\,
      \slaveRegDo_mux_4_reg[15]_0\(6) => \MU_SRL[3].mu_srl_reg_n_12\,
      \slaveRegDo_mux_4_reg[15]_0\(5) => \MU_SRL[3].mu_srl_reg_n_13\,
      \slaveRegDo_mux_4_reg[15]_0\(4) => \MU_SRL[3].mu_srl_reg_n_14\,
      \slaveRegDo_mux_4_reg[15]_0\(3) => \MU_SRL[3].mu_srl_reg_n_15\,
      \slaveRegDo_mux_4_reg[15]_0\(2) => \MU_SRL[3].mu_srl_reg_n_16\,
      \slaveRegDo_mux_4_reg[15]_0\(1) => \MU_SRL[3].mu_srl_reg_n_17\,
      \slaveRegDo_mux_4_reg[15]_0\(0) => \MU_SRL[3].mu_srl_reg_n_18\,
      \slaveRegDo_mux_4_reg[15]_1\(15) => \MU_SRL[0].mu_srl_reg_n_4\,
      \slaveRegDo_mux_4_reg[15]_1\(14) => \MU_SRL[0].mu_srl_reg_n_5\,
      \slaveRegDo_mux_4_reg[15]_1\(13) => \MU_SRL[0].mu_srl_reg_n_6\,
      \slaveRegDo_mux_4_reg[15]_1\(12) => \MU_SRL[0].mu_srl_reg_n_7\,
      \slaveRegDo_mux_4_reg[15]_1\(11) => \MU_SRL[0].mu_srl_reg_n_8\,
      \slaveRegDo_mux_4_reg[15]_1\(10) => \MU_SRL[0].mu_srl_reg_n_9\,
      \slaveRegDo_mux_4_reg[15]_1\(9) => \MU_SRL[0].mu_srl_reg_n_10\,
      \slaveRegDo_mux_4_reg[15]_1\(8) => \MU_SRL[0].mu_srl_reg_n_11\,
      \slaveRegDo_mux_4_reg[15]_1\(7) => \MU_SRL[0].mu_srl_reg_n_12\,
      \slaveRegDo_mux_4_reg[15]_1\(6) => \MU_SRL[0].mu_srl_reg_n_13\,
      \slaveRegDo_mux_4_reg[15]_1\(5) => \MU_SRL[0].mu_srl_reg_n_14\,
      \slaveRegDo_mux_4_reg[15]_1\(4) => \MU_SRL[0].mu_srl_reg_n_15\,
      \slaveRegDo_mux_4_reg[15]_1\(3) => \MU_SRL[0].mu_srl_reg_n_16\,
      \slaveRegDo_mux_4_reg[15]_1\(2) => \MU_SRL[0].mu_srl_reg_n_17\,
      \slaveRegDo_mux_4_reg[15]_1\(1) => \MU_SRL[0].mu_srl_reg_n_18\,
      \slaveRegDo_mux_4_reg[15]_1\(0) => \MU_SRL[0].mu_srl_reg_n_19\,
      \slaveRegDo_mux_4_reg[15]_2\(15) => \MU_SRL[2].mu_srl_reg_n_3\,
      \slaveRegDo_mux_4_reg[15]_2\(14) => \MU_SRL[2].mu_srl_reg_n_4\,
      \slaveRegDo_mux_4_reg[15]_2\(13) => \MU_SRL[2].mu_srl_reg_n_5\,
      \slaveRegDo_mux_4_reg[15]_2\(12) => \MU_SRL[2].mu_srl_reg_n_6\,
      \slaveRegDo_mux_4_reg[15]_2\(11) => \MU_SRL[2].mu_srl_reg_n_7\,
      \slaveRegDo_mux_4_reg[15]_2\(10) => \MU_SRL[2].mu_srl_reg_n_8\,
      \slaveRegDo_mux_4_reg[15]_2\(9) => \MU_SRL[2].mu_srl_reg_n_9\,
      \slaveRegDo_mux_4_reg[15]_2\(8) => \MU_SRL[2].mu_srl_reg_n_10\,
      \slaveRegDo_mux_4_reg[15]_2\(7) => \MU_SRL[2].mu_srl_reg_n_11\,
      \slaveRegDo_mux_4_reg[15]_2\(6) => \MU_SRL[2].mu_srl_reg_n_12\,
      \slaveRegDo_mux_4_reg[15]_2\(5) => \MU_SRL[2].mu_srl_reg_n_13\,
      \slaveRegDo_mux_4_reg[15]_2\(4) => \MU_SRL[2].mu_srl_reg_n_14\,
      \slaveRegDo_mux_4_reg[15]_2\(3) => \MU_SRL[2].mu_srl_reg_n_15\,
      \slaveRegDo_mux_4_reg[15]_2\(2) => \MU_SRL[2].mu_srl_reg_n_16\,
      \slaveRegDo_mux_4_reg[15]_2\(1) => \MU_SRL[2].mu_srl_reg_n_17\,
      \slaveRegDo_mux_4_reg[15]_2\(0) => \MU_SRL[2].mu_srl_reg_n_18\
    );
\MU_SRL[2].mu_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized1\
     port map (
      E(0) => mu_config_cs_shift_en(2),
      Q(15) => \MU_SRL[2].mu_srl_reg_n_3\,
      Q(14) => \MU_SRL[2].mu_srl_reg_n_4\,
      Q(13) => \MU_SRL[2].mu_srl_reg_n_5\,
      Q(12) => \MU_SRL[2].mu_srl_reg_n_6\,
      Q(11) => \MU_SRL[2].mu_srl_reg_n_7\,
      Q(10) => \MU_SRL[2].mu_srl_reg_n_8\,
      Q(9) => \MU_SRL[2].mu_srl_reg_n_9\,
      Q(8) => \MU_SRL[2].mu_srl_reg_n_10\,
      Q(7) => \MU_SRL[2].mu_srl_reg_n_11\,
      Q(6) => \MU_SRL[2].mu_srl_reg_n_12\,
      Q(5) => \MU_SRL[2].mu_srl_reg_n_13\,
      Q(4) => \MU_SRL[2].mu_srl_reg_n_14\,
      Q(3) => \MU_SRL[2].mu_srl_reg_n_15\,
      Q(2) => \MU_SRL[2].mu_srl_reg_n_16\,
      Q(1) => \MU_SRL[2].mu_srl_reg_n_17\,
      Q(0) => \MU_SRL[2].mu_srl_reg_n_18\,
      \current_state_reg[3]_0\ => \MU_SRL[0].mu_srl_reg_n_3\,
      data_out_sel_reg_0 => \MU_SRL[2].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(2),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[2].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18
    );
\MU_SRL[3].mu_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized2\
     port map (
      E(0) => mu_config_cs_shift_en(3),
      Q(15) => \MU_SRL[3].mu_srl_reg_n_3\,
      Q(14) => \MU_SRL[3].mu_srl_reg_n_4\,
      Q(13) => \MU_SRL[3].mu_srl_reg_n_5\,
      Q(12) => \MU_SRL[3].mu_srl_reg_n_6\,
      Q(11) => \MU_SRL[3].mu_srl_reg_n_7\,
      Q(10) => \MU_SRL[3].mu_srl_reg_n_8\,
      Q(9) => \MU_SRL[3].mu_srl_reg_n_9\,
      Q(8) => \MU_SRL[3].mu_srl_reg_n_10\,
      Q(7) => \MU_SRL[3].mu_srl_reg_n_11\,
      Q(6) => \MU_SRL[3].mu_srl_reg_n_12\,
      Q(5) => \MU_SRL[3].mu_srl_reg_n_13\,
      Q(4) => \MU_SRL[3].mu_srl_reg_n_14\,
      Q(3) => \MU_SRL[3].mu_srl_reg_n_15\,
      Q(2) => \MU_SRL[3].mu_srl_reg_n_16\,
      Q(1) => \MU_SRL[3].mu_srl_reg_n_17\,
      Q(0) => \MU_SRL[3].mu_srl_reg_n_18\,
      \current_state_reg[3]_0\ => \MU_SRL[0].mu_srl_reg_n_3\,
      data_out_sel_reg_0 => \MU_SRL[3].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(3),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[3].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18
    );
\MU_SRL[4].mu_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized3\
     port map (
      E(0) => mu_config_cs_shift_en(4),
      Q(15) => \MU_SRL[4].mu_srl_reg_n_3\,
      Q(14) => \MU_SRL[4].mu_srl_reg_n_4\,
      Q(13) => \MU_SRL[4].mu_srl_reg_n_5\,
      Q(12) => \MU_SRL[4].mu_srl_reg_n_6\,
      Q(11) => \MU_SRL[4].mu_srl_reg_n_7\,
      Q(10) => \MU_SRL[4].mu_srl_reg_n_8\,
      Q(9) => \MU_SRL[4].mu_srl_reg_n_9\,
      Q(8) => \MU_SRL[4].mu_srl_reg_n_10\,
      Q(7) => \MU_SRL[4].mu_srl_reg_n_11\,
      Q(6) => \MU_SRL[4].mu_srl_reg_n_12\,
      Q(5) => \MU_SRL[4].mu_srl_reg_n_13\,
      Q(4) => \MU_SRL[4].mu_srl_reg_n_14\,
      Q(3) => \MU_SRL[4].mu_srl_reg_n_15\,
      Q(2) => \MU_SRL[4].mu_srl_reg_n_16\,
      Q(1) => \MU_SRL[4].mu_srl_reg_n_17\,
      Q(0) => \MU_SRL[4].mu_srl_reg_n_18\,
      \current_state_reg[3]_0\ => \MU_SRL[0].mu_srl_reg_n_3\,
      data_out_sel_reg_0 => \MU_SRL[4].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(4),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[4].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18
    );
\MU_SRL[5].mu_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized4\
     port map (
      E(0) => mu_config_cs_shift_en(5),
      Q(15) => \MU_SRL[5].mu_srl_reg_n_3\,
      Q(14) => \MU_SRL[5].mu_srl_reg_n_4\,
      Q(13) => \MU_SRL[5].mu_srl_reg_n_5\,
      Q(12) => \MU_SRL[5].mu_srl_reg_n_6\,
      Q(11) => \MU_SRL[5].mu_srl_reg_n_7\,
      Q(10) => \MU_SRL[5].mu_srl_reg_n_8\,
      Q(9) => \MU_SRL[5].mu_srl_reg_n_9\,
      Q(8) => \MU_SRL[5].mu_srl_reg_n_10\,
      Q(7) => \MU_SRL[5].mu_srl_reg_n_11\,
      Q(6) => \MU_SRL[5].mu_srl_reg_n_12\,
      Q(5) => \MU_SRL[5].mu_srl_reg_n_13\,
      Q(4) => \MU_SRL[5].mu_srl_reg_n_14\,
      Q(3) => \MU_SRL[5].mu_srl_reg_n_15\,
      Q(2) => \MU_SRL[5].mu_srl_reg_n_16\,
      Q(1) => \MU_SRL[5].mu_srl_reg_n_17\,
      Q(0) => \MU_SRL[5].mu_srl_reg_n_18\,
      \current_state_reg[3]_0\ => \MU_SRL[0].mu_srl_reg_n_3\,
      data_out_sel_reg_0 => \MU_SRL[5].mu_srl_reg_n_2\,
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(5),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      serial_dout_reg_0 => \MU_SRL[5].mu_srl_reg_n_0\,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18
    );
\TC_SRL[0].tc_srl_reg\: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized5\
     port map (
      E(0) => shift_en_reg_0(0),
      \G_1PIPE_IFACE.s_daddr_r_reg[8]\ => \TC_SRL[0].tc_srl_reg_n_2\,
      Q(15) => \TC_SRL[0].tc_srl_reg_n_3\,
      Q(14) => \TC_SRL[0].tc_srl_reg_n_4\,
      Q(13) => \TC_SRL[0].tc_srl_reg_n_5\,
      Q(12) => \TC_SRL[0].tc_srl_reg_n_6\,
      Q(11) => \TC_SRL[0].tc_srl_reg_n_7\,
      Q(10) => \TC_SRL[0].tc_srl_reg_n_8\,
      Q(9) => \TC_SRL[0].tc_srl_reg_n_9\,
      Q(8) => \TC_SRL[0].tc_srl_reg_n_10\,
      Q(7) => \TC_SRL[0].tc_srl_reg_n_11\,
      Q(6) => \TC_SRL[0].tc_srl_reg_n_12\,
      Q(5) => \TC_SRL[0].tc_srl_reg_n_13\,
      Q(4) => \TC_SRL[0].tc_srl_reg_n_14\,
      Q(3) => \TC_SRL[0].tc_srl_reg_n_15\,
      Q(2) => \TC_SRL[0].tc_srl_reg_n_16\,
      Q(1) => \TC_SRL[0].tc_srl_reg_n_17\,
      Q(0) => \TC_SRL[0].tc_srl_reg_n_18\,
      \parallel_dout_reg[15]_0\(0) => \parallel_dout_reg[15]\(0),
      s_daddr_o(12 downto 0) => s_daddr(12 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(14 downto 0) => s_di(14 downto 0),
      s_dwe_o => s_dwe,
      \shadow_reg[15]_0\ => reg_srl_fff_n_18,
      tc_config_cs_serial_output => tc_config_cs_serial_output
    );
U_XSDB_SLAVE: entity work.ila_full_aurora_xsdbs_v1_0_2_xsdbs
     port map (
      s_daddr_o(16 downto 0) => s_daddr(16 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      s_do_i(15) => \slaveRegDo_mux_reg_n_0_[15]\,
      s_do_i(14) => \slaveRegDo_mux_reg_n_0_[14]\,
      s_do_i(13) => \slaveRegDo_mux_reg_n_0_[13]\,
      s_do_i(12) => \slaveRegDo_mux_reg_n_0_[12]\,
      s_do_i(11) => \slaveRegDo_mux_reg_n_0_[11]\,
      s_do_i(10) => \slaveRegDo_mux_reg_n_0_[10]\,
      s_do_i(9) => \slaveRegDo_mux_reg_n_0_[9]\,
      s_do_i(8) => \slaveRegDo_mux_reg_n_0_[8]\,
      s_do_i(7) => \slaveRegDo_mux_reg_n_0_[7]\,
      s_do_i(6) => \slaveRegDo_mux_reg_n_0_[6]\,
      s_do_i(5) => \slaveRegDo_mux_reg_n_0_[5]\,
      s_do_i(4) => \slaveRegDo_mux_reg_n_0_[4]\,
      s_do_i(3) => \slaveRegDo_mux_reg_n_0_[3]\,
      s_do_i(2) => \slaveRegDo_mux_reg_n_0_[2]\,
      s_do_i(1) => \slaveRegDo_mux_reg_n_0_[1]\,
      s_do_i(0) => \slaveRegDo_mux_reg_n_0_[0]\,
      s_drdy_i => regDrdy_reg_n_0,
      s_dwe_o => s_dwe,
      s_rst_o => s_rst,
      sl_iport_i(36 downto 0) => \out\(36 downto 0),
      sl_oport_o(16 downto 0) => sl_oport_o(16 downto 0)
    );
adv_drdy_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBFFF00008000"
    )
        port map (
      I0 => s_den,
      I1 => adv_drdy_i_2_n_0,
      I2 => s_daddr(2),
      I3 => s_daddr(3),
      I4 => p_0_in1_in,
      I5 => adv_drdy,
      O => adv_drdy_i_1_n_0
    );
adv_drdy_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_daddr(0),
      I1 => s_daddr(1),
      O => adv_drdy_i_2_n_0
    );
adv_drdy_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => adv_drdy_i_1_n_0,
      Q => adv_drdy,
      R => '0'
    );
adv_rb_drdy3_reg_srl4: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^s_dclk_o\,
      D => drdy_mux_ff1,
      Q => adv_rb_drdy3_reg_srl4_n_0
    );
adv_rb_drdy4_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => adv_rb_drdy3_reg_srl4_n_0,
      Q => adv_rb_drdy4,
      R => '0'
    );
\clk_lost_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[0]\,
      O => \p_0_in__9\(0)
    );
\clk_lost_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[0]\,
      I1 => \clk_lost_cnt_reg_n_0_[1]\,
      O => \p_0_in__9\(1)
    );
\clk_lost_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[0]\,
      I1 => \clk_lost_cnt_reg_n_0_[1]\,
      I2 => \clk_lost_cnt_reg_n_0_[2]\,
      O => \p_0_in__9\(2)
    );
\clk_lost_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[1]\,
      I1 => \clk_lost_cnt_reg_n_0_[0]\,
      I2 => \clk_lost_cnt_reg_n_0_[2]\,
      I3 => \clk_lost_cnt_reg_n_0_[3]\,
      O => \p_0_in__9\(3)
    );
\clk_lost_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[2]\,
      I1 => \clk_lost_cnt_reg_n_0_[0]\,
      I2 => \clk_lost_cnt_reg_n_0_[1]\,
      I3 => \clk_lost_cnt_reg_n_0_[3]\,
      I4 => \clk_lost_cnt_reg_n_0_[4]\,
      O => \p_0_in__9\(4)
    );
\clk_lost_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[3]\,
      I1 => \clk_lost_cnt_reg_n_0_[1]\,
      I2 => \clk_lost_cnt_reg_n_0_[0]\,
      I3 => \clk_lost_cnt_reg_n_0_[2]\,
      I4 => \clk_lost_cnt_reg_n_0_[4]\,
      I5 => \clk_lost_cnt_reg_n_0_[5]\,
      O => \p_0_in__9\(5)
    );
\clk_lost_cnt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \clk_lost_cnt[8]_i_4_n_0\,
      I1 => \clk_lost_cnt_reg_n_0_[6]\,
      O => \p_0_in__9\(6)
    );
\clk_lost_cnt[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \clk_lost_cnt[8]_i_4_n_0\,
      I1 => \clk_lost_cnt_reg_n_0_[6]\,
      I2 => \clk_lost_cnt_reg_n_0_[7]\,
      O => \p_0_in__9\(7)
    );
\clk_lost_cnt[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BE"
    )
        port map (
      I0 => s_rst,
      I1 => next_state_xsdb,
      I2 => ila_clk_flag_sync2,
      O => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => clk_lost_cnt_reg(8),
      O => \clk_lost_cnt[8]_i_2_n_0\
    );
\clk_lost_cnt[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[6]\,
      I1 => \clk_lost_cnt[8]_i_4_n_0\,
      I2 => \clk_lost_cnt_reg_n_0_[7]\,
      O => \p_0_in__9\(8)
    );
\clk_lost_cnt[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \clk_lost_cnt_reg_n_0_[5]\,
      I1 => \clk_lost_cnt_reg_n_0_[3]\,
      I2 => \clk_lost_cnt_reg_n_0_[1]\,
      I3 => \clk_lost_cnt_reg_n_0_[0]\,
      I4 => \clk_lost_cnt_reg_n_0_[2]\,
      I5 => \clk_lost_cnt_reg_n_0_[4]\,
      O => \clk_lost_cnt[8]_i_4_n_0\
    );
\clk_lost_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(0),
      Q => \clk_lost_cnt_reg_n_0_[0]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(1),
      Q => \clk_lost_cnt_reg_n_0_[1]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(2),
      Q => \clk_lost_cnt_reg_n_0_[2]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(3),
      Q => \clk_lost_cnt_reg_n_0_[3]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(4),
      Q => \clk_lost_cnt_reg_n_0_[4]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(5),
      Q => \clk_lost_cnt_reg_n_0_[5]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(6),
      Q => \clk_lost_cnt_reg_n_0_[6]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(7),
      Q => \clk_lost_cnt_reg_n_0_[7]\,
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
\clk_lost_cnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => \clk_lost_cnt[8]_i_2_n_0\,
      D => \p_0_in__9\(8),
      Q => clk_lost_cnt_reg(8),
      R => \clk_lost_cnt[8]_i_1_n_0\
    );
clk_lost_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0082"
    )
        port map (
      I0 => clk_lost_cnt_reg(8),
      I1 => ila_clk_flag_sync2,
      I2 => next_state_xsdb,
      I3 => s_rst,
      O => clk_lost_i_1_n_0
    );
clk_lost_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => clk_lost_i_1_n_0,
      Q => clk_lost,
      R => '0'
    );
\count0[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => count0_reg(0),
      O => p_0_in(0)
    );
\count0[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => count0_reg(0),
      I1 => count0_reg(1),
      O => p_0_in(1)
    );
\count0[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => count0_reg(0),
      I1 => count0_reg(1),
      I2 => count0_reg(2),
      O => p_0_in(2)
    );
\count0[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => count0_reg(1),
      I1 => count0_reg(0),
      I2 => count0_reg(2),
      I3 => count0_reg(3),
      O => p_0_in(3)
    );
\count0[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => count0_reg(2),
      I1 => count0_reg(0),
      I2 => count0_reg(1),
      I3 => count0_reg(3),
      I4 => count0_reg(4),
      O => p_0_in(4)
    );
\count0[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => count0_reg(3),
      I1 => count0_reg(1),
      I2 => count0_reg(0),
      I3 => count0_reg(2),
      I4 => count0_reg(4),
      I5 => count0_reg(5),
      O => p_0_in(5)
    );
\count0[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_rst,
      I1 => count0_reg(6),
      O => \count0[6]_i_1_n_0\
    );
\count0[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => count0_reg(4),
      I1 => count0_reg(2),
      I2 => count0_reg(0),
      I3 => count0_reg(1),
      I4 => count0_reg(3),
      I5 => count0_reg(5),
      O => p_0_in(6)
    );
\count0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(0),
      Q => count0_reg(0),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(1),
      Q => count0_reg(1),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(2),
      Q => count0_reg(2),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(3),
      Q => count0_reg(3),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(4),
      Q => count0_reg(4),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(5),
      Q => count0_reg(5),
      R => \count0[6]_i_1_n_0\
    );
\count0_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => sel,
      D => p_0_in(6),
      Q => count0_reg(6),
      R => \count0[6]_i_1_n_0\
    );
\count1[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => count1_reg(0),
      O => \p_0_in__0\(0)
    );
\count1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => count1_reg(0),
      I1 => count1_reg(1),
      O => \p_0_in__0\(1)
    );
\count1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => count1_reg(0),
      I1 => count1_reg(1),
      I2 => count1_reg(2),
      O => \p_0_in__0\(2)
    );
\count1[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => count1_reg(1),
      I1 => count1_reg(0),
      I2 => count1_reg(2),
      I3 => count1_reg(3),
      O => \p_0_in__0\(3)
    );
\count1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => count1_reg(2),
      I1 => count1_reg(0),
      I2 => count1_reg(1),
      I3 => count1_reg(3),
      I4 => count1_reg(4),
      O => \p_0_in__0\(4)
    );
\count1[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => count1_reg(3),
      I1 => count1_reg(1),
      I2 => count1_reg(0),
      I3 => count1_reg(2),
      I4 => count1_reg(4),
      I5 => count1_reg(5),
      O => \p_0_in__0\(5)
    );
\count1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_rst,
      I1 => count1_reg(6),
      O => \count1[6]_i_1_n_0\
    );
\count1[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => count1_reg(4),
      I1 => count1_reg(2),
      I2 => count1_reg(0),
      I3 => count1_reg(1),
      I4 => count1_reg(3),
      I5 => count1_reg(5),
      O => \p_0_in__0\(6)
    );
\count1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(0),
      Q => count1_reg(0),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(1),
      Q => count1_reg(1),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(2),
      Q => count1_reg(2),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(3),
      Q => count1_reg(3),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(4),
      Q => count1_reg(4),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(5),
      Q => count1_reg(5),
      R => \count1[6]_i_1_n_0\
    );
\count1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => drdy_ffa_i_1_n_0,
      D => \p_0_in__0\(6),
      Q => count1_reg(6),
      R => \count1[6]_i_1_n_0\
    );
count_tt_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => xsdb_rden_ff8,
      I1 => count_tt,
      O => count_tt_i_1_n_0
    );
count_tt_reg: unisim.vcomponents.FDSE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => count_tt_i_1_n_0,
      Q => count_tt,
      S => s_rst
    );
\curr_read_block[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^next_state\(0),
      I1 => Q(0),
      O => \curr_read_block_reg[0]\(0)
    );
\current_state[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \current_state[6]_i_5_n_0\,
      I1 => \current_state[6]_i_4_n_0\,
      I2 => s_daddr(5),
      I3 => s_daddr(4),
      I4 => s_daddr(3),
      I5 => \xsdb_reg[15]_i_4__1_n_0\,
      O => \^read_data_en\
    );
\current_state[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \current_state_reg[5]\,
      I1 => \current_state_reg[5]_0\,
      I2 => \xsdb_reg[15]_i_4__1_n_0\,
      I3 => \xsdb_reg[15]_i_3__2_n_0\,
      I4 => \current_state[6]_i_4_n_0\,
      I5 => \current_state[6]_i_5_n_0\,
      O => \^next_state\(0)
    );
\current_state[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040000000"
    )
        port map (
      I0 => \current_state_reg[5]\,
      I1 => \current_state_reg[6]\,
      I2 => \xsdb_reg[15]_i_4__1_n_0\,
      I3 => \xsdb_reg[15]_i_3__2_n_0\,
      I4 => \current_state[6]_i_4_n_0\,
      I5 => \current_state[6]_i_5_n_0\,
      O => \^next_state\(1)
    );
\current_state[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080000000000000"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(2),
      I2 => s_den,
      I3 => s_daddr(12),
      I4 => s_daddr(8),
      I5 => s_daddr(7),
      O => \current_state[6]_i_4_n_0\
    );
\current_state[6]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => s_daddr(2),
      I1 => s_daddr(1),
      I2 => s_daddr(0),
      O => \current_state[6]_i_5_n_0\
    );
\drdyCount[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000BBA"
    )
        port map (
      I0 => s_den,
      I1 => \drdyCount_reg_n_0_[0]\,
      I2 => \drdyCount_reg_n_0_[4]\,
      I3 => \drdyCount[5]_i_5_n_0\,
      I4 => s_rst,
      I5 => \drdyCount_reg_n_0_[5]\,
      O => \drdyCount[0]_i_1_n_0\
    );
\drdyCount[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[0]\,
      I1 => \drdyCount_reg_n_0_[1]\,
      O => drdyCount0(1)
    );
\drdyCount[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[0]\,
      I1 => \drdyCount_reg_n_0_[1]\,
      I2 => \drdyCount_reg_n_0_[2]\,
      O => drdyCount0(2)
    );
\drdyCount[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[1]\,
      I1 => \drdyCount_reg_n_0_[0]\,
      I2 => \drdyCount_reg_n_0_[2]\,
      I3 => \drdyCount_reg_n_0_[3]\,
      O => drdyCount0(3)
    );
\drdyCount[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000006A00FF006A"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[4]\,
      I1 => p_2_in,
      I2 => \drdyCount[4]_i_2_n_0\,
      I3 => \drdyCount1__4\,
      I4 => s_den,
      I5 => \isSRLAddress__0\,
      O => \drdyCount[4]_i_1_n_0\
    );
\drdyCount[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[3]\,
      I1 => \drdyCount_reg_n_0_[1]\,
      I2 => \drdyCount_reg_n_0_[0]\,
      I3 => \drdyCount_reg_n_0_[2]\,
      O => \drdyCount[4]_i_2_n_0\
    );
\drdyCount[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000008"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(2),
      I2 => \drdyCount[4]_i_4_n_0\,
      I3 => drdy_ffa_i_2_n_0,
      I4 => \slaveRegDo_mux_0[9]_i_7_n_0\,
      I5 => s_daddr(12),
      O => \isSRLAddress__0\
    );
\drdyCount[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => s_daddr(4),
      I1 => s_daddr(5),
      I2 => s_daddr(6),
      I3 => s_daddr(7),
      O => \drdyCount[4]_i_4_n_0\
    );
\drdyCount[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \drdyCount1__4\,
      I1 => s_den,
      O => \drdyCount[5]_i_1_n_0\
    );
\drdyCount[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => s_den,
      I1 => \drdyCount_reg_n_0_[5]\,
      I2 => \drdyCount_reg_n_0_[0]\,
      I3 => \drdyCount[5]_i_5_n_0\,
      I4 => \drdyCount_reg_n_0_[4]\,
      O => p_2_in
    );
\drdyCount[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[4]\,
      I1 => \drdyCount_reg_n_0_[2]\,
      I2 => \drdyCount_reg_n_0_[0]\,
      I3 => \drdyCount_reg_n_0_[1]\,
      I4 => \drdyCount_reg_n_0_[3]\,
      I5 => \drdyCount_reg_n_0_[5]\,
      O => p_3_in(5)
    );
\drdyCount[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEEEEEEEEE"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[5]\,
      I1 => s_rst,
      I2 => \drdyCount_reg_n_0_[1]\,
      I3 => \drdyCount_reg_n_0_[2]\,
      I4 => \drdyCount_reg_n_0_[3]\,
      I5 => \drdyCount_reg_n_0_[4]\,
      O => \drdyCount1__4\
    );
\drdyCount[5]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[1]\,
      I1 => \drdyCount_reg_n_0_[2]\,
      I2 => \drdyCount_reg_n_0_[3]\,
      O => \drdyCount[5]_i_5_n_0\
    );
\drdyCount_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \drdyCount[0]_i_1_n_0\,
      Q => \drdyCount_reg_n_0_[0]\,
      R => '0'
    );
\drdyCount_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => p_2_in,
      D => drdyCount0(1),
      Q => \drdyCount_reg_n_0_[1]\,
      R => \drdyCount[5]_i_1_n_0\
    );
\drdyCount_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => p_2_in,
      D => drdyCount0(2),
      Q => \drdyCount_reg_n_0_[2]\,
      R => \drdyCount[5]_i_1_n_0\
    );
\drdyCount_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => p_2_in,
      D => drdyCount0(3),
      Q => \drdyCount_reg_n_0_[3]\,
      R => \drdyCount[5]_i_1_n_0\
    );
\drdyCount_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \drdyCount[4]_i_1_n_0\,
      Q => \drdyCount_reg_n_0_[4]\,
      R => '0'
    );
\drdyCount_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^s_dclk_o\,
      CE => p_2_in,
      D => p_3_in(5),
      Q => \drdyCount_reg_n_0_[5]\,
      R => \drdyCount[5]_i_1_n_0\
    );
drdy_ff7_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => s_daddr(9),
      I1 => s_daddr(8),
      I2 => s_daddr(10),
      I3 => s_daddr(11),
      I4 => drdy_ff7_i_2_n_0,
      I5 => drdy_ff9_i_3_n_0,
      O => xsdb_rden_ff7
    );
drdy_ff7_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(2),
      I2 => s_daddr(1),
      I3 => s_daddr(0),
      O => drdy_ff7_i_2_n_0
    );
drdy_ff7_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => xsdb_rden_ff7,
      Q => drdy_ff7,
      R => s_rst
    );
drdy_ff8_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => drdy_ff8_i_2_n_0,
      I1 => s_daddr(11),
      I2 => s_daddr(8),
      I3 => s_daddr(10),
      I4 => s_daddr(9),
      I5 => drdy_ff9_i_3_n_0,
      O => xsdb_rden_ff8
    );
drdy_ff8_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(3),
      I3 => s_daddr(2),
      O => drdy_ff8_i_2_n_0
    );
drdy_ff8_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => xsdb_rden_ff8,
      Q => drdy_ff8,
      R => s_rst
    );
drdy_ff9_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => s_daddr(9),
      I1 => s_daddr(8),
      I2 => s_daddr(10),
      I3 => s_daddr(11),
      I4 => drdy_ff9_i_2_n_0,
      I5 => drdy_ff9_i_3_n_0,
      O => sel
    );
drdy_ff9_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(3),
      I3 => s_daddr(2),
      O => drdy_ff9_i_2_n_0
    );
drdy_ff9_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => s_dwe,
      I1 => s_den,
      I2 => s_daddr(7),
      I3 => s_daddr(6),
      I4 => s_daddr(5),
      I5 => s_daddr(4),
      O => drdy_ff9_i_3_n_0
    );
drdy_ff9_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => sel,
      Q => drdy_ff9,
      R => s_rst
    );
drdy_ffa_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => drdy_ffa_i_2_n_0,
      I1 => s_daddr(0),
      I2 => s_daddr(1),
      I3 => s_daddr(3),
      I4 => s_daddr(2),
      I5 => drdy_ff9_i_3_n_0,
      O => drdy_ffa_i_1_n_0
    );
drdy_ffa_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => s_daddr(9),
      I1 => s_daddr(8),
      I2 => s_daddr(10),
      I3 => s_daddr(11),
      O => drdy_ffa_i_2_n_0
    );
drdy_ffa_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => drdy_ffa_i_1_n_0,
      Q => drdy_ffa,
      R => s_rst
    );
drdy_mux_ff1_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => drdy_mux_ff,
      Q => drdy_mux_ff1,
      R => '0'
    );
drdy_mux_ff_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \drdyCount_reg_n_0_[0]\,
      I1 => \drdyCount_reg_n_0_[4]\,
      I2 => \drdyCount_reg_n_0_[5]\,
      I3 => \drdyCount_reg_n_0_[3]\,
      I4 => \drdyCount_reg_n_0_[2]\,
      I5 => \drdyCount_reg_n_0_[1]\,
      O => drdy_mux_ff_i_1_n_0
    );
drdy_mux_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => drdy_mux_ff_i_1_n_0,
      Q => drdy_mux_ff,
      R => '0'
    );
dummy_temp1_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => dummy_temp1_reg_0,
      Q => dummy_temp1,
      R => '0'
    );
dummy_temp_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => dummy_temp1,
      Q => dummy_temp,
      R => '0'
    );
ila_clk_flag_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => ila_clk_flag,
      I1 => next_state_ila,
      I2 => s_dclk_flag_sync2,
      O => ila_clk_flag_i_1_n_0
    );
ila_clk_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => ila_clk_flag_reg_0,
      CE => '1',
      D => ila_clk_flag_i_1_n_0,
      Q => ila_clk_flag,
      R => '0'
    );
ila_clk_flag_sync1_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => ila_clk_flag,
      Q => ila_clk_flag_sync1,
      R => '0'
    );
ila_clk_flag_sync2_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => ila_clk_flag_sync1,
      Q => ila_clk_flag_sync2,
      R => '0'
    );
next_state_ila_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => ila_clk_flag_reg_0,
      CE => '1',
      D => s_dclk_flag_sync2,
      Q => next_state_ila,
      R => '0'
    );
next_state_xsdb_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => ila_clk_flag_sync2,
      Q => next_state_xsdb,
      R => s_rst
    );
read_en_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000B000B0BF4"
    )
        port map (
      I0 => \^read_data_en\,
      I1 => read_en_i_2,
      I2 => read_en_i_2_0,
      I3 => \^next_state\(1),
      I4 => \^next_state\(0),
      I5 => read_en_i_2_1(0),
      O => \G_1PIPE_IFACE.s_daddr_r_reg[5]\
    );
\regAck_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => regAck_temp,
      Q => regAck_reg,
      R => '0'
    );
\regAck_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => regAck_temp_reg,
      Q => \regAck_reg_n_0_[1]\,
      R => '0'
    );
\regAck_temp_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => s_den,
      Q => regAck_temp,
      R => '0'
    );
\regAck_temp_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => E(0),
      Q => regAck_temp_reg,
      R => '0'
    );
regDrdy_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0000AAAAFCFF"
    )
        port map (
      I0 => drdy_mux_ff1,
      I1 => regDrdy_i_2_n_0,
      I2 => s_daddr(2),
      I3 => s_daddr(3),
      I4 => p_0_in1_in,
      I5 => regDrdy_i_4_n_0,
      O => regDrdy_i_1_n_0
    );
regDrdy_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => drdy_ff9,
      I1 => adv_rb_drdy4,
      I2 => s_daddr(1),
      I3 => s_daddr(0),
      I4 => drdy_ff8,
      I5 => drdy_ffa,
      O => regDrdy_i_2_n_0
    );
regDrdy_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => drdy_ffa_i_2_n_0,
      I1 => s_daddr(12),
      I2 => s_daddr(7),
      I3 => s_daddr(6),
      I4 => s_daddr(5),
      I5 => s_daddr(4),
      O => p_0_in1_in
    );
regDrdy_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF40"
    )
        port map (
      I0 => regDrdy_i_5_n_0,
      I1 => s_daddr(2),
      I2 => s_daddr(3),
      I3 => regDrdy_i_6_n_0,
      O => regDrdy_i_4_n_0
    );
regDrdy_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => regAck_reg,
      I1 => drdy_mux_ff1,
      I2 => s_daddr(1),
      I3 => s_daddr(0),
      I4 => adv_drdy,
      I5 => \regAck_reg_n_0_[1]\,
      O => regDrdy_i_5_n_0
    );
regDrdy_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000040007FFF"
    )
        port map (
      I0 => drdy_ff7,
      I1 => s_daddr(2),
      I2 => s_daddr(1),
      I3 => s_daddr(0),
      I4 => drdy_mux_ff1,
      I5 => s_daddr(3),
      O => regDrdy_i_6_n_0
    );
regDrdy_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => regDrdy_i_1_n_0,
      Q => regDrdy_reg_n_0,
      R => '0'
    );
reg_15: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized36\
     port map (
      SR(0) => \^sr\(0),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_6_n_0,
      \xsdb_reg_reg[10]\ => reg_15_n_5,
      \xsdb_reg_reg[11]\ => reg_15_n_4,
      \xsdb_reg_reg[12]\ => reg_15_n_3,
      \xsdb_reg_reg[13]\ => reg_15_n_2,
      \xsdb_reg_reg[14]\ => reg_15_n_1,
      \xsdb_reg_reg[15]\ => reg_15_n_0,
      \xsdb_reg_reg[1]\ => reg_15_n_14,
      \xsdb_reg_reg[2]\ => \^use_probe_debug_circuit_1\,
      \xsdb_reg_reg[3]\ => reg_15_n_12,
      \xsdb_reg_reg[4]\ => reg_15_n_11,
      \xsdb_reg_reg[5]\ => reg_15_n_10,
      \xsdb_reg_reg[6]\ => reg_15_n_9,
      \xsdb_reg_reg[7]\ => reg_15_n_8,
      \xsdb_reg_reg[8]\ => reg_15_n_7,
      \xsdb_reg_reg[9]\ => reg_15_n_6
    );
reg_16: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized37\
     port map (
      read_reset_addr(9 downto 0) => \^read_reset_addr\(9 downto 0),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \slaveRegDo_mux_0[1]_i_2\ => reg_15_n_14,
      \slaveRegDo_mux_0[1]_i_2_0\ => reg_17_n_15,
      \slaveRegDo_mux_0[2]_i_2\ => \^use_probe_debug_circuit_1\,
      \slaveRegDo_mux_0[2]_i_2_0\ => reg_17_n_14,
      \slaveRegDo_mux_0[3]_i_2\ => reg_15_n_12,
      \slaveRegDo_mux_0[3]_i_2_0\ => reg_17_n_13,
      \xsdb_reg_reg[0]\ => reg_6_n_0,
      \xsdb_reg_reg[10]\ => reg_16_n_18,
      \xsdb_reg_reg[11]\ => reg_16_n_17,
      \xsdb_reg_reg[12]\ => reg_16_n_16,
      \xsdb_reg_reg[13]\ => reg_16_n_15,
      \xsdb_reg_reg[14]\ => reg_16_n_14,
      \xsdb_reg_reg[15]\ => reg_16_n_13,
      \xsdb_reg_reg[1]\ => reg_16_n_12,
      \xsdb_reg_reg[2]\ => reg_16_n_11,
      \xsdb_reg_reg[3]\ => reg_16_n_0
    );
reg_17: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized38\
     port map (
      D(1) => reg_17_n_0,
      D(0) => reg_17_n_1,
      SR(0) => \^sr\(0),
      read_reset_addr(6 downto 1) => \^read_reset_addr\(9 downto 4),
      read_reset_addr(0) => \^read_reset_addr\(0),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \slaveRegDo_mux_01__6\ => \slaveRegDo_mux_01__6\,
      \slaveRegDo_mux_0[5]_i_2\ => reg_15_n_10,
      \slaveRegDo_mux_0[6]_i_2\ => reg_15_n_9,
      \slaveRegDo_mux_0_reg[0]\ => reg_81_n_10,
      \slaveRegDo_mux_0_reg[0]_0\ => reg_19_n_11,
      \slaveRegDo_mux_0_reg[0]_1\ => reg_9_n_4,
      \slaveRegDo_mux_0_reg[0]_2\ => reg_7_n_4,
      \slaveRegDo_mux_0_reg[10]\ => reg_15_n_5,
      \slaveRegDo_mux_0_reg[10]_0\ => reg_16_n_18,
      \slaveRegDo_mux_0_reg[11]\ => reg_15_n_4,
      \slaveRegDo_mux_0_reg[11]_0\ => reg_16_n_17,
      \slaveRegDo_mux_0_reg[12]\ => reg_15_n_3,
      \slaveRegDo_mux_0_reg[12]_0\ => reg_16_n_16,
      \slaveRegDo_mux_0_reg[13]\ => reg_15_n_2,
      \slaveRegDo_mux_0_reg[13]_0\ => reg_16_n_15,
      \slaveRegDo_mux_0_reg[14]\ => reg_15_n_1,
      \slaveRegDo_mux_0_reg[14]_0\ => reg_16_n_14,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0[15]_i_12_n_0\,
      \slaveRegDo_mux_0_reg[15]_0\ => reg_15_n_0,
      \slaveRegDo_mux_0_reg[15]_1\ => reg_16_n_13,
      \slaveRegDo_mux_0_reg[4]\ => reg_15_n_11,
      \slaveRegDo_mux_0_reg[6]\ => \slaveRegDo_mux_0[15]_i_3_n_0\,
      \slaveRegDo_mux_0_reg[6]_0\(1) => \slaveRegDo_mux_1[6]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[6]_0\(0) => \slaveRegDo_mux_1[0]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[6]_1\ => reg_81_n_15,
      \slaveRegDo_mux_0_reg[6]_2\ => \slaveRegDo_mux_0[15]_i_7_n_0\,
      \slaveRegDo_mux_0_reg[6]_3\ => \slaveRegDo_mux_0[15]_i_14_n_0\,
      \slaveRegDo_mux_0_reg[6]_4\ => reg_19_n_8,
      \slaveRegDo_mux_0_reg[6]_5\ => reg_7_n_14,
      \slaveRegDo_mux_0_reg[6]_6\ => reg_6_n_1,
      \slaveRegDo_mux_0_reg[7]\ => reg_15_n_8,
      \slaveRegDo_mux_0_reg[8]\ => reg_15_n_7,
      \slaveRegDo_mux_0_reg[9]\ => reg_15_n_6,
      \xsdb_reg_reg[0]\ => reg_6_n_0,
      \xsdb_reg_reg[10]\ => reg_17_n_7,
      \xsdb_reg_reg[11]\ => reg_17_n_8,
      \xsdb_reg_reg[12]\ => reg_17_n_9,
      \xsdb_reg_reg[13]\ => reg_17_n_10,
      \xsdb_reg_reg[14]\ => reg_17_n_11,
      \xsdb_reg_reg[15]\ => reg_17_n_12,
      \xsdb_reg_reg[1]\ => reg_17_n_15,
      \xsdb_reg_reg[2]\ => reg_17_n_14,
      \xsdb_reg_reg[3]\ => reg_17_n_13,
      \xsdb_reg_reg[4]\ => reg_17_n_2,
      \xsdb_reg_reg[5]\ => reg_17_n_3,
      \xsdb_reg_reg[7]\ => reg_17_n_4,
      \xsdb_reg_reg[8]\ => reg_17_n_5,
      \xsdb_reg_reg[9]\ => reg_17_n_6
    );
reg_18: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized39\
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[2]\ => reg_18_n_0,
      Q(0) => reg_9_n_5,
      in0 => \^in0\,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \slaveRegDo_mux_0[1]_i_2\ => reg_19_n_15,
      \slaveRegDo_mux_0[2]_i_2\(1 downto 0) => \^capture_qual_ctrl_1\(1 downto 0),
      \slaveRegDo_mux_0[2]_i_2_0\ => reg_19_n_14,
      \slaveRegDo_mux_0[3]_i_2\ => reg_19_n_13,
      \slaveRegDo_mux_0[7]_i_3\ => reg_1a_n_8,
      \slaveRegDo_mux_0[7]_i_3_0\ => reg_19_n_12,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0[15]_i_14_n_0\,
      \slaveRegDo_mux_0_reg[7]_0\ => \slaveRegDo_mux_0[7]_i_8_n_0\,
      \xsdb_reg_reg[0]\ => reg_18_n_15,
      \xsdb_reg_reg[0]_0\ => reg_6_n_0,
      \xsdb_reg_reg[10]\ => reg_18_n_9,
      \xsdb_reg_reg[11]\ => reg_18_n_8,
      \xsdb_reg_reg[12]\ => reg_18_n_7,
      \xsdb_reg_reg[13]\ => reg_18_n_6,
      \xsdb_reg_reg[14]\ => reg_18_n_5,
      \xsdb_reg_reg[15]\ => reg_18_n_4,
      \xsdb_reg_reg[1]\ => reg_18_n_3,
      \xsdb_reg_reg[2]\ => reg_18_n_2,
      \xsdb_reg_reg[3]\ => reg_18_n_1,
      \xsdb_reg_reg[4]\ => reg_18_n_14,
      \xsdb_reg_reg[5]\ => reg_18_n_13,
      \xsdb_reg_reg[6]\ => reg_18_n_12,
      \xsdb_reg_reg[8]\ => reg_18_n_11,
      \xsdb_reg_reg[9]\ => reg_18_n_10
    );
reg_19: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized40\
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[1]\ => reg_19_n_0,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_0\ => reg_19_n_1,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_1\ => reg_19_n_2,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_10\ => reg_19_n_11,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_2\ => reg_19_n_3,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_3\ => reg_19_n_4,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_4\ => reg_19_n_5,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_5\ => reg_19_n_6,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_6\ => reg_19_n_7,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_7\ => reg_19_n_8,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_8\ => reg_19_n_9,
      \G_1PIPE_IFACE.s_daddr_r_reg[1]_9\ => reg_19_n_10,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \slaveRegDo_mux_0[0]_i_2\ => reg_1a_n_15,
      \slaveRegDo_mux_0[0]_i_2_0\ => reg_18_n_15,
      \slaveRegDo_mux_0[5]_i_2\ => reg_1a_n_10,
      \slaveRegDo_mux_0[5]_i_2_0\ => reg_18_n_13,
      \slaveRegDo_mux_0[6]_i_2\ => reg_1a_n_9,
      \slaveRegDo_mux_0[6]_i_2_0\ => reg_18_n_12,
      \slaveRegDo_mux_0_reg[10]\ => reg_1a_n_5,
      \slaveRegDo_mux_0_reg[10]_0\ => reg_18_n_9,
      \slaveRegDo_mux_0_reg[11]\ => reg_1a_n_4,
      \slaveRegDo_mux_0_reg[11]_0\ => reg_18_n_8,
      \slaveRegDo_mux_0_reg[12]\ => reg_1a_n_3,
      \slaveRegDo_mux_0_reg[12]_0\ => reg_18_n_7,
      \slaveRegDo_mux_0_reg[13]\ => reg_1a_n_2,
      \slaveRegDo_mux_0_reg[13]_0\ => reg_18_n_6,
      \slaveRegDo_mux_0_reg[14]\ => reg_1a_n_1,
      \slaveRegDo_mux_0_reg[14]_0\ => reg_18_n_5,
      \slaveRegDo_mux_0_reg[15]\ => reg_1a_n_0,
      \slaveRegDo_mux_0_reg[15]_0\ => reg_18_n_4,
      \slaveRegDo_mux_0_reg[4]\ => \slaveRegDo_mux_0[15]_i_11_n_0\,
      \slaveRegDo_mux_0_reg[4]_0\ => reg_1a_n_11,
      \slaveRegDo_mux_0_reg[4]_1\ => reg_18_n_14,
      \slaveRegDo_mux_0_reg[8]\ => reg_1a_n_7,
      \slaveRegDo_mux_0_reg[8]_0\ => reg_18_n_11,
      \slaveRegDo_mux_0_reg[9]\ => reg_1a_n_6,
      \slaveRegDo_mux_0_reg[9]_0\ => reg_18_n_10,
      \xsdb_reg_reg[0]\ => reg_6_n_0,
      \xsdb_reg_reg[1]\ => reg_19_n_15,
      \xsdb_reg_reg[2]\ => reg_19_n_14,
      \xsdb_reg_reg[3]\ => reg_19_n_13,
      \xsdb_reg_reg[7]\ => reg_19_n_12
    );
reg_1a: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized41\
     port map (
      in0 => \^in0\,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_1a_n_15,
      \xsdb_reg_reg[0]_0\ => reg_6_n_0,
      \xsdb_reg_reg[10]\ => reg_1a_n_5,
      \xsdb_reg_reg[11]\ => reg_1a_n_4,
      \xsdb_reg_reg[12]\ => reg_1a_n_3,
      \xsdb_reg_reg[13]\ => reg_1a_n_2,
      \xsdb_reg_reg[14]\ => reg_1a_n_1,
      \xsdb_reg_reg[15]\ => reg_1a_n_0,
      \xsdb_reg_reg[2]\(1 downto 0) => \^capture_qual_ctrl_1\(1 downto 0),
      \xsdb_reg_reg[4]\ => reg_1a_n_11,
      \xsdb_reg_reg[5]\ => reg_1a_n_10,
      \xsdb_reg_reg[6]\ => reg_1a_n_9,
      \xsdb_reg_reg[7]\ => reg_1a_n_8,
      \xsdb_reg_reg[8]\ => reg_1a_n_7,
      \xsdb_reg_reg[9]\ => reg_1a_n_6
    );
reg_6: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized21\
     port map (
      \G_1PIPE_IFACE.s_den_r_reg\ => reg_6_n_0,
      Q(0) => reg_8_n_0,
      s_daddr_o(8 downto 5) => s_daddr(12 downto 9),
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      s_dwe_o => s_dwe,
      \xsdb_reg_reg[0]\ => reg_6_n_16,
      \xsdb_reg_reg[0]_0\ => \TC_SRL[0].tc_srl_reg_n_2\,
      \xsdb_reg_reg[15]\(11 downto 3) => slaveRegDo_6(15 downto 7),
      \xsdb_reg_reg[15]\(2 downto 0) => slaveRegDo_6(5 downto 3),
      \xsdb_reg_reg[1]\ => reg_6_n_15,
      \xsdb_reg_reg[2]\ => reg_6_n_14,
      \xsdb_reg_reg[6]\ => reg_6_n_1
    );
reg_7: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized22\
     port map (
      D(3) => reg_7_n_0,
      D(2) => reg_7_n_1,
      D(1) => reg_7_n_2,
      D(0) => reg_7_n_3,
      DOUT_O => DOUT_O,
      \G_1PIPE_IFACE.s_daddr_r_reg[0]\ => reg_7_n_15,
      \G_1PIPE_IFACE.s_daddr_r_reg[0]_0\ => reg_7_n_17,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]\ => reg_7_n_6,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]_0\ => reg_7_n_7,
      \G_1PIPE_IFACE.s_daddr_r_reg[2]_1\ => reg_7_n_8,
      \G_1PIPE_IFACE.s_daddr_r_reg[3]\ => reg_7_n_4,
      Q(3) => reg_9_n_6,
      Q(2) => reg_9_n_7,
      Q(1) => reg_9_n_8,
      Q(0) => reg_9_n_9,
      halt_ctrl => halt_ctrl,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      scnt_cmp_temp => scnt_cmp_temp,
      \slaveRegDo_mux_01__6\ => \slaveRegDo_mux_01__6\,
      \slaveRegDo_mux_0[0]_i_2\ => reg_6_n_16,
      \slaveRegDo_mux_0[1]_i_2\ => \slaveRegDo_mux_0[3]_i_9_n_0\,
      \slaveRegDo_mux_0[1]_i_4\ => reg_6_n_15,
      \slaveRegDo_mux_0[2]_i_4\ => reg_6_n_14,
      \slaveRegDo_mux_0[3]_i_2\(2) => reg_8_n_1,
      \slaveRegDo_mux_0[3]_i_2\(1) => reg_8_n_2,
      \slaveRegDo_mux_0[3]_i_2\(0) => reg_8_n_3,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0[15]_i_14_n_0\,
      \slaveRegDo_mux_0_reg[15]_0\(7 downto 2) => slaveRegDo_6(15 downto 10),
      \slaveRegDo_mux_0_reg[15]_0\(1) => slaveRegDo_6(7),
      \slaveRegDo_mux_0_reg[15]_0\(0) => slaveRegDo_6(3),
      \slaveRegDo_mux_0_reg[15]_1\ => \slaveRegDo_mux_0[15]_i_13_n_0\,
      \slaveRegDo_mux_0_reg[1]\ => reg_81_n_11,
      \slaveRegDo_mux_0_reg[1]_0\ => reg_18_n_3,
      \slaveRegDo_mux_0_reg[1]_1\ => reg_16_n_12,
      \slaveRegDo_mux_0_reg[2]\ => reg_81_n_12,
      \slaveRegDo_mux_0_reg[2]_0\ => reg_18_n_2,
      \slaveRegDo_mux_0_reg[2]_1\ => reg_16_n_11,
      \slaveRegDo_mux_0_reg[3]\ => reg_81_n_13,
      \slaveRegDo_mux_0_reg[3]_0\ => reg_18_n_1,
      \slaveRegDo_mux_0_reg[3]_1\ => reg_16_n_0,
      \slaveRegDo_mux_0_reg[4]\ => reg_9_n_0,
      \slaveRegDo_mux_0_reg[5]\ => \slaveRegDo_mux_0[15]_i_7_n_0\,
      \slaveRegDo_mux_0_reg[5]_0\ => \slaveRegDo_mux_0[15]_i_3_n_0\,
      \slaveRegDo_mux_0_reg[5]_1\(3) => \slaveRegDo_mux_1[5]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[5]_1\(2) => \slaveRegDo_mux_1[3]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[5]_1\(1) => \slaveRegDo_mux_1[2]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[5]_1\(0) => \slaveRegDo_mux_1[1]_i_1_n_0\,
      \slaveRegDo_mux_0_reg[5]_2\ => reg_81_n_14,
      \slaveRegDo_mux_0_reg[5]_3\ => drdy_ff7_i_2_n_0,
      \slaveRegDo_mux_0_reg[5]_4\ => reg_9_n_1,
      \slaveRegDo_mux_0_reg[5]_5\ => reg_19_n_9,
      \slaveRegDo_mux_0_reg[5]_6\ => reg_17_n_3,
      \slaveRegDo_mux_0_reg[7]\ => \slaveRegDo_mux_0[10]_i_7_n_0\,
      \slaveRegDo_mux_0_reg[8]\ => reg_9_n_2,
      \slaveRegDo_mux_0_reg[9]\ => \slaveRegDo_mux_0[9]_i_7_n_0\,
      \slaveRegDo_mux_0_reg[9]_0\ => reg_9_n_3,
      u_wcnt_hcmp_q => u_wcnt_hcmp_q,
      u_wcnt_lcmp_q => u_wcnt_lcmp_q,
      wcnt_hcmp_temp => wcnt_hcmp_temp,
      wcnt_lcmp_temp => wcnt_lcmp_temp,
      \xsdb_reg_reg[0]\ => arm_ctrl,
      \xsdb_reg_reg[0]_0\ => reg_6_n_0,
      \xsdb_reg_reg[11]\ => reg_7_n_9,
      \xsdb_reg_reg[12]\ => reg_7_n_10,
      \xsdb_reg_reg[13]\ => reg_7_n_11,
      \xsdb_reg_reg[14]\ => reg_7_n_12,
      \xsdb_reg_reg[15]\ => reg_7_n_13,
      \xsdb_reg_reg[6]\ => reg_7_n_14
    );
reg_8: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized23\
     port map (
      D(4) => clk_lost,
      D(3 downto 0) => \xsdb_reg_reg[3]\(3 downto 0),
      Q(4) => reg_8_n_0,
      Q(3) => reg_8_n_1,
      Q(2) => reg_8_n_2,
      Q(1) => reg_8_n_3,
      Q(0) => reg_8_n_4,
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den
    );
reg_80: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized42\
     port map (
      \G_1PIPE_IFACE.s_daddr_r_reg[6]\ => reg_80_n_1,
      \G_1PIPE_IFACE.s_den_r_reg\ => reg_80_n_0,
      s_daddr_o(12 downto 0) => s_daddr(12 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      s_dwe_o => s_dwe,
      slaveRegDo_80(15 downto 0) => slaveRegDo_80(15 downto 0)
    );
reg_81: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized43\
     port map (
      D(9) => reg_81_n_0,
      D(8) => reg_81_n_1,
      D(7) => reg_81_n_2,
      D(6) => reg_81_n_3,
      D(5) => reg_81_n_4,
      D(4) => reg_81_n_5,
      D(3) => reg_81_n_6,
      D(2) => reg_81_n_7,
      D(1) => reg_81_n_8,
      D(0) => reg_81_n_9,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      slaveRegDo_80(15 downto 0) => slaveRegDo_80(15 downto 0),
      slaveRegDo_82(15 downto 0) => slaveRegDo_82(15 downto 0),
      slaveRegDo_84(15 downto 0) => slaveRegDo_84(15 downto 0),
      \slaveRegDo_mux_0[0]_i_3\ => reg_83_n_15,
      \slaveRegDo_mux_0[10]_i_2\ => reg_83_n_5,
      \slaveRegDo_mux_0[11]_i_2\ => reg_83_n_4,
      \slaveRegDo_mux_0[12]_i_2\ => reg_83_n_3,
      \slaveRegDo_mux_0[13]_i_2\ => reg_83_n_2,
      \slaveRegDo_mux_0[14]_i_2\ => reg_83_n_1,
      \slaveRegDo_mux_0[15]_i_2\ => reg_83_n_0,
      \slaveRegDo_mux_0[1]_i_3\ => reg_83_n_14,
      \slaveRegDo_mux_0[2]_i_3\ => reg_83_n_13,
      \slaveRegDo_mux_0[3]_i_3\ => reg_83_n_12,
      \slaveRegDo_mux_0[4]_i_2\ => reg_83_n_11,
      \slaveRegDo_mux_0[5]_i_3\ => reg_83_n_10,
      \slaveRegDo_mux_0[6]_i_3\ => reg_83_n_9,
      \slaveRegDo_mux_0[7]_i_2\ => reg_83_n_8,
      \slaveRegDo_mux_0[8]_i_2\ => reg_83_n_7,
      \slaveRegDo_mux_0[9]_i_2\ => reg_83_n_6,
      \slaveRegDo_mux_0_reg[0]\ => reg_85_n_15,
      \slaveRegDo_mux_0_reg[10]\ => reg_7_n_15,
      \slaveRegDo_mux_0_reg[10]_0\ => reg_17_n_7,
      \slaveRegDo_mux_0_reg[10]_1\ => reg_19_n_5,
      \slaveRegDo_mux_0_reg[10]_2\ => reg_85_n_5,
      \slaveRegDo_mux_0_reg[11]\ => reg_19_n_4,
      \slaveRegDo_mux_0_reg[11]_0\ => reg_17_n_8,
      \slaveRegDo_mux_0_reg[11]_1\ => reg_7_n_9,
      \slaveRegDo_mux_0_reg[11]_2\ => reg_85_n_4,
      \slaveRegDo_mux_0_reg[12]\ => reg_19_n_3,
      \slaveRegDo_mux_0_reg[12]_0\ => reg_17_n_9,
      \slaveRegDo_mux_0_reg[12]_1\ => reg_7_n_10,
      \slaveRegDo_mux_0_reg[12]_2\ => reg_85_n_3,
      \slaveRegDo_mux_0_reg[13]\ => reg_19_n_2,
      \slaveRegDo_mux_0_reg[13]_0\ => reg_17_n_10,
      \slaveRegDo_mux_0_reg[13]_1\ => reg_7_n_11,
      \slaveRegDo_mux_0_reg[13]_2\ => reg_85_n_2,
      \slaveRegDo_mux_0_reg[14]\ => reg_19_n_1,
      \slaveRegDo_mux_0_reg[14]_0\ => reg_17_n_11,
      \slaveRegDo_mux_0_reg[14]_1\ => reg_7_n_12,
      \slaveRegDo_mux_0_reg[14]_2\ => reg_85_n_1,
      \slaveRegDo_mux_0_reg[15]\ => \slaveRegDo_mux_0[15]_i_3_n_0\,
      \slaveRegDo_mux_0_reg[15]_0\ => \slaveRegDo_mux_0[15]_i_7_n_0\,
      \slaveRegDo_mux_0_reg[15]_1\ => reg_19_n_0,
      \slaveRegDo_mux_0_reg[15]_2\ => reg_17_n_12,
      \slaveRegDo_mux_0_reg[15]_3\ => reg_7_n_13,
      \slaveRegDo_mux_0_reg[15]_4\ => \slaveRegDo_mux_0[15]_i_9_n_0\,
      \slaveRegDo_mux_0_reg[15]_5\ => reg_85_n_0,
      \slaveRegDo_mux_0_reg[1]\ => reg_85_n_14,
      \slaveRegDo_mux_0_reg[2]\ => reg_85_n_13,
      \slaveRegDo_mux_0_reg[3]\ => reg_85_n_12,
      \slaveRegDo_mux_0_reg[4]\ => reg_7_n_6,
      \slaveRegDo_mux_0_reg[4]_0\ => reg_19_n_10,
      \slaveRegDo_mux_0_reg[4]_1\ => reg_17_n_2,
      \slaveRegDo_mux_0_reg[4]_2\ => reg_85_n_11,
      \slaveRegDo_mux_0_reg[5]\ => reg_85_n_10,
      \slaveRegDo_mux_0_reg[6]\ => reg_85_n_9,
      \slaveRegDo_mux_0_reg[7]\ => reg_18_n_0,
      \slaveRegDo_mux_0_reg[7]_0\ => reg_7_n_17,
      \slaveRegDo_mux_0_reg[7]_1\ => reg_17_n_4,
      \slaveRegDo_mux_0_reg[7]_2\ => reg_85_n_8,
      \slaveRegDo_mux_0_reg[8]\ => reg_7_n_7,
      \slaveRegDo_mux_0_reg[8]_0\ => reg_19_n_7,
      \slaveRegDo_mux_0_reg[8]_1\ => reg_17_n_5,
      \slaveRegDo_mux_0_reg[8]_2\ => reg_85_n_7,
      \slaveRegDo_mux_0_reg[9]\ => reg_7_n_8,
      \slaveRegDo_mux_0_reg[9]_0\ => reg_19_n_6,
      \slaveRegDo_mux_0_reg[9]_1\ => reg_17_n_6,
      \slaveRegDo_mux_0_reg[9]_2\ => reg_85_n_6,
      \xsdb_reg_reg[0]\ => reg_81_n_10,
      \xsdb_reg_reg[0]_0\ => reg_80_n_0,
      \xsdb_reg_reg[1]\ => reg_81_n_11,
      \xsdb_reg_reg[2]\ => reg_81_n_12,
      \xsdb_reg_reg[3]\ => reg_81_n_13,
      \xsdb_reg_reg[5]\ => reg_81_n_14,
      \xsdb_reg_reg[6]\ => reg_81_n_15
    );
reg_82: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized44\
     port map (
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      slaveRegDo_82(15 downto 0) => slaveRegDo_82(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_80_n_0
    );
reg_83: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized45\
     port map (
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_83_n_15,
      \xsdb_reg_reg[0]_0\ => reg_80_n_0,
      \xsdb_reg_reg[10]\ => reg_83_n_5,
      \xsdb_reg_reg[11]\ => reg_83_n_4,
      \xsdb_reg_reg[12]\ => reg_83_n_3,
      \xsdb_reg_reg[13]\ => reg_83_n_2,
      \xsdb_reg_reg[14]\ => reg_83_n_1,
      \xsdb_reg_reg[15]\ => reg_83_n_0,
      \xsdb_reg_reg[1]\ => reg_83_n_14,
      \xsdb_reg_reg[2]\ => reg_83_n_13,
      \xsdb_reg_reg[3]\ => reg_83_n_12,
      \xsdb_reg_reg[4]\ => reg_83_n_11,
      \xsdb_reg_reg[5]\ => reg_83_n_10,
      \xsdb_reg_reg[6]\ => reg_83_n_9,
      \xsdb_reg_reg[7]\ => reg_83_n_8,
      \xsdb_reg_reg[8]\ => reg_83_n_7,
      \xsdb_reg_reg[9]\ => reg_83_n_6
    );
reg_84: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized46\
     port map (
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      slaveRegDo_84(15 downto 0) => slaveRegDo_84(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_80_n_0
    );
reg_85: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized47\
     port map (
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      \xsdb_reg_reg[0]\ => reg_85_n_15,
      \xsdb_reg_reg[0]_0\ => reg_80_n_0,
      \xsdb_reg_reg[10]\ => reg_85_n_5,
      \xsdb_reg_reg[11]\ => reg_85_n_4,
      \xsdb_reg_reg[12]\ => reg_85_n_3,
      \xsdb_reg_reg[13]\ => reg_85_n_2,
      \xsdb_reg_reg[14]\ => reg_85_n_1,
      \xsdb_reg_reg[15]\ => reg_85_n_0,
      \xsdb_reg_reg[1]\ => reg_85_n_14,
      \xsdb_reg_reg[2]\ => reg_85_n_13,
      \xsdb_reg_reg[3]\ => reg_85_n_12,
      \xsdb_reg_reg[4]\ => reg_85_n_11,
      \xsdb_reg_reg[5]\ => reg_85_n_10,
      \xsdb_reg_reg[6]\ => reg_85_n_9,
      \xsdb_reg_reg[7]\ => reg_85_n_8,
      \xsdb_reg_reg[8]\ => reg_85_n_7,
      \xsdb_reg_reg[9]\ => reg_85_n_6
    );
reg_887: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized49\
     port map (
      D(0) => reg_887_n_0,
      \out\ => dummy_temp,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_do_o(0) => slaveRegDo_890(3),
      slaveRegDo_mux_211_in => slaveRegDo_mux_211_in,
      \slaveRegDo_mux_2_reg[3]\ => \slaveRegDo_mux_2[6]_i_3_n_0\,
      \slaveRegDo_mux_2_reg[3]_0\ => \slaveRegDo_mux_2[3]_i_3_n_0\,
      \slaveRegDo_mux_2_reg[3]_1\(0) => \slaveRegDo_mux_1[3]_i_1_n_0\
    );
reg_88d: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized51\
     port map (
      D(1) => reg_88d_n_0,
      D(0) => reg_88d_n_1,
      s_daddr_o(4 downto 0) => s_daddr(4 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_do_o(1 downto 0) => slaveRegDo_890(1 downto 0),
      slaveRegDo_mux_211_in => slaveRegDo_mux_211_in,
      \slaveRegDo_mux_2_reg[1]\ => \slaveRegDo_mux_2[6]_i_3_n_0\,
      \slaveRegDo_mux_2_reg[1]_0\ => \slaveRegDo_mux_2[3]_i_3_n_0\,
      \slaveRegDo_mux_2_reg[1]_1\(1) => \slaveRegDo_mux_1[1]_i_1_n_0\,
      \slaveRegDo_mux_2_reg[1]_1\(0) => \slaveRegDo_mux_1[0]_i_1_n_0\,
      \xsdb_reg_reg[1]\(1 downto 0) => \xsdb_reg_reg[1]\(1 downto 0)
    );
reg_890: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized54\
     port map (
      din_i(15 downto 0) => B"0000000000000000",
      dout_o(15 downto 0) => NLW_reg_890_dout_o_UNCONNECTED(15 downto 0),
      rst_reg_i => '0',
      s_daddr_i(12 downto 0) => s_daddr(12 downto 0),
      s_dclk_i => \^s_dclk_o\,
      s_den_i => s_den,
      s_di_i(15 downto 0) => s_di(15 downto 0),
      s_do_o(15 downto 0) => slaveRegDo_890(15 downto 0),
      s_dwe_i => s_dwe
    );
reg_9: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg__parameterized24\
     port map (
      Q(0) => reg_8_n_4,
      s_daddr_o(3 downto 0) => s_daddr(3 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      \slaveRegDo_mux_0[9]_i_3\(3 downto 2) => slaveRegDo_6(9 downto 8),
      \slaveRegDo_mux_0[9]_i_3\(1 downto 0) => slaveRegDo_6(5 downto 4),
      \xsdb_reg_reg[0]\ => reg_9_n_4,
      \xsdb_reg_reg[4]\ => reg_9_n_0,
      \xsdb_reg_reg[5]\ => reg_9_n_1,
      \xsdb_reg_reg[7]\(4) => reg_9_n_5,
      \xsdb_reg_reg[7]\(3) => reg_9_n_6,
      \xsdb_reg_reg[7]\(2) => reg_9_n_7,
      \xsdb_reg_reg[7]\(1) => reg_9_n_8,
      \xsdb_reg_reg[7]\(0) => reg_9_n_9,
      \xsdb_reg_reg[8]\ => reg_9_n_2,
      \xsdb_reg_reg[9]\ => reg_9_n_3,
      \xsdb_reg_reg[9]_0\(9 downto 0) => \xsdb_reg_reg[9]\(9 downto 0)
    );
reg_srl_fff: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_p2s__parameterized6\
     port map (
      D(0) => D(0),
      E(0) => shift_en_reg(0),
      \G_1PIPE_IFACE.s_daddr_r_reg[3]\ => reg_srl_fff_n_2,
      \G_1PIPE_IFACE.s_di_r_reg[15]\ => reg_srl_fff_n_18,
      Q(6) => reg_stream_ffe_n_5,
      Q(5) => reg_stream_ffe_n_6,
      Q(4) => reg_stream_ffe_n_7,
      Q(3) => reg_stream_ffe_n_8,
      Q(2) => reg_stream_ffe_n_10,
      Q(1) => reg_stream_ffe_n_11,
      Q(0) => reg_stream_ffe_n_13,
      capture_ctrl_config_serial_output => capture_ctrl_config_serial_output,
      \parallel_dout_reg[11]_0\ => reg_srl_fff_n_11,
      \parallel_dout_reg[12]_0\ => reg_srl_fff_n_12,
      \parallel_dout_reg[13]_0\ => reg_srl_fff_n_13,
      \parallel_dout_reg[14]_0\ => reg_srl_fff_n_14,
      \parallel_dout_reg[1]_0\ => reg_srl_fff_n_3,
      \parallel_dout_reg[2]_0\ => reg_srl_fff_n_4,
      \parallel_dout_reg[3]_0\ => reg_srl_fff_n_5,
      \parallel_dout_reg[4]_0\ => reg_srl_fff_n_6,
      \parallel_dout_reg[5]_0\ => reg_srl_fff_n_7,
      \parallel_dout_reg[6]_0\ => reg_srl_fff_n_8,
      \parallel_dout_reg[8]_0\ => reg_srl_fff_n_9,
      \parallel_dout_reg[9]_0\ => reg_srl_fff_n_10,
      s_daddr_o(12 downto 0) => s_daddr(12 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      s_dwe_o => s_dwe,
      \slaveRegDo_ff8_reg[15]\ => reg_srl_fff_n_15,
      \slaveRegDo_ff8_reg[15]_0\ => reg_srl_fff_n_16,
      \slaveRegDo_ff8_reg[15]_1\ => reg_srl_fff_n_17,
      slaveRegDo_ff9(0) => slaveRegDo_ff9(5),
      \slaveRegDo_mux_3_reg[0]\ => \slaveRegDo_mux_3[5]_i_4_n_0\,
      \slaveRegDo_mux_3_reg[0]_0\ => reg_stream_ffd_n_0,
      \slaveRegDo_mux_3_reg[10]\ => \slaveRegDo_ff8_reg_n_0_[15]\,
      \slaveRegDo_mux_3_reg[14]\(6 downto 3) => \^debug_data_in\(14 downto 11),
      \slaveRegDo_mux_3_reg[14]\(2 downto 1) => \^debug_data_in\(9 downto 8),
      \slaveRegDo_mux_3_reg[14]\(0) => \^debug_data_in\(6),
      \slaveRegDo_mux_3_reg[1]\ => \slaveRegDo_mux_3[4]_i_2_n_0\,
      \slaveRegDo_mux_3_reg[1]_0\ => \slaveRegDo_mux_3[14]_i_2_n_0\,
      \slaveRegDo_mux_3_reg[1]_1\ => reg_stream_ffe_n_0,
      \slaveRegDo_mux_3_reg[2]\ => reg_stream_ffe_n_1,
      \slaveRegDo_mux_3_reg[3]\ => reg_stream_ffe_n_2,
      \slaveRegDo_mux_3_reg[4]\ => reg_stream_ffe_n_3,
      \slaveRegDo_mux_3_reg[5]\ => \slaveRegDo_mux_3[5]_i_2_n_0\,
      \slaveRegDo_mux_3_reg[5]_0\ => \slaveRegDo_mux_3[5]_i_3_n_0\,
      \slaveRegDo_mux_3_reg[5]_1\ => reg_stream_ffd_n_17,
      \slaveRegDo_mux_3_reg[6]\ => \slaveRegDo_mux_3[15]_i_3_n_0\,
      \slaveRegDo_mux_3_reg[6]_0\ => \slaveRegDo_mux_3[15]_i_4_n_0\
    );
reg_stream_ffd: entity work.ila_full_aurora_xsdbs_v1_0_2_reg_stream
     port map (
      Q(4) => reg_stream_ffe_n_4,
      Q(3) => reg_stream_ffe_n_9,
      Q(2) => reg_stream_ffe_n_12,
      Q(1) => reg_stream_ffe_n_14,
      Q(0) => reg_stream_ffe_n_15,
      s_daddr_o(5) => s_daddr(12),
      s_daddr_o(4 downto 3) => s_daddr(8 downto 7),
      s_daddr_o(2 downto 0) => s_daddr(2 downto 0),
      s_dclk_o => \^s_dclk_o\,
      s_den_o => s_den,
      s_di_o(15 downto 0) => s_di(15 downto 0),
      s_dwe_o => s_dwe,
      slaveRegDo_ffa(0) => slaveRegDo_ffa(5),
      \slaveRegDo_ffa_reg[5]\ => reg_stream_ffd_n_0,
      \slaveRegDo_ffa_reg[5]_0\ => reg_stream_ffd_n_17,
      \slaveRegDo_mux_3_reg[10]\ => reg_srl_fff_n_15,
      \slaveRegDo_mux_3_reg[15]\ => \slaveRegDo_mux_3[15]_i_3_n_0\,
      \slaveRegDo_mux_3_reg[15]_0\ => \slaveRegDo_mux_3[15]_i_4_n_0\,
      \slaveRegDo_mux_3_reg[15]_1\ => reg_srl_fff_n_17,
      \slaveRegDo_mux_3_reg[5]\ => \slaveRegDo_mux_3[5]_i_3_n_0\,
      \slaveRegDo_mux_3_reg[5]_0\ => \slaveRegDo_mux_3[5]_i_2_n_0\,
      \slaveRegDo_mux_3_reg[7]\ => reg_srl_fff_n_16,
      \xsdb_reg_reg[0]\ => \xsdb_reg[15]_i_3__2_n_0\,
      \xsdb_reg_reg[0]_0\ => \xsdb_reg[15]_i_4__1_n_0\,
      \xsdb_reg_reg[10]\ => reg_stream_ffd_n_19,
      \xsdb_reg_reg[15]\(15 downto 0) => \^debug_data_in\(15 downto 0),
      \xsdb_reg_reg[15]_0\ => reg_stream_ffd_n_20,
      \xsdb_reg_reg[7]\ => reg_stream_ffd_n_18
    );
reg_stream_ffe: entity work.\ila_full_aurora_xsdbs_v1_0_2_reg_stream__parameterized0\
     port map (
      E(0) => E(0),
      Q(11) => reg_stream_ffe_n_4,
      Q(10) => reg_stream_ffe_n_5,
      Q(9) => reg_stream_ffe_n_6,
      Q(8) => reg_stream_ffe_n_7,
      Q(7) => reg_stream_ffe_n_8,
      Q(6) => reg_stream_ffe_n_9,
      Q(5) => reg_stream_ffe_n_10,
      Q(4) => reg_stream_ffe_n_11,
      Q(3) => reg_stream_ffe_n_12,
      Q(2) => reg_stream_ffe_n_13,
      Q(1) => reg_stream_ffe_n_14,
      Q(0) => reg_stream_ffe_n_15,
      s_dclk_o => \^s_dclk_o\,
      slaveRegDo_ffa(0) => slaveRegDo_ffa(5),
      \slaveRegDo_mux_3_reg[4]\ => \slaveRegDo_mux_3[5]_i_2_n_0\,
      \slaveRegDo_mux_3_reg[4]_0\ => \slaveRegDo_mux_3[5]_i_3_n_0\,
      \slaveRegDo_mux_3_reg[4]_1\(3 downto 0) => \^debug_data_in\(4 downto 1),
      \slaveRegDo_mux_3_reg[4]_2\ => \slaveRegDo_mux_3[5]_i_4_n_0\,
      \xsdb_reg_reg[15]\(15 downto 0) => \xsdb_reg_reg[15]\(15 downto 0),
      \xsdb_reg_reg[1]\ => reg_stream_ffe_n_0,
      \xsdb_reg_reg[2]\ => reg_stream_ffe_n_1,
      \xsdb_reg_reg[3]\ => reg_stream_ffe_n_2,
      \xsdb_reg_reg[4]\ => reg_stream_ffe_n_3
    );
s_dclk_flag_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => s_dclk_flag,
      I1 => next_state_xsdb,
      I2 => ila_clk_flag_sync2,
      O => s_dclk_flag_i_1_n_0
    );
s_dclk_flag_reg: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => s_dclk_flag_i_1_n_0,
      Q => s_dclk_flag,
      R => s_rst
    );
s_dclk_flag_sync1_reg: unisim.vcomponents.FDRE
     port map (
      C => ila_clk_flag_reg_0,
      CE => '1',
      D => s_dclk_flag,
      Q => s_dclk_flag_sync1,
      R => '0'
    );
s_dclk_flag_sync2_reg: unisim.vcomponents.FDRE
     port map (
      C => ila_clk_flag_reg_0,
      CE => '1',
      D => s_dclk_flag_sync1,
      Q => s_dclk_flag_sync2,
      R => '0'
    );
\shift_reg0[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF2F2F2"
    )
        port map (
      I0 => \shift_reg0_reg_n_0_[5]\,
      I1 => drdy_ff9,
      I2 => s_rst,
      I3 => \shift_reg0[5]_i_2_n_0\,
      I4 => \shift_reg0[5]_i_3_n_0\,
      O => \shift_reg0[5]_i_1_n_0\
    );
\shift_reg0[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => count0_reg(6),
      I1 => count0_reg(5),
      I2 => count0_reg(4),
      I3 => count0_reg(3),
      O => \shift_reg0[5]_i_2_n_0\
    );
\shift_reg0[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => count0_reg(2),
      I1 => count0_reg(1),
      I2 => count0_reg(0),
      O => \shift_reg0[5]_i_3_n_0\
    );
\shift_reg0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \shift_reg0[5]_i_1_n_0\,
      Q => \shift_reg0_reg_n_0_[5]\,
      R => '0'
    );
\shift_reg1[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF2F2F2"
    )
        port map (
      I0 => \shift_reg1_reg_n_0_[5]\,
      I1 => drdy_ffa,
      I2 => s_rst,
      I3 => \shift_reg1[5]_i_2_n_0\,
      I4 => \shift_reg1[5]_i_3_n_0\,
      O => \shift_reg1[5]_i_1_n_0\
    );
\shift_reg1[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => count1_reg(6),
      I1 => count1_reg(5),
      I2 => count1_reg(4),
      I3 => count1_reg(3),
      O => \shift_reg1[5]_i_2_n_0\
    );
\shift_reg1[5]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => count1_reg(2),
      I1 => count1_reg(1),
      I2 => count1_reg(0),
      O => \shift_reg1[5]_i_3_n_0\
    );
\shift_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \shift_reg1[5]_i_1_n_0\,
      Q => \shift_reg1_reg_n_0_[5]\,
      R => '0'
    );
\slaveRegDo_ff8[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"72"
    )
        port map (
      I0 => xsdb_rden_ff8,
      I1 => count_tt,
      I2 => \slaveRegDo_ff8_reg_n_0_[15]\,
      O => \slaveRegDo_ff8[15]_i_1_n_0\
    );
\slaveRegDo_ff8[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D8"
    )
        port map (
      I0 => xsdb_rden_ff8,
      I1 => count_tt,
      I2 => \slaveRegDo_ff8_reg_n_0_[4]\,
      O => \slaveRegDo_ff8[4]_i_1_n_0\
    );
\slaveRegDo_ff8_reg[15]\: unisim.vcomponents.FDSE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_ff8[15]_i_1_n_0\,
      Q => \slaveRegDo_ff8_reg_n_0_[15]\,
      S => s_rst
    );
\slaveRegDo_ff8_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_ff8[4]_i_1_n_0\,
      Q => \slaveRegDo_ff8_reg_n_0_[4]\,
      R => s_rst
    );
\slaveRegDo_ff9_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \shift_reg0_reg_n_0_[5]\,
      Q => slaveRegDo_ff9(5),
      R => s_rst
    );
\slaveRegDo_ffa_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \shift_reg1_reg_n_0_[5]\,
      Q => slaveRegDo_ffa(5),
      R => s_rst
    );
\slaveRegDo_mux[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[0]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(0),
      I2 => slaveRegDo_mux_5(0),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(0)
    );
\slaveRegDo_mux[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(0),
      I1 => slaveRegDo_mux_3(0),
      I2 => slaveRegDo_mux_0(0),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(0),
      O => \slaveRegDo_mux[0]_i_2_n_0\
    );
\slaveRegDo_mux[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[10]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(10),
      I2 => slaveRegDo_mux_5(10),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(10)
    );
\slaveRegDo_mux[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(10),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(10),
      I4 => slaveRegDo_mux_0(10),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[10]_i_2_n_0\
    );
\slaveRegDo_mux[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[11]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(11),
      I2 => slaveRegDo_mux_5(11),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(11)
    );
\slaveRegDo_mux[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(11),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(11),
      I4 => slaveRegDo_mux_0(11),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[11]_i_2_n_0\
    );
\slaveRegDo_mux[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[12]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(12),
      I2 => slaveRegDo_mux_5(12),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(12)
    );
\slaveRegDo_mux[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(12),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(12),
      I4 => slaveRegDo_mux_0(12),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[12]_i_2_n_0\
    );
\slaveRegDo_mux[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[13]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(13),
      I2 => slaveRegDo_mux_5(13),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(13)
    );
\slaveRegDo_mux[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(13),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(13),
      I4 => slaveRegDo_mux_0(13),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[13]_i_2_n_0\
    );
\slaveRegDo_mux[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[14]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(14),
      I2 => slaveRegDo_mux_5(14),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(14)
    );
\slaveRegDo_mux[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(14),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(14),
      I4 => slaveRegDo_mux_0(14),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[14]_i_2_n_0\
    );
\slaveRegDo_mux[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[15]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(15),
      I2 => slaveRegDo_mux_5(15),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(15)
    );
\slaveRegDo_mux[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(15),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(15),
      I4 => slaveRegDo_mux_0(15),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[15]_i_2_n_0\
    );
\slaveRegDo_mux[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[1]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(1),
      I2 => slaveRegDo_mux_5(1),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(1)
    );
\slaveRegDo_mux[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(1),
      I1 => slaveRegDo_mux_3(1),
      I2 => slaveRegDo_mux_0(1),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(1),
      O => \slaveRegDo_mux[1]_i_2_n_0\
    );
\slaveRegDo_mux[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[2]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(2),
      I2 => slaveRegDo_mux_5(2),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(2)
    );
\slaveRegDo_mux[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(2),
      I1 => slaveRegDo_mux_3(2),
      I2 => slaveRegDo_mux_0(2),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(2),
      O => \slaveRegDo_mux[2]_i_2_n_0\
    );
\slaveRegDo_mux[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[3]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(3),
      I2 => slaveRegDo_mux_5(3),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(3)
    );
\slaveRegDo_mux[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(3),
      I1 => slaveRegDo_mux_3(3),
      I2 => slaveRegDo_mux_0(3),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(3),
      O => \slaveRegDo_mux[3]_i_2_n_0\
    );
\slaveRegDo_mux[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[4]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(4),
      I2 => slaveRegDo_mux_5(4),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(4)
    );
\slaveRegDo_mux[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(4),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(4),
      I4 => slaveRegDo_mux_0(4),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[4]_i_2_n_0\
    );
\slaveRegDo_mux[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[5]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(5),
      I2 => slaveRegDo_mux_5(5),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(5)
    );
\slaveRegDo_mux[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(5),
      I1 => slaveRegDo_mux_3(5),
      I2 => slaveRegDo_mux_0(5),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(5),
      O => \slaveRegDo_mux[5]_i_2_n_0\
    );
\slaveRegDo_mux[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F000CCAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[6]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(6),
      I2 => slaveRegDo_mux_5(6),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(6)
    );
\slaveRegDo_mux[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => slaveRegDo_mux_1(6),
      I1 => slaveRegDo_mux_3(6),
      I2 => slaveRegDo_mux_0(6),
      I3 => s_daddr(10),
      I4 => s_daddr(11),
      I5 => slaveRegDo_mux_2(6),
      O => \slaveRegDo_mux[6]_i_2_n_0\
    );
\slaveRegDo_mux[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[7]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(7),
      I2 => slaveRegDo_mux_5(7),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(7)
    );
\slaveRegDo_mux[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(7),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(7),
      I4 => slaveRegDo_mux_0(7),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[7]_i_2_n_0\
    );
\slaveRegDo_mux[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[8]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(8),
      I2 => slaveRegDo_mux_5(8),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(8)
    );
\slaveRegDo_mux[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(8),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(8),
      I4 => slaveRegDo_mux_0(8),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[8]_i_2_n_0\
    );
\slaveRegDo_mux[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEEAAAAAAAA"
    )
        port map (
      I0 => \slaveRegDo_mux[9]_i_2_n_0\,
      I1 => slaveRegDo_mux_4(9),
      I2 => slaveRegDo_mux_5(9),
      I3 => s_daddr(11),
      I4 => s_daddr(10),
      I5 => s_daddr(12),
      O => slaveRegDo_mux(9)
    );
\slaveRegDo_mux[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000B383B080"
    )
        port map (
      I0 => slaveRegDo_mux_3(9),
      I1 => s_daddr(10),
      I2 => s_daddr(11),
      I3 => slaveRegDo_mux_2(9),
      I4 => slaveRegDo_mux_0(9),
      I5 => s_daddr(12),
      O => \slaveRegDo_mux[9]_i_2_n_0\
    );
\slaveRegDo_mux_0[10]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0051"
    )
        port map (
      I0 => s_daddr(5),
      I1 => s_daddr(4),
      I2 => s_daddr(7),
      I3 => s_daddr(3),
      O => \slaveRegDo_mux_0[10]_i_7_n_0\
    );
\slaveRegDo_mux_0[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \slaveRegDo_mux_01__6\,
      I1 => s_daddr(8),
      I2 => s_daddr(9),
      I3 => s_daddr(6),
      O => \slaveRegDo_mux_0[15]_i_10_n_0\
    );
\slaveRegDo_mux_0[15]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AE00"
    )
        port map (
      I0 => s_daddr(5),
      I1 => s_daddr(4),
      I2 => s_daddr(7),
      I3 => s_daddr(3),
      I4 => s_daddr(2),
      O => \slaveRegDo_mux_0[15]_i_11_n_0\
    );
\slaveRegDo_mux_0[15]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40404440"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(2),
      I2 => s_daddr(5),
      I3 => s_daddr(4),
      I4 => s_daddr(7),
      O => \slaveRegDo_mux_0[15]_i_12_n_0\
    );
\slaveRegDo_mux_0[15]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_daddr(2),
      I1 => s_daddr(3),
      O => \slaveRegDo_mux_0[15]_i_13_n_0\
    );
\slaveRegDo_mux_0[15]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => s_daddr(7),
      I1 => s_daddr(4),
      I2 => s_daddr(5),
      O => \slaveRegDo_mux_0[15]_i_14_n_0\
    );
\slaveRegDo_mux_0[15]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => \slaveRegDo_mux_0[15]_i_10_n_0\,
      I1 => s_daddr(4),
      I2 => s_daddr(3),
      I3 => s_daddr(5),
      I4 => s_daddr(7),
      O => \slaveRegDo_mux_0[15]_i_3_n_0\
    );
\slaveRegDo_mux_0[15]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => s_daddr(6),
      I1 => s_daddr(9),
      I2 => s_daddr(8),
      I3 => \slaveRegDo_mux_01__6\,
      I4 => s_daddr(7),
      I5 => s_daddr(5),
      O => \slaveRegDo_mux_0[15]_i_7_n_0\
    );
\slaveRegDo_mux_0[15]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(2),
      I2 => s_daddr(4),
      O => \slaveRegDo_mux_0[15]_i_9_n_0\
    );
\slaveRegDo_mux_0[3]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => s_daddr(2),
      I1 => s_daddr(3),
      O => \slaveRegDo_mux_0[3]_i_9_n_0\
    );
\slaveRegDo_mux_0[6]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(5),
      I3 => s_daddr(6),
      O => \slaveRegDo_mux_0[6]_i_10_n_0\
    );
\slaveRegDo_mux_0[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF8A88"
    )
        port map (
      I0 => s_daddr(7),
      I1 => \slaveRegDo_mux_0[6]_i_10_n_0\,
      I2 => \slaveRegDo_mux_0[9]_i_7_n_0\,
      I3 => s_daddr(2),
      I4 => s_daddr(9),
      I5 => s_daddr(8),
      O => \slaveRegDo_mux_01__6\
    );
\slaveRegDo_mux_0[7]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_daddr(0),
      I1 => s_daddr(1),
      O => \slaveRegDo_mux_0[7]_i_8_n_0\
    );
\slaveRegDo_mux_0[9]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => s_daddr(0),
      I1 => s_daddr(1),
      O => \slaveRegDo_mux_0[9]_i_7_n_0\
    );
\slaveRegDo_mux_0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_17_n_1,
      Q => slaveRegDo_mux_0(0),
      R => '0'
    );
\slaveRegDo_mux_0_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_5,
      Q => slaveRegDo_mux_0(10),
      R => '0'
    );
\slaveRegDo_mux_0_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_4,
      Q => slaveRegDo_mux_0(11),
      R => '0'
    );
\slaveRegDo_mux_0_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_3,
      Q => slaveRegDo_mux_0(12),
      R => '0'
    );
\slaveRegDo_mux_0_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_2,
      Q => slaveRegDo_mux_0(13),
      R => '0'
    );
\slaveRegDo_mux_0_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_1,
      Q => slaveRegDo_mux_0(14),
      R => '0'
    );
\slaveRegDo_mux_0_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_0,
      Q => slaveRegDo_mux_0(15),
      R => '0'
    );
\slaveRegDo_mux_0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_7_n_3,
      Q => slaveRegDo_mux_0(1),
      R => '0'
    );
\slaveRegDo_mux_0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_7_n_2,
      Q => slaveRegDo_mux_0(2),
      R => '0'
    );
\slaveRegDo_mux_0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_7_n_1,
      Q => slaveRegDo_mux_0(3),
      R => '0'
    );
\slaveRegDo_mux_0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_9,
      Q => slaveRegDo_mux_0(4),
      R => '0'
    );
\slaveRegDo_mux_0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_7_n_0,
      Q => slaveRegDo_mux_0(5),
      R => '0'
    );
\slaveRegDo_mux_0_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_17_n_0,
      Q => slaveRegDo_mux_0(6),
      R => '0'
    );
\slaveRegDo_mux_0_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_8,
      Q => slaveRegDo_mux_0(7),
      R => '0'
    );
\slaveRegDo_mux_0_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_7,
      Q => slaveRegDo_mux_0(8),
      R => '0'
    );
\slaveRegDo_mux_0_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_81_n_6,
      Q => slaveRegDo_mux_0(9),
      R => '0'
    );
\slaveRegDo_mux_1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002E0200"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(2),
      I3 => s_daddr(4),
      I4 => s_daddr(3),
      O => \slaveRegDo_mux_1[0]_i_1_n_0\
    );
\slaveRegDo_mux_1[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(2),
      I3 => s_daddr(0),
      O => \slaveRegDo_mux_1[1]_i_1_n_0\
    );
\slaveRegDo_mux_1[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(2),
      I3 => s_daddr(0),
      O => \slaveRegDo_mux_1[2]_i_1_n_0\
    );
\slaveRegDo_mux_1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(2),
      I3 => s_daddr(0),
      I4 => s_daddr(1),
      O => \slaveRegDo_mux_1[3]_i_1_n_0\
    );
\slaveRegDo_mux_1[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20000400"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(2),
      I3 => s_daddr(0),
      I4 => s_daddr(1),
      O => \slaveRegDo_mux_1[5]_i_1_n_0\
    );
\slaveRegDo_mux_1[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0F0FF8F"
    )
        port map (
      I0 => s_daddr(0),
      I1 => s_daddr(1),
      I2 => s_daddr(4),
      I3 => s_daddr(2),
      I4 => s_daddr(3),
      O => \slaveRegDo_mux_1[6]_i_1_n_0\
    );
\slaveRegDo_mux_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[0]_i_1_n_0\,
      Q => slaveRegDo_mux_1(0),
      R => '0'
    );
\slaveRegDo_mux_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[1]_i_1_n_0\,
      Q => slaveRegDo_mux_1(1),
      R => '0'
    );
\slaveRegDo_mux_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[2]_i_1_n_0\,
      Q => slaveRegDo_mux_1(2),
      R => '0'
    );
\slaveRegDo_mux_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[3]_i_1_n_0\,
      Q => slaveRegDo_mux_1(3),
      R => '0'
    );
\slaveRegDo_mux_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[5]_i_1_n_0\,
      Q => slaveRegDo_mux_1(5),
      R => '0'
    );
\slaveRegDo_mux_1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_1[6]_i_1_n_0\,
      Q => slaveRegDo_mux_1(6),
      R => '0'
    );
\slaveRegDo_mux_2[15]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \slaveRegDo_mux_2[6]_i_3_n_0\,
      O => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \slaveRegDo_mux_1[2]_i_1_n_0\,
      I1 => slaveRegDo_mux_211_in,
      I2 => slaveRegDo_890(2),
      I3 => \slaveRegDo_mux_2[6]_i_3_n_0\,
      O => \slaveRegDo_mux_2[2]_i_1_n_0\
    );
\slaveRegDo_mux_2[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \slaveRegDo_mux_2[3]_i_4_n_0\,
      I1 => slaveRegDo_mux_211_in,
      O => \slaveRegDo_mux_2[3]_i_3_n_0\
    );
\slaveRegDo_mux_2[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FB00000000"
    )
        port map (
      I0 => s_daddr(2),
      I1 => s_daddr(3),
      I2 => s_daddr(4),
      I3 => reg_80_n_1,
      I4 => \slaveRegDo_mux_2[6]_i_4_n_0\,
      I5 => s_daddr(7),
      O => \slaveRegDo_mux_2[3]_i_4_n_0\
    );
\slaveRegDo_mux_2[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \slaveRegDo_mux_1[5]_i_1_n_0\,
      I1 => slaveRegDo_mux_211_in,
      I2 => slaveRegDo_890(5),
      I3 => \slaveRegDo_mux_2[6]_i_3_n_0\,
      O => \slaveRegDo_mux_2[5]_i_1_n_0\
    );
\slaveRegDo_mux_2[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \slaveRegDo_mux_1[6]_i_1_n_0\,
      I1 => slaveRegDo_mux_211_in,
      I2 => slaveRegDo_890(6),
      I3 => \slaveRegDo_mux_2[6]_i_3_n_0\,
      O => \slaveRegDo_mux_2[6]_i_1_n_0\
    );
\slaveRegDo_mux_2[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055557FFF"
    )
        port map (
      I0 => s_daddr(7),
      I1 => s_daddr(0),
      I2 => s_daddr(1),
      I3 => s_daddr(2),
      I4 => \slaveRegDo_mux_0[6]_i_10_n_0\,
      I5 => \slaveRegDo_mux_2[6]_i_4_n_0\,
      O => slaveRegDo_mux_211_in
    );
\slaveRegDo_mux_2[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => s_daddr(4),
      I1 => s_daddr(2),
      I2 => \slaveRegDo_mux_2[3]_i_3_n_0\,
      I3 => s_daddr(3),
      I4 => s_daddr(1),
      I5 => s_daddr(0),
      O => \slaveRegDo_mux_2[6]_i_3_n_0\
    );
\slaveRegDo_mux_2[6]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_daddr(8),
      I1 => s_daddr(9),
      O => \slaveRegDo_mux_2[6]_i_4_n_0\
    );
\slaveRegDo_mux_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_88d_n_1,
      Q => slaveRegDo_mux_2(0),
      R => '0'
    );
\slaveRegDo_mux_2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(10),
      Q => slaveRegDo_mux_2(10),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(11),
      Q => slaveRegDo_mux_2(11),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(12),
      Q => slaveRegDo_mux_2(12),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(13),
      Q => slaveRegDo_mux_2(13),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(14),
      Q => slaveRegDo_mux_2(14),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(15),
      Q => slaveRegDo_mux_2(15),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_88d_n_0,
      Q => slaveRegDo_mux_2(1),
      R => '0'
    );
\slaveRegDo_mux_2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_2[2]_i_1_n_0\,
      Q => slaveRegDo_mux_2(2),
      R => '0'
    );
\slaveRegDo_mux_2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_887_n_0,
      Q => slaveRegDo_mux_2(3),
      R => '0'
    );
\slaveRegDo_mux_2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(4),
      Q => slaveRegDo_mux_2(4),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_2[5]_i_1_n_0\,
      Q => slaveRegDo_mux_2(5),
      R => '0'
    );
\slaveRegDo_mux_2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \slaveRegDo_mux_2[6]_i_1_n_0\,
      Q => slaveRegDo_mux_2(6),
      R => '0'
    );
\slaveRegDo_mux_2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(7),
      Q => slaveRegDo_mux_2(7),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(8),
      Q => slaveRegDo_mux_2(8),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_890(9),
      Q => slaveRegDo_mux_2(9),
      R => \slaveRegDo_mux_2[15]_i_1_n_0\
    );
\slaveRegDo_mux_3[14]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(2),
      I3 => s_daddr(3),
      O => \slaveRegDo_mux_3[14]_i_2_n_0\
    );
\slaveRegDo_mux_3[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => s_daddr(9),
      I1 => s_daddr(8),
      I2 => s_daddr(7),
      I3 => s_daddr(6),
      I4 => s_daddr(5),
      I5 => s_daddr(4),
      O => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(2),
      I3 => s_daddr(3),
      O => \slaveRegDo_mux_3[15]_i_3_n_0\
    );
\slaveRegDo_mux_3[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => s_daddr(1),
      I1 => s_daddr(0),
      I2 => s_daddr(2),
      I3 => s_daddr(3),
      O => \slaveRegDo_mux_3[15]_i_4_n_0\
    );
\slaveRegDo_mux_3[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0054000000040000"
    )
        port map (
      I0 => s_daddr(1),
      I1 => \slaveRegDo_ff8_reg_n_0_[4]\,
      I2 => s_daddr(0),
      I3 => s_daddr(2),
      I4 => s_daddr(3),
      I5 => slaveRegDo_ff9(5),
      O => \slaveRegDo_mux_3[4]_i_2_n_0\
    );
\slaveRegDo_mux_3[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7D"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(2),
      I2 => s_daddr(0),
      O => \slaveRegDo_mux_3[5]_i_2_n_0\
    );
\slaveRegDo_mux_3[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2822"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(1),
      I2 => s_daddr(0),
      I3 => s_daddr(2),
      O => \slaveRegDo_mux_3[5]_i_3_n_0\
    );
\slaveRegDo_mux_3[5]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3FF5"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(0),
      I2 => s_daddr(1),
      I3 => s_daddr(2),
      O => \slaveRegDo_mux_3[5]_i_4_n_0\
    );
\slaveRegDo_mux_3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_2,
      Q => slaveRegDo_mux_3(0),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_stream_ffd_n_19,
      Q => slaveRegDo_mux_3(10),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_11,
      Q => slaveRegDo_mux_3(11),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_12,
      Q => slaveRegDo_mux_3(12),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_13,
      Q => slaveRegDo_mux_3(13),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_14,
      Q => slaveRegDo_mux_3(14),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_stream_ffd_n_20,
      Q => slaveRegDo_mux_3(15),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_3,
      Q => slaveRegDo_mux_3(1),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_4,
      Q => slaveRegDo_mux_3(2),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_5,
      Q => slaveRegDo_mux_3(3),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_6,
      Q => slaveRegDo_mux_3(4),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_7,
      Q => slaveRegDo_mux_3(5),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_8,
      Q => slaveRegDo_mux_3(6),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_stream_ffd_n_18,
      Q => slaveRegDo_mux_3(7),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_9,
      Q => slaveRegDo_mux_3(8),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => reg_srl_fff_n_10,
      Q => slaveRegDo_mux_3(9),
      R => \slaveRegDo_mux_3[15]_i_1_n_0\
    );
\slaveRegDo_mux_4_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_18\,
      Q => slaveRegDo_mux_4(0),
      R => '0'
    );
\slaveRegDo_mux_4_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_8\,
      Q => slaveRegDo_mux_4(10),
      R => '0'
    );
\slaveRegDo_mux_4_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_7\,
      Q => slaveRegDo_mux_4(11),
      R => '0'
    );
\slaveRegDo_mux_4_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_6\,
      Q => slaveRegDo_mux_4(12),
      R => '0'
    );
\slaveRegDo_mux_4_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_5\,
      Q => slaveRegDo_mux_4(13),
      R => '0'
    );
\slaveRegDo_mux_4_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_4\,
      Q => slaveRegDo_mux_4(14),
      R => '0'
    );
\slaveRegDo_mux_4_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_3\,
      Q => slaveRegDo_mux_4(15),
      R => '0'
    );
\slaveRegDo_mux_4_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_17\,
      Q => slaveRegDo_mux_4(1),
      R => '0'
    );
\slaveRegDo_mux_4_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_16\,
      Q => slaveRegDo_mux_4(2),
      R => '0'
    );
\slaveRegDo_mux_4_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_15\,
      Q => slaveRegDo_mux_4(3),
      R => '0'
    );
\slaveRegDo_mux_4_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_14\,
      Q => slaveRegDo_mux_4(4),
      R => '0'
    );
\slaveRegDo_mux_4_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_13\,
      Q => slaveRegDo_mux_4(5),
      R => '0'
    );
\slaveRegDo_mux_4_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_12\,
      Q => slaveRegDo_mux_4(6),
      R => '0'
    );
\slaveRegDo_mux_4_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_11\,
      Q => slaveRegDo_mux_4(7),
      R => '0'
    );
\slaveRegDo_mux_4_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_10\,
      Q => slaveRegDo_mux_4(8),
      R => '0'
    );
\slaveRegDo_mux_4_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \MU_SRL[1].mu_srl_reg_n_9\,
      Q => slaveRegDo_mux_4(9),
      R => '0'
    );
\slaveRegDo_mux_5_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_18\,
      Q => slaveRegDo_mux_5(0),
      R => '0'
    );
\slaveRegDo_mux_5_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_8\,
      Q => slaveRegDo_mux_5(10),
      R => '0'
    );
\slaveRegDo_mux_5_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_7\,
      Q => slaveRegDo_mux_5(11),
      R => '0'
    );
\slaveRegDo_mux_5_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_6\,
      Q => slaveRegDo_mux_5(12),
      R => '0'
    );
\slaveRegDo_mux_5_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_5\,
      Q => slaveRegDo_mux_5(13),
      R => '0'
    );
\slaveRegDo_mux_5_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_4\,
      Q => slaveRegDo_mux_5(14),
      R => '0'
    );
\slaveRegDo_mux_5_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_3\,
      Q => slaveRegDo_mux_5(15),
      R => '0'
    );
\slaveRegDo_mux_5_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_17\,
      Q => slaveRegDo_mux_5(1),
      R => '0'
    );
\slaveRegDo_mux_5_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_16\,
      Q => slaveRegDo_mux_5(2),
      R => '0'
    );
\slaveRegDo_mux_5_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_15\,
      Q => slaveRegDo_mux_5(3),
      R => '0'
    );
\slaveRegDo_mux_5_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_14\,
      Q => slaveRegDo_mux_5(4),
      R => '0'
    );
\slaveRegDo_mux_5_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_13\,
      Q => slaveRegDo_mux_5(5),
      R => '0'
    );
\slaveRegDo_mux_5_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_12\,
      Q => slaveRegDo_mux_5(6),
      R => '0'
    );
\slaveRegDo_mux_5_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_11\,
      Q => slaveRegDo_mux_5(7),
      R => '0'
    );
\slaveRegDo_mux_5_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_10\,
      Q => slaveRegDo_mux_5(8),
      R => '0'
    );
\slaveRegDo_mux_5_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => \TC_SRL[0].tc_srl_reg_n_9\,
      Q => slaveRegDo_mux_5(9),
      R => '0'
    );
\slaveRegDo_mux_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(0),
      Q => \slaveRegDo_mux_reg_n_0_[0]\,
      R => '0'
    );
\slaveRegDo_mux_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(10),
      Q => \slaveRegDo_mux_reg_n_0_[10]\,
      R => '0'
    );
\slaveRegDo_mux_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(11),
      Q => \slaveRegDo_mux_reg_n_0_[11]\,
      R => '0'
    );
\slaveRegDo_mux_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(12),
      Q => \slaveRegDo_mux_reg_n_0_[12]\,
      R => '0'
    );
\slaveRegDo_mux_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(13),
      Q => \slaveRegDo_mux_reg_n_0_[13]\,
      R => '0'
    );
\slaveRegDo_mux_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(14),
      Q => \slaveRegDo_mux_reg_n_0_[14]\,
      R => '0'
    );
\slaveRegDo_mux_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(15),
      Q => \slaveRegDo_mux_reg_n_0_[15]\,
      R => '0'
    );
\slaveRegDo_mux_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(1),
      Q => \slaveRegDo_mux_reg_n_0_[1]\,
      R => '0'
    );
\slaveRegDo_mux_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(2),
      Q => \slaveRegDo_mux_reg_n_0_[2]\,
      R => '0'
    );
\slaveRegDo_mux_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(3),
      Q => \slaveRegDo_mux_reg_n_0_[3]\,
      R => '0'
    );
\slaveRegDo_mux_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(4),
      Q => \slaveRegDo_mux_reg_n_0_[4]\,
      R => '0'
    );
\slaveRegDo_mux_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(5),
      Q => \slaveRegDo_mux_reg_n_0_[5]\,
      R => '0'
    );
\slaveRegDo_mux_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(6),
      Q => \slaveRegDo_mux_reg_n_0_[6]\,
      R => '0'
    );
\slaveRegDo_mux_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(7),
      Q => \slaveRegDo_mux_reg_n_0_[7]\,
      R => '0'
    );
\slaveRegDo_mux_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(8),
      Q => \slaveRegDo_mux_reg_n_0_[8]\,
      R => '0'
    );
\slaveRegDo_mux_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^s_dclk_o\,
      CE => '1',
      D => slaveRegDo_mux(9),
      Q => \slaveRegDo_mux_reg_n_0_[9]\,
      R => '0'
    );
u_srlD_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[0].mu_srl_reg_n_0\,
      I1 => \MU_SRL[0].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(0),
      O => mu_config_cs_serial_output(0)
    );
\u_srlD_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[1].mu_srl_reg_n_0\,
      I1 => \MU_SRL[1].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(1),
      O => mu_config_cs_serial_output(1)
    );
\u_srlD_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[2].mu_srl_reg_n_0\,
      I1 => \MU_SRL[2].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(2),
      O => mu_config_cs_serial_output(2)
    );
\u_srlD_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[3].mu_srl_reg_n_0\,
      I1 => \MU_SRL[3].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(3),
      O => mu_config_cs_serial_output(3)
    );
\u_srlD_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[4].mu_srl_reg_n_0\,
      I1 => \MU_SRL[4].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(4),
      O => mu_config_cs_serial_output(4)
    );
\u_srlD_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MU_SRL[5].mu_srl_reg_n_0\,
      I1 => \MU_SRL[5].mu_srl_reg_n_2\,
      I2 => mu_config_cs_serial_input(5),
      O => mu_config_cs_serial_output(5)
    );
\xsdb_reg[15]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => s_daddr(3),
      I1 => s_daddr(4),
      I2 => s_daddr(5),
      O => \xsdb_reg[15]_i_3__2_n_0\
    );
\xsdb_reg[15]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8F00000000000000"
    )
        port map (
      I0 => s_daddr(6),
      I1 => s_daddr(7),
      I2 => s_daddr(8),
      I3 => s_daddr(9),
      I4 => s_daddr(10),
      I5 => s_daddr(11),
      O => \xsdb_reg[15]_i_4__1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_allx_typeA is
  port (
    \out\ : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    tc_config_cs_serial_output : in STD_LOGIC;
    \parallel_dout_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_allx_typeA : entity is "ltlib_v1_0_0_allx_typeA";
end ila_full_aurora_ltlib_v1_0_0_allx_typeA;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_allx_typeA is
  signal all_dly2 : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
DUT: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_24
     port map (
      D(5 downto 0) => D(5 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\(0) => Q(0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(5 downto 0) => all_dly2(5 downto 0),
      \out\ => \out\,
      \parallel_dout_reg[15]\(0) => \parallel_dout_reg[15]\(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg(0) => shift_en_reg(0),
      tc_config_cs_serial_output => tc_config_cs_serial_output
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(0),
      Q => all_dly2(0),
      R => '0'
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(1),
      Q => all_dly2(1),
      R => '0'
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(2),
      Q => all_dly2(2),
      R => '0'
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(3),
      Q => all_dly2(3),
      R => '0'
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(4),
      Q => all_dly2(4),
      R => '0'
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => D(5),
      Q => all_dly2(5),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized0\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \probeDelay1_reg[16]_0\ : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 47 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized0\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized0\ is
  signal all_in : STD_LOGIC_VECTOR ( 127 downto 0 );
begin
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized0\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_in(127 downto 0) => all_in(127 downto 0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(0),
      Q => all_in(1),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(20),
      Q => all_in(21),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(22),
      Q => all_in(23),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(24),
      Q => all_in(25),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(26),
      Q => all_in(27),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(28),
      Q => all_in(29),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(30),
      Q => all_in(31),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(32),
      Q => all_in(33),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(34),
      Q => all_in(35),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(36),
      Q => all_in(37),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(38),
      Q => all_in(39),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(2),
      Q => all_in(3),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(40),
      Q => all_in(41),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(42),
      Q => all_in(43),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(44),
      Q => all_in(45),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(46),
      Q => all_in(47),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(48),
      Q => all_in(49),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(50),
      Q => all_in(51),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(52),
      Q => all_in(53),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(54),
      Q => all_in(55),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(56),
      Q => all_in(57),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(58),
      Q => all_in(59),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(4),
      Q => all_in(5),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(60),
      Q => all_in(61),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(62),
      Q => all_in(63),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(64),
      Q => all_in(65),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(66),
      Q => all_in(67),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(68),
      Q => all_in(69),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(70),
      Q => all_in(71),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(72),
      Q => all_in(73),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(74),
      Q => all_in(75),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(76),
      Q => all_in(77),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(78),
      Q => all_in(79),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(6),
      Q => all_in(7),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(80),
      Q => all_in(81),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(82),
      Q => all_in(83),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(84),
      Q => all_in(85),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(86),
      Q => all_in(87),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(88),
      Q => all_in(89),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(90),
      Q => all_in(91),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(92),
      Q => all_in(93),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(94),
      Q => all_in(95),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(96),
      Q => all_in(97),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(98),
      Q => all_in(99),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(8),
      Q => all_in(9),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(100),
      Q => all_in(101),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(102),
      Q => all_in(103),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(104),
      Q => all_in(105),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(106),
      Q => all_in(107),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(108),
      Q => all_in(109),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(110),
      Q => all_in(111),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(112),
      Q => all_in(113),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(114),
      Q => all_in(115),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(116),
      Q => all_in(117),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(118),
      Q => all_in(119),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(10),
      Q => all_in(11),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(120),
      Q => all_in(121),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(122),
      Q => all_in(123),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(124),
      Q => all_in(125),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(126),
      Q => all_in(127),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(12),
      Q => all_in(13),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(14),
      Q => all_in(15),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(16),
      Q => all_in(17),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(18),
      Q => all_in(19),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(0),
      Q => all_in(0),
      R => '0'
    );
\probeDelay1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(10),
      Q => all_in(20),
      R => '0'
    );
\probeDelay1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(11),
      Q => all_in(22),
      R => '0'
    );
\probeDelay1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(12),
      Q => all_in(24),
      R => '0'
    );
\probeDelay1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(13),
      Q => all_in(26),
      R => '0'
    );
\probeDelay1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(14),
      Q => all_in(28),
      R => '0'
    );
\probeDelay1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(15),
      Q => all_in(30),
      R => '0'
    );
\probeDelay1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(0),
      Q => all_in(32),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(1),
      Q => all_in(34),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(2),
      Q => all_in(36),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(3),
      Q => all_in(38),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(1),
      Q => all_in(2),
      R => '0'
    );
\probeDelay1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(4),
      Q => all_in(40),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(5),
      Q => all_in(42),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(6),
      Q => all_in(44),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(7),
      Q => all_in(46),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(8),
      Q => all_in(48),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(9),
      Q => all_in(50),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(10),
      Q => all_in(52),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(11),
      Q => all_in(54),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(12),
      Q => all_in(56),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(13),
      Q => all_in(58),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(2),
      Q => all_in(4),
      R => '0'
    );
\probeDelay1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(14),
      Q => all_in(60),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(15),
      Q => all_in(62),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(16),
      Q => all_in(64),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(17),
      Q => all_in(66),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(18),
      Q => all_in(68),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(19),
      Q => all_in(70),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(20),
      Q => all_in(72),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(21),
      Q => all_in(74),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(22),
      Q => all_in(76),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(23),
      Q => all_in(78),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(3),
      Q => all_in(6),
      R => '0'
    );
\probeDelay1_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(24),
      Q => all_in(80),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(25),
      Q => all_in(82),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(26),
      Q => all_in(84),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(27),
      Q => all_in(86),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(28),
      Q => all_in(88),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(29),
      Q => all_in(90),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(30),
      Q => all_in(92),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(31),
      Q => all_in(94),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(32),
      Q => all_in(96),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(33),
      Q => all_in(98),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(4),
      Q => all_in(8),
      R => '0'
    );
\probeDelay1_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(34),
      Q => all_in(100),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(35),
      Q => all_in(102),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(36),
      Q => all_in(104),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(37),
      Q => all_in(106),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(38),
      Q => all_in(108),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(39),
      Q => all_in(110),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(40),
      Q => all_in(112),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(41),
      Q => all_in(114),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(42),
      Q => all_in(116),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(43),
      Q => all_in(118),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(5),
      Q => all_in(10),
      R => '0'
    );
\probeDelay1_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(44),
      Q => all_in(120),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(45),
      Q => all_in(122),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(46),
      Q => all_in(124),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe0(47),
      Q => all_in(126),
      R => \probeDelay1_reg[16]_0\
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(6),
      Q => all_in(12),
      R => '0'
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(7),
      Q => all_in(14),
      R => '0'
    );
\probeDelay1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(8),
      Q => all_in(16),
      R => '0'
    );
\probeDelay1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \probeDelay1_reg[15]_0\(9),
      Q => all_in(18),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC;
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1\ is
  signal all_dly1 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal all_dly2 : STD_LOGIC_VECTOR ( 0 to 0 );
begin
DUT: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_11
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_dly1(0) => all_dly1(0),
      all_dly2(0) => all_dly2(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_dly1(0),
      Q => all_dly2(0),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe2(0),
      Q => all_dly1(0),
      R => \probeDelay1_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1_13\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC;
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1_13\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1_13\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1_13\ is
  signal all_dly1 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal all_dly2 : STD_LOGIC_VECTOR ( 0 to 0 );
begin
DUT: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA_14
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_dly1(0) => all_dly1(0),
      all_dly2(0) => all_dly2(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_dly1(0),
      Q => all_dly2(0),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe1(0),
      Q => all_dly1(0),
      R => \probeDelay1_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized2\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC;
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized2\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized2\ is
  signal all_in : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
DUT: entity work.ila_full_aurora_ltlib_v1_0_0_all_typeA
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_in(15 downto 0) => all_in(15 downto 0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(0),
      Q => all_in(1),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(2),
      Q => all_in(3),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(4),
      Q => all_in(5),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(6),
      Q => all_in(7),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(8),
      Q => all_in(9),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(10),
      Q => all_in(11),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(12),
      Q => all_in(13),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(14),
      Q => all_in(15),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(0),
      Q => all_in(0),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(1),
      Q => all_in(2),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(2),
      Q => all_in(4),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(3),
      Q => all_in(6),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(4),
      Q => all_in(8),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(5),
      Q => all_in(10),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(6),
      Q => all_in(12),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe3(7),
      Q => all_in(14),
      R => \probeDelay1_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC;
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3\ is
  signal all_in : STD_LOGIC_VECTOR ( 63 downto 0 );
begin
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_in(63 downto 0) => all_in(63 downto 0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(0),
      Q => all_in(1),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(20),
      Q => all_in(21),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(22),
      Q => all_in(23),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(24),
      Q => all_in(25),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(26),
      Q => all_in(27),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(28),
      Q => all_in(29),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(30),
      Q => all_in(31),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(32),
      Q => all_in(33),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(34),
      Q => all_in(35),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(36),
      Q => all_in(37),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(38),
      Q => all_in(39),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(2),
      Q => all_in(3),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(40),
      Q => all_in(41),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(42),
      Q => all_in(43),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(44),
      Q => all_in(45),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(46),
      Q => all_in(47),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(48),
      Q => all_in(49),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(50),
      Q => all_in(51),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(52),
      Q => all_in(53),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(54),
      Q => all_in(55),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(56),
      Q => all_in(57),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(58),
      Q => all_in(59),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(4),
      Q => all_in(5),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(60),
      Q => all_in(61),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(62),
      Q => all_in(63),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(6),
      Q => all_in(7),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(8),
      Q => all_in(9),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(10),
      Q => all_in(11),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(12),
      Q => all_in(13),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(14),
      Q => all_in(15),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(16),
      Q => all_in(17),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(18),
      Q => all_in(19),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(0),
      Q => all_in(0),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(10),
      Q => all_in(20),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(11),
      Q => all_in(22),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(12),
      Q => all_in(24),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(13),
      Q => all_in(26),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(14),
      Q => all_in(28),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(15),
      Q => all_in(30),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(16),
      Q => all_in(32),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(17),
      Q => all_in(34),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(18),
      Q => all_in(36),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(19),
      Q => all_in(38),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(1),
      Q => all_in(2),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(20),
      Q => all_in(40),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(21),
      Q => all_in(42),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(22),
      Q => all_in(44),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(23),
      Q => all_in(46),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(24),
      Q => all_in(48),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(25),
      Q => all_in(50),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(26),
      Q => all_in(52),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(27),
      Q => all_in(54),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(28),
      Q => all_in(56),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(29),
      Q => all_in(58),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(2),
      Q => all_in(4),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(30),
      Q => all_in(60),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(31),
      Q => all_in(62),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(3),
      Q => all_in(6),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(4),
      Q => all_in(8),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(5),
      Q => all_in(10),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(6),
      Q => all_in(12),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(7),
      Q => all_in(14),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(8),
      Q => all_in(16),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe5(9),
      Q => all_in(18),
      R => \probeDelay1_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3_4\ is
  port (
    \out\ : out STD_LOGIC;
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC;
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3_4\ : entity is "ltlib_v1_0_0_allx_typeA";
end \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3_4\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3_4\ is
  signal all_in : STD_LOGIC_VECTOR ( 63 downto 0 );
begin
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized1_5\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      all_in(63 downto 0) => all_in(63 downto 0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
\i_use_input_reg_eq1.probeDelay2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(0),
      Q => all_in(1),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(20),
      Q => all_in(21),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(22),
      Q => all_in(23),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(24),
      Q => all_in(25),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(26),
      Q => all_in(27),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(28),
      Q => all_in(29),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(30),
      Q => all_in(31),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(32),
      Q => all_in(33),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(34),
      Q => all_in(35),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(36),
      Q => all_in(37),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(38),
      Q => all_in(39),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(2),
      Q => all_in(3),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(40),
      Q => all_in(41),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(42),
      Q => all_in(43),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(44),
      Q => all_in(45),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(46),
      Q => all_in(47),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(48),
      Q => all_in(49),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(50),
      Q => all_in(51),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(52),
      Q => all_in(53),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(54),
      Q => all_in(55),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(56),
      Q => all_in(57),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(58),
      Q => all_in(59),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(4),
      Q => all_in(5),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(60),
      Q => all_in(61),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(62),
      Q => all_in(63),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(6),
      Q => all_in(7),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(8),
      Q => all_in(9),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(10),
      Q => all_in(11),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(12),
      Q => all_in(13),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(14),
      Q => all_in(15),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(16),
      Q => all_in(17),
      R => '0'
    );
\i_use_input_reg_eq1.probeDelay2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => all_in(18),
      Q => all_in(19),
      R => '0'
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(0),
      Q => all_in(0),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(10),
      Q => all_in(20),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(11),
      Q => all_in(22),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(12),
      Q => all_in(24),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(13),
      Q => all_in(26),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(14),
      Q => all_in(28),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(15),
      Q => all_in(30),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(16),
      Q => all_in(32),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(17),
      Q => all_in(34),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(18),
      Q => all_in(36),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(19),
      Q => all_in(38),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(1),
      Q => all_in(2),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(20),
      Q => all_in(40),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(21),
      Q => all_in(42),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(22),
      Q => all_in(44),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(23),
      Q => all_in(46),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(24),
      Q => all_in(48),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(25),
      Q => all_in(50),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(26),
      Q => all_in(52),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(27),
      Q => all_in(54),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(28),
      Q => all_in(56),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(29),
      Q => all_in(58),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(2),
      Q => all_in(4),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(30),
      Q => all_in(60),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(31),
      Q => all_in(62),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(3),
      Q => all_in(6),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(4),
      Q => all_in(8),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(5),
      Q => all_in(10),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(6),
      Q => all_in(12),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(7),
      Q => all_in(14),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(8),
      Q => all_in(16),
      R => \probeDelay1_reg[0]_0\
    );
\probeDelay1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => probe4(9),
      Q => all_in(18),
      R => \probeDelay1_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay is
  port (
    \probeDelay1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    shift_en_reg : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    SRL_D_I : in STD_LOGIC;
    \probeDelay1_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay : entity is "ltlib_v1_0_0_allx_typeA_nodelay";
end ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay is
  signal \^probedelay1_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
  \probeDelay1_reg[9]_0\(9 downto 0) <= \^probedelay1_reg[9]_0\(9 downto 0);
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2\
     port map (
      E(0) => E(0),
      PROBES_I(19) => \^probedelay1_reg[9]_0\(9),
      PROBES_I(18) => Q(9),
      PROBES_I(17) => \^probedelay1_reg[9]_0\(8),
      PROBES_I(16) => Q(8),
      PROBES_I(15) => \^probedelay1_reg[9]_0\(7),
      PROBES_I(14) => Q(7),
      PROBES_I(13) => \^probedelay1_reg[9]_0\(6),
      PROBES_I(12) => Q(6),
      PROBES_I(11) => \^probedelay1_reg[9]_0\(5),
      PROBES_I(10) => Q(5),
      PROBES_I(9) => \^probedelay1_reg[9]_0\(4),
      PROBES_I(8) => Q(4),
      PROBES_I(7) => \^probedelay1_reg[9]_0\(3),
      PROBES_I(6) => Q(3),
      PROBES_I(5) => \^probedelay1_reg[9]_0\(2),
      PROBES_I(4) => Q(2),
      PROBES_I(3) => \^probedelay1_reg[9]_0\(1),
      PROBES_I(2) => Q(1),
      PROBES_I(1) => \^probedelay1_reg[9]_0\(0),
      PROBES_I(0) => Q(0),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => SRL_Q_O,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(0),
      Q => \^probedelay1_reg[9]_0\(0),
      R => '0'
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(1),
      Q => \^probedelay1_reg[9]_0\(1),
      R => '0'
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(2),
      Q => \^probedelay1_reg[9]_0\(2),
      R => '0'
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(3),
      Q => \^probedelay1_reg[9]_0\(3),
      R => '0'
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(4),
      Q => \^probedelay1_reg[9]_0\(4),
      R => '0'
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(5),
      Q => \^probedelay1_reg[9]_0\(5),
      R => '0'
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(6),
      Q => \^probedelay1_reg[9]_0\(6),
      R => '0'
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(7),
      Q => \^probedelay1_reg[9]_0\(7),
      R => '0'
    );
\probeDelay1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(8),
      Q => \^probedelay1_reg[9]_0\(8),
      R => '0'
    );
\probeDelay1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]_0\,
      CE => '1',
      D => Q(9),
      Q => \^probedelay1_reg[9]_0\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_50 is
  port (
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
    SRL_D_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_50 : entity is "ltlib_v1_0_0_allx_typeA_nodelay";
end ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_50;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_50 is
begin
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_51\
     port map (
      E(0) => E(0),
      PROBES_I(19 downto 0) => PROBES_I(19 downto 0),
      SRL_D_I => SRL_D_I,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg,
      shift_en_reg_0 => shift_en_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_58 is
  port (
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    \iwcnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    SRL_D_I : in STD_LOGIC;
    \probeDelay1_reg[9]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_58 : entity is "ltlib_v1_0_0_allx_typeA_nodelay";
end ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_58;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_58 is
  signal all_dly2 : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
DUT: entity work.\ila_full_aurora_ltlib_v1_0_0_all_typeA__parameterized2_59\
     port map (
      DOUT_O => DOUT_O,
      PROBES_I(19) => all_dly2(9),
      PROBES_I(18) => Q(9),
      PROBES_I(17) => all_dly2(8),
      PROBES_I(16) => Q(8),
      PROBES_I(15) => all_dly2(7),
      PROBES_I(14) => Q(7),
      PROBES_I(13) => all_dly2(6),
      PROBES_I(12) => Q(6),
      PROBES_I(11) => all_dly2(5),
      PROBES_I(10) => Q(5),
      PROBES_I(9) => all_dly2(4),
      PROBES_I(8) => Q(4),
      PROBES_I(7) => all_dly2(3),
      PROBES_I(6) => Q(3),
      PROBES_I(5) => all_dly2(2),
      PROBES_I(4) => Q(2),
      PROBES_I(3) => all_dly2(1),
      PROBES_I(2) => Q(1),
      PROBES_I(1) => all_dly2(0),
      PROBES_I(0) => Q(0),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => SRL_Q_O,
      \iwcnt_reg[0]\(0) => \iwcnt_reg[0]\(0),
      s_dclk_o => s_dclk_o
    );
\probeDelay1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(0),
      Q => all_dly2(0),
      R => '0'
    );
\probeDelay1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(1),
      Q => all_dly2(1),
      R => '0'
    );
\probeDelay1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(2),
      Q => all_dly2(2),
      R => '0'
    );
\probeDelay1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(3),
      Q => all_dly2(3),
      R => '0'
    );
\probeDelay1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(4),
      Q => all_dly2(4),
      R => '0'
    );
\probeDelay1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(5),
      Q => all_dly2(5),
      R => '0'
    );
\probeDelay1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(6),
      Q => all_dly2(6),
      R => '0'
    );
\probeDelay1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(7),
      Q => all_dly2(7),
      R => '0'
    );
\probeDelay1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(8),
      Q => all_dly2(8),
      R => '0'
    );
\probeDelay1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]_0\,
      CE => '1',
      D => Q(9),
      Q => all_dly2(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_top is
  port (
    D : out STD_LOGIC_VECTOR ( 138 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_top : entity is "blk_mem_gen_v8_4_4_blk_mem_gen_top";
end ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_top;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_top is
begin
\valid.cstr\: entity work.ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_generic_cstr
     port map (
      D(138 downto 0) => D(138 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_match is
  port (
    shift_en_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \yes_output_reg.dout_reg_reg_0\ : out STD_LOGIC;
    tc_config_cs_serial_output : in STD_LOGIC;
    \parallel_dout_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_match : entity is "ltlib_v1_0_0_match";
end ila_full_aurora_ltlib_v1_0_0_match;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_match is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
\TRIGGER_EQ[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \yes_output_reg.dout_reg\,
      I1 => Q(1),
      O => \yes_output_reg.dout_reg_reg_0\
    );
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_allx_typeA
     port map (
      D(5 downto 0) => D(5 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      \out\ => match_dout,
      \parallel_dout_reg[15]\(0) => \parallel_dout_reg[15]\(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg(0) => shift_en_reg(0),
      tc_config_cs_serial_output => tc_config_cs_serial_output
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized0\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \probeDelay1_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \out\ : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 47 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized0\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized0\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized0\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe0(47 downto 0) => probe0(47 downto 0),
      \probeDelay1_reg[15]_0\(15 downto 0) => \probeDelay1_reg[15]\(15 downto 0),
      \probeDelay1_reg[16]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized1\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized1\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized1\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized1\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1_13\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe1(0) => probe1(0),
      \probeDelay1_reg[0]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized1_0\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized1_0\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized1_0\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized1_0\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized1\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe2(0) => probe2(0),
      \probeDelay1_reg[0]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized2\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized2\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized2\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized2\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized2\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe3(7 downto 0) => probe3(7 downto 0),
      \probeDelay1_reg[0]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized3\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized3\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized3\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized3\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3_4\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe4(31 downto 0) => probe4(31 downto 0),
      \probeDelay1_reg[0]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ila_full_aurora_ltlib_v1_0_0_match__parameterized3_1\ is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 0 to 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \ila_full_aurora_ltlib_v1_0_0_match__parameterized3_1\ : entity is "ltlib_v1_0_0_match";
end \ila_full_aurora_ltlib_v1_0_0_match__parameterized3_1\;

architecture STRUCTURE of \ila_full_aurora_ltlib_v1_0_0_match__parameterized3_1\ is
  signal match_dout : STD_LOGIC;
  signal \yes_output_reg.dout_reg\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \yes_output_reg.dout_reg\ : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \yes_output_reg.dout_reg_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \yes_output_reg.dout_reg_reg\ : label is "yes";
begin
  D(0) <= \yes_output_reg.dout_reg\;
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.\ila_full_aurora_ltlib_v1_0_0_allx_typeA__parameterized3\
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => match_dout,
      probe5(31 downto 0) => probe5(31 downto 0),
      \probeDelay1_reg[0]_0\ => \out\,
      s_dclk_o => s_dclk_o
    );
\yes_output_reg.dout_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => match_dout,
      Q => \yes_output_reg.dout_reg\,
      R => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_match_nodelay is
  port (
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
    SRL_D_I : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_match_nodelay : entity is "ltlib_v1_0_0_match_nodelay";
end ila_full_aurora_ltlib_v1_0_0_match_nodelay;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_match_nodelay is
begin
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_50
     port map (
      E(0) => E(0),
      PROBES_I(19 downto 0) => PROBES_I(19 downto 0),
      SRL_D_I => SRL_D_I,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg,
      shift_en_reg_0 => shift_en_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_match_nodelay_49 is
  port (
    \probeDelay1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    shift_en_reg : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    SRL_D_I : in STD_LOGIC;
    \probeDelay1_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_match_nodelay_49 : entity is "ltlib_v1_0_0_match_nodelay";
end ila_full_aurora_ltlib_v1_0_0_match_nodelay_49;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_match_nodelay_49 is
begin
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay
     port map (
      E(0) => E(0),
      Q(9 downto 0) => Q(9 downto 0),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => SRL_Q_O,
      \probeDelay1_reg[0]_0\ => \probeDelay1_reg[0]\,
      \probeDelay1_reg[9]_0\(9 downto 0) => \probeDelay1_reg[9]\(9 downto 0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ltlib_v1_0_0_match_nodelay_57 is
  port (
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    \iwcnt_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    SRL_D_I : in STD_LOGIC;
    \probeDelay1_reg[9]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ltlib_v1_0_0_match_nodelay_57 : entity is "ltlib_v1_0_0_match_nodelay";
end ila_full_aurora_ltlib_v1_0_0_match_nodelay_57;

architecture STRUCTURE of ila_full_aurora_ltlib_v1_0_0_match_nodelay_57 is
begin
\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst\: entity work.ila_full_aurora_ltlib_v1_0_0_allx_typeA_nodelay_58
     port map (
      DOUT_O => DOUT_O,
      Q(9 downto 0) => Q(9 downto 0),
      SRL_D_I => SRL_D_I,
      SRL_Q_O => SRL_Q_O,
      \iwcnt_reg[0]\(0) => \iwcnt_reg[0]\(0),
      \probeDelay1_reg[9]_0\ => \probeDelay1_reg[9]\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4_synth is
  port (
    D : out STD_LOGIC_VECTOR ( 138 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end ila_full_aurora_blk_mem_gen_v8_4_4_synth;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.ila_full_aurora_blk_mem_gen_v8_4_4_blk_mem_gen_top
     port map (
      D(138 downto 0) => D(138 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_cap_sample_counter is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \capture_qual_ctrl_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    u_scnt_cmp_q_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 9 downto 0 );
    DOUT_O : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    u_scnt_cmp_q_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_data_1 : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_dclk_o : in STD_LOGIC;
    cmp_reset : in STD_LOGIC;
    scnt_cmp_temp : in STD_LOGIC;
    \probeDelay1_reg[9]\ : in STD_LOGIC;
    u_scnt_cmp_q_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    basic_trigger : in STD_LOGIC;
    u_scnt_cmp_q_3 : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_cap_sample_counter : entity is "ila_v6_2_10_ila_cap_sample_counter";
end ila_full_aurora_ila_v6_2_10_ila_cap_sample_counter;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_cap_sample_counter is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal U_SCRST_n_3 : STD_LOGIC;
  signal \^capture_qual_ctrl_reg[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1_0 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal \iscnt[9]_i_3_n_0\ : STD_LOGIC;
  signal \p_0_in__10\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal scnt : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal scnt_cmp_ce : STD_LOGIC;
  signal \^u_scnt_cmp_q_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i_intcap.icap_addr[0]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \iscnt[0]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \iscnt[1]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \iscnt[2]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \iscnt[3]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \iscnt[4]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \iscnt[6]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \iscnt[7]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \iscnt[8]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \iscnt[9]_i_2\ : label is "soft_lutpair0";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_scnt_cmp_q : label is "PRIMITIVE";
begin
  E(0) <= \^e\(0);
  \capture_qual_ctrl_reg[0]\(1 downto 0) <= \^capture_qual_ctrl_reg[0]\(1 downto 0);
  u_scnt_cmp_q_0(0) <= \^u_scnt_cmp_q_0\(0);
U_SCE: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut4_54
     port map (
      A(3 downto 2) => \^capture_qual_ctrl_reg[0]\(1 downto 0),
      A(1 downto 0) => A(1 downto 0),
      E(0) => \^e\(0),
      cfg_data_0 => cfg_data_0,
      cfg_data_1 => cfg_data_1,
      \iscnt_reg[9]\(0) => u_scnt_cmp_q_1(0),
      s_dclk_o => s_dclk_o
    );
U_SCMPCE: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut5_55
     port map (
      A(4) => \^u_scnt_cmp_q_0\(0),
      A(3 downto 2) => \^capture_qual_ctrl_reg[0]\(1 downto 0),
      A(1 downto 0) => A(1 downto 0),
      cfg_data_0 => cfg_data_0,
      cfg_data_1_0 => cfg_data_1_0,
      s_dclk_o => s_dclk_o,
      scnt_cmp_ce => scnt_cmp_ce,
      u_scnt_cmp_q(0) => u_scnt_cmp_q_1(0)
    );
U_SCRST: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut6_56
     port map (
      A(2 downto 0) => A(2 downto 0),
      SR(0) => U_SCRST_n_3,
      SRL_D_I => cfg_data_2,
      basic_trigger => basic_trigger,
      \capture_qual_ctrl_reg[0]\(1 downto 0) => \^capture_qual_ctrl_reg[0]\(1 downto 0),
      cfg_data_1_0 => cfg_data_1_0,
      \iscnt_reg[9]\(0) => u_scnt_cmp_q_1(0),
      \iscnt_reg[9]_0\(0) => \^u_scnt_cmp_q_0\(0),
      s_dclk_o => s_dclk_o,
      u_scnt_cmp_q(1 downto 0) => u_scnt_cmp_q_2(1 downto 0),
      u_scnt_cmp_q_0 => u_scnt_cmp_q_3
    );
\i_intcap.icap_addr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(0),
      I1 => \out\(0),
      I2 => Q(0),
      O => D(0)
    );
\i_intcap.icap_addr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(1),
      I1 => \out\(1),
      I2 => Q(1),
      O => D(1)
    );
\i_intcap.icap_addr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(2),
      I1 => \out\(2),
      I2 => Q(2),
      O => D(2)
    );
\i_intcap.icap_addr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(3),
      I1 => \out\(3),
      I2 => Q(3),
      O => D(3)
    );
\i_intcap.icap_addr[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(4),
      I1 => \out\(4),
      I2 => Q(4),
      O => D(4)
    );
\i_intcap.icap_addr[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(5),
      I1 => \out\(5),
      I2 => Q(5),
      O => D(5)
    );
\i_intcap.icap_addr[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(6),
      I1 => \out\(6),
      I2 => Q(6),
      O => D(6)
    );
\i_intcap.icap_addr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(7),
      I1 => \out\(7),
      I2 => Q(7),
      O => D(7)
    );
\i_intcap.icap_addr[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(8),
      I1 => \out\(8),
      I2 => Q(8),
      O => D(8)
    );
\i_intcap.icap_addr[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => scnt(9),
      I1 => \out\(9),
      I2 => Q(9),
      O => D(9)
    );
\iscnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => scnt(0),
      O => \p_0_in__10\(0)
    );
\iscnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => scnt(0),
      I1 => scnt(1),
      O => \p_0_in__10\(1)
    );
\iscnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => scnt(0),
      I1 => scnt(1),
      I2 => scnt(2),
      O => \p_0_in__10\(2)
    );
\iscnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => scnt(1),
      I1 => scnt(0),
      I2 => scnt(2),
      I3 => scnt(3),
      O => \p_0_in__10\(3)
    );
\iscnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => scnt(2),
      I1 => scnt(0),
      I2 => scnt(1),
      I3 => scnt(3),
      I4 => scnt(4),
      O => \p_0_in__10\(4)
    );
\iscnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => scnt(3),
      I1 => scnt(1),
      I2 => scnt(0),
      I3 => scnt(2),
      I4 => scnt(4),
      I5 => scnt(5),
      O => \p_0_in__10\(5)
    );
\iscnt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \iscnt[9]_i_3_n_0\,
      I1 => scnt(6),
      O => \p_0_in__10\(6)
    );
\iscnt[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \iscnt[9]_i_3_n_0\,
      I1 => scnt(6),
      I2 => scnt(7),
      O => \p_0_in__10\(7)
    );
\iscnt[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => scnt(6),
      I1 => \iscnt[9]_i_3_n_0\,
      I2 => scnt(7),
      I3 => scnt(8),
      O => \p_0_in__10\(8)
    );
\iscnt[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => scnt(7),
      I1 => \iscnt[9]_i_3_n_0\,
      I2 => scnt(6),
      I3 => scnt(8),
      I4 => scnt(9),
      O => \p_0_in__10\(9)
    );
\iscnt[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => scnt(5),
      I1 => scnt(3),
      I2 => scnt(1),
      I3 => scnt(0),
      I4 => scnt(2),
      I5 => scnt(4),
      O => \iscnt[9]_i_3_n_0\
    );
\iscnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(0),
      Q => scnt(0),
      R => U_SCRST_n_3
    );
\iscnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(1),
      Q => scnt(1),
      R => U_SCRST_n_3
    );
\iscnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(2),
      Q => scnt(2),
      R => U_SCRST_n_3
    );
\iscnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(3),
      Q => scnt(3),
      R => U_SCRST_n_3
    );
\iscnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(4),
      Q => scnt(4),
      R => U_SCRST_n_3
    );
\iscnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(5),
      Q => scnt(5),
      R => U_SCRST_n_3
    );
\iscnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(6),
      Q => scnt(6),
      R => U_SCRST_n_3
    );
\iscnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(7),
      Q => scnt(7),
      R => U_SCRST_n_3
    );
\iscnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(8),
      Q => scnt(8),
      R => U_SCRST_n_3
    );
\iscnt_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[9]\,
      CE => \^e\(0),
      D => \p_0_in__10\(9),
      Q => scnt(9),
      R => U_SCRST_n_3
    );
u_scnt_cmp: entity work.ila_full_aurora_ltlib_v1_0_0_match_nodelay_57
     port map (
      DOUT_O => DOUT_O,
      Q(9 downto 0) => scnt(9 downto 0),
      SRL_D_I => cfg_data_2,
      SRL_Q_O => SRL_Q_O,
      \iwcnt_reg[0]\(0) => u_scnt_cmp_q_1(0),
      \probeDelay1_reg[9]\ => \probeDelay1_reg[9]\,
      s_dclk_o => s_dclk_o
    );
u_scnt_cmp_q: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => \probeDelay1_reg[9]\,
      CE => scnt_cmp_ce,
      D => scnt_cmp_temp,
      Q => \^u_scnt_cmp_q_0\(0),
      R => cmp_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_cap_window_counter is
  port (
    u_wcnt_lcmp_q_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    wcnt_hcmp : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    shift_en_reg_1 : out STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    SRL_Q_O : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_dclk_o : in STD_LOGIC;
    cmp_reset : in STD_LOGIC;
    wcnt_lcmp_temp : in STD_LOGIC;
    \probeDelay1_reg[0]\ : in STD_LOGIC;
    wcnt_hcmp_temp : in STD_LOGIC;
    \iwcnt_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_cap_window_counter : entity is "ila_v6_2_10_ila_cap_window_counter";
end ila_full_aurora_ila_v6_2_10_ila_cap_window_counter;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_cap_window_counter is
  signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal cfg_data_3 : STD_LOGIC;
  signal \iwcnt[9]_i_2_n_0\ : STD_LOGIC;
  signal \p_0_in__11\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \^u_wcnt_lcmp_q_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wcnt_ce : STD_LOGIC;
  signal \^wcnt_hcmp\ : STD_LOGIC;
  signal wcnt_hcmp_ce : STD_LOGIC;
  signal wcnt_lcmp_ce : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \iwcnt[1]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \iwcnt[2]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \iwcnt[3]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \iwcnt[4]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \iwcnt[6]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \iwcnt[7]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \iwcnt[8]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \iwcnt[9]_i_1\ : label is "soft_lutpair5";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of u_wcnt_hcmp_q : label is "PRIMITIVE";
  attribute BOX_TYPE of u_wcnt_lcmp_q : label is "PRIMITIVE";
begin
  Q(9 downto 0) <= \^q\(9 downto 0);
  u_wcnt_lcmp_q_0(0) <= \^u_wcnt_lcmp_q_0\(0);
  wcnt_hcmp <= \^wcnt_hcmp\;
U_WCE: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut4
     port map (
      A(3 downto 0) => A(3 downto 0),
      E(0) => wcnt_ce,
      SRL_Q_O => SRL_Q_O,
      cfg_data_0 => cfg_data_0,
      \iwcnt_reg[0]\(0) => E(0),
      s_dclk_o => s_dclk_o
    );
U_WHCMPCE: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut5
     port map (
      A(4) => \^wcnt_hcmp\,
      A(3 downto 0) => A(3 downto 0),
      E(0) => E(0),
      SRL_D_I => cfg_data_3,
      SRL_Q_O => cfg_data_2,
      s_dclk_o => s_dclk_o,
      wcnt_hcmp_ce => wcnt_hcmp_ce
    );
U_WLCMPCE: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut5_48
     port map (
      A(4) => \^u_wcnt_lcmp_q_0\(0),
      A(3 downto 0) => A(3 downto 0),
      E(0) => E(0),
      SRL_D_I => cfg_data_1,
      cfg_data_0 => cfg_data_0,
      s_dclk_o => s_dclk_o,
      wcnt_lcmp_ce => wcnt_lcmp_ce
    );
\iwcnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \p_0_in__11\(0)
    );
\iwcnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \p_0_in__11\(1)
    );
\iwcnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      O => \p_0_in__11\(2)
    );
\iwcnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \p_0_in__11\(3)
    );
\iwcnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \p_0_in__11\(4)
    );
\iwcnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \p_0_in__11\(5)
    );
\iwcnt[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \iwcnt[9]_i_2_n_0\,
      I1 => \^q\(6),
      O => \p_0_in__11\(6)
    );
\iwcnt[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \iwcnt[9]_i_2_n_0\,
      I1 => \^q\(6),
      I2 => \^q\(7),
      O => \p_0_in__11\(7)
    );
\iwcnt[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(6),
      I1 => \iwcnt[9]_i_2_n_0\,
      I2 => \^q\(7),
      I3 => \^q\(8),
      O => \p_0_in__11\(8)
    );
\iwcnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(7),
      I1 => \iwcnt[9]_i_2_n_0\,
      I2 => \^q\(6),
      I3 => \^q\(8),
      I4 => \^q\(9),
      O => \p_0_in__11\(9)
    );
\iwcnt[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(4),
      O => \iwcnt[9]_i_2_n_0\
    );
\iwcnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(0),
      Q => \^q\(0),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(1),
      Q => \^q\(1),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(2),
      Q => \^q\(2),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(3),
      Q => \^q\(3),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(4),
      Q => \^q\(4),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(5),
      Q => \^q\(5),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(6),
      Q => \^q\(6),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(7),
      Q => \^q\(7),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(8),
      Q => \^q\(8),
      R => \iwcnt_reg[9]_0\(0)
    );
\iwcnt_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_ce,
      D => \p_0_in__11\(9),
      Q => \^q\(9),
      R => \iwcnt_reg[9]_0\(0)
    );
u_wcnt_hcmp: entity work.ila_full_aurora_ltlib_v1_0_0_match_nodelay
     port map (
      E(0) => E(0),
      PROBES_I(19) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(9),
      PROBES_I(18) => \^q\(9),
      PROBES_I(17) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(8),
      PROBES_I(16) => \^q\(8),
      PROBES_I(15) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(7),
      PROBES_I(14) => \^q\(7),
      PROBES_I(13) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(6),
      PROBES_I(12) => \^q\(6),
      PROBES_I(11) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(5),
      PROBES_I(10) => \^q\(5),
      PROBES_I(9) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(4),
      PROBES_I(8) => \^q\(4),
      PROBES_I(7) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(3),
      PROBES_I(6) => \^q\(3),
      PROBES_I(5) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(2),
      PROBES_I(4) => \^q\(2),
      PROBES_I(3) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(1),
      PROBES_I(2) => \^q\(1),
      PROBES_I(1) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(0),
      PROBES_I(0) => \^q\(0),
      SRL_D_I => cfg_data_3,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg_0,
      shift_en_reg_0 => shift_en_reg_1
    );
u_wcnt_hcmp_q: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_hcmp_ce,
      D => wcnt_hcmp_temp,
      Q => \^wcnt_hcmp\,
      R => cmp_reset
    );
u_wcnt_lcmp: entity work.ila_full_aurora_ltlib_v1_0_0_match_nodelay_49
     port map (
      E(0) => E(0),
      Q(9 downto 0) => \^q\(9 downto 0),
      SRL_D_I => cfg_data_1,
      SRL_Q_O => cfg_data_2,
      \probeDelay1_reg[0]\ => \probeDelay1_reg[0]\,
      \probeDelay1_reg[9]\(9 downto 0) => \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2\(9 downto 0),
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg
    );
u_wcnt_lcmp_q: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => wcnt_lcmp_ce,
      D => wcnt_lcmp_temp,
      Q => \^u_wcnt_lcmp_q_0\(0),
      R => cmp_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_trig_match is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D : out STD_LOGIC_VECTOR ( 5 downto 0 );
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 5 downto 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_dclk_o : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \probeDelay1_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    probe0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_trig_match : entity is "ila_v6_2_10_ila_trig_match";
end ila_full_aurora_ila_v6_2_10_ila_trig_match;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_trig_match is
begin
\N_DDR_MODE.G_NMU[0].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized0\
     port map (
      D(0) => D(0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(0),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(0),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(0),
      \out\ => \out\,
      probe0(47 downto 0) => probe0(47 downto 0),
      \probeDelay1_reg[15]\(15 downto 0) => \probeDelay1_reg[15]\(15 downto 0),
      s_dclk_o => s_dclk_o
    );
\N_DDR_MODE.G_NMU[1].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized1\
     port map (
      D(0) => D(1),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(1),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(1),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(1),
      \out\ => \out\,
      probe1(0) => probe1(0),
      s_dclk_o => s_dclk_o
    );
\N_DDR_MODE.G_NMU[2].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized1_0\
     port map (
      D(0) => D(2),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(2),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(2),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(2),
      \out\ => \out\,
      probe2(0) => probe2(0),
      s_dclk_o => s_dclk_o
    );
\N_DDR_MODE.G_NMU[3].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized2\
     port map (
      D(0) => D(3),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(3),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(3),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(3),
      \out\ => \out\,
      probe3(7 downto 0) => probe3(7 downto 0),
      s_dclk_o => s_dclk_o
    );
\N_DDR_MODE.G_NMU[4].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized3\
     port map (
      D(0) => D(4),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(4),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(4),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(4),
      \out\ => \out\,
      probe4(31 downto 0) => probe4(31 downto 0),
      s_dclk_o => s_dclk_o
    );
\N_DDR_MODE.G_NMU[5].U_M\: entity work.\ila_full_aurora_ltlib_v1_0_0_match__parameterized3_1\
     port map (
      D(0) => D(5),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(0) => mu_config_cs_serial_input(5),
      mu_config_cs_serial_output(0) => mu_config_cs_serial_output(5),
      mu_config_cs_shift_en(0) => mu_config_cs_shift_en(5),
      \out\ => \out\,
      probe5(31 downto 0) => probe5(31 downto 0),
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_blk_mem_gen_v8_4_4 is
  port (
    D : out STD_LOGIC_VECTOR ( 138 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
end ila_full_aurora_blk_mem_gen_v8_4_4;

architecture STRUCTURE of ila_full_aurora_blk_mem_gen_v8_4_4 is
begin
inst_blk_mem_gen: entity work.ila_full_aurora_blk_mem_gen_v8_4_4_synth
     port map (
      D(138 downto 0) => D(138 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_cap_addrgen is
  port (
    A : out STD_LOGIC_VECTOR ( 2 downto 0 );
    u_scnt_cmp_q : out STD_LOGIC_VECTOR ( 0 to 0 );
    wcnt_hcmp : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CAP_WR_EN_O_reg_0 : out STD_LOGIC;
    DOUT_O : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    SRL_Q_O : out STD_LOGIC;
    \captured_samples_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    u_wcnt_lcmp_q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_dclk_o : in STD_LOGIC;
    scnt_cmp_temp : in STD_LOGIC;
    \probeDelay1_reg[0]\ : in STD_LOGIC;
    wcnt_lcmp_temp : in STD_LOGIC;
    wcnt_hcmp_temp : in STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    u_scnt_cmp_q_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    basic_trigger : in STD_LOGIC;
    u_scnt_cmp_q_1 : in STD_LOGIC;
    \captured_samples_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_cap_addrgen : entity is "ila_v6_2_10_ila_cap_addrgen";
end ila_full_aurora_ila_v6_2_10_ila_cap_addrgen;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_cap_addrgen is
  signal \^a\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cap_addr_next : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal cfg_data_vec : STD_LOGIC_VECTOR ( 16 downto 1 );
  signal cfg_data_vec_sync1 : STD_LOGIC_VECTOR ( 32 downto 0 );
  attribute async_reg : string;
  attribute async_reg of cfg_data_vec_sync1 : signal is "true";
  signal cfg_data_vec_sync2 : STD_LOGIC_VECTOR ( 32 downto 0 );
  attribute async_reg of cfg_data_vec_sync2 : signal is "true";
  signal cmp_reset : STD_LOGIC;
  signal icap_addr : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of icap_addr : signal is std.standard.true;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of icap_addr : signal is "yes";
  attribute async_reg of icap_addr : signal is "true";
  signal icap_wr_en : STD_LOGIC;
  attribute DONT_TOUCH of icap_wr_en : signal is std.standard.true;
  attribute RTL_KEEP of icap_wr_en : signal is "yes";
  attribute async_reg of icap_wr_en : signal is "true";
  signal n_0_0 : STD_LOGIC;
  signal n_0_1 : STD_LOGIC;
  signal n_0_10 : STD_LOGIC;
  signal n_0_11 : STD_LOGIC;
  signal n_0_12 : STD_LOGIC;
  signal n_0_13 : STD_LOGIC;
  signal n_0_14 : STD_LOGIC;
  signal n_0_15 : STD_LOGIC;
  signal n_0_2 : STD_LOGIC;
  signal n_0_3 : STD_LOGIC;
  signal n_0_4 : STD_LOGIC;
  signal n_0_5 : STD_LOGIC;
  signal n_0_6 : STD_LOGIC;
  signal n_0_7 : STD_LOGIC;
  signal n_0_8 : STD_LOGIC;
  signal n_0_9 : STD_LOGIC;
  signal scnt_ce : STD_LOGIC;
  signal \^u_scnt_cmp_q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wcnt : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of CAP_WR_EN_O_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of CAP_WR_EN_O_reg : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[12]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[13]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[14]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[15]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[16]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[17]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[18]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[18]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[19]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[19]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[20]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[20]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[21]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[21]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[22]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[22]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[23]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[23]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[24]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[24]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[25]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[25]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[26]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[26]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[27]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[27]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[28]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[28]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[29]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[29]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[30]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[30]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[31]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[31]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[32]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[32]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[12]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[13]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[14]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[15]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[16]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[17]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[18]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[18]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[19]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[19]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[20]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[20]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[21]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[21]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[22]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[22]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[23]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[23]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[24]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[24]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[25]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[25]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[26]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[26]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[27]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[27]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[28]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[28]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[29]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[29]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[30]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[30]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[31]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[31]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[32]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[32]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \cfg_data_vec_sync2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \cfg_data_vec_sync2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[0]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[1]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[2]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[3]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[4]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[5]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[6]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[7]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[8]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.CAP_ADDR_O_reg[9]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.CAP_ADDR_O_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[0]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[0]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[1]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[1]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[2]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[2]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[3]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[3]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[4]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[4]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[5]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[5]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[6]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[6]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[7]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[7]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[8]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[8]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \i_intcap.icap_addr_reg[9]\ : label is std.standard.true;
  attribute DONT_TOUCH of \i_intcap.icap_addr_reg[9]\ : label is std.standard.true;
  attribute KEEP of \i_intcap.icap_addr_reg[9]\ : label is "yes";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of \i_o_to_64k.u_selx\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \i_o_to_64k.u_selx\ : label is "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.u_selx ";
  attribute ASYNC_REG_boolean of icap_wr_en_reg : label is std.standard.true;
  attribute DONT_TOUCH of icap_wr_en_reg : label is std.standard.true;
  attribute KEEP of icap_wr_en_reg : label is "yes";
begin
  A(2 downto 0) <= \^a\(2 downto 0);
  u_scnt_cmp_q(0) <= \^u_scnt_cmp_q\(0);
CAP_WR_EN_O_reg: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_wr_en,
      Q => CAP_WR_EN_O_reg_0,
      R => Q(0)
    );
U_CMPRESET: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut6
     port map (
      A(4 downto 2) => \^a\(2 downto 0),
      A(1 downto 0) => u_wcnt_lcmp_q(1 downto 0),
      E(0) => E(0),
      cfg_data_0 => cfg_data_0,
      cfg_data_1 => cfg_data_1,
      cmp_reset => cmp_reset,
      s_dclk_o => s_dclk_o,
      u_wcnt_hcmp_q(0) => \^u_scnt_cmp_q\(0)
    );
\captured_samples_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(0),
      Q => \captured_samples_reg[9]_0\(0),
      R => '0'
    );
\captured_samples_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(1),
      Q => \captured_samples_reg[9]_0\(1),
      R => '0'
    );
\captured_samples_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(2),
      Q => \captured_samples_reg[9]_0\(2),
      R => '0'
    );
\captured_samples_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(3),
      Q => \captured_samples_reg[9]_0\(3),
      R => '0'
    );
\captured_samples_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(4),
      Q => \captured_samples_reg[9]_0\(4),
      R => '0'
    );
\captured_samples_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(5),
      Q => \captured_samples_reg[9]_0\(5),
      R => '0'
    );
\captured_samples_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(6),
      Q => \captured_samples_reg[9]_0\(6),
      R => '0'
    );
\captured_samples_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(7),
      Q => \captured_samples_reg[9]_0\(7),
      R => '0'
    );
\captured_samples_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(8),
      Q => \captured_samples_reg[9]_0\(8),
      R => '0'
    );
\captured_samples_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => \captured_samples_reg[0]_0\(0),
      D => wcnt(9),
      Q => \captured_samples_reg[9]_0\(9),
      R => '0'
    );
\cfg_data_vec_sync1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => in0(0),
      Q => cfg_data_vec_sync1(0),
      R => '0'
    );
\cfg_data_vec_sync1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(10),
      Q => cfg_data_vec_sync1(10),
      R => '0'
    );
\cfg_data_vec_sync1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(11),
      Q => cfg_data_vec_sync1(11),
      R => '0'
    );
\cfg_data_vec_sync1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(12),
      Q => cfg_data_vec_sync1(12),
      R => '0'
    );
\cfg_data_vec_sync1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(13),
      Q => cfg_data_vec_sync1(13),
      R => '0'
    );
\cfg_data_vec_sync1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(14),
      Q => cfg_data_vec_sync1(14),
      R => '0'
    );
\cfg_data_vec_sync1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(15),
      Q => cfg_data_vec_sync1(15),
      R => '0'
    );
\cfg_data_vec_sync1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(16),
      Q => cfg_data_vec_sync1(16),
      R => '0'
    );
\cfg_data_vec_sync1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_15,
      Q => cfg_data_vec_sync1(17),
      R => '0'
    );
\cfg_data_vec_sync1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_14,
      Q => cfg_data_vec_sync1(18),
      R => '0'
    );
\cfg_data_vec_sync1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_13,
      Q => cfg_data_vec_sync1(19),
      R => '0'
    );
\cfg_data_vec_sync1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(1),
      Q => cfg_data_vec_sync1(1),
      R => '0'
    );
\cfg_data_vec_sync1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_12,
      Q => cfg_data_vec_sync1(20),
      R => '0'
    );
\cfg_data_vec_sync1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_11,
      Q => cfg_data_vec_sync1(21),
      R => '0'
    );
\cfg_data_vec_sync1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_10,
      Q => cfg_data_vec_sync1(22),
      R => '0'
    );
\cfg_data_vec_sync1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_9,
      Q => cfg_data_vec_sync1(23),
      R => '0'
    );
\cfg_data_vec_sync1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_8,
      Q => cfg_data_vec_sync1(24),
      R => '0'
    );
\cfg_data_vec_sync1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_7,
      Q => cfg_data_vec_sync1(25),
      R => '0'
    );
\cfg_data_vec_sync1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_6,
      Q => cfg_data_vec_sync1(26),
      R => '0'
    );
\cfg_data_vec_sync1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_5,
      Q => cfg_data_vec_sync1(27),
      R => '0'
    );
\cfg_data_vec_sync1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_4,
      Q => cfg_data_vec_sync1(28),
      R => '0'
    );
\cfg_data_vec_sync1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_3,
      Q => cfg_data_vec_sync1(29),
      R => '0'
    );
\cfg_data_vec_sync1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(2),
      Q => cfg_data_vec_sync1(2),
      R => '0'
    );
\cfg_data_vec_sync1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_2,
      Q => cfg_data_vec_sync1(30),
      R => '0'
    );
\cfg_data_vec_sync1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_1,
      Q => cfg_data_vec_sync1(31),
      R => '0'
    );
\cfg_data_vec_sync1_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => n_0_0,
      Q => cfg_data_vec_sync1(32),
      R => '0'
    );
\cfg_data_vec_sync1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(3),
      Q => cfg_data_vec_sync1(3),
      R => '0'
    );
\cfg_data_vec_sync1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(4),
      Q => cfg_data_vec_sync1(4),
      R => '0'
    );
\cfg_data_vec_sync1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(5),
      Q => cfg_data_vec_sync1(5),
      R => '0'
    );
\cfg_data_vec_sync1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(6),
      Q => cfg_data_vec_sync1(6),
      R => '0'
    );
\cfg_data_vec_sync1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(7),
      Q => cfg_data_vec_sync1(7),
      R => '0'
    );
\cfg_data_vec_sync1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(8),
      Q => cfg_data_vec_sync1(8),
      R => '0'
    );
\cfg_data_vec_sync1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec(9),
      Q => cfg_data_vec_sync1(9),
      R => '0'
    );
\cfg_data_vec_sync2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(0),
      Q => cfg_data_vec_sync2(0),
      R => '0'
    );
\cfg_data_vec_sync2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(10),
      Q => cfg_data_vec_sync2(10),
      R => '0'
    );
\cfg_data_vec_sync2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(11),
      Q => cfg_data_vec_sync2(11),
      R => '0'
    );
\cfg_data_vec_sync2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(12),
      Q => cfg_data_vec_sync2(12),
      R => '0'
    );
\cfg_data_vec_sync2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(13),
      Q => cfg_data_vec_sync2(13),
      R => '0'
    );
\cfg_data_vec_sync2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(14),
      Q => cfg_data_vec_sync2(14),
      R => '0'
    );
\cfg_data_vec_sync2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(15),
      Q => cfg_data_vec_sync2(15),
      R => '0'
    );
\cfg_data_vec_sync2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(16),
      Q => cfg_data_vec_sync2(16),
      R => '0'
    );
\cfg_data_vec_sync2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(17),
      Q => cfg_data_vec_sync2(17),
      R => '0'
    );
\cfg_data_vec_sync2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(18),
      Q => cfg_data_vec_sync2(18),
      R => '0'
    );
\cfg_data_vec_sync2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(19),
      Q => cfg_data_vec_sync2(19),
      R => '0'
    );
\cfg_data_vec_sync2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(1),
      Q => cfg_data_vec_sync2(1),
      R => '0'
    );
\cfg_data_vec_sync2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(20),
      Q => cfg_data_vec_sync2(20),
      R => '0'
    );
\cfg_data_vec_sync2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(21),
      Q => cfg_data_vec_sync2(21),
      R => '0'
    );
\cfg_data_vec_sync2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(22),
      Q => cfg_data_vec_sync2(22),
      R => '0'
    );
\cfg_data_vec_sync2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(23),
      Q => cfg_data_vec_sync2(23),
      R => '0'
    );
\cfg_data_vec_sync2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(24),
      Q => cfg_data_vec_sync2(24),
      R => '0'
    );
\cfg_data_vec_sync2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(25),
      Q => cfg_data_vec_sync2(25),
      R => '0'
    );
\cfg_data_vec_sync2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(26),
      Q => cfg_data_vec_sync2(26),
      R => '0'
    );
\cfg_data_vec_sync2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(27),
      Q => cfg_data_vec_sync2(27),
      R => '0'
    );
\cfg_data_vec_sync2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(28),
      Q => cfg_data_vec_sync2(28),
      R => '0'
    );
\cfg_data_vec_sync2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(29),
      Q => cfg_data_vec_sync2(29),
      R => '0'
    );
\cfg_data_vec_sync2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(2),
      Q => cfg_data_vec_sync2(2),
      R => '0'
    );
\cfg_data_vec_sync2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(30),
      Q => cfg_data_vec_sync2(30),
      R => '0'
    );
\cfg_data_vec_sync2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(31),
      Q => cfg_data_vec_sync2(31),
      R => '0'
    );
\cfg_data_vec_sync2_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(32),
      Q => cfg_data_vec_sync2(32),
      R => '0'
    );
\cfg_data_vec_sync2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(3),
      Q => cfg_data_vec_sync2(3),
      R => '0'
    );
\cfg_data_vec_sync2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(4),
      Q => cfg_data_vec_sync2(4),
      R => '0'
    );
\cfg_data_vec_sync2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(5),
      Q => cfg_data_vec_sync2(5),
      R => '0'
    );
\cfg_data_vec_sync2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(6),
      Q => cfg_data_vec_sync2(6),
      R => '0'
    );
\cfg_data_vec_sync2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(7),
      Q => cfg_data_vec_sync2(7),
      R => '0'
    );
\cfg_data_vec_sync2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(8),
      Q => cfg_data_vec_sync2(8),
      R => '0'
    );
\cfg_data_vec_sync2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cfg_data_vec_sync1(9),
      Q => cfg_data_vec_sync2(9),
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_0
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_1
    );
i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_10
    );
i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_11
    );
i_12: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_12
    );
i_13: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_13
    );
i_14: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_14
    );
i_15: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_15
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_2
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_3
    );
i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_4
    );
i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_5
    );
i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_6
    );
i_7: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_7
    );
i_8: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_8
    );
i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_9
    );
\i_intcap.CAP_ADDR_O_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(0),
      Q => \out\(0),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(1),
      Q => \out\(1),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(2),
      Q => \out\(2),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(3),
      Q => \out\(3),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(4),
      Q => \out\(4),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(5),
      Q => \out\(5),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(6),
      Q => \out\(6),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(7),
      Q => \out\(7),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(8),
      Q => \out\(8),
      R => Q(0)
    );
\i_intcap.CAP_ADDR_O_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => icap_addr(9),
      Q => \out\(9),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(0),
      Q => icap_addr(0),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(1),
      Q => icap_addr(1),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(2),
      Q => icap_addr(2),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(3),
      Q => icap_addr(3),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(4),
      Q => icap_addr(4),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(5),
      Q => icap_addr(5),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(6),
      Q => icap_addr(6),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(7),
      Q => icap_addr(7),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(8),
      Q => icap_addr(8),
      R => Q(0)
    );
\i_intcap.icap_addr_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => cap_addr_next(9),
      Q => icap_addr(9),
      R => Q(0)
    );
\i_o_to_64k.cfg_data_vec_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(9),
      Q => cfg_data_vec(10),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(10),
      Q => cfg_data_vec(11),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(11),
      Q => cfg_data_vec(12),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(12),
      Q => cfg_data_vec(13),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(13),
      Q => cfg_data_vec(14),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(14),
      Q => cfg_data_vec(15),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(15),
      Q => cfg_data_vec(16),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => in0(0),
      Q => cfg_data_vec(1),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(1),
      Q => cfg_data_vec(2),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(2),
      Q => cfg_data_vec(3),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(3),
      Q => cfg_data_vec(4),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(4),
      Q => cfg_data_vec(5),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(5),
      Q => cfg_data_vec(6),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(6),
      Q => cfg_data_vec(7),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(7),
      Q => cfg_data_vec(8),
      R => '0'
    );
\i_o_to_64k.cfg_data_vec_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk_o,
      CE => E(0),
      D => cfg_data_vec(8),
      Q => cfg_data_vec(9),
      R => '0'
    );
\i_o_to_64k.u_selx\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => E(0),
      CLK => s_dclk_o,
      D => cfg_data_vec(16),
      Q => cfg_data_0
    );
icap_wr_en_reg: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => scnt_ce,
      Q => icap_wr_en,
      R => Q(0)
    );
u_cap_sample_counter: entity work.ila_full_aurora_ila_v6_2_10_ila_cap_sample_counter
     port map (
      A(2) => \^a\(2),
      A(1 downto 0) => u_wcnt_lcmp_q(1 downto 0),
      D(9 downto 0) => cap_addr_next(9 downto 0),
      DOUT_O => DOUT_O,
      E(0) => scnt_ce,
      Q(9 downto 0) => wcnt(9 downto 0),
      SRL_Q_O => cfg_data_2,
      basic_trigger => basic_trigger,
      \capture_qual_ctrl_reg[0]\(1 downto 0) => \^a\(1 downto 0),
      cfg_data_1 => cfg_data_1,
      cmp_reset => cmp_reset,
      \out\(9 downto 0) => cfg_data_vec_sync2(10 downto 1),
      \probeDelay1_reg[9]\ => \probeDelay1_reg[0]\,
      s_dclk_o => s_dclk_o,
      scnt_cmp_temp => scnt_cmp_temp,
      u_scnt_cmp_q_0(0) => \^u_scnt_cmp_q\(0),
      u_scnt_cmp_q_1(0) => E(0),
      u_scnt_cmp_q_2(1 downto 0) => u_scnt_cmp_q_0(1 downto 0),
      u_scnt_cmp_q_3 => u_scnt_cmp_q_1
    );
u_cap_window_counter: entity work.ila_full_aurora_ila_v6_2_10_ila_cap_window_counter
     port map (
      A(3 downto 2) => \^a\(1 downto 0),
      A(1 downto 0) => u_wcnt_lcmp_q(1 downto 0),
      E(0) => E(0),
      Q(9 downto 0) => wcnt(9 downto 0),
      SRL_Q_O => cfg_data_2,
      cmp_reset => cmp_reset,
      \iwcnt_reg[9]_0\(0) => Q(0),
      \probeDelay1_reg[0]\ => \probeDelay1_reg[0]\,
      s_dclk_o => s_dclk_o,
      shift_en_reg => shift_en_reg,
      shift_en_reg_0 => shift_en_reg_0,
      shift_en_reg_1 => SRL_Q_O,
      u_wcnt_lcmp_q_0(0) => \^a\(2),
      wcnt_hcmp => wcnt_hcmp,
      wcnt_hcmp_temp => wcnt_hcmp_temp,
      wcnt_lcmp_temp => wcnt_lcmp_temp
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_trigger is
  port (
    mu_config_cs_serial_input : out STD_LOGIC_VECTOR ( 5 downto 0 );
    shift_en_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    TRIGGER_EQ : out STD_LOGIC;
    mu_config_cs_serial_output : in STD_LOGIC_VECTOR ( 5 downto 0 );
    mu_config_cs_shift_en : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_dclk_o : in STD_LOGIC;
    tc_config_cs_serial_output : in STD_LOGIC;
    \parallel_dout_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    probe0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_trigger : entity is "ila_v6_2_10_ila_trigger";
end ila_full_aurora_ila_v6_2_10_ila_trigger;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_trigger is
  signal \N_DDR_TC.N_DDR_TC_INST[0].U_TC_n_1\ : STD_LOGIC;
  signal trigCondIn_temp : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
\N_DDR_TC.N_DDR_TC_INST[0].U_TC\: entity work.ila_full_aurora_ltlib_v1_0_0_match
     port map (
      D(5 downto 0) => trigCondIn_temp(5 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(1 downto 0) => Q(2 downto 1),
      \parallel_dout_reg[15]\(0) => \parallel_dout_reg[15]\(0),
      s_dclk_o => s_dclk_o,
      shift_en_reg(0) => shift_en_reg(0),
      tc_config_cs_serial_output => tc_config_cs_serial_output,
      \yes_output_reg.dout_reg_reg_0\ => \N_DDR_TC.N_DDR_TC_INST[0].U_TC_n_1\
    );
\TRIGGER_EQ_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \N_DDR_TC.N_DDR_TC_INST[0].U_TC_n_1\,
      Q => TRIGGER_EQ,
      R => '0'
    );
U_TM: entity work.ila_full_aurora_ila_v6_2_10_ila_trig_match
     port map (
      D(5 downto 0) => trigCondIn_temp(5 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(0) => Q(0),
      mu_config_cs_serial_input(5 downto 0) => mu_config_cs_serial_input(5 downto 0),
      mu_config_cs_serial_output(5 downto 0) => mu_config_cs_serial_output(5 downto 0),
      mu_config_cs_shift_en(5 downto 0) => mu_config_cs_shift_en(5 downto 0),
      \out\ => \out\,
      probe0(47 downto 0) => probe0(47 downto 0),
      probe1(0) => probe1(0),
      probe2(0) => probe2(0),
      probe3(7 downto 0) => probe3(7 downto 0),
      probe4(31 downto 0) => probe4(31 downto 0),
      probe5(31 downto 0) => probe5(31 downto 0),
      \probeDelay1_reg[15]\(15 downto 0) => D(15 downto 0),
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_cap_ctrl_legacy is
  port (
    A : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \out\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    CAP_WR_EN_O_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    CAP_DONE_O_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DOUT_O : out STD_LOGIC;
    shift_en_reg : out STD_LOGIC;
    shift_en_reg_0 : out STD_LOGIC;
    \captured_samples_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    capture_ctrl_config_serial_output : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    scnt_cmp_temp : in STD_LOGIC;
    \probeDelay1_reg[0]\ : in STD_LOGIC;
    wcnt_lcmp_temp : in STD_LOGIC;
    wcnt_hcmp_temp : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    basic_trigger : in STD_LOGIC;
    itrigger_out_reg_0 : in STD_LOGIC;
    u_scnt_cmp_q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \captured_samples_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_cap_ctrl_legacy : entity is "ila_v6_2_10_ila_cap_ctrl_legacy";
end ila_full_aurora_ila_v6_2_10_ila_cap_ctrl_legacy;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_cap_ctrl_legacy is
  signal \^a\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^cap_done_o_reg_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal U_CDONE_n_1 : STD_LOGIC;
  signal cfg_data_0 : STD_LOGIC;
  signal cfg_data_1 : STD_LOGIC;
  signal cfg_data_2 : STD_LOGIC;
  signal \itrigger_in__0\ : STD_LOGIC;
  signal itrigger_out : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of itrigger_out : signal is "yes";
  attribute async_reg : string;
  attribute async_reg of itrigger_out : signal is "true";
  signal itrigger_out_inst_n_0 : STD_LOGIC;
  attribute async_reg of itrigger_out_inst_n_0 : signal is "true";
  signal scnt_cmp : STD_LOGIC;
  signal u_cap_addrgen_n_1 : STD_LOGIC;
  signal u_cap_addrgen_n_2 : STD_LOGIC;
  signal wcnt_hcmp : STD_LOGIC;
  signal wcnt_lcmp : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of itrigger_out_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of itrigger_out_reg : label is "yes";
begin
  A(1 downto 0) <= \^a\(1 downto 0);
  CAP_DONE_O_reg_0(1 downto 0) <= \^cap_done_o_reg_0\(1 downto 0);
CAP_DONE_O_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => U_CDONE_n_1,
      Q => \^cap_done_o_reg_0\(1),
      R => '0'
    );
CAP_TRIGGER_O_reg: unisim.vcomponents.FDRE
     port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => itrigger_out_inst_n_0,
      Q => \^cap_done_o_reg_0\(0),
      R => Q(0)
    );
U_CDONE: entity work.\ila_full_aurora_ltlib_v1_0_0_cfglut6__parameterized0\
     port map (
      A(4) => wcnt_lcmp,
      A(3) => u_cap_addrgen_n_1,
      A(2) => u_cap_addrgen_n_2,
      A(1 downto 0) => \^a\(1 downto 0),
      CAP_DONE_O_reg => U_CDONE_n_1,
      CAP_DONE_O_reg_0(0) => \^cap_done_o_reg_0\(1),
      D(0) => D(0),
      E(0) => E(0),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_0\ => \probeDelay1_reg[0]\,
      Q(1 downto 0) => Q(1 downto 0),
      SRL_Q_O => cfg_data_2,
      s_dclk_o => s_dclk_o,
      wcnt_hcmp => wcnt_hcmp
    );
U_NS0: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut7
     port map (
      A(3) => scnt_cmp,
      A(2) => u_cap_addrgen_n_1,
      A(1) => u_cap_addrgen_n_2,
      A(0) => \^a\(1),
      E(0) => E(0),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_0\(0) => \^a\(0),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_1\ => \probeDelay1_reg[0]\,
      \I_YESLUT6.I_YES_OREG.O_reg_reg_2\(0) => wcnt_lcmp,
      Q(0) => Q(0),
      cfg_data_0 => cfg_data_0,
      in0(0) => cfg_data_1,
      s_dclk_o => s_dclk_o,
      wcnt_hcmp => wcnt_hcmp
    );
U_NS1: entity work.ila_full_aurora_ltlib_v1_0_0_cfglut7_47
     port map (
      A(2) => scnt_cmp,
      A(1) => u_cap_addrgen_n_1,
      A(0) => u_cap_addrgen_n_2,
      E(0) => E(0),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_0\(0) => \^a\(1),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(1) => wcnt_lcmp,
      \I_YESLUT6.I_YES_OREG.O_reg_reg_1\(0) => \^a\(0),
      \I_YESLUT6.I_YES_OREG.O_reg_reg_2\ => \probeDelay1_reg[0]\,
      Q(0) => Q(0),
      capture_ctrl_config_serial_output => capture_ctrl_config_serial_output,
      cfg_data_0 => cfg_data_0,
      s_dclk_o => s_dclk_o,
      wcnt_hcmp => wcnt_hcmp
    );
itrigger_in: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \^a\(1),
      I1 => \^a\(0),
      I2 => basic_trigger,
      I3 => itrigger_out_reg_0,
      O => \itrigger_in__0\
    );
itrigger_out_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => itrigger_out,
      O => itrigger_out_inst_n_0
    );
itrigger_out_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \probeDelay1_reg[0]\,
      CE => '1',
      D => \itrigger_in__0\,
      Q => itrigger_out,
      R => Q(0)
    );
u_cap_addrgen: entity work.ila_full_aurora_ila_v6_2_10_ila_cap_addrgen
     port map (
      A(2) => wcnt_lcmp,
      A(1) => u_cap_addrgen_n_1,
      A(0) => u_cap_addrgen_n_2,
      CAP_WR_EN_O_reg_0 => CAP_WR_EN_O_reg,
      DOUT_O => DOUT_O,
      E(0) => E(0),
      Q(0) => Q(0),
      SRL_Q_O => cfg_data_2,
      basic_trigger => basic_trigger,
      \captured_samples_reg[0]_0\(0) => \captured_samples_reg[0]\(0),
      \captured_samples_reg[9]_0\(9 downto 0) => \captured_samples_reg[9]\(9 downto 0),
      in0(0) => cfg_data_1,
      \out\(9 downto 0) => \out\(9 downto 0),
      \probeDelay1_reg[0]\ => \probeDelay1_reg[0]\,
      s_dclk_o => s_dclk_o,
      scnt_cmp_temp => scnt_cmp_temp,
      shift_en_reg => shift_en_reg,
      shift_en_reg_0 => shift_en_reg_0,
      u_scnt_cmp_q(0) => scnt_cmp,
      u_scnt_cmp_q_0(1 downto 0) => u_scnt_cmp_q(1 downto 0),
      u_scnt_cmp_q_1 => itrigger_out_reg_0,
      u_wcnt_lcmp_q(1 downto 0) => \^a\(1 downto 0),
      wcnt_hcmp => wcnt_hcmp,
      wcnt_hcmp_temp => wcnt_hcmp_temp,
      wcnt_lcmp_temp => wcnt_lcmp_temp
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_trace_memory is
  port (
    D : out STD_LOGIC_VECTOR ( 138 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
    s_dclk_o : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    DIADI : in STD_LOGIC_VECTOR ( 31 downto 0 );
    DIPADIP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 30 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_trace_memory : entity is "ila_v6_2_10_ila_trace_memory";
end ila_full_aurora_ila_v6_2_10_ila_trace_memory;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_trace_memory is
begin
\SUBCORE_RAM_BLK_MEM_1.trace_block_memory\: entity work.ila_full_aurora_blk_mem_gen_v8_4_4
     port map (
      D(138 downto 0) => D(138 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30 downto 0),
      DIADI(31 downto 0) => DIADI(31 downto 0),
      DIPADIP(3 downto 0) => DIPADIP(3 downto 0),
      Q(9 downto 0) => Q(9 downto 0),
      \out\ => \out\,
      s_dclk_o => s_dclk_o
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila_core is
  port (
    sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
    \out\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
    dummy_temp1_reg : in STD_LOGIC;
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila_core : entity is "ila_v6_2_10_ila_core";
end ila_full_aurora_ila_v6_2_10_ila_core;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila_core is
  signal O_reg : STD_LOGIC;
  signal TRIGGER_EQ : STD_LOGIC;
  signal arm_ctrl : STD_LOGIC;
  signal arm_status : STD_LOGIC;
  signal basic_trigger : STD_LOGIC;
  signal cap_done : STD_LOGIC;
  signal cap_trigger_out : STD_LOGIC;
  signal cap_wr_addr : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal cap_wr_en : STD_LOGIC;
  signal capture_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal capture_ctrl_config_cs_serial_input : STD_LOGIC;
  signal capture_ctrl_config_en : STD_LOGIC;
  signal capture_ctrl_config_serial_output : STD_LOGIC;
  signal capture_qual_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute async_reg : string;
  attribute async_reg of capture_qual_ctrl : signal is "true";
  signal capture_qual_ctrl_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal capture_qual_ctrl_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute async_reg of capture_qual_ctrl_2 : signal is "true";
  signal curr_read_block : STD_LOGIC_VECTOR ( 0 to 0 );
  signal data_out_en_1 : STD_LOGIC;
  signal data_word_out : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal debug_data_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal debug_data_in_sync1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute async_reg of debug_data_in_sync1 : signal is "true";
  signal debug_data_in_sync2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute async_reg of debug_data_in_sync2 : signal is "true";
  signal en_adv_trigger : STD_LOGIC;
  attribute async_reg of en_adv_trigger : signal is "true";
  signal en_adv_trigger_1 : STD_LOGIC;
  signal en_adv_trigger_2 : STD_LOGIC;
  attribute async_reg of en_adv_trigger_2 : signal is "true";
  signal halt_ctrl : STD_LOGIC;
  signal halt_status : STD_LOGIC;
  signal mem_data_out : STD_LOGIC_VECTOR ( 138 downto 0 );
  signal mu_config_cs_serial_input : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal mu_config_cs_serial_output : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal mu_config_cs_shift_en : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal next_state : STD_LOGIC_VECTOR ( 6 downto 3 );
  signal probe_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal read_addr_reset : STD_LOGIC;
  signal read_data_en : STD_LOGIC;
  signal read_reset_addr : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal reset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s_dclk : STD_LOGIC;
  signal \shifted_data_in_reg[7][0]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][100]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][101]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][102]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][103]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][104]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][105]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][106]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][107]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][108]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][109]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][10]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][110]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][111]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][112]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][113]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][114]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][115]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][116]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][117]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][118]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][119]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][11]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][120]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][121]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][122]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][123]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][124]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][125]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][126]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][127]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][128]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][129]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][12]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][130]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][131]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][132]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][133]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][134]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][135]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][136]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][137]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][13]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][14]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][15]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][16]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][17]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][18]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][19]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][1]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][20]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][21]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][22]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][23]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][24]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][25]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][26]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][27]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][28]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][29]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][2]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][30]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][31]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][32]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][33]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][34]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][35]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][36]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][37]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][38]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][39]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][3]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][40]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][41]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][42]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][43]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][44]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][45]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][46]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][47]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][48]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][49]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][4]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][50]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][51]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][52]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][53]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][54]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][55]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][56]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][57]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][58]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][59]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][5]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][60]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][61]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][62]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][63]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][64]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][65]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][66]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][67]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][68]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][69]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][6]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][70]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][71]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][72]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][73]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][74]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][75]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][76]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][77]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][78]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][79]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][7]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][80]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][81]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][82]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][83]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][84]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][85]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][86]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][87]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][88]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][89]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][8]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][90]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][91]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][92]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][93]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][94]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][95]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][96]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][97]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][98]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][99]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg[7][9]_srl8_n_0\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][0]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][100]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][101]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][102]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][103]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][104]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][105]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][106]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][107]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][108]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][109]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][10]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][110]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][111]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][112]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][113]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][114]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][115]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][116]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][117]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][118]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][119]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][11]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][120]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][121]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][122]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][123]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][124]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][125]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][126]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][127]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][128]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][129]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][12]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][130]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][131]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][132]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][133]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][134]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][135]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][136]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][137]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][13]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][14]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][15]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][16]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][17]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][18]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][19]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][1]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][20]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][21]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][22]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][23]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][24]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][25]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][26]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][27]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][28]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][29]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][2]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][30]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][31]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][32]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][33]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][34]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][35]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][36]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][37]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][38]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][39]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][3]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][40]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][41]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][42]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][43]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][44]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][45]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][46]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][47]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][48]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][49]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][4]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][50]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][51]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][52]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][53]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][54]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][55]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][56]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][57]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][58]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][59]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][5]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][60]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][61]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][62]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][63]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][64]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][65]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][66]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][67]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][68]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][69]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][6]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][70]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][71]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][72]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][73]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][74]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][75]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][76]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][77]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][78]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][79]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][7]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][80]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][81]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][82]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][83]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][84]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][85]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][86]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][87]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][88]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][89]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][8]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][90]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][91]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][92]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][93]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][94]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][95]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][96]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][97]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][98]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][99]\ : STD_LOGIC;
  signal \shifted_data_in_reg_n_0_[8][9]\ : STD_LOGIC;
  signal tc_config_cs_serial_input : STD_LOGIC;
  signal tc_config_cs_serial_output : STD_LOGIC;
  signal tc_config_cs_shift_en : STD_LOGIC;
  signal trace_data_ack : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \trace_data_ack_reg_n_0_[0]\ : STD_LOGIC;
  signal trace_read_addr : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal trace_read_en : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp\ : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1\ : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp\ : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1\ : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp\ : STD_LOGIC;
  signal \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1\ : STD_LOGIC;
  signal u_ila_cap_ctrl_n_1 : STD_LOGIC;
  signal u_ila_regs_n_28 : STD_LOGIC;
  signal u_ila_regs_n_32 : STD_LOGIC;
  signal u_ila_reset_ctrl_n_2 : STD_LOGIC;
  signal u_ila_reset_ctrl_n_6 : STD_LOGIC;
  signal use_probe_debug_circuit : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of use_probe_debug_circuit : signal is std.standard.true;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of use_probe_debug_circuit : signal is "yes";
  attribute async_reg of use_probe_debug_circuit : signal is "true";
  signal use_probe_debug_circuit_1 : STD_LOGIC;
  signal use_probe_debug_circuit_2 : STD_LOGIC;
  attribute DONT_TOUCH of use_probe_debug_circuit_2 : signal is std.standard.true;
  attribute RTL_KEEP of use_probe_debug_circuit_2 : signal is "yes";
  attribute async_reg of use_probe_debug_circuit_2 : signal is "true";
  signal xsdb_memory_read_inst_n_15 : STD_LOGIC;
  signal xsdb_memory_read_inst_n_16 : STD_LOGIC;
  signal xsdb_memory_read_inst_n_17 : STD_LOGIC;
  signal xsdb_memory_read_inst_n_18 : STD_LOGIC;
  signal xsdb_memory_read_inst_n_3 : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \capture_qual_ctrl_2_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \capture_qual_ctrl_2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \capture_qual_ctrl_2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \capture_qual_ctrl_2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \capture_qual_ctrl_reg[0]\ : label is std.standard.true;
  attribute KEEP of \capture_qual_ctrl_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \capture_qual_ctrl_reg[1]\ : label is std.standard.true;
  attribute KEEP of \capture_qual_ctrl_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[12]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[13]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[14]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[15]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync1_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[0]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[10]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[11]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[12]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[13]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[14]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[15]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[2]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[3]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[4]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[5]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[6]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[7]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[8]\ : label is "yes";
  attribute ASYNC_REG_boolean of \debug_data_in_sync2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \debug_data_in_sync2_reg[9]\ : label is "yes";
  attribute ASYNC_REG_boolean of en_adv_trigger_2_reg : label is std.standard.true;
  attribute KEEP of en_adv_trigger_2_reg : label is "yes";
  attribute ASYNC_REG_boolean of en_adv_trigger_reg : label is std.standard.true;
  attribute KEEP of en_adv_trigger_reg : label is "yes";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \shifted_data_in_reg[7][0]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name : string;
  attribute srl_name of \shifted_data_in_reg[7][0]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][0]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][100]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][100]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][100]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][101]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][101]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][101]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][102]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][102]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][102]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][103]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][103]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][103]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][104]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][104]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][104]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][105]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][105]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][105]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][106]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][106]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][106]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][107]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][107]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][107]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][108]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][108]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][108]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][109]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][109]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][109]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][10]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][10]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][10]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][110]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][110]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][110]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][111]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][111]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][111]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][112]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][112]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][112]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][113]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][113]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][113]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][114]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][114]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][114]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][115]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][115]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][115]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][116]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][116]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][116]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][117]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][117]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][117]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][118]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][118]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][118]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][119]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][119]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][119]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][11]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][11]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][11]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][120]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][120]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][120]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][121]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][121]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][121]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][122]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][122]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][122]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][123]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][123]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][123]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][124]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][124]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][124]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][125]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][125]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][125]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][126]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][126]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][126]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][127]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][127]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][127]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][128]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][128]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][128]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][129]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][129]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][129]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][12]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][12]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][12]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][130]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][130]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][130]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][131]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][131]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][131]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][132]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][132]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][132]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][133]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][133]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][133]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][134]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][134]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][134]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][135]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][135]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][135]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][136]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][136]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][136]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][137]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][137]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][137]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][13]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][13]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][13]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][14]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][14]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][14]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][15]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][15]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][15]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][16]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][16]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][16]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][17]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][17]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][17]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][18]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][18]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][18]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][19]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][19]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][19]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][1]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][1]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][1]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][20]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][20]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][20]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][21]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][21]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][21]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][22]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][22]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][22]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][23]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][23]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][23]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][24]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][24]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][24]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][25]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][25]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][25]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][26]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][26]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][26]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][27]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][27]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][27]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][28]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][28]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][28]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][29]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][29]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][29]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][2]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][2]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][2]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][30]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][30]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][30]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][31]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][31]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][31]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][32]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][32]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][32]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][33]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][33]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][33]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][34]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][34]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][34]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][35]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][35]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][35]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][36]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][36]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][36]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][37]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][37]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][37]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][38]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][38]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][38]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][39]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][39]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][39]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][3]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][3]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][3]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][40]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][40]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][40]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][41]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][41]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][41]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][42]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][42]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][42]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][43]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][43]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][43]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][44]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][44]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][44]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][45]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][45]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][45]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][46]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][46]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][46]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][47]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][47]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][47]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][48]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][48]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][48]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][49]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][49]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][49]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][4]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][4]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][4]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][50]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][50]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][50]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][51]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][51]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][51]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][52]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][52]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][52]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][53]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][53]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][53]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][54]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][54]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][54]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][55]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][55]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][55]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][56]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][56]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][56]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][57]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][57]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][57]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][58]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][58]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][58]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][59]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][59]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][59]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][5]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][5]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][5]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][60]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][60]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][60]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][61]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][61]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][61]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][62]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][62]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][62]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][63]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][63]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][63]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][64]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][64]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][64]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][65]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][65]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][65]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][66]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][66]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][66]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][67]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][67]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][67]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][68]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][68]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][68]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][69]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][69]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][69]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][6]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][6]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][6]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][70]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][70]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][70]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][71]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][71]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][71]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][72]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][72]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][72]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][73]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][73]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][73]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][74]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][74]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][74]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][75]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][75]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][75]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][76]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][76]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][76]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][77]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][77]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][77]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][78]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][78]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][78]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][79]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][79]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][79]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][7]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][7]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][7]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][80]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][80]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][80]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][81]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][81]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][81]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][82]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][82]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][82]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][83]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][83]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][83]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][84]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][84]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][84]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][85]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][85]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][85]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][86]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][86]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][86]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][87]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][87]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][87]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][88]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][88]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][88]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][89]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][89]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][89]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][8]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][8]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][8]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][90]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][90]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][90]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][91]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][91]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][91]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][92]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][92]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][92]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][93]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][93]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][93]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][94]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][94]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][94]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][95]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][95]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][95]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][96]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][96]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][96]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][97]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][97]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][97]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][98]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][98]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][98]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][99]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][99]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][99]_srl8 ";
  attribute srl_bus_name of \shifted_data_in_reg[7][9]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7] ";
  attribute srl_name of \shifted_data_in_reg[7][9]_srl8\ : label is "U0/\ila_core_inst/shifted_data_in_reg[7][9]_srl8 ";
  attribute ASYNC_REG_boolean of use_probe_debug_circuit_2_reg : label is std.standard.true;
  attribute DONT_TOUCH of use_probe_debug_circuit_2_reg : label is std.standard.true;
  attribute KEEP of use_probe_debug_circuit_2_reg : label is "yes";
  attribute ASYNC_REG_boolean of use_probe_debug_circuit_reg : label is std.standard.true;
  attribute DONT_TOUCH of use_probe_debug_circuit_reg : label is std.standard.true;
  attribute KEEP of use_probe_debug_circuit_reg : label is "yes";
begin
basic_trigger_reg: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => TRIGGER_EQ,
      Q => basic_trigger,
      R => '0'
    );
\capture_qual_ctrl_2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => capture_qual_ctrl_1(0),
      Q => capture_qual_ctrl_2(0),
      R => '0'
    );
\capture_qual_ctrl_2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => capture_qual_ctrl_1(1),
      Q => capture_qual_ctrl_2(1),
      R => '0'
    );
\capture_qual_ctrl_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => capture_qual_ctrl_2(0),
      Q => capture_qual_ctrl(0),
      R => '0'
    );
\capture_qual_ctrl_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => capture_qual_ctrl_2(1),
      Q => capture_qual_ctrl(1),
      R => '0'
    );
\debug_data_in_sync1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(0),
      Q => debug_data_in_sync1(0),
      R => '0'
    );
\debug_data_in_sync1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(10),
      Q => debug_data_in_sync1(10),
      R => '0'
    );
\debug_data_in_sync1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(11),
      Q => debug_data_in_sync1(11),
      R => '0'
    );
\debug_data_in_sync1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(12),
      Q => debug_data_in_sync1(12),
      R => '0'
    );
\debug_data_in_sync1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(13),
      Q => debug_data_in_sync1(13),
      R => '0'
    );
\debug_data_in_sync1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(14),
      Q => debug_data_in_sync1(14),
      R => '0'
    );
\debug_data_in_sync1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(15),
      Q => debug_data_in_sync1(15),
      R => '0'
    );
\debug_data_in_sync1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(1),
      Q => debug_data_in_sync1(1),
      R => '0'
    );
\debug_data_in_sync1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(2),
      Q => debug_data_in_sync1(2),
      R => '0'
    );
\debug_data_in_sync1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(3),
      Q => debug_data_in_sync1(3),
      R => '0'
    );
\debug_data_in_sync1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(4),
      Q => debug_data_in_sync1(4),
      R => '0'
    );
\debug_data_in_sync1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(5),
      Q => debug_data_in_sync1(5),
      R => '0'
    );
\debug_data_in_sync1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(6),
      Q => debug_data_in_sync1(6),
      R => '0'
    );
\debug_data_in_sync1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(7),
      Q => debug_data_in_sync1(7),
      R => '0'
    );
\debug_data_in_sync1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(8),
      Q => debug_data_in_sync1(8),
      R => '0'
    );
\debug_data_in_sync1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in(9),
      Q => debug_data_in_sync1(9),
      R => '0'
    );
\debug_data_in_sync2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(0),
      Q => debug_data_in_sync2(0),
      R => '0'
    );
\debug_data_in_sync2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(10),
      Q => debug_data_in_sync2(10),
      R => '0'
    );
\debug_data_in_sync2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(11),
      Q => debug_data_in_sync2(11),
      R => '0'
    );
\debug_data_in_sync2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(12),
      Q => debug_data_in_sync2(12),
      R => '0'
    );
\debug_data_in_sync2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(13),
      Q => debug_data_in_sync2(13),
      R => '0'
    );
\debug_data_in_sync2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(14),
      Q => debug_data_in_sync2(14),
      R => '0'
    );
\debug_data_in_sync2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(15),
      Q => debug_data_in_sync2(15),
      R => '0'
    );
\debug_data_in_sync2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(1),
      Q => debug_data_in_sync2(1),
      R => '0'
    );
\debug_data_in_sync2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(2),
      Q => debug_data_in_sync2(2),
      R => '0'
    );
\debug_data_in_sync2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(3),
      Q => debug_data_in_sync2(3),
      R => '0'
    );
\debug_data_in_sync2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(4),
      Q => debug_data_in_sync2(4),
      R => '0'
    );
\debug_data_in_sync2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(5),
      Q => debug_data_in_sync2(5),
      R => '0'
    );
\debug_data_in_sync2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(6),
      Q => debug_data_in_sync2(6),
      R => '0'
    );
\debug_data_in_sync2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(7),
      Q => debug_data_in_sync2(7),
      R => '0'
    );
\debug_data_in_sync2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(8),
      Q => debug_data_in_sync2(8),
      R => '0'
    );
\debug_data_in_sync2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => debug_data_in_sync1(9),
      Q => debug_data_in_sync2(9),
      R => '0'
    );
en_adv_trigger_2_reg: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => en_adv_trigger_1,
      Q => en_adv_trigger_2,
      R => '0'
    );
en_adv_trigger_reg: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => en_adv_trigger_2,
      Q => en_adv_trigger,
      R => '0'
    );
ila_trace_memory_inst: entity work.ila_full_aurora_ila_v6_2_10_ila_trace_memory
     port map (
      D(138 downto 0) => mem_data_out(138 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => trace_read_en,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(9 downto 0) => cap_wr_addr(9 downto 0),
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(31) => \shifted_data_in_reg_n_0_[8][70]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(30) => \shifted_data_in_reg_n_0_[8][69]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(29) => \shifted_data_in_reg_n_0_[8][68]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(28) => \shifted_data_in_reg_n_0_[8][67]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(27) => \shifted_data_in_reg_n_0_[8][66]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(26) => \shifted_data_in_reg_n_0_[8][65]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(25) => \shifted_data_in_reg_n_0_[8][64]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(24) => \shifted_data_in_reg_n_0_[8][63]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(23) => \shifted_data_in_reg_n_0_[8][61]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(22) => \shifted_data_in_reg_n_0_[8][60]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(21) => \shifted_data_in_reg_n_0_[8][59]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(20) => \shifted_data_in_reg_n_0_[8][58]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(19) => \shifted_data_in_reg_n_0_[8][57]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(18) => \shifted_data_in_reg_n_0_[8][56]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(17) => \shifted_data_in_reg_n_0_[8][55]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(16) => \shifted_data_in_reg_n_0_[8][54]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(15) => \shifted_data_in_reg_n_0_[8][52]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(14) => \shifted_data_in_reg_n_0_[8][51]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(13) => \shifted_data_in_reg_n_0_[8][50]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(12) => \shifted_data_in_reg_n_0_[8][49]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(11) => \shifted_data_in_reg_n_0_[8][48]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(10) => \shifted_data_in_reg_n_0_[8][47]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(9) => \shifted_data_in_reg_n_0_[8][46]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(8) => \shifted_data_in_reg_n_0_[8][45]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(7) => \shifted_data_in_reg_n_0_[8][43]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(6) => \shifted_data_in_reg_n_0_[8][42]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(5) => \shifted_data_in_reg_n_0_[8][41]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(4) => \shifted_data_in_reg_n_0_[8][40]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(3) => \shifted_data_in_reg_n_0_[8][39]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(2) => \shifted_data_in_reg_n_0_[8][38]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(1) => \shifted_data_in_reg_n_0_[8][37]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0) => \shifted_data_in_reg_n_0_[8][36]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3) => \shifted_data_in_reg_n_0_[8][71]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(2) => \shifted_data_in_reg_n_0_[8][62]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(1) => \shifted_data_in_reg_n_0_[8][53]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(0) => \shifted_data_in_reg_n_0_[8][44]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(31) => \shifted_data_in_reg_n_0_[8][106]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(30) => \shifted_data_in_reg_n_0_[8][105]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(29) => \shifted_data_in_reg_n_0_[8][104]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(28) => \shifted_data_in_reg_n_0_[8][103]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(27) => \shifted_data_in_reg_n_0_[8][102]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(26) => \shifted_data_in_reg_n_0_[8][101]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(25) => \shifted_data_in_reg_n_0_[8][100]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(24) => \shifted_data_in_reg_n_0_[8][99]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(23) => \shifted_data_in_reg_n_0_[8][97]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(22) => \shifted_data_in_reg_n_0_[8][96]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(21) => \shifted_data_in_reg_n_0_[8][95]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(20) => \shifted_data_in_reg_n_0_[8][94]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(19) => \shifted_data_in_reg_n_0_[8][93]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(18) => \shifted_data_in_reg_n_0_[8][92]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(17) => \shifted_data_in_reg_n_0_[8][91]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(16) => \shifted_data_in_reg_n_0_[8][90]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(15) => \shifted_data_in_reg_n_0_[8][88]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(14) => \shifted_data_in_reg_n_0_[8][87]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(13) => \shifted_data_in_reg_n_0_[8][86]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(12) => \shifted_data_in_reg_n_0_[8][85]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(11) => \shifted_data_in_reg_n_0_[8][84]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(10) => \shifted_data_in_reg_n_0_[8][83]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(9) => \shifted_data_in_reg_n_0_[8][82]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(8) => \shifted_data_in_reg_n_0_[8][81]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(7) => \shifted_data_in_reg_n_0_[8][79]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(6) => \shifted_data_in_reg_n_0_[8][78]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(5) => \shifted_data_in_reg_n_0_[8][77]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(4) => \shifted_data_in_reg_n_0_[8][76]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3) => \shifted_data_in_reg_n_0_[8][75]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(2) => \shifted_data_in_reg_n_0_[8][74]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(1) => \shifted_data_in_reg_n_0_[8][73]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(0) => \shifted_data_in_reg_n_0_[8][72]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3) => \shifted_data_in_reg_n_0_[8][107]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(2) => \shifted_data_in_reg_n_0_[8][98]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(1) => \shifted_data_in_reg_n_0_[8][89]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(0) => \shifted_data_in_reg_n_0_[8][80]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(30) => cap_trigger_out,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(29) => \shifted_data_in_reg_n_0_[8][137]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(28) => \shifted_data_in_reg_n_0_[8][136]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(27) => \shifted_data_in_reg_n_0_[8][135]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(26) => \shifted_data_in_reg_n_0_[8][134]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(25) => \shifted_data_in_reg_n_0_[8][133]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(24) => \shifted_data_in_reg_n_0_[8][132]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(23) => \shifted_data_in_reg_n_0_[8][131]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(22) => \shifted_data_in_reg_n_0_[8][130]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(21) => \shifted_data_in_reg_n_0_[8][129]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(20) => \shifted_data_in_reg_n_0_[8][128]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(19) => \shifted_data_in_reg_n_0_[8][127]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(18) => \shifted_data_in_reg_n_0_[8][126]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(17) => \shifted_data_in_reg_n_0_[8][125]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(16) => \shifted_data_in_reg_n_0_[8][124]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(15) => \shifted_data_in_reg_n_0_[8][123]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(14) => \shifted_data_in_reg_n_0_[8][122]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(13) => \shifted_data_in_reg_n_0_[8][121]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(12) => \shifted_data_in_reg_n_0_[8][120]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(11) => \shifted_data_in_reg_n_0_[8][119]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(10) => \shifted_data_in_reg_n_0_[8][118]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(9) => \shifted_data_in_reg_n_0_[8][117]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(8) => \shifted_data_in_reg_n_0_[8][116]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(7) => \shifted_data_in_reg_n_0_[8][115]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(6) => \shifted_data_in_reg_n_0_[8][114]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(5) => \shifted_data_in_reg_n_0_[8][113]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(4) => \shifted_data_in_reg_n_0_[8][112]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(3) => \shifted_data_in_reg_n_0_[8][111]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(2) => \shifted_data_in_reg_n_0_[8][110]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(1) => \shifted_data_in_reg_n_0_[8][109]\,
      \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(0) => \shifted_data_in_reg_n_0_[8][108]\,
      DIADI(31) => \shifted_data_in_reg_n_0_[8][34]\,
      DIADI(30) => \shifted_data_in_reg_n_0_[8][33]\,
      DIADI(29) => \shifted_data_in_reg_n_0_[8][32]\,
      DIADI(28) => \shifted_data_in_reg_n_0_[8][31]\,
      DIADI(27) => \shifted_data_in_reg_n_0_[8][30]\,
      DIADI(26) => \shifted_data_in_reg_n_0_[8][29]\,
      DIADI(25) => \shifted_data_in_reg_n_0_[8][28]\,
      DIADI(24) => \shifted_data_in_reg_n_0_[8][27]\,
      DIADI(23) => \shifted_data_in_reg_n_0_[8][25]\,
      DIADI(22) => \shifted_data_in_reg_n_0_[8][24]\,
      DIADI(21) => \shifted_data_in_reg_n_0_[8][23]\,
      DIADI(20) => \shifted_data_in_reg_n_0_[8][22]\,
      DIADI(19) => \shifted_data_in_reg_n_0_[8][21]\,
      DIADI(18) => \shifted_data_in_reg_n_0_[8][20]\,
      DIADI(17) => \shifted_data_in_reg_n_0_[8][19]\,
      DIADI(16) => \shifted_data_in_reg_n_0_[8][18]\,
      DIADI(15) => \shifted_data_in_reg_n_0_[8][16]\,
      DIADI(14) => \shifted_data_in_reg_n_0_[8][15]\,
      DIADI(13) => \shifted_data_in_reg_n_0_[8][14]\,
      DIADI(12) => \shifted_data_in_reg_n_0_[8][13]\,
      DIADI(11) => \shifted_data_in_reg_n_0_[8][12]\,
      DIADI(10) => \shifted_data_in_reg_n_0_[8][11]\,
      DIADI(9) => \shifted_data_in_reg_n_0_[8][10]\,
      DIADI(8) => \shifted_data_in_reg_n_0_[8][9]\,
      DIADI(7) => \shifted_data_in_reg_n_0_[8][7]\,
      DIADI(6) => \shifted_data_in_reg_n_0_[8][6]\,
      DIADI(5) => \shifted_data_in_reg_n_0_[8][5]\,
      DIADI(4) => \shifted_data_in_reg_n_0_[8][4]\,
      DIADI(3) => \shifted_data_in_reg_n_0_[8][3]\,
      DIADI(2) => \shifted_data_in_reg_n_0_[8][2]\,
      DIADI(1) => \shifted_data_in_reg_n_0_[8][1]\,
      DIADI(0) => \shifted_data_in_reg_n_0_[8][0]\,
      DIPADIP(3) => \shifted_data_in_reg_n_0_[8][35]\,
      DIPADIP(2) => \shifted_data_in_reg_n_0_[8][26]\,
      DIPADIP(1) => \shifted_data_in_reg_n_0_[8][17]\,
      DIPADIP(0) => \shifted_data_in_reg_n_0_[8][8]\,
      Q(9 downto 0) => trace_read_addr(9 downto 0),
      \out\ => cap_wr_en,
      s_dclk_o => s_dclk
    );
\probeDelay1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(0),
      I1 => probe0(0),
      I2 => use_probe_debug_circuit,
      O => probe_data(0)
    );
\probeDelay1[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(10),
      I1 => probe0(10),
      I2 => use_probe_debug_circuit,
      O => probe_data(10)
    );
\probeDelay1[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(11),
      I1 => probe0(11),
      I2 => use_probe_debug_circuit,
      O => probe_data(11)
    );
\probeDelay1[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(12),
      I1 => probe0(12),
      I2 => use_probe_debug_circuit,
      O => probe_data(12)
    );
\probeDelay1[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(13),
      I1 => probe0(13),
      I2 => use_probe_debug_circuit,
      O => probe_data(13)
    );
\probeDelay1[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(14),
      I1 => probe0(14),
      I2 => use_probe_debug_circuit,
      O => probe_data(14)
    );
\probeDelay1[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(15),
      I1 => probe0(15),
      I2 => use_probe_debug_circuit,
      O => probe_data(15)
    );
\probeDelay1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(1),
      I1 => probe0(1),
      I2 => use_probe_debug_circuit,
      O => probe_data(1)
    );
\probeDelay1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(2),
      I1 => probe0(2),
      I2 => use_probe_debug_circuit,
      O => probe_data(2)
    );
\probeDelay1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(3),
      I1 => probe0(3),
      I2 => use_probe_debug_circuit,
      O => probe_data(3)
    );
\probeDelay1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(4),
      I1 => probe0(4),
      I2 => use_probe_debug_circuit,
      O => probe_data(4)
    );
\probeDelay1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(5),
      I1 => probe0(5),
      I2 => use_probe_debug_circuit,
      O => probe_data(5)
    );
\probeDelay1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(6),
      I1 => probe0(6),
      I2 => use_probe_debug_circuit,
      O => probe_data(6)
    );
\probeDelay1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(7),
      I1 => probe0(7),
      I2 => use_probe_debug_circuit,
      O => probe_data(7)
    );
\probeDelay1[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(8),
      I1 => probe0(8),
      I2 => use_probe_debug_circuit,
      O => probe_data(8)
    );
\probeDelay1[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => debug_data_in_sync2(9),
      I1 => probe0(9),
      I2 => use_probe_debug_circuit,
      O => probe_data(9)
    );
\shifted_data_in_reg[7][0]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(0),
      Q => \shifted_data_in_reg[7][0]_srl8_n_0\
    );
\shifted_data_in_reg[7][100]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(26),
      Q => \shifted_data_in_reg[7][100]_srl8_n_0\
    );
\shifted_data_in_reg[7][101]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(27),
      Q => \shifted_data_in_reg[7][101]_srl8_n_0\
    );
\shifted_data_in_reg[7][102]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(28),
      Q => \shifted_data_in_reg[7][102]_srl8_n_0\
    );
\shifted_data_in_reg[7][103]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(29),
      Q => \shifted_data_in_reg[7][103]_srl8_n_0\
    );
\shifted_data_in_reg[7][104]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(30),
      Q => \shifted_data_in_reg[7][104]_srl8_n_0\
    );
\shifted_data_in_reg[7][105]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(31),
      Q => \shifted_data_in_reg[7][105]_srl8_n_0\
    );
\shifted_data_in_reg[7][106]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(0),
      Q => \shifted_data_in_reg[7][106]_srl8_n_0\
    );
\shifted_data_in_reg[7][107]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(1),
      Q => \shifted_data_in_reg[7][107]_srl8_n_0\
    );
\shifted_data_in_reg[7][108]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(2),
      Q => \shifted_data_in_reg[7][108]_srl8_n_0\
    );
\shifted_data_in_reg[7][109]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(3),
      Q => \shifted_data_in_reg[7][109]_srl8_n_0\
    );
\shifted_data_in_reg[7][10]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(10),
      Q => \shifted_data_in_reg[7][10]_srl8_n_0\
    );
\shifted_data_in_reg[7][110]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(4),
      Q => \shifted_data_in_reg[7][110]_srl8_n_0\
    );
\shifted_data_in_reg[7][111]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(5),
      Q => \shifted_data_in_reg[7][111]_srl8_n_0\
    );
\shifted_data_in_reg[7][112]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(6),
      Q => \shifted_data_in_reg[7][112]_srl8_n_0\
    );
\shifted_data_in_reg[7][113]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(7),
      Q => \shifted_data_in_reg[7][113]_srl8_n_0\
    );
\shifted_data_in_reg[7][114]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(8),
      Q => \shifted_data_in_reg[7][114]_srl8_n_0\
    );
\shifted_data_in_reg[7][115]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(9),
      Q => \shifted_data_in_reg[7][115]_srl8_n_0\
    );
\shifted_data_in_reg[7][116]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(10),
      Q => \shifted_data_in_reg[7][116]_srl8_n_0\
    );
\shifted_data_in_reg[7][117]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(11),
      Q => \shifted_data_in_reg[7][117]_srl8_n_0\
    );
\shifted_data_in_reg[7][118]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(12),
      Q => \shifted_data_in_reg[7][118]_srl8_n_0\
    );
\shifted_data_in_reg[7][119]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(13),
      Q => \shifted_data_in_reg[7][119]_srl8_n_0\
    );
\shifted_data_in_reg[7][11]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(11),
      Q => \shifted_data_in_reg[7][11]_srl8_n_0\
    );
\shifted_data_in_reg[7][120]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(14),
      Q => \shifted_data_in_reg[7][120]_srl8_n_0\
    );
\shifted_data_in_reg[7][121]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(15),
      Q => \shifted_data_in_reg[7][121]_srl8_n_0\
    );
\shifted_data_in_reg[7][122]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(16),
      Q => \shifted_data_in_reg[7][122]_srl8_n_0\
    );
\shifted_data_in_reg[7][123]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(17),
      Q => \shifted_data_in_reg[7][123]_srl8_n_0\
    );
\shifted_data_in_reg[7][124]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(18),
      Q => \shifted_data_in_reg[7][124]_srl8_n_0\
    );
\shifted_data_in_reg[7][125]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(19),
      Q => \shifted_data_in_reg[7][125]_srl8_n_0\
    );
\shifted_data_in_reg[7][126]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(20),
      Q => \shifted_data_in_reg[7][126]_srl8_n_0\
    );
\shifted_data_in_reg[7][127]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(21),
      Q => \shifted_data_in_reg[7][127]_srl8_n_0\
    );
\shifted_data_in_reg[7][128]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(22),
      Q => \shifted_data_in_reg[7][128]_srl8_n_0\
    );
\shifted_data_in_reg[7][129]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(23),
      Q => \shifted_data_in_reg[7][129]_srl8_n_0\
    );
\shifted_data_in_reg[7][12]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(12),
      Q => \shifted_data_in_reg[7][12]_srl8_n_0\
    );
\shifted_data_in_reg[7][130]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(24),
      Q => \shifted_data_in_reg[7][130]_srl8_n_0\
    );
\shifted_data_in_reg[7][131]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(25),
      Q => \shifted_data_in_reg[7][131]_srl8_n_0\
    );
\shifted_data_in_reg[7][132]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(26),
      Q => \shifted_data_in_reg[7][132]_srl8_n_0\
    );
\shifted_data_in_reg[7][133]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(27),
      Q => \shifted_data_in_reg[7][133]_srl8_n_0\
    );
\shifted_data_in_reg[7][134]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(28),
      Q => \shifted_data_in_reg[7][134]_srl8_n_0\
    );
\shifted_data_in_reg[7][135]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(29),
      Q => \shifted_data_in_reg[7][135]_srl8_n_0\
    );
\shifted_data_in_reg[7][136]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(30),
      Q => \shifted_data_in_reg[7][136]_srl8_n_0\
    );
\shifted_data_in_reg[7][137]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe5(31),
      Q => \shifted_data_in_reg[7][137]_srl8_n_0\
    );
\shifted_data_in_reg[7][13]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(13),
      Q => \shifted_data_in_reg[7][13]_srl8_n_0\
    );
\shifted_data_in_reg[7][14]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(14),
      Q => \shifted_data_in_reg[7][14]_srl8_n_0\
    );
\shifted_data_in_reg[7][15]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(15),
      Q => \shifted_data_in_reg[7][15]_srl8_n_0\
    );
\shifted_data_in_reg[7][16]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(16),
      Q => \shifted_data_in_reg[7][16]_srl8_n_0\
    );
\shifted_data_in_reg[7][17]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(17),
      Q => \shifted_data_in_reg[7][17]_srl8_n_0\
    );
\shifted_data_in_reg[7][18]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(18),
      Q => \shifted_data_in_reg[7][18]_srl8_n_0\
    );
\shifted_data_in_reg[7][19]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(19),
      Q => \shifted_data_in_reg[7][19]_srl8_n_0\
    );
\shifted_data_in_reg[7][1]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(1),
      Q => \shifted_data_in_reg[7][1]_srl8_n_0\
    );
\shifted_data_in_reg[7][20]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(20),
      Q => \shifted_data_in_reg[7][20]_srl8_n_0\
    );
\shifted_data_in_reg[7][21]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(21),
      Q => \shifted_data_in_reg[7][21]_srl8_n_0\
    );
\shifted_data_in_reg[7][22]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(22),
      Q => \shifted_data_in_reg[7][22]_srl8_n_0\
    );
\shifted_data_in_reg[7][23]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(23),
      Q => \shifted_data_in_reg[7][23]_srl8_n_0\
    );
\shifted_data_in_reg[7][24]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(24),
      Q => \shifted_data_in_reg[7][24]_srl8_n_0\
    );
\shifted_data_in_reg[7][25]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(25),
      Q => \shifted_data_in_reg[7][25]_srl8_n_0\
    );
\shifted_data_in_reg[7][26]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(26),
      Q => \shifted_data_in_reg[7][26]_srl8_n_0\
    );
\shifted_data_in_reg[7][27]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(27),
      Q => \shifted_data_in_reg[7][27]_srl8_n_0\
    );
\shifted_data_in_reg[7][28]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(28),
      Q => \shifted_data_in_reg[7][28]_srl8_n_0\
    );
\shifted_data_in_reg[7][29]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(29),
      Q => \shifted_data_in_reg[7][29]_srl8_n_0\
    );
\shifted_data_in_reg[7][2]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(2),
      Q => \shifted_data_in_reg[7][2]_srl8_n_0\
    );
\shifted_data_in_reg[7][30]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(30),
      Q => \shifted_data_in_reg[7][30]_srl8_n_0\
    );
\shifted_data_in_reg[7][31]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(31),
      Q => \shifted_data_in_reg[7][31]_srl8_n_0\
    );
\shifted_data_in_reg[7][32]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(32),
      Q => \shifted_data_in_reg[7][32]_srl8_n_0\
    );
\shifted_data_in_reg[7][33]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(33),
      Q => \shifted_data_in_reg[7][33]_srl8_n_0\
    );
\shifted_data_in_reg[7][34]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(34),
      Q => \shifted_data_in_reg[7][34]_srl8_n_0\
    );
\shifted_data_in_reg[7][35]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(35),
      Q => \shifted_data_in_reg[7][35]_srl8_n_0\
    );
\shifted_data_in_reg[7][36]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(36),
      Q => \shifted_data_in_reg[7][36]_srl8_n_0\
    );
\shifted_data_in_reg[7][37]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(37),
      Q => \shifted_data_in_reg[7][37]_srl8_n_0\
    );
\shifted_data_in_reg[7][38]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(38),
      Q => \shifted_data_in_reg[7][38]_srl8_n_0\
    );
\shifted_data_in_reg[7][39]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(39),
      Q => \shifted_data_in_reg[7][39]_srl8_n_0\
    );
\shifted_data_in_reg[7][3]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(3),
      Q => \shifted_data_in_reg[7][3]_srl8_n_0\
    );
\shifted_data_in_reg[7][40]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(40),
      Q => \shifted_data_in_reg[7][40]_srl8_n_0\
    );
\shifted_data_in_reg[7][41]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(41),
      Q => \shifted_data_in_reg[7][41]_srl8_n_0\
    );
\shifted_data_in_reg[7][42]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(42),
      Q => \shifted_data_in_reg[7][42]_srl8_n_0\
    );
\shifted_data_in_reg[7][43]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(43),
      Q => \shifted_data_in_reg[7][43]_srl8_n_0\
    );
\shifted_data_in_reg[7][44]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(44),
      Q => \shifted_data_in_reg[7][44]_srl8_n_0\
    );
\shifted_data_in_reg[7][45]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(45),
      Q => \shifted_data_in_reg[7][45]_srl8_n_0\
    );
\shifted_data_in_reg[7][46]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(46),
      Q => \shifted_data_in_reg[7][46]_srl8_n_0\
    );
\shifted_data_in_reg[7][47]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(47),
      Q => \shifted_data_in_reg[7][47]_srl8_n_0\
    );
\shifted_data_in_reg[7][48]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(48),
      Q => \shifted_data_in_reg[7][48]_srl8_n_0\
    );
\shifted_data_in_reg[7][49]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(49),
      Q => \shifted_data_in_reg[7][49]_srl8_n_0\
    );
\shifted_data_in_reg[7][4]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(4),
      Q => \shifted_data_in_reg[7][4]_srl8_n_0\
    );
\shifted_data_in_reg[7][50]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(50),
      Q => \shifted_data_in_reg[7][50]_srl8_n_0\
    );
\shifted_data_in_reg[7][51]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(51),
      Q => \shifted_data_in_reg[7][51]_srl8_n_0\
    );
\shifted_data_in_reg[7][52]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(52),
      Q => \shifted_data_in_reg[7][52]_srl8_n_0\
    );
\shifted_data_in_reg[7][53]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(53),
      Q => \shifted_data_in_reg[7][53]_srl8_n_0\
    );
\shifted_data_in_reg[7][54]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(54),
      Q => \shifted_data_in_reg[7][54]_srl8_n_0\
    );
\shifted_data_in_reg[7][55]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(55),
      Q => \shifted_data_in_reg[7][55]_srl8_n_0\
    );
\shifted_data_in_reg[7][56]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(56),
      Q => \shifted_data_in_reg[7][56]_srl8_n_0\
    );
\shifted_data_in_reg[7][57]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(57),
      Q => \shifted_data_in_reg[7][57]_srl8_n_0\
    );
\shifted_data_in_reg[7][58]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(58),
      Q => \shifted_data_in_reg[7][58]_srl8_n_0\
    );
\shifted_data_in_reg[7][59]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(59),
      Q => \shifted_data_in_reg[7][59]_srl8_n_0\
    );
\shifted_data_in_reg[7][5]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(5),
      Q => \shifted_data_in_reg[7][5]_srl8_n_0\
    );
\shifted_data_in_reg[7][60]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(60),
      Q => \shifted_data_in_reg[7][60]_srl8_n_0\
    );
\shifted_data_in_reg[7][61]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(61),
      Q => \shifted_data_in_reg[7][61]_srl8_n_0\
    );
\shifted_data_in_reg[7][62]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(62),
      Q => \shifted_data_in_reg[7][62]_srl8_n_0\
    );
\shifted_data_in_reg[7][63]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(63),
      Q => \shifted_data_in_reg[7][63]_srl8_n_0\
    );
\shifted_data_in_reg[7][64]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe1(0),
      Q => \shifted_data_in_reg[7][64]_srl8_n_0\
    );
\shifted_data_in_reg[7][65]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe2(0),
      Q => \shifted_data_in_reg[7][65]_srl8_n_0\
    );
\shifted_data_in_reg[7][66]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(0),
      Q => \shifted_data_in_reg[7][66]_srl8_n_0\
    );
\shifted_data_in_reg[7][67]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(1),
      Q => \shifted_data_in_reg[7][67]_srl8_n_0\
    );
\shifted_data_in_reg[7][68]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(2),
      Q => \shifted_data_in_reg[7][68]_srl8_n_0\
    );
\shifted_data_in_reg[7][69]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(3),
      Q => \shifted_data_in_reg[7][69]_srl8_n_0\
    );
\shifted_data_in_reg[7][6]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(6),
      Q => \shifted_data_in_reg[7][6]_srl8_n_0\
    );
\shifted_data_in_reg[7][70]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(4),
      Q => \shifted_data_in_reg[7][70]_srl8_n_0\
    );
\shifted_data_in_reg[7][71]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(5),
      Q => \shifted_data_in_reg[7][71]_srl8_n_0\
    );
\shifted_data_in_reg[7][72]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(6),
      Q => \shifted_data_in_reg[7][72]_srl8_n_0\
    );
\shifted_data_in_reg[7][73]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe3(7),
      Q => \shifted_data_in_reg[7][73]_srl8_n_0\
    );
\shifted_data_in_reg[7][74]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(0),
      Q => \shifted_data_in_reg[7][74]_srl8_n_0\
    );
\shifted_data_in_reg[7][75]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(1),
      Q => \shifted_data_in_reg[7][75]_srl8_n_0\
    );
\shifted_data_in_reg[7][76]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(2),
      Q => \shifted_data_in_reg[7][76]_srl8_n_0\
    );
\shifted_data_in_reg[7][77]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(3),
      Q => \shifted_data_in_reg[7][77]_srl8_n_0\
    );
\shifted_data_in_reg[7][78]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(4),
      Q => \shifted_data_in_reg[7][78]_srl8_n_0\
    );
\shifted_data_in_reg[7][79]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(5),
      Q => \shifted_data_in_reg[7][79]_srl8_n_0\
    );
\shifted_data_in_reg[7][7]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(7),
      Q => \shifted_data_in_reg[7][7]_srl8_n_0\
    );
\shifted_data_in_reg[7][80]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(6),
      Q => \shifted_data_in_reg[7][80]_srl8_n_0\
    );
\shifted_data_in_reg[7][81]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(7),
      Q => \shifted_data_in_reg[7][81]_srl8_n_0\
    );
\shifted_data_in_reg[7][82]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(8),
      Q => \shifted_data_in_reg[7][82]_srl8_n_0\
    );
\shifted_data_in_reg[7][83]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(9),
      Q => \shifted_data_in_reg[7][83]_srl8_n_0\
    );
\shifted_data_in_reg[7][84]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(10),
      Q => \shifted_data_in_reg[7][84]_srl8_n_0\
    );
\shifted_data_in_reg[7][85]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(11),
      Q => \shifted_data_in_reg[7][85]_srl8_n_0\
    );
\shifted_data_in_reg[7][86]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(12),
      Q => \shifted_data_in_reg[7][86]_srl8_n_0\
    );
\shifted_data_in_reg[7][87]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(13),
      Q => \shifted_data_in_reg[7][87]_srl8_n_0\
    );
\shifted_data_in_reg[7][88]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(14),
      Q => \shifted_data_in_reg[7][88]_srl8_n_0\
    );
\shifted_data_in_reg[7][89]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(15),
      Q => \shifted_data_in_reg[7][89]_srl8_n_0\
    );
\shifted_data_in_reg[7][8]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(8),
      Q => \shifted_data_in_reg[7][8]_srl8_n_0\
    );
\shifted_data_in_reg[7][90]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(16),
      Q => \shifted_data_in_reg[7][90]_srl8_n_0\
    );
\shifted_data_in_reg[7][91]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(17),
      Q => \shifted_data_in_reg[7][91]_srl8_n_0\
    );
\shifted_data_in_reg[7][92]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(18),
      Q => \shifted_data_in_reg[7][92]_srl8_n_0\
    );
\shifted_data_in_reg[7][93]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(19),
      Q => \shifted_data_in_reg[7][93]_srl8_n_0\
    );
\shifted_data_in_reg[7][94]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(20),
      Q => \shifted_data_in_reg[7][94]_srl8_n_0\
    );
\shifted_data_in_reg[7][95]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(21),
      Q => \shifted_data_in_reg[7][95]_srl8_n_0\
    );
\shifted_data_in_reg[7][96]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(22),
      Q => \shifted_data_in_reg[7][96]_srl8_n_0\
    );
\shifted_data_in_reg[7][97]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(23),
      Q => \shifted_data_in_reg[7][97]_srl8_n_0\
    );
\shifted_data_in_reg[7][98]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(24),
      Q => \shifted_data_in_reg[7][98]_srl8_n_0\
    );
\shifted_data_in_reg[7][99]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe4(25),
      Q => \shifted_data_in_reg[7][99]_srl8_n_0\
    );
\shifted_data_in_reg[7][9]_srl8\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      D => probe0(9),
      Q => \shifted_data_in_reg[7][9]_srl8_n_0\
    );
\shifted_data_in_reg[8][0]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][0]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][0]\,
      R => '0'
    );
\shifted_data_in_reg[8][100]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][100]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][100]\,
      R => '0'
    );
\shifted_data_in_reg[8][101]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][101]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][101]\,
      R => '0'
    );
\shifted_data_in_reg[8][102]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][102]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][102]\,
      R => '0'
    );
\shifted_data_in_reg[8][103]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][103]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][103]\,
      R => '0'
    );
\shifted_data_in_reg[8][104]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][104]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][104]\,
      R => '0'
    );
\shifted_data_in_reg[8][105]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][105]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][105]\,
      R => '0'
    );
\shifted_data_in_reg[8][106]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][106]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][106]\,
      R => '0'
    );
\shifted_data_in_reg[8][107]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][107]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][107]\,
      R => '0'
    );
\shifted_data_in_reg[8][108]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][108]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][108]\,
      R => '0'
    );
\shifted_data_in_reg[8][109]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][109]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][109]\,
      R => '0'
    );
\shifted_data_in_reg[8][10]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][10]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][10]\,
      R => '0'
    );
\shifted_data_in_reg[8][110]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][110]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][110]\,
      R => '0'
    );
\shifted_data_in_reg[8][111]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][111]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][111]\,
      R => '0'
    );
\shifted_data_in_reg[8][112]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][112]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][112]\,
      R => '0'
    );
\shifted_data_in_reg[8][113]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][113]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][113]\,
      R => '0'
    );
\shifted_data_in_reg[8][114]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][114]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][114]\,
      R => '0'
    );
\shifted_data_in_reg[8][115]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][115]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][115]\,
      R => '0'
    );
\shifted_data_in_reg[8][116]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][116]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][116]\,
      R => '0'
    );
\shifted_data_in_reg[8][117]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][117]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][117]\,
      R => '0'
    );
\shifted_data_in_reg[8][118]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][118]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][118]\,
      R => '0'
    );
\shifted_data_in_reg[8][119]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][119]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][119]\,
      R => '0'
    );
\shifted_data_in_reg[8][11]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][11]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][11]\,
      R => '0'
    );
\shifted_data_in_reg[8][120]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][120]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][120]\,
      R => '0'
    );
\shifted_data_in_reg[8][121]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][121]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][121]\,
      R => '0'
    );
\shifted_data_in_reg[8][122]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][122]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][122]\,
      R => '0'
    );
\shifted_data_in_reg[8][123]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][123]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][123]\,
      R => '0'
    );
\shifted_data_in_reg[8][124]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][124]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][124]\,
      R => '0'
    );
\shifted_data_in_reg[8][125]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][125]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][125]\,
      R => '0'
    );
\shifted_data_in_reg[8][126]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][126]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][126]\,
      R => '0'
    );
\shifted_data_in_reg[8][127]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][127]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][127]\,
      R => '0'
    );
\shifted_data_in_reg[8][128]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][128]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][128]\,
      R => '0'
    );
\shifted_data_in_reg[8][129]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][129]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][129]\,
      R => '0'
    );
\shifted_data_in_reg[8][12]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][12]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][12]\,
      R => '0'
    );
\shifted_data_in_reg[8][130]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][130]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][130]\,
      R => '0'
    );
\shifted_data_in_reg[8][131]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][131]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][131]\,
      R => '0'
    );
\shifted_data_in_reg[8][132]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][132]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][132]\,
      R => '0'
    );
\shifted_data_in_reg[8][133]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][133]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][133]\,
      R => '0'
    );
\shifted_data_in_reg[8][134]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][134]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][134]\,
      R => '0'
    );
\shifted_data_in_reg[8][135]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][135]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][135]\,
      R => '0'
    );
\shifted_data_in_reg[8][136]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][136]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][136]\,
      R => '0'
    );
\shifted_data_in_reg[8][137]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][137]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][137]\,
      R => '0'
    );
\shifted_data_in_reg[8][13]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][13]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][13]\,
      R => '0'
    );
\shifted_data_in_reg[8][14]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][14]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][14]\,
      R => '0'
    );
\shifted_data_in_reg[8][15]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][15]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][15]\,
      R => '0'
    );
\shifted_data_in_reg[8][16]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][16]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][16]\,
      R => '0'
    );
\shifted_data_in_reg[8][17]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][17]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][17]\,
      R => '0'
    );
\shifted_data_in_reg[8][18]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][18]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][18]\,
      R => '0'
    );
\shifted_data_in_reg[8][19]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][19]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][19]\,
      R => '0'
    );
\shifted_data_in_reg[8][1]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][1]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][1]\,
      R => '0'
    );
\shifted_data_in_reg[8][20]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][20]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][20]\,
      R => '0'
    );
\shifted_data_in_reg[8][21]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][21]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][21]\,
      R => '0'
    );
\shifted_data_in_reg[8][22]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][22]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][22]\,
      R => '0'
    );
\shifted_data_in_reg[8][23]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][23]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][23]\,
      R => '0'
    );
\shifted_data_in_reg[8][24]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][24]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][24]\,
      R => '0'
    );
\shifted_data_in_reg[8][25]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][25]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][25]\,
      R => '0'
    );
\shifted_data_in_reg[8][26]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][26]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][26]\,
      R => '0'
    );
\shifted_data_in_reg[8][27]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][27]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][27]\,
      R => '0'
    );
\shifted_data_in_reg[8][28]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][28]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][28]\,
      R => '0'
    );
\shifted_data_in_reg[8][29]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][29]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][29]\,
      R => '0'
    );
\shifted_data_in_reg[8][2]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][2]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][2]\,
      R => '0'
    );
\shifted_data_in_reg[8][30]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][30]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][30]\,
      R => '0'
    );
\shifted_data_in_reg[8][31]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][31]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][31]\,
      R => '0'
    );
\shifted_data_in_reg[8][32]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][32]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][32]\,
      R => '0'
    );
\shifted_data_in_reg[8][33]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][33]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][33]\,
      R => '0'
    );
\shifted_data_in_reg[8][34]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][34]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][34]\,
      R => '0'
    );
\shifted_data_in_reg[8][35]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][35]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][35]\,
      R => '0'
    );
\shifted_data_in_reg[8][36]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][36]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][36]\,
      R => '0'
    );
\shifted_data_in_reg[8][37]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][37]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][37]\,
      R => '0'
    );
\shifted_data_in_reg[8][38]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][38]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][38]\,
      R => '0'
    );
\shifted_data_in_reg[8][39]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][39]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][39]\,
      R => '0'
    );
\shifted_data_in_reg[8][3]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][3]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][3]\,
      R => '0'
    );
\shifted_data_in_reg[8][40]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][40]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][40]\,
      R => '0'
    );
\shifted_data_in_reg[8][41]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][41]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][41]\,
      R => '0'
    );
\shifted_data_in_reg[8][42]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][42]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][42]\,
      R => '0'
    );
\shifted_data_in_reg[8][43]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][43]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][43]\,
      R => '0'
    );
\shifted_data_in_reg[8][44]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][44]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][44]\,
      R => '0'
    );
\shifted_data_in_reg[8][45]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][45]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][45]\,
      R => '0'
    );
\shifted_data_in_reg[8][46]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][46]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][46]\,
      R => '0'
    );
\shifted_data_in_reg[8][47]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][47]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][47]\,
      R => '0'
    );
\shifted_data_in_reg[8][48]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][48]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][48]\,
      R => '0'
    );
\shifted_data_in_reg[8][49]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][49]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][49]\,
      R => '0'
    );
\shifted_data_in_reg[8][4]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][4]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][4]\,
      R => '0'
    );
\shifted_data_in_reg[8][50]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][50]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][50]\,
      R => '0'
    );
\shifted_data_in_reg[8][51]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][51]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][51]\,
      R => '0'
    );
\shifted_data_in_reg[8][52]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][52]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][52]\,
      R => '0'
    );
\shifted_data_in_reg[8][53]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][53]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][53]\,
      R => '0'
    );
\shifted_data_in_reg[8][54]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][54]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][54]\,
      R => '0'
    );
\shifted_data_in_reg[8][55]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][55]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][55]\,
      R => '0'
    );
\shifted_data_in_reg[8][56]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][56]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][56]\,
      R => '0'
    );
\shifted_data_in_reg[8][57]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][57]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][57]\,
      R => '0'
    );
\shifted_data_in_reg[8][58]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][58]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][58]\,
      R => '0'
    );
\shifted_data_in_reg[8][59]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][59]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][59]\,
      R => '0'
    );
\shifted_data_in_reg[8][5]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][5]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][5]\,
      R => '0'
    );
\shifted_data_in_reg[8][60]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][60]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][60]\,
      R => '0'
    );
\shifted_data_in_reg[8][61]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][61]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][61]\,
      R => '0'
    );
\shifted_data_in_reg[8][62]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][62]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][62]\,
      R => '0'
    );
\shifted_data_in_reg[8][63]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][63]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][63]\,
      R => '0'
    );
\shifted_data_in_reg[8][64]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][64]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][64]\,
      R => '0'
    );
\shifted_data_in_reg[8][65]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][65]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][65]\,
      R => '0'
    );
\shifted_data_in_reg[8][66]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][66]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][66]\,
      R => '0'
    );
\shifted_data_in_reg[8][67]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][67]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][67]\,
      R => '0'
    );
\shifted_data_in_reg[8][68]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][68]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][68]\,
      R => '0'
    );
\shifted_data_in_reg[8][69]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][69]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][69]\,
      R => '0'
    );
\shifted_data_in_reg[8][6]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][6]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][6]\,
      R => '0'
    );
\shifted_data_in_reg[8][70]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][70]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][70]\,
      R => '0'
    );
\shifted_data_in_reg[8][71]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][71]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][71]\,
      R => '0'
    );
\shifted_data_in_reg[8][72]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][72]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][72]\,
      R => '0'
    );
\shifted_data_in_reg[8][73]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][73]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][73]\,
      R => '0'
    );
\shifted_data_in_reg[8][74]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][74]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][74]\,
      R => '0'
    );
\shifted_data_in_reg[8][75]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][75]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][75]\,
      R => '0'
    );
\shifted_data_in_reg[8][76]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][76]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][76]\,
      R => '0'
    );
\shifted_data_in_reg[8][77]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][77]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][77]\,
      R => '0'
    );
\shifted_data_in_reg[8][78]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][78]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][78]\,
      R => '0'
    );
\shifted_data_in_reg[8][79]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][79]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][79]\,
      R => '0'
    );
\shifted_data_in_reg[8][7]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][7]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][7]\,
      R => '0'
    );
\shifted_data_in_reg[8][80]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][80]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][80]\,
      R => '0'
    );
\shifted_data_in_reg[8][81]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][81]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][81]\,
      R => '0'
    );
\shifted_data_in_reg[8][82]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][82]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][82]\,
      R => '0'
    );
\shifted_data_in_reg[8][83]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][83]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][83]\,
      R => '0'
    );
\shifted_data_in_reg[8][84]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][84]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][84]\,
      R => '0'
    );
\shifted_data_in_reg[8][85]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][85]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][85]\,
      R => '0'
    );
\shifted_data_in_reg[8][86]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][86]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][86]\,
      R => '0'
    );
\shifted_data_in_reg[8][87]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][87]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][87]\,
      R => '0'
    );
\shifted_data_in_reg[8][88]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][88]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][88]\,
      R => '0'
    );
\shifted_data_in_reg[8][89]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][89]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][89]\,
      R => '0'
    );
\shifted_data_in_reg[8][8]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][8]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][8]\,
      R => '0'
    );
\shifted_data_in_reg[8][90]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][90]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][90]\,
      R => '0'
    );
\shifted_data_in_reg[8][91]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][91]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][91]\,
      R => '0'
    );
\shifted_data_in_reg[8][92]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][92]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][92]\,
      R => '0'
    );
\shifted_data_in_reg[8][93]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][93]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][93]\,
      R => '0'
    );
\shifted_data_in_reg[8][94]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][94]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][94]\,
      R => '0'
    );
\shifted_data_in_reg[8][95]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][95]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][95]\,
      R => '0'
    );
\shifted_data_in_reg[8][96]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][96]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][96]\,
      R => '0'
    );
\shifted_data_in_reg[8][97]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][97]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][97]\,
      R => '0'
    );
\shifted_data_in_reg[8][98]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][98]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][98]\,
      R => '0'
    );
\shifted_data_in_reg[8][99]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][99]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][99]\,
      R => '0'
    );
\shifted_data_in_reg[8][9]\: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => \shifted_data_in_reg[7][9]_srl8_n_0\,
      Q => \shifted_data_in_reg_n_0_[8][9]\,
      R => '0'
    );
\trace_data_ack_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk,
      CE => '1',
      D => trace_read_en,
      Q => \trace_data_ack_reg_n_0_[0]\,
      R => '0'
    );
\trace_data_ack_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => s_dclk,
      CE => '1',
      D => \trace_data_ack_reg_n_0_[0]\,
      Q => trace_data_ack(1),
      R => '0'
    );
u_ila_cap_ctrl: entity work.ila_full_aurora_ila_v6_2_10_ila_cap_ctrl_legacy
     port map (
      A(1) => O_reg,
      A(0) => u_ila_cap_ctrl_n_1,
      CAP_DONE_O_reg_0(1) => cap_done,
      CAP_DONE_O_reg_0(0) => cap_trigger_out,
      CAP_WR_EN_O_reg => cap_wr_en,
      D(0) => capture_ctrl_config_cs_serial_input,
      DOUT_O => \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1\,
      E(0) => capture_ctrl_config_en,
      Q(1 downto 0) => reset(1 downto 0),
      basic_trigger => basic_trigger,
      capture_ctrl_config_serial_output => capture_ctrl_config_serial_output,
      \captured_samples_reg[0]\(0) => u_ila_reset_ctrl_n_6,
      \captured_samples_reg[9]\(9 downto 0) => capture_cnt(9 downto 0),
      itrigger_out_reg_0 => en_adv_trigger,
      \out\(9 downto 0) => cap_wr_addr(9 downto 0),
      \probeDelay1_reg[0]\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      s_dclk_o => s_dclk,
      scnt_cmp_temp => \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp\,
      shift_en_reg => \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1\,
      shift_en_reg_0 => \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1\,
      u_scnt_cmp_q(1 downto 0) => capture_qual_ctrl(1 downto 0),
      wcnt_hcmp_temp => \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp\,
      wcnt_lcmp_temp => \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp\
    );
u_ila_regs: entity work.ila_full_aurora_ila_v6_2_10_ila_register
     port map (
      D(0) => capture_ctrl_config_cs_serial_input,
      DOUT_O => \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1\,
      E(0) => data_out_en_1,
      \G_1PIPE_IFACE.s_daddr_r_reg[5]\ => u_ila_regs_n_28,
      Q(0) => curr_read_block(0),
      SR(0) => read_addr_reset,
      arm_ctrl => arm_ctrl,
      capture_ctrl_config_serial_output => capture_ctrl_config_serial_output,
      capture_qual_ctrl_1(1 downto 0) => capture_qual_ctrl_1(1 downto 0),
      \curr_read_block_reg[0]\(0) => u_ila_regs_n_32,
      \current_state_reg[5]\ => xsdb_memory_read_inst_n_3,
      \current_state_reg[5]_0\ => xsdb_memory_read_inst_n_17,
      \current_state_reg[6]\ => xsdb_memory_read_inst_n_18,
      debug_data_in(15 downto 0) => debug_data_in(15 downto 0),
      dummy_temp1_reg_0 => dummy_temp1_reg,
      halt_ctrl => halt_ctrl,
      ila_clk_flag_reg_0 => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      in0 => en_adv_trigger_1,
      mu_config_cs_serial_input(5 downto 0) => mu_config_cs_serial_input(5 downto 0),
      mu_config_cs_serial_output(5 downto 0) => mu_config_cs_serial_output(5 downto 0),
      mu_config_cs_shift_en(5 downto 0) => mu_config_cs_shift_en(5 downto 0),
      next_state(1 downto 0) => next_state(6 downto 5),
      \out\(36 downto 0) => \out\(36 downto 0),
      \parallel_dout_reg[15]\(0) => tc_config_cs_serial_input,
      read_data_en => read_data_en,
      read_en_i_2 => xsdb_memory_read_inst_n_15,
      read_en_i_2_0 => xsdb_memory_read_inst_n_16,
      read_en_i_2_1(0) => next_state(3),
      read_reset_addr(9 downto 0) => read_reset_addr(9 downto 0),
      s_dclk_o => s_dclk,
      scnt_cmp_temp => \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp\,
      shift_en_reg(0) => capture_ctrl_config_en,
      shift_en_reg_0(0) => tc_config_cs_shift_en,
      sl_oport_o(16 downto 0) => sl_oport_o(16 downto 0),
      tc_config_cs_serial_output => tc_config_cs_serial_output,
      u_wcnt_hcmp_q => \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1\,
      u_wcnt_lcmp_q => \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1\,
      use_probe_debug_circuit_1 => use_probe_debug_circuit_1,
      wcnt_hcmp_temp => \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp\,
      wcnt_lcmp_temp => \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp\,
      \xsdb_reg_reg[15]\(15 downto 0) => data_word_out(15 downto 0),
      \xsdb_reg_reg[1]\(1) => O_reg,
      \xsdb_reg_reg[1]\(0) => u_ila_cap_ctrl_n_1,
      \xsdb_reg_reg[3]\(3) => cap_done,
      \xsdb_reg_reg[3]\(2) => cap_trigger_out,
      \xsdb_reg_reg[3]\(1) => halt_status,
      \xsdb_reg_reg[3]\(0) => arm_status,
      \xsdb_reg_reg[9]\(9 downto 0) => capture_cnt(9 downto 0)
    );
u_ila_reset_ctrl: entity work.ila_full_aurora_ila_v6_2_10_ila_reset_ctrl
     port map (
      Q(3) => u_ila_reset_ctrl_n_2,
      Q(2) => reset(3),
      Q(1 downto 0) => reset(1 downto 0),
      arm_ctrl => arm_ctrl,
      dout_reg1_reg(1) => halt_status,
      dout_reg1_reg(0) => arm_status,
      halt_ctrl => halt_ctrl,
      last_din_reg => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      prev_cap_done_reg_0(0) => cap_done,
      \reset_out_reg[0]_0\(0) => u_ila_reset_ctrl_n_6,
      s_dclk_o => s_dclk
    );
u_trig: entity work.ila_full_aurora_ila_v6_2_10_ila_trigger
     port map (
      D(15 downto 0) => probe_data(15 downto 0),
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      Q(2) => u_ila_reset_ctrl_n_2,
      Q(1) => reset(3),
      Q(0) => reset(0),
      TRIGGER_EQ => TRIGGER_EQ,
      mu_config_cs_serial_input(5 downto 0) => mu_config_cs_serial_input(5 downto 0),
      mu_config_cs_serial_output(5 downto 0) => mu_config_cs_serial_output(5 downto 0),
      mu_config_cs_shift_en(5 downto 0) => mu_config_cs_shift_en(5 downto 0),
      \out\ => use_probe_debug_circuit,
      \parallel_dout_reg[15]\(0) => tc_config_cs_shift_en,
      probe0(47 downto 0) => probe0(63 downto 16),
      probe1(0) => probe1(0),
      probe2(0) => probe2(0),
      probe3(7 downto 0) => probe3(7 downto 0),
      probe4(31 downto 0) => probe4(31 downto 0),
      probe5(31 downto 0) => probe5(31 downto 0),
      s_dclk_o => s_dclk,
      shift_en_reg(0) => tc_config_cs_serial_input,
      tc_config_cs_serial_output => tc_config_cs_serial_output
    );
use_probe_debug_circuit_2_reg: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => use_probe_debug_circuit_1,
      Q => use_probe_debug_circuit_2,
      R => '0'
    );
use_probe_debug_circuit_reg: unisim.vcomponents.FDRE
     port map (
      C => \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\,
      CE => '1',
      D => use_probe_debug_circuit_2,
      Q => use_probe_debug_circuit,
      R => '0'
    );
xsdb_memory_read_inst: entity work.ila_full_aurora_ltlib_v1_0_0_generic_memrd
     port map (
      D(0) => trace_read_en,
      E(0) => data_out_en_1,
      Q(9 downto 0) => trace_read_addr(9 downto 0),
      SR(0) => read_addr_reset,
      \curr_read_block_reg[0]_0\(0) => curr_read_block(0),
      \curr_read_block_reg[0]_1\(0) => u_ila_regs_n_32,
      \curr_read_block_reg[2]_0\(15 downto 0) => data_word_out(15 downto 0),
      \curr_read_block_reg[3]_0\ => xsdb_memory_read_inst_n_17,
      \curr_read_block_reg[3]_1\ => xsdb_memory_read_inst_n_18,
      \current_state_reg[0]_0\ => xsdb_memory_read_inst_n_3,
      \current_state_reg[2]_0\(0) => trace_data_ack(1),
      \current_state_reg[3]_0\ => xsdb_memory_read_inst_n_15,
      \current_state_reg[4]_0\ => xsdb_memory_read_inst_n_16,
      \current_state_reg[5]_0\(0) => next_state(3),
      \current_state_reg[6]_0\(1 downto 0) => next_state(6 downto 5),
      \input_data_reg[138]_0\(138 downto 0) => mem_data_out(138 downto 0),
      read_data_en => read_data_en,
      read_en_reg_0 => u_ila_regs_n_28,
      read_reset_addr(9 downto 0) => read_reset_addr(9 downto 0),
      s_dclk_o => s_dclk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora_ila_v6_2_10_ila is
  port (
    clk : in STD_LOGIC;
    clk_nobuf : in STD_LOGIC;
    clkdiv_out : out STD_LOGIC;
    sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
    sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
    trig_in : in STD_LOGIC;
    trig_in_ack : out STD_LOGIC;
    trig_out : out STD_LOGIC;
    trig_out_ack : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe39 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe42 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe45 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe46 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe47 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe48 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe49 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe52 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe53 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe54 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe55 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe56 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe57 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe58 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe59 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe60 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe61 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe62 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe63 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe64 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe65 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe66 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe67 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe68 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe69 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe70 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe71 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe72 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe73 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe74 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe75 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe76 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe77 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe78 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe79 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe80 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe81 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe82 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe83 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe84 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe85 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe86 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe87 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe88 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe89 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe90 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe91 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe92 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe93 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe94 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe95 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe96 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe97 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe98 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe99 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe100 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe101 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe102 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe103 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe104 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe105 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe106 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe107 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe108 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe109 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe110 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe111 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe112 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe113 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe114 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe115 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe116 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe117 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe118 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe119 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe120 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe121 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe122 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe123 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe124 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe125 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe126 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe127 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe128 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe129 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe130 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe131 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe132 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe133 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe134 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe135 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe136 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe137 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe138 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe139 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe140 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe141 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe142 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe143 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe144 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe145 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe146 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe147 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe148 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe149 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe150 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe151 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe152 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe153 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe154 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe155 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe156 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe157 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe158 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe159 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe160 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe161 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe162 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe163 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe164 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe165 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe166 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe167 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe168 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe169 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe170 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe171 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe172 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe173 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe174 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe175 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe176 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe177 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe178 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe179 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe180 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe181 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe182 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe183 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe184 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe185 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe186 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe187 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe188 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe189 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe190 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe191 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe192 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe193 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe194 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe195 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe196 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe197 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe198 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe199 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe200 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe201 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe202 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe203 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe204 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe205 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe206 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe207 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe208 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe209 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe210 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe211 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe212 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe213 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe214 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe215 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe216 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe217 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe218 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe219 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe220 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe221 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe222 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe223 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe224 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe225 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe226 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe227 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe228 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe229 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe230 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe231 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe232 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe233 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe234 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe235 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe236 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe237 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe238 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe239 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe240 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe241 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe242 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe243 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe244 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe245 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe246 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe247 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe248 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe249 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe250 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe251 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe252 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe253 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe254 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe255 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe256 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe257 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe258 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe259 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe260 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe261 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe262 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe263 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe264 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe265 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe266 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe267 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe268 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe269 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe270 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe271 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe272 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe273 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe274 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe275 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe276 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe277 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe278 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe279 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe280 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe281 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe282 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe283 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe284 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe285 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe286 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe287 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe288 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe289 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe290 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe291 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe292 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe293 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe294 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe295 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe296 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe297 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe298 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe299 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe300 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe301 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe302 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe303 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe304 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe305 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe306 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe307 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe308 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe309 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe310 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe311 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe312 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe313 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe314 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe315 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe316 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe317 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe318 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe319 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe320 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe321 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe322 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe323 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe324 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe325 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe326 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe327 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe328 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe329 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe330 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe331 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe332 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe333 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe334 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe335 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe336 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe337 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe338 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe339 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe340 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe341 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe342 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe343 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe344 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe345 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe346 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe347 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe348 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe349 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe350 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe351 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe352 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe353 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe354 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe355 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe356 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe357 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe358 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe359 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe360 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe361 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe362 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe363 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe364 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe365 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe366 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe367 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe368 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe369 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe370 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe371 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe372 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe373 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe374 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe375 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe376 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe377 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe378 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe379 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe380 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe381 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe382 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe383 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe384 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe385 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe386 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe387 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe388 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe389 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe390 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe391 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe392 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe393 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe394 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe395 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe396 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe397 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe398 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe399 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe400 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe401 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe402 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe403 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe404 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe405 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe406 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe407 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe408 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe409 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe410 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe411 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe412 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe413 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe414 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe415 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe416 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe417 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe418 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe419 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe420 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe421 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe422 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe423 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe424 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe425 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe426 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe427 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe428 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe429 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe430 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe431 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe432 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe433 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe434 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe435 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe436 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe437 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe438 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe439 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe440 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe441 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe442 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe443 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe444 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe445 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe446 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe447 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe448 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe449 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe450 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe451 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe452 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe453 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe454 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe455 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe456 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe457 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe458 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe459 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe460 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe461 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe462 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe463 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe464 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe465 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe466 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe467 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe468 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe469 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe470 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe471 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe472 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe473 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe474 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe475 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe476 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe477 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe478 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe479 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe480 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe481 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe482 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe483 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe484 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe485 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe486 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe487 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe488 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe489 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe490 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe491 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe492 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe493 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe494 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe495 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe496 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe497 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe498 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe499 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe500 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe501 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe502 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe503 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe504 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe505 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe506 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe507 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe508 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe509 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe510 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe511 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe512 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe513 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe514 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe515 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe516 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe517 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe518 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe519 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe520 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe521 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe522 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe523 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe524 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe525 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe526 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe527 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe528 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe529 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe530 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe531 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe532 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe533 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe534 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe535 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe536 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe537 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe538 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe539 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe540 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe541 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe542 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe543 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe544 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe545 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe546 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe547 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe548 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe549 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe550 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe551 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe552 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe553 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe554 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe555 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe556 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe557 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe558 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe559 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe560 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe561 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe562 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe563 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe564 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe565 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe566 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe567 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe568 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe569 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe570 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe571 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe572 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe573 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe574 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe575 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe576 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe577 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe578 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe579 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe580 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe581 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe582 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe583 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe584 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe585 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe586 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe587 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe588 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe589 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe590 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe591 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe592 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe593 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe594 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe595 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe596 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe597 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe598 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe599 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe600 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe601 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe602 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe603 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe604 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe605 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe606 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe607 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe608 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe609 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe610 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe611 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe612 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe613 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe614 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe615 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe616 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe617 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe618 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe619 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe620 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe621 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe622 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe623 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe624 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe625 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe626 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe627 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe628 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe629 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe630 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe631 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe632 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe633 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe634 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe635 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe636 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe637 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe638 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe639 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe640 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe641 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe642 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe643 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe644 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe645 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe646 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe647 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe648 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe649 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe650 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe651 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe652 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe653 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe654 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe655 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe656 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe657 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe658 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe659 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe660 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe661 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe662 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe663 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe664 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe665 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe666 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe667 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe668 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe669 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe670 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe671 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe672 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe673 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe674 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe675 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe676 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe677 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe678 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe679 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe680 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe681 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe682 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe683 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe684 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe685 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe686 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe687 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe688 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe689 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe690 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe691 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe692 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe693 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe694 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe695 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe696 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe697 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe698 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe699 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe700 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe701 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe702 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe703 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe704 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe705 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe706 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe707 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe708 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe709 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe710 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe711 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe712 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe713 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe714 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe715 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe716 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe717 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe718 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe719 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe720 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe721 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe722 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe723 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe724 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe725 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe726 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe727 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe728 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe729 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe730 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe731 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe732 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe733 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe734 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe735 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe736 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe737 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe738 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe739 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe740 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe741 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe742 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe743 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe744 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe745 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe746 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe747 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe748 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe749 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe750 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe751 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe752 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe753 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe754 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe755 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe756 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe757 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe758 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe759 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe760 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe761 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe762 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe763 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe764 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe765 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe766 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe767 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe768 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe769 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe770 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe771 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe772 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe773 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe774 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe775 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe776 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe777 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe778 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe779 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe780 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe781 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe782 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe783 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe784 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe785 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe786 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe787 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe788 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe789 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe790 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe791 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe792 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe793 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe794 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe795 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe796 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe797 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe798 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe799 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe800 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe801 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe802 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe803 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe804 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe805 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe806 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe807 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe808 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe809 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe810 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe811 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe812 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe813 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe814 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe815 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe816 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe817 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe818 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe819 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe820 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe821 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe822 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe823 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe824 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe825 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe826 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe827 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe828 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe829 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe830 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe831 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe832 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe833 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe834 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe835 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe836 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe837 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe838 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe839 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe840 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe841 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe842 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe843 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe844 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe845 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe846 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe847 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe848 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe849 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe850 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe851 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe852 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe853 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe854 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe855 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe856 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe857 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe858 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe859 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe860 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe861 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe862 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe863 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe864 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe865 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe866 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe867 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe868 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe869 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe870 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe871 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe872 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe873 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe874 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe875 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe876 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe877 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe878 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe879 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe880 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe881 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe882 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe883 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe884 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe885 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe886 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe887 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe888 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe889 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe890 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe891 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe892 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe893 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe894 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe895 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe896 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe897 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe898 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe899 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe900 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe901 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe902 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe903 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe904 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe905 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe906 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe907 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe908 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe909 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe910 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe911 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe912 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe913 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe914 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe915 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe916 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe917 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe918 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe919 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe920 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe921 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe922 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe923 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe924 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe925 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe926 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe927 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe928 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe929 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe930 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe931 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe932 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe933 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe934 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe935 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe936 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe937 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe938 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe939 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe940 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe941 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe942 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe943 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe944 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe945 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe946 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe947 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe948 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe949 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe950 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe951 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe952 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe953 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe954 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe955 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe956 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe957 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe958 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe959 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe960 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe961 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe962 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe963 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe964 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe965 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe966 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe967 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe968 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe969 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe970 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe971 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe972 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe973 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe974 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe975 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe976 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe977 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe978 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe979 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe980 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe981 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe982 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe983 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe984 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe985 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe986 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe987 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe988 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe989 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe990 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe991 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe992 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe993 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe994 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe995 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe996 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe997 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe998 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe999 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1000 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1001 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1002 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1003 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1004 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1005 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1006 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1007 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1008 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1009 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1010 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1011 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1012 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1013 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1014 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1015 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1016 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1017 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1018 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1019 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1020 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1021 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1022 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe1023 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute C_ADV_TRIGGER : integer;
  attribute C_ADV_TRIGGER of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_BUILD_REVISION : integer;
  attribute C_BUILD_REVISION of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_CAPTURE_TYPE : integer;
  attribute C_CAPTURE_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_CLKFBOUT_MULT_F : string;
  attribute C_CLKFBOUT_MULT_F of ila_full_aurora_ila_v6_2_10_ila : entity is "10.000000";
  attribute C_CLKOUT0_DIVIDE_F : string;
  attribute C_CLKOUT0_DIVIDE_F of ila_full_aurora_ila_v6_2_10_ila : entity is "10.000000";
  attribute C_CLK_FREQ : string;
  attribute C_CLK_FREQ of ila_full_aurora_ila_v6_2_10_ila : entity is "200.000000";
  attribute C_CLK_PERIOD : string;
  attribute C_CLK_PERIOD of ila_full_aurora_ila_v6_2_10_ila : entity is "10.000000";
  attribute C_CORE_INFO1 : integer;
  attribute C_CORE_INFO1 of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_CORE_INFO2 : integer;
  attribute C_CORE_INFO2 of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_CORE_MAJOR_VER : integer;
  attribute C_CORE_MAJOR_VER of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute C_CORE_MINOR_VER : integer;
  attribute C_CORE_MINOR_VER of ila_full_aurora_ila_v6_2_10_ila : entity is 2;
  attribute C_CORE_TYPE : integer;
  attribute C_CORE_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_CSE_DRV_VER : integer;
  attribute C_CSE_DRV_VER of ila_full_aurora_ila_v6_2_10_ila : entity is 2;
  attribute C_DATA_DEPTH : integer;
  attribute C_DATA_DEPTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1024;
  attribute C_DDR_CLK_GEN : integer;
  attribute C_DDR_CLK_GEN of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_DIVCLK_DIVIDE : integer;
  attribute C_DIVCLK_DIVIDE of ila_full_aurora_ila_v6_2_10_ila : entity is 3;
  attribute C_ENABLE_ILA_AXI_MON : integer;
  attribute C_ENABLE_ILA_AXI_MON of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_EN_DDR_ILA : integer;
  attribute C_EN_DDR_ILA of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_EN_STRG_QUAL : integer;
  attribute C_EN_STRG_QUAL of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_EN_TIME_TAG : integer;
  attribute C_EN_TIME_TAG of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_ILA_CLK_FREQ : integer;
  attribute C_ILA_CLK_FREQ of ila_full_aurora_ila_v6_2_10_ila : entity is 2000000;
  attribute C_INPUT_PIPE_STAGES : integer;
  attribute C_INPUT_PIPE_STAGES of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_MAJOR_VERSION : integer;
  attribute C_MAJOR_VERSION of ila_full_aurora_ila_v6_2_10_ila : entity is 2019;
  attribute C_MINOR_VERSION : integer;
  attribute C_MINOR_VERSION of ila_full_aurora_ila_v6_2_10_ila : entity is 2;
  attribute C_MU_TYPE : integer;
  attribute C_MU_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_NEXT_SLAVE : integer;
  attribute C_NEXT_SLAVE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_NUM_MONITOR_SLOTS : integer;
  attribute C_NUM_MONITOR_SLOTS of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_NUM_OF_PROBES : integer;
  attribute C_NUM_OF_PROBES of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute C_PIPE_IFACE : integer;
  attribute C_PIPE_IFACE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE0_MU_CNT : integer;
  attribute C_PROBE0_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE0_TYPE : integer;
  attribute C_PROBE0_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE0_WIDTH : integer;
  attribute C_PROBE0_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 64;
  attribute C_PROBE1000_MU_CNT : integer;
  attribute C_PROBE1000_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1000_TYPE : integer;
  attribute C_PROBE1000_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1000_WIDTH : integer;
  attribute C_PROBE1000_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1001_MU_CNT : integer;
  attribute C_PROBE1001_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1001_TYPE : integer;
  attribute C_PROBE1001_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1001_WIDTH : integer;
  attribute C_PROBE1001_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1002_MU_CNT : integer;
  attribute C_PROBE1002_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1002_TYPE : integer;
  attribute C_PROBE1002_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1002_WIDTH : integer;
  attribute C_PROBE1002_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1003_MU_CNT : integer;
  attribute C_PROBE1003_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1003_TYPE : integer;
  attribute C_PROBE1003_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1003_WIDTH : integer;
  attribute C_PROBE1003_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1004_MU_CNT : integer;
  attribute C_PROBE1004_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1004_TYPE : integer;
  attribute C_PROBE1004_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1004_WIDTH : integer;
  attribute C_PROBE1004_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1005_MU_CNT : integer;
  attribute C_PROBE1005_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1005_TYPE : integer;
  attribute C_PROBE1005_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1005_WIDTH : integer;
  attribute C_PROBE1005_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1006_MU_CNT : integer;
  attribute C_PROBE1006_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1006_TYPE : integer;
  attribute C_PROBE1006_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1006_WIDTH : integer;
  attribute C_PROBE1006_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1007_MU_CNT : integer;
  attribute C_PROBE1007_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1007_TYPE : integer;
  attribute C_PROBE1007_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1007_WIDTH : integer;
  attribute C_PROBE1007_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1008_MU_CNT : integer;
  attribute C_PROBE1008_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1008_TYPE : integer;
  attribute C_PROBE1008_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1008_WIDTH : integer;
  attribute C_PROBE1008_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1009_MU_CNT : integer;
  attribute C_PROBE1009_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1009_TYPE : integer;
  attribute C_PROBE1009_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1009_WIDTH : integer;
  attribute C_PROBE1009_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE100_MU_CNT : integer;
  attribute C_PROBE100_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE100_TYPE : integer;
  attribute C_PROBE100_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE100_WIDTH : integer;
  attribute C_PROBE100_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1010_MU_CNT : integer;
  attribute C_PROBE1010_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1010_TYPE : integer;
  attribute C_PROBE1010_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1010_WIDTH : integer;
  attribute C_PROBE1010_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1011_MU_CNT : integer;
  attribute C_PROBE1011_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1011_TYPE : integer;
  attribute C_PROBE1011_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1011_WIDTH : integer;
  attribute C_PROBE1011_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1012_MU_CNT : integer;
  attribute C_PROBE1012_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1012_TYPE : integer;
  attribute C_PROBE1012_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1012_WIDTH : integer;
  attribute C_PROBE1012_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1013_MU_CNT : integer;
  attribute C_PROBE1013_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1013_TYPE : integer;
  attribute C_PROBE1013_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1013_WIDTH : integer;
  attribute C_PROBE1013_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1014_MU_CNT : integer;
  attribute C_PROBE1014_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1014_TYPE : integer;
  attribute C_PROBE1014_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1014_WIDTH : integer;
  attribute C_PROBE1014_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1015_MU_CNT : integer;
  attribute C_PROBE1015_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1015_TYPE : integer;
  attribute C_PROBE1015_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1015_WIDTH : integer;
  attribute C_PROBE1015_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1016_MU_CNT : integer;
  attribute C_PROBE1016_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1016_TYPE : integer;
  attribute C_PROBE1016_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1016_WIDTH : integer;
  attribute C_PROBE1016_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1017_MU_CNT : integer;
  attribute C_PROBE1017_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1017_TYPE : integer;
  attribute C_PROBE1017_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1017_WIDTH : integer;
  attribute C_PROBE1017_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1018_MU_CNT : integer;
  attribute C_PROBE1018_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1018_TYPE : integer;
  attribute C_PROBE1018_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1018_WIDTH : integer;
  attribute C_PROBE1018_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1019_MU_CNT : integer;
  attribute C_PROBE1019_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1019_TYPE : integer;
  attribute C_PROBE1019_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1019_WIDTH : integer;
  attribute C_PROBE1019_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE101_MU_CNT : integer;
  attribute C_PROBE101_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE101_TYPE : integer;
  attribute C_PROBE101_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE101_WIDTH : integer;
  attribute C_PROBE101_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1020_MU_CNT : integer;
  attribute C_PROBE1020_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1020_TYPE : integer;
  attribute C_PROBE1020_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1020_WIDTH : integer;
  attribute C_PROBE1020_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1021_MU_CNT : integer;
  attribute C_PROBE1021_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1021_TYPE : integer;
  attribute C_PROBE1021_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1021_WIDTH : integer;
  attribute C_PROBE1021_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1022_MU_CNT : integer;
  attribute C_PROBE1022_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1022_TYPE : integer;
  attribute C_PROBE1022_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1022_WIDTH : integer;
  attribute C_PROBE1022_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1023_MU_CNT : integer;
  attribute C_PROBE1023_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1023_TYPE : integer;
  attribute C_PROBE1023_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1023_WIDTH : integer;
  attribute C_PROBE1023_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE102_MU_CNT : integer;
  attribute C_PROBE102_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE102_TYPE : integer;
  attribute C_PROBE102_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE102_WIDTH : integer;
  attribute C_PROBE102_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE103_MU_CNT : integer;
  attribute C_PROBE103_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE103_TYPE : integer;
  attribute C_PROBE103_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE103_WIDTH : integer;
  attribute C_PROBE103_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE104_MU_CNT : integer;
  attribute C_PROBE104_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE104_TYPE : integer;
  attribute C_PROBE104_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE104_WIDTH : integer;
  attribute C_PROBE104_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE105_MU_CNT : integer;
  attribute C_PROBE105_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE105_TYPE : integer;
  attribute C_PROBE105_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE105_WIDTH : integer;
  attribute C_PROBE105_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE106_MU_CNT : integer;
  attribute C_PROBE106_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE106_TYPE : integer;
  attribute C_PROBE106_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE106_WIDTH : integer;
  attribute C_PROBE106_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE107_MU_CNT : integer;
  attribute C_PROBE107_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE107_TYPE : integer;
  attribute C_PROBE107_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE107_WIDTH : integer;
  attribute C_PROBE107_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE108_MU_CNT : integer;
  attribute C_PROBE108_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE108_TYPE : integer;
  attribute C_PROBE108_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE108_WIDTH : integer;
  attribute C_PROBE108_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE109_MU_CNT : integer;
  attribute C_PROBE109_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE109_TYPE : integer;
  attribute C_PROBE109_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE109_WIDTH : integer;
  attribute C_PROBE109_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE10_MU_CNT : integer;
  attribute C_PROBE10_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE10_TYPE : integer;
  attribute C_PROBE10_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE10_WIDTH : integer;
  attribute C_PROBE10_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE110_MU_CNT : integer;
  attribute C_PROBE110_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE110_TYPE : integer;
  attribute C_PROBE110_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE110_WIDTH : integer;
  attribute C_PROBE110_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE111_MU_CNT : integer;
  attribute C_PROBE111_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE111_TYPE : integer;
  attribute C_PROBE111_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE111_WIDTH : integer;
  attribute C_PROBE111_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE112_MU_CNT : integer;
  attribute C_PROBE112_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE112_TYPE : integer;
  attribute C_PROBE112_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE112_WIDTH : integer;
  attribute C_PROBE112_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE113_MU_CNT : integer;
  attribute C_PROBE113_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE113_TYPE : integer;
  attribute C_PROBE113_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE113_WIDTH : integer;
  attribute C_PROBE113_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE114_MU_CNT : integer;
  attribute C_PROBE114_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE114_TYPE : integer;
  attribute C_PROBE114_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE114_WIDTH : integer;
  attribute C_PROBE114_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE115_MU_CNT : integer;
  attribute C_PROBE115_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE115_TYPE : integer;
  attribute C_PROBE115_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE115_WIDTH : integer;
  attribute C_PROBE115_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE116_MU_CNT : integer;
  attribute C_PROBE116_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE116_TYPE : integer;
  attribute C_PROBE116_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE116_WIDTH : integer;
  attribute C_PROBE116_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE117_MU_CNT : integer;
  attribute C_PROBE117_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE117_TYPE : integer;
  attribute C_PROBE117_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE117_WIDTH : integer;
  attribute C_PROBE117_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE118_MU_CNT : integer;
  attribute C_PROBE118_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE118_TYPE : integer;
  attribute C_PROBE118_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE118_WIDTH : integer;
  attribute C_PROBE118_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE119_MU_CNT : integer;
  attribute C_PROBE119_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE119_TYPE : integer;
  attribute C_PROBE119_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE119_WIDTH : integer;
  attribute C_PROBE119_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE11_MU_CNT : integer;
  attribute C_PROBE11_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE11_TYPE : integer;
  attribute C_PROBE11_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE11_WIDTH : integer;
  attribute C_PROBE11_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE120_MU_CNT : integer;
  attribute C_PROBE120_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE120_TYPE : integer;
  attribute C_PROBE120_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE120_WIDTH : integer;
  attribute C_PROBE120_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE121_MU_CNT : integer;
  attribute C_PROBE121_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE121_TYPE : integer;
  attribute C_PROBE121_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE121_WIDTH : integer;
  attribute C_PROBE121_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE122_MU_CNT : integer;
  attribute C_PROBE122_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE122_TYPE : integer;
  attribute C_PROBE122_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE122_WIDTH : integer;
  attribute C_PROBE122_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE123_MU_CNT : integer;
  attribute C_PROBE123_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE123_TYPE : integer;
  attribute C_PROBE123_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE123_WIDTH : integer;
  attribute C_PROBE123_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE124_MU_CNT : integer;
  attribute C_PROBE124_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE124_TYPE : integer;
  attribute C_PROBE124_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE124_WIDTH : integer;
  attribute C_PROBE124_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE125_MU_CNT : integer;
  attribute C_PROBE125_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE125_TYPE : integer;
  attribute C_PROBE125_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE125_WIDTH : integer;
  attribute C_PROBE125_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE126_MU_CNT : integer;
  attribute C_PROBE126_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE126_TYPE : integer;
  attribute C_PROBE126_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE126_WIDTH : integer;
  attribute C_PROBE126_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE127_MU_CNT : integer;
  attribute C_PROBE127_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE127_TYPE : integer;
  attribute C_PROBE127_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE127_WIDTH : integer;
  attribute C_PROBE127_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE128_MU_CNT : integer;
  attribute C_PROBE128_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE128_TYPE : integer;
  attribute C_PROBE128_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE128_WIDTH : integer;
  attribute C_PROBE128_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE129_MU_CNT : integer;
  attribute C_PROBE129_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE129_TYPE : integer;
  attribute C_PROBE129_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE129_WIDTH : integer;
  attribute C_PROBE129_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE12_MU_CNT : integer;
  attribute C_PROBE12_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE12_TYPE : integer;
  attribute C_PROBE12_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE12_WIDTH : integer;
  attribute C_PROBE12_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE130_MU_CNT : integer;
  attribute C_PROBE130_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE130_TYPE : integer;
  attribute C_PROBE130_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE130_WIDTH : integer;
  attribute C_PROBE130_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE131_MU_CNT : integer;
  attribute C_PROBE131_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE131_TYPE : integer;
  attribute C_PROBE131_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE131_WIDTH : integer;
  attribute C_PROBE131_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE132_MU_CNT : integer;
  attribute C_PROBE132_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE132_TYPE : integer;
  attribute C_PROBE132_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE132_WIDTH : integer;
  attribute C_PROBE132_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE133_MU_CNT : integer;
  attribute C_PROBE133_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE133_TYPE : integer;
  attribute C_PROBE133_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE133_WIDTH : integer;
  attribute C_PROBE133_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE134_MU_CNT : integer;
  attribute C_PROBE134_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE134_TYPE : integer;
  attribute C_PROBE134_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE134_WIDTH : integer;
  attribute C_PROBE134_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE135_MU_CNT : integer;
  attribute C_PROBE135_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE135_TYPE : integer;
  attribute C_PROBE135_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE135_WIDTH : integer;
  attribute C_PROBE135_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE136_MU_CNT : integer;
  attribute C_PROBE136_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE136_TYPE : integer;
  attribute C_PROBE136_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE136_WIDTH : integer;
  attribute C_PROBE136_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE137_MU_CNT : integer;
  attribute C_PROBE137_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE137_TYPE : integer;
  attribute C_PROBE137_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE137_WIDTH : integer;
  attribute C_PROBE137_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE138_MU_CNT : integer;
  attribute C_PROBE138_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE138_TYPE : integer;
  attribute C_PROBE138_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE138_WIDTH : integer;
  attribute C_PROBE138_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE139_MU_CNT : integer;
  attribute C_PROBE139_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE139_TYPE : integer;
  attribute C_PROBE139_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE139_WIDTH : integer;
  attribute C_PROBE139_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE13_MU_CNT : integer;
  attribute C_PROBE13_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE13_TYPE : integer;
  attribute C_PROBE13_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE13_WIDTH : integer;
  attribute C_PROBE13_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE140_MU_CNT : integer;
  attribute C_PROBE140_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE140_TYPE : integer;
  attribute C_PROBE140_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE140_WIDTH : integer;
  attribute C_PROBE140_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE141_MU_CNT : integer;
  attribute C_PROBE141_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE141_TYPE : integer;
  attribute C_PROBE141_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE141_WIDTH : integer;
  attribute C_PROBE141_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE142_MU_CNT : integer;
  attribute C_PROBE142_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE142_TYPE : integer;
  attribute C_PROBE142_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE142_WIDTH : integer;
  attribute C_PROBE142_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE143_MU_CNT : integer;
  attribute C_PROBE143_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE143_TYPE : integer;
  attribute C_PROBE143_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE143_WIDTH : integer;
  attribute C_PROBE143_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE144_MU_CNT : integer;
  attribute C_PROBE144_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE144_TYPE : integer;
  attribute C_PROBE144_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE144_WIDTH : integer;
  attribute C_PROBE144_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE145_MU_CNT : integer;
  attribute C_PROBE145_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE145_TYPE : integer;
  attribute C_PROBE145_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE145_WIDTH : integer;
  attribute C_PROBE145_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE146_MU_CNT : integer;
  attribute C_PROBE146_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE146_TYPE : integer;
  attribute C_PROBE146_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE146_WIDTH : integer;
  attribute C_PROBE146_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE147_MU_CNT : integer;
  attribute C_PROBE147_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE147_TYPE : integer;
  attribute C_PROBE147_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE147_WIDTH : integer;
  attribute C_PROBE147_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE148_MU_CNT : integer;
  attribute C_PROBE148_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE148_TYPE : integer;
  attribute C_PROBE148_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE148_WIDTH : integer;
  attribute C_PROBE148_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE149_MU_CNT : integer;
  attribute C_PROBE149_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE149_TYPE : integer;
  attribute C_PROBE149_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE149_WIDTH : integer;
  attribute C_PROBE149_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE14_MU_CNT : integer;
  attribute C_PROBE14_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE14_TYPE : integer;
  attribute C_PROBE14_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE14_WIDTH : integer;
  attribute C_PROBE14_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE150_MU_CNT : integer;
  attribute C_PROBE150_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE150_TYPE : integer;
  attribute C_PROBE150_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE150_WIDTH : integer;
  attribute C_PROBE150_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE151_MU_CNT : integer;
  attribute C_PROBE151_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE151_TYPE : integer;
  attribute C_PROBE151_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE151_WIDTH : integer;
  attribute C_PROBE151_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE152_MU_CNT : integer;
  attribute C_PROBE152_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE152_TYPE : integer;
  attribute C_PROBE152_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE152_WIDTH : integer;
  attribute C_PROBE152_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE153_MU_CNT : integer;
  attribute C_PROBE153_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE153_TYPE : integer;
  attribute C_PROBE153_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE153_WIDTH : integer;
  attribute C_PROBE153_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE154_MU_CNT : integer;
  attribute C_PROBE154_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE154_TYPE : integer;
  attribute C_PROBE154_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE154_WIDTH : integer;
  attribute C_PROBE154_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE155_MU_CNT : integer;
  attribute C_PROBE155_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE155_TYPE : integer;
  attribute C_PROBE155_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE155_WIDTH : integer;
  attribute C_PROBE155_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE156_MU_CNT : integer;
  attribute C_PROBE156_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE156_TYPE : integer;
  attribute C_PROBE156_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE156_WIDTH : integer;
  attribute C_PROBE156_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE157_MU_CNT : integer;
  attribute C_PROBE157_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE157_TYPE : integer;
  attribute C_PROBE157_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE157_WIDTH : integer;
  attribute C_PROBE157_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE158_MU_CNT : integer;
  attribute C_PROBE158_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE158_TYPE : integer;
  attribute C_PROBE158_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE158_WIDTH : integer;
  attribute C_PROBE158_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE159_MU_CNT : integer;
  attribute C_PROBE159_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE159_TYPE : integer;
  attribute C_PROBE159_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE159_WIDTH : integer;
  attribute C_PROBE159_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE15_MU_CNT : integer;
  attribute C_PROBE15_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE15_TYPE : integer;
  attribute C_PROBE15_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE15_WIDTH : integer;
  attribute C_PROBE15_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE160_MU_CNT : integer;
  attribute C_PROBE160_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE160_TYPE : integer;
  attribute C_PROBE160_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE160_WIDTH : integer;
  attribute C_PROBE160_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE161_MU_CNT : integer;
  attribute C_PROBE161_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE161_TYPE : integer;
  attribute C_PROBE161_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE161_WIDTH : integer;
  attribute C_PROBE161_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE162_MU_CNT : integer;
  attribute C_PROBE162_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE162_TYPE : integer;
  attribute C_PROBE162_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE162_WIDTH : integer;
  attribute C_PROBE162_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE163_MU_CNT : integer;
  attribute C_PROBE163_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE163_TYPE : integer;
  attribute C_PROBE163_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE163_WIDTH : integer;
  attribute C_PROBE163_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE164_MU_CNT : integer;
  attribute C_PROBE164_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE164_TYPE : integer;
  attribute C_PROBE164_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE164_WIDTH : integer;
  attribute C_PROBE164_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE165_MU_CNT : integer;
  attribute C_PROBE165_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE165_TYPE : integer;
  attribute C_PROBE165_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE165_WIDTH : integer;
  attribute C_PROBE165_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE166_MU_CNT : integer;
  attribute C_PROBE166_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE166_TYPE : integer;
  attribute C_PROBE166_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE166_WIDTH : integer;
  attribute C_PROBE166_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE167_MU_CNT : integer;
  attribute C_PROBE167_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE167_TYPE : integer;
  attribute C_PROBE167_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE167_WIDTH : integer;
  attribute C_PROBE167_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE168_MU_CNT : integer;
  attribute C_PROBE168_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE168_TYPE : integer;
  attribute C_PROBE168_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE168_WIDTH : integer;
  attribute C_PROBE168_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE169_MU_CNT : integer;
  attribute C_PROBE169_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE169_TYPE : integer;
  attribute C_PROBE169_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE169_WIDTH : integer;
  attribute C_PROBE169_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE16_MU_CNT : integer;
  attribute C_PROBE16_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE16_TYPE : integer;
  attribute C_PROBE16_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE16_WIDTH : integer;
  attribute C_PROBE16_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE170_MU_CNT : integer;
  attribute C_PROBE170_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE170_TYPE : integer;
  attribute C_PROBE170_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE170_WIDTH : integer;
  attribute C_PROBE170_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE171_MU_CNT : integer;
  attribute C_PROBE171_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE171_TYPE : integer;
  attribute C_PROBE171_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE171_WIDTH : integer;
  attribute C_PROBE171_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE172_MU_CNT : integer;
  attribute C_PROBE172_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE172_TYPE : integer;
  attribute C_PROBE172_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE172_WIDTH : integer;
  attribute C_PROBE172_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE173_MU_CNT : integer;
  attribute C_PROBE173_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE173_TYPE : integer;
  attribute C_PROBE173_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE173_WIDTH : integer;
  attribute C_PROBE173_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE174_MU_CNT : integer;
  attribute C_PROBE174_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE174_TYPE : integer;
  attribute C_PROBE174_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE174_WIDTH : integer;
  attribute C_PROBE174_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE175_MU_CNT : integer;
  attribute C_PROBE175_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE175_TYPE : integer;
  attribute C_PROBE175_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE175_WIDTH : integer;
  attribute C_PROBE175_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE176_MU_CNT : integer;
  attribute C_PROBE176_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE176_TYPE : integer;
  attribute C_PROBE176_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE176_WIDTH : integer;
  attribute C_PROBE176_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE177_MU_CNT : integer;
  attribute C_PROBE177_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE177_TYPE : integer;
  attribute C_PROBE177_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE177_WIDTH : integer;
  attribute C_PROBE177_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE178_MU_CNT : integer;
  attribute C_PROBE178_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE178_TYPE : integer;
  attribute C_PROBE178_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE178_WIDTH : integer;
  attribute C_PROBE178_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE179_MU_CNT : integer;
  attribute C_PROBE179_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE179_TYPE : integer;
  attribute C_PROBE179_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE179_WIDTH : integer;
  attribute C_PROBE179_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE17_MU_CNT : integer;
  attribute C_PROBE17_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE17_TYPE : integer;
  attribute C_PROBE17_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE17_WIDTH : integer;
  attribute C_PROBE17_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE180_MU_CNT : integer;
  attribute C_PROBE180_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE180_TYPE : integer;
  attribute C_PROBE180_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE180_WIDTH : integer;
  attribute C_PROBE180_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE181_MU_CNT : integer;
  attribute C_PROBE181_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE181_TYPE : integer;
  attribute C_PROBE181_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE181_WIDTH : integer;
  attribute C_PROBE181_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE182_MU_CNT : integer;
  attribute C_PROBE182_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE182_TYPE : integer;
  attribute C_PROBE182_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE182_WIDTH : integer;
  attribute C_PROBE182_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE183_MU_CNT : integer;
  attribute C_PROBE183_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE183_TYPE : integer;
  attribute C_PROBE183_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE183_WIDTH : integer;
  attribute C_PROBE183_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE184_MU_CNT : integer;
  attribute C_PROBE184_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE184_TYPE : integer;
  attribute C_PROBE184_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE184_WIDTH : integer;
  attribute C_PROBE184_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE185_MU_CNT : integer;
  attribute C_PROBE185_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE185_TYPE : integer;
  attribute C_PROBE185_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE185_WIDTH : integer;
  attribute C_PROBE185_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE186_MU_CNT : integer;
  attribute C_PROBE186_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE186_TYPE : integer;
  attribute C_PROBE186_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE186_WIDTH : integer;
  attribute C_PROBE186_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE187_MU_CNT : integer;
  attribute C_PROBE187_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE187_TYPE : integer;
  attribute C_PROBE187_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE187_WIDTH : integer;
  attribute C_PROBE187_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE188_MU_CNT : integer;
  attribute C_PROBE188_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE188_TYPE : integer;
  attribute C_PROBE188_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE188_WIDTH : integer;
  attribute C_PROBE188_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE189_MU_CNT : integer;
  attribute C_PROBE189_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE189_TYPE : integer;
  attribute C_PROBE189_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE189_WIDTH : integer;
  attribute C_PROBE189_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE18_MU_CNT : integer;
  attribute C_PROBE18_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE18_TYPE : integer;
  attribute C_PROBE18_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE18_WIDTH : integer;
  attribute C_PROBE18_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE190_MU_CNT : integer;
  attribute C_PROBE190_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE190_TYPE : integer;
  attribute C_PROBE190_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE190_WIDTH : integer;
  attribute C_PROBE190_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE191_MU_CNT : integer;
  attribute C_PROBE191_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE191_TYPE : integer;
  attribute C_PROBE191_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE191_WIDTH : integer;
  attribute C_PROBE191_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE192_MU_CNT : integer;
  attribute C_PROBE192_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE192_TYPE : integer;
  attribute C_PROBE192_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE192_WIDTH : integer;
  attribute C_PROBE192_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE193_MU_CNT : integer;
  attribute C_PROBE193_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE193_TYPE : integer;
  attribute C_PROBE193_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE193_WIDTH : integer;
  attribute C_PROBE193_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE194_MU_CNT : integer;
  attribute C_PROBE194_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE194_TYPE : integer;
  attribute C_PROBE194_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE194_WIDTH : integer;
  attribute C_PROBE194_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE195_MU_CNT : integer;
  attribute C_PROBE195_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE195_TYPE : integer;
  attribute C_PROBE195_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE195_WIDTH : integer;
  attribute C_PROBE195_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE196_MU_CNT : integer;
  attribute C_PROBE196_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE196_TYPE : integer;
  attribute C_PROBE196_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE196_WIDTH : integer;
  attribute C_PROBE196_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE197_MU_CNT : integer;
  attribute C_PROBE197_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE197_TYPE : integer;
  attribute C_PROBE197_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE197_WIDTH : integer;
  attribute C_PROBE197_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE198_MU_CNT : integer;
  attribute C_PROBE198_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE198_TYPE : integer;
  attribute C_PROBE198_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE198_WIDTH : integer;
  attribute C_PROBE198_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE199_MU_CNT : integer;
  attribute C_PROBE199_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE199_TYPE : integer;
  attribute C_PROBE199_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE199_WIDTH : integer;
  attribute C_PROBE199_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE19_MU_CNT : integer;
  attribute C_PROBE19_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE19_TYPE : integer;
  attribute C_PROBE19_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE19_WIDTH : integer;
  attribute C_PROBE19_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1_MU_CNT : integer;
  attribute C_PROBE1_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE1_TYPE : integer;
  attribute C_PROBE1_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE1_WIDTH : integer;
  attribute C_PROBE1_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE200_MU_CNT : integer;
  attribute C_PROBE200_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE200_TYPE : integer;
  attribute C_PROBE200_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE200_WIDTH : integer;
  attribute C_PROBE200_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE201_MU_CNT : integer;
  attribute C_PROBE201_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE201_TYPE : integer;
  attribute C_PROBE201_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE201_WIDTH : integer;
  attribute C_PROBE201_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE202_MU_CNT : integer;
  attribute C_PROBE202_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE202_TYPE : integer;
  attribute C_PROBE202_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE202_WIDTH : integer;
  attribute C_PROBE202_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE203_MU_CNT : integer;
  attribute C_PROBE203_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE203_TYPE : integer;
  attribute C_PROBE203_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE203_WIDTH : integer;
  attribute C_PROBE203_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE204_MU_CNT : integer;
  attribute C_PROBE204_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE204_TYPE : integer;
  attribute C_PROBE204_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE204_WIDTH : integer;
  attribute C_PROBE204_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE205_MU_CNT : integer;
  attribute C_PROBE205_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE205_TYPE : integer;
  attribute C_PROBE205_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE205_WIDTH : integer;
  attribute C_PROBE205_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE206_MU_CNT : integer;
  attribute C_PROBE206_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE206_TYPE : integer;
  attribute C_PROBE206_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE206_WIDTH : integer;
  attribute C_PROBE206_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE207_MU_CNT : integer;
  attribute C_PROBE207_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE207_TYPE : integer;
  attribute C_PROBE207_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE207_WIDTH : integer;
  attribute C_PROBE207_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE208_MU_CNT : integer;
  attribute C_PROBE208_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE208_TYPE : integer;
  attribute C_PROBE208_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE208_WIDTH : integer;
  attribute C_PROBE208_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE209_MU_CNT : integer;
  attribute C_PROBE209_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE209_TYPE : integer;
  attribute C_PROBE209_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE209_WIDTH : integer;
  attribute C_PROBE209_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE20_MU_CNT : integer;
  attribute C_PROBE20_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE20_TYPE : integer;
  attribute C_PROBE20_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE20_WIDTH : integer;
  attribute C_PROBE20_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE210_MU_CNT : integer;
  attribute C_PROBE210_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE210_TYPE : integer;
  attribute C_PROBE210_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE210_WIDTH : integer;
  attribute C_PROBE210_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE211_MU_CNT : integer;
  attribute C_PROBE211_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE211_TYPE : integer;
  attribute C_PROBE211_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE211_WIDTH : integer;
  attribute C_PROBE211_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE212_MU_CNT : integer;
  attribute C_PROBE212_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE212_TYPE : integer;
  attribute C_PROBE212_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE212_WIDTH : integer;
  attribute C_PROBE212_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE213_MU_CNT : integer;
  attribute C_PROBE213_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE213_TYPE : integer;
  attribute C_PROBE213_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE213_WIDTH : integer;
  attribute C_PROBE213_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE214_MU_CNT : integer;
  attribute C_PROBE214_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE214_TYPE : integer;
  attribute C_PROBE214_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE214_WIDTH : integer;
  attribute C_PROBE214_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE215_MU_CNT : integer;
  attribute C_PROBE215_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE215_TYPE : integer;
  attribute C_PROBE215_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE215_WIDTH : integer;
  attribute C_PROBE215_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE216_MU_CNT : integer;
  attribute C_PROBE216_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE216_TYPE : integer;
  attribute C_PROBE216_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE216_WIDTH : integer;
  attribute C_PROBE216_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE217_MU_CNT : integer;
  attribute C_PROBE217_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE217_TYPE : integer;
  attribute C_PROBE217_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE217_WIDTH : integer;
  attribute C_PROBE217_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE218_MU_CNT : integer;
  attribute C_PROBE218_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE218_TYPE : integer;
  attribute C_PROBE218_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE218_WIDTH : integer;
  attribute C_PROBE218_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE219_MU_CNT : integer;
  attribute C_PROBE219_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE219_TYPE : integer;
  attribute C_PROBE219_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE219_WIDTH : integer;
  attribute C_PROBE219_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE21_MU_CNT : integer;
  attribute C_PROBE21_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE21_TYPE : integer;
  attribute C_PROBE21_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE21_WIDTH : integer;
  attribute C_PROBE21_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE220_MU_CNT : integer;
  attribute C_PROBE220_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE220_TYPE : integer;
  attribute C_PROBE220_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE220_WIDTH : integer;
  attribute C_PROBE220_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE221_MU_CNT : integer;
  attribute C_PROBE221_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE221_TYPE : integer;
  attribute C_PROBE221_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE221_WIDTH : integer;
  attribute C_PROBE221_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE222_MU_CNT : integer;
  attribute C_PROBE222_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE222_TYPE : integer;
  attribute C_PROBE222_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE222_WIDTH : integer;
  attribute C_PROBE222_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE223_MU_CNT : integer;
  attribute C_PROBE223_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE223_TYPE : integer;
  attribute C_PROBE223_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE223_WIDTH : integer;
  attribute C_PROBE223_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE224_MU_CNT : integer;
  attribute C_PROBE224_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE224_TYPE : integer;
  attribute C_PROBE224_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE224_WIDTH : integer;
  attribute C_PROBE224_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE225_MU_CNT : integer;
  attribute C_PROBE225_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE225_TYPE : integer;
  attribute C_PROBE225_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE225_WIDTH : integer;
  attribute C_PROBE225_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE226_MU_CNT : integer;
  attribute C_PROBE226_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE226_TYPE : integer;
  attribute C_PROBE226_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE226_WIDTH : integer;
  attribute C_PROBE226_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE227_MU_CNT : integer;
  attribute C_PROBE227_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE227_TYPE : integer;
  attribute C_PROBE227_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE227_WIDTH : integer;
  attribute C_PROBE227_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE228_MU_CNT : integer;
  attribute C_PROBE228_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE228_TYPE : integer;
  attribute C_PROBE228_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE228_WIDTH : integer;
  attribute C_PROBE228_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE229_MU_CNT : integer;
  attribute C_PROBE229_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE229_TYPE : integer;
  attribute C_PROBE229_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE229_WIDTH : integer;
  attribute C_PROBE229_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE22_MU_CNT : integer;
  attribute C_PROBE22_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE22_TYPE : integer;
  attribute C_PROBE22_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE22_WIDTH : integer;
  attribute C_PROBE22_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE230_MU_CNT : integer;
  attribute C_PROBE230_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE230_TYPE : integer;
  attribute C_PROBE230_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE230_WIDTH : integer;
  attribute C_PROBE230_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE231_MU_CNT : integer;
  attribute C_PROBE231_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE231_TYPE : integer;
  attribute C_PROBE231_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE231_WIDTH : integer;
  attribute C_PROBE231_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE232_MU_CNT : integer;
  attribute C_PROBE232_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE232_TYPE : integer;
  attribute C_PROBE232_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE232_WIDTH : integer;
  attribute C_PROBE232_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE233_MU_CNT : integer;
  attribute C_PROBE233_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE233_TYPE : integer;
  attribute C_PROBE233_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE233_WIDTH : integer;
  attribute C_PROBE233_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE234_MU_CNT : integer;
  attribute C_PROBE234_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE234_TYPE : integer;
  attribute C_PROBE234_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE234_WIDTH : integer;
  attribute C_PROBE234_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE235_MU_CNT : integer;
  attribute C_PROBE235_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE235_TYPE : integer;
  attribute C_PROBE235_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE235_WIDTH : integer;
  attribute C_PROBE235_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE236_MU_CNT : integer;
  attribute C_PROBE236_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE236_TYPE : integer;
  attribute C_PROBE236_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE236_WIDTH : integer;
  attribute C_PROBE236_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE237_MU_CNT : integer;
  attribute C_PROBE237_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE237_TYPE : integer;
  attribute C_PROBE237_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE237_WIDTH : integer;
  attribute C_PROBE237_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE238_MU_CNT : integer;
  attribute C_PROBE238_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE238_TYPE : integer;
  attribute C_PROBE238_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE238_WIDTH : integer;
  attribute C_PROBE238_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE239_MU_CNT : integer;
  attribute C_PROBE239_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE239_TYPE : integer;
  attribute C_PROBE239_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE239_WIDTH : integer;
  attribute C_PROBE239_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE23_MU_CNT : integer;
  attribute C_PROBE23_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE23_TYPE : integer;
  attribute C_PROBE23_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE23_WIDTH : integer;
  attribute C_PROBE23_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE240_MU_CNT : integer;
  attribute C_PROBE240_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE240_TYPE : integer;
  attribute C_PROBE240_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE240_WIDTH : integer;
  attribute C_PROBE240_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE241_MU_CNT : integer;
  attribute C_PROBE241_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE241_TYPE : integer;
  attribute C_PROBE241_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE241_WIDTH : integer;
  attribute C_PROBE241_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE242_MU_CNT : integer;
  attribute C_PROBE242_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE242_TYPE : integer;
  attribute C_PROBE242_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE242_WIDTH : integer;
  attribute C_PROBE242_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE243_MU_CNT : integer;
  attribute C_PROBE243_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE243_TYPE : integer;
  attribute C_PROBE243_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE243_WIDTH : integer;
  attribute C_PROBE243_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE244_MU_CNT : integer;
  attribute C_PROBE244_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE244_TYPE : integer;
  attribute C_PROBE244_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE244_WIDTH : integer;
  attribute C_PROBE244_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE245_MU_CNT : integer;
  attribute C_PROBE245_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE245_TYPE : integer;
  attribute C_PROBE245_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE245_WIDTH : integer;
  attribute C_PROBE245_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE246_MU_CNT : integer;
  attribute C_PROBE246_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE246_TYPE : integer;
  attribute C_PROBE246_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE246_WIDTH : integer;
  attribute C_PROBE246_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE247_MU_CNT : integer;
  attribute C_PROBE247_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE247_TYPE : integer;
  attribute C_PROBE247_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE247_WIDTH : integer;
  attribute C_PROBE247_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE248_MU_CNT : integer;
  attribute C_PROBE248_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE248_TYPE : integer;
  attribute C_PROBE248_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE248_WIDTH : integer;
  attribute C_PROBE248_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE249_MU_CNT : integer;
  attribute C_PROBE249_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE249_TYPE : integer;
  attribute C_PROBE249_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE249_WIDTH : integer;
  attribute C_PROBE249_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE24_MU_CNT : integer;
  attribute C_PROBE24_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE24_TYPE : integer;
  attribute C_PROBE24_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE24_WIDTH : integer;
  attribute C_PROBE24_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE250_MU_CNT : integer;
  attribute C_PROBE250_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE250_TYPE : integer;
  attribute C_PROBE250_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE250_WIDTH : integer;
  attribute C_PROBE250_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE251_MU_CNT : integer;
  attribute C_PROBE251_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE251_TYPE : integer;
  attribute C_PROBE251_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE251_WIDTH : integer;
  attribute C_PROBE251_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE252_MU_CNT : integer;
  attribute C_PROBE252_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE252_TYPE : integer;
  attribute C_PROBE252_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE252_WIDTH : integer;
  attribute C_PROBE252_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE253_MU_CNT : integer;
  attribute C_PROBE253_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE253_TYPE : integer;
  attribute C_PROBE253_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE253_WIDTH : integer;
  attribute C_PROBE253_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE254_MU_CNT : integer;
  attribute C_PROBE254_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE254_TYPE : integer;
  attribute C_PROBE254_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE254_WIDTH : integer;
  attribute C_PROBE254_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE255_MU_CNT : integer;
  attribute C_PROBE255_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE255_TYPE : integer;
  attribute C_PROBE255_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE255_WIDTH : integer;
  attribute C_PROBE255_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE256_MU_CNT : integer;
  attribute C_PROBE256_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE256_TYPE : integer;
  attribute C_PROBE256_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE256_WIDTH : integer;
  attribute C_PROBE256_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE257_MU_CNT : integer;
  attribute C_PROBE257_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE257_TYPE : integer;
  attribute C_PROBE257_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE257_WIDTH : integer;
  attribute C_PROBE257_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE258_MU_CNT : integer;
  attribute C_PROBE258_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE258_TYPE : integer;
  attribute C_PROBE258_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE258_WIDTH : integer;
  attribute C_PROBE258_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE259_MU_CNT : integer;
  attribute C_PROBE259_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE259_TYPE : integer;
  attribute C_PROBE259_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE259_WIDTH : integer;
  attribute C_PROBE259_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE25_MU_CNT : integer;
  attribute C_PROBE25_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE25_TYPE : integer;
  attribute C_PROBE25_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE25_WIDTH : integer;
  attribute C_PROBE25_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE260_MU_CNT : integer;
  attribute C_PROBE260_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE260_TYPE : integer;
  attribute C_PROBE260_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE260_WIDTH : integer;
  attribute C_PROBE260_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE261_MU_CNT : integer;
  attribute C_PROBE261_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE261_TYPE : integer;
  attribute C_PROBE261_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE261_WIDTH : integer;
  attribute C_PROBE261_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE262_MU_CNT : integer;
  attribute C_PROBE262_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE262_TYPE : integer;
  attribute C_PROBE262_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE262_WIDTH : integer;
  attribute C_PROBE262_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE263_MU_CNT : integer;
  attribute C_PROBE263_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE263_TYPE : integer;
  attribute C_PROBE263_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE263_WIDTH : integer;
  attribute C_PROBE263_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE264_MU_CNT : integer;
  attribute C_PROBE264_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE264_TYPE : integer;
  attribute C_PROBE264_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE264_WIDTH : integer;
  attribute C_PROBE264_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE265_MU_CNT : integer;
  attribute C_PROBE265_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE265_TYPE : integer;
  attribute C_PROBE265_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE265_WIDTH : integer;
  attribute C_PROBE265_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE266_MU_CNT : integer;
  attribute C_PROBE266_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE266_TYPE : integer;
  attribute C_PROBE266_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE266_WIDTH : integer;
  attribute C_PROBE266_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE267_MU_CNT : integer;
  attribute C_PROBE267_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE267_TYPE : integer;
  attribute C_PROBE267_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE267_WIDTH : integer;
  attribute C_PROBE267_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE268_MU_CNT : integer;
  attribute C_PROBE268_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE268_TYPE : integer;
  attribute C_PROBE268_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE268_WIDTH : integer;
  attribute C_PROBE268_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE269_MU_CNT : integer;
  attribute C_PROBE269_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE269_TYPE : integer;
  attribute C_PROBE269_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE269_WIDTH : integer;
  attribute C_PROBE269_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE26_MU_CNT : integer;
  attribute C_PROBE26_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE26_TYPE : integer;
  attribute C_PROBE26_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE26_WIDTH : integer;
  attribute C_PROBE26_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE270_MU_CNT : integer;
  attribute C_PROBE270_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE270_TYPE : integer;
  attribute C_PROBE270_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE270_WIDTH : integer;
  attribute C_PROBE270_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE271_MU_CNT : integer;
  attribute C_PROBE271_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE271_TYPE : integer;
  attribute C_PROBE271_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE271_WIDTH : integer;
  attribute C_PROBE271_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE272_MU_CNT : integer;
  attribute C_PROBE272_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE272_TYPE : integer;
  attribute C_PROBE272_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE272_WIDTH : integer;
  attribute C_PROBE272_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE273_MU_CNT : integer;
  attribute C_PROBE273_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE273_TYPE : integer;
  attribute C_PROBE273_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE273_WIDTH : integer;
  attribute C_PROBE273_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE274_MU_CNT : integer;
  attribute C_PROBE274_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE274_TYPE : integer;
  attribute C_PROBE274_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE274_WIDTH : integer;
  attribute C_PROBE274_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE275_MU_CNT : integer;
  attribute C_PROBE275_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE275_TYPE : integer;
  attribute C_PROBE275_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE275_WIDTH : integer;
  attribute C_PROBE275_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE276_MU_CNT : integer;
  attribute C_PROBE276_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE276_TYPE : integer;
  attribute C_PROBE276_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE276_WIDTH : integer;
  attribute C_PROBE276_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE277_MU_CNT : integer;
  attribute C_PROBE277_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE277_TYPE : integer;
  attribute C_PROBE277_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE277_WIDTH : integer;
  attribute C_PROBE277_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE278_MU_CNT : integer;
  attribute C_PROBE278_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE278_TYPE : integer;
  attribute C_PROBE278_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE278_WIDTH : integer;
  attribute C_PROBE278_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE279_MU_CNT : integer;
  attribute C_PROBE279_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE279_TYPE : integer;
  attribute C_PROBE279_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE279_WIDTH : integer;
  attribute C_PROBE279_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE27_MU_CNT : integer;
  attribute C_PROBE27_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE27_TYPE : integer;
  attribute C_PROBE27_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE27_WIDTH : integer;
  attribute C_PROBE27_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE280_MU_CNT : integer;
  attribute C_PROBE280_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE280_TYPE : integer;
  attribute C_PROBE280_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE280_WIDTH : integer;
  attribute C_PROBE280_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE281_MU_CNT : integer;
  attribute C_PROBE281_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE281_TYPE : integer;
  attribute C_PROBE281_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE281_WIDTH : integer;
  attribute C_PROBE281_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE282_MU_CNT : integer;
  attribute C_PROBE282_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE282_TYPE : integer;
  attribute C_PROBE282_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE282_WIDTH : integer;
  attribute C_PROBE282_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE283_MU_CNT : integer;
  attribute C_PROBE283_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE283_TYPE : integer;
  attribute C_PROBE283_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE283_WIDTH : integer;
  attribute C_PROBE283_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE284_MU_CNT : integer;
  attribute C_PROBE284_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE284_TYPE : integer;
  attribute C_PROBE284_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE284_WIDTH : integer;
  attribute C_PROBE284_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE285_MU_CNT : integer;
  attribute C_PROBE285_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE285_TYPE : integer;
  attribute C_PROBE285_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE285_WIDTH : integer;
  attribute C_PROBE285_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE286_MU_CNT : integer;
  attribute C_PROBE286_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE286_TYPE : integer;
  attribute C_PROBE286_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE286_WIDTH : integer;
  attribute C_PROBE286_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE287_MU_CNT : integer;
  attribute C_PROBE287_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE287_TYPE : integer;
  attribute C_PROBE287_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE287_WIDTH : integer;
  attribute C_PROBE287_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE288_MU_CNT : integer;
  attribute C_PROBE288_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE288_TYPE : integer;
  attribute C_PROBE288_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE288_WIDTH : integer;
  attribute C_PROBE288_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE289_MU_CNT : integer;
  attribute C_PROBE289_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE289_TYPE : integer;
  attribute C_PROBE289_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE289_WIDTH : integer;
  attribute C_PROBE289_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE28_MU_CNT : integer;
  attribute C_PROBE28_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE28_TYPE : integer;
  attribute C_PROBE28_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE28_WIDTH : integer;
  attribute C_PROBE28_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE290_MU_CNT : integer;
  attribute C_PROBE290_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE290_TYPE : integer;
  attribute C_PROBE290_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE290_WIDTH : integer;
  attribute C_PROBE290_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE291_MU_CNT : integer;
  attribute C_PROBE291_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE291_TYPE : integer;
  attribute C_PROBE291_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE291_WIDTH : integer;
  attribute C_PROBE291_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE292_MU_CNT : integer;
  attribute C_PROBE292_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE292_TYPE : integer;
  attribute C_PROBE292_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE292_WIDTH : integer;
  attribute C_PROBE292_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE293_MU_CNT : integer;
  attribute C_PROBE293_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE293_TYPE : integer;
  attribute C_PROBE293_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE293_WIDTH : integer;
  attribute C_PROBE293_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE294_MU_CNT : integer;
  attribute C_PROBE294_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE294_TYPE : integer;
  attribute C_PROBE294_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE294_WIDTH : integer;
  attribute C_PROBE294_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE295_MU_CNT : integer;
  attribute C_PROBE295_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE295_TYPE : integer;
  attribute C_PROBE295_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE295_WIDTH : integer;
  attribute C_PROBE295_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE296_MU_CNT : integer;
  attribute C_PROBE296_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE296_TYPE : integer;
  attribute C_PROBE296_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE296_WIDTH : integer;
  attribute C_PROBE296_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE297_MU_CNT : integer;
  attribute C_PROBE297_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE297_TYPE : integer;
  attribute C_PROBE297_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE297_WIDTH : integer;
  attribute C_PROBE297_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE298_MU_CNT : integer;
  attribute C_PROBE298_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE298_TYPE : integer;
  attribute C_PROBE298_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE298_WIDTH : integer;
  attribute C_PROBE298_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE299_MU_CNT : integer;
  attribute C_PROBE299_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE299_TYPE : integer;
  attribute C_PROBE299_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE299_WIDTH : integer;
  attribute C_PROBE299_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE29_MU_CNT : integer;
  attribute C_PROBE29_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE29_TYPE : integer;
  attribute C_PROBE29_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE29_WIDTH : integer;
  attribute C_PROBE29_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE2_MU_CNT : integer;
  attribute C_PROBE2_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE2_TYPE : integer;
  attribute C_PROBE2_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE2_WIDTH : integer;
  attribute C_PROBE2_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE300_MU_CNT : integer;
  attribute C_PROBE300_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE300_TYPE : integer;
  attribute C_PROBE300_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE300_WIDTH : integer;
  attribute C_PROBE300_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE301_MU_CNT : integer;
  attribute C_PROBE301_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE301_TYPE : integer;
  attribute C_PROBE301_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE301_WIDTH : integer;
  attribute C_PROBE301_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE302_MU_CNT : integer;
  attribute C_PROBE302_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE302_TYPE : integer;
  attribute C_PROBE302_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE302_WIDTH : integer;
  attribute C_PROBE302_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE303_MU_CNT : integer;
  attribute C_PROBE303_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE303_TYPE : integer;
  attribute C_PROBE303_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE303_WIDTH : integer;
  attribute C_PROBE303_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE304_MU_CNT : integer;
  attribute C_PROBE304_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE304_TYPE : integer;
  attribute C_PROBE304_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE304_WIDTH : integer;
  attribute C_PROBE304_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE305_MU_CNT : integer;
  attribute C_PROBE305_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE305_TYPE : integer;
  attribute C_PROBE305_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE305_WIDTH : integer;
  attribute C_PROBE305_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE306_MU_CNT : integer;
  attribute C_PROBE306_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE306_TYPE : integer;
  attribute C_PROBE306_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE306_WIDTH : integer;
  attribute C_PROBE306_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE307_MU_CNT : integer;
  attribute C_PROBE307_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE307_TYPE : integer;
  attribute C_PROBE307_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE307_WIDTH : integer;
  attribute C_PROBE307_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE308_MU_CNT : integer;
  attribute C_PROBE308_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE308_TYPE : integer;
  attribute C_PROBE308_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE308_WIDTH : integer;
  attribute C_PROBE308_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE309_MU_CNT : integer;
  attribute C_PROBE309_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE309_TYPE : integer;
  attribute C_PROBE309_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE309_WIDTH : integer;
  attribute C_PROBE309_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE30_MU_CNT : integer;
  attribute C_PROBE30_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE30_TYPE : integer;
  attribute C_PROBE30_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE30_WIDTH : integer;
  attribute C_PROBE30_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE310_MU_CNT : integer;
  attribute C_PROBE310_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE310_TYPE : integer;
  attribute C_PROBE310_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE310_WIDTH : integer;
  attribute C_PROBE310_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE311_MU_CNT : integer;
  attribute C_PROBE311_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE311_TYPE : integer;
  attribute C_PROBE311_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE311_WIDTH : integer;
  attribute C_PROBE311_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE312_MU_CNT : integer;
  attribute C_PROBE312_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE312_TYPE : integer;
  attribute C_PROBE312_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE312_WIDTH : integer;
  attribute C_PROBE312_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE313_MU_CNT : integer;
  attribute C_PROBE313_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE313_TYPE : integer;
  attribute C_PROBE313_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE313_WIDTH : integer;
  attribute C_PROBE313_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE314_MU_CNT : integer;
  attribute C_PROBE314_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE314_TYPE : integer;
  attribute C_PROBE314_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE314_WIDTH : integer;
  attribute C_PROBE314_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE315_MU_CNT : integer;
  attribute C_PROBE315_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE315_TYPE : integer;
  attribute C_PROBE315_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE315_WIDTH : integer;
  attribute C_PROBE315_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE316_MU_CNT : integer;
  attribute C_PROBE316_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE316_TYPE : integer;
  attribute C_PROBE316_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE316_WIDTH : integer;
  attribute C_PROBE316_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE317_MU_CNT : integer;
  attribute C_PROBE317_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE317_TYPE : integer;
  attribute C_PROBE317_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE317_WIDTH : integer;
  attribute C_PROBE317_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE318_MU_CNT : integer;
  attribute C_PROBE318_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE318_TYPE : integer;
  attribute C_PROBE318_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE318_WIDTH : integer;
  attribute C_PROBE318_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE319_MU_CNT : integer;
  attribute C_PROBE319_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE319_TYPE : integer;
  attribute C_PROBE319_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE319_WIDTH : integer;
  attribute C_PROBE319_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE31_MU_CNT : integer;
  attribute C_PROBE31_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE31_TYPE : integer;
  attribute C_PROBE31_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE31_WIDTH : integer;
  attribute C_PROBE31_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE320_MU_CNT : integer;
  attribute C_PROBE320_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE320_TYPE : integer;
  attribute C_PROBE320_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE320_WIDTH : integer;
  attribute C_PROBE320_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE321_MU_CNT : integer;
  attribute C_PROBE321_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE321_TYPE : integer;
  attribute C_PROBE321_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE321_WIDTH : integer;
  attribute C_PROBE321_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE322_MU_CNT : integer;
  attribute C_PROBE322_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE322_TYPE : integer;
  attribute C_PROBE322_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE322_WIDTH : integer;
  attribute C_PROBE322_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE323_MU_CNT : integer;
  attribute C_PROBE323_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE323_TYPE : integer;
  attribute C_PROBE323_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE323_WIDTH : integer;
  attribute C_PROBE323_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE324_MU_CNT : integer;
  attribute C_PROBE324_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE324_TYPE : integer;
  attribute C_PROBE324_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE324_WIDTH : integer;
  attribute C_PROBE324_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE325_MU_CNT : integer;
  attribute C_PROBE325_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE325_TYPE : integer;
  attribute C_PROBE325_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE325_WIDTH : integer;
  attribute C_PROBE325_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE326_MU_CNT : integer;
  attribute C_PROBE326_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE326_TYPE : integer;
  attribute C_PROBE326_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE326_WIDTH : integer;
  attribute C_PROBE326_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE327_MU_CNT : integer;
  attribute C_PROBE327_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE327_TYPE : integer;
  attribute C_PROBE327_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE327_WIDTH : integer;
  attribute C_PROBE327_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE328_MU_CNT : integer;
  attribute C_PROBE328_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE328_TYPE : integer;
  attribute C_PROBE328_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE328_WIDTH : integer;
  attribute C_PROBE328_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE329_MU_CNT : integer;
  attribute C_PROBE329_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE329_TYPE : integer;
  attribute C_PROBE329_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE329_WIDTH : integer;
  attribute C_PROBE329_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE32_MU_CNT : integer;
  attribute C_PROBE32_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE32_TYPE : integer;
  attribute C_PROBE32_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE32_WIDTH : integer;
  attribute C_PROBE32_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE330_MU_CNT : integer;
  attribute C_PROBE330_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE330_TYPE : integer;
  attribute C_PROBE330_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE330_WIDTH : integer;
  attribute C_PROBE330_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE331_MU_CNT : integer;
  attribute C_PROBE331_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE331_TYPE : integer;
  attribute C_PROBE331_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE331_WIDTH : integer;
  attribute C_PROBE331_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE332_MU_CNT : integer;
  attribute C_PROBE332_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE332_TYPE : integer;
  attribute C_PROBE332_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE332_WIDTH : integer;
  attribute C_PROBE332_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE333_MU_CNT : integer;
  attribute C_PROBE333_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE333_TYPE : integer;
  attribute C_PROBE333_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE333_WIDTH : integer;
  attribute C_PROBE333_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE334_MU_CNT : integer;
  attribute C_PROBE334_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE334_TYPE : integer;
  attribute C_PROBE334_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE334_WIDTH : integer;
  attribute C_PROBE334_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE335_MU_CNT : integer;
  attribute C_PROBE335_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE335_TYPE : integer;
  attribute C_PROBE335_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE335_WIDTH : integer;
  attribute C_PROBE335_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE336_MU_CNT : integer;
  attribute C_PROBE336_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE336_TYPE : integer;
  attribute C_PROBE336_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE336_WIDTH : integer;
  attribute C_PROBE336_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE337_MU_CNT : integer;
  attribute C_PROBE337_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE337_TYPE : integer;
  attribute C_PROBE337_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE337_WIDTH : integer;
  attribute C_PROBE337_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE338_MU_CNT : integer;
  attribute C_PROBE338_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE338_TYPE : integer;
  attribute C_PROBE338_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE338_WIDTH : integer;
  attribute C_PROBE338_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE339_MU_CNT : integer;
  attribute C_PROBE339_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE339_TYPE : integer;
  attribute C_PROBE339_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE339_WIDTH : integer;
  attribute C_PROBE339_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE33_MU_CNT : integer;
  attribute C_PROBE33_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE33_TYPE : integer;
  attribute C_PROBE33_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE33_WIDTH : integer;
  attribute C_PROBE33_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE340_MU_CNT : integer;
  attribute C_PROBE340_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE340_TYPE : integer;
  attribute C_PROBE340_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE340_WIDTH : integer;
  attribute C_PROBE340_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE341_MU_CNT : integer;
  attribute C_PROBE341_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE341_TYPE : integer;
  attribute C_PROBE341_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE341_WIDTH : integer;
  attribute C_PROBE341_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE342_MU_CNT : integer;
  attribute C_PROBE342_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE342_TYPE : integer;
  attribute C_PROBE342_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE342_WIDTH : integer;
  attribute C_PROBE342_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE343_MU_CNT : integer;
  attribute C_PROBE343_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE343_TYPE : integer;
  attribute C_PROBE343_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE343_WIDTH : integer;
  attribute C_PROBE343_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE344_MU_CNT : integer;
  attribute C_PROBE344_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE344_TYPE : integer;
  attribute C_PROBE344_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE344_WIDTH : integer;
  attribute C_PROBE344_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE345_MU_CNT : integer;
  attribute C_PROBE345_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE345_TYPE : integer;
  attribute C_PROBE345_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE345_WIDTH : integer;
  attribute C_PROBE345_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE346_MU_CNT : integer;
  attribute C_PROBE346_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE346_TYPE : integer;
  attribute C_PROBE346_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE346_WIDTH : integer;
  attribute C_PROBE346_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE347_MU_CNT : integer;
  attribute C_PROBE347_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE347_TYPE : integer;
  attribute C_PROBE347_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE347_WIDTH : integer;
  attribute C_PROBE347_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE348_MU_CNT : integer;
  attribute C_PROBE348_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE348_TYPE : integer;
  attribute C_PROBE348_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE348_WIDTH : integer;
  attribute C_PROBE348_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE349_MU_CNT : integer;
  attribute C_PROBE349_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE349_TYPE : integer;
  attribute C_PROBE349_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE349_WIDTH : integer;
  attribute C_PROBE349_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE34_MU_CNT : integer;
  attribute C_PROBE34_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE34_TYPE : integer;
  attribute C_PROBE34_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE34_WIDTH : integer;
  attribute C_PROBE34_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE350_MU_CNT : integer;
  attribute C_PROBE350_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE350_TYPE : integer;
  attribute C_PROBE350_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE350_WIDTH : integer;
  attribute C_PROBE350_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE351_MU_CNT : integer;
  attribute C_PROBE351_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE351_TYPE : integer;
  attribute C_PROBE351_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE351_WIDTH : integer;
  attribute C_PROBE351_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE352_MU_CNT : integer;
  attribute C_PROBE352_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE352_TYPE : integer;
  attribute C_PROBE352_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE352_WIDTH : integer;
  attribute C_PROBE352_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE353_MU_CNT : integer;
  attribute C_PROBE353_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE353_TYPE : integer;
  attribute C_PROBE353_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE353_WIDTH : integer;
  attribute C_PROBE353_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE354_MU_CNT : integer;
  attribute C_PROBE354_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE354_TYPE : integer;
  attribute C_PROBE354_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE354_WIDTH : integer;
  attribute C_PROBE354_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE355_MU_CNT : integer;
  attribute C_PROBE355_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE355_TYPE : integer;
  attribute C_PROBE355_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE355_WIDTH : integer;
  attribute C_PROBE355_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE356_MU_CNT : integer;
  attribute C_PROBE356_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE356_TYPE : integer;
  attribute C_PROBE356_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE356_WIDTH : integer;
  attribute C_PROBE356_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE357_MU_CNT : integer;
  attribute C_PROBE357_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE357_TYPE : integer;
  attribute C_PROBE357_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE357_WIDTH : integer;
  attribute C_PROBE357_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE358_MU_CNT : integer;
  attribute C_PROBE358_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE358_TYPE : integer;
  attribute C_PROBE358_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE358_WIDTH : integer;
  attribute C_PROBE358_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE359_MU_CNT : integer;
  attribute C_PROBE359_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE359_TYPE : integer;
  attribute C_PROBE359_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE359_WIDTH : integer;
  attribute C_PROBE359_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE35_MU_CNT : integer;
  attribute C_PROBE35_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE35_TYPE : integer;
  attribute C_PROBE35_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE35_WIDTH : integer;
  attribute C_PROBE35_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE360_MU_CNT : integer;
  attribute C_PROBE360_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE360_TYPE : integer;
  attribute C_PROBE360_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE360_WIDTH : integer;
  attribute C_PROBE360_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE361_MU_CNT : integer;
  attribute C_PROBE361_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE361_TYPE : integer;
  attribute C_PROBE361_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE361_WIDTH : integer;
  attribute C_PROBE361_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE362_MU_CNT : integer;
  attribute C_PROBE362_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE362_TYPE : integer;
  attribute C_PROBE362_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE362_WIDTH : integer;
  attribute C_PROBE362_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE363_MU_CNT : integer;
  attribute C_PROBE363_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE363_TYPE : integer;
  attribute C_PROBE363_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE363_WIDTH : integer;
  attribute C_PROBE363_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE364_MU_CNT : integer;
  attribute C_PROBE364_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE364_TYPE : integer;
  attribute C_PROBE364_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE364_WIDTH : integer;
  attribute C_PROBE364_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE365_MU_CNT : integer;
  attribute C_PROBE365_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE365_TYPE : integer;
  attribute C_PROBE365_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE365_WIDTH : integer;
  attribute C_PROBE365_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE366_MU_CNT : integer;
  attribute C_PROBE366_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE366_TYPE : integer;
  attribute C_PROBE366_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE366_WIDTH : integer;
  attribute C_PROBE366_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE367_MU_CNT : integer;
  attribute C_PROBE367_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE367_TYPE : integer;
  attribute C_PROBE367_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE367_WIDTH : integer;
  attribute C_PROBE367_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE368_MU_CNT : integer;
  attribute C_PROBE368_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE368_TYPE : integer;
  attribute C_PROBE368_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE368_WIDTH : integer;
  attribute C_PROBE368_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE369_MU_CNT : integer;
  attribute C_PROBE369_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE369_TYPE : integer;
  attribute C_PROBE369_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE369_WIDTH : integer;
  attribute C_PROBE369_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE36_MU_CNT : integer;
  attribute C_PROBE36_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE36_TYPE : integer;
  attribute C_PROBE36_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE36_WIDTH : integer;
  attribute C_PROBE36_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE370_MU_CNT : integer;
  attribute C_PROBE370_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE370_TYPE : integer;
  attribute C_PROBE370_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE370_WIDTH : integer;
  attribute C_PROBE370_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE371_MU_CNT : integer;
  attribute C_PROBE371_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE371_TYPE : integer;
  attribute C_PROBE371_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE371_WIDTH : integer;
  attribute C_PROBE371_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE372_MU_CNT : integer;
  attribute C_PROBE372_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE372_TYPE : integer;
  attribute C_PROBE372_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE372_WIDTH : integer;
  attribute C_PROBE372_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE373_MU_CNT : integer;
  attribute C_PROBE373_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE373_TYPE : integer;
  attribute C_PROBE373_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE373_WIDTH : integer;
  attribute C_PROBE373_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE374_MU_CNT : integer;
  attribute C_PROBE374_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE374_TYPE : integer;
  attribute C_PROBE374_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE374_WIDTH : integer;
  attribute C_PROBE374_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE375_MU_CNT : integer;
  attribute C_PROBE375_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE375_TYPE : integer;
  attribute C_PROBE375_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE375_WIDTH : integer;
  attribute C_PROBE375_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE376_MU_CNT : integer;
  attribute C_PROBE376_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE376_TYPE : integer;
  attribute C_PROBE376_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE376_WIDTH : integer;
  attribute C_PROBE376_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE377_MU_CNT : integer;
  attribute C_PROBE377_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE377_TYPE : integer;
  attribute C_PROBE377_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE377_WIDTH : integer;
  attribute C_PROBE377_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE378_MU_CNT : integer;
  attribute C_PROBE378_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE378_TYPE : integer;
  attribute C_PROBE378_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE378_WIDTH : integer;
  attribute C_PROBE378_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE379_MU_CNT : integer;
  attribute C_PROBE379_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE379_TYPE : integer;
  attribute C_PROBE379_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE379_WIDTH : integer;
  attribute C_PROBE379_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE37_MU_CNT : integer;
  attribute C_PROBE37_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE37_TYPE : integer;
  attribute C_PROBE37_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE37_WIDTH : integer;
  attribute C_PROBE37_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE380_MU_CNT : integer;
  attribute C_PROBE380_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE380_TYPE : integer;
  attribute C_PROBE380_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE380_WIDTH : integer;
  attribute C_PROBE380_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE381_MU_CNT : integer;
  attribute C_PROBE381_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE381_TYPE : integer;
  attribute C_PROBE381_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE381_WIDTH : integer;
  attribute C_PROBE381_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE382_MU_CNT : integer;
  attribute C_PROBE382_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE382_TYPE : integer;
  attribute C_PROBE382_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE382_WIDTH : integer;
  attribute C_PROBE382_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE383_MU_CNT : integer;
  attribute C_PROBE383_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE383_TYPE : integer;
  attribute C_PROBE383_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE383_WIDTH : integer;
  attribute C_PROBE383_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE384_MU_CNT : integer;
  attribute C_PROBE384_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE384_TYPE : integer;
  attribute C_PROBE384_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE384_WIDTH : integer;
  attribute C_PROBE384_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE385_MU_CNT : integer;
  attribute C_PROBE385_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE385_TYPE : integer;
  attribute C_PROBE385_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE385_WIDTH : integer;
  attribute C_PROBE385_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE386_MU_CNT : integer;
  attribute C_PROBE386_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE386_TYPE : integer;
  attribute C_PROBE386_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE386_WIDTH : integer;
  attribute C_PROBE386_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE387_MU_CNT : integer;
  attribute C_PROBE387_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE387_TYPE : integer;
  attribute C_PROBE387_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE387_WIDTH : integer;
  attribute C_PROBE387_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE388_MU_CNT : integer;
  attribute C_PROBE388_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE388_TYPE : integer;
  attribute C_PROBE388_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE388_WIDTH : integer;
  attribute C_PROBE388_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE389_MU_CNT : integer;
  attribute C_PROBE389_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE389_TYPE : integer;
  attribute C_PROBE389_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE389_WIDTH : integer;
  attribute C_PROBE389_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE38_MU_CNT : integer;
  attribute C_PROBE38_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE38_TYPE : integer;
  attribute C_PROBE38_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE38_WIDTH : integer;
  attribute C_PROBE38_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE390_MU_CNT : integer;
  attribute C_PROBE390_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE390_TYPE : integer;
  attribute C_PROBE390_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE390_WIDTH : integer;
  attribute C_PROBE390_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE391_MU_CNT : integer;
  attribute C_PROBE391_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE391_TYPE : integer;
  attribute C_PROBE391_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE391_WIDTH : integer;
  attribute C_PROBE391_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE392_MU_CNT : integer;
  attribute C_PROBE392_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE392_TYPE : integer;
  attribute C_PROBE392_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE392_WIDTH : integer;
  attribute C_PROBE392_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE393_MU_CNT : integer;
  attribute C_PROBE393_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE393_TYPE : integer;
  attribute C_PROBE393_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE393_WIDTH : integer;
  attribute C_PROBE393_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE394_MU_CNT : integer;
  attribute C_PROBE394_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE394_TYPE : integer;
  attribute C_PROBE394_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE394_WIDTH : integer;
  attribute C_PROBE394_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE395_MU_CNT : integer;
  attribute C_PROBE395_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE395_TYPE : integer;
  attribute C_PROBE395_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE395_WIDTH : integer;
  attribute C_PROBE395_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE396_MU_CNT : integer;
  attribute C_PROBE396_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE396_TYPE : integer;
  attribute C_PROBE396_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE396_WIDTH : integer;
  attribute C_PROBE396_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE397_MU_CNT : integer;
  attribute C_PROBE397_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE397_TYPE : integer;
  attribute C_PROBE397_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE397_WIDTH : integer;
  attribute C_PROBE397_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE398_MU_CNT : integer;
  attribute C_PROBE398_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE398_TYPE : integer;
  attribute C_PROBE398_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE398_WIDTH : integer;
  attribute C_PROBE398_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE399_MU_CNT : integer;
  attribute C_PROBE399_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE399_TYPE : integer;
  attribute C_PROBE399_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE399_WIDTH : integer;
  attribute C_PROBE399_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE39_MU_CNT : integer;
  attribute C_PROBE39_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE39_TYPE : integer;
  attribute C_PROBE39_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE39_WIDTH : integer;
  attribute C_PROBE39_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE3_MU_CNT : integer;
  attribute C_PROBE3_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE3_TYPE : integer;
  attribute C_PROBE3_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE3_WIDTH : integer;
  attribute C_PROBE3_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 8;
  attribute C_PROBE400_MU_CNT : integer;
  attribute C_PROBE400_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE400_TYPE : integer;
  attribute C_PROBE400_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE400_WIDTH : integer;
  attribute C_PROBE400_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE401_MU_CNT : integer;
  attribute C_PROBE401_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE401_TYPE : integer;
  attribute C_PROBE401_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE401_WIDTH : integer;
  attribute C_PROBE401_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE402_MU_CNT : integer;
  attribute C_PROBE402_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE402_TYPE : integer;
  attribute C_PROBE402_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE402_WIDTH : integer;
  attribute C_PROBE402_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE403_MU_CNT : integer;
  attribute C_PROBE403_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE403_TYPE : integer;
  attribute C_PROBE403_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE403_WIDTH : integer;
  attribute C_PROBE403_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE404_MU_CNT : integer;
  attribute C_PROBE404_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE404_TYPE : integer;
  attribute C_PROBE404_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE404_WIDTH : integer;
  attribute C_PROBE404_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE405_MU_CNT : integer;
  attribute C_PROBE405_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE405_TYPE : integer;
  attribute C_PROBE405_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE405_WIDTH : integer;
  attribute C_PROBE405_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE406_MU_CNT : integer;
  attribute C_PROBE406_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE406_TYPE : integer;
  attribute C_PROBE406_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE406_WIDTH : integer;
  attribute C_PROBE406_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE407_MU_CNT : integer;
  attribute C_PROBE407_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE407_TYPE : integer;
  attribute C_PROBE407_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE407_WIDTH : integer;
  attribute C_PROBE407_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE408_MU_CNT : integer;
  attribute C_PROBE408_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE408_TYPE : integer;
  attribute C_PROBE408_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE408_WIDTH : integer;
  attribute C_PROBE408_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE409_MU_CNT : integer;
  attribute C_PROBE409_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE409_TYPE : integer;
  attribute C_PROBE409_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE409_WIDTH : integer;
  attribute C_PROBE409_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE40_MU_CNT : integer;
  attribute C_PROBE40_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE40_TYPE : integer;
  attribute C_PROBE40_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE40_WIDTH : integer;
  attribute C_PROBE40_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE410_MU_CNT : integer;
  attribute C_PROBE410_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE410_TYPE : integer;
  attribute C_PROBE410_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE410_WIDTH : integer;
  attribute C_PROBE410_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE411_MU_CNT : integer;
  attribute C_PROBE411_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE411_TYPE : integer;
  attribute C_PROBE411_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE411_WIDTH : integer;
  attribute C_PROBE411_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE412_MU_CNT : integer;
  attribute C_PROBE412_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE412_TYPE : integer;
  attribute C_PROBE412_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE412_WIDTH : integer;
  attribute C_PROBE412_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE413_MU_CNT : integer;
  attribute C_PROBE413_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE413_TYPE : integer;
  attribute C_PROBE413_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE413_WIDTH : integer;
  attribute C_PROBE413_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE414_MU_CNT : integer;
  attribute C_PROBE414_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE414_TYPE : integer;
  attribute C_PROBE414_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE414_WIDTH : integer;
  attribute C_PROBE414_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE415_MU_CNT : integer;
  attribute C_PROBE415_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE415_TYPE : integer;
  attribute C_PROBE415_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE415_WIDTH : integer;
  attribute C_PROBE415_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE416_MU_CNT : integer;
  attribute C_PROBE416_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE416_TYPE : integer;
  attribute C_PROBE416_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE416_WIDTH : integer;
  attribute C_PROBE416_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE417_MU_CNT : integer;
  attribute C_PROBE417_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE417_TYPE : integer;
  attribute C_PROBE417_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE417_WIDTH : integer;
  attribute C_PROBE417_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE418_MU_CNT : integer;
  attribute C_PROBE418_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE418_TYPE : integer;
  attribute C_PROBE418_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE418_WIDTH : integer;
  attribute C_PROBE418_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE419_MU_CNT : integer;
  attribute C_PROBE419_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE419_TYPE : integer;
  attribute C_PROBE419_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE419_WIDTH : integer;
  attribute C_PROBE419_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE41_MU_CNT : integer;
  attribute C_PROBE41_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE41_TYPE : integer;
  attribute C_PROBE41_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE41_WIDTH : integer;
  attribute C_PROBE41_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE420_MU_CNT : integer;
  attribute C_PROBE420_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE420_TYPE : integer;
  attribute C_PROBE420_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE420_WIDTH : integer;
  attribute C_PROBE420_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE421_MU_CNT : integer;
  attribute C_PROBE421_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE421_TYPE : integer;
  attribute C_PROBE421_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE421_WIDTH : integer;
  attribute C_PROBE421_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE422_MU_CNT : integer;
  attribute C_PROBE422_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE422_TYPE : integer;
  attribute C_PROBE422_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE422_WIDTH : integer;
  attribute C_PROBE422_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE423_MU_CNT : integer;
  attribute C_PROBE423_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE423_TYPE : integer;
  attribute C_PROBE423_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE423_WIDTH : integer;
  attribute C_PROBE423_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE424_MU_CNT : integer;
  attribute C_PROBE424_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE424_TYPE : integer;
  attribute C_PROBE424_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE424_WIDTH : integer;
  attribute C_PROBE424_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE425_MU_CNT : integer;
  attribute C_PROBE425_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE425_TYPE : integer;
  attribute C_PROBE425_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE425_WIDTH : integer;
  attribute C_PROBE425_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE426_MU_CNT : integer;
  attribute C_PROBE426_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE426_TYPE : integer;
  attribute C_PROBE426_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE426_WIDTH : integer;
  attribute C_PROBE426_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE427_MU_CNT : integer;
  attribute C_PROBE427_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE427_TYPE : integer;
  attribute C_PROBE427_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE427_WIDTH : integer;
  attribute C_PROBE427_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE428_MU_CNT : integer;
  attribute C_PROBE428_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE428_TYPE : integer;
  attribute C_PROBE428_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE428_WIDTH : integer;
  attribute C_PROBE428_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE429_MU_CNT : integer;
  attribute C_PROBE429_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE429_TYPE : integer;
  attribute C_PROBE429_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE429_WIDTH : integer;
  attribute C_PROBE429_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE42_MU_CNT : integer;
  attribute C_PROBE42_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE42_TYPE : integer;
  attribute C_PROBE42_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE42_WIDTH : integer;
  attribute C_PROBE42_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE430_MU_CNT : integer;
  attribute C_PROBE430_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE430_TYPE : integer;
  attribute C_PROBE430_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE430_WIDTH : integer;
  attribute C_PROBE430_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE431_MU_CNT : integer;
  attribute C_PROBE431_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE431_TYPE : integer;
  attribute C_PROBE431_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE431_WIDTH : integer;
  attribute C_PROBE431_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE432_MU_CNT : integer;
  attribute C_PROBE432_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE432_TYPE : integer;
  attribute C_PROBE432_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE432_WIDTH : integer;
  attribute C_PROBE432_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE433_MU_CNT : integer;
  attribute C_PROBE433_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE433_TYPE : integer;
  attribute C_PROBE433_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE433_WIDTH : integer;
  attribute C_PROBE433_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE434_MU_CNT : integer;
  attribute C_PROBE434_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE434_TYPE : integer;
  attribute C_PROBE434_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE434_WIDTH : integer;
  attribute C_PROBE434_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE435_MU_CNT : integer;
  attribute C_PROBE435_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE435_TYPE : integer;
  attribute C_PROBE435_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE435_WIDTH : integer;
  attribute C_PROBE435_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE436_MU_CNT : integer;
  attribute C_PROBE436_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE436_TYPE : integer;
  attribute C_PROBE436_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE436_WIDTH : integer;
  attribute C_PROBE436_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE437_MU_CNT : integer;
  attribute C_PROBE437_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE437_TYPE : integer;
  attribute C_PROBE437_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE437_WIDTH : integer;
  attribute C_PROBE437_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE438_MU_CNT : integer;
  attribute C_PROBE438_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE438_TYPE : integer;
  attribute C_PROBE438_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE438_WIDTH : integer;
  attribute C_PROBE438_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE439_MU_CNT : integer;
  attribute C_PROBE439_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE439_TYPE : integer;
  attribute C_PROBE439_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE439_WIDTH : integer;
  attribute C_PROBE439_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE43_MU_CNT : integer;
  attribute C_PROBE43_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE43_TYPE : integer;
  attribute C_PROBE43_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE43_WIDTH : integer;
  attribute C_PROBE43_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE440_MU_CNT : integer;
  attribute C_PROBE440_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE440_TYPE : integer;
  attribute C_PROBE440_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE440_WIDTH : integer;
  attribute C_PROBE440_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE441_MU_CNT : integer;
  attribute C_PROBE441_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE441_TYPE : integer;
  attribute C_PROBE441_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE441_WIDTH : integer;
  attribute C_PROBE441_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE442_MU_CNT : integer;
  attribute C_PROBE442_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE442_TYPE : integer;
  attribute C_PROBE442_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE442_WIDTH : integer;
  attribute C_PROBE442_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE443_MU_CNT : integer;
  attribute C_PROBE443_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE443_TYPE : integer;
  attribute C_PROBE443_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE443_WIDTH : integer;
  attribute C_PROBE443_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE444_MU_CNT : integer;
  attribute C_PROBE444_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE444_TYPE : integer;
  attribute C_PROBE444_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE444_WIDTH : integer;
  attribute C_PROBE444_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE445_MU_CNT : integer;
  attribute C_PROBE445_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE445_TYPE : integer;
  attribute C_PROBE445_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE445_WIDTH : integer;
  attribute C_PROBE445_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE446_MU_CNT : integer;
  attribute C_PROBE446_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE446_TYPE : integer;
  attribute C_PROBE446_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE446_WIDTH : integer;
  attribute C_PROBE446_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE447_MU_CNT : integer;
  attribute C_PROBE447_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE447_TYPE : integer;
  attribute C_PROBE447_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE447_WIDTH : integer;
  attribute C_PROBE447_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE448_MU_CNT : integer;
  attribute C_PROBE448_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE448_TYPE : integer;
  attribute C_PROBE448_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE448_WIDTH : integer;
  attribute C_PROBE448_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE449_MU_CNT : integer;
  attribute C_PROBE449_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE449_TYPE : integer;
  attribute C_PROBE449_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE449_WIDTH : integer;
  attribute C_PROBE449_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE44_MU_CNT : integer;
  attribute C_PROBE44_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE44_TYPE : integer;
  attribute C_PROBE44_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE44_WIDTH : integer;
  attribute C_PROBE44_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE450_MU_CNT : integer;
  attribute C_PROBE450_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE450_TYPE : integer;
  attribute C_PROBE450_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE450_WIDTH : integer;
  attribute C_PROBE450_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE451_MU_CNT : integer;
  attribute C_PROBE451_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE451_TYPE : integer;
  attribute C_PROBE451_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE451_WIDTH : integer;
  attribute C_PROBE451_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE452_MU_CNT : integer;
  attribute C_PROBE452_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE452_TYPE : integer;
  attribute C_PROBE452_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE452_WIDTH : integer;
  attribute C_PROBE452_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE453_MU_CNT : integer;
  attribute C_PROBE453_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE453_TYPE : integer;
  attribute C_PROBE453_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE453_WIDTH : integer;
  attribute C_PROBE453_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE454_MU_CNT : integer;
  attribute C_PROBE454_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE454_TYPE : integer;
  attribute C_PROBE454_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE454_WIDTH : integer;
  attribute C_PROBE454_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE455_MU_CNT : integer;
  attribute C_PROBE455_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE455_TYPE : integer;
  attribute C_PROBE455_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE455_WIDTH : integer;
  attribute C_PROBE455_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE456_MU_CNT : integer;
  attribute C_PROBE456_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE456_TYPE : integer;
  attribute C_PROBE456_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE456_WIDTH : integer;
  attribute C_PROBE456_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE457_MU_CNT : integer;
  attribute C_PROBE457_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE457_TYPE : integer;
  attribute C_PROBE457_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE457_WIDTH : integer;
  attribute C_PROBE457_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE458_MU_CNT : integer;
  attribute C_PROBE458_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE458_TYPE : integer;
  attribute C_PROBE458_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE458_WIDTH : integer;
  attribute C_PROBE458_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE459_MU_CNT : integer;
  attribute C_PROBE459_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE459_TYPE : integer;
  attribute C_PROBE459_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE459_WIDTH : integer;
  attribute C_PROBE459_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE45_MU_CNT : integer;
  attribute C_PROBE45_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE45_TYPE : integer;
  attribute C_PROBE45_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE45_WIDTH : integer;
  attribute C_PROBE45_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE460_MU_CNT : integer;
  attribute C_PROBE460_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE460_TYPE : integer;
  attribute C_PROBE460_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE460_WIDTH : integer;
  attribute C_PROBE460_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE461_MU_CNT : integer;
  attribute C_PROBE461_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE461_TYPE : integer;
  attribute C_PROBE461_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE461_WIDTH : integer;
  attribute C_PROBE461_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE462_MU_CNT : integer;
  attribute C_PROBE462_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE462_TYPE : integer;
  attribute C_PROBE462_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE462_WIDTH : integer;
  attribute C_PROBE462_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE463_MU_CNT : integer;
  attribute C_PROBE463_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE463_TYPE : integer;
  attribute C_PROBE463_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE463_WIDTH : integer;
  attribute C_PROBE463_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE464_MU_CNT : integer;
  attribute C_PROBE464_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE464_TYPE : integer;
  attribute C_PROBE464_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE464_WIDTH : integer;
  attribute C_PROBE464_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE465_MU_CNT : integer;
  attribute C_PROBE465_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE465_TYPE : integer;
  attribute C_PROBE465_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE465_WIDTH : integer;
  attribute C_PROBE465_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE466_MU_CNT : integer;
  attribute C_PROBE466_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE466_TYPE : integer;
  attribute C_PROBE466_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE466_WIDTH : integer;
  attribute C_PROBE466_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE467_MU_CNT : integer;
  attribute C_PROBE467_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE467_TYPE : integer;
  attribute C_PROBE467_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE467_WIDTH : integer;
  attribute C_PROBE467_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE468_MU_CNT : integer;
  attribute C_PROBE468_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE468_TYPE : integer;
  attribute C_PROBE468_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE468_WIDTH : integer;
  attribute C_PROBE468_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE469_MU_CNT : integer;
  attribute C_PROBE469_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE469_TYPE : integer;
  attribute C_PROBE469_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE469_WIDTH : integer;
  attribute C_PROBE469_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE46_MU_CNT : integer;
  attribute C_PROBE46_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE46_TYPE : integer;
  attribute C_PROBE46_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE46_WIDTH : integer;
  attribute C_PROBE46_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE470_MU_CNT : integer;
  attribute C_PROBE470_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE470_TYPE : integer;
  attribute C_PROBE470_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE470_WIDTH : integer;
  attribute C_PROBE470_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE471_MU_CNT : integer;
  attribute C_PROBE471_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE471_TYPE : integer;
  attribute C_PROBE471_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE471_WIDTH : integer;
  attribute C_PROBE471_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE472_MU_CNT : integer;
  attribute C_PROBE472_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE472_TYPE : integer;
  attribute C_PROBE472_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE472_WIDTH : integer;
  attribute C_PROBE472_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE473_MU_CNT : integer;
  attribute C_PROBE473_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE473_TYPE : integer;
  attribute C_PROBE473_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE473_WIDTH : integer;
  attribute C_PROBE473_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE474_MU_CNT : integer;
  attribute C_PROBE474_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE474_TYPE : integer;
  attribute C_PROBE474_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE474_WIDTH : integer;
  attribute C_PROBE474_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE475_MU_CNT : integer;
  attribute C_PROBE475_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE475_TYPE : integer;
  attribute C_PROBE475_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE475_WIDTH : integer;
  attribute C_PROBE475_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE476_MU_CNT : integer;
  attribute C_PROBE476_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE476_TYPE : integer;
  attribute C_PROBE476_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE476_WIDTH : integer;
  attribute C_PROBE476_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE477_MU_CNT : integer;
  attribute C_PROBE477_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE477_TYPE : integer;
  attribute C_PROBE477_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE477_WIDTH : integer;
  attribute C_PROBE477_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE478_MU_CNT : integer;
  attribute C_PROBE478_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE478_TYPE : integer;
  attribute C_PROBE478_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE478_WIDTH : integer;
  attribute C_PROBE478_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE479_MU_CNT : integer;
  attribute C_PROBE479_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE479_TYPE : integer;
  attribute C_PROBE479_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE479_WIDTH : integer;
  attribute C_PROBE479_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE47_MU_CNT : integer;
  attribute C_PROBE47_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE47_TYPE : integer;
  attribute C_PROBE47_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE47_WIDTH : integer;
  attribute C_PROBE47_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE480_MU_CNT : integer;
  attribute C_PROBE480_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE480_TYPE : integer;
  attribute C_PROBE480_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE480_WIDTH : integer;
  attribute C_PROBE480_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE481_MU_CNT : integer;
  attribute C_PROBE481_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE481_TYPE : integer;
  attribute C_PROBE481_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE481_WIDTH : integer;
  attribute C_PROBE481_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE482_MU_CNT : integer;
  attribute C_PROBE482_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE482_TYPE : integer;
  attribute C_PROBE482_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE482_WIDTH : integer;
  attribute C_PROBE482_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE483_MU_CNT : integer;
  attribute C_PROBE483_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE483_TYPE : integer;
  attribute C_PROBE483_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE483_WIDTH : integer;
  attribute C_PROBE483_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE484_MU_CNT : integer;
  attribute C_PROBE484_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE484_TYPE : integer;
  attribute C_PROBE484_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE484_WIDTH : integer;
  attribute C_PROBE484_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE485_MU_CNT : integer;
  attribute C_PROBE485_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE485_TYPE : integer;
  attribute C_PROBE485_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE485_WIDTH : integer;
  attribute C_PROBE485_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE486_MU_CNT : integer;
  attribute C_PROBE486_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE486_TYPE : integer;
  attribute C_PROBE486_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE486_WIDTH : integer;
  attribute C_PROBE486_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE487_MU_CNT : integer;
  attribute C_PROBE487_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE487_TYPE : integer;
  attribute C_PROBE487_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE487_WIDTH : integer;
  attribute C_PROBE487_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE488_MU_CNT : integer;
  attribute C_PROBE488_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE488_TYPE : integer;
  attribute C_PROBE488_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE488_WIDTH : integer;
  attribute C_PROBE488_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE489_MU_CNT : integer;
  attribute C_PROBE489_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE489_TYPE : integer;
  attribute C_PROBE489_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE489_WIDTH : integer;
  attribute C_PROBE489_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE48_MU_CNT : integer;
  attribute C_PROBE48_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE48_TYPE : integer;
  attribute C_PROBE48_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE48_WIDTH : integer;
  attribute C_PROBE48_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE490_MU_CNT : integer;
  attribute C_PROBE490_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE490_TYPE : integer;
  attribute C_PROBE490_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE490_WIDTH : integer;
  attribute C_PROBE490_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE491_MU_CNT : integer;
  attribute C_PROBE491_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE491_TYPE : integer;
  attribute C_PROBE491_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE491_WIDTH : integer;
  attribute C_PROBE491_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE492_MU_CNT : integer;
  attribute C_PROBE492_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE492_TYPE : integer;
  attribute C_PROBE492_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE492_WIDTH : integer;
  attribute C_PROBE492_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE493_MU_CNT : integer;
  attribute C_PROBE493_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE493_TYPE : integer;
  attribute C_PROBE493_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE493_WIDTH : integer;
  attribute C_PROBE493_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE494_MU_CNT : integer;
  attribute C_PROBE494_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE494_TYPE : integer;
  attribute C_PROBE494_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE494_WIDTH : integer;
  attribute C_PROBE494_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE495_MU_CNT : integer;
  attribute C_PROBE495_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE495_TYPE : integer;
  attribute C_PROBE495_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE495_WIDTH : integer;
  attribute C_PROBE495_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE496_MU_CNT : integer;
  attribute C_PROBE496_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE496_TYPE : integer;
  attribute C_PROBE496_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE496_WIDTH : integer;
  attribute C_PROBE496_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE497_MU_CNT : integer;
  attribute C_PROBE497_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE497_TYPE : integer;
  attribute C_PROBE497_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE497_WIDTH : integer;
  attribute C_PROBE497_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE498_MU_CNT : integer;
  attribute C_PROBE498_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE498_TYPE : integer;
  attribute C_PROBE498_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE498_WIDTH : integer;
  attribute C_PROBE498_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE499_MU_CNT : integer;
  attribute C_PROBE499_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE499_TYPE : integer;
  attribute C_PROBE499_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE499_WIDTH : integer;
  attribute C_PROBE499_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE49_MU_CNT : integer;
  attribute C_PROBE49_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE49_TYPE : integer;
  attribute C_PROBE49_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE49_WIDTH : integer;
  attribute C_PROBE49_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE4_MU_CNT : integer;
  attribute C_PROBE4_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE4_TYPE : integer;
  attribute C_PROBE4_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE4_WIDTH : integer;
  attribute C_PROBE4_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 32;
  attribute C_PROBE500_MU_CNT : integer;
  attribute C_PROBE500_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE500_TYPE : integer;
  attribute C_PROBE500_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE500_WIDTH : integer;
  attribute C_PROBE500_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE501_MU_CNT : integer;
  attribute C_PROBE501_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE501_TYPE : integer;
  attribute C_PROBE501_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE501_WIDTH : integer;
  attribute C_PROBE501_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE502_MU_CNT : integer;
  attribute C_PROBE502_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE502_TYPE : integer;
  attribute C_PROBE502_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE502_WIDTH : integer;
  attribute C_PROBE502_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE503_MU_CNT : integer;
  attribute C_PROBE503_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE503_TYPE : integer;
  attribute C_PROBE503_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE503_WIDTH : integer;
  attribute C_PROBE503_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE504_MU_CNT : integer;
  attribute C_PROBE504_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE504_TYPE : integer;
  attribute C_PROBE504_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE504_WIDTH : integer;
  attribute C_PROBE504_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE505_MU_CNT : integer;
  attribute C_PROBE505_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE505_TYPE : integer;
  attribute C_PROBE505_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE505_WIDTH : integer;
  attribute C_PROBE505_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE506_MU_CNT : integer;
  attribute C_PROBE506_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE506_TYPE : integer;
  attribute C_PROBE506_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE506_WIDTH : integer;
  attribute C_PROBE506_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE507_MU_CNT : integer;
  attribute C_PROBE507_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE507_TYPE : integer;
  attribute C_PROBE507_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE507_WIDTH : integer;
  attribute C_PROBE507_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE508_MU_CNT : integer;
  attribute C_PROBE508_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE508_TYPE : integer;
  attribute C_PROBE508_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE508_WIDTH : integer;
  attribute C_PROBE508_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE509_MU_CNT : integer;
  attribute C_PROBE509_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE509_TYPE : integer;
  attribute C_PROBE509_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE509_WIDTH : integer;
  attribute C_PROBE509_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE50_MU_CNT : integer;
  attribute C_PROBE50_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE50_TYPE : integer;
  attribute C_PROBE50_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE50_WIDTH : integer;
  attribute C_PROBE50_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE510_MU_CNT : integer;
  attribute C_PROBE510_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE510_TYPE : integer;
  attribute C_PROBE510_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE510_WIDTH : integer;
  attribute C_PROBE510_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE511_MU_CNT : integer;
  attribute C_PROBE511_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE511_TYPE : integer;
  attribute C_PROBE511_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE511_WIDTH : integer;
  attribute C_PROBE511_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE512_MU_CNT : integer;
  attribute C_PROBE512_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE512_TYPE : integer;
  attribute C_PROBE512_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE512_WIDTH : integer;
  attribute C_PROBE512_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE513_MU_CNT : integer;
  attribute C_PROBE513_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE513_TYPE : integer;
  attribute C_PROBE513_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE513_WIDTH : integer;
  attribute C_PROBE513_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE514_MU_CNT : integer;
  attribute C_PROBE514_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE514_TYPE : integer;
  attribute C_PROBE514_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE514_WIDTH : integer;
  attribute C_PROBE514_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE515_MU_CNT : integer;
  attribute C_PROBE515_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE515_TYPE : integer;
  attribute C_PROBE515_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE515_WIDTH : integer;
  attribute C_PROBE515_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE516_MU_CNT : integer;
  attribute C_PROBE516_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE516_TYPE : integer;
  attribute C_PROBE516_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE516_WIDTH : integer;
  attribute C_PROBE516_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE517_MU_CNT : integer;
  attribute C_PROBE517_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE517_TYPE : integer;
  attribute C_PROBE517_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE517_WIDTH : integer;
  attribute C_PROBE517_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE518_MU_CNT : integer;
  attribute C_PROBE518_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE518_TYPE : integer;
  attribute C_PROBE518_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE518_WIDTH : integer;
  attribute C_PROBE518_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE519_MU_CNT : integer;
  attribute C_PROBE519_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE519_TYPE : integer;
  attribute C_PROBE519_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE519_WIDTH : integer;
  attribute C_PROBE519_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE51_MU_CNT : integer;
  attribute C_PROBE51_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE51_TYPE : integer;
  attribute C_PROBE51_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE51_WIDTH : integer;
  attribute C_PROBE51_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE520_MU_CNT : integer;
  attribute C_PROBE520_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE520_TYPE : integer;
  attribute C_PROBE520_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE520_WIDTH : integer;
  attribute C_PROBE520_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE521_MU_CNT : integer;
  attribute C_PROBE521_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE521_TYPE : integer;
  attribute C_PROBE521_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE521_WIDTH : integer;
  attribute C_PROBE521_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE522_MU_CNT : integer;
  attribute C_PROBE522_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE522_TYPE : integer;
  attribute C_PROBE522_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE522_WIDTH : integer;
  attribute C_PROBE522_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE523_MU_CNT : integer;
  attribute C_PROBE523_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE523_TYPE : integer;
  attribute C_PROBE523_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE523_WIDTH : integer;
  attribute C_PROBE523_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE524_MU_CNT : integer;
  attribute C_PROBE524_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE524_TYPE : integer;
  attribute C_PROBE524_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE524_WIDTH : integer;
  attribute C_PROBE524_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE525_MU_CNT : integer;
  attribute C_PROBE525_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE525_TYPE : integer;
  attribute C_PROBE525_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE525_WIDTH : integer;
  attribute C_PROBE525_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE526_MU_CNT : integer;
  attribute C_PROBE526_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE526_TYPE : integer;
  attribute C_PROBE526_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE526_WIDTH : integer;
  attribute C_PROBE526_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE527_MU_CNT : integer;
  attribute C_PROBE527_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE527_TYPE : integer;
  attribute C_PROBE527_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE527_WIDTH : integer;
  attribute C_PROBE527_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE528_MU_CNT : integer;
  attribute C_PROBE528_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE528_TYPE : integer;
  attribute C_PROBE528_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE528_WIDTH : integer;
  attribute C_PROBE528_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE529_MU_CNT : integer;
  attribute C_PROBE529_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE529_TYPE : integer;
  attribute C_PROBE529_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE529_WIDTH : integer;
  attribute C_PROBE529_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE52_MU_CNT : integer;
  attribute C_PROBE52_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE52_TYPE : integer;
  attribute C_PROBE52_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE52_WIDTH : integer;
  attribute C_PROBE52_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE530_MU_CNT : integer;
  attribute C_PROBE530_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE530_TYPE : integer;
  attribute C_PROBE530_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE530_WIDTH : integer;
  attribute C_PROBE530_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE531_MU_CNT : integer;
  attribute C_PROBE531_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE531_TYPE : integer;
  attribute C_PROBE531_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE531_WIDTH : integer;
  attribute C_PROBE531_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE532_MU_CNT : integer;
  attribute C_PROBE532_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE532_TYPE : integer;
  attribute C_PROBE532_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE532_WIDTH : integer;
  attribute C_PROBE532_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE533_MU_CNT : integer;
  attribute C_PROBE533_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE533_TYPE : integer;
  attribute C_PROBE533_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE533_WIDTH : integer;
  attribute C_PROBE533_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE534_MU_CNT : integer;
  attribute C_PROBE534_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE534_TYPE : integer;
  attribute C_PROBE534_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE534_WIDTH : integer;
  attribute C_PROBE534_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE535_MU_CNT : integer;
  attribute C_PROBE535_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE535_TYPE : integer;
  attribute C_PROBE535_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE535_WIDTH : integer;
  attribute C_PROBE535_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE536_MU_CNT : integer;
  attribute C_PROBE536_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE536_TYPE : integer;
  attribute C_PROBE536_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE536_WIDTH : integer;
  attribute C_PROBE536_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE537_MU_CNT : integer;
  attribute C_PROBE537_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE537_TYPE : integer;
  attribute C_PROBE537_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE537_WIDTH : integer;
  attribute C_PROBE537_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE538_MU_CNT : integer;
  attribute C_PROBE538_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE538_TYPE : integer;
  attribute C_PROBE538_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE538_WIDTH : integer;
  attribute C_PROBE538_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE539_MU_CNT : integer;
  attribute C_PROBE539_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE539_TYPE : integer;
  attribute C_PROBE539_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE539_WIDTH : integer;
  attribute C_PROBE539_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE53_MU_CNT : integer;
  attribute C_PROBE53_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE53_TYPE : integer;
  attribute C_PROBE53_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE53_WIDTH : integer;
  attribute C_PROBE53_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE540_MU_CNT : integer;
  attribute C_PROBE540_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE540_TYPE : integer;
  attribute C_PROBE540_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE540_WIDTH : integer;
  attribute C_PROBE540_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE541_MU_CNT : integer;
  attribute C_PROBE541_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE541_TYPE : integer;
  attribute C_PROBE541_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE541_WIDTH : integer;
  attribute C_PROBE541_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE542_MU_CNT : integer;
  attribute C_PROBE542_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE542_TYPE : integer;
  attribute C_PROBE542_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE542_WIDTH : integer;
  attribute C_PROBE542_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE543_MU_CNT : integer;
  attribute C_PROBE543_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE543_TYPE : integer;
  attribute C_PROBE543_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE543_WIDTH : integer;
  attribute C_PROBE543_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE544_MU_CNT : integer;
  attribute C_PROBE544_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE544_TYPE : integer;
  attribute C_PROBE544_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE544_WIDTH : integer;
  attribute C_PROBE544_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE545_MU_CNT : integer;
  attribute C_PROBE545_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE545_TYPE : integer;
  attribute C_PROBE545_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE545_WIDTH : integer;
  attribute C_PROBE545_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE546_MU_CNT : integer;
  attribute C_PROBE546_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE546_TYPE : integer;
  attribute C_PROBE546_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE546_WIDTH : integer;
  attribute C_PROBE546_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE547_MU_CNT : integer;
  attribute C_PROBE547_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE547_TYPE : integer;
  attribute C_PROBE547_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE547_WIDTH : integer;
  attribute C_PROBE547_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE548_MU_CNT : integer;
  attribute C_PROBE548_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE548_TYPE : integer;
  attribute C_PROBE548_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE548_WIDTH : integer;
  attribute C_PROBE548_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE549_MU_CNT : integer;
  attribute C_PROBE549_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE549_TYPE : integer;
  attribute C_PROBE549_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE549_WIDTH : integer;
  attribute C_PROBE549_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE54_MU_CNT : integer;
  attribute C_PROBE54_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE54_TYPE : integer;
  attribute C_PROBE54_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE54_WIDTH : integer;
  attribute C_PROBE54_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE550_MU_CNT : integer;
  attribute C_PROBE550_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE550_TYPE : integer;
  attribute C_PROBE550_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE550_WIDTH : integer;
  attribute C_PROBE550_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE551_MU_CNT : integer;
  attribute C_PROBE551_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE551_TYPE : integer;
  attribute C_PROBE551_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE551_WIDTH : integer;
  attribute C_PROBE551_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE552_MU_CNT : integer;
  attribute C_PROBE552_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE552_TYPE : integer;
  attribute C_PROBE552_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE552_WIDTH : integer;
  attribute C_PROBE552_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE553_MU_CNT : integer;
  attribute C_PROBE553_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE553_TYPE : integer;
  attribute C_PROBE553_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE553_WIDTH : integer;
  attribute C_PROBE553_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE554_MU_CNT : integer;
  attribute C_PROBE554_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE554_TYPE : integer;
  attribute C_PROBE554_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE554_WIDTH : integer;
  attribute C_PROBE554_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE555_MU_CNT : integer;
  attribute C_PROBE555_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE555_TYPE : integer;
  attribute C_PROBE555_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE555_WIDTH : integer;
  attribute C_PROBE555_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE556_MU_CNT : integer;
  attribute C_PROBE556_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE556_TYPE : integer;
  attribute C_PROBE556_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE556_WIDTH : integer;
  attribute C_PROBE556_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE557_MU_CNT : integer;
  attribute C_PROBE557_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE557_TYPE : integer;
  attribute C_PROBE557_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE557_WIDTH : integer;
  attribute C_PROBE557_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE558_MU_CNT : integer;
  attribute C_PROBE558_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE558_TYPE : integer;
  attribute C_PROBE558_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE558_WIDTH : integer;
  attribute C_PROBE558_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE559_MU_CNT : integer;
  attribute C_PROBE559_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE559_TYPE : integer;
  attribute C_PROBE559_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE559_WIDTH : integer;
  attribute C_PROBE559_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE55_MU_CNT : integer;
  attribute C_PROBE55_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE55_TYPE : integer;
  attribute C_PROBE55_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE55_WIDTH : integer;
  attribute C_PROBE55_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE560_MU_CNT : integer;
  attribute C_PROBE560_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE560_TYPE : integer;
  attribute C_PROBE560_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE560_WIDTH : integer;
  attribute C_PROBE560_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE561_MU_CNT : integer;
  attribute C_PROBE561_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE561_TYPE : integer;
  attribute C_PROBE561_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE561_WIDTH : integer;
  attribute C_PROBE561_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE562_MU_CNT : integer;
  attribute C_PROBE562_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE562_TYPE : integer;
  attribute C_PROBE562_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE562_WIDTH : integer;
  attribute C_PROBE562_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE563_MU_CNT : integer;
  attribute C_PROBE563_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE563_TYPE : integer;
  attribute C_PROBE563_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE563_WIDTH : integer;
  attribute C_PROBE563_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE564_MU_CNT : integer;
  attribute C_PROBE564_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE564_TYPE : integer;
  attribute C_PROBE564_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE564_WIDTH : integer;
  attribute C_PROBE564_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE565_MU_CNT : integer;
  attribute C_PROBE565_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE565_TYPE : integer;
  attribute C_PROBE565_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE565_WIDTH : integer;
  attribute C_PROBE565_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE566_MU_CNT : integer;
  attribute C_PROBE566_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE566_TYPE : integer;
  attribute C_PROBE566_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE566_WIDTH : integer;
  attribute C_PROBE566_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE567_MU_CNT : integer;
  attribute C_PROBE567_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE567_TYPE : integer;
  attribute C_PROBE567_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE567_WIDTH : integer;
  attribute C_PROBE567_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE568_MU_CNT : integer;
  attribute C_PROBE568_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE568_TYPE : integer;
  attribute C_PROBE568_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE568_WIDTH : integer;
  attribute C_PROBE568_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE569_MU_CNT : integer;
  attribute C_PROBE569_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE569_TYPE : integer;
  attribute C_PROBE569_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE569_WIDTH : integer;
  attribute C_PROBE569_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE56_MU_CNT : integer;
  attribute C_PROBE56_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE56_TYPE : integer;
  attribute C_PROBE56_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE56_WIDTH : integer;
  attribute C_PROBE56_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE570_MU_CNT : integer;
  attribute C_PROBE570_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE570_TYPE : integer;
  attribute C_PROBE570_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE570_WIDTH : integer;
  attribute C_PROBE570_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE571_MU_CNT : integer;
  attribute C_PROBE571_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE571_TYPE : integer;
  attribute C_PROBE571_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE571_WIDTH : integer;
  attribute C_PROBE571_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE572_MU_CNT : integer;
  attribute C_PROBE572_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE572_TYPE : integer;
  attribute C_PROBE572_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE572_WIDTH : integer;
  attribute C_PROBE572_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE573_MU_CNT : integer;
  attribute C_PROBE573_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE573_TYPE : integer;
  attribute C_PROBE573_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE573_WIDTH : integer;
  attribute C_PROBE573_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE574_MU_CNT : integer;
  attribute C_PROBE574_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE574_TYPE : integer;
  attribute C_PROBE574_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE574_WIDTH : integer;
  attribute C_PROBE574_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE575_MU_CNT : integer;
  attribute C_PROBE575_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE575_TYPE : integer;
  attribute C_PROBE575_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE575_WIDTH : integer;
  attribute C_PROBE575_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE576_MU_CNT : integer;
  attribute C_PROBE576_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE576_TYPE : integer;
  attribute C_PROBE576_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE576_WIDTH : integer;
  attribute C_PROBE576_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE577_MU_CNT : integer;
  attribute C_PROBE577_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE577_TYPE : integer;
  attribute C_PROBE577_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE577_WIDTH : integer;
  attribute C_PROBE577_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE578_MU_CNT : integer;
  attribute C_PROBE578_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE578_TYPE : integer;
  attribute C_PROBE578_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE578_WIDTH : integer;
  attribute C_PROBE578_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE579_MU_CNT : integer;
  attribute C_PROBE579_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE579_TYPE : integer;
  attribute C_PROBE579_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE579_WIDTH : integer;
  attribute C_PROBE579_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE57_MU_CNT : integer;
  attribute C_PROBE57_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE57_TYPE : integer;
  attribute C_PROBE57_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE57_WIDTH : integer;
  attribute C_PROBE57_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE580_MU_CNT : integer;
  attribute C_PROBE580_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE580_TYPE : integer;
  attribute C_PROBE580_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE580_WIDTH : integer;
  attribute C_PROBE580_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE581_MU_CNT : integer;
  attribute C_PROBE581_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE581_TYPE : integer;
  attribute C_PROBE581_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE581_WIDTH : integer;
  attribute C_PROBE581_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE582_MU_CNT : integer;
  attribute C_PROBE582_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE582_TYPE : integer;
  attribute C_PROBE582_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE582_WIDTH : integer;
  attribute C_PROBE582_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE583_MU_CNT : integer;
  attribute C_PROBE583_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE583_TYPE : integer;
  attribute C_PROBE583_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE583_WIDTH : integer;
  attribute C_PROBE583_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE584_MU_CNT : integer;
  attribute C_PROBE584_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE584_TYPE : integer;
  attribute C_PROBE584_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE584_WIDTH : integer;
  attribute C_PROBE584_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE585_MU_CNT : integer;
  attribute C_PROBE585_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE585_TYPE : integer;
  attribute C_PROBE585_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE585_WIDTH : integer;
  attribute C_PROBE585_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE586_MU_CNT : integer;
  attribute C_PROBE586_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE586_TYPE : integer;
  attribute C_PROBE586_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE586_WIDTH : integer;
  attribute C_PROBE586_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE587_MU_CNT : integer;
  attribute C_PROBE587_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE587_TYPE : integer;
  attribute C_PROBE587_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE587_WIDTH : integer;
  attribute C_PROBE587_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE588_MU_CNT : integer;
  attribute C_PROBE588_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE588_TYPE : integer;
  attribute C_PROBE588_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE588_WIDTH : integer;
  attribute C_PROBE588_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE589_MU_CNT : integer;
  attribute C_PROBE589_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE589_TYPE : integer;
  attribute C_PROBE589_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE589_WIDTH : integer;
  attribute C_PROBE589_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE58_MU_CNT : integer;
  attribute C_PROBE58_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE58_TYPE : integer;
  attribute C_PROBE58_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE58_WIDTH : integer;
  attribute C_PROBE58_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE590_MU_CNT : integer;
  attribute C_PROBE590_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE590_TYPE : integer;
  attribute C_PROBE590_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE590_WIDTH : integer;
  attribute C_PROBE590_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE591_MU_CNT : integer;
  attribute C_PROBE591_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE591_TYPE : integer;
  attribute C_PROBE591_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE591_WIDTH : integer;
  attribute C_PROBE591_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE592_MU_CNT : integer;
  attribute C_PROBE592_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE592_TYPE : integer;
  attribute C_PROBE592_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE592_WIDTH : integer;
  attribute C_PROBE592_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE593_MU_CNT : integer;
  attribute C_PROBE593_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE593_TYPE : integer;
  attribute C_PROBE593_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE593_WIDTH : integer;
  attribute C_PROBE593_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE594_MU_CNT : integer;
  attribute C_PROBE594_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE594_TYPE : integer;
  attribute C_PROBE594_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE594_WIDTH : integer;
  attribute C_PROBE594_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE595_MU_CNT : integer;
  attribute C_PROBE595_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE595_TYPE : integer;
  attribute C_PROBE595_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE595_WIDTH : integer;
  attribute C_PROBE595_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE596_MU_CNT : integer;
  attribute C_PROBE596_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE596_TYPE : integer;
  attribute C_PROBE596_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE596_WIDTH : integer;
  attribute C_PROBE596_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE597_MU_CNT : integer;
  attribute C_PROBE597_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE597_TYPE : integer;
  attribute C_PROBE597_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE597_WIDTH : integer;
  attribute C_PROBE597_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE598_MU_CNT : integer;
  attribute C_PROBE598_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE598_TYPE : integer;
  attribute C_PROBE598_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE598_WIDTH : integer;
  attribute C_PROBE598_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE599_MU_CNT : integer;
  attribute C_PROBE599_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE599_TYPE : integer;
  attribute C_PROBE599_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE599_WIDTH : integer;
  attribute C_PROBE599_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE59_MU_CNT : integer;
  attribute C_PROBE59_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE59_TYPE : integer;
  attribute C_PROBE59_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE59_WIDTH : integer;
  attribute C_PROBE59_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE5_MU_CNT : integer;
  attribute C_PROBE5_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE5_TYPE : integer;
  attribute C_PROBE5_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_PROBE5_WIDTH : integer;
  attribute C_PROBE5_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 32;
  attribute C_PROBE600_MU_CNT : integer;
  attribute C_PROBE600_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE600_TYPE : integer;
  attribute C_PROBE600_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE600_WIDTH : integer;
  attribute C_PROBE600_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE601_MU_CNT : integer;
  attribute C_PROBE601_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE601_TYPE : integer;
  attribute C_PROBE601_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE601_WIDTH : integer;
  attribute C_PROBE601_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE602_MU_CNT : integer;
  attribute C_PROBE602_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE602_TYPE : integer;
  attribute C_PROBE602_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE602_WIDTH : integer;
  attribute C_PROBE602_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE603_MU_CNT : integer;
  attribute C_PROBE603_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE603_TYPE : integer;
  attribute C_PROBE603_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE603_WIDTH : integer;
  attribute C_PROBE603_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE604_MU_CNT : integer;
  attribute C_PROBE604_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE604_TYPE : integer;
  attribute C_PROBE604_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE604_WIDTH : integer;
  attribute C_PROBE604_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE605_MU_CNT : integer;
  attribute C_PROBE605_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE605_TYPE : integer;
  attribute C_PROBE605_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE605_WIDTH : integer;
  attribute C_PROBE605_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE606_MU_CNT : integer;
  attribute C_PROBE606_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE606_TYPE : integer;
  attribute C_PROBE606_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE606_WIDTH : integer;
  attribute C_PROBE606_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE607_MU_CNT : integer;
  attribute C_PROBE607_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE607_TYPE : integer;
  attribute C_PROBE607_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE607_WIDTH : integer;
  attribute C_PROBE607_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE608_MU_CNT : integer;
  attribute C_PROBE608_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE608_TYPE : integer;
  attribute C_PROBE608_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE608_WIDTH : integer;
  attribute C_PROBE608_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE609_MU_CNT : integer;
  attribute C_PROBE609_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE609_TYPE : integer;
  attribute C_PROBE609_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE609_WIDTH : integer;
  attribute C_PROBE609_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE60_MU_CNT : integer;
  attribute C_PROBE60_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE60_TYPE : integer;
  attribute C_PROBE60_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE60_WIDTH : integer;
  attribute C_PROBE60_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE610_MU_CNT : integer;
  attribute C_PROBE610_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE610_TYPE : integer;
  attribute C_PROBE610_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE610_WIDTH : integer;
  attribute C_PROBE610_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE611_MU_CNT : integer;
  attribute C_PROBE611_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE611_TYPE : integer;
  attribute C_PROBE611_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE611_WIDTH : integer;
  attribute C_PROBE611_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE612_MU_CNT : integer;
  attribute C_PROBE612_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE612_TYPE : integer;
  attribute C_PROBE612_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE612_WIDTH : integer;
  attribute C_PROBE612_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE613_MU_CNT : integer;
  attribute C_PROBE613_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE613_TYPE : integer;
  attribute C_PROBE613_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE613_WIDTH : integer;
  attribute C_PROBE613_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE614_MU_CNT : integer;
  attribute C_PROBE614_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE614_TYPE : integer;
  attribute C_PROBE614_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE614_WIDTH : integer;
  attribute C_PROBE614_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE615_MU_CNT : integer;
  attribute C_PROBE615_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE615_TYPE : integer;
  attribute C_PROBE615_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE615_WIDTH : integer;
  attribute C_PROBE615_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE616_MU_CNT : integer;
  attribute C_PROBE616_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE616_TYPE : integer;
  attribute C_PROBE616_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE616_WIDTH : integer;
  attribute C_PROBE616_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE617_MU_CNT : integer;
  attribute C_PROBE617_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE617_TYPE : integer;
  attribute C_PROBE617_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE617_WIDTH : integer;
  attribute C_PROBE617_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE618_MU_CNT : integer;
  attribute C_PROBE618_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE618_TYPE : integer;
  attribute C_PROBE618_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE618_WIDTH : integer;
  attribute C_PROBE618_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE619_MU_CNT : integer;
  attribute C_PROBE619_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE619_TYPE : integer;
  attribute C_PROBE619_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE619_WIDTH : integer;
  attribute C_PROBE619_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE61_MU_CNT : integer;
  attribute C_PROBE61_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE61_TYPE : integer;
  attribute C_PROBE61_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE61_WIDTH : integer;
  attribute C_PROBE61_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE620_MU_CNT : integer;
  attribute C_PROBE620_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE620_TYPE : integer;
  attribute C_PROBE620_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE620_WIDTH : integer;
  attribute C_PROBE620_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE621_MU_CNT : integer;
  attribute C_PROBE621_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE621_TYPE : integer;
  attribute C_PROBE621_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE621_WIDTH : integer;
  attribute C_PROBE621_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE622_MU_CNT : integer;
  attribute C_PROBE622_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE622_TYPE : integer;
  attribute C_PROBE622_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE622_WIDTH : integer;
  attribute C_PROBE622_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE623_MU_CNT : integer;
  attribute C_PROBE623_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE623_TYPE : integer;
  attribute C_PROBE623_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE623_WIDTH : integer;
  attribute C_PROBE623_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE624_MU_CNT : integer;
  attribute C_PROBE624_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE624_TYPE : integer;
  attribute C_PROBE624_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE624_WIDTH : integer;
  attribute C_PROBE624_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE625_MU_CNT : integer;
  attribute C_PROBE625_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE625_TYPE : integer;
  attribute C_PROBE625_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE625_WIDTH : integer;
  attribute C_PROBE625_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE626_MU_CNT : integer;
  attribute C_PROBE626_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE626_TYPE : integer;
  attribute C_PROBE626_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE626_WIDTH : integer;
  attribute C_PROBE626_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE627_MU_CNT : integer;
  attribute C_PROBE627_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE627_TYPE : integer;
  attribute C_PROBE627_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE627_WIDTH : integer;
  attribute C_PROBE627_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE628_MU_CNT : integer;
  attribute C_PROBE628_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE628_TYPE : integer;
  attribute C_PROBE628_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE628_WIDTH : integer;
  attribute C_PROBE628_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE629_MU_CNT : integer;
  attribute C_PROBE629_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE629_TYPE : integer;
  attribute C_PROBE629_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE629_WIDTH : integer;
  attribute C_PROBE629_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE62_MU_CNT : integer;
  attribute C_PROBE62_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE62_TYPE : integer;
  attribute C_PROBE62_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE62_WIDTH : integer;
  attribute C_PROBE62_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE630_MU_CNT : integer;
  attribute C_PROBE630_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE630_TYPE : integer;
  attribute C_PROBE630_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE630_WIDTH : integer;
  attribute C_PROBE630_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE631_MU_CNT : integer;
  attribute C_PROBE631_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE631_TYPE : integer;
  attribute C_PROBE631_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE631_WIDTH : integer;
  attribute C_PROBE631_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE632_MU_CNT : integer;
  attribute C_PROBE632_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE632_TYPE : integer;
  attribute C_PROBE632_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE632_WIDTH : integer;
  attribute C_PROBE632_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE633_MU_CNT : integer;
  attribute C_PROBE633_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE633_TYPE : integer;
  attribute C_PROBE633_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE633_WIDTH : integer;
  attribute C_PROBE633_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE634_MU_CNT : integer;
  attribute C_PROBE634_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE634_TYPE : integer;
  attribute C_PROBE634_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE634_WIDTH : integer;
  attribute C_PROBE634_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE635_MU_CNT : integer;
  attribute C_PROBE635_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE635_TYPE : integer;
  attribute C_PROBE635_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE635_WIDTH : integer;
  attribute C_PROBE635_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE636_MU_CNT : integer;
  attribute C_PROBE636_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE636_TYPE : integer;
  attribute C_PROBE636_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE636_WIDTH : integer;
  attribute C_PROBE636_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE637_MU_CNT : integer;
  attribute C_PROBE637_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE637_TYPE : integer;
  attribute C_PROBE637_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE637_WIDTH : integer;
  attribute C_PROBE637_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE638_MU_CNT : integer;
  attribute C_PROBE638_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE638_TYPE : integer;
  attribute C_PROBE638_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE638_WIDTH : integer;
  attribute C_PROBE638_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE639_MU_CNT : integer;
  attribute C_PROBE639_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE639_TYPE : integer;
  attribute C_PROBE639_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE639_WIDTH : integer;
  attribute C_PROBE639_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE63_MU_CNT : integer;
  attribute C_PROBE63_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE63_TYPE : integer;
  attribute C_PROBE63_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE63_WIDTH : integer;
  attribute C_PROBE63_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE640_MU_CNT : integer;
  attribute C_PROBE640_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE640_TYPE : integer;
  attribute C_PROBE640_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE640_WIDTH : integer;
  attribute C_PROBE640_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE641_MU_CNT : integer;
  attribute C_PROBE641_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE641_TYPE : integer;
  attribute C_PROBE641_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE641_WIDTH : integer;
  attribute C_PROBE641_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE642_MU_CNT : integer;
  attribute C_PROBE642_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE642_TYPE : integer;
  attribute C_PROBE642_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE642_WIDTH : integer;
  attribute C_PROBE642_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE643_MU_CNT : integer;
  attribute C_PROBE643_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE643_TYPE : integer;
  attribute C_PROBE643_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE643_WIDTH : integer;
  attribute C_PROBE643_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE644_MU_CNT : integer;
  attribute C_PROBE644_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE644_TYPE : integer;
  attribute C_PROBE644_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE644_WIDTH : integer;
  attribute C_PROBE644_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE645_MU_CNT : integer;
  attribute C_PROBE645_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE645_TYPE : integer;
  attribute C_PROBE645_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE645_WIDTH : integer;
  attribute C_PROBE645_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE646_MU_CNT : integer;
  attribute C_PROBE646_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE646_TYPE : integer;
  attribute C_PROBE646_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE646_WIDTH : integer;
  attribute C_PROBE646_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE647_MU_CNT : integer;
  attribute C_PROBE647_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE647_TYPE : integer;
  attribute C_PROBE647_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE647_WIDTH : integer;
  attribute C_PROBE647_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE648_MU_CNT : integer;
  attribute C_PROBE648_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE648_TYPE : integer;
  attribute C_PROBE648_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE648_WIDTH : integer;
  attribute C_PROBE648_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE649_MU_CNT : integer;
  attribute C_PROBE649_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE649_TYPE : integer;
  attribute C_PROBE649_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE649_WIDTH : integer;
  attribute C_PROBE649_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE64_MU_CNT : integer;
  attribute C_PROBE64_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE64_TYPE : integer;
  attribute C_PROBE64_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE64_WIDTH : integer;
  attribute C_PROBE64_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE650_MU_CNT : integer;
  attribute C_PROBE650_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE650_TYPE : integer;
  attribute C_PROBE650_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE650_WIDTH : integer;
  attribute C_PROBE650_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE651_MU_CNT : integer;
  attribute C_PROBE651_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE651_TYPE : integer;
  attribute C_PROBE651_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE651_WIDTH : integer;
  attribute C_PROBE651_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE652_MU_CNT : integer;
  attribute C_PROBE652_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE652_TYPE : integer;
  attribute C_PROBE652_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE652_WIDTH : integer;
  attribute C_PROBE652_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE653_MU_CNT : integer;
  attribute C_PROBE653_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE653_TYPE : integer;
  attribute C_PROBE653_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE653_WIDTH : integer;
  attribute C_PROBE653_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE654_MU_CNT : integer;
  attribute C_PROBE654_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE654_TYPE : integer;
  attribute C_PROBE654_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE654_WIDTH : integer;
  attribute C_PROBE654_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE655_MU_CNT : integer;
  attribute C_PROBE655_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE655_TYPE : integer;
  attribute C_PROBE655_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE655_WIDTH : integer;
  attribute C_PROBE655_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE656_MU_CNT : integer;
  attribute C_PROBE656_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE656_TYPE : integer;
  attribute C_PROBE656_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE656_WIDTH : integer;
  attribute C_PROBE656_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE657_MU_CNT : integer;
  attribute C_PROBE657_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE657_TYPE : integer;
  attribute C_PROBE657_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE657_WIDTH : integer;
  attribute C_PROBE657_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE658_MU_CNT : integer;
  attribute C_PROBE658_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE658_TYPE : integer;
  attribute C_PROBE658_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE658_WIDTH : integer;
  attribute C_PROBE658_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE659_MU_CNT : integer;
  attribute C_PROBE659_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE659_TYPE : integer;
  attribute C_PROBE659_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE659_WIDTH : integer;
  attribute C_PROBE659_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE65_MU_CNT : integer;
  attribute C_PROBE65_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE65_TYPE : integer;
  attribute C_PROBE65_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE65_WIDTH : integer;
  attribute C_PROBE65_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE660_MU_CNT : integer;
  attribute C_PROBE660_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE660_TYPE : integer;
  attribute C_PROBE660_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE660_WIDTH : integer;
  attribute C_PROBE660_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE661_MU_CNT : integer;
  attribute C_PROBE661_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE661_TYPE : integer;
  attribute C_PROBE661_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE661_WIDTH : integer;
  attribute C_PROBE661_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE662_MU_CNT : integer;
  attribute C_PROBE662_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE662_TYPE : integer;
  attribute C_PROBE662_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE662_WIDTH : integer;
  attribute C_PROBE662_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE663_MU_CNT : integer;
  attribute C_PROBE663_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE663_TYPE : integer;
  attribute C_PROBE663_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE663_WIDTH : integer;
  attribute C_PROBE663_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE664_MU_CNT : integer;
  attribute C_PROBE664_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE664_TYPE : integer;
  attribute C_PROBE664_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE664_WIDTH : integer;
  attribute C_PROBE664_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE665_MU_CNT : integer;
  attribute C_PROBE665_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE665_TYPE : integer;
  attribute C_PROBE665_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE665_WIDTH : integer;
  attribute C_PROBE665_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE666_MU_CNT : integer;
  attribute C_PROBE666_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE666_TYPE : integer;
  attribute C_PROBE666_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE666_WIDTH : integer;
  attribute C_PROBE666_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE667_MU_CNT : integer;
  attribute C_PROBE667_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE667_TYPE : integer;
  attribute C_PROBE667_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE667_WIDTH : integer;
  attribute C_PROBE667_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE668_MU_CNT : integer;
  attribute C_PROBE668_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE668_TYPE : integer;
  attribute C_PROBE668_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE668_WIDTH : integer;
  attribute C_PROBE668_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE669_MU_CNT : integer;
  attribute C_PROBE669_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE669_TYPE : integer;
  attribute C_PROBE669_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE669_WIDTH : integer;
  attribute C_PROBE669_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE66_MU_CNT : integer;
  attribute C_PROBE66_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE66_TYPE : integer;
  attribute C_PROBE66_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE66_WIDTH : integer;
  attribute C_PROBE66_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE670_MU_CNT : integer;
  attribute C_PROBE670_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE670_TYPE : integer;
  attribute C_PROBE670_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE670_WIDTH : integer;
  attribute C_PROBE670_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE671_MU_CNT : integer;
  attribute C_PROBE671_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE671_TYPE : integer;
  attribute C_PROBE671_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE671_WIDTH : integer;
  attribute C_PROBE671_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE672_MU_CNT : integer;
  attribute C_PROBE672_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE672_TYPE : integer;
  attribute C_PROBE672_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE672_WIDTH : integer;
  attribute C_PROBE672_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE673_MU_CNT : integer;
  attribute C_PROBE673_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE673_TYPE : integer;
  attribute C_PROBE673_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE673_WIDTH : integer;
  attribute C_PROBE673_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE674_MU_CNT : integer;
  attribute C_PROBE674_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE674_TYPE : integer;
  attribute C_PROBE674_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE674_WIDTH : integer;
  attribute C_PROBE674_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE675_MU_CNT : integer;
  attribute C_PROBE675_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE675_TYPE : integer;
  attribute C_PROBE675_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE675_WIDTH : integer;
  attribute C_PROBE675_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE676_MU_CNT : integer;
  attribute C_PROBE676_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE676_TYPE : integer;
  attribute C_PROBE676_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE676_WIDTH : integer;
  attribute C_PROBE676_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE677_MU_CNT : integer;
  attribute C_PROBE677_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE677_TYPE : integer;
  attribute C_PROBE677_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE677_WIDTH : integer;
  attribute C_PROBE677_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE678_MU_CNT : integer;
  attribute C_PROBE678_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE678_TYPE : integer;
  attribute C_PROBE678_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE678_WIDTH : integer;
  attribute C_PROBE678_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE679_MU_CNT : integer;
  attribute C_PROBE679_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE679_TYPE : integer;
  attribute C_PROBE679_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE679_WIDTH : integer;
  attribute C_PROBE679_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE67_MU_CNT : integer;
  attribute C_PROBE67_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE67_TYPE : integer;
  attribute C_PROBE67_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE67_WIDTH : integer;
  attribute C_PROBE67_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE680_MU_CNT : integer;
  attribute C_PROBE680_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE680_TYPE : integer;
  attribute C_PROBE680_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE680_WIDTH : integer;
  attribute C_PROBE680_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE681_MU_CNT : integer;
  attribute C_PROBE681_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE681_TYPE : integer;
  attribute C_PROBE681_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE681_WIDTH : integer;
  attribute C_PROBE681_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE682_MU_CNT : integer;
  attribute C_PROBE682_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE682_TYPE : integer;
  attribute C_PROBE682_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE682_WIDTH : integer;
  attribute C_PROBE682_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE683_MU_CNT : integer;
  attribute C_PROBE683_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE683_TYPE : integer;
  attribute C_PROBE683_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE683_WIDTH : integer;
  attribute C_PROBE683_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE684_MU_CNT : integer;
  attribute C_PROBE684_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE684_TYPE : integer;
  attribute C_PROBE684_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE684_WIDTH : integer;
  attribute C_PROBE684_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE685_MU_CNT : integer;
  attribute C_PROBE685_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE685_TYPE : integer;
  attribute C_PROBE685_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE685_WIDTH : integer;
  attribute C_PROBE685_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE686_MU_CNT : integer;
  attribute C_PROBE686_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE686_TYPE : integer;
  attribute C_PROBE686_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE686_WIDTH : integer;
  attribute C_PROBE686_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE687_MU_CNT : integer;
  attribute C_PROBE687_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE687_TYPE : integer;
  attribute C_PROBE687_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE687_WIDTH : integer;
  attribute C_PROBE687_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE688_MU_CNT : integer;
  attribute C_PROBE688_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE688_TYPE : integer;
  attribute C_PROBE688_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE688_WIDTH : integer;
  attribute C_PROBE688_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE689_MU_CNT : integer;
  attribute C_PROBE689_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE689_TYPE : integer;
  attribute C_PROBE689_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE689_WIDTH : integer;
  attribute C_PROBE689_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE68_MU_CNT : integer;
  attribute C_PROBE68_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE68_TYPE : integer;
  attribute C_PROBE68_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE68_WIDTH : integer;
  attribute C_PROBE68_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE690_MU_CNT : integer;
  attribute C_PROBE690_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE690_TYPE : integer;
  attribute C_PROBE690_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE690_WIDTH : integer;
  attribute C_PROBE690_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE691_MU_CNT : integer;
  attribute C_PROBE691_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE691_TYPE : integer;
  attribute C_PROBE691_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE691_WIDTH : integer;
  attribute C_PROBE691_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE692_MU_CNT : integer;
  attribute C_PROBE692_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE692_TYPE : integer;
  attribute C_PROBE692_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE692_WIDTH : integer;
  attribute C_PROBE692_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE693_MU_CNT : integer;
  attribute C_PROBE693_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE693_TYPE : integer;
  attribute C_PROBE693_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE693_WIDTH : integer;
  attribute C_PROBE693_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE694_MU_CNT : integer;
  attribute C_PROBE694_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE694_TYPE : integer;
  attribute C_PROBE694_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE694_WIDTH : integer;
  attribute C_PROBE694_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE695_MU_CNT : integer;
  attribute C_PROBE695_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE695_TYPE : integer;
  attribute C_PROBE695_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE695_WIDTH : integer;
  attribute C_PROBE695_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE696_MU_CNT : integer;
  attribute C_PROBE696_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE696_TYPE : integer;
  attribute C_PROBE696_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE696_WIDTH : integer;
  attribute C_PROBE696_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE697_MU_CNT : integer;
  attribute C_PROBE697_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE697_TYPE : integer;
  attribute C_PROBE697_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE697_WIDTH : integer;
  attribute C_PROBE697_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE698_MU_CNT : integer;
  attribute C_PROBE698_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE698_TYPE : integer;
  attribute C_PROBE698_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE698_WIDTH : integer;
  attribute C_PROBE698_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE699_MU_CNT : integer;
  attribute C_PROBE699_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE699_TYPE : integer;
  attribute C_PROBE699_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE699_WIDTH : integer;
  attribute C_PROBE699_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE69_MU_CNT : integer;
  attribute C_PROBE69_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE69_TYPE : integer;
  attribute C_PROBE69_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE69_WIDTH : integer;
  attribute C_PROBE69_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE6_MU_CNT : integer;
  attribute C_PROBE6_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE6_TYPE : integer;
  attribute C_PROBE6_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE6_WIDTH : integer;
  attribute C_PROBE6_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE700_MU_CNT : integer;
  attribute C_PROBE700_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE700_TYPE : integer;
  attribute C_PROBE700_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE700_WIDTH : integer;
  attribute C_PROBE700_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE701_MU_CNT : integer;
  attribute C_PROBE701_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE701_TYPE : integer;
  attribute C_PROBE701_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE701_WIDTH : integer;
  attribute C_PROBE701_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE702_MU_CNT : integer;
  attribute C_PROBE702_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE702_TYPE : integer;
  attribute C_PROBE702_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE702_WIDTH : integer;
  attribute C_PROBE702_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE703_MU_CNT : integer;
  attribute C_PROBE703_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE703_TYPE : integer;
  attribute C_PROBE703_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE703_WIDTH : integer;
  attribute C_PROBE703_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE704_MU_CNT : integer;
  attribute C_PROBE704_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE704_TYPE : integer;
  attribute C_PROBE704_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE704_WIDTH : integer;
  attribute C_PROBE704_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE705_MU_CNT : integer;
  attribute C_PROBE705_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE705_TYPE : integer;
  attribute C_PROBE705_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE705_WIDTH : integer;
  attribute C_PROBE705_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE706_MU_CNT : integer;
  attribute C_PROBE706_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE706_TYPE : integer;
  attribute C_PROBE706_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE706_WIDTH : integer;
  attribute C_PROBE706_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE707_MU_CNT : integer;
  attribute C_PROBE707_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE707_TYPE : integer;
  attribute C_PROBE707_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE707_WIDTH : integer;
  attribute C_PROBE707_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE708_MU_CNT : integer;
  attribute C_PROBE708_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE708_TYPE : integer;
  attribute C_PROBE708_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE708_WIDTH : integer;
  attribute C_PROBE708_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE709_MU_CNT : integer;
  attribute C_PROBE709_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE709_TYPE : integer;
  attribute C_PROBE709_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE709_WIDTH : integer;
  attribute C_PROBE709_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE70_MU_CNT : integer;
  attribute C_PROBE70_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE70_TYPE : integer;
  attribute C_PROBE70_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE70_WIDTH : integer;
  attribute C_PROBE70_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE710_MU_CNT : integer;
  attribute C_PROBE710_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE710_TYPE : integer;
  attribute C_PROBE710_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE710_WIDTH : integer;
  attribute C_PROBE710_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE711_MU_CNT : integer;
  attribute C_PROBE711_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE711_TYPE : integer;
  attribute C_PROBE711_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE711_WIDTH : integer;
  attribute C_PROBE711_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE712_MU_CNT : integer;
  attribute C_PROBE712_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE712_TYPE : integer;
  attribute C_PROBE712_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE712_WIDTH : integer;
  attribute C_PROBE712_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE713_MU_CNT : integer;
  attribute C_PROBE713_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE713_TYPE : integer;
  attribute C_PROBE713_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE713_WIDTH : integer;
  attribute C_PROBE713_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE714_MU_CNT : integer;
  attribute C_PROBE714_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE714_TYPE : integer;
  attribute C_PROBE714_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE714_WIDTH : integer;
  attribute C_PROBE714_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE715_MU_CNT : integer;
  attribute C_PROBE715_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE715_TYPE : integer;
  attribute C_PROBE715_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE715_WIDTH : integer;
  attribute C_PROBE715_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE716_MU_CNT : integer;
  attribute C_PROBE716_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE716_TYPE : integer;
  attribute C_PROBE716_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE716_WIDTH : integer;
  attribute C_PROBE716_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE717_MU_CNT : integer;
  attribute C_PROBE717_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE717_TYPE : integer;
  attribute C_PROBE717_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE717_WIDTH : integer;
  attribute C_PROBE717_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE718_MU_CNT : integer;
  attribute C_PROBE718_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE718_TYPE : integer;
  attribute C_PROBE718_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE718_WIDTH : integer;
  attribute C_PROBE718_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE719_MU_CNT : integer;
  attribute C_PROBE719_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE719_TYPE : integer;
  attribute C_PROBE719_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE719_WIDTH : integer;
  attribute C_PROBE719_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE71_MU_CNT : integer;
  attribute C_PROBE71_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE71_TYPE : integer;
  attribute C_PROBE71_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE71_WIDTH : integer;
  attribute C_PROBE71_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE720_MU_CNT : integer;
  attribute C_PROBE720_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE720_TYPE : integer;
  attribute C_PROBE720_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE720_WIDTH : integer;
  attribute C_PROBE720_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE721_MU_CNT : integer;
  attribute C_PROBE721_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE721_TYPE : integer;
  attribute C_PROBE721_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE721_WIDTH : integer;
  attribute C_PROBE721_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE722_MU_CNT : integer;
  attribute C_PROBE722_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE722_TYPE : integer;
  attribute C_PROBE722_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE722_WIDTH : integer;
  attribute C_PROBE722_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE723_MU_CNT : integer;
  attribute C_PROBE723_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE723_TYPE : integer;
  attribute C_PROBE723_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE723_WIDTH : integer;
  attribute C_PROBE723_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE724_MU_CNT : integer;
  attribute C_PROBE724_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE724_TYPE : integer;
  attribute C_PROBE724_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE724_WIDTH : integer;
  attribute C_PROBE724_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE725_MU_CNT : integer;
  attribute C_PROBE725_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE725_TYPE : integer;
  attribute C_PROBE725_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE725_WIDTH : integer;
  attribute C_PROBE725_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE726_MU_CNT : integer;
  attribute C_PROBE726_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE726_TYPE : integer;
  attribute C_PROBE726_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE726_WIDTH : integer;
  attribute C_PROBE726_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE727_MU_CNT : integer;
  attribute C_PROBE727_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE727_TYPE : integer;
  attribute C_PROBE727_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE727_WIDTH : integer;
  attribute C_PROBE727_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE728_MU_CNT : integer;
  attribute C_PROBE728_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE728_TYPE : integer;
  attribute C_PROBE728_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE728_WIDTH : integer;
  attribute C_PROBE728_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE729_MU_CNT : integer;
  attribute C_PROBE729_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE729_TYPE : integer;
  attribute C_PROBE729_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE729_WIDTH : integer;
  attribute C_PROBE729_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE72_MU_CNT : integer;
  attribute C_PROBE72_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE72_TYPE : integer;
  attribute C_PROBE72_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE72_WIDTH : integer;
  attribute C_PROBE72_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE730_MU_CNT : integer;
  attribute C_PROBE730_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE730_TYPE : integer;
  attribute C_PROBE730_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE730_WIDTH : integer;
  attribute C_PROBE730_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE731_MU_CNT : integer;
  attribute C_PROBE731_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE731_TYPE : integer;
  attribute C_PROBE731_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE731_WIDTH : integer;
  attribute C_PROBE731_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE732_MU_CNT : integer;
  attribute C_PROBE732_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE732_TYPE : integer;
  attribute C_PROBE732_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE732_WIDTH : integer;
  attribute C_PROBE732_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE733_MU_CNT : integer;
  attribute C_PROBE733_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE733_TYPE : integer;
  attribute C_PROBE733_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE733_WIDTH : integer;
  attribute C_PROBE733_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE734_MU_CNT : integer;
  attribute C_PROBE734_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE734_TYPE : integer;
  attribute C_PROBE734_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE734_WIDTH : integer;
  attribute C_PROBE734_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE735_MU_CNT : integer;
  attribute C_PROBE735_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE735_TYPE : integer;
  attribute C_PROBE735_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE735_WIDTH : integer;
  attribute C_PROBE735_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE736_MU_CNT : integer;
  attribute C_PROBE736_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE736_TYPE : integer;
  attribute C_PROBE736_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE736_WIDTH : integer;
  attribute C_PROBE736_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE737_MU_CNT : integer;
  attribute C_PROBE737_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE737_TYPE : integer;
  attribute C_PROBE737_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE737_WIDTH : integer;
  attribute C_PROBE737_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE738_MU_CNT : integer;
  attribute C_PROBE738_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE738_TYPE : integer;
  attribute C_PROBE738_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE738_WIDTH : integer;
  attribute C_PROBE738_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE739_MU_CNT : integer;
  attribute C_PROBE739_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE739_TYPE : integer;
  attribute C_PROBE739_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE739_WIDTH : integer;
  attribute C_PROBE739_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE73_MU_CNT : integer;
  attribute C_PROBE73_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE73_TYPE : integer;
  attribute C_PROBE73_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE73_WIDTH : integer;
  attribute C_PROBE73_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE740_MU_CNT : integer;
  attribute C_PROBE740_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE740_TYPE : integer;
  attribute C_PROBE740_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE740_WIDTH : integer;
  attribute C_PROBE740_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE741_MU_CNT : integer;
  attribute C_PROBE741_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE741_TYPE : integer;
  attribute C_PROBE741_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE741_WIDTH : integer;
  attribute C_PROBE741_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE742_MU_CNT : integer;
  attribute C_PROBE742_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE742_TYPE : integer;
  attribute C_PROBE742_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE742_WIDTH : integer;
  attribute C_PROBE742_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE743_MU_CNT : integer;
  attribute C_PROBE743_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE743_TYPE : integer;
  attribute C_PROBE743_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE743_WIDTH : integer;
  attribute C_PROBE743_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE744_MU_CNT : integer;
  attribute C_PROBE744_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE744_TYPE : integer;
  attribute C_PROBE744_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE744_WIDTH : integer;
  attribute C_PROBE744_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE745_MU_CNT : integer;
  attribute C_PROBE745_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE745_TYPE : integer;
  attribute C_PROBE745_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE745_WIDTH : integer;
  attribute C_PROBE745_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE746_MU_CNT : integer;
  attribute C_PROBE746_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE746_TYPE : integer;
  attribute C_PROBE746_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE746_WIDTH : integer;
  attribute C_PROBE746_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE747_MU_CNT : integer;
  attribute C_PROBE747_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE747_TYPE : integer;
  attribute C_PROBE747_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE747_WIDTH : integer;
  attribute C_PROBE747_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE748_MU_CNT : integer;
  attribute C_PROBE748_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE748_TYPE : integer;
  attribute C_PROBE748_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE748_WIDTH : integer;
  attribute C_PROBE748_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE749_MU_CNT : integer;
  attribute C_PROBE749_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE749_TYPE : integer;
  attribute C_PROBE749_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE749_WIDTH : integer;
  attribute C_PROBE749_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE74_MU_CNT : integer;
  attribute C_PROBE74_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE74_TYPE : integer;
  attribute C_PROBE74_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE74_WIDTH : integer;
  attribute C_PROBE74_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE750_MU_CNT : integer;
  attribute C_PROBE750_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE750_TYPE : integer;
  attribute C_PROBE750_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE750_WIDTH : integer;
  attribute C_PROBE750_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE751_MU_CNT : integer;
  attribute C_PROBE751_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE751_TYPE : integer;
  attribute C_PROBE751_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE751_WIDTH : integer;
  attribute C_PROBE751_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE752_MU_CNT : integer;
  attribute C_PROBE752_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE752_TYPE : integer;
  attribute C_PROBE752_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE752_WIDTH : integer;
  attribute C_PROBE752_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE753_MU_CNT : integer;
  attribute C_PROBE753_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE753_TYPE : integer;
  attribute C_PROBE753_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE753_WIDTH : integer;
  attribute C_PROBE753_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE754_MU_CNT : integer;
  attribute C_PROBE754_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE754_TYPE : integer;
  attribute C_PROBE754_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE754_WIDTH : integer;
  attribute C_PROBE754_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE755_MU_CNT : integer;
  attribute C_PROBE755_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE755_TYPE : integer;
  attribute C_PROBE755_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE755_WIDTH : integer;
  attribute C_PROBE755_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE756_MU_CNT : integer;
  attribute C_PROBE756_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE756_TYPE : integer;
  attribute C_PROBE756_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE756_WIDTH : integer;
  attribute C_PROBE756_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE757_MU_CNT : integer;
  attribute C_PROBE757_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE757_TYPE : integer;
  attribute C_PROBE757_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE757_WIDTH : integer;
  attribute C_PROBE757_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE758_MU_CNT : integer;
  attribute C_PROBE758_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE758_TYPE : integer;
  attribute C_PROBE758_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE758_WIDTH : integer;
  attribute C_PROBE758_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE759_MU_CNT : integer;
  attribute C_PROBE759_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE759_TYPE : integer;
  attribute C_PROBE759_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE759_WIDTH : integer;
  attribute C_PROBE759_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE75_MU_CNT : integer;
  attribute C_PROBE75_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE75_TYPE : integer;
  attribute C_PROBE75_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE75_WIDTH : integer;
  attribute C_PROBE75_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE760_MU_CNT : integer;
  attribute C_PROBE760_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE760_TYPE : integer;
  attribute C_PROBE760_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE760_WIDTH : integer;
  attribute C_PROBE760_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE761_MU_CNT : integer;
  attribute C_PROBE761_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE761_TYPE : integer;
  attribute C_PROBE761_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE761_WIDTH : integer;
  attribute C_PROBE761_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE762_MU_CNT : integer;
  attribute C_PROBE762_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE762_TYPE : integer;
  attribute C_PROBE762_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE762_WIDTH : integer;
  attribute C_PROBE762_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE763_MU_CNT : integer;
  attribute C_PROBE763_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE763_TYPE : integer;
  attribute C_PROBE763_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE763_WIDTH : integer;
  attribute C_PROBE763_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE764_MU_CNT : integer;
  attribute C_PROBE764_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE764_TYPE : integer;
  attribute C_PROBE764_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE764_WIDTH : integer;
  attribute C_PROBE764_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE765_MU_CNT : integer;
  attribute C_PROBE765_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE765_TYPE : integer;
  attribute C_PROBE765_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE765_WIDTH : integer;
  attribute C_PROBE765_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE766_MU_CNT : integer;
  attribute C_PROBE766_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE766_TYPE : integer;
  attribute C_PROBE766_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE766_WIDTH : integer;
  attribute C_PROBE766_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE767_MU_CNT : integer;
  attribute C_PROBE767_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE767_TYPE : integer;
  attribute C_PROBE767_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE767_WIDTH : integer;
  attribute C_PROBE767_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE768_MU_CNT : integer;
  attribute C_PROBE768_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE768_TYPE : integer;
  attribute C_PROBE768_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE768_WIDTH : integer;
  attribute C_PROBE768_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE769_MU_CNT : integer;
  attribute C_PROBE769_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE769_TYPE : integer;
  attribute C_PROBE769_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE769_WIDTH : integer;
  attribute C_PROBE769_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE76_MU_CNT : integer;
  attribute C_PROBE76_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE76_TYPE : integer;
  attribute C_PROBE76_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE76_WIDTH : integer;
  attribute C_PROBE76_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE770_MU_CNT : integer;
  attribute C_PROBE770_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE770_TYPE : integer;
  attribute C_PROBE770_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE770_WIDTH : integer;
  attribute C_PROBE770_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE771_MU_CNT : integer;
  attribute C_PROBE771_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE771_TYPE : integer;
  attribute C_PROBE771_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE771_WIDTH : integer;
  attribute C_PROBE771_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE772_MU_CNT : integer;
  attribute C_PROBE772_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE772_TYPE : integer;
  attribute C_PROBE772_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE772_WIDTH : integer;
  attribute C_PROBE772_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE773_MU_CNT : integer;
  attribute C_PROBE773_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE773_TYPE : integer;
  attribute C_PROBE773_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE773_WIDTH : integer;
  attribute C_PROBE773_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE774_MU_CNT : integer;
  attribute C_PROBE774_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE774_TYPE : integer;
  attribute C_PROBE774_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE774_WIDTH : integer;
  attribute C_PROBE774_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE775_MU_CNT : integer;
  attribute C_PROBE775_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE775_TYPE : integer;
  attribute C_PROBE775_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE775_WIDTH : integer;
  attribute C_PROBE775_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE776_MU_CNT : integer;
  attribute C_PROBE776_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE776_TYPE : integer;
  attribute C_PROBE776_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE776_WIDTH : integer;
  attribute C_PROBE776_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE777_MU_CNT : integer;
  attribute C_PROBE777_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE777_TYPE : integer;
  attribute C_PROBE777_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE777_WIDTH : integer;
  attribute C_PROBE777_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE778_MU_CNT : integer;
  attribute C_PROBE778_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE778_TYPE : integer;
  attribute C_PROBE778_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE778_WIDTH : integer;
  attribute C_PROBE778_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE779_MU_CNT : integer;
  attribute C_PROBE779_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE779_TYPE : integer;
  attribute C_PROBE779_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE779_WIDTH : integer;
  attribute C_PROBE779_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE77_MU_CNT : integer;
  attribute C_PROBE77_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE77_TYPE : integer;
  attribute C_PROBE77_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE77_WIDTH : integer;
  attribute C_PROBE77_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE780_MU_CNT : integer;
  attribute C_PROBE780_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE780_TYPE : integer;
  attribute C_PROBE780_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE780_WIDTH : integer;
  attribute C_PROBE780_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE781_MU_CNT : integer;
  attribute C_PROBE781_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE781_TYPE : integer;
  attribute C_PROBE781_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE781_WIDTH : integer;
  attribute C_PROBE781_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE782_MU_CNT : integer;
  attribute C_PROBE782_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE782_TYPE : integer;
  attribute C_PROBE782_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE782_WIDTH : integer;
  attribute C_PROBE782_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE783_MU_CNT : integer;
  attribute C_PROBE783_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE783_TYPE : integer;
  attribute C_PROBE783_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE783_WIDTH : integer;
  attribute C_PROBE783_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE784_MU_CNT : integer;
  attribute C_PROBE784_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE784_TYPE : integer;
  attribute C_PROBE784_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE784_WIDTH : integer;
  attribute C_PROBE784_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE785_MU_CNT : integer;
  attribute C_PROBE785_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE785_TYPE : integer;
  attribute C_PROBE785_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE785_WIDTH : integer;
  attribute C_PROBE785_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE786_MU_CNT : integer;
  attribute C_PROBE786_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE786_TYPE : integer;
  attribute C_PROBE786_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE786_WIDTH : integer;
  attribute C_PROBE786_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE787_MU_CNT : integer;
  attribute C_PROBE787_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE787_TYPE : integer;
  attribute C_PROBE787_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE787_WIDTH : integer;
  attribute C_PROBE787_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE788_MU_CNT : integer;
  attribute C_PROBE788_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE788_TYPE : integer;
  attribute C_PROBE788_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE788_WIDTH : integer;
  attribute C_PROBE788_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE789_MU_CNT : integer;
  attribute C_PROBE789_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE789_TYPE : integer;
  attribute C_PROBE789_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE789_WIDTH : integer;
  attribute C_PROBE789_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE78_MU_CNT : integer;
  attribute C_PROBE78_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE78_TYPE : integer;
  attribute C_PROBE78_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE78_WIDTH : integer;
  attribute C_PROBE78_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE790_MU_CNT : integer;
  attribute C_PROBE790_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE790_TYPE : integer;
  attribute C_PROBE790_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE790_WIDTH : integer;
  attribute C_PROBE790_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE791_MU_CNT : integer;
  attribute C_PROBE791_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE791_TYPE : integer;
  attribute C_PROBE791_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE791_WIDTH : integer;
  attribute C_PROBE791_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE792_MU_CNT : integer;
  attribute C_PROBE792_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE792_TYPE : integer;
  attribute C_PROBE792_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE792_WIDTH : integer;
  attribute C_PROBE792_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE793_MU_CNT : integer;
  attribute C_PROBE793_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE793_TYPE : integer;
  attribute C_PROBE793_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE793_WIDTH : integer;
  attribute C_PROBE793_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE794_MU_CNT : integer;
  attribute C_PROBE794_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE794_TYPE : integer;
  attribute C_PROBE794_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE794_WIDTH : integer;
  attribute C_PROBE794_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE795_MU_CNT : integer;
  attribute C_PROBE795_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE795_TYPE : integer;
  attribute C_PROBE795_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE795_WIDTH : integer;
  attribute C_PROBE795_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE796_MU_CNT : integer;
  attribute C_PROBE796_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE796_TYPE : integer;
  attribute C_PROBE796_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE796_WIDTH : integer;
  attribute C_PROBE796_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE797_MU_CNT : integer;
  attribute C_PROBE797_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE797_TYPE : integer;
  attribute C_PROBE797_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE797_WIDTH : integer;
  attribute C_PROBE797_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE798_MU_CNT : integer;
  attribute C_PROBE798_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE798_TYPE : integer;
  attribute C_PROBE798_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE798_WIDTH : integer;
  attribute C_PROBE798_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE799_MU_CNT : integer;
  attribute C_PROBE799_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE799_TYPE : integer;
  attribute C_PROBE799_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE799_WIDTH : integer;
  attribute C_PROBE799_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE79_MU_CNT : integer;
  attribute C_PROBE79_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE79_TYPE : integer;
  attribute C_PROBE79_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE79_WIDTH : integer;
  attribute C_PROBE79_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE7_MU_CNT : integer;
  attribute C_PROBE7_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE7_TYPE : integer;
  attribute C_PROBE7_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE7_WIDTH : integer;
  attribute C_PROBE7_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE800_MU_CNT : integer;
  attribute C_PROBE800_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE800_TYPE : integer;
  attribute C_PROBE800_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE800_WIDTH : integer;
  attribute C_PROBE800_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE801_MU_CNT : integer;
  attribute C_PROBE801_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE801_TYPE : integer;
  attribute C_PROBE801_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE801_WIDTH : integer;
  attribute C_PROBE801_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE802_MU_CNT : integer;
  attribute C_PROBE802_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE802_TYPE : integer;
  attribute C_PROBE802_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE802_WIDTH : integer;
  attribute C_PROBE802_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE803_MU_CNT : integer;
  attribute C_PROBE803_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE803_TYPE : integer;
  attribute C_PROBE803_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE803_WIDTH : integer;
  attribute C_PROBE803_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE804_MU_CNT : integer;
  attribute C_PROBE804_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE804_TYPE : integer;
  attribute C_PROBE804_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE804_WIDTH : integer;
  attribute C_PROBE804_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE805_MU_CNT : integer;
  attribute C_PROBE805_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE805_TYPE : integer;
  attribute C_PROBE805_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE805_WIDTH : integer;
  attribute C_PROBE805_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE806_MU_CNT : integer;
  attribute C_PROBE806_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE806_TYPE : integer;
  attribute C_PROBE806_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE806_WIDTH : integer;
  attribute C_PROBE806_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE807_MU_CNT : integer;
  attribute C_PROBE807_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE807_TYPE : integer;
  attribute C_PROBE807_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE807_WIDTH : integer;
  attribute C_PROBE807_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE808_MU_CNT : integer;
  attribute C_PROBE808_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE808_TYPE : integer;
  attribute C_PROBE808_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE808_WIDTH : integer;
  attribute C_PROBE808_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE809_MU_CNT : integer;
  attribute C_PROBE809_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE809_TYPE : integer;
  attribute C_PROBE809_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE809_WIDTH : integer;
  attribute C_PROBE809_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE80_MU_CNT : integer;
  attribute C_PROBE80_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE80_TYPE : integer;
  attribute C_PROBE80_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE80_WIDTH : integer;
  attribute C_PROBE80_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE810_MU_CNT : integer;
  attribute C_PROBE810_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE810_TYPE : integer;
  attribute C_PROBE810_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE810_WIDTH : integer;
  attribute C_PROBE810_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE811_MU_CNT : integer;
  attribute C_PROBE811_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE811_TYPE : integer;
  attribute C_PROBE811_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE811_WIDTH : integer;
  attribute C_PROBE811_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE812_MU_CNT : integer;
  attribute C_PROBE812_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE812_TYPE : integer;
  attribute C_PROBE812_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE812_WIDTH : integer;
  attribute C_PROBE812_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE813_MU_CNT : integer;
  attribute C_PROBE813_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE813_TYPE : integer;
  attribute C_PROBE813_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE813_WIDTH : integer;
  attribute C_PROBE813_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE814_MU_CNT : integer;
  attribute C_PROBE814_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE814_TYPE : integer;
  attribute C_PROBE814_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE814_WIDTH : integer;
  attribute C_PROBE814_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE815_MU_CNT : integer;
  attribute C_PROBE815_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE815_TYPE : integer;
  attribute C_PROBE815_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE815_WIDTH : integer;
  attribute C_PROBE815_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE816_MU_CNT : integer;
  attribute C_PROBE816_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE816_TYPE : integer;
  attribute C_PROBE816_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE816_WIDTH : integer;
  attribute C_PROBE816_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE817_MU_CNT : integer;
  attribute C_PROBE817_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE817_TYPE : integer;
  attribute C_PROBE817_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE817_WIDTH : integer;
  attribute C_PROBE817_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE818_MU_CNT : integer;
  attribute C_PROBE818_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE818_TYPE : integer;
  attribute C_PROBE818_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE818_WIDTH : integer;
  attribute C_PROBE818_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE819_MU_CNT : integer;
  attribute C_PROBE819_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE819_TYPE : integer;
  attribute C_PROBE819_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE819_WIDTH : integer;
  attribute C_PROBE819_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE81_MU_CNT : integer;
  attribute C_PROBE81_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE81_TYPE : integer;
  attribute C_PROBE81_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE81_WIDTH : integer;
  attribute C_PROBE81_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE820_MU_CNT : integer;
  attribute C_PROBE820_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE820_TYPE : integer;
  attribute C_PROBE820_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE820_WIDTH : integer;
  attribute C_PROBE820_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE821_MU_CNT : integer;
  attribute C_PROBE821_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE821_TYPE : integer;
  attribute C_PROBE821_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE821_WIDTH : integer;
  attribute C_PROBE821_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE822_MU_CNT : integer;
  attribute C_PROBE822_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE822_TYPE : integer;
  attribute C_PROBE822_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE822_WIDTH : integer;
  attribute C_PROBE822_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE823_MU_CNT : integer;
  attribute C_PROBE823_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE823_TYPE : integer;
  attribute C_PROBE823_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE823_WIDTH : integer;
  attribute C_PROBE823_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE824_MU_CNT : integer;
  attribute C_PROBE824_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE824_TYPE : integer;
  attribute C_PROBE824_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE824_WIDTH : integer;
  attribute C_PROBE824_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE825_MU_CNT : integer;
  attribute C_PROBE825_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE825_TYPE : integer;
  attribute C_PROBE825_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE825_WIDTH : integer;
  attribute C_PROBE825_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE826_MU_CNT : integer;
  attribute C_PROBE826_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE826_TYPE : integer;
  attribute C_PROBE826_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE826_WIDTH : integer;
  attribute C_PROBE826_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE827_MU_CNT : integer;
  attribute C_PROBE827_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE827_TYPE : integer;
  attribute C_PROBE827_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE827_WIDTH : integer;
  attribute C_PROBE827_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE828_MU_CNT : integer;
  attribute C_PROBE828_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE828_TYPE : integer;
  attribute C_PROBE828_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE828_WIDTH : integer;
  attribute C_PROBE828_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE829_MU_CNT : integer;
  attribute C_PROBE829_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE829_TYPE : integer;
  attribute C_PROBE829_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE829_WIDTH : integer;
  attribute C_PROBE829_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE82_MU_CNT : integer;
  attribute C_PROBE82_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE82_TYPE : integer;
  attribute C_PROBE82_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE82_WIDTH : integer;
  attribute C_PROBE82_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE830_MU_CNT : integer;
  attribute C_PROBE830_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE830_TYPE : integer;
  attribute C_PROBE830_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE830_WIDTH : integer;
  attribute C_PROBE830_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE831_MU_CNT : integer;
  attribute C_PROBE831_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE831_TYPE : integer;
  attribute C_PROBE831_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE831_WIDTH : integer;
  attribute C_PROBE831_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE832_MU_CNT : integer;
  attribute C_PROBE832_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE832_TYPE : integer;
  attribute C_PROBE832_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE832_WIDTH : integer;
  attribute C_PROBE832_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE833_MU_CNT : integer;
  attribute C_PROBE833_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE833_TYPE : integer;
  attribute C_PROBE833_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE833_WIDTH : integer;
  attribute C_PROBE833_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE834_MU_CNT : integer;
  attribute C_PROBE834_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE834_TYPE : integer;
  attribute C_PROBE834_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE834_WIDTH : integer;
  attribute C_PROBE834_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE835_MU_CNT : integer;
  attribute C_PROBE835_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE835_TYPE : integer;
  attribute C_PROBE835_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE835_WIDTH : integer;
  attribute C_PROBE835_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE836_MU_CNT : integer;
  attribute C_PROBE836_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE836_TYPE : integer;
  attribute C_PROBE836_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE836_WIDTH : integer;
  attribute C_PROBE836_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE837_MU_CNT : integer;
  attribute C_PROBE837_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE837_TYPE : integer;
  attribute C_PROBE837_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE837_WIDTH : integer;
  attribute C_PROBE837_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE838_MU_CNT : integer;
  attribute C_PROBE838_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE838_TYPE : integer;
  attribute C_PROBE838_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE838_WIDTH : integer;
  attribute C_PROBE838_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE839_MU_CNT : integer;
  attribute C_PROBE839_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE839_TYPE : integer;
  attribute C_PROBE839_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE839_WIDTH : integer;
  attribute C_PROBE839_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE83_MU_CNT : integer;
  attribute C_PROBE83_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE83_TYPE : integer;
  attribute C_PROBE83_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE83_WIDTH : integer;
  attribute C_PROBE83_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE840_MU_CNT : integer;
  attribute C_PROBE840_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE840_TYPE : integer;
  attribute C_PROBE840_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE840_WIDTH : integer;
  attribute C_PROBE840_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE841_MU_CNT : integer;
  attribute C_PROBE841_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE841_TYPE : integer;
  attribute C_PROBE841_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE841_WIDTH : integer;
  attribute C_PROBE841_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE842_MU_CNT : integer;
  attribute C_PROBE842_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE842_TYPE : integer;
  attribute C_PROBE842_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE842_WIDTH : integer;
  attribute C_PROBE842_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE843_MU_CNT : integer;
  attribute C_PROBE843_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE843_TYPE : integer;
  attribute C_PROBE843_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE843_WIDTH : integer;
  attribute C_PROBE843_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE844_MU_CNT : integer;
  attribute C_PROBE844_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE844_TYPE : integer;
  attribute C_PROBE844_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE844_WIDTH : integer;
  attribute C_PROBE844_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE845_MU_CNT : integer;
  attribute C_PROBE845_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE845_TYPE : integer;
  attribute C_PROBE845_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE845_WIDTH : integer;
  attribute C_PROBE845_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE846_MU_CNT : integer;
  attribute C_PROBE846_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE846_TYPE : integer;
  attribute C_PROBE846_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE846_WIDTH : integer;
  attribute C_PROBE846_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE847_MU_CNT : integer;
  attribute C_PROBE847_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE847_TYPE : integer;
  attribute C_PROBE847_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE847_WIDTH : integer;
  attribute C_PROBE847_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE848_MU_CNT : integer;
  attribute C_PROBE848_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE848_TYPE : integer;
  attribute C_PROBE848_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE848_WIDTH : integer;
  attribute C_PROBE848_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE849_MU_CNT : integer;
  attribute C_PROBE849_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE849_TYPE : integer;
  attribute C_PROBE849_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE849_WIDTH : integer;
  attribute C_PROBE849_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE84_MU_CNT : integer;
  attribute C_PROBE84_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE84_TYPE : integer;
  attribute C_PROBE84_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE84_WIDTH : integer;
  attribute C_PROBE84_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE850_MU_CNT : integer;
  attribute C_PROBE850_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE850_TYPE : integer;
  attribute C_PROBE850_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE850_WIDTH : integer;
  attribute C_PROBE850_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE851_MU_CNT : integer;
  attribute C_PROBE851_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE851_TYPE : integer;
  attribute C_PROBE851_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE851_WIDTH : integer;
  attribute C_PROBE851_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE852_MU_CNT : integer;
  attribute C_PROBE852_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE852_TYPE : integer;
  attribute C_PROBE852_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE852_WIDTH : integer;
  attribute C_PROBE852_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE853_MU_CNT : integer;
  attribute C_PROBE853_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE853_TYPE : integer;
  attribute C_PROBE853_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE853_WIDTH : integer;
  attribute C_PROBE853_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE854_MU_CNT : integer;
  attribute C_PROBE854_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE854_TYPE : integer;
  attribute C_PROBE854_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE854_WIDTH : integer;
  attribute C_PROBE854_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE855_MU_CNT : integer;
  attribute C_PROBE855_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE855_TYPE : integer;
  attribute C_PROBE855_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE855_WIDTH : integer;
  attribute C_PROBE855_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE856_MU_CNT : integer;
  attribute C_PROBE856_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE856_TYPE : integer;
  attribute C_PROBE856_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE856_WIDTH : integer;
  attribute C_PROBE856_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE857_MU_CNT : integer;
  attribute C_PROBE857_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE857_TYPE : integer;
  attribute C_PROBE857_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE857_WIDTH : integer;
  attribute C_PROBE857_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE858_MU_CNT : integer;
  attribute C_PROBE858_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE858_TYPE : integer;
  attribute C_PROBE858_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE858_WIDTH : integer;
  attribute C_PROBE858_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE859_MU_CNT : integer;
  attribute C_PROBE859_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE859_TYPE : integer;
  attribute C_PROBE859_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE859_WIDTH : integer;
  attribute C_PROBE859_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE85_MU_CNT : integer;
  attribute C_PROBE85_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE85_TYPE : integer;
  attribute C_PROBE85_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE85_WIDTH : integer;
  attribute C_PROBE85_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE860_MU_CNT : integer;
  attribute C_PROBE860_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE860_TYPE : integer;
  attribute C_PROBE860_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE860_WIDTH : integer;
  attribute C_PROBE860_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE861_MU_CNT : integer;
  attribute C_PROBE861_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE861_TYPE : integer;
  attribute C_PROBE861_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE861_WIDTH : integer;
  attribute C_PROBE861_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE862_MU_CNT : integer;
  attribute C_PROBE862_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE862_TYPE : integer;
  attribute C_PROBE862_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE862_WIDTH : integer;
  attribute C_PROBE862_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE863_MU_CNT : integer;
  attribute C_PROBE863_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE863_TYPE : integer;
  attribute C_PROBE863_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE863_WIDTH : integer;
  attribute C_PROBE863_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE864_MU_CNT : integer;
  attribute C_PROBE864_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE864_TYPE : integer;
  attribute C_PROBE864_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE864_WIDTH : integer;
  attribute C_PROBE864_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE865_MU_CNT : integer;
  attribute C_PROBE865_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE865_TYPE : integer;
  attribute C_PROBE865_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE865_WIDTH : integer;
  attribute C_PROBE865_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE866_MU_CNT : integer;
  attribute C_PROBE866_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE866_TYPE : integer;
  attribute C_PROBE866_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE866_WIDTH : integer;
  attribute C_PROBE866_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE867_MU_CNT : integer;
  attribute C_PROBE867_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE867_TYPE : integer;
  attribute C_PROBE867_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE867_WIDTH : integer;
  attribute C_PROBE867_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE868_MU_CNT : integer;
  attribute C_PROBE868_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE868_TYPE : integer;
  attribute C_PROBE868_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE868_WIDTH : integer;
  attribute C_PROBE868_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE869_MU_CNT : integer;
  attribute C_PROBE869_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE869_TYPE : integer;
  attribute C_PROBE869_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE869_WIDTH : integer;
  attribute C_PROBE869_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE86_MU_CNT : integer;
  attribute C_PROBE86_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE86_TYPE : integer;
  attribute C_PROBE86_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE86_WIDTH : integer;
  attribute C_PROBE86_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE870_MU_CNT : integer;
  attribute C_PROBE870_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE870_TYPE : integer;
  attribute C_PROBE870_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE870_WIDTH : integer;
  attribute C_PROBE870_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE871_MU_CNT : integer;
  attribute C_PROBE871_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE871_TYPE : integer;
  attribute C_PROBE871_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE871_WIDTH : integer;
  attribute C_PROBE871_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE872_MU_CNT : integer;
  attribute C_PROBE872_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE872_TYPE : integer;
  attribute C_PROBE872_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE872_WIDTH : integer;
  attribute C_PROBE872_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE873_MU_CNT : integer;
  attribute C_PROBE873_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE873_TYPE : integer;
  attribute C_PROBE873_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE873_WIDTH : integer;
  attribute C_PROBE873_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE874_MU_CNT : integer;
  attribute C_PROBE874_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE874_TYPE : integer;
  attribute C_PROBE874_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE874_WIDTH : integer;
  attribute C_PROBE874_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE875_MU_CNT : integer;
  attribute C_PROBE875_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE875_TYPE : integer;
  attribute C_PROBE875_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE875_WIDTH : integer;
  attribute C_PROBE875_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE876_MU_CNT : integer;
  attribute C_PROBE876_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE876_TYPE : integer;
  attribute C_PROBE876_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE876_WIDTH : integer;
  attribute C_PROBE876_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE877_MU_CNT : integer;
  attribute C_PROBE877_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE877_TYPE : integer;
  attribute C_PROBE877_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE877_WIDTH : integer;
  attribute C_PROBE877_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE878_MU_CNT : integer;
  attribute C_PROBE878_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE878_TYPE : integer;
  attribute C_PROBE878_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE878_WIDTH : integer;
  attribute C_PROBE878_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE879_MU_CNT : integer;
  attribute C_PROBE879_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE879_TYPE : integer;
  attribute C_PROBE879_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE879_WIDTH : integer;
  attribute C_PROBE879_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE87_MU_CNT : integer;
  attribute C_PROBE87_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE87_TYPE : integer;
  attribute C_PROBE87_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE87_WIDTH : integer;
  attribute C_PROBE87_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE880_MU_CNT : integer;
  attribute C_PROBE880_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE880_TYPE : integer;
  attribute C_PROBE880_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE880_WIDTH : integer;
  attribute C_PROBE880_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE881_MU_CNT : integer;
  attribute C_PROBE881_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE881_TYPE : integer;
  attribute C_PROBE881_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE881_WIDTH : integer;
  attribute C_PROBE881_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE882_MU_CNT : integer;
  attribute C_PROBE882_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE882_TYPE : integer;
  attribute C_PROBE882_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE882_WIDTH : integer;
  attribute C_PROBE882_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE883_MU_CNT : integer;
  attribute C_PROBE883_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE883_TYPE : integer;
  attribute C_PROBE883_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE883_WIDTH : integer;
  attribute C_PROBE883_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE884_MU_CNT : integer;
  attribute C_PROBE884_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE884_TYPE : integer;
  attribute C_PROBE884_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE884_WIDTH : integer;
  attribute C_PROBE884_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE885_MU_CNT : integer;
  attribute C_PROBE885_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE885_TYPE : integer;
  attribute C_PROBE885_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE885_WIDTH : integer;
  attribute C_PROBE885_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE886_MU_CNT : integer;
  attribute C_PROBE886_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE886_TYPE : integer;
  attribute C_PROBE886_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE886_WIDTH : integer;
  attribute C_PROBE886_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE887_MU_CNT : integer;
  attribute C_PROBE887_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE887_TYPE : integer;
  attribute C_PROBE887_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE887_WIDTH : integer;
  attribute C_PROBE887_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE888_MU_CNT : integer;
  attribute C_PROBE888_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE888_TYPE : integer;
  attribute C_PROBE888_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE888_WIDTH : integer;
  attribute C_PROBE888_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE889_MU_CNT : integer;
  attribute C_PROBE889_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE889_TYPE : integer;
  attribute C_PROBE889_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE889_WIDTH : integer;
  attribute C_PROBE889_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE88_MU_CNT : integer;
  attribute C_PROBE88_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE88_TYPE : integer;
  attribute C_PROBE88_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE88_WIDTH : integer;
  attribute C_PROBE88_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE890_MU_CNT : integer;
  attribute C_PROBE890_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE890_TYPE : integer;
  attribute C_PROBE890_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE890_WIDTH : integer;
  attribute C_PROBE890_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE891_MU_CNT : integer;
  attribute C_PROBE891_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE891_TYPE : integer;
  attribute C_PROBE891_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE891_WIDTH : integer;
  attribute C_PROBE891_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE892_MU_CNT : integer;
  attribute C_PROBE892_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE892_TYPE : integer;
  attribute C_PROBE892_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE892_WIDTH : integer;
  attribute C_PROBE892_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE893_MU_CNT : integer;
  attribute C_PROBE893_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE893_TYPE : integer;
  attribute C_PROBE893_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE893_WIDTH : integer;
  attribute C_PROBE893_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE894_MU_CNT : integer;
  attribute C_PROBE894_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE894_TYPE : integer;
  attribute C_PROBE894_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE894_WIDTH : integer;
  attribute C_PROBE894_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE895_MU_CNT : integer;
  attribute C_PROBE895_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE895_TYPE : integer;
  attribute C_PROBE895_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE895_WIDTH : integer;
  attribute C_PROBE895_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE896_MU_CNT : integer;
  attribute C_PROBE896_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE896_TYPE : integer;
  attribute C_PROBE896_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE896_WIDTH : integer;
  attribute C_PROBE896_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE897_MU_CNT : integer;
  attribute C_PROBE897_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE897_TYPE : integer;
  attribute C_PROBE897_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE897_WIDTH : integer;
  attribute C_PROBE897_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE898_MU_CNT : integer;
  attribute C_PROBE898_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE898_TYPE : integer;
  attribute C_PROBE898_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE898_WIDTH : integer;
  attribute C_PROBE898_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE899_MU_CNT : integer;
  attribute C_PROBE899_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE899_TYPE : integer;
  attribute C_PROBE899_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE899_WIDTH : integer;
  attribute C_PROBE899_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE89_MU_CNT : integer;
  attribute C_PROBE89_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE89_TYPE : integer;
  attribute C_PROBE89_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE89_WIDTH : integer;
  attribute C_PROBE89_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE8_MU_CNT : integer;
  attribute C_PROBE8_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE8_TYPE : integer;
  attribute C_PROBE8_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE8_WIDTH : integer;
  attribute C_PROBE8_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE900_MU_CNT : integer;
  attribute C_PROBE900_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE900_TYPE : integer;
  attribute C_PROBE900_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE900_WIDTH : integer;
  attribute C_PROBE900_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE901_MU_CNT : integer;
  attribute C_PROBE901_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE901_TYPE : integer;
  attribute C_PROBE901_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE901_WIDTH : integer;
  attribute C_PROBE901_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE902_MU_CNT : integer;
  attribute C_PROBE902_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE902_TYPE : integer;
  attribute C_PROBE902_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE902_WIDTH : integer;
  attribute C_PROBE902_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE903_MU_CNT : integer;
  attribute C_PROBE903_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE903_TYPE : integer;
  attribute C_PROBE903_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE903_WIDTH : integer;
  attribute C_PROBE903_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE904_MU_CNT : integer;
  attribute C_PROBE904_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE904_TYPE : integer;
  attribute C_PROBE904_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE904_WIDTH : integer;
  attribute C_PROBE904_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE905_MU_CNT : integer;
  attribute C_PROBE905_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE905_TYPE : integer;
  attribute C_PROBE905_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE905_WIDTH : integer;
  attribute C_PROBE905_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE906_MU_CNT : integer;
  attribute C_PROBE906_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE906_TYPE : integer;
  attribute C_PROBE906_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE906_WIDTH : integer;
  attribute C_PROBE906_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE907_MU_CNT : integer;
  attribute C_PROBE907_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE907_TYPE : integer;
  attribute C_PROBE907_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE907_WIDTH : integer;
  attribute C_PROBE907_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE908_MU_CNT : integer;
  attribute C_PROBE908_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE908_TYPE : integer;
  attribute C_PROBE908_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE908_WIDTH : integer;
  attribute C_PROBE908_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE909_MU_CNT : integer;
  attribute C_PROBE909_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE909_TYPE : integer;
  attribute C_PROBE909_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE909_WIDTH : integer;
  attribute C_PROBE909_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE90_MU_CNT : integer;
  attribute C_PROBE90_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE90_TYPE : integer;
  attribute C_PROBE90_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE90_WIDTH : integer;
  attribute C_PROBE90_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE910_MU_CNT : integer;
  attribute C_PROBE910_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE910_TYPE : integer;
  attribute C_PROBE910_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE910_WIDTH : integer;
  attribute C_PROBE910_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE911_MU_CNT : integer;
  attribute C_PROBE911_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE911_TYPE : integer;
  attribute C_PROBE911_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE911_WIDTH : integer;
  attribute C_PROBE911_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE912_MU_CNT : integer;
  attribute C_PROBE912_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE912_TYPE : integer;
  attribute C_PROBE912_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE912_WIDTH : integer;
  attribute C_PROBE912_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE913_MU_CNT : integer;
  attribute C_PROBE913_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE913_TYPE : integer;
  attribute C_PROBE913_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE913_WIDTH : integer;
  attribute C_PROBE913_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE914_MU_CNT : integer;
  attribute C_PROBE914_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE914_TYPE : integer;
  attribute C_PROBE914_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE914_WIDTH : integer;
  attribute C_PROBE914_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE915_MU_CNT : integer;
  attribute C_PROBE915_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE915_TYPE : integer;
  attribute C_PROBE915_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE915_WIDTH : integer;
  attribute C_PROBE915_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE916_MU_CNT : integer;
  attribute C_PROBE916_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE916_TYPE : integer;
  attribute C_PROBE916_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE916_WIDTH : integer;
  attribute C_PROBE916_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE917_MU_CNT : integer;
  attribute C_PROBE917_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE917_TYPE : integer;
  attribute C_PROBE917_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE917_WIDTH : integer;
  attribute C_PROBE917_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE918_MU_CNT : integer;
  attribute C_PROBE918_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE918_TYPE : integer;
  attribute C_PROBE918_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE918_WIDTH : integer;
  attribute C_PROBE918_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE919_MU_CNT : integer;
  attribute C_PROBE919_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE919_TYPE : integer;
  attribute C_PROBE919_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE919_WIDTH : integer;
  attribute C_PROBE919_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE91_MU_CNT : integer;
  attribute C_PROBE91_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE91_TYPE : integer;
  attribute C_PROBE91_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE91_WIDTH : integer;
  attribute C_PROBE91_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE920_MU_CNT : integer;
  attribute C_PROBE920_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE920_TYPE : integer;
  attribute C_PROBE920_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE920_WIDTH : integer;
  attribute C_PROBE920_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE921_MU_CNT : integer;
  attribute C_PROBE921_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE921_TYPE : integer;
  attribute C_PROBE921_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE921_WIDTH : integer;
  attribute C_PROBE921_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE922_MU_CNT : integer;
  attribute C_PROBE922_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE922_TYPE : integer;
  attribute C_PROBE922_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE922_WIDTH : integer;
  attribute C_PROBE922_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE923_MU_CNT : integer;
  attribute C_PROBE923_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE923_TYPE : integer;
  attribute C_PROBE923_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE923_WIDTH : integer;
  attribute C_PROBE923_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE924_MU_CNT : integer;
  attribute C_PROBE924_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE924_TYPE : integer;
  attribute C_PROBE924_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE924_WIDTH : integer;
  attribute C_PROBE924_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE925_MU_CNT : integer;
  attribute C_PROBE925_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE925_TYPE : integer;
  attribute C_PROBE925_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE925_WIDTH : integer;
  attribute C_PROBE925_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE926_MU_CNT : integer;
  attribute C_PROBE926_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE926_TYPE : integer;
  attribute C_PROBE926_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE926_WIDTH : integer;
  attribute C_PROBE926_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE927_MU_CNT : integer;
  attribute C_PROBE927_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE927_TYPE : integer;
  attribute C_PROBE927_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE927_WIDTH : integer;
  attribute C_PROBE927_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE928_MU_CNT : integer;
  attribute C_PROBE928_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE928_TYPE : integer;
  attribute C_PROBE928_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE928_WIDTH : integer;
  attribute C_PROBE928_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE929_MU_CNT : integer;
  attribute C_PROBE929_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE929_TYPE : integer;
  attribute C_PROBE929_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE929_WIDTH : integer;
  attribute C_PROBE929_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE92_MU_CNT : integer;
  attribute C_PROBE92_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE92_TYPE : integer;
  attribute C_PROBE92_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE92_WIDTH : integer;
  attribute C_PROBE92_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE930_MU_CNT : integer;
  attribute C_PROBE930_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE930_TYPE : integer;
  attribute C_PROBE930_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE930_WIDTH : integer;
  attribute C_PROBE930_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE931_MU_CNT : integer;
  attribute C_PROBE931_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE931_TYPE : integer;
  attribute C_PROBE931_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE931_WIDTH : integer;
  attribute C_PROBE931_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE932_MU_CNT : integer;
  attribute C_PROBE932_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE932_TYPE : integer;
  attribute C_PROBE932_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE932_WIDTH : integer;
  attribute C_PROBE932_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE933_MU_CNT : integer;
  attribute C_PROBE933_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE933_TYPE : integer;
  attribute C_PROBE933_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE933_WIDTH : integer;
  attribute C_PROBE933_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE934_MU_CNT : integer;
  attribute C_PROBE934_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE934_TYPE : integer;
  attribute C_PROBE934_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE934_WIDTH : integer;
  attribute C_PROBE934_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE935_MU_CNT : integer;
  attribute C_PROBE935_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE935_TYPE : integer;
  attribute C_PROBE935_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE935_WIDTH : integer;
  attribute C_PROBE935_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE936_MU_CNT : integer;
  attribute C_PROBE936_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE936_TYPE : integer;
  attribute C_PROBE936_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE936_WIDTH : integer;
  attribute C_PROBE936_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE937_MU_CNT : integer;
  attribute C_PROBE937_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE937_TYPE : integer;
  attribute C_PROBE937_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE937_WIDTH : integer;
  attribute C_PROBE937_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE938_MU_CNT : integer;
  attribute C_PROBE938_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE938_TYPE : integer;
  attribute C_PROBE938_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE938_WIDTH : integer;
  attribute C_PROBE938_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE939_MU_CNT : integer;
  attribute C_PROBE939_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE939_TYPE : integer;
  attribute C_PROBE939_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE939_WIDTH : integer;
  attribute C_PROBE939_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE93_MU_CNT : integer;
  attribute C_PROBE93_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE93_TYPE : integer;
  attribute C_PROBE93_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE93_WIDTH : integer;
  attribute C_PROBE93_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE940_MU_CNT : integer;
  attribute C_PROBE940_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE940_TYPE : integer;
  attribute C_PROBE940_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE940_WIDTH : integer;
  attribute C_PROBE940_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE941_MU_CNT : integer;
  attribute C_PROBE941_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE941_TYPE : integer;
  attribute C_PROBE941_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE941_WIDTH : integer;
  attribute C_PROBE941_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE942_MU_CNT : integer;
  attribute C_PROBE942_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE942_TYPE : integer;
  attribute C_PROBE942_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE942_WIDTH : integer;
  attribute C_PROBE942_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE943_MU_CNT : integer;
  attribute C_PROBE943_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE943_TYPE : integer;
  attribute C_PROBE943_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE943_WIDTH : integer;
  attribute C_PROBE943_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE944_MU_CNT : integer;
  attribute C_PROBE944_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE944_TYPE : integer;
  attribute C_PROBE944_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE944_WIDTH : integer;
  attribute C_PROBE944_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE945_MU_CNT : integer;
  attribute C_PROBE945_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE945_TYPE : integer;
  attribute C_PROBE945_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE945_WIDTH : integer;
  attribute C_PROBE945_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE946_MU_CNT : integer;
  attribute C_PROBE946_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE946_TYPE : integer;
  attribute C_PROBE946_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE946_WIDTH : integer;
  attribute C_PROBE946_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE947_MU_CNT : integer;
  attribute C_PROBE947_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE947_TYPE : integer;
  attribute C_PROBE947_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE947_WIDTH : integer;
  attribute C_PROBE947_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE948_MU_CNT : integer;
  attribute C_PROBE948_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE948_TYPE : integer;
  attribute C_PROBE948_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE948_WIDTH : integer;
  attribute C_PROBE948_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE949_MU_CNT : integer;
  attribute C_PROBE949_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE949_TYPE : integer;
  attribute C_PROBE949_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE949_WIDTH : integer;
  attribute C_PROBE949_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE94_MU_CNT : integer;
  attribute C_PROBE94_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE94_TYPE : integer;
  attribute C_PROBE94_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE94_WIDTH : integer;
  attribute C_PROBE94_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE950_MU_CNT : integer;
  attribute C_PROBE950_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE950_TYPE : integer;
  attribute C_PROBE950_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE950_WIDTH : integer;
  attribute C_PROBE950_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE951_MU_CNT : integer;
  attribute C_PROBE951_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE951_TYPE : integer;
  attribute C_PROBE951_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE951_WIDTH : integer;
  attribute C_PROBE951_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE952_MU_CNT : integer;
  attribute C_PROBE952_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE952_TYPE : integer;
  attribute C_PROBE952_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE952_WIDTH : integer;
  attribute C_PROBE952_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE953_MU_CNT : integer;
  attribute C_PROBE953_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE953_TYPE : integer;
  attribute C_PROBE953_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE953_WIDTH : integer;
  attribute C_PROBE953_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE954_MU_CNT : integer;
  attribute C_PROBE954_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE954_TYPE : integer;
  attribute C_PROBE954_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE954_WIDTH : integer;
  attribute C_PROBE954_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE955_MU_CNT : integer;
  attribute C_PROBE955_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE955_TYPE : integer;
  attribute C_PROBE955_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE955_WIDTH : integer;
  attribute C_PROBE955_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE956_MU_CNT : integer;
  attribute C_PROBE956_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE956_TYPE : integer;
  attribute C_PROBE956_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE956_WIDTH : integer;
  attribute C_PROBE956_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE957_MU_CNT : integer;
  attribute C_PROBE957_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE957_TYPE : integer;
  attribute C_PROBE957_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE957_WIDTH : integer;
  attribute C_PROBE957_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE958_MU_CNT : integer;
  attribute C_PROBE958_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE958_TYPE : integer;
  attribute C_PROBE958_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE958_WIDTH : integer;
  attribute C_PROBE958_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE959_MU_CNT : integer;
  attribute C_PROBE959_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE959_TYPE : integer;
  attribute C_PROBE959_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE959_WIDTH : integer;
  attribute C_PROBE959_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE95_MU_CNT : integer;
  attribute C_PROBE95_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE95_TYPE : integer;
  attribute C_PROBE95_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE95_WIDTH : integer;
  attribute C_PROBE95_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE960_MU_CNT : integer;
  attribute C_PROBE960_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE960_TYPE : integer;
  attribute C_PROBE960_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE960_WIDTH : integer;
  attribute C_PROBE960_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE961_MU_CNT : integer;
  attribute C_PROBE961_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE961_TYPE : integer;
  attribute C_PROBE961_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE961_WIDTH : integer;
  attribute C_PROBE961_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE962_MU_CNT : integer;
  attribute C_PROBE962_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE962_TYPE : integer;
  attribute C_PROBE962_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE962_WIDTH : integer;
  attribute C_PROBE962_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE963_MU_CNT : integer;
  attribute C_PROBE963_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE963_TYPE : integer;
  attribute C_PROBE963_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE963_WIDTH : integer;
  attribute C_PROBE963_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE964_MU_CNT : integer;
  attribute C_PROBE964_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE964_TYPE : integer;
  attribute C_PROBE964_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE964_WIDTH : integer;
  attribute C_PROBE964_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE965_MU_CNT : integer;
  attribute C_PROBE965_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE965_TYPE : integer;
  attribute C_PROBE965_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE965_WIDTH : integer;
  attribute C_PROBE965_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE966_MU_CNT : integer;
  attribute C_PROBE966_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE966_TYPE : integer;
  attribute C_PROBE966_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE966_WIDTH : integer;
  attribute C_PROBE966_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE967_MU_CNT : integer;
  attribute C_PROBE967_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE967_TYPE : integer;
  attribute C_PROBE967_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE967_WIDTH : integer;
  attribute C_PROBE967_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE968_MU_CNT : integer;
  attribute C_PROBE968_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE968_TYPE : integer;
  attribute C_PROBE968_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE968_WIDTH : integer;
  attribute C_PROBE968_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE969_MU_CNT : integer;
  attribute C_PROBE969_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE969_TYPE : integer;
  attribute C_PROBE969_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE969_WIDTH : integer;
  attribute C_PROBE969_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE96_MU_CNT : integer;
  attribute C_PROBE96_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE96_TYPE : integer;
  attribute C_PROBE96_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE96_WIDTH : integer;
  attribute C_PROBE96_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE970_MU_CNT : integer;
  attribute C_PROBE970_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE970_TYPE : integer;
  attribute C_PROBE970_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE970_WIDTH : integer;
  attribute C_PROBE970_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE971_MU_CNT : integer;
  attribute C_PROBE971_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE971_TYPE : integer;
  attribute C_PROBE971_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE971_WIDTH : integer;
  attribute C_PROBE971_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE972_MU_CNT : integer;
  attribute C_PROBE972_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE972_TYPE : integer;
  attribute C_PROBE972_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE972_WIDTH : integer;
  attribute C_PROBE972_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE973_MU_CNT : integer;
  attribute C_PROBE973_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE973_TYPE : integer;
  attribute C_PROBE973_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE973_WIDTH : integer;
  attribute C_PROBE973_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE974_MU_CNT : integer;
  attribute C_PROBE974_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE974_TYPE : integer;
  attribute C_PROBE974_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE974_WIDTH : integer;
  attribute C_PROBE974_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE975_MU_CNT : integer;
  attribute C_PROBE975_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE975_TYPE : integer;
  attribute C_PROBE975_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE975_WIDTH : integer;
  attribute C_PROBE975_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE976_MU_CNT : integer;
  attribute C_PROBE976_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE976_TYPE : integer;
  attribute C_PROBE976_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE976_WIDTH : integer;
  attribute C_PROBE976_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE977_MU_CNT : integer;
  attribute C_PROBE977_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE977_TYPE : integer;
  attribute C_PROBE977_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE977_WIDTH : integer;
  attribute C_PROBE977_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE978_MU_CNT : integer;
  attribute C_PROBE978_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE978_TYPE : integer;
  attribute C_PROBE978_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE978_WIDTH : integer;
  attribute C_PROBE978_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE979_MU_CNT : integer;
  attribute C_PROBE979_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE979_TYPE : integer;
  attribute C_PROBE979_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE979_WIDTH : integer;
  attribute C_PROBE979_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE97_MU_CNT : integer;
  attribute C_PROBE97_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE97_TYPE : integer;
  attribute C_PROBE97_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE97_WIDTH : integer;
  attribute C_PROBE97_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE980_MU_CNT : integer;
  attribute C_PROBE980_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE980_TYPE : integer;
  attribute C_PROBE980_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE980_WIDTH : integer;
  attribute C_PROBE980_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE981_MU_CNT : integer;
  attribute C_PROBE981_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE981_TYPE : integer;
  attribute C_PROBE981_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE981_WIDTH : integer;
  attribute C_PROBE981_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE982_MU_CNT : integer;
  attribute C_PROBE982_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE982_TYPE : integer;
  attribute C_PROBE982_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE982_WIDTH : integer;
  attribute C_PROBE982_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE983_MU_CNT : integer;
  attribute C_PROBE983_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE983_TYPE : integer;
  attribute C_PROBE983_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE983_WIDTH : integer;
  attribute C_PROBE983_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE984_MU_CNT : integer;
  attribute C_PROBE984_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE984_TYPE : integer;
  attribute C_PROBE984_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE984_WIDTH : integer;
  attribute C_PROBE984_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE985_MU_CNT : integer;
  attribute C_PROBE985_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE985_TYPE : integer;
  attribute C_PROBE985_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE985_WIDTH : integer;
  attribute C_PROBE985_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE986_MU_CNT : integer;
  attribute C_PROBE986_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE986_TYPE : integer;
  attribute C_PROBE986_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE986_WIDTH : integer;
  attribute C_PROBE986_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE987_MU_CNT : integer;
  attribute C_PROBE987_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE987_TYPE : integer;
  attribute C_PROBE987_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE987_WIDTH : integer;
  attribute C_PROBE987_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE988_MU_CNT : integer;
  attribute C_PROBE988_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE988_TYPE : integer;
  attribute C_PROBE988_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE988_WIDTH : integer;
  attribute C_PROBE988_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE989_MU_CNT : integer;
  attribute C_PROBE989_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE989_TYPE : integer;
  attribute C_PROBE989_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE989_WIDTH : integer;
  attribute C_PROBE989_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE98_MU_CNT : integer;
  attribute C_PROBE98_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE98_TYPE : integer;
  attribute C_PROBE98_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE98_WIDTH : integer;
  attribute C_PROBE98_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE990_MU_CNT : integer;
  attribute C_PROBE990_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE990_TYPE : integer;
  attribute C_PROBE990_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE990_WIDTH : integer;
  attribute C_PROBE990_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE991_MU_CNT : integer;
  attribute C_PROBE991_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE991_TYPE : integer;
  attribute C_PROBE991_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE991_WIDTH : integer;
  attribute C_PROBE991_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE992_MU_CNT : integer;
  attribute C_PROBE992_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE992_TYPE : integer;
  attribute C_PROBE992_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE992_WIDTH : integer;
  attribute C_PROBE992_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE993_MU_CNT : integer;
  attribute C_PROBE993_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE993_TYPE : integer;
  attribute C_PROBE993_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE993_WIDTH : integer;
  attribute C_PROBE993_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE994_MU_CNT : integer;
  attribute C_PROBE994_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE994_TYPE : integer;
  attribute C_PROBE994_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE994_WIDTH : integer;
  attribute C_PROBE994_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE995_MU_CNT : integer;
  attribute C_PROBE995_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE995_TYPE : integer;
  attribute C_PROBE995_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE995_WIDTH : integer;
  attribute C_PROBE995_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE996_MU_CNT : integer;
  attribute C_PROBE996_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE996_TYPE : integer;
  attribute C_PROBE996_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE996_WIDTH : integer;
  attribute C_PROBE996_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE997_MU_CNT : integer;
  attribute C_PROBE997_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE997_TYPE : integer;
  attribute C_PROBE997_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE997_WIDTH : integer;
  attribute C_PROBE997_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE998_MU_CNT : integer;
  attribute C_PROBE998_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE998_TYPE : integer;
  attribute C_PROBE998_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE998_WIDTH : integer;
  attribute C_PROBE998_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE999_MU_CNT : integer;
  attribute C_PROBE999_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE999_TYPE : integer;
  attribute C_PROBE999_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE999_WIDTH : integer;
  attribute C_PROBE999_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE99_MU_CNT : integer;
  attribute C_PROBE99_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE99_TYPE : integer;
  attribute C_PROBE99_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE99_WIDTH : integer;
  attribute C_PROBE99_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE9_MU_CNT : integer;
  attribute C_PROBE9_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE9_TYPE : integer;
  attribute C_PROBE9_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_PROBE9_WIDTH : integer;
  attribute C_PROBE9_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_RAM_STYLE : string;
  attribute C_RAM_STYLE of ila_full_aurora_ila_v6_2_10_ila : entity is "SUBCORE";
  attribute C_SLOT_0_AXIS_TDEST_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TDEST_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXIS_TID_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TID_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXIS_TUSER_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_ARUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_ARUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_AWUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_AWUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_BUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_BUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_ID_WIDTH : integer;
  attribute C_SLOT_0_AXI_ID_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_PROTOCOL : string;
  attribute C_SLOT_0_AXI_PROTOCOL of ila_full_aurora_ila_v6_2_10_ila : entity is "AXI4";
  attribute C_SLOT_0_AXI_RUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_RUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_SLOT_0_AXI_WUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_WUSER_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_TC_TYPE : integer;
  attribute C_TC_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_TIME_TAG_WIDTH : integer;
  attribute C_TIME_TAG_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 32;
  attribute C_TRIGIN_EN : integer;
  attribute C_TRIGIN_EN of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_TRIGOUT_EN : integer;
  attribute C_TRIGOUT_EN of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute C_USE_TEST_REG : integer;
  attribute C_USE_TEST_REG of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of ila_full_aurora_ila_v6_2_10_ila : entity is "virtex7";
  attribute C_XLNX_HW_PROBE_INFO : string;
  attribute C_XLNX_HW_PROBE_INFO of ila_full_aurora_ila_v6_2_10_ila : entity is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY1 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY1 of ila_full_aurora_ila_v6_2_10_ila : entity is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY2 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY2 of ila_full_aurora_ila_v6_2_10_ila : entity is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY3 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY3 of ila_full_aurora_ila_v6_2_10_ila : entity is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY4 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY4 of ila_full_aurora_ila_v6_2_10_ila : entity is "DEFAULT";
  attribute C_XSDB_SLAVE_TYPE : integer;
  attribute C_XSDB_SLAVE_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 17;
  attribute IS_DEBUG_CORE : string;
  attribute IS_DEBUG_CORE of ila_full_aurora_ila_v6_2_10_ila : entity is "TRUE";
  attribute LC_COMPUTED_DATA_WIDTH : integer;
  attribute LC_COMPUTED_DATA_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 138;
  attribute LC_DATA_WIDTH : integer;
  attribute LC_DATA_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 138;
  attribute LC_MATCH_TPID_VEC : string;
  attribute LC_MATCH_TPID_VEC of ila_full_aurora_ila_v6_2_10_ila : entity is "1536'b000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
  attribute LC_MU_CNT_STRING : string;
  attribute LC_MU_CNT_STRING of ila_full_aurora_ila_v6_2_10_ila : entity is "4096' ";
  attribute LC_MU_COUNT : integer;
  attribute LC_MU_COUNT of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute LC_MU_COUNT_EN : integer;
  attribute LC_MU_COUNT_EN of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute LC_NUM_OF_PROBES : integer;
  attribute LC_NUM_OF_PROBES of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute LC_NUM_PROBES : integer;
  attribute LC_NUM_PROBES of ila_full_aurora_ila_v6_2_10_ila : entity is 6;
  attribute LC_NUM_TRIG_EQS : integer;
  attribute LC_NUM_TRIG_EQS of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE0_IS_DATA : string;
  attribute LC_PROBE0_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE0_IS_TRIG : string;
  attribute LC_PROBE0_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE0_MU_CNT : integer;
  attribute LC_PROBE0_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE0_PID : string;
  attribute LC_PROBE0_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000000";
  attribute LC_PROBE0_TYPE : integer;
  attribute LC_PROBE0_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE0_WIDTH : integer;
  attribute LC_PROBE0_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 64;
  attribute LC_PROBE1000_IS_DATA : string;
  attribute LC_PROBE1000_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1000_IS_TRIG : string;
  attribute LC_PROBE1000_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1000_MU_CNT : integer;
  attribute LC_PROBE1000_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1000_PID : string;
  attribute LC_PROBE1000_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101000";
  attribute LC_PROBE1000_TYPE : integer;
  attribute LC_PROBE1000_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1000_WIDTH : integer;
  attribute LC_PROBE1000_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1001_IS_DATA : string;
  attribute LC_PROBE1001_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1001_IS_TRIG : string;
  attribute LC_PROBE1001_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1001_MU_CNT : integer;
  attribute LC_PROBE1001_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1001_PID : string;
  attribute LC_PROBE1001_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101001";
  attribute LC_PROBE1001_TYPE : integer;
  attribute LC_PROBE1001_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1001_WIDTH : integer;
  attribute LC_PROBE1001_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1002_IS_DATA : string;
  attribute LC_PROBE1002_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1002_IS_TRIG : string;
  attribute LC_PROBE1002_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1002_MU_CNT : integer;
  attribute LC_PROBE1002_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1002_PID : string;
  attribute LC_PROBE1002_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101010";
  attribute LC_PROBE1002_TYPE : integer;
  attribute LC_PROBE1002_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1002_WIDTH : integer;
  attribute LC_PROBE1002_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1003_IS_DATA : string;
  attribute LC_PROBE1003_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1003_IS_TRIG : string;
  attribute LC_PROBE1003_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1003_MU_CNT : integer;
  attribute LC_PROBE1003_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1003_PID : string;
  attribute LC_PROBE1003_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101011";
  attribute LC_PROBE1003_TYPE : integer;
  attribute LC_PROBE1003_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1003_WIDTH : integer;
  attribute LC_PROBE1003_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1004_IS_DATA : string;
  attribute LC_PROBE1004_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1004_IS_TRIG : string;
  attribute LC_PROBE1004_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1004_MU_CNT : integer;
  attribute LC_PROBE1004_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1004_PID : string;
  attribute LC_PROBE1004_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101100";
  attribute LC_PROBE1004_TYPE : integer;
  attribute LC_PROBE1004_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1004_WIDTH : integer;
  attribute LC_PROBE1004_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1005_IS_DATA : string;
  attribute LC_PROBE1005_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1005_IS_TRIG : string;
  attribute LC_PROBE1005_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1005_MU_CNT : integer;
  attribute LC_PROBE1005_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1005_PID : string;
  attribute LC_PROBE1005_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101101";
  attribute LC_PROBE1005_TYPE : integer;
  attribute LC_PROBE1005_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1005_WIDTH : integer;
  attribute LC_PROBE1005_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1006_IS_DATA : string;
  attribute LC_PROBE1006_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1006_IS_TRIG : string;
  attribute LC_PROBE1006_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1006_MU_CNT : integer;
  attribute LC_PROBE1006_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1006_PID : string;
  attribute LC_PROBE1006_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101110";
  attribute LC_PROBE1006_TYPE : integer;
  attribute LC_PROBE1006_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1006_WIDTH : integer;
  attribute LC_PROBE1006_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1007_IS_DATA : string;
  attribute LC_PROBE1007_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1007_IS_TRIG : string;
  attribute LC_PROBE1007_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1007_MU_CNT : integer;
  attribute LC_PROBE1007_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1007_PID : string;
  attribute LC_PROBE1007_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111101111";
  attribute LC_PROBE1007_TYPE : integer;
  attribute LC_PROBE1007_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1007_WIDTH : integer;
  attribute LC_PROBE1007_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1008_IS_DATA : string;
  attribute LC_PROBE1008_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1008_IS_TRIG : string;
  attribute LC_PROBE1008_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1008_MU_CNT : integer;
  attribute LC_PROBE1008_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1008_PID : string;
  attribute LC_PROBE1008_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110000";
  attribute LC_PROBE1008_TYPE : integer;
  attribute LC_PROBE1008_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1008_WIDTH : integer;
  attribute LC_PROBE1008_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1009_IS_DATA : string;
  attribute LC_PROBE1009_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1009_IS_TRIG : string;
  attribute LC_PROBE1009_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1009_MU_CNT : integer;
  attribute LC_PROBE1009_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1009_PID : string;
  attribute LC_PROBE1009_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110001";
  attribute LC_PROBE1009_TYPE : integer;
  attribute LC_PROBE1009_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1009_WIDTH : integer;
  attribute LC_PROBE1009_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE100_IS_DATA : string;
  attribute LC_PROBE100_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE100_IS_TRIG : string;
  attribute LC_PROBE100_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE100_MU_CNT : integer;
  attribute LC_PROBE100_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE100_PID : string;
  attribute LC_PROBE100_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100100";
  attribute LC_PROBE100_TYPE : integer;
  attribute LC_PROBE100_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE100_WIDTH : integer;
  attribute LC_PROBE100_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1010_IS_DATA : string;
  attribute LC_PROBE1010_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1010_IS_TRIG : string;
  attribute LC_PROBE1010_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1010_MU_CNT : integer;
  attribute LC_PROBE1010_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1010_PID : string;
  attribute LC_PROBE1010_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110010";
  attribute LC_PROBE1010_TYPE : integer;
  attribute LC_PROBE1010_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1010_WIDTH : integer;
  attribute LC_PROBE1010_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1011_IS_DATA : string;
  attribute LC_PROBE1011_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1011_IS_TRIG : string;
  attribute LC_PROBE1011_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1011_MU_CNT : integer;
  attribute LC_PROBE1011_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1011_PID : string;
  attribute LC_PROBE1011_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110011";
  attribute LC_PROBE1011_TYPE : integer;
  attribute LC_PROBE1011_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1011_WIDTH : integer;
  attribute LC_PROBE1011_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1012_IS_DATA : string;
  attribute LC_PROBE1012_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1012_IS_TRIG : string;
  attribute LC_PROBE1012_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1012_MU_CNT : integer;
  attribute LC_PROBE1012_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1012_PID : string;
  attribute LC_PROBE1012_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110100";
  attribute LC_PROBE1012_TYPE : integer;
  attribute LC_PROBE1012_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1012_WIDTH : integer;
  attribute LC_PROBE1012_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1013_IS_DATA : string;
  attribute LC_PROBE1013_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1013_IS_TRIG : string;
  attribute LC_PROBE1013_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1013_MU_CNT : integer;
  attribute LC_PROBE1013_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1013_PID : string;
  attribute LC_PROBE1013_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110101";
  attribute LC_PROBE1013_TYPE : integer;
  attribute LC_PROBE1013_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1013_WIDTH : integer;
  attribute LC_PROBE1013_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1014_IS_DATA : string;
  attribute LC_PROBE1014_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1014_IS_TRIG : string;
  attribute LC_PROBE1014_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1014_MU_CNT : integer;
  attribute LC_PROBE1014_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1014_PID : string;
  attribute LC_PROBE1014_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110110";
  attribute LC_PROBE1014_TYPE : integer;
  attribute LC_PROBE1014_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1014_WIDTH : integer;
  attribute LC_PROBE1014_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1015_IS_DATA : string;
  attribute LC_PROBE1015_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1015_IS_TRIG : string;
  attribute LC_PROBE1015_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1015_MU_CNT : integer;
  attribute LC_PROBE1015_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1015_PID : string;
  attribute LC_PROBE1015_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111110111";
  attribute LC_PROBE1015_TYPE : integer;
  attribute LC_PROBE1015_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1015_WIDTH : integer;
  attribute LC_PROBE1015_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1016_IS_DATA : string;
  attribute LC_PROBE1016_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1016_IS_TRIG : string;
  attribute LC_PROBE1016_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1016_MU_CNT : integer;
  attribute LC_PROBE1016_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1016_PID : string;
  attribute LC_PROBE1016_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111000";
  attribute LC_PROBE1016_TYPE : integer;
  attribute LC_PROBE1016_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1016_WIDTH : integer;
  attribute LC_PROBE1016_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1017_IS_DATA : string;
  attribute LC_PROBE1017_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1017_IS_TRIG : string;
  attribute LC_PROBE1017_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1017_MU_CNT : integer;
  attribute LC_PROBE1017_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1017_PID : string;
  attribute LC_PROBE1017_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111001";
  attribute LC_PROBE1017_TYPE : integer;
  attribute LC_PROBE1017_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1017_WIDTH : integer;
  attribute LC_PROBE1017_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1018_IS_DATA : string;
  attribute LC_PROBE1018_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1018_IS_TRIG : string;
  attribute LC_PROBE1018_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1018_MU_CNT : integer;
  attribute LC_PROBE1018_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1018_PID : string;
  attribute LC_PROBE1018_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111010";
  attribute LC_PROBE1018_TYPE : integer;
  attribute LC_PROBE1018_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1018_WIDTH : integer;
  attribute LC_PROBE1018_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1019_IS_DATA : string;
  attribute LC_PROBE1019_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1019_IS_TRIG : string;
  attribute LC_PROBE1019_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1019_MU_CNT : integer;
  attribute LC_PROBE1019_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1019_PID : string;
  attribute LC_PROBE1019_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111011";
  attribute LC_PROBE1019_TYPE : integer;
  attribute LC_PROBE1019_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1019_WIDTH : integer;
  attribute LC_PROBE1019_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE101_IS_DATA : string;
  attribute LC_PROBE101_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE101_IS_TRIG : string;
  attribute LC_PROBE101_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE101_MU_CNT : integer;
  attribute LC_PROBE101_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE101_PID : string;
  attribute LC_PROBE101_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100101";
  attribute LC_PROBE101_TYPE : integer;
  attribute LC_PROBE101_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE101_WIDTH : integer;
  attribute LC_PROBE101_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1020_IS_DATA : string;
  attribute LC_PROBE1020_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1020_IS_TRIG : string;
  attribute LC_PROBE1020_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1020_MU_CNT : integer;
  attribute LC_PROBE1020_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1020_PID : string;
  attribute LC_PROBE1020_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111100";
  attribute LC_PROBE1020_TYPE : integer;
  attribute LC_PROBE1020_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1020_WIDTH : integer;
  attribute LC_PROBE1020_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1021_IS_DATA : string;
  attribute LC_PROBE1021_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1021_IS_TRIG : string;
  attribute LC_PROBE1021_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1021_MU_CNT : integer;
  attribute LC_PROBE1021_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1021_PID : string;
  attribute LC_PROBE1021_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111101";
  attribute LC_PROBE1021_TYPE : integer;
  attribute LC_PROBE1021_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1021_WIDTH : integer;
  attribute LC_PROBE1021_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1022_IS_DATA : string;
  attribute LC_PROBE1022_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1022_IS_TRIG : string;
  attribute LC_PROBE1022_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1022_MU_CNT : integer;
  attribute LC_PROBE1022_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1022_PID : string;
  attribute LC_PROBE1022_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111110";
  attribute LC_PROBE1022_TYPE : integer;
  attribute LC_PROBE1022_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1022_WIDTH : integer;
  attribute LC_PROBE1022_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1023_IS_DATA : string;
  attribute LC_PROBE1023_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1023_IS_TRIG : string;
  attribute LC_PROBE1023_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE1023_MU_CNT : integer;
  attribute LC_PROBE1023_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1023_PID : string;
  attribute LC_PROBE1023_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111111111";
  attribute LC_PROBE1023_TYPE : integer;
  attribute LC_PROBE1023_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1023_WIDTH : integer;
  attribute LC_PROBE1023_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE102_IS_DATA : string;
  attribute LC_PROBE102_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE102_IS_TRIG : string;
  attribute LC_PROBE102_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE102_MU_CNT : integer;
  attribute LC_PROBE102_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE102_PID : string;
  attribute LC_PROBE102_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100110";
  attribute LC_PROBE102_TYPE : integer;
  attribute LC_PROBE102_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE102_WIDTH : integer;
  attribute LC_PROBE102_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE103_IS_DATA : string;
  attribute LC_PROBE103_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE103_IS_TRIG : string;
  attribute LC_PROBE103_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE103_MU_CNT : integer;
  attribute LC_PROBE103_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE103_PID : string;
  attribute LC_PROBE103_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100111";
  attribute LC_PROBE103_TYPE : integer;
  attribute LC_PROBE103_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE103_WIDTH : integer;
  attribute LC_PROBE103_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE104_IS_DATA : string;
  attribute LC_PROBE104_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE104_IS_TRIG : string;
  attribute LC_PROBE104_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE104_MU_CNT : integer;
  attribute LC_PROBE104_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE104_PID : string;
  attribute LC_PROBE104_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101000";
  attribute LC_PROBE104_TYPE : integer;
  attribute LC_PROBE104_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE104_WIDTH : integer;
  attribute LC_PROBE104_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE105_IS_DATA : string;
  attribute LC_PROBE105_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE105_IS_TRIG : string;
  attribute LC_PROBE105_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE105_MU_CNT : integer;
  attribute LC_PROBE105_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE105_PID : string;
  attribute LC_PROBE105_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101001";
  attribute LC_PROBE105_TYPE : integer;
  attribute LC_PROBE105_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE105_WIDTH : integer;
  attribute LC_PROBE105_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE106_IS_DATA : string;
  attribute LC_PROBE106_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE106_IS_TRIG : string;
  attribute LC_PROBE106_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE106_MU_CNT : integer;
  attribute LC_PROBE106_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE106_PID : string;
  attribute LC_PROBE106_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101010";
  attribute LC_PROBE106_TYPE : integer;
  attribute LC_PROBE106_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE106_WIDTH : integer;
  attribute LC_PROBE106_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE107_IS_DATA : string;
  attribute LC_PROBE107_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE107_IS_TRIG : string;
  attribute LC_PROBE107_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE107_MU_CNT : integer;
  attribute LC_PROBE107_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE107_PID : string;
  attribute LC_PROBE107_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101011";
  attribute LC_PROBE107_TYPE : integer;
  attribute LC_PROBE107_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE107_WIDTH : integer;
  attribute LC_PROBE107_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE108_IS_DATA : string;
  attribute LC_PROBE108_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE108_IS_TRIG : string;
  attribute LC_PROBE108_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE108_MU_CNT : integer;
  attribute LC_PROBE108_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE108_PID : string;
  attribute LC_PROBE108_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101100";
  attribute LC_PROBE108_TYPE : integer;
  attribute LC_PROBE108_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE108_WIDTH : integer;
  attribute LC_PROBE108_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE109_IS_DATA : string;
  attribute LC_PROBE109_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE109_IS_TRIG : string;
  attribute LC_PROBE109_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE109_MU_CNT : integer;
  attribute LC_PROBE109_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE109_PID : string;
  attribute LC_PROBE109_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101101";
  attribute LC_PROBE109_TYPE : integer;
  attribute LC_PROBE109_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE109_WIDTH : integer;
  attribute LC_PROBE109_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE10_IS_DATA : string;
  attribute LC_PROBE10_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE10_IS_TRIG : string;
  attribute LC_PROBE10_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE10_MU_CNT : integer;
  attribute LC_PROBE10_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE10_PID : string;
  attribute LC_PROBE10_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001010";
  attribute LC_PROBE10_TYPE : integer;
  attribute LC_PROBE10_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE10_WIDTH : integer;
  attribute LC_PROBE10_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE110_IS_DATA : string;
  attribute LC_PROBE110_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE110_IS_TRIG : string;
  attribute LC_PROBE110_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE110_MU_CNT : integer;
  attribute LC_PROBE110_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE110_PID : string;
  attribute LC_PROBE110_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101110";
  attribute LC_PROBE110_TYPE : integer;
  attribute LC_PROBE110_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE110_WIDTH : integer;
  attribute LC_PROBE110_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE111_IS_DATA : string;
  attribute LC_PROBE111_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE111_IS_TRIG : string;
  attribute LC_PROBE111_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE111_MU_CNT : integer;
  attribute LC_PROBE111_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE111_PID : string;
  attribute LC_PROBE111_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001101111";
  attribute LC_PROBE111_TYPE : integer;
  attribute LC_PROBE111_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE111_WIDTH : integer;
  attribute LC_PROBE111_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE112_IS_DATA : string;
  attribute LC_PROBE112_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE112_IS_TRIG : string;
  attribute LC_PROBE112_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE112_MU_CNT : integer;
  attribute LC_PROBE112_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE112_PID : string;
  attribute LC_PROBE112_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110000";
  attribute LC_PROBE112_TYPE : integer;
  attribute LC_PROBE112_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE112_WIDTH : integer;
  attribute LC_PROBE112_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE113_IS_DATA : string;
  attribute LC_PROBE113_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE113_IS_TRIG : string;
  attribute LC_PROBE113_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE113_MU_CNT : integer;
  attribute LC_PROBE113_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE113_PID : string;
  attribute LC_PROBE113_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110001";
  attribute LC_PROBE113_TYPE : integer;
  attribute LC_PROBE113_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE113_WIDTH : integer;
  attribute LC_PROBE113_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE114_IS_DATA : string;
  attribute LC_PROBE114_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE114_IS_TRIG : string;
  attribute LC_PROBE114_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE114_MU_CNT : integer;
  attribute LC_PROBE114_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE114_PID : string;
  attribute LC_PROBE114_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110010";
  attribute LC_PROBE114_TYPE : integer;
  attribute LC_PROBE114_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE114_WIDTH : integer;
  attribute LC_PROBE114_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE115_IS_DATA : string;
  attribute LC_PROBE115_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE115_IS_TRIG : string;
  attribute LC_PROBE115_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE115_MU_CNT : integer;
  attribute LC_PROBE115_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE115_PID : string;
  attribute LC_PROBE115_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110011";
  attribute LC_PROBE115_TYPE : integer;
  attribute LC_PROBE115_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE115_WIDTH : integer;
  attribute LC_PROBE115_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE116_IS_DATA : string;
  attribute LC_PROBE116_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE116_IS_TRIG : string;
  attribute LC_PROBE116_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE116_MU_CNT : integer;
  attribute LC_PROBE116_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE116_PID : string;
  attribute LC_PROBE116_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110100";
  attribute LC_PROBE116_TYPE : integer;
  attribute LC_PROBE116_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE116_WIDTH : integer;
  attribute LC_PROBE116_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE117_IS_DATA : string;
  attribute LC_PROBE117_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE117_IS_TRIG : string;
  attribute LC_PROBE117_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE117_MU_CNT : integer;
  attribute LC_PROBE117_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE117_PID : string;
  attribute LC_PROBE117_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110101";
  attribute LC_PROBE117_TYPE : integer;
  attribute LC_PROBE117_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE117_WIDTH : integer;
  attribute LC_PROBE117_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE118_IS_DATA : string;
  attribute LC_PROBE118_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE118_IS_TRIG : string;
  attribute LC_PROBE118_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE118_MU_CNT : integer;
  attribute LC_PROBE118_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE118_PID : string;
  attribute LC_PROBE118_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110110";
  attribute LC_PROBE118_TYPE : integer;
  attribute LC_PROBE118_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE118_WIDTH : integer;
  attribute LC_PROBE118_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE119_IS_DATA : string;
  attribute LC_PROBE119_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE119_IS_TRIG : string;
  attribute LC_PROBE119_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE119_MU_CNT : integer;
  attribute LC_PROBE119_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE119_PID : string;
  attribute LC_PROBE119_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001110111";
  attribute LC_PROBE119_TYPE : integer;
  attribute LC_PROBE119_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE119_WIDTH : integer;
  attribute LC_PROBE119_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE11_IS_DATA : string;
  attribute LC_PROBE11_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE11_IS_TRIG : string;
  attribute LC_PROBE11_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE11_MU_CNT : integer;
  attribute LC_PROBE11_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE11_PID : string;
  attribute LC_PROBE11_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001011";
  attribute LC_PROBE11_TYPE : integer;
  attribute LC_PROBE11_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE11_WIDTH : integer;
  attribute LC_PROBE11_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE120_IS_DATA : string;
  attribute LC_PROBE120_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE120_IS_TRIG : string;
  attribute LC_PROBE120_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE120_MU_CNT : integer;
  attribute LC_PROBE120_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE120_PID : string;
  attribute LC_PROBE120_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111000";
  attribute LC_PROBE120_TYPE : integer;
  attribute LC_PROBE120_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE120_WIDTH : integer;
  attribute LC_PROBE120_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE121_IS_DATA : string;
  attribute LC_PROBE121_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE121_IS_TRIG : string;
  attribute LC_PROBE121_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE121_MU_CNT : integer;
  attribute LC_PROBE121_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE121_PID : string;
  attribute LC_PROBE121_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111001";
  attribute LC_PROBE121_TYPE : integer;
  attribute LC_PROBE121_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE121_WIDTH : integer;
  attribute LC_PROBE121_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE122_IS_DATA : string;
  attribute LC_PROBE122_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE122_IS_TRIG : string;
  attribute LC_PROBE122_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE122_MU_CNT : integer;
  attribute LC_PROBE122_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE122_PID : string;
  attribute LC_PROBE122_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111010";
  attribute LC_PROBE122_TYPE : integer;
  attribute LC_PROBE122_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE122_WIDTH : integer;
  attribute LC_PROBE122_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE123_IS_DATA : string;
  attribute LC_PROBE123_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE123_IS_TRIG : string;
  attribute LC_PROBE123_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE123_MU_CNT : integer;
  attribute LC_PROBE123_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE123_PID : string;
  attribute LC_PROBE123_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111011";
  attribute LC_PROBE123_TYPE : integer;
  attribute LC_PROBE123_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE123_WIDTH : integer;
  attribute LC_PROBE123_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE124_IS_DATA : string;
  attribute LC_PROBE124_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE124_IS_TRIG : string;
  attribute LC_PROBE124_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE124_MU_CNT : integer;
  attribute LC_PROBE124_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE124_PID : string;
  attribute LC_PROBE124_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111100";
  attribute LC_PROBE124_TYPE : integer;
  attribute LC_PROBE124_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE124_WIDTH : integer;
  attribute LC_PROBE124_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE125_IS_DATA : string;
  attribute LC_PROBE125_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE125_IS_TRIG : string;
  attribute LC_PROBE125_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE125_MU_CNT : integer;
  attribute LC_PROBE125_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE125_PID : string;
  attribute LC_PROBE125_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111101";
  attribute LC_PROBE125_TYPE : integer;
  attribute LC_PROBE125_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE125_WIDTH : integer;
  attribute LC_PROBE125_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE126_IS_DATA : string;
  attribute LC_PROBE126_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE126_IS_TRIG : string;
  attribute LC_PROBE126_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE126_MU_CNT : integer;
  attribute LC_PROBE126_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE126_PID : string;
  attribute LC_PROBE126_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111110";
  attribute LC_PROBE126_TYPE : integer;
  attribute LC_PROBE126_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE126_WIDTH : integer;
  attribute LC_PROBE126_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE127_IS_DATA : string;
  attribute LC_PROBE127_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE127_IS_TRIG : string;
  attribute LC_PROBE127_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE127_MU_CNT : integer;
  attribute LC_PROBE127_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE127_PID : string;
  attribute LC_PROBE127_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001111111";
  attribute LC_PROBE127_TYPE : integer;
  attribute LC_PROBE127_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE127_WIDTH : integer;
  attribute LC_PROBE127_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE128_IS_DATA : string;
  attribute LC_PROBE128_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE128_IS_TRIG : string;
  attribute LC_PROBE128_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE128_MU_CNT : integer;
  attribute LC_PROBE128_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE128_PID : string;
  attribute LC_PROBE128_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000000";
  attribute LC_PROBE128_TYPE : integer;
  attribute LC_PROBE128_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE128_WIDTH : integer;
  attribute LC_PROBE128_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE129_IS_DATA : string;
  attribute LC_PROBE129_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE129_IS_TRIG : string;
  attribute LC_PROBE129_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE129_MU_CNT : integer;
  attribute LC_PROBE129_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE129_PID : string;
  attribute LC_PROBE129_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000001";
  attribute LC_PROBE129_TYPE : integer;
  attribute LC_PROBE129_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE129_WIDTH : integer;
  attribute LC_PROBE129_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE12_IS_DATA : string;
  attribute LC_PROBE12_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE12_IS_TRIG : string;
  attribute LC_PROBE12_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE12_MU_CNT : integer;
  attribute LC_PROBE12_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE12_PID : string;
  attribute LC_PROBE12_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001100";
  attribute LC_PROBE12_TYPE : integer;
  attribute LC_PROBE12_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE12_WIDTH : integer;
  attribute LC_PROBE12_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE130_IS_DATA : string;
  attribute LC_PROBE130_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE130_IS_TRIG : string;
  attribute LC_PROBE130_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE130_MU_CNT : integer;
  attribute LC_PROBE130_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE130_PID : string;
  attribute LC_PROBE130_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000010";
  attribute LC_PROBE130_TYPE : integer;
  attribute LC_PROBE130_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE130_WIDTH : integer;
  attribute LC_PROBE130_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE131_IS_DATA : string;
  attribute LC_PROBE131_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE131_IS_TRIG : string;
  attribute LC_PROBE131_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE131_MU_CNT : integer;
  attribute LC_PROBE131_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE131_PID : string;
  attribute LC_PROBE131_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000011";
  attribute LC_PROBE131_TYPE : integer;
  attribute LC_PROBE131_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE131_WIDTH : integer;
  attribute LC_PROBE131_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE132_IS_DATA : string;
  attribute LC_PROBE132_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE132_IS_TRIG : string;
  attribute LC_PROBE132_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE132_MU_CNT : integer;
  attribute LC_PROBE132_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE132_PID : string;
  attribute LC_PROBE132_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000100";
  attribute LC_PROBE132_TYPE : integer;
  attribute LC_PROBE132_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE132_WIDTH : integer;
  attribute LC_PROBE132_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE133_IS_DATA : string;
  attribute LC_PROBE133_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE133_IS_TRIG : string;
  attribute LC_PROBE133_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE133_MU_CNT : integer;
  attribute LC_PROBE133_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE133_PID : string;
  attribute LC_PROBE133_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000101";
  attribute LC_PROBE133_TYPE : integer;
  attribute LC_PROBE133_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE133_WIDTH : integer;
  attribute LC_PROBE133_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE134_IS_DATA : string;
  attribute LC_PROBE134_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE134_IS_TRIG : string;
  attribute LC_PROBE134_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE134_MU_CNT : integer;
  attribute LC_PROBE134_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE134_PID : string;
  attribute LC_PROBE134_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000110";
  attribute LC_PROBE134_TYPE : integer;
  attribute LC_PROBE134_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE134_WIDTH : integer;
  attribute LC_PROBE134_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE135_IS_DATA : string;
  attribute LC_PROBE135_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE135_IS_TRIG : string;
  attribute LC_PROBE135_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE135_MU_CNT : integer;
  attribute LC_PROBE135_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE135_PID : string;
  attribute LC_PROBE135_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010000111";
  attribute LC_PROBE135_TYPE : integer;
  attribute LC_PROBE135_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE135_WIDTH : integer;
  attribute LC_PROBE135_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE136_IS_DATA : string;
  attribute LC_PROBE136_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE136_IS_TRIG : string;
  attribute LC_PROBE136_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE136_MU_CNT : integer;
  attribute LC_PROBE136_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE136_PID : string;
  attribute LC_PROBE136_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001000";
  attribute LC_PROBE136_TYPE : integer;
  attribute LC_PROBE136_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE136_WIDTH : integer;
  attribute LC_PROBE136_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE137_IS_DATA : string;
  attribute LC_PROBE137_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE137_IS_TRIG : string;
  attribute LC_PROBE137_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE137_MU_CNT : integer;
  attribute LC_PROBE137_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE137_PID : string;
  attribute LC_PROBE137_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001001";
  attribute LC_PROBE137_TYPE : integer;
  attribute LC_PROBE137_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE137_WIDTH : integer;
  attribute LC_PROBE137_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE138_IS_DATA : string;
  attribute LC_PROBE138_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE138_IS_TRIG : string;
  attribute LC_PROBE138_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE138_MU_CNT : integer;
  attribute LC_PROBE138_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE138_PID : string;
  attribute LC_PROBE138_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001010";
  attribute LC_PROBE138_TYPE : integer;
  attribute LC_PROBE138_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE138_WIDTH : integer;
  attribute LC_PROBE138_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE139_IS_DATA : string;
  attribute LC_PROBE139_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE139_IS_TRIG : string;
  attribute LC_PROBE139_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE139_MU_CNT : integer;
  attribute LC_PROBE139_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE139_PID : string;
  attribute LC_PROBE139_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001011";
  attribute LC_PROBE139_TYPE : integer;
  attribute LC_PROBE139_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE139_WIDTH : integer;
  attribute LC_PROBE139_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE13_IS_DATA : string;
  attribute LC_PROBE13_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE13_IS_TRIG : string;
  attribute LC_PROBE13_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE13_MU_CNT : integer;
  attribute LC_PROBE13_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE13_PID : string;
  attribute LC_PROBE13_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001101";
  attribute LC_PROBE13_TYPE : integer;
  attribute LC_PROBE13_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE13_WIDTH : integer;
  attribute LC_PROBE13_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE140_IS_DATA : string;
  attribute LC_PROBE140_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE140_IS_TRIG : string;
  attribute LC_PROBE140_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE140_MU_CNT : integer;
  attribute LC_PROBE140_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE140_PID : string;
  attribute LC_PROBE140_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001100";
  attribute LC_PROBE140_TYPE : integer;
  attribute LC_PROBE140_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE140_WIDTH : integer;
  attribute LC_PROBE140_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE141_IS_DATA : string;
  attribute LC_PROBE141_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE141_IS_TRIG : string;
  attribute LC_PROBE141_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE141_MU_CNT : integer;
  attribute LC_PROBE141_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE141_PID : string;
  attribute LC_PROBE141_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001101";
  attribute LC_PROBE141_TYPE : integer;
  attribute LC_PROBE141_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE141_WIDTH : integer;
  attribute LC_PROBE141_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE142_IS_DATA : string;
  attribute LC_PROBE142_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE142_IS_TRIG : string;
  attribute LC_PROBE142_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE142_MU_CNT : integer;
  attribute LC_PROBE142_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE142_PID : string;
  attribute LC_PROBE142_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001110";
  attribute LC_PROBE142_TYPE : integer;
  attribute LC_PROBE142_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE142_WIDTH : integer;
  attribute LC_PROBE142_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE143_IS_DATA : string;
  attribute LC_PROBE143_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE143_IS_TRIG : string;
  attribute LC_PROBE143_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE143_MU_CNT : integer;
  attribute LC_PROBE143_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE143_PID : string;
  attribute LC_PROBE143_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010001111";
  attribute LC_PROBE143_TYPE : integer;
  attribute LC_PROBE143_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE143_WIDTH : integer;
  attribute LC_PROBE143_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE144_IS_DATA : string;
  attribute LC_PROBE144_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE144_IS_TRIG : string;
  attribute LC_PROBE144_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE144_MU_CNT : integer;
  attribute LC_PROBE144_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE144_PID : string;
  attribute LC_PROBE144_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010000";
  attribute LC_PROBE144_TYPE : integer;
  attribute LC_PROBE144_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE144_WIDTH : integer;
  attribute LC_PROBE144_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE145_IS_DATA : string;
  attribute LC_PROBE145_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE145_IS_TRIG : string;
  attribute LC_PROBE145_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE145_MU_CNT : integer;
  attribute LC_PROBE145_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE145_PID : string;
  attribute LC_PROBE145_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010001";
  attribute LC_PROBE145_TYPE : integer;
  attribute LC_PROBE145_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE145_WIDTH : integer;
  attribute LC_PROBE145_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE146_IS_DATA : string;
  attribute LC_PROBE146_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE146_IS_TRIG : string;
  attribute LC_PROBE146_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE146_MU_CNT : integer;
  attribute LC_PROBE146_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE146_PID : string;
  attribute LC_PROBE146_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010010";
  attribute LC_PROBE146_TYPE : integer;
  attribute LC_PROBE146_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE146_WIDTH : integer;
  attribute LC_PROBE146_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE147_IS_DATA : string;
  attribute LC_PROBE147_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE147_IS_TRIG : string;
  attribute LC_PROBE147_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE147_MU_CNT : integer;
  attribute LC_PROBE147_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE147_PID : string;
  attribute LC_PROBE147_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010011";
  attribute LC_PROBE147_TYPE : integer;
  attribute LC_PROBE147_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE147_WIDTH : integer;
  attribute LC_PROBE147_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE148_IS_DATA : string;
  attribute LC_PROBE148_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE148_IS_TRIG : string;
  attribute LC_PROBE148_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE148_MU_CNT : integer;
  attribute LC_PROBE148_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE148_PID : string;
  attribute LC_PROBE148_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010100";
  attribute LC_PROBE148_TYPE : integer;
  attribute LC_PROBE148_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE148_WIDTH : integer;
  attribute LC_PROBE148_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE149_IS_DATA : string;
  attribute LC_PROBE149_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE149_IS_TRIG : string;
  attribute LC_PROBE149_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE149_MU_CNT : integer;
  attribute LC_PROBE149_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE149_PID : string;
  attribute LC_PROBE149_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010101";
  attribute LC_PROBE149_TYPE : integer;
  attribute LC_PROBE149_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE149_WIDTH : integer;
  attribute LC_PROBE149_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE14_IS_DATA : string;
  attribute LC_PROBE14_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE14_IS_TRIG : string;
  attribute LC_PROBE14_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE14_MU_CNT : integer;
  attribute LC_PROBE14_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE14_PID : string;
  attribute LC_PROBE14_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001110";
  attribute LC_PROBE14_TYPE : integer;
  attribute LC_PROBE14_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE14_WIDTH : integer;
  attribute LC_PROBE14_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE150_IS_DATA : string;
  attribute LC_PROBE150_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE150_IS_TRIG : string;
  attribute LC_PROBE150_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE150_MU_CNT : integer;
  attribute LC_PROBE150_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE150_PID : string;
  attribute LC_PROBE150_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010110";
  attribute LC_PROBE150_TYPE : integer;
  attribute LC_PROBE150_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE150_WIDTH : integer;
  attribute LC_PROBE150_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE151_IS_DATA : string;
  attribute LC_PROBE151_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE151_IS_TRIG : string;
  attribute LC_PROBE151_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE151_MU_CNT : integer;
  attribute LC_PROBE151_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE151_PID : string;
  attribute LC_PROBE151_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010010111";
  attribute LC_PROBE151_TYPE : integer;
  attribute LC_PROBE151_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE151_WIDTH : integer;
  attribute LC_PROBE151_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE152_IS_DATA : string;
  attribute LC_PROBE152_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE152_IS_TRIG : string;
  attribute LC_PROBE152_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE152_MU_CNT : integer;
  attribute LC_PROBE152_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE152_PID : string;
  attribute LC_PROBE152_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011000";
  attribute LC_PROBE152_TYPE : integer;
  attribute LC_PROBE152_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE152_WIDTH : integer;
  attribute LC_PROBE152_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE153_IS_DATA : string;
  attribute LC_PROBE153_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE153_IS_TRIG : string;
  attribute LC_PROBE153_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE153_MU_CNT : integer;
  attribute LC_PROBE153_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE153_PID : string;
  attribute LC_PROBE153_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011001";
  attribute LC_PROBE153_TYPE : integer;
  attribute LC_PROBE153_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE153_WIDTH : integer;
  attribute LC_PROBE153_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE154_IS_DATA : string;
  attribute LC_PROBE154_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE154_IS_TRIG : string;
  attribute LC_PROBE154_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE154_MU_CNT : integer;
  attribute LC_PROBE154_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE154_PID : string;
  attribute LC_PROBE154_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011010";
  attribute LC_PROBE154_TYPE : integer;
  attribute LC_PROBE154_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE154_WIDTH : integer;
  attribute LC_PROBE154_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE155_IS_DATA : string;
  attribute LC_PROBE155_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE155_IS_TRIG : string;
  attribute LC_PROBE155_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE155_MU_CNT : integer;
  attribute LC_PROBE155_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE155_PID : string;
  attribute LC_PROBE155_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011011";
  attribute LC_PROBE155_TYPE : integer;
  attribute LC_PROBE155_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE155_WIDTH : integer;
  attribute LC_PROBE155_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE156_IS_DATA : string;
  attribute LC_PROBE156_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE156_IS_TRIG : string;
  attribute LC_PROBE156_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE156_MU_CNT : integer;
  attribute LC_PROBE156_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE156_PID : string;
  attribute LC_PROBE156_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011100";
  attribute LC_PROBE156_TYPE : integer;
  attribute LC_PROBE156_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE156_WIDTH : integer;
  attribute LC_PROBE156_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE157_IS_DATA : string;
  attribute LC_PROBE157_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE157_IS_TRIG : string;
  attribute LC_PROBE157_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE157_MU_CNT : integer;
  attribute LC_PROBE157_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE157_PID : string;
  attribute LC_PROBE157_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011101";
  attribute LC_PROBE157_TYPE : integer;
  attribute LC_PROBE157_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE157_WIDTH : integer;
  attribute LC_PROBE157_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE158_IS_DATA : string;
  attribute LC_PROBE158_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE158_IS_TRIG : string;
  attribute LC_PROBE158_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE158_MU_CNT : integer;
  attribute LC_PROBE158_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE158_PID : string;
  attribute LC_PROBE158_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011110";
  attribute LC_PROBE158_TYPE : integer;
  attribute LC_PROBE158_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE158_WIDTH : integer;
  attribute LC_PROBE158_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE159_IS_DATA : string;
  attribute LC_PROBE159_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE159_IS_TRIG : string;
  attribute LC_PROBE159_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE159_MU_CNT : integer;
  attribute LC_PROBE159_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE159_PID : string;
  attribute LC_PROBE159_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010011111";
  attribute LC_PROBE159_TYPE : integer;
  attribute LC_PROBE159_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE159_WIDTH : integer;
  attribute LC_PROBE159_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE15_IS_DATA : string;
  attribute LC_PROBE15_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE15_IS_TRIG : string;
  attribute LC_PROBE15_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE15_MU_CNT : integer;
  attribute LC_PROBE15_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE15_PID : string;
  attribute LC_PROBE15_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001111";
  attribute LC_PROBE15_TYPE : integer;
  attribute LC_PROBE15_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE15_WIDTH : integer;
  attribute LC_PROBE15_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE160_IS_DATA : string;
  attribute LC_PROBE160_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE160_IS_TRIG : string;
  attribute LC_PROBE160_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE160_MU_CNT : integer;
  attribute LC_PROBE160_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE160_PID : string;
  attribute LC_PROBE160_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100000";
  attribute LC_PROBE160_TYPE : integer;
  attribute LC_PROBE160_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE160_WIDTH : integer;
  attribute LC_PROBE160_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE161_IS_DATA : string;
  attribute LC_PROBE161_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE161_IS_TRIG : string;
  attribute LC_PROBE161_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE161_MU_CNT : integer;
  attribute LC_PROBE161_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE161_PID : string;
  attribute LC_PROBE161_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100001";
  attribute LC_PROBE161_TYPE : integer;
  attribute LC_PROBE161_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE161_WIDTH : integer;
  attribute LC_PROBE161_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE162_IS_DATA : string;
  attribute LC_PROBE162_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE162_IS_TRIG : string;
  attribute LC_PROBE162_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE162_MU_CNT : integer;
  attribute LC_PROBE162_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE162_PID : string;
  attribute LC_PROBE162_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100010";
  attribute LC_PROBE162_TYPE : integer;
  attribute LC_PROBE162_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE162_WIDTH : integer;
  attribute LC_PROBE162_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE163_IS_DATA : string;
  attribute LC_PROBE163_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE163_IS_TRIG : string;
  attribute LC_PROBE163_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE163_MU_CNT : integer;
  attribute LC_PROBE163_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE163_PID : string;
  attribute LC_PROBE163_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100011";
  attribute LC_PROBE163_TYPE : integer;
  attribute LC_PROBE163_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE163_WIDTH : integer;
  attribute LC_PROBE163_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE164_IS_DATA : string;
  attribute LC_PROBE164_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE164_IS_TRIG : string;
  attribute LC_PROBE164_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE164_MU_CNT : integer;
  attribute LC_PROBE164_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE164_PID : string;
  attribute LC_PROBE164_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100100";
  attribute LC_PROBE164_TYPE : integer;
  attribute LC_PROBE164_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE164_WIDTH : integer;
  attribute LC_PROBE164_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE165_IS_DATA : string;
  attribute LC_PROBE165_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE165_IS_TRIG : string;
  attribute LC_PROBE165_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE165_MU_CNT : integer;
  attribute LC_PROBE165_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE165_PID : string;
  attribute LC_PROBE165_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100101";
  attribute LC_PROBE165_TYPE : integer;
  attribute LC_PROBE165_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE165_WIDTH : integer;
  attribute LC_PROBE165_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE166_IS_DATA : string;
  attribute LC_PROBE166_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE166_IS_TRIG : string;
  attribute LC_PROBE166_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE166_MU_CNT : integer;
  attribute LC_PROBE166_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE166_PID : string;
  attribute LC_PROBE166_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100110";
  attribute LC_PROBE166_TYPE : integer;
  attribute LC_PROBE166_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE166_WIDTH : integer;
  attribute LC_PROBE166_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE167_IS_DATA : string;
  attribute LC_PROBE167_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE167_IS_TRIG : string;
  attribute LC_PROBE167_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE167_MU_CNT : integer;
  attribute LC_PROBE167_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE167_PID : string;
  attribute LC_PROBE167_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010100111";
  attribute LC_PROBE167_TYPE : integer;
  attribute LC_PROBE167_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE167_WIDTH : integer;
  attribute LC_PROBE167_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE168_IS_DATA : string;
  attribute LC_PROBE168_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE168_IS_TRIG : string;
  attribute LC_PROBE168_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE168_MU_CNT : integer;
  attribute LC_PROBE168_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE168_PID : string;
  attribute LC_PROBE168_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101000";
  attribute LC_PROBE168_TYPE : integer;
  attribute LC_PROBE168_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE168_WIDTH : integer;
  attribute LC_PROBE168_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE169_IS_DATA : string;
  attribute LC_PROBE169_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE169_IS_TRIG : string;
  attribute LC_PROBE169_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE169_MU_CNT : integer;
  attribute LC_PROBE169_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE169_PID : string;
  attribute LC_PROBE169_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101001";
  attribute LC_PROBE169_TYPE : integer;
  attribute LC_PROBE169_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE169_WIDTH : integer;
  attribute LC_PROBE169_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE16_IS_DATA : string;
  attribute LC_PROBE16_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE16_IS_TRIG : string;
  attribute LC_PROBE16_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE16_MU_CNT : integer;
  attribute LC_PROBE16_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE16_PID : string;
  attribute LC_PROBE16_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010000";
  attribute LC_PROBE16_TYPE : integer;
  attribute LC_PROBE16_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE16_WIDTH : integer;
  attribute LC_PROBE16_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE170_IS_DATA : string;
  attribute LC_PROBE170_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE170_IS_TRIG : string;
  attribute LC_PROBE170_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE170_MU_CNT : integer;
  attribute LC_PROBE170_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE170_PID : string;
  attribute LC_PROBE170_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101010";
  attribute LC_PROBE170_TYPE : integer;
  attribute LC_PROBE170_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE170_WIDTH : integer;
  attribute LC_PROBE170_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE171_IS_DATA : string;
  attribute LC_PROBE171_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE171_IS_TRIG : string;
  attribute LC_PROBE171_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE171_MU_CNT : integer;
  attribute LC_PROBE171_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE171_PID : string;
  attribute LC_PROBE171_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101011";
  attribute LC_PROBE171_TYPE : integer;
  attribute LC_PROBE171_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE171_WIDTH : integer;
  attribute LC_PROBE171_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE172_IS_DATA : string;
  attribute LC_PROBE172_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE172_IS_TRIG : string;
  attribute LC_PROBE172_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE172_MU_CNT : integer;
  attribute LC_PROBE172_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE172_PID : string;
  attribute LC_PROBE172_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101100";
  attribute LC_PROBE172_TYPE : integer;
  attribute LC_PROBE172_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE172_WIDTH : integer;
  attribute LC_PROBE172_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE173_IS_DATA : string;
  attribute LC_PROBE173_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE173_IS_TRIG : string;
  attribute LC_PROBE173_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE173_MU_CNT : integer;
  attribute LC_PROBE173_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE173_PID : string;
  attribute LC_PROBE173_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101101";
  attribute LC_PROBE173_TYPE : integer;
  attribute LC_PROBE173_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE173_WIDTH : integer;
  attribute LC_PROBE173_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE174_IS_DATA : string;
  attribute LC_PROBE174_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE174_IS_TRIG : string;
  attribute LC_PROBE174_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE174_MU_CNT : integer;
  attribute LC_PROBE174_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE174_PID : string;
  attribute LC_PROBE174_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101110";
  attribute LC_PROBE174_TYPE : integer;
  attribute LC_PROBE174_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE174_WIDTH : integer;
  attribute LC_PROBE174_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE175_IS_DATA : string;
  attribute LC_PROBE175_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE175_IS_TRIG : string;
  attribute LC_PROBE175_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE175_MU_CNT : integer;
  attribute LC_PROBE175_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE175_PID : string;
  attribute LC_PROBE175_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010101111";
  attribute LC_PROBE175_TYPE : integer;
  attribute LC_PROBE175_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE175_WIDTH : integer;
  attribute LC_PROBE175_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE176_IS_DATA : string;
  attribute LC_PROBE176_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE176_IS_TRIG : string;
  attribute LC_PROBE176_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE176_MU_CNT : integer;
  attribute LC_PROBE176_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE176_PID : string;
  attribute LC_PROBE176_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110000";
  attribute LC_PROBE176_TYPE : integer;
  attribute LC_PROBE176_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE176_WIDTH : integer;
  attribute LC_PROBE176_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE177_IS_DATA : string;
  attribute LC_PROBE177_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE177_IS_TRIG : string;
  attribute LC_PROBE177_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE177_MU_CNT : integer;
  attribute LC_PROBE177_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE177_PID : string;
  attribute LC_PROBE177_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110001";
  attribute LC_PROBE177_TYPE : integer;
  attribute LC_PROBE177_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE177_WIDTH : integer;
  attribute LC_PROBE177_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE178_IS_DATA : string;
  attribute LC_PROBE178_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE178_IS_TRIG : string;
  attribute LC_PROBE178_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE178_MU_CNT : integer;
  attribute LC_PROBE178_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE178_PID : string;
  attribute LC_PROBE178_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110010";
  attribute LC_PROBE178_TYPE : integer;
  attribute LC_PROBE178_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE178_WIDTH : integer;
  attribute LC_PROBE178_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE179_IS_DATA : string;
  attribute LC_PROBE179_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE179_IS_TRIG : string;
  attribute LC_PROBE179_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE179_MU_CNT : integer;
  attribute LC_PROBE179_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE179_PID : string;
  attribute LC_PROBE179_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110011";
  attribute LC_PROBE179_TYPE : integer;
  attribute LC_PROBE179_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE179_WIDTH : integer;
  attribute LC_PROBE179_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE17_IS_DATA : string;
  attribute LC_PROBE17_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE17_IS_TRIG : string;
  attribute LC_PROBE17_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE17_MU_CNT : integer;
  attribute LC_PROBE17_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE17_PID : string;
  attribute LC_PROBE17_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010001";
  attribute LC_PROBE17_TYPE : integer;
  attribute LC_PROBE17_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE17_WIDTH : integer;
  attribute LC_PROBE17_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE180_IS_DATA : string;
  attribute LC_PROBE180_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE180_IS_TRIG : string;
  attribute LC_PROBE180_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE180_MU_CNT : integer;
  attribute LC_PROBE180_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE180_PID : string;
  attribute LC_PROBE180_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110100";
  attribute LC_PROBE180_TYPE : integer;
  attribute LC_PROBE180_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE180_WIDTH : integer;
  attribute LC_PROBE180_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE181_IS_DATA : string;
  attribute LC_PROBE181_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE181_IS_TRIG : string;
  attribute LC_PROBE181_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE181_MU_CNT : integer;
  attribute LC_PROBE181_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE181_PID : string;
  attribute LC_PROBE181_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110101";
  attribute LC_PROBE181_TYPE : integer;
  attribute LC_PROBE181_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE181_WIDTH : integer;
  attribute LC_PROBE181_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE182_IS_DATA : string;
  attribute LC_PROBE182_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE182_IS_TRIG : string;
  attribute LC_PROBE182_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE182_MU_CNT : integer;
  attribute LC_PROBE182_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE182_PID : string;
  attribute LC_PROBE182_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110110";
  attribute LC_PROBE182_TYPE : integer;
  attribute LC_PROBE182_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE182_WIDTH : integer;
  attribute LC_PROBE182_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE183_IS_DATA : string;
  attribute LC_PROBE183_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE183_IS_TRIG : string;
  attribute LC_PROBE183_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE183_MU_CNT : integer;
  attribute LC_PROBE183_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE183_PID : string;
  attribute LC_PROBE183_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010110111";
  attribute LC_PROBE183_TYPE : integer;
  attribute LC_PROBE183_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE183_WIDTH : integer;
  attribute LC_PROBE183_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE184_IS_DATA : string;
  attribute LC_PROBE184_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE184_IS_TRIG : string;
  attribute LC_PROBE184_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE184_MU_CNT : integer;
  attribute LC_PROBE184_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE184_PID : string;
  attribute LC_PROBE184_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111000";
  attribute LC_PROBE184_TYPE : integer;
  attribute LC_PROBE184_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE184_WIDTH : integer;
  attribute LC_PROBE184_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE185_IS_DATA : string;
  attribute LC_PROBE185_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE185_IS_TRIG : string;
  attribute LC_PROBE185_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE185_MU_CNT : integer;
  attribute LC_PROBE185_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE185_PID : string;
  attribute LC_PROBE185_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111001";
  attribute LC_PROBE185_TYPE : integer;
  attribute LC_PROBE185_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE185_WIDTH : integer;
  attribute LC_PROBE185_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE186_IS_DATA : string;
  attribute LC_PROBE186_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE186_IS_TRIG : string;
  attribute LC_PROBE186_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE186_MU_CNT : integer;
  attribute LC_PROBE186_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE186_PID : string;
  attribute LC_PROBE186_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111010";
  attribute LC_PROBE186_TYPE : integer;
  attribute LC_PROBE186_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE186_WIDTH : integer;
  attribute LC_PROBE186_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE187_IS_DATA : string;
  attribute LC_PROBE187_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE187_IS_TRIG : string;
  attribute LC_PROBE187_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE187_MU_CNT : integer;
  attribute LC_PROBE187_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE187_PID : string;
  attribute LC_PROBE187_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111011";
  attribute LC_PROBE187_TYPE : integer;
  attribute LC_PROBE187_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE187_WIDTH : integer;
  attribute LC_PROBE187_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE188_IS_DATA : string;
  attribute LC_PROBE188_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE188_IS_TRIG : string;
  attribute LC_PROBE188_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE188_MU_CNT : integer;
  attribute LC_PROBE188_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE188_PID : string;
  attribute LC_PROBE188_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111100";
  attribute LC_PROBE188_TYPE : integer;
  attribute LC_PROBE188_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE188_WIDTH : integer;
  attribute LC_PROBE188_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE189_IS_DATA : string;
  attribute LC_PROBE189_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE189_IS_TRIG : string;
  attribute LC_PROBE189_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE189_MU_CNT : integer;
  attribute LC_PROBE189_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE189_PID : string;
  attribute LC_PROBE189_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111101";
  attribute LC_PROBE189_TYPE : integer;
  attribute LC_PROBE189_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE189_WIDTH : integer;
  attribute LC_PROBE189_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE18_IS_DATA : string;
  attribute LC_PROBE18_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE18_IS_TRIG : string;
  attribute LC_PROBE18_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE18_MU_CNT : integer;
  attribute LC_PROBE18_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE18_PID : string;
  attribute LC_PROBE18_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010010";
  attribute LC_PROBE18_TYPE : integer;
  attribute LC_PROBE18_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE18_WIDTH : integer;
  attribute LC_PROBE18_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE190_IS_DATA : string;
  attribute LC_PROBE190_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE190_IS_TRIG : string;
  attribute LC_PROBE190_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE190_MU_CNT : integer;
  attribute LC_PROBE190_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE190_PID : string;
  attribute LC_PROBE190_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111110";
  attribute LC_PROBE190_TYPE : integer;
  attribute LC_PROBE190_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE190_WIDTH : integer;
  attribute LC_PROBE190_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE191_IS_DATA : string;
  attribute LC_PROBE191_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE191_IS_TRIG : string;
  attribute LC_PROBE191_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE191_MU_CNT : integer;
  attribute LC_PROBE191_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE191_PID : string;
  attribute LC_PROBE191_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000010111111";
  attribute LC_PROBE191_TYPE : integer;
  attribute LC_PROBE191_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE191_WIDTH : integer;
  attribute LC_PROBE191_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE192_IS_DATA : string;
  attribute LC_PROBE192_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE192_IS_TRIG : string;
  attribute LC_PROBE192_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE192_MU_CNT : integer;
  attribute LC_PROBE192_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE192_PID : string;
  attribute LC_PROBE192_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000000";
  attribute LC_PROBE192_TYPE : integer;
  attribute LC_PROBE192_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE192_WIDTH : integer;
  attribute LC_PROBE192_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE193_IS_DATA : string;
  attribute LC_PROBE193_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE193_IS_TRIG : string;
  attribute LC_PROBE193_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE193_MU_CNT : integer;
  attribute LC_PROBE193_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE193_PID : string;
  attribute LC_PROBE193_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000001";
  attribute LC_PROBE193_TYPE : integer;
  attribute LC_PROBE193_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE193_WIDTH : integer;
  attribute LC_PROBE193_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE194_IS_DATA : string;
  attribute LC_PROBE194_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE194_IS_TRIG : string;
  attribute LC_PROBE194_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE194_MU_CNT : integer;
  attribute LC_PROBE194_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE194_PID : string;
  attribute LC_PROBE194_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000010";
  attribute LC_PROBE194_TYPE : integer;
  attribute LC_PROBE194_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE194_WIDTH : integer;
  attribute LC_PROBE194_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE195_IS_DATA : string;
  attribute LC_PROBE195_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE195_IS_TRIG : string;
  attribute LC_PROBE195_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE195_MU_CNT : integer;
  attribute LC_PROBE195_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE195_PID : string;
  attribute LC_PROBE195_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000011";
  attribute LC_PROBE195_TYPE : integer;
  attribute LC_PROBE195_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE195_WIDTH : integer;
  attribute LC_PROBE195_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE196_IS_DATA : string;
  attribute LC_PROBE196_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE196_IS_TRIG : string;
  attribute LC_PROBE196_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE196_MU_CNT : integer;
  attribute LC_PROBE196_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE196_PID : string;
  attribute LC_PROBE196_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000100";
  attribute LC_PROBE196_TYPE : integer;
  attribute LC_PROBE196_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE196_WIDTH : integer;
  attribute LC_PROBE196_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE197_IS_DATA : string;
  attribute LC_PROBE197_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE197_IS_TRIG : string;
  attribute LC_PROBE197_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE197_MU_CNT : integer;
  attribute LC_PROBE197_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE197_PID : string;
  attribute LC_PROBE197_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000101";
  attribute LC_PROBE197_TYPE : integer;
  attribute LC_PROBE197_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE197_WIDTH : integer;
  attribute LC_PROBE197_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE198_IS_DATA : string;
  attribute LC_PROBE198_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE198_IS_TRIG : string;
  attribute LC_PROBE198_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE198_MU_CNT : integer;
  attribute LC_PROBE198_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE198_PID : string;
  attribute LC_PROBE198_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000110";
  attribute LC_PROBE198_TYPE : integer;
  attribute LC_PROBE198_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE198_WIDTH : integer;
  attribute LC_PROBE198_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE199_IS_DATA : string;
  attribute LC_PROBE199_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE199_IS_TRIG : string;
  attribute LC_PROBE199_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE199_MU_CNT : integer;
  attribute LC_PROBE199_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE199_PID : string;
  attribute LC_PROBE199_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011000111";
  attribute LC_PROBE199_TYPE : integer;
  attribute LC_PROBE199_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE199_WIDTH : integer;
  attribute LC_PROBE199_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE19_IS_DATA : string;
  attribute LC_PROBE19_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE19_IS_TRIG : string;
  attribute LC_PROBE19_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE19_MU_CNT : integer;
  attribute LC_PROBE19_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE19_PID : string;
  attribute LC_PROBE19_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010011";
  attribute LC_PROBE19_TYPE : integer;
  attribute LC_PROBE19_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE19_WIDTH : integer;
  attribute LC_PROBE19_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1_IS_DATA : string;
  attribute LC_PROBE1_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE1_IS_TRIG : string;
  attribute LC_PROBE1_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE1_MU_CNT : integer;
  attribute LC_PROBE1_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE1_PID : string;
  attribute LC_PROBE1_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000001";
  attribute LC_PROBE1_TYPE : integer;
  attribute LC_PROBE1_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE1_WIDTH : integer;
  attribute LC_PROBE1_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE200_IS_DATA : string;
  attribute LC_PROBE200_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE200_IS_TRIG : string;
  attribute LC_PROBE200_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE200_MU_CNT : integer;
  attribute LC_PROBE200_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE200_PID : string;
  attribute LC_PROBE200_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001000";
  attribute LC_PROBE200_TYPE : integer;
  attribute LC_PROBE200_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE200_WIDTH : integer;
  attribute LC_PROBE200_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE201_IS_DATA : string;
  attribute LC_PROBE201_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE201_IS_TRIG : string;
  attribute LC_PROBE201_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE201_MU_CNT : integer;
  attribute LC_PROBE201_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE201_PID : string;
  attribute LC_PROBE201_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001001";
  attribute LC_PROBE201_TYPE : integer;
  attribute LC_PROBE201_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE201_WIDTH : integer;
  attribute LC_PROBE201_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE202_IS_DATA : string;
  attribute LC_PROBE202_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE202_IS_TRIG : string;
  attribute LC_PROBE202_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE202_MU_CNT : integer;
  attribute LC_PROBE202_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE202_PID : string;
  attribute LC_PROBE202_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001010";
  attribute LC_PROBE202_TYPE : integer;
  attribute LC_PROBE202_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE202_WIDTH : integer;
  attribute LC_PROBE202_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE203_IS_DATA : string;
  attribute LC_PROBE203_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE203_IS_TRIG : string;
  attribute LC_PROBE203_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE203_MU_CNT : integer;
  attribute LC_PROBE203_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE203_PID : string;
  attribute LC_PROBE203_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001011";
  attribute LC_PROBE203_TYPE : integer;
  attribute LC_PROBE203_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE203_WIDTH : integer;
  attribute LC_PROBE203_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE204_IS_DATA : string;
  attribute LC_PROBE204_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE204_IS_TRIG : string;
  attribute LC_PROBE204_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE204_MU_CNT : integer;
  attribute LC_PROBE204_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE204_PID : string;
  attribute LC_PROBE204_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001100";
  attribute LC_PROBE204_TYPE : integer;
  attribute LC_PROBE204_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE204_WIDTH : integer;
  attribute LC_PROBE204_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE205_IS_DATA : string;
  attribute LC_PROBE205_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE205_IS_TRIG : string;
  attribute LC_PROBE205_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE205_MU_CNT : integer;
  attribute LC_PROBE205_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE205_PID : string;
  attribute LC_PROBE205_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001101";
  attribute LC_PROBE205_TYPE : integer;
  attribute LC_PROBE205_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE205_WIDTH : integer;
  attribute LC_PROBE205_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE206_IS_DATA : string;
  attribute LC_PROBE206_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE206_IS_TRIG : string;
  attribute LC_PROBE206_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE206_MU_CNT : integer;
  attribute LC_PROBE206_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE206_PID : string;
  attribute LC_PROBE206_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001110";
  attribute LC_PROBE206_TYPE : integer;
  attribute LC_PROBE206_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE206_WIDTH : integer;
  attribute LC_PROBE206_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE207_IS_DATA : string;
  attribute LC_PROBE207_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE207_IS_TRIG : string;
  attribute LC_PROBE207_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE207_MU_CNT : integer;
  attribute LC_PROBE207_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE207_PID : string;
  attribute LC_PROBE207_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011001111";
  attribute LC_PROBE207_TYPE : integer;
  attribute LC_PROBE207_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE207_WIDTH : integer;
  attribute LC_PROBE207_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE208_IS_DATA : string;
  attribute LC_PROBE208_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE208_IS_TRIG : string;
  attribute LC_PROBE208_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE208_MU_CNT : integer;
  attribute LC_PROBE208_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE208_PID : string;
  attribute LC_PROBE208_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010000";
  attribute LC_PROBE208_TYPE : integer;
  attribute LC_PROBE208_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE208_WIDTH : integer;
  attribute LC_PROBE208_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE209_IS_DATA : string;
  attribute LC_PROBE209_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE209_IS_TRIG : string;
  attribute LC_PROBE209_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE209_MU_CNT : integer;
  attribute LC_PROBE209_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE209_PID : string;
  attribute LC_PROBE209_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010001";
  attribute LC_PROBE209_TYPE : integer;
  attribute LC_PROBE209_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE209_WIDTH : integer;
  attribute LC_PROBE209_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE20_IS_DATA : string;
  attribute LC_PROBE20_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE20_IS_TRIG : string;
  attribute LC_PROBE20_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE20_MU_CNT : integer;
  attribute LC_PROBE20_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE20_PID : string;
  attribute LC_PROBE20_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010100";
  attribute LC_PROBE20_TYPE : integer;
  attribute LC_PROBE20_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE20_WIDTH : integer;
  attribute LC_PROBE20_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE210_IS_DATA : string;
  attribute LC_PROBE210_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE210_IS_TRIG : string;
  attribute LC_PROBE210_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE210_MU_CNT : integer;
  attribute LC_PROBE210_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE210_PID : string;
  attribute LC_PROBE210_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010010";
  attribute LC_PROBE210_TYPE : integer;
  attribute LC_PROBE210_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE210_WIDTH : integer;
  attribute LC_PROBE210_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE211_IS_DATA : string;
  attribute LC_PROBE211_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE211_IS_TRIG : string;
  attribute LC_PROBE211_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE211_MU_CNT : integer;
  attribute LC_PROBE211_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE211_PID : string;
  attribute LC_PROBE211_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010011";
  attribute LC_PROBE211_TYPE : integer;
  attribute LC_PROBE211_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE211_WIDTH : integer;
  attribute LC_PROBE211_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE212_IS_DATA : string;
  attribute LC_PROBE212_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE212_IS_TRIG : string;
  attribute LC_PROBE212_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE212_MU_CNT : integer;
  attribute LC_PROBE212_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE212_PID : string;
  attribute LC_PROBE212_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010100";
  attribute LC_PROBE212_TYPE : integer;
  attribute LC_PROBE212_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE212_WIDTH : integer;
  attribute LC_PROBE212_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE213_IS_DATA : string;
  attribute LC_PROBE213_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE213_IS_TRIG : string;
  attribute LC_PROBE213_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE213_MU_CNT : integer;
  attribute LC_PROBE213_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE213_PID : string;
  attribute LC_PROBE213_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010101";
  attribute LC_PROBE213_TYPE : integer;
  attribute LC_PROBE213_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE213_WIDTH : integer;
  attribute LC_PROBE213_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE214_IS_DATA : string;
  attribute LC_PROBE214_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE214_IS_TRIG : string;
  attribute LC_PROBE214_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE214_MU_CNT : integer;
  attribute LC_PROBE214_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE214_PID : string;
  attribute LC_PROBE214_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010110";
  attribute LC_PROBE214_TYPE : integer;
  attribute LC_PROBE214_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE214_WIDTH : integer;
  attribute LC_PROBE214_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE215_IS_DATA : string;
  attribute LC_PROBE215_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE215_IS_TRIG : string;
  attribute LC_PROBE215_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE215_MU_CNT : integer;
  attribute LC_PROBE215_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE215_PID : string;
  attribute LC_PROBE215_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011010111";
  attribute LC_PROBE215_TYPE : integer;
  attribute LC_PROBE215_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE215_WIDTH : integer;
  attribute LC_PROBE215_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE216_IS_DATA : string;
  attribute LC_PROBE216_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE216_IS_TRIG : string;
  attribute LC_PROBE216_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE216_MU_CNT : integer;
  attribute LC_PROBE216_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE216_PID : string;
  attribute LC_PROBE216_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011000";
  attribute LC_PROBE216_TYPE : integer;
  attribute LC_PROBE216_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE216_WIDTH : integer;
  attribute LC_PROBE216_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE217_IS_DATA : string;
  attribute LC_PROBE217_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE217_IS_TRIG : string;
  attribute LC_PROBE217_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE217_MU_CNT : integer;
  attribute LC_PROBE217_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE217_PID : string;
  attribute LC_PROBE217_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011001";
  attribute LC_PROBE217_TYPE : integer;
  attribute LC_PROBE217_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE217_WIDTH : integer;
  attribute LC_PROBE217_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE218_IS_DATA : string;
  attribute LC_PROBE218_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE218_IS_TRIG : string;
  attribute LC_PROBE218_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE218_MU_CNT : integer;
  attribute LC_PROBE218_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE218_PID : string;
  attribute LC_PROBE218_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011010";
  attribute LC_PROBE218_TYPE : integer;
  attribute LC_PROBE218_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE218_WIDTH : integer;
  attribute LC_PROBE218_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE219_IS_DATA : string;
  attribute LC_PROBE219_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE219_IS_TRIG : string;
  attribute LC_PROBE219_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE219_MU_CNT : integer;
  attribute LC_PROBE219_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE219_PID : string;
  attribute LC_PROBE219_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011011";
  attribute LC_PROBE219_TYPE : integer;
  attribute LC_PROBE219_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE219_WIDTH : integer;
  attribute LC_PROBE219_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE21_IS_DATA : string;
  attribute LC_PROBE21_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE21_IS_TRIG : string;
  attribute LC_PROBE21_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE21_MU_CNT : integer;
  attribute LC_PROBE21_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE21_PID : string;
  attribute LC_PROBE21_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010101";
  attribute LC_PROBE21_TYPE : integer;
  attribute LC_PROBE21_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE21_WIDTH : integer;
  attribute LC_PROBE21_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE220_IS_DATA : string;
  attribute LC_PROBE220_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE220_IS_TRIG : string;
  attribute LC_PROBE220_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE220_MU_CNT : integer;
  attribute LC_PROBE220_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE220_PID : string;
  attribute LC_PROBE220_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011100";
  attribute LC_PROBE220_TYPE : integer;
  attribute LC_PROBE220_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE220_WIDTH : integer;
  attribute LC_PROBE220_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE221_IS_DATA : string;
  attribute LC_PROBE221_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE221_IS_TRIG : string;
  attribute LC_PROBE221_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE221_MU_CNT : integer;
  attribute LC_PROBE221_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE221_PID : string;
  attribute LC_PROBE221_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011101";
  attribute LC_PROBE221_TYPE : integer;
  attribute LC_PROBE221_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE221_WIDTH : integer;
  attribute LC_PROBE221_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE222_IS_DATA : string;
  attribute LC_PROBE222_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE222_IS_TRIG : string;
  attribute LC_PROBE222_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE222_MU_CNT : integer;
  attribute LC_PROBE222_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE222_PID : string;
  attribute LC_PROBE222_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011110";
  attribute LC_PROBE222_TYPE : integer;
  attribute LC_PROBE222_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE222_WIDTH : integer;
  attribute LC_PROBE222_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE223_IS_DATA : string;
  attribute LC_PROBE223_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE223_IS_TRIG : string;
  attribute LC_PROBE223_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE223_MU_CNT : integer;
  attribute LC_PROBE223_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE223_PID : string;
  attribute LC_PROBE223_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011011111";
  attribute LC_PROBE223_TYPE : integer;
  attribute LC_PROBE223_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE223_WIDTH : integer;
  attribute LC_PROBE223_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE224_IS_DATA : string;
  attribute LC_PROBE224_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE224_IS_TRIG : string;
  attribute LC_PROBE224_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE224_MU_CNT : integer;
  attribute LC_PROBE224_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE224_PID : string;
  attribute LC_PROBE224_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100000";
  attribute LC_PROBE224_TYPE : integer;
  attribute LC_PROBE224_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE224_WIDTH : integer;
  attribute LC_PROBE224_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE225_IS_DATA : string;
  attribute LC_PROBE225_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE225_IS_TRIG : string;
  attribute LC_PROBE225_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE225_MU_CNT : integer;
  attribute LC_PROBE225_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE225_PID : string;
  attribute LC_PROBE225_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100001";
  attribute LC_PROBE225_TYPE : integer;
  attribute LC_PROBE225_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE225_WIDTH : integer;
  attribute LC_PROBE225_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE226_IS_DATA : string;
  attribute LC_PROBE226_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE226_IS_TRIG : string;
  attribute LC_PROBE226_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE226_MU_CNT : integer;
  attribute LC_PROBE226_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE226_PID : string;
  attribute LC_PROBE226_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100010";
  attribute LC_PROBE226_TYPE : integer;
  attribute LC_PROBE226_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE226_WIDTH : integer;
  attribute LC_PROBE226_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE227_IS_DATA : string;
  attribute LC_PROBE227_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE227_IS_TRIG : string;
  attribute LC_PROBE227_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE227_MU_CNT : integer;
  attribute LC_PROBE227_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE227_PID : string;
  attribute LC_PROBE227_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100011";
  attribute LC_PROBE227_TYPE : integer;
  attribute LC_PROBE227_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE227_WIDTH : integer;
  attribute LC_PROBE227_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE228_IS_DATA : string;
  attribute LC_PROBE228_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE228_IS_TRIG : string;
  attribute LC_PROBE228_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE228_MU_CNT : integer;
  attribute LC_PROBE228_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE228_PID : string;
  attribute LC_PROBE228_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100100";
  attribute LC_PROBE228_TYPE : integer;
  attribute LC_PROBE228_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE228_WIDTH : integer;
  attribute LC_PROBE228_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE229_IS_DATA : string;
  attribute LC_PROBE229_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE229_IS_TRIG : string;
  attribute LC_PROBE229_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE229_MU_CNT : integer;
  attribute LC_PROBE229_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE229_PID : string;
  attribute LC_PROBE229_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100101";
  attribute LC_PROBE229_TYPE : integer;
  attribute LC_PROBE229_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE229_WIDTH : integer;
  attribute LC_PROBE229_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE22_IS_DATA : string;
  attribute LC_PROBE22_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE22_IS_TRIG : string;
  attribute LC_PROBE22_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE22_MU_CNT : integer;
  attribute LC_PROBE22_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE22_PID : string;
  attribute LC_PROBE22_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010110";
  attribute LC_PROBE22_TYPE : integer;
  attribute LC_PROBE22_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE22_WIDTH : integer;
  attribute LC_PROBE22_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE230_IS_DATA : string;
  attribute LC_PROBE230_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE230_IS_TRIG : string;
  attribute LC_PROBE230_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE230_MU_CNT : integer;
  attribute LC_PROBE230_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE230_PID : string;
  attribute LC_PROBE230_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100110";
  attribute LC_PROBE230_TYPE : integer;
  attribute LC_PROBE230_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE230_WIDTH : integer;
  attribute LC_PROBE230_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE231_IS_DATA : string;
  attribute LC_PROBE231_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE231_IS_TRIG : string;
  attribute LC_PROBE231_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE231_MU_CNT : integer;
  attribute LC_PROBE231_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE231_PID : string;
  attribute LC_PROBE231_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011100111";
  attribute LC_PROBE231_TYPE : integer;
  attribute LC_PROBE231_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE231_WIDTH : integer;
  attribute LC_PROBE231_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE232_IS_DATA : string;
  attribute LC_PROBE232_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE232_IS_TRIG : string;
  attribute LC_PROBE232_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE232_MU_CNT : integer;
  attribute LC_PROBE232_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE232_PID : string;
  attribute LC_PROBE232_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101000";
  attribute LC_PROBE232_TYPE : integer;
  attribute LC_PROBE232_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE232_WIDTH : integer;
  attribute LC_PROBE232_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE233_IS_DATA : string;
  attribute LC_PROBE233_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE233_IS_TRIG : string;
  attribute LC_PROBE233_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE233_MU_CNT : integer;
  attribute LC_PROBE233_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE233_PID : string;
  attribute LC_PROBE233_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101001";
  attribute LC_PROBE233_TYPE : integer;
  attribute LC_PROBE233_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE233_WIDTH : integer;
  attribute LC_PROBE233_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE234_IS_DATA : string;
  attribute LC_PROBE234_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE234_IS_TRIG : string;
  attribute LC_PROBE234_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE234_MU_CNT : integer;
  attribute LC_PROBE234_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE234_PID : string;
  attribute LC_PROBE234_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101010";
  attribute LC_PROBE234_TYPE : integer;
  attribute LC_PROBE234_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE234_WIDTH : integer;
  attribute LC_PROBE234_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE235_IS_DATA : string;
  attribute LC_PROBE235_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE235_IS_TRIG : string;
  attribute LC_PROBE235_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE235_MU_CNT : integer;
  attribute LC_PROBE235_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE235_PID : string;
  attribute LC_PROBE235_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101011";
  attribute LC_PROBE235_TYPE : integer;
  attribute LC_PROBE235_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE235_WIDTH : integer;
  attribute LC_PROBE235_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE236_IS_DATA : string;
  attribute LC_PROBE236_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE236_IS_TRIG : string;
  attribute LC_PROBE236_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE236_MU_CNT : integer;
  attribute LC_PROBE236_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE236_PID : string;
  attribute LC_PROBE236_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101100";
  attribute LC_PROBE236_TYPE : integer;
  attribute LC_PROBE236_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE236_WIDTH : integer;
  attribute LC_PROBE236_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE237_IS_DATA : string;
  attribute LC_PROBE237_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE237_IS_TRIG : string;
  attribute LC_PROBE237_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE237_MU_CNT : integer;
  attribute LC_PROBE237_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE237_PID : string;
  attribute LC_PROBE237_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101101";
  attribute LC_PROBE237_TYPE : integer;
  attribute LC_PROBE237_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE237_WIDTH : integer;
  attribute LC_PROBE237_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE238_IS_DATA : string;
  attribute LC_PROBE238_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE238_IS_TRIG : string;
  attribute LC_PROBE238_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE238_MU_CNT : integer;
  attribute LC_PROBE238_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE238_PID : string;
  attribute LC_PROBE238_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101110";
  attribute LC_PROBE238_TYPE : integer;
  attribute LC_PROBE238_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE238_WIDTH : integer;
  attribute LC_PROBE238_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE239_IS_DATA : string;
  attribute LC_PROBE239_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE239_IS_TRIG : string;
  attribute LC_PROBE239_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE239_MU_CNT : integer;
  attribute LC_PROBE239_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE239_PID : string;
  attribute LC_PROBE239_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011101111";
  attribute LC_PROBE239_TYPE : integer;
  attribute LC_PROBE239_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE239_WIDTH : integer;
  attribute LC_PROBE239_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE23_IS_DATA : string;
  attribute LC_PROBE23_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE23_IS_TRIG : string;
  attribute LC_PROBE23_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE23_MU_CNT : integer;
  attribute LC_PROBE23_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE23_PID : string;
  attribute LC_PROBE23_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000010111";
  attribute LC_PROBE23_TYPE : integer;
  attribute LC_PROBE23_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE23_WIDTH : integer;
  attribute LC_PROBE23_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE240_IS_DATA : string;
  attribute LC_PROBE240_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE240_IS_TRIG : string;
  attribute LC_PROBE240_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE240_MU_CNT : integer;
  attribute LC_PROBE240_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE240_PID : string;
  attribute LC_PROBE240_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110000";
  attribute LC_PROBE240_TYPE : integer;
  attribute LC_PROBE240_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE240_WIDTH : integer;
  attribute LC_PROBE240_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE241_IS_DATA : string;
  attribute LC_PROBE241_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE241_IS_TRIG : string;
  attribute LC_PROBE241_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE241_MU_CNT : integer;
  attribute LC_PROBE241_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE241_PID : string;
  attribute LC_PROBE241_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110001";
  attribute LC_PROBE241_TYPE : integer;
  attribute LC_PROBE241_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE241_WIDTH : integer;
  attribute LC_PROBE241_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE242_IS_DATA : string;
  attribute LC_PROBE242_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE242_IS_TRIG : string;
  attribute LC_PROBE242_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE242_MU_CNT : integer;
  attribute LC_PROBE242_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE242_PID : string;
  attribute LC_PROBE242_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110010";
  attribute LC_PROBE242_TYPE : integer;
  attribute LC_PROBE242_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE242_WIDTH : integer;
  attribute LC_PROBE242_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE243_IS_DATA : string;
  attribute LC_PROBE243_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE243_IS_TRIG : string;
  attribute LC_PROBE243_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE243_MU_CNT : integer;
  attribute LC_PROBE243_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE243_PID : string;
  attribute LC_PROBE243_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110011";
  attribute LC_PROBE243_TYPE : integer;
  attribute LC_PROBE243_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE243_WIDTH : integer;
  attribute LC_PROBE243_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE244_IS_DATA : string;
  attribute LC_PROBE244_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE244_IS_TRIG : string;
  attribute LC_PROBE244_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE244_MU_CNT : integer;
  attribute LC_PROBE244_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE244_PID : string;
  attribute LC_PROBE244_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110100";
  attribute LC_PROBE244_TYPE : integer;
  attribute LC_PROBE244_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE244_WIDTH : integer;
  attribute LC_PROBE244_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE245_IS_DATA : string;
  attribute LC_PROBE245_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE245_IS_TRIG : string;
  attribute LC_PROBE245_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE245_MU_CNT : integer;
  attribute LC_PROBE245_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE245_PID : string;
  attribute LC_PROBE245_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110101";
  attribute LC_PROBE245_TYPE : integer;
  attribute LC_PROBE245_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE245_WIDTH : integer;
  attribute LC_PROBE245_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE246_IS_DATA : string;
  attribute LC_PROBE246_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE246_IS_TRIG : string;
  attribute LC_PROBE246_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE246_MU_CNT : integer;
  attribute LC_PROBE246_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE246_PID : string;
  attribute LC_PROBE246_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110110";
  attribute LC_PROBE246_TYPE : integer;
  attribute LC_PROBE246_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE246_WIDTH : integer;
  attribute LC_PROBE246_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE247_IS_DATA : string;
  attribute LC_PROBE247_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE247_IS_TRIG : string;
  attribute LC_PROBE247_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE247_MU_CNT : integer;
  attribute LC_PROBE247_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE247_PID : string;
  attribute LC_PROBE247_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011110111";
  attribute LC_PROBE247_TYPE : integer;
  attribute LC_PROBE247_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE247_WIDTH : integer;
  attribute LC_PROBE247_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE248_IS_DATA : string;
  attribute LC_PROBE248_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE248_IS_TRIG : string;
  attribute LC_PROBE248_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE248_MU_CNT : integer;
  attribute LC_PROBE248_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE248_PID : string;
  attribute LC_PROBE248_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111000";
  attribute LC_PROBE248_TYPE : integer;
  attribute LC_PROBE248_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE248_WIDTH : integer;
  attribute LC_PROBE248_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE249_IS_DATA : string;
  attribute LC_PROBE249_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE249_IS_TRIG : string;
  attribute LC_PROBE249_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE249_MU_CNT : integer;
  attribute LC_PROBE249_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE249_PID : string;
  attribute LC_PROBE249_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111001";
  attribute LC_PROBE249_TYPE : integer;
  attribute LC_PROBE249_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE249_WIDTH : integer;
  attribute LC_PROBE249_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE24_IS_DATA : string;
  attribute LC_PROBE24_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE24_IS_TRIG : string;
  attribute LC_PROBE24_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE24_MU_CNT : integer;
  attribute LC_PROBE24_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE24_PID : string;
  attribute LC_PROBE24_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011000";
  attribute LC_PROBE24_TYPE : integer;
  attribute LC_PROBE24_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE24_WIDTH : integer;
  attribute LC_PROBE24_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE250_IS_DATA : string;
  attribute LC_PROBE250_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE250_IS_TRIG : string;
  attribute LC_PROBE250_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE250_MU_CNT : integer;
  attribute LC_PROBE250_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE250_PID : string;
  attribute LC_PROBE250_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111010";
  attribute LC_PROBE250_TYPE : integer;
  attribute LC_PROBE250_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE250_WIDTH : integer;
  attribute LC_PROBE250_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE251_IS_DATA : string;
  attribute LC_PROBE251_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE251_IS_TRIG : string;
  attribute LC_PROBE251_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE251_MU_CNT : integer;
  attribute LC_PROBE251_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE251_PID : string;
  attribute LC_PROBE251_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111011";
  attribute LC_PROBE251_TYPE : integer;
  attribute LC_PROBE251_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE251_WIDTH : integer;
  attribute LC_PROBE251_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE252_IS_DATA : string;
  attribute LC_PROBE252_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE252_IS_TRIG : string;
  attribute LC_PROBE252_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE252_MU_CNT : integer;
  attribute LC_PROBE252_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE252_PID : string;
  attribute LC_PROBE252_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111100";
  attribute LC_PROBE252_TYPE : integer;
  attribute LC_PROBE252_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE252_WIDTH : integer;
  attribute LC_PROBE252_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE253_IS_DATA : string;
  attribute LC_PROBE253_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE253_IS_TRIG : string;
  attribute LC_PROBE253_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE253_MU_CNT : integer;
  attribute LC_PROBE253_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE253_PID : string;
  attribute LC_PROBE253_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111101";
  attribute LC_PROBE253_TYPE : integer;
  attribute LC_PROBE253_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE253_WIDTH : integer;
  attribute LC_PROBE253_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE254_IS_DATA : string;
  attribute LC_PROBE254_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE254_IS_TRIG : string;
  attribute LC_PROBE254_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE254_MU_CNT : integer;
  attribute LC_PROBE254_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE254_PID : string;
  attribute LC_PROBE254_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111110";
  attribute LC_PROBE254_TYPE : integer;
  attribute LC_PROBE254_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE254_WIDTH : integer;
  attribute LC_PROBE254_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE255_IS_DATA : string;
  attribute LC_PROBE255_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE255_IS_TRIG : string;
  attribute LC_PROBE255_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE255_MU_CNT : integer;
  attribute LC_PROBE255_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE255_PID : string;
  attribute LC_PROBE255_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000011111111";
  attribute LC_PROBE255_TYPE : integer;
  attribute LC_PROBE255_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE255_WIDTH : integer;
  attribute LC_PROBE255_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE256_IS_DATA : string;
  attribute LC_PROBE256_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE256_IS_TRIG : string;
  attribute LC_PROBE256_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE256_MU_CNT : integer;
  attribute LC_PROBE256_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE256_PID : string;
  attribute LC_PROBE256_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000000";
  attribute LC_PROBE256_TYPE : integer;
  attribute LC_PROBE256_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE256_WIDTH : integer;
  attribute LC_PROBE256_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE257_IS_DATA : string;
  attribute LC_PROBE257_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE257_IS_TRIG : string;
  attribute LC_PROBE257_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE257_MU_CNT : integer;
  attribute LC_PROBE257_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE257_PID : string;
  attribute LC_PROBE257_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000001";
  attribute LC_PROBE257_TYPE : integer;
  attribute LC_PROBE257_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE257_WIDTH : integer;
  attribute LC_PROBE257_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE258_IS_DATA : string;
  attribute LC_PROBE258_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE258_IS_TRIG : string;
  attribute LC_PROBE258_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE258_MU_CNT : integer;
  attribute LC_PROBE258_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE258_PID : string;
  attribute LC_PROBE258_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000010";
  attribute LC_PROBE258_TYPE : integer;
  attribute LC_PROBE258_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE258_WIDTH : integer;
  attribute LC_PROBE258_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE259_IS_DATA : string;
  attribute LC_PROBE259_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE259_IS_TRIG : string;
  attribute LC_PROBE259_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE259_MU_CNT : integer;
  attribute LC_PROBE259_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE259_PID : string;
  attribute LC_PROBE259_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000011";
  attribute LC_PROBE259_TYPE : integer;
  attribute LC_PROBE259_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE259_WIDTH : integer;
  attribute LC_PROBE259_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE25_IS_DATA : string;
  attribute LC_PROBE25_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE25_IS_TRIG : string;
  attribute LC_PROBE25_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE25_MU_CNT : integer;
  attribute LC_PROBE25_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE25_PID : string;
  attribute LC_PROBE25_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011001";
  attribute LC_PROBE25_TYPE : integer;
  attribute LC_PROBE25_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE25_WIDTH : integer;
  attribute LC_PROBE25_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE260_IS_DATA : string;
  attribute LC_PROBE260_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE260_IS_TRIG : string;
  attribute LC_PROBE260_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE260_MU_CNT : integer;
  attribute LC_PROBE260_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE260_PID : string;
  attribute LC_PROBE260_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000100";
  attribute LC_PROBE260_TYPE : integer;
  attribute LC_PROBE260_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE260_WIDTH : integer;
  attribute LC_PROBE260_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE261_IS_DATA : string;
  attribute LC_PROBE261_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE261_IS_TRIG : string;
  attribute LC_PROBE261_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE261_MU_CNT : integer;
  attribute LC_PROBE261_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE261_PID : string;
  attribute LC_PROBE261_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000101";
  attribute LC_PROBE261_TYPE : integer;
  attribute LC_PROBE261_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE261_WIDTH : integer;
  attribute LC_PROBE261_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE262_IS_DATA : string;
  attribute LC_PROBE262_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE262_IS_TRIG : string;
  attribute LC_PROBE262_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE262_MU_CNT : integer;
  attribute LC_PROBE262_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE262_PID : string;
  attribute LC_PROBE262_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000110";
  attribute LC_PROBE262_TYPE : integer;
  attribute LC_PROBE262_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE262_WIDTH : integer;
  attribute LC_PROBE262_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE263_IS_DATA : string;
  attribute LC_PROBE263_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE263_IS_TRIG : string;
  attribute LC_PROBE263_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE263_MU_CNT : integer;
  attribute LC_PROBE263_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE263_PID : string;
  attribute LC_PROBE263_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100000111";
  attribute LC_PROBE263_TYPE : integer;
  attribute LC_PROBE263_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE263_WIDTH : integer;
  attribute LC_PROBE263_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE264_IS_DATA : string;
  attribute LC_PROBE264_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE264_IS_TRIG : string;
  attribute LC_PROBE264_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE264_MU_CNT : integer;
  attribute LC_PROBE264_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE264_PID : string;
  attribute LC_PROBE264_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001000";
  attribute LC_PROBE264_TYPE : integer;
  attribute LC_PROBE264_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE264_WIDTH : integer;
  attribute LC_PROBE264_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE265_IS_DATA : string;
  attribute LC_PROBE265_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE265_IS_TRIG : string;
  attribute LC_PROBE265_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE265_MU_CNT : integer;
  attribute LC_PROBE265_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE265_PID : string;
  attribute LC_PROBE265_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001001";
  attribute LC_PROBE265_TYPE : integer;
  attribute LC_PROBE265_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE265_WIDTH : integer;
  attribute LC_PROBE265_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE266_IS_DATA : string;
  attribute LC_PROBE266_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE266_IS_TRIG : string;
  attribute LC_PROBE266_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE266_MU_CNT : integer;
  attribute LC_PROBE266_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE266_PID : string;
  attribute LC_PROBE266_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001010";
  attribute LC_PROBE266_TYPE : integer;
  attribute LC_PROBE266_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE266_WIDTH : integer;
  attribute LC_PROBE266_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE267_IS_DATA : string;
  attribute LC_PROBE267_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE267_IS_TRIG : string;
  attribute LC_PROBE267_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE267_MU_CNT : integer;
  attribute LC_PROBE267_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE267_PID : string;
  attribute LC_PROBE267_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001011";
  attribute LC_PROBE267_TYPE : integer;
  attribute LC_PROBE267_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE267_WIDTH : integer;
  attribute LC_PROBE267_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE268_IS_DATA : string;
  attribute LC_PROBE268_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE268_IS_TRIG : string;
  attribute LC_PROBE268_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE268_MU_CNT : integer;
  attribute LC_PROBE268_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE268_PID : string;
  attribute LC_PROBE268_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001100";
  attribute LC_PROBE268_TYPE : integer;
  attribute LC_PROBE268_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE268_WIDTH : integer;
  attribute LC_PROBE268_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE269_IS_DATA : string;
  attribute LC_PROBE269_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE269_IS_TRIG : string;
  attribute LC_PROBE269_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE269_MU_CNT : integer;
  attribute LC_PROBE269_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE269_PID : string;
  attribute LC_PROBE269_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001101";
  attribute LC_PROBE269_TYPE : integer;
  attribute LC_PROBE269_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE269_WIDTH : integer;
  attribute LC_PROBE269_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE26_IS_DATA : string;
  attribute LC_PROBE26_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE26_IS_TRIG : string;
  attribute LC_PROBE26_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE26_MU_CNT : integer;
  attribute LC_PROBE26_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE26_PID : string;
  attribute LC_PROBE26_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011010";
  attribute LC_PROBE26_TYPE : integer;
  attribute LC_PROBE26_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE26_WIDTH : integer;
  attribute LC_PROBE26_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE270_IS_DATA : string;
  attribute LC_PROBE270_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE270_IS_TRIG : string;
  attribute LC_PROBE270_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE270_MU_CNT : integer;
  attribute LC_PROBE270_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE270_PID : string;
  attribute LC_PROBE270_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001110";
  attribute LC_PROBE270_TYPE : integer;
  attribute LC_PROBE270_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE270_WIDTH : integer;
  attribute LC_PROBE270_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE271_IS_DATA : string;
  attribute LC_PROBE271_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE271_IS_TRIG : string;
  attribute LC_PROBE271_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE271_MU_CNT : integer;
  attribute LC_PROBE271_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE271_PID : string;
  attribute LC_PROBE271_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100001111";
  attribute LC_PROBE271_TYPE : integer;
  attribute LC_PROBE271_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE271_WIDTH : integer;
  attribute LC_PROBE271_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE272_IS_DATA : string;
  attribute LC_PROBE272_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE272_IS_TRIG : string;
  attribute LC_PROBE272_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE272_MU_CNT : integer;
  attribute LC_PROBE272_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE272_PID : string;
  attribute LC_PROBE272_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010000";
  attribute LC_PROBE272_TYPE : integer;
  attribute LC_PROBE272_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE272_WIDTH : integer;
  attribute LC_PROBE272_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE273_IS_DATA : string;
  attribute LC_PROBE273_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE273_IS_TRIG : string;
  attribute LC_PROBE273_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE273_MU_CNT : integer;
  attribute LC_PROBE273_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE273_PID : string;
  attribute LC_PROBE273_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010001";
  attribute LC_PROBE273_TYPE : integer;
  attribute LC_PROBE273_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE273_WIDTH : integer;
  attribute LC_PROBE273_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE274_IS_DATA : string;
  attribute LC_PROBE274_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE274_IS_TRIG : string;
  attribute LC_PROBE274_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE274_MU_CNT : integer;
  attribute LC_PROBE274_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE274_PID : string;
  attribute LC_PROBE274_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010010";
  attribute LC_PROBE274_TYPE : integer;
  attribute LC_PROBE274_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE274_WIDTH : integer;
  attribute LC_PROBE274_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE275_IS_DATA : string;
  attribute LC_PROBE275_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE275_IS_TRIG : string;
  attribute LC_PROBE275_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE275_MU_CNT : integer;
  attribute LC_PROBE275_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE275_PID : string;
  attribute LC_PROBE275_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010011";
  attribute LC_PROBE275_TYPE : integer;
  attribute LC_PROBE275_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE275_WIDTH : integer;
  attribute LC_PROBE275_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE276_IS_DATA : string;
  attribute LC_PROBE276_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE276_IS_TRIG : string;
  attribute LC_PROBE276_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE276_MU_CNT : integer;
  attribute LC_PROBE276_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE276_PID : string;
  attribute LC_PROBE276_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010100";
  attribute LC_PROBE276_TYPE : integer;
  attribute LC_PROBE276_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE276_WIDTH : integer;
  attribute LC_PROBE276_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE277_IS_DATA : string;
  attribute LC_PROBE277_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE277_IS_TRIG : string;
  attribute LC_PROBE277_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE277_MU_CNT : integer;
  attribute LC_PROBE277_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE277_PID : string;
  attribute LC_PROBE277_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010101";
  attribute LC_PROBE277_TYPE : integer;
  attribute LC_PROBE277_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE277_WIDTH : integer;
  attribute LC_PROBE277_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE278_IS_DATA : string;
  attribute LC_PROBE278_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE278_IS_TRIG : string;
  attribute LC_PROBE278_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE278_MU_CNT : integer;
  attribute LC_PROBE278_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE278_PID : string;
  attribute LC_PROBE278_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010110";
  attribute LC_PROBE278_TYPE : integer;
  attribute LC_PROBE278_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE278_WIDTH : integer;
  attribute LC_PROBE278_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE279_IS_DATA : string;
  attribute LC_PROBE279_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE279_IS_TRIG : string;
  attribute LC_PROBE279_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE279_MU_CNT : integer;
  attribute LC_PROBE279_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE279_PID : string;
  attribute LC_PROBE279_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100010111";
  attribute LC_PROBE279_TYPE : integer;
  attribute LC_PROBE279_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE279_WIDTH : integer;
  attribute LC_PROBE279_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE27_IS_DATA : string;
  attribute LC_PROBE27_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE27_IS_TRIG : string;
  attribute LC_PROBE27_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE27_MU_CNT : integer;
  attribute LC_PROBE27_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE27_PID : string;
  attribute LC_PROBE27_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011011";
  attribute LC_PROBE27_TYPE : integer;
  attribute LC_PROBE27_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE27_WIDTH : integer;
  attribute LC_PROBE27_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE280_IS_DATA : string;
  attribute LC_PROBE280_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE280_IS_TRIG : string;
  attribute LC_PROBE280_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE280_MU_CNT : integer;
  attribute LC_PROBE280_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE280_PID : string;
  attribute LC_PROBE280_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011000";
  attribute LC_PROBE280_TYPE : integer;
  attribute LC_PROBE280_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE280_WIDTH : integer;
  attribute LC_PROBE280_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE281_IS_DATA : string;
  attribute LC_PROBE281_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE281_IS_TRIG : string;
  attribute LC_PROBE281_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE281_MU_CNT : integer;
  attribute LC_PROBE281_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE281_PID : string;
  attribute LC_PROBE281_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011001";
  attribute LC_PROBE281_TYPE : integer;
  attribute LC_PROBE281_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE281_WIDTH : integer;
  attribute LC_PROBE281_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE282_IS_DATA : string;
  attribute LC_PROBE282_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE282_IS_TRIG : string;
  attribute LC_PROBE282_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE282_MU_CNT : integer;
  attribute LC_PROBE282_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE282_PID : string;
  attribute LC_PROBE282_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011010";
  attribute LC_PROBE282_TYPE : integer;
  attribute LC_PROBE282_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE282_WIDTH : integer;
  attribute LC_PROBE282_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE283_IS_DATA : string;
  attribute LC_PROBE283_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE283_IS_TRIG : string;
  attribute LC_PROBE283_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE283_MU_CNT : integer;
  attribute LC_PROBE283_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE283_PID : string;
  attribute LC_PROBE283_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011011";
  attribute LC_PROBE283_TYPE : integer;
  attribute LC_PROBE283_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE283_WIDTH : integer;
  attribute LC_PROBE283_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE284_IS_DATA : string;
  attribute LC_PROBE284_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE284_IS_TRIG : string;
  attribute LC_PROBE284_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE284_MU_CNT : integer;
  attribute LC_PROBE284_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE284_PID : string;
  attribute LC_PROBE284_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011100";
  attribute LC_PROBE284_TYPE : integer;
  attribute LC_PROBE284_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE284_WIDTH : integer;
  attribute LC_PROBE284_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE285_IS_DATA : string;
  attribute LC_PROBE285_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE285_IS_TRIG : string;
  attribute LC_PROBE285_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE285_MU_CNT : integer;
  attribute LC_PROBE285_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE285_PID : string;
  attribute LC_PROBE285_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011101";
  attribute LC_PROBE285_TYPE : integer;
  attribute LC_PROBE285_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE285_WIDTH : integer;
  attribute LC_PROBE285_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE286_IS_DATA : string;
  attribute LC_PROBE286_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE286_IS_TRIG : string;
  attribute LC_PROBE286_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE286_MU_CNT : integer;
  attribute LC_PROBE286_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE286_PID : string;
  attribute LC_PROBE286_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011110";
  attribute LC_PROBE286_TYPE : integer;
  attribute LC_PROBE286_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE286_WIDTH : integer;
  attribute LC_PROBE286_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE287_IS_DATA : string;
  attribute LC_PROBE287_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE287_IS_TRIG : string;
  attribute LC_PROBE287_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE287_MU_CNT : integer;
  attribute LC_PROBE287_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE287_PID : string;
  attribute LC_PROBE287_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100011111";
  attribute LC_PROBE287_TYPE : integer;
  attribute LC_PROBE287_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE287_WIDTH : integer;
  attribute LC_PROBE287_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE288_IS_DATA : string;
  attribute LC_PROBE288_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE288_IS_TRIG : string;
  attribute LC_PROBE288_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE288_MU_CNT : integer;
  attribute LC_PROBE288_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE288_PID : string;
  attribute LC_PROBE288_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100000";
  attribute LC_PROBE288_TYPE : integer;
  attribute LC_PROBE288_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE288_WIDTH : integer;
  attribute LC_PROBE288_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE289_IS_DATA : string;
  attribute LC_PROBE289_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE289_IS_TRIG : string;
  attribute LC_PROBE289_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE289_MU_CNT : integer;
  attribute LC_PROBE289_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE289_PID : string;
  attribute LC_PROBE289_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100001";
  attribute LC_PROBE289_TYPE : integer;
  attribute LC_PROBE289_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE289_WIDTH : integer;
  attribute LC_PROBE289_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE28_IS_DATA : string;
  attribute LC_PROBE28_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE28_IS_TRIG : string;
  attribute LC_PROBE28_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE28_MU_CNT : integer;
  attribute LC_PROBE28_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE28_PID : string;
  attribute LC_PROBE28_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011100";
  attribute LC_PROBE28_TYPE : integer;
  attribute LC_PROBE28_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE28_WIDTH : integer;
  attribute LC_PROBE28_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE290_IS_DATA : string;
  attribute LC_PROBE290_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE290_IS_TRIG : string;
  attribute LC_PROBE290_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE290_MU_CNT : integer;
  attribute LC_PROBE290_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE290_PID : string;
  attribute LC_PROBE290_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100010";
  attribute LC_PROBE290_TYPE : integer;
  attribute LC_PROBE290_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE290_WIDTH : integer;
  attribute LC_PROBE290_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE291_IS_DATA : string;
  attribute LC_PROBE291_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE291_IS_TRIG : string;
  attribute LC_PROBE291_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE291_MU_CNT : integer;
  attribute LC_PROBE291_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE291_PID : string;
  attribute LC_PROBE291_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100011";
  attribute LC_PROBE291_TYPE : integer;
  attribute LC_PROBE291_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE291_WIDTH : integer;
  attribute LC_PROBE291_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE292_IS_DATA : string;
  attribute LC_PROBE292_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE292_IS_TRIG : string;
  attribute LC_PROBE292_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE292_MU_CNT : integer;
  attribute LC_PROBE292_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE292_PID : string;
  attribute LC_PROBE292_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100100";
  attribute LC_PROBE292_TYPE : integer;
  attribute LC_PROBE292_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE292_WIDTH : integer;
  attribute LC_PROBE292_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE293_IS_DATA : string;
  attribute LC_PROBE293_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE293_IS_TRIG : string;
  attribute LC_PROBE293_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE293_MU_CNT : integer;
  attribute LC_PROBE293_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE293_PID : string;
  attribute LC_PROBE293_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100101";
  attribute LC_PROBE293_TYPE : integer;
  attribute LC_PROBE293_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE293_WIDTH : integer;
  attribute LC_PROBE293_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE294_IS_DATA : string;
  attribute LC_PROBE294_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE294_IS_TRIG : string;
  attribute LC_PROBE294_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE294_MU_CNT : integer;
  attribute LC_PROBE294_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE294_PID : string;
  attribute LC_PROBE294_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100110";
  attribute LC_PROBE294_TYPE : integer;
  attribute LC_PROBE294_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE294_WIDTH : integer;
  attribute LC_PROBE294_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE295_IS_DATA : string;
  attribute LC_PROBE295_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE295_IS_TRIG : string;
  attribute LC_PROBE295_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE295_MU_CNT : integer;
  attribute LC_PROBE295_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE295_PID : string;
  attribute LC_PROBE295_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100100111";
  attribute LC_PROBE295_TYPE : integer;
  attribute LC_PROBE295_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE295_WIDTH : integer;
  attribute LC_PROBE295_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE296_IS_DATA : string;
  attribute LC_PROBE296_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE296_IS_TRIG : string;
  attribute LC_PROBE296_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE296_MU_CNT : integer;
  attribute LC_PROBE296_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE296_PID : string;
  attribute LC_PROBE296_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101000";
  attribute LC_PROBE296_TYPE : integer;
  attribute LC_PROBE296_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE296_WIDTH : integer;
  attribute LC_PROBE296_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE297_IS_DATA : string;
  attribute LC_PROBE297_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE297_IS_TRIG : string;
  attribute LC_PROBE297_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE297_MU_CNT : integer;
  attribute LC_PROBE297_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE297_PID : string;
  attribute LC_PROBE297_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101001";
  attribute LC_PROBE297_TYPE : integer;
  attribute LC_PROBE297_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE297_WIDTH : integer;
  attribute LC_PROBE297_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE298_IS_DATA : string;
  attribute LC_PROBE298_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE298_IS_TRIG : string;
  attribute LC_PROBE298_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE298_MU_CNT : integer;
  attribute LC_PROBE298_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE298_PID : string;
  attribute LC_PROBE298_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101010";
  attribute LC_PROBE298_TYPE : integer;
  attribute LC_PROBE298_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE298_WIDTH : integer;
  attribute LC_PROBE298_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE299_IS_DATA : string;
  attribute LC_PROBE299_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE299_IS_TRIG : string;
  attribute LC_PROBE299_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE299_MU_CNT : integer;
  attribute LC_PROBE299_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE299_PID : string;
  attribute LC_PROBE299_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101011";
  attribute LC_PROBE299_TYPE : integer;
  attribute LC_PROBE299_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE299_WIDTH : integer;
  attribute LC_PROBE299_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE29_IS_DATA : string;
  attribute LC_PROBE29_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE29_IS_TRIG : string;
  attribute LC_PROBE29_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE29_MU_CNT : integer;
  attribute LC_PROBE29_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE29_PID : string;
  attribute LC_PROBE29_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011101";
  attribute LC_PROBE29_TYPE : integer;
  attribute LC_PROBE29_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE29_WIDTH : integer;
  attribute LC_PROBE29_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE2_IS_DATA : string;
  attribute LC_PROBE2_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE2_IS_TRIG : string;
  attribute LC_PROBE2_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE2_MU_CNT : integer;
  attribute LC_PROBE2_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE2_PID : string;
  attribute LC_PROBE2_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000010";
  attribute LC_PROBE2_TYPE : integer;
  attribute LC_PROBE2_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE2_WIDTH : integer;
  attribute LC_PROBE2_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE300_IS_DATA : string;
  attribute LC_PROBE300_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE300_IS_TRIG : string;
  attribute LC_PROBE300_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE300_MU_CNT : integer;
  attribute LC_PROBE300_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE300_PID : string;
  attribute LC_PROBE300_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101100";
  attribute LC_PROBE300_TYPE : integer;
  attribute LC_PROBE300_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE300_WIDTH : integer;
  attribute LC_PROBE300_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE301_IS_DATA : string;
  attribute LC_PROBE301_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE301_IS_TRIG : string;
  attribute LC_PROBE301_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE301_MU_CNT : integer;
  attribute LC_PROBE301_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE301_PID : string;
  attribute LC_PROBE301_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101101";
  attribute LC_PROBE301_TYPE : integer;
  attribute LC_PROBE301_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE301_WIDTH : integer;
  attribute LC_PROBE301_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE302_IS_DATA : string;
  attribute LC_PROBE302_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE302_IS_TRIG : string;
  attribute LC_PROBE302_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE302_MU_CNT : integer;
  attribute LC_PROBE302_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE302_PID : string;
  attribute LC_PROBE302_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101110";
  attribute LC_PROBE302_TYPE : integer;
  attribute LC_PROBE302_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE302_WIDTH : integer;
  attribute LC_PROBE302_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE303_IS_DATA : string;
  attribute LC_PROBE303_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE303_IS_TRIG : string;
  attribute LC_PROBE303_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE303_MU_CNT : integer;
  attribute LC_PROBE303_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE303_PID : string;
  attribute LC_PROBE303_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100101111";
  attribute LC_PROBE303_TYPE : integer;
  attribute LC_PROBE303_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE303_WIDTH : integer;
  attribute LC_PROBE303_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE304_IS_DATA : string;
  attribute LC_PROBE304_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE304_IS_TRIG : string;
  attribute LC_PROBE304_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE304_MU_CNT : integer;
  attribute LC_PROBE304_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE304_PID : string;
  attribute LC_PROBE304_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110000";
  attribute LC_PROBE304_TYPE : integer;
  attribute LC_PROBE304_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE304_WIDTH : integer;
  attribute LC_PROBE304_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE305_IS_DATA : string;
  attribute LC_PROBE305_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE305_IS_TRIG : string;
  attribute LC_PROBE305_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE305_MU_CNT : integer;
  attribute LC_PROBE305_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE305_PID : string;
  attribute LC_PROBE305_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110001";
  attribute LC_PROBE305_TYPE : integer;
  attribute LC_PROBE305_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE305_WIDTH : integer;
  attribute LC_PROBE305_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE306_IS_DATA : string;
  attribute LC_PROBE306_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE306_IS_TRIG : string;
  attribute LC_PROBE306_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE306_MU_CNT : integer;
  attribute LC_PROBE306_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE306_PID : string;
  attribute LC_PROBE306_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110010";
  attribute LC_PROBE306_TYPE : integer;
  attribute LC_PROBE306_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE306_WIDTH : integer;
  attribute LC_PROBE306_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE307_IS_DATA : string;
  attribute LC_PROBE307_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE307_IS_TRIG : string;
  attribute LC_PROBE307_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE307_MU_CNT : integer;
  attribute LC_PROBE307_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE307_PID : string;
  attribute LC_PROBE307_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110011";
  attribute LC_PROBE307_TYPE : integer;
  attribute LC_PROBE307_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE307_WIDTH : integer;
  attribute LC_PROBE307_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE308_IS_DATA : string;
  attribute LC_PROBE308_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE308_IS_TRIG : string;
  attribute LC_PROBE308_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE308_MU_CNT : integer;
  attribute LC_PROBE308_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE308_PID : string;
  attribute LC_PROBE308_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110100";
  attribute LC_PROBE308_TYPE : integer;
  attribute LC_PROBE308_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE308_WIDTH : integer;
  attribute LC_PROBE308_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE309_IS_DATA : string;
  attribute LC_PROBE309_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE309_IS_TRIG : string;
  attribute LC_PROBE309_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE309_MU_CNT : integer;
  attribute LC_PROBE309_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE309_PID : string;
  attribute LC_PROBE309_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110101";
  attribute LC_PROBE309_TYPE : integer;
  attribute LC_PROBE309_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE309_WIDTH : integer;
  attribute LC_PROBE309_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE30_IS_DATA : string;
  attribute LC_PROBE30_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE30_IS_TRIG : string;
  attribute LC_PROBE30_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE30_MU_CNT : integer;
  attribute LC_PROBE30_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE30_PID : string;
  attribute LC_PROBE30_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011110";
  attribute LC_PROBE30_TYPE : integer;
  attribute LC_PROBE30_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE30_WIDTH : integer;
  attribute LC_PROBE30_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE310_IS_DATA : string;
  attribute LC_PROBE310_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE310_IS_TRIG : string;
  attribute LC_PROBE310_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE310_MU_CNT : integer;
  attribute LC_PROBE310_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE310_PID : string;
  attribute LC_PROBE310_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110110";
  attribute LC_PROBE310_TYPE : integer;
  attribute LC_PROBE310_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE310_WIDTH : integer;
  attribute LC_PROBE310_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE311_IS_DATA : string;
  attribute LC_PROBE311_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE311_IS_TRIG : string;
  attribute LC_PROBE311_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE311_MU_CNT : integer;
  attribute LC_PROBE311_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE311_PID : string;
  attribute LC_PROBE311_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100110111";
  attribute LC_PROBE311_TYPE : integer;
  attribute LC_PROBE311_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE311_WIDTH : integer;
  attribute LC_PROBE311_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE312_IS_DATA : string;
  attribute LC_PROBE312_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE312_IS_TRIG : string;
  attribute LC_PROBE312_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE312_MU_CNT : integer;
  attribute LC_PROBE312_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE312_PID : string;
  attribute LC_PROBE312_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111000";
  attribute LC_PROBE312_TYPE : integer;
  attribute LC_PROBE312_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE312_WIDTH : integer;
  attribute LC_PROBE312_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE313_IS_DATA : string;
  attribute LC_PROBE313_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE313_IS_TRIG : string;
  attribute LC_PROBE313_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE313_MU_CNT : integer;
  attribute LC_PROBE313_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE313_PID : string;
  attribute LC_PROBE313_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111001";
  attribute LC_PROBE313_TYPE : integer;
  attribute LC_PROBE313_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE313_WIDTH : integer;
  attribute LC_PROBE313_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE314_IS_DATA : string;
  attribute LC_PROBE314_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE314_IS_TRIG : string;
  attribute LC_PROBE314_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE314_MU_CNT : integer;
  attribute LC_PROBE314_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE314_PID : string;
  attribute LC_PROBE314_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111010";
  attribute LC_PROBE314_TYPE : integer;
  attribute LC_PROBE314_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE314_WIDTH : integer;
  attribute LC_PROBE314_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE315_IS_DATA : string;
  attribute LC_PROBE315_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE315_IS_TRIG : string;
  attribute LC_PROBE315_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE315_MU_CNT : integer;
  attribute LC_PROBE315_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE315_PID : string;
  attribute LC_PROBE315_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111011";
  attribute LC_PROBE315_TYPE : integer;
  attribute LC_PROBE315_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE315_WIDTH : integer;
  attribute LC_PROBE315_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE316_IS_DATA : string;
  attribute LC_PROBE316_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE316_IS_TRIG : string;
  attribute LC_PROBE316_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE316_MU_CNT : integer;
  attribute LC_PROBE316_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE316_PID : string;
  attribute LC_PROBE316_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111100";
  attribute LC_PROBE316_TYPE : integer;
  attribute LC_PROBE316_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE316_WIDTH : integer;
  attribute LC_PROBE316_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE317_IS_DATA : string;
  attribute LC_PROBE317_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE317_IS_TRIG : string;
  attribute LC_PROBE317_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE317_MU_CNT : integer;
  attribute LC_PROBE317_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE317_PID : string;
  attribute LC_PROBE317_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111101";
  attribute LC_PROBE317_TYPE : integer;
  attribute LC_PROBE317_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE317_WIDTH : integer;
  attribute LC_PROBE317_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE318_IS_DATA : string;
  attribute LC_PROBE318_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE318_IS_TRIG : string;
  attribute LC_PROBE318_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE318_MU_CNT : integer;
  attribute LC_PROBE318_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE318_PID : string;
  attribute LC_PROBE318_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111110";
  attribute LC_PROBE318_TYPE : integer;
  attribute LC_PROBE318_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE318_WIDTH : integer;
  attribute LC_PROBE318_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE319_IS_DATA : string;
  attribute LC_PROBE319_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE319_IS_TRIG : string;
  attribute LC_PROBE319_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE319_MU_CNT : integer;
  attribute LC_PROBE319_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE319_PID : string;
  attribute LC_PROBE319_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000100111111";
  attribute LC_PROBE319_TYPE : integer;
  attribute LC_PROBE319_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE319_WIDTH : integer;
  attribute LC_PROBE319_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE31_IS_DATA : string;
  attribute LC_PROBE31_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE31_IS_TRIG : string;
  attribute LC_PROBE31_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE31_MU_CNT : integer;
  attribute LC_PROBE31_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE31_PID : string;
  attribute LC_PROBE31_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000011111";
  attribute LC_PROBE31_TYPE : integer;
  attribute LC_PROBE31_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE31_WIDTH : integer;
  attribute LC_PROBE31_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE320_IS_DATA : string;
  attribute LC_PROBE320_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE320_IS_TRIG : string;
  attribute LC_PROBE320_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE320_MU_CNT : integer;
  attribute LC_PROBE320_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE320_PID : string;
  attribute LC_PROBE320_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000000";
  attribute LC_PROBE320_TYPE : integer;
  attribute LC_PROBE320_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE320_WIDTH : integer;
  attribute LC_PROBE320_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE321_IS_DATA : string;
  attribute LC_PROBE321_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE321_IS_TRIG : string;
  attribute LC_PROBE321_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE321_MU_CNT : integer;
  attribute LC_PROBE321_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE321_PID : string;
  attribute LC_PROBE321_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000001";
  attribute LC_PROBE321_TYPE : integer;
  attribute LC_PROBE321_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE321_WIDTH : integer;
  attribute LC_PROBE321_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE322_IS_DATA : string;
  attribute LC_PROBE322_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE322_IS_TRIG : string;
  attribute LC_PROBE322_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE322_MU_CNT : integer;
  attribute LC_PROBE322_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE322_PID : string;
  attribute LC_PROBE322_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000010";
  attribute LC_PROBE322_TYPE : integer;
  attribute LC_PROBE322_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE322_WIDTH : integer;
  attribute LC_PROBE322_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE323_IS_DATA : string;
  attribute LC_PROBE323_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE323_IS_TRIG : string;
  attribute LC_PROBE323_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE323_MU_CNT : integer;
  attribute LC_PROBE323_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE323_PID : string;
  attribute LC_PROBE323_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000011";
  attribute LC_PROBE323_TYPE : integer;
  attribute LC_PROBE323_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE323_WIDTH : integer;
  attribute LC_PROBE323_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE324_IS_DATA : string;
  attribute LC_PROBE324_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE324_IS_TRIG : string;
  attribute LC_PROBE324_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE324_MU_CNT : integer;
  attribute LC_PROBE324_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE324_PID : string;
  attribute LC_PROBE324_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000100";
  attribute LC_PROBE324_TYPE : integer;
  attribute LC_PROBE324_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE324_WIDTH : integer;
  attribute LC_PROBE324_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE325_IS_DATA : string;
  attribute LC_PROBE325_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE325_IS_TRIG : string;
  attribute LC_PROBE325_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE325_MU_CNT : integer;
  attribute LC_PROBE325_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE325_PID : string;
  attribute LC_PROBE325_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000101";
  attribute LC_PROBE325_TYPE : integer;
  attribute LC_PROBE325_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE325_WIDTH : integer;
  attribute LC_PROBE325_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE326_IS_DATA : string;
  attribute LC_PROBE326_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE326_IS_TRIG : string;
  attribute LC_PROBE326_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE326_MU_CNT : integer;
  attribute LC_PROBE326_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE326_PID : string;
  attribute LC_PROBE326_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000110";
  attribute LC_PROBE326_TYPE : integer;
  attribute LC_PROBE326_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE326_WIDTH : integer;
  attribute LC_PROBE326_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE327_IS_DATA : string;
  attribute LC_PROBE327_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE327_IS_TRIG : string;
  attribute LC_PROBE327_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE327_MU_CNT : integer;
  attribute LC_PROBE327_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE327_PID : string;
  attribute LC_PROBE327_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101000111";
  attribute LC_PROBE327_TYPE : integer;
  attribute LC_PROBE327_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE327_WIDTH : integer;
  attribute LC_PROBE327_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE328_IS_DATA : string;
  attribute LC_PROBE328_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE328_IS_TRIG : string;
  attribute LC_PROBE328_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE328_MU_CNT : integer;
  attribute LC_PROBE328_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE328_PID : string;
  attribute LC_PROBE328_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001000";
  attribute LC_PROBE328_TYPE : integer;
  attribute LC_PROBE328_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE328_WIDTH : integer;
  attribute LC_PROBE328_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE329_IS_DATA : string;
  attribute LC_PROBE329_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE329_IS_TRIG : string;
  attribute LC_PROBE329_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE329_MU_CNT : integer;
  attribute LC_PROBE329_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE329_PID : string;
  attribute LC_PROBE329_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001001";
  attribute LC_PROBE329_TYPE : integer;
  attribute LC_PROBE329_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE329_WIDTH : integer;
  attribute LC_PROBE329_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE32_IS_DATA : string;
  attribute LC_PROBE32_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE32_IS_TRIG : string;
  attribute LC_PROBE32_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE32_MU_CNT : integer;
  attribute LC_PROBE32_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE32_PID : string;
  attribute LC_PROBE32_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100000";
  attribute LC_PROBE32_TYPE : integer;
  attribute LC_PROBE32_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE32_WIDTH : integer;
  attribute LC_PROBE32_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE330_IS_DATA : string;
  attribute LC_PROBE330_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE330_IS_TRIG : string;
  attribute LC_PROBE330_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE330_MU_CNT : integer;
  attribute LC_PROBE330_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE330_PID : string;
  attribute LC_PROBE330_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001010";
  attribute LC_PROBE330_TYPE : integer;
  attribute LC_PROBE330_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE330_WIDTH : integer;
  attribute LC_PROBE330_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE331_IS_DATA : string;
  attribute LC_PROBE331_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE331_IS_TRIG : string;
  attribute LC_PROBE331_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE331_MU_CNT : integer;
  attribute LC_PROBE331_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE331_PID : string;
  attribute LC_PROBE331_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001011";
  attribute LC_PROBE331_TYPE : integer;
  attribute LC_PROBE331_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE331_WIDTH : integer;
  attribute LC_PROBE331_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE332_IS_DATA : string;
  attribute LC_PROBE332_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE332_IS_TRIG : string;
  attribute LC_PROBE332_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE332_MU_CNT : integer;
  attribute LC_PROBE332_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE332_PID : string;
  attribute LC_PROBE332_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001100";
  attribute LC_PROBE332_TYPE : integer;
  attribute LC_PROBE332_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE332_WIDTH : integer;
  attribute LC_PROBE332_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE333_IS_DATA : string;
  attribute LC_PROBE333_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE333_IS_TRIG : string;
  attribute LC_PROBE333_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE333_MU_CNT : integer;
  attribute LC_PROBE333_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE333_PID : string;
  attribute LC_PROBE333_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001101";
  attribute LC_PROBE333_TYPE : integer;
  attribute LC_PROBE333_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE333_WIDTH : integer;
  attribute LC_PROBE333_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE334_IS_DATA : string;
  attribute LC_PROBE334_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE334_IS_TRIG : string;
  attribute LC_PROBE334_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE334_MU_CNT : integer;
  attribute LC_PROBE334_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE334_PID : string;
  attribute LC_PROBE334_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001110";
  attribute LC_PROBE334_TYPE : integer;
  attribute LC_PROBE334_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE334_WIDTH : integer;
  attribute LC_PROBE334_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE335_IS_DATA : string;
  attribute LC_PROBE335_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE335_IS_TRIG : string;
  attribute LC_PROBE335_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE335_MU_CNT : integer;
  attribute LC_PROBE335_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE335_PID : string;
  attribute LC_PROBE335_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101001111";
  attribute LC_PROBE335_TYPE : integer;
  attribute LC_PROBE335_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE335_WIDTH : integer;
  attribute LC_PROBE335_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE336_IS_DATA : string;
  attribute LC_PROBE336_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE336_IS_TRIG : string;
  attribute LC_PROBE336_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE336_MU_CNT : integer;
  attribute LC_PROBE336_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE336_PID : string;
  attribute LC_PROBE336_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010000";
  attribute LC_PROBE336_TYPE : integer;
  attribute LC_PROBE336_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE336_WIDTH : integer;
  attribute LC_PROBE336_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE337_IS_DATA : string;
  attribute LC_PROBE337_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE337_IS_TRIG : string;
  attribute LC_PROBE337_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE337_MU_CNT : integer;
  attribute LC_PROBE337_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE337_PID : string;
  attribute LC_PROBE337_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010001";
  attribute LC_PROBE337_TYPE : integer;
  attribute LC_PROBE337_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE337_WIDTH : integer;
  attribute LC_PROBE337_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE338_IS_DATA : string;
  attribute LC_PROBE338_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE338_IS_TRIG : string;
  attribute LC_PROBE338_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE338_MU_CNT : integer;
  attribute LC_PROBE338_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE338_PID : string;
  attribute LC_PROBE338_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010010";
  attribute LC_PROBE338_TYPE : integer;
  attribute LC_PROBE338_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE338_WIDTH : integer;
  attribute LC_PROBE338_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE339_IS_DATA : string;
  attribute LC_PROBE339_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE339_IS_TRIG : string;
  attribute LC_PROBE339_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE339_MU_CNT : integer;
  attribute LC_PROBE339_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE339_PID : string;
  attribute LC_PROBE339_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010011";
  attribute LC_PROBE339_TYPE : integer;
  attribute LC_PROBE339_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE339_WIDTH : integer;
  attribute LC_PROBE339_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE33_IS_DATA : string;
  attribute LC_PROBE33_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE33_IS_TRIG : string;
  attribute LC_PROBE33_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE33_MU_CNT : integer;
  attribute LC_PROBE33_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE33_PID : string;
  attribute LC_PROBE33_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100001";
  attribute LC_PROBE33_TYPE : integer;
  attribute LC_PROBE33_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE33_WIDTH : integer;
  attribute LC_PROBE33_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE340_IS_DATA : string;
  attribute LC_PROBE340_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE340_IS_TRIG : string;
  attribute LC_PROBE340_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE340_MU_CNT : integer;
  attribute LC_PROBE340_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE340_PID : string;
  attribute LC_PROBE340_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010100";
  attribute LC_PROBE340_TYPE : integer;
  attribute LC_PROBE340_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE340_WIDTH : integer;
  attribute LC_PROBE340_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE341_IS_DATA : string;
  attribute LC_PROBE341_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE341_IS_TRIG : string;
  attribute LC_PROBE341_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE341_MU_CNT : integer;
  attribute LC_PROBE341_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE341_PID : string;
  attribute LC_PROBE341_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010101";
  attribute LC_PROBE341_TYPE : integer;
  attribute LC_PROBE341_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE341_WIDTH : integer;
  attribute LC_PROBE341_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE342_IS_DATA : string;
  attribute LC_PROBE342_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE342_IS_TRIG : string;
  attribute LC_PROBE342_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE342_MU_CNT : integer;
  attribute LC_PROBE342_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE342_PID : string;
  attribute LC_PROBE342_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010110";
  attribute LC_PROBE342_TYPE : integer;
  attribute LC_PROBE342_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE342_WIDTH : integer;
  attribute LC_PROBE342_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE343_IS_DATA : string;
  attribute LC_PROBE343_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE343_IS_TRIG : string;
  attribute LC_PROBE343_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE343_MU_CNT : integer;
  attribute LC_PROBE343_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE343_PID : string;
  attribute LC_PROBE343_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101010111";
  attribute LC_PROBE343_TYPE : integer;
  attribute LC_PROBE343_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE343_WIDTH : integer;
  attribute LC_PROBE343_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE344_IS_DATA : string;
  attribute LC_PROBE344_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE344_IS_TRIG : string;
  attribute LC_PROBE344_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE344_MU_CNT : integer;
  attribute LC_PROBE344_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE344_PID : string;
  attribute LC_PROBE344_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011000";
  attribute LC_PROBE344_TYPE : integer;
  attribute LC_PROBE344_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE344_WIDTH : integer;
  attribute LC_PROBE344_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE345_IS_DATA : string;
  attribute LC_PROBE345_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE345_IS_TRIG : string;
  attribute LC_PROBE345_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE345_MU_CNT : integer;
  attribute LC_PROBE345_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE345_PID : string;
  attribute LC_PROBE345_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011001";
  attribute LC_PROBE345_TYPE : integer;
  attribute LC_PROBE345_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE345_WIDTH : integer;
  attribute LC_PROBE345_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE346_IS_DATA : string;
  attribute LC_PROBE346_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE346_IS_TRIG : string;
  attribute LC_PROBE346_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE346_MU_CNT : integer;
  attribute LC_PROBE346_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE346_PID : string;
  attribute LC_PROBE346_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011010";
  attribute LC_PROBE346_TYPE : integer;
  attribute LC_PROBE346_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE346_WIDTH : integer;
  attribute LC_PROBE346_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE347_IS_DATA : string;
  attribute LC_PROBE347_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE347_IS_TRIG : string;
  attribute LC_PROBE347_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE347_MU_CNT : integer;
  attribute LC_PROBE347_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE347_PID : string;
  attribute LC_PROBE347_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011011";
  attribute LC_PROBE347_TYPE : integer;
  attribute LC_PROBE347_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE347_WIDTH : integer;
  attribute LC_PROBE347_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE348_IS_DATA : string;
  attribute LC_PROBE348_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE348_IS_TRIG : string;
  attribute LC_PROBE348_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE348_MU_CNT : integer;
  attribute LC_PROBE348_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE348_PID : string;
  attribute LC_PROBE348_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011100";
  attribute LC_PROBE348_TYPE : integer;
  attribute LC_PROBE348_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE348_WIDTH : integer;
  attribute LC_PROBE348_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE349_IS_DATA : string;
  attribute LC_PROBE349_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE349_IS_TRIG : string;
  attribute LC_PROBE349_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE349_MU_CNT : integer;
  attribute LC_PROBE349_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE349_PID : string;
  attribute LC_PROBE349_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011101";
  attribute LC_PROBE349_TYPE : integer;
  attribute LC_PROBE349_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE349_WIDTH : integer;
  attribute LC_PROBE349_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE34_IS_DATA : string;
  attribute LC_PROBE34_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE34_IS_TRIG : string;
  attribute LC_PROBE34_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE34_MU_CNT : integer;
  attribute LC_PROBE34_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE34_PID : string;
  attribute LC_PROBE34_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100010";
  attribute LC_PROBE34_TYPE : integer;
  attribute LC_PROBE34_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE34_WIDTH : integer;
  attribute LC_PROBE34_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE350_IS_DATA : string;
  attribute LC_PROBE350_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE350_IS_TRIG : string;
  attribute LC_PROBE350_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE350_MU_CNT : integer;
  attribute LC_PROBE350_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE350_PID : string;
  attribute LC_PROBE350_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011110";
  attribute LC_PROBE350_TYPE : integer;
  attribute LC_PROBE350_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE350_WIDTH : integer;
  attribute LC_PROBE350_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE351_IS_DATA : string;
  attribute LC_PROBE351_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE351_IS_TRIG : string;
  attribute LC_PROBE351_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE351_MU_CNT : integer;
  attribute LC_PROBE351_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE351_PID : string;
  attribute LC_PROBE351_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101011111";
  attribute LC_PROBE351_TYPE : integer;
  attribute LC_PROBE351_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE351_WIDTH : integer;
  attribute LC_PROBE351_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE352_IS_DATA : string;
  attribute LC_PROBE352_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE352_IS_TRIG : string;
  attribute LC_PROBE352_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE352_MU_CNT : integer;
  attribute LC_PROBE352_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE352_PID : string;
  attribute LC_PROBE352_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100000";
  attribute LC_PROBE352_TYPE : integer;
  attribute LC_PROBE352_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE352_WIDTH : integer;
  attribute LC_PROBE352_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE353_IS_DATA : string;
  attribute LC_PROBE353_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE353_IS_TRIG : string;
  attribute LC_PROBE353_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE353_MU_CNT : integer;
  attribute LC_PROBE353_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE353_PID : string;
  attribute LC_PROBE353_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100001";
  attribute LC_PROBE353_TYPE : integer;
  attribute LC_PROBE353_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE353_WIDTH : integer;
  attribute LC_PROBE353_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE354_IS_DATA : string;
  attribute LC_PROBE354_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE354_IS_TRIG : string;
  attribute LC_PROBE354_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE354_MU_CNT : integer;
  attribute LC_PROBE354_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE354_PID : string;
  attribute LC_PROBE354_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100010";
  attribute LC_PROBE354_TYPE : integer;
  attribute LC_PROBE354_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE354_WIDTH : integer;
  attribute LC_PROBE354_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE355_IS_DATA : string;
  attribute LC_PROBE355_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE355_IS_TRIG : string;
  attribute LC_PROBE355_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE355_MU_CNT : integer;
  attribute LC_PROBE355_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE355_PID : string;
  attribute LC_PROBE355_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100011";
  attribute LC_PROBE355_TYPE : integer;
  attribute LC_PROBE355_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE355_WIDTH : integer;
  attribute LC_PROBE355_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE356_IS_DATA : string;
  attribute LC_PROBE356_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE356_IS_TRIG : string;
  attribute LC_PROBE356_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE356_MU_CNT : integer;
  attribute LC_PROBE356_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE356_PID : string;
  attribute LC_PROBE356_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100100";
  attribute LC_PROBE356_TYPE : integer;
  attribute LC_PROBE356_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE356_WIDTH : integer;
  attribute LC_PROBE356_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE357_IS_DATA : string;
  attribute LC_PROBE357_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE357_IS_TRIG : string;
  attribute LC_PROBE357_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE357_MU_CNT : integer;
  attribute LC_PROBE357_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE357_PID : string;
  attribute LC_PROBE357_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100101";
  attribute LC_PROBE357_TYPE : integer;
  attribute LC_PROBE357_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE357_WIDTH : integer;
  attribute LC_PROBE357_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE358_IS_DATA : string;
  attribute LC_PROBE358_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE358_IS_TRIG : string;
  attribute LC_PROBE358_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE358_MU_CNT : integer;
  attribute LC_PROBE358_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE358_PID : string;
  attribute LC_PROBE358_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100110";
  attribute LC_PROBE358_TYPE : integer;
  attribute LC_PROBE358_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE358_WIDTH : integer;
  attribute LC_PROBE358_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE359_IS_DATA : string;
  attribute LC_PROBE359_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE359_IS_TRIG : string;
  attribute LC_PROBE359_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE359_MU_CNT : integer;
  attribute LC_PROBE359_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE359_PID : string;
  attribute LC_PROBE359_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101100111";
  attribute LC_PROBE359_TYPE : integer;
  attribute LC_PROBE359_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE359_WIDTH : integer;
  attribute LC_PROBE359_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE35_IS_DATA : string;
  attribute LC_PROBE35_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE35_IS_TRIG : string;
  attribute LC_PROBE35_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE35_MU_CNT : integer;
  attribute LC_PROBE35_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE35_PID : string;
  attribute LC_PROBE35_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100011";
  attribute LC_PROBE35_TYPE : integer;
  attribute LC_PROBE35_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE35_WIDTH : integer;
  attribute LC_PROBE35_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE360_IS_DATA : string;
  attribute LC_PROBE360_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE360_IS_TRIG : string;
  attribute LC_PROBE360_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE360_MU_CNT : integer;
  attribute LC_PROBE360_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE360_PID : string;
  attribute LC_PROBE360_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101000";
  attribute LC_PROBE360_TYPE : integer;
  attribute LC_PROBE360_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE360_WIDTH : integer;
  attribute LC_PROBE360_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE361_IS_DATA : string;
  attribute LC_PROBE361_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE361_IS_TRIG : string;
  attribute LC_PROBE361_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE361_MU_CNT : integer;
  attribute LC_PROBE361_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE361_PID : string;
  attribute LC_PROBE361_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101001";
  attribute LC_PROBE361_TYPE : integer;
  attribute LC_PROBE361_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE361_WIDTH : integer;
  attribute LC_PROBE361_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE362_IS_DATA : string;
  attribute LC_PROBE362_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE362_IS_TRIG : string;
  attribute LC_PROBE362_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE362_MU_CNT : integer;
  attribute LC_PROBE362_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE362_PID : string;
  attribute LC_PROBE362_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101010";
  attribute LC_PROBE362_TYPE : integer;
  attribute LC_PROBE362_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE362_WIDTH : integer;
  attribute LC_PROBE362_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE363_IS_DATA : string;
  attribute LC_PROBE363_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE363_IS_TRIG : string;
  attribute LC_PROBE363_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE363_MU_CNT : integer;
  attribute LC_PROBE363_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE363_PID : string;
  attribute LC_PROBE363_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101011";
  attribute LC_PROBE363_TYPE : integer;
  attribute LC_PROBE363_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE363_WIDTH : integer;
  attribute LC_PROBE363_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE364_IS_DATA : string;
  attribute LC_PROBE364_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE364_IS_TRIG : string;
  attribute LC_PROBE364_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE364_MU_CNT : integer;
  attribute LC_PROBE364_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE364_PID : string;
  attribute LC_PROBE364_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101100";
  attribute LC_PROBE364_TYPE : integer;
  attribute LC_PROBE364_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE364_WIDTH : integer;
  attribute LC_PROBE364_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE365_IS_DATA : string;
  attribute LC_PROBE365_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE365_IS_TRIG : string;
  attribute LC_PROBE365_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE365_MU_CNT : integer;
  attribute LC_PROBE365_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE365_PID : string;
  attribute LC_PROBE365_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101101";
  attribute LC_PROBE365_TYPE : integer;
  attribute LC_PROBE365_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE365_WIDTH : integer;
  attribute LC_PROBE365_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE366_IS_DATA : string;
  attribute LC_PROBE366_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE366_IS_TRIG : string;
  attribute LC_PROBE366_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE366_MU_CNT : integer;
  attribute LC_PROBE366_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE366_PID : string;
  attribute LC_PROBE366_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101110";
  attribute LC_PROBE366_TYPE : integer;
  attribute LC_PROBE366_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE366_WIDTH : integer;
  attribute LC_PROBE366_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE367_IS_DATA : string;
  attribute LC_PROBE367_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE367_IS_TRIG : string;
  attribute LC_PROBE367_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE367_MU_CNT : integer;
  attribute LC_PROBE367_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE367_PID : string;
  attribute LC_PROBE367_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101101111";
  attribute LC_PROBE367_TYPE : integer;
  attribute LC_PROBE367_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE367_WIDTH : integer;
  attribute LC_PROBE367_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE368_IS_DATA : string;
  attribute LC_PROBE368_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE368_IS_TRIG : string;
  attribute LC_PROBE368_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE368_MU_CNT : integer;
  attribute LC_PROBE368_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE368_PID : string;
  attribute LC_PROBE368_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110000";
  attribute LC_PROBE368_TYPE : integer;
  attribute LC_PROBE368_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE368_WIDTH : integer;
  attribute LC_PROBE368_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE369_IS_DATA : string;
  attribute LC_PROBE369_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE369_IS_TRIG : string;
  attribute LC_PROBE369_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE369_MU_CNT : integer;
  attribute LC_PROBE369_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE369_PID : string;
  attribute LC_PROBE369_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110001";
  attribute LC_PROBE369_TYPE : integer;
  attribute LC_PROBE369_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE369_WIDTH : integer;
  attribute LC_PROBE369_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE36_IS_DATA : string;
  attribute LC_PROBE36_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE36_IS_TRIG : string;
  attribute LC_PROBE36_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE36_MU_CNT : integer;
  attribute LC_PROBE36_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE36_PID : string;
  attribute LC_PROBE36_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100100";
  attribute LC_PROBE36_TYPE : integer;
  attribute LC_PROBE36_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE36_WIDTH : integer;
  attribute LC_PROBE36_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE370_IS_DATA : string;
  attribute LC_PROBE370_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE370_IS_TRIG : string;
  attribute LC_PROBE370_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE370_MU_CNT : integer;
  attribute LC_PROBE370_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE370_PID : string;
  attribute LC_PROBE370_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110010";
  attribute LC_PROBE370_TYPE : integer;
  attribute LC_PROBE370_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE370_WIDTH : integer;
  attribute LC_PROBE370_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE371_IS_DATA : string;
  attribute LC_PROBE371_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE371_IS_TRIG : string;
  attribute LC_PROBE371_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE371_MU_CNT : integer;
  attribute LC_PROBE371_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE371_PID : string;
  attribute LC_PROBE371_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110011";
  attribute LC_PROBE371_TYPE : integer;
  attribute LC_PROBE371_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE371_WIDTH : integer;
  attribute LC_PROBE371_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE372_IS_DATA : string;
  attribute LC_PROBE372_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE372_IS_TRIG : string;
  attribute LC_PROBE372_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE372_MU_CNT : integer;
  attribute LC_PROBE372_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE372_PID : string;
  attribute LC_PROBE372_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110100";
  attribute LC_PROBE372_TYPE : integer;
  attribute LC_PROBE372_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE372_WIDTH : integer;
  attribute LC_PROBE372_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE373_IS_DATA : string;
  attribute LC_PROBE373_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE373_IS_TRIG : string;
  attribute LC_PROBE373_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE373_MU_CNT : integer;
  attribute LC_PROBE373_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE373_PID : string;
  attribute LC_PROBE373_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110101";
  attribute LC_PROBE373_TYPE : integer;
  attribute LC_PROBE373_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE373_WIDTH : integer;
  attribute LC_PROBE373_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE374_IS_DATA : string;
  attribute LC_PROBE374_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE374_IS_TRIG : string;
  attribute LC_PROBE374_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE374_MU_CNT : integer;
  attribute LC_PROBE374_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE374_PID : string;
  attribute LC_PROBE374_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110110";
  attribute LC_PROBE374_TYPE : integer;
  attribute LC_PROBE374_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE374_WIDTH : integer;
  attribute LC_PROBE374_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE375_IS_DATA : string;
  attribute LC_PROBE375_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE375_IS_TRIG : string;
  attribute LC_PROBE375_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE375_MU_CNT : integer;
  attribute LC_PROBE375_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE375_PID : string;
  attribute LC_PROBE375_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101110111";
  attribute LC_PROBE375_TYPE : integer;
  attribute LC_PROBE375_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE375_WIDTH : integer;
  attribute LC_PROBE375_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE376_IS_DATA : string;
  attribute LC_PROBE376_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE376_IS_TRIG : string;
  attribute LC_PROBE376_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE376_MU_CNT : integer;
  attribute LC_PROBE376_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE376_PID : string;
  attribute LC_PROBE376_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111000";
  attribute LC_PROBE376_TYPE : integer;
  attribute LC_PROBE376_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE376_WIDTH : integer;
  attribute LC_PROBE376_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE377_IS_DATA : string;
  attribute LC_PROBE377_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE377_IS_TRIG : string;
  attribute LC_PROBE377_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE377_MU_CNT : integer;
  attribute LC_PROBE377_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE377_PID : string;
  attribute LC_PROBE377_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111001";
  attribute LC_PROBE377_TYPE : integer;
  attribute LC_PROBE377_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE377_WIDTH : integer;
  attribute LC_PROBE377_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE378_IS_DATA : string;
  attribute LC_PROBE378_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE378_IS_TRIG : string;
  attribute LC_PROBE378_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE378_MU_CNT : integer;
  attribute LC_PROBE378_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE378_PID : string;
  attribute LC_PROBE378_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111010";
  attribute LC_PROBE378_TYPE : integer;
  attribute LC_PROBE378_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE378_WIDTH : integer;
  attribute LC_PROBE378_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE379_IS_DATA : string;
  attribute LC_PROBE379_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE379_IS_TRIG : string;
  attribute LC_PROBE379_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE379_MU_CNT : integer;
  attribute LC_PROBE379_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE379_PID : string;
  attribute LC_PROBE379_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111011";
  attribute LC_PROBE379_TYPE : integer;
  attribute LC_PROBE379_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE379_WIDTH : integer;
  attribute LC_PROBE379_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE37_IS_DATA : string;
  attribute LC_PROBE37_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE37_IS_TRIG : string;
  attribute LC_PROBE37_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE37_MU_CNT : integer;
  attribute LC_PROBE37_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE37_PID : string;
  attribute LC_PROBE37_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100101";
  attribute LC_PROBE37_TYPE : integer;
  attribute LC_PROBE37_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE37_WIDTH : integer;
  attribute LC_PROBE37_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE380_IS_DATA : string;
  attribute LC_PROBE380_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE380_IS_TRIG : string;
  attribute LC_PROBE380_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE380_MU_CNT : integer;
  attribute LC_PROBE380_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE380_PID : string;
  attribute LC_PROBE380_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111100";
  attribute LC_PROBE380_TYPE : integer;
  attribute LC_PROBE380_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE380_WIDTH : integer;
  attribute LC_PROBE380_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE381_IS_DATA : string;
  attribute LC_PROBE381_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE381_IS_TRIG : string;
  attribute LC_PROBE381_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE381_MU_CNT : integer;
  attribute LC_PROBE381_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE381_PID : string;
  attribute LC_PROBE381_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111101";
  attribute LC_PROBE381_TYPE : integer;
  attribute LC_PROBE381_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE381_WIDTH : integer;
  attribute LC_PROBE381_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE382_IS_DATA : string;
  attribute LC_PROBE382_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE382_IS_TRIG : string;
  attribute LC_PROBE382_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE382_MU_CNT : integer;
  attribute LC_PROBE382_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE382_PID : string;
  attribute LC_PROBE382_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111110";
  attribute LC_PROBE382_TYPE : integer;
  attribute LC_PROBE382_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE382_WIDTH : integer;
  attribute LC_PROBE382_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE383_IS_DATA : string;
  attribute LC_PROBE383_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE383_IS_TRIG : string;
  attribute LC_PROBE383_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE383_MU_CNT : integer;
  attribute LC_PROBE383_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE383_PID : string;
  attribute LC_PROBE383_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000101111111";
  attribute LC_PROBE383_TYPE : integer;
  attribute LC_PROBE383_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE383_WIDTH : integer;
  attribute LC_PROBE383_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE384_IS_DATA : string;
  attribute LC_PROBE384_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE384_IS_TRIG : string;
  attribute LC_PROBE384_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE384_MU_CNT : integer;
  attribute LC_PROBE384_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE384_PID : string;
  attribute LC_PROBE384_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000000";
  attribute LC_PROBE384_TYPE : integer;
  attribute LC_PROBE384_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE384_WIDTH : integer;
  attribute LC_PROBE384_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE385_IS_DATA : string;
  attribute LC_PROBE385_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE385_IS_TRIG : string;
  attribute LC_PROBE385_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE385_MU_CNT : integer;
  attribute LC_PROBE385_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE385_PID : string;
  attribute LC_PROBE385_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000001";
  attribute LC_PROBE385_TYPE : integer;
  attribute LC_PROBE385_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE385_WIDTH : integer;
  attribute LC_PROBE385_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE386_IS_DATA : string;
  attribute LC_PROBE386_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE386_IS_TRIG : string;
  attribute LC_PROBE386_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE386_MU_CNT : integer;
  attribute LC_PROBE386_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE386_PID : string;
  attribute LC_PROBE386_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000010";
  attribute LC_PROBE386_TYPE : integer;
  attribute LC_PROBE386_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE386_WIDTH : integer;
  attribute LC_PROBE386_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE387_IS_DATA : string;
  attribute LC_PROBE387_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE387_IS_TRIG : string;
  attribute LC_PROBE387_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE387_MU_CNT : integer;
  attribute LC_PROBE387_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE387_PID : string;
  attribute LC_PROBE387_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000011";
  attribute LC_PROBE387_TYPE : integer;
  attribute LC_PROBE387_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE387_WIDTH : integer;
  attribute LC_PROBE387_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE388_IS_DATA : string;
  attribute LC_PROBE388_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE388_IS_TRIG : string;
  attribute LC_PROBE388_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE388_MU_CNT : integer;
  attribute LC_PROBE388_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE388_PID : string;
  attribute LC_PROBE388_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000100";
  attribute LC_PROBE388_TYPE : integer;
  attribute LC_PROBE388_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE388_WIDTH : integer;
  attribute LC_PROBE388_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE389_IS_DATA : string;
  attribute LC_PROBE389_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE389_IS_TRIG : string;
  attribute LC_PROBE389_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE389_MU_CNT : integer;
  attribute LC_PROBE389_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE389_PID : string;
  attribute LC_PROBE389_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000101";
  attribute LC_PROBE389_TYPE : integer;
  attribute LC_PROBE389_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE389_WIDTH : integer;
  attribute LC_PROBE389_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE38_IS_DATA : string;
  attribute LC_PROBE38_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE38_IS_TRIG : string;
  attribute LC_PROBE38_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE38_MU_CNT : integer;
  attribute LC_PROBE38_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE38_PID : string;
  attribute LC_PROBE38_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100110";
  attribute LC_PROBE38_TYPE : integer;
  attribute LC_PROBE38_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE38_WIDTH : integer;
  attribute LC_PROBE38_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE390_IS_DATA : string;
  attribute LC_PROBE390_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE390_IS_TRIG : string;
  attribute LC_PROBE390_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE390_MU_CNT : integer;
  attribute LC_PROBE390_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE390_PID : string;
  attribute LC_PROBE390_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000110";
  attribute LC_PROBE390_TYPE : integer;
  attribute LC_PROBE390_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE390_WIDTH : integer;
  attribute LC_PROBE390_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE391_IS_DATA : string;
  attribute LC_PROBE391_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE391_IS_TRIG : string;
  attribute LC_PROBE391_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE391_MU_CNT : integer;
  attribute LC_PROBE391_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE391_PID : string;
  attribute LC_PROBE391_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110000111";
  attribute LC_PROBE391_TYPE : integer;
  attribute LC_PROBE391_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE391_WIDTH : integer;
  attribute LC_PROBE391_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE392_IS_DATA : string;
  attribute LC_PROBE392_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE392_IS_TRIG : string;
  attribute LC_PROBE392_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE392_MU_CNT : integer;
  attribute LC_PROBE392_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE392_PID : string;
  attribute LC_PROBE392_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001000";
  attribute LC_PROBE392_TYPE : integer;
  attribute LC_PROBE392_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE392_WIDTH : integer;
  attribute LC_PROBE392_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE393_IS_DATA : string;
  attribute LC_PROBE393_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE393_IS_TRIG : string;
  attribute LC_PROBE393_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE393_MU_CNT : integer;
  attribute LC_PROBE393_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE393_PID : string;
  attribute LC_PROBE393_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001001";
  attribute LC_PROBE393_TYPE : integer;
  attribute LC_PROBE393_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE393_WIDTH : integer;
  attribute LC_PROBE393_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE394_IS_DATA : string;
  attribute LC_PROBE394_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE394_IS_TRIG : string;
  attribute LC_PROBE394_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE394_MU_CNT : integer;
  attribute LC_PROBE394_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE394_PID : string;
  attribute LC_PROBE394_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001010";
  attribute LC_PROBE394_TYPE : integer;
  attribute LC_PROBE394_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE394_WIDTH : integer;
  attribute LC_PROBE394_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE395_IS_DATA : string;
  attribute LC_PROBE395_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE395_IS_TRIG : string;
  attribute LC_PROBE395_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE395_MU_CNT : integer;
  attribute LC_PROBE395_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE395_PID : string;
  attribute LC_PROBE395_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001011";
  attribute LC_PROBE395_TYPE : integer;
  attribute LC_PROBE395_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE395_WIDTH : integer;
  attribute LC_PROBE395_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE396_IS_DATA : string;
  attribute LC_PROBE396_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE396_IS_TRIG : string;
  attribute LC_PROBE396_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE396_MU_CNT : integer;
  attribute LC_PROBE396_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE396_PID : string;
  attribute LC_PROBE396_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001100";
  attribute LC_PROBE396_TYPE : integer;
  attribute LC_PROBE396_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE396_WIDTH : integer;
  attribute LC_PROBE396_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE397_IS_DATA : string;
  attribute LC_PROBE397_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE397_IS_TRIG : string;
  attribute LC_PROBE397_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE397_MU_CNT : integer;
  attribute LC_PROBE397_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE397_PID : string;
  attribute LC_PROBE397_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001101";
  attribute LC_PROBE397_TYPE : integer;
  attribute LC_PROBE397_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE397_WIDTH : integer;
  attribute LC_PROBE397_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE398_IS_DATA : string;
  attribute LC_PROBE398_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE398_IS_TRIG : string;
  attribute LC_PROBE398_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE398_MU_CNT : integer;
  attribute LC_PROBE398_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE398_PID : string;
  attribute LC_PROBE398_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001110";
  attribute LC_PROBE398_TYPE : integer;
  attribute LC_PROBE398_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE398_WIDTH : integer;
  attribute LC_PROBE398_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE399_IS_DATA : string;
  attribute LC_PROBE399_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE399_IS_TRIG : string;
  attribute LC_PROBE399_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE399_MU_CNT : integer;
  attribute LC_PROBE399_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE399_PID : string;
  attribute LC_PROBE399_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110001111";
  attribute LC_PROBE399_TYPE : integer;
  attribute LC_PROBE399_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE399_WIDTH : integer;
  attribute LC_PROBE399_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE39_IS_DATA : string;
  attribute LC_PROBE39_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE39_IS_TRIG : string;
  attribute LC_PROBE39_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE39_MU_CNT : integer;
  attribute LC_PROBE39_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE39_PID : string;
  attribute LC_PROBE39_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000100111";
  attribute LC_PROBE39_TYPE : integer;
  attribute LC_PROBE39_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE39_WIDTH : integer;
  attribute LC_PROBE39_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE3_IS_DATA : string;
  attribute LC_PROBE3_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE3_IS_TRIG : string;
  attribute LC_PROBE3_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE3_MU_CNT : integer;
  attribute LC_PROBE3_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE3_PID : string;
  attribute LC_PROBE3_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000011";
  attribute LC_PROBE3_TYPE : integer;
  attribute LC_PROBE3_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE3_WIDTH : integer;
  attribute LC_PROBE3_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 8;
  attribute LC_PROBE400_IS_DATA : string;
  attribute LC_PROBE400_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE400_IS_TRIG : string;
  attribute LC_PROBE400_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE400_MU_CNT : integer;
  attribute LC_PROBE400_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE400_PID : string;
  attribute LC_PROBE400_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010000";
  attribute LC_PROBE400_TYPE : integer;
  attribute LC_PROBE400_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE400_WIDTH : integer;
  attribute LC_PROBE400_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE401_IS_DATA : string;
  attribute LC_PROBE401_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE401_IS_TRIG : string;
  attribute LC_PROBE401_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE401_MU_CNT : integer;
  attribute LC_PROBE401_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE401_PID : string;
  attribute LC_PROBE401_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010001";
  attribute LC_PROBE401_TYPE : integer;
  attribute LC_PROBE401_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE401_WIDTH : integer;
  attribute LC_PROBE401_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE402_IS_DATA : string;
  attribute LC_PROBE402_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE402_IS_TRIG : string;
  attribute LC_PROBE402_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE402_MU_CNT : integer;
  attribute LC_PROBE402_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE402_PID : string;
  attribute LC_PROBE402_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010010";
  attribute LC_PROBE402_TYPE : integer;
  attribute LC_PROBE402_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE402_WIDTH : integer;
  attribute LC_PROBE402_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE403_IS_DATA : string;
  attribute LC_PROBE403_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE403_IS_TRIG : string;
  attribute LC_PROBE403_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE403_MU_CNT : integer;
  attribute LC_PROBE403_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE403_PID : string;
  attribute LC_PROBE403_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010011";
  attribute LC_PROBE403_TYPE : integer;
  attribute LC_PROBE403_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE403_WIDTH : integer;
  attribute LC_PROBE403_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE404_IS_DATA : string;
  attribute LC_PROBE404_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE404_IS_TRIG : string;
  attribute LC_PROBE404_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE404_MU_CNT : integer;
  attribute LC_PROBE404_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE404_PID : string;
  attribute LC_PROBE404_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010100";
  attribute LC_PROBE404_TYPE : integer;
  attribute LC_PROBE404_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE404_WIDTH : integer;
  attribute LC_PROBE404_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE405_IS_DATA : string;
  attribute LC_PROBE405_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE405_IS_TRIG : string;
  attribute LC_PROBE405_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE405_MU_CNT : integer;
  attribute LC_PROBE405_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE405_PID : string;
  attribute LC_PROBE405_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010101";
  attribute LC_PROBE405_TYPE : integer;
  attribute LC_PROBE405_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE405_WIDTH : integer;
  attribute LC_PROBE405_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE406_IS_DATA : string;
  attribute LC_PROBE406_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE406_IS_TRIG : string;
  attribute LC_PROBE406_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE406_MU_CNT : integer;
  attribute LC_PROBE406_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE406_PID : string;
  attribute LC_PROBE406_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010110";
  attribute LC_PROBE406_TYPE : integer;
  attribute LC_PROBE406_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE406_WIDTH : integer;
  attribute LC_PROBE406_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE407_IS_DATA : string;
  attribute LC_PROBE407_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE407_IS_TRIG : string;
  attribute LC_PROBE407_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE407_MU_CNT : integer;
  attribute LC_PROBE407_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE407_PID : string;
  attribute LC_PROBE407_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110010111";
  attribute LC_PROBE407_TYPE : integer;
  attribute LC_PROBE407_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE407_WIDTH : integer;
  attribute LC_PROBE407_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE408_IS_DATA : string;
  attribute LC_PROBE408_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE408_IS_TRIG : string;
  attribute LC_PROBE408_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE408_MU_CNT : integer;
  attribute LC_PROBE408_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE408_PID : string;
  attribute LC_PROBE408_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011000";
  attribute LC_PROBE408_TYPE : integer;
  attribute LC_PROBE408_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE408_WIDTH : integer;
  attribute LC_PROBE408_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE409_IS_DATA : string;
  attribute LC_PROBE409_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE409_IS_TRIG : string;
  attribute LC_PROBE409_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE409_MU_CNT : integer;
  attribute LC_PROBE409_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE409_PID : string;
  attribute LC_PROBE409_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011001";
  attribute LC_PROBE409_TYPE : integer;
  attribute LC_PROBE409_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE409_WIDTH : integer;
  attribute LC_PROBE409_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE40_IS_DATA : string;
  attribute LC_PROBE40_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE40_IS_TRIG : string;
  attribute LC_PROBE40_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE40_MU_CNT : integer;
  attribute LC_PROBE40_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE40_PID : string;
  attribute LC_PROBE40_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101000";
  attribute LC_PROBE40_TYPE : integer;
  attribute LC_PROBE40_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE40_WIDTH : integer;
  attribute LC_PROBE40_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE410_IS_DATA : string;
  attribute LC_PROBE410_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE410_IS_TRIG : string;
  attribute LC_PROBE410_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE410_MU_CNT : integer;
  attribute LC_PROBE410_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE410_PID : string;
  attribute LC_PROBE410_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011010";
  attribute LC_PROBE410_TYPE : integer;
  attribute LC_PROBE410_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE410_WIDTH : integer;
  attribute LC_PROBE410_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE411_IS_DATA : string;
  attribute LC_PROBE411_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE411_IS_TRIG : string;
  attribute LC_PROBE411_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE411_MU_CNT : integer;
  attribute LC_PROBE411_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE411_PID : string;
  attribute LC_PROBE411_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011011";
  attribute LC_PROBE411_TYPE : integer;
  attribute LC_PROBE411_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE411_WIDTH : integer;
  attribute LC_PROBE411_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE412_IS_DATA : string;
  attribute LC_PROBE412_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE412_IS_TRIG : string;
  attribute LC_PROBE412_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE412_MU_CNT : integer;
  attribute LC_PROBE412_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE412_PID : string;
  attribute LC_PROBE412_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011100";
  attribute LC_PROBE412_TYPE : integer;
  attribute LC_PROBE412_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE412_WIDTH : integer;
  attribute LC_PROBE412_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE413_IS_DATA : string;
  attribute LC_PROBE413_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE413_IS_TRIG : string;
  attribute LC_PROBE413_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE413_MU_CNT : integer;
  attribute LC_PROBE413_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE413_PID : string;
  attribute LC_PROBE413_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011101";
  attribute LC_PROBE413_TYPE : integer;
  attribute LC_PROBE413_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE413_WIDTH : integer;
  attribute LC_PROBE413_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE414_IS_DATA : string;
  attribute LC_PROBE414_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE414_IS_TRIG : string;
  attribute LC_PROBE414_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE414_MU_CNT : integer;
  attribute LC_PROBE414_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE414_PID : string;
  attribute LC_PROBE414_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011110";
  attribute LC_PROBE414_TYPE : integer;
  attribute LC_PROBE414_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE414_WIDTH : integer;
  attribute LC_PROBE414_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE415_IS_DATA : string;
  attribute LC_PROBE415_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE415_IS_TRIG : string;
  attribute LC_PROBE415_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE415_MU_CNT : integer;
  attribute LC_PROBE415_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE415_PID : string;
  attribute LC_PROBE415_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110011111";
  attribute LC_PROBE415_TYPE : integer;
  attribute LC_PROBE415_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE415_WIDTH : integer;
  attribute LC_PROBE415_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE416_IS_DATA : string;
  attribute LC_PROBE416_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE416_IS_TRIG : string;
  attribute LC_PROBE416_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE416_MU_CNT : integer;
  attribute LC_PROBE416_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE416_PID : string;
  attribute LC_PROBE416_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100000";
  attribute LC_PROBE416_TYPE : integer;
  attribute LC_PROBE416_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE416_WIDTH : integer;
  attribute LC_PROBE416_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE417_IS_DATA : string;
  attribute LC_PROBE417_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE417_IS_TRIG : string;
  attribute LC_PROBE417_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE417_MU_CNT : integer;
  attribute LC_PROBE417_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE417_PID : string;
  attribute LC_PROBE417_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100001";
  attribute LC_PROBE417_TYPE : integer;
  attribute LC_PROBE417_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE417_WIDTH : integer;
  attribute LC_PROBE417_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE418_IS_DATA : string;
  attribute LC_PROBE418_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE418_IS_TRIG : string;
  attribute LC_PROBE418_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE418_MU_CNT : integer;
  attribute LC_PROBE418_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE418_PID : string;
  attribute LC_PROBE418_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100010";
  attribute LC_PROBE418_TYPE : integer;
  attribute LC_PROBE418_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE418_WIDTH : integer;
  attribute LC_PROBE418_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE419_IS_DATA : string;
  attribute LC_PROBE419_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE419_IS_TRIG : string;
  attribute LC_PROBE419_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE419_MU_CNT : integer;
  attribute LC_PROBE419_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE419_PID : string;
  attribute LC_PROBE419_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100011";
  attribute LC_PROBE419_TYPE : integer;
  attribute LC_PROBE419_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE419_WIDTH : integer;
  attribute LC_PROBE419_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE41_IS_DATA : string;
  attribute LC_PROBE41_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE41_IS_TRIG : string;
  attribute LC_PROBE41_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE41_MU_CNT : integer;
  attribute LC_PROBE41_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE41_PID : string;
  attribute LC_PROBE41_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101001";
  attribute LC_PROBE41_TYPE : integer;
  attribute LC_PROBE41_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE41_WIDTH : integer;
  attribute LC_PROBE41_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE420_IS_DATA : string;
  attribute LC_PROBE420_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE420_IS_TRIG : string;
  attribute LC_PROBE420_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE420_MU_CNT : integer;
  attribute LC_PROBE420_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE420_PID : string;
  attribute LC_PROBE420_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100100";
  attribute LC_PROBE420_TYPE : integer;
  attribute LC_PROBE420_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE420_WIDTH : integer;
  attribute LC_PROBE420_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE421_IS_DATA : string;
  attribute LC_PROBE421_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE421_IS_TRIG : string;
  attribute LC_PROBE421_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE421_MU_CNT : integer;
  attribute LC_PROBE421_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE421_PID : string;
  attribute LC_PROBE421_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100101";
  attribute LC_PROBE421_TYPE : integer;
  attribute LC_PROBE421_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE421_WIDTH : integer;
  attribute LC_PROBE421_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE422_IS_DATA : string;
  attribute LC_PROBE422_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE422_IS_TRIG : string;
  attribute LC_PROBE422_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE422_MU_CNT : integer;
  attribute LC_PROBE422_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE422_PID : string;
  attribute LC_PROBE422_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100110";
  attribute LC_PROBE422_TYPE : integer;
  attribute LC_PROBE422_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE422_WIDTH : integer;
  attribute LC_PROBE422_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE423_IS_DATA : string;
  attribute LC_PROBE423_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE423_IS_TRIG : string;
  attribute LC_PROBE423_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE423_MU_CNT : integer;
  attribute LC_PROBE423_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE423_PID : string;
  attribute LC_PROBE423_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110100111";
  attribute LC_PROBE423_TYPE : integer;
  attribute LC_PROBE423_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE423_WIDTH : integer;
  attribute LC_PROBE423_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE424_IS_DATA : string;
  attribute LC_PROBE424_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE424_IS_TRIG : string;
  attribute LC_PROBE424_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE424_MU_CNT : integer;
  attribute LC_PROBE424_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE424_PID : string;
  attribute LC_PROBE424_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101000";
  attribute LC_PROBE424_TYPE : integer;
  attribute LC_PROBE424_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE424_WIDTH : integer;
  attribute LC_PROBE424_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE425_IS_DATA : string;
  attribute LC_PROBE425_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE425_IS_TRIG : string;
  attribute LC_PROBE425_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE425_MU_CNT : integer;
  attribute LC_PROBE425_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE425_PID : string;
  attribute LC_PROBE425_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101001";
  attribute LC_PROBE425_TYPE : integer;
  attribute LC_PROBE425_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE425_WIDTH : integer;
  attribute LC_PROBE425_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE426_IS_DATA : string;
  attribute LC_PROBE426_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE426_IS_TRIG : string;
  attribute LC_PROBE426_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE426_MU_CNT : integer;
  attribute LC_PROBE426_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE426_PID : string;
  attribute LC_PROBE426_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101010";
  attribute LC_PROBE426_TYPE : integer;
  attribute LC_PROBE426_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE426_WIDTH : integer;
  attribute LC_PROBE426_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE427_IS_DATA : string;
  attribute LC_PROBE427_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE427_IS_TRIG : string;
  attribute LC_PROBE427_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE427_MU_CNT : integer;
  attribute LC_PROBE427_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE427_PID : string;
  attribute LC_PROBE427_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101011";
  attribute LC_PROBE427_TYPE : integer;
  attribute LC_PROBE427_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE427_WIDTH : integer;
  attribute LC_PROBE427_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE428_IS_DATA : string;
  attribute LC_PROBE428_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE428_IS_TRIG : string;
  attribute LC_PROBE428_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE428_MU_CNT : integer;
  attribute LC_PROBE428_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE428_PID : string;
  attribute LC_PROBE428_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101100";
  attribute LC_PROBE428_TYPE : integer;
  attribute LC_PROBE428_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE428_WIDTH : integer;
  attribute LC_PROBE428_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE429_IS_DATA : string;
  attribute LC_PROBE429_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE429_IS_TRIG : string;
  attribute LC_PROBE429_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE429_MU_CNT : integer;
  attribute LC_PROBE429_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE429_PID : string;
  attribute LC_PROBE429_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101101";
  attribute LC_PROBE429_TYPE : integer;
  attribute LC_PROBE429_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE429_WIDTH : integer;
  attribute LC_PROBE429_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE42_IS_DATA : string;
  attribute LC_PROBE42_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE42_IS_TRIG : string;
  attribute LC_PROBE42_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE42_MU_CNT : integer;
  attribute LC_PROBE42_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE42_PID : string;
  attribute LC_PROBE42_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101010";
  attribute LC_PROBE42_TYPE : integer;
  attribute LC_PROBE42_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE42_WIDTH : integer;
  attribute LC_PROBE42_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE430_IS_DATA : string;
  attribute LC_PROBE430_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE430_IS_TRIG : string;
  attribute LC_PROBE430_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE430_MU_CNT : integer;
  attribute LC_PROBE430_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE430_PID : string;
  attribute LC_PROBE430_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101110";
  attribute LC_PROBE430_TYPE : integer;
  attribute LC_PROBE430_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE430_WIDTH : integer;
  attribute LC_PROBE430_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE431_IS_DATA : string;
  attribute LC_PROBE431_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE431_IS_TRIG : string;
  attribute LC_PROBE431_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE431_MU_CNT : integer;
  attribute LC_PROBE431_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE431_PID : string;
  attribute LC_PROBE431_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110101111";
  attribute LC_PROBE431_TYPE : integer;
  attribute LC_PROBE431_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE431_WIDTH : integer;
  attribute LC_PROBE431_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE432_IS_DATA : string;
  attribute LC_PROBE432_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE432_IS_TRIG : string;
  attribute LC_PROBE432_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE432_MU_CNT : integer;
  attribute LC_PROBE432_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE432_PID : string;
  attribute LC_PROBE432_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110000";
  attribute LC_PROBE432_TYPE : integer;
  attribute LC_PROBE432_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE432_WIDTH : integer;
  attribute LC_PROBE432_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE433_IS_DATA : string;
  attribute LC_PROBE433_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE433_IS_TRIG : string;
  attribute LC_PROBE433_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE433_MU_CNT : integer;
  attribute LC_PROBE433_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE433_PID : string;
  attribute LC_PROBE433_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110001";
  attribute LC_PROBE433_TYPE : integer;
  attribute LC_PROBE433_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE433_WIDTH : integer;
  attribute LC_PROBE433_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE434_IS_DATA : string;
  attribute LC_PROBE434_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE434_IS_TRIG : string;
  attribute LC_PROBE434_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE434_MU_CNT : integer;
  attribute LC_PROBE434_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE434_PID : string;
  attribute LC_PROBE434_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110010";
  attribute LC_PROBE434_TYPE : integer;
  attribute LC_PROBE434_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE434_WIDTH : integer;
  attribute LC_PROBE434_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE435_IS_DATA : string;
  attribute LC_PROBE435_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE435_IS_TRIG : string;
  attribute LC_PROBE435_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE435_MU_CNT : integer;
  attribute LC_PROBE435_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE435_PID : string;
  attribute LC_PROBE435_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110011";
  attribute LC_PROBE435_TYPE : integer;
  attribute LC_PROBE435_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE435_WIDTH : integer;
  attribute LC_PROBE435_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE436_IS_DATA : string;
  attribute LC_PROBE436_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE436_IS_TRIG : string;
  attribute LC_PROBE436_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE436_MU_CNT : integer;
  attribute LC_PROBE436_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE436_PID : string;
  attribute LC_PROBE436_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110100";
  attribute LC_PROBE436_TYPE : integer;
  attribute LC_PROBE436_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE436_WIDTH : integer;
  attribute LC_PROBE436_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE437_IS_DATA : string;
  attribute LC_PROBE437_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE437_IS_TRIG : string;
  attribute LC_PROBE437_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE437_MU_CNT : integer;
  attribute LC_PROBE437_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE437_PID : string;
  attribute LC_PROBE437_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110101";
  attribute LC_PROBE437_TYPE : integer;
  attribute LC_PROBE437_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE437_WIDTH : integer;
  attribute LC_PROBE437_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE438_IS_DATA : string;
  attribute LC_PROBE438_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE438_IS_TRIG : string;
  attribute LC_PROBE438_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE438_MU_CNT : integer;
  attribute LC_PROBE438_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE438_PID : string;
  attribute LC_PROBE438_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110110";
  attribute LC_PROBE438_TYPE : integer;
  attribute LC_PROBE438_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE438_WIDTH : integer;
  attribute LC_PROBE438_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE439_IS_DATA : string;
  attribute LC_PROBE439_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE439_IS_TRIG : string;
  attribute LC_PROBE439_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE439_MU_CNT : integer;
  attribute LC_PROBE439_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE439_PID : string;
  attribute LC_PROBE439_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110110111";
  attribute LC_PROBE439_TYPE : integer;
  attribute LC_PROBE439_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE439_WIDTH : integer;
  attribute LC_PROBE439_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE43_IS_DATA : string;
  attribute LC_PROBE43_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE43_IS_TRIG : string;
  attribute LC_PROBE43_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE43_MU_CNT : integer;
  attribute LC_PROBE43_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE43_PID : string;
  attribute LC_PROBE43_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101011";
  attribute LC_PROBE43_TYPE : integer;
  attribute LC_PROBE43_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE43_WIDTH : integer;
  attribute LC_PROBE43_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE440_IS_DATA : string;
  attribute LC_PROBE440_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE440_IS_TRIG : string;
  attribute LC_PROBE440_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE440_MU_CNT : integer;
  attribute LC_PROBE440_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE440_PID : string;
  attribute LC_PROBE440_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111000";
  attribute LC_PROBE440_TYPE : integer;
  attribute LC_PROBE440_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE440_WIDTH : integer;
  attribute LC_PROBE440_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE441_IS_DATA : string;
  attribute LC_PROBE441_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE441_IS_TRIG : string;
  attribute LC_PROBE441_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE441_MU_CNT : integer;
  attribute LC_PROBE441_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE441_PID : string;
  attribute LC_PROBE441_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111001";
  attribute LC_PROBE441_TYPE : integer;
  attribute LC_PROBE441_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE441_WIDTH : integer;
  attribute LC_PROBE441_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE442_IS_DATA : string;
  attribute LC_PROBE442_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE442_IS_TRIG : string;
  attribute LC_PROBE442_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE442_MU_CNT : integer;
  attribute LC_PROBE442_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE442_PID : string;
  attribute LC_PROBE442_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111010";
  attribute LC_PROBE442_TYPE : integer;
  attribute LC_PROBE442_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE442_WIDTH : integer;
  attribute LC_PROBE442_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE443_IS_DATA : string;
  attribute LC_PROBE443_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE443_IS_TRIG : string;
  attribute LC_PROBE443_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE443_MU_CNT : integer;
  attribute LC_PROBE443_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE443_PID : string;
  attribute LC_PROBE443_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111011";
  attribute LC_PROBE443_TYPE : integer;
  attribute LC_PROBE443_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE443_WIDTH : integer;
  attribute LC_PROBE443_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE444_IS_DATA : string;
  attribute LC_PROBE444_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE444_IS_TRIG : string;
  attribute LC_PROBE444_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE444_MU_CNT : integer;
  attribute LC_PROBE444_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE444_PID : string;
  attribute LC_PROBE444_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111100";
  attribute LC_PROBE444_TYPE : integer;
  attribute LC_PROBE444_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE444_WIDTH : integer;
  attribute LC_PROBE444_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE445_IS_DATA : string;
  attribute LC_PROBE445_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE445_IS_TRIG : string;
  attribute LC_PROBE445_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE445_MU_CNT : integer;
  attribute LC_PROBE445_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE445_PID : string;
  attribute LC_PROBE445_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111101";
  attribute LC_PROBE445_TYPE : integer;
  attribute LC_PROBE445_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE445_WIDTH : integer;
  attribute LC_PROBE445_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE446_IS_DATA : string;
  attribute LC_PROBE446_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE446_IS_TRIG : string;
  attribute LC_PROBE446_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE446_MU_CNT : integer;
  attribute LC_PROBE446_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE446_PID : string;
  attribute LC_PROBE446_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111110";
  attribute LC_PROBE446_TYPE : integer;
  attribute LC_PROBE446_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE446_WIDTH : integer;
  attribute LC_PROBE446_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE447_IS_DATA : string;
  attribute LC_PROBE447_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE447_IS_TRIG : string;
  attribute LC_PROBE447_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE447_MU_CNT : integer;
  attribute LC_PROBE447_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE447_PID : string;
  attribute LC_PROBE447_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000110111111";
  attribute LC_PROBE447_TYPE : integer;
  attribute LC_PROBE447_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE447_WIDTH : integer;
  attribute LC_PROBE447_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE448_IS_DATA : string;
  attribute LC_PROBE448_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE448_IS_TRIG : string;
  attribute LC_PROBE448_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE448_MU_CNT : integer;
  attribute LC_PROBE448_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE448_PID : string;
  attribute LC_PROBE448_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000000";
  attribute LC_PROBE448_TYPE : integer;
  attribute LC_PROBE448_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE448_WIDTH : integer;
  attribute LC_PROBE448_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE449_IS_DATA : string;
  attribute LC_PROBE449_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE449_IS_TRIG : string;
  attribute LC_PROBE449_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE449_MU_CNT : integer;
  attribute LC_PROBE449_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE449_PID : string;
  attribute LC_PROBE449_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000001";
  attribute LC_PROBE449_TYPE : integer;
  attribute LC_PROBE449_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE449_WIDTH : integer;
  attribute LC_PROBE449_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE44_IS_DATA : string;
  attribute LC_PROBE44_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE44_IS_TRIG : string;
  attribute LC_PROBE44_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE44_MU_CNT : integer;
  attribute LC_PROBE44_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE44_PID : string;
  attribute LC_PROBE44_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101100";
  attribute LC_PROBE44_TYPE : integer;
  attribute LC_PROBE44_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE44_WIDTH : integer;
  attribute LC_PROBE44_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE450_IS_DATA : string;
  attribute LC_PROBE450_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE450_IS_TRIG : string;
  attribute LC_PROBE450_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE450_MU_CNT : integer;
  attribute LC_PROBE450_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE450_PID : string;
  attribute LC_PROBE450_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000010";
  attribute LC_PROBE450_TYPE : integer;
  attribute LC_PROBE450_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE450_WIDTH : integer;
  attribute LC_PROBE450_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE451_IS_DATA : string;
  attribute LC_PROBE451_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE451_IS_TRIG : string;
  attribute LC_PROBE451_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE451_MU_CNT : integer;
  attribute LC_PROBE451_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE451_PID : string;
  attribute LC_PROBE451_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000011";
  attribute LC_PROBE451_TYPE : integer;
  attribute LC_PROBE451_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE451_WIDTH : integer;
  attribute LC_PROBE451_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE452_IS_DATA : string;
  attribute LC_PROBE452_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE452_IS_TRIG : string;
  attribute LC_PROBE452_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE452_MU_CNT : integer;
  attribute LC_PROBE452_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE452_PID : string;
  attribute LC_PROBE452_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000100";
  attribute LC_PROBE452_TYPE : integer;
  attribute LC_PROBE452_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE452_WIDTH : integer;
  attribute LC_PROBE452_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE453_IS_DATA : string;
  attribute LC_PROBE453_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE453_IS_TRIG : string;
  attribute LC_PROBE453_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE453_MU_CNT : integer;
  attribute LC_PROBE453_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE453_PID : string;
  attribute LC_PROBE453_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000101";
  attribute LC_PROBE453_TYPE : integer;
  attribute LC_PROBE453_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE453_WIDTH : integer;
  attribute LC_PROBE453_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE454_IS_DATA : string;
  attribute LC_PROBE454_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE454_IS_TRIG : string;
  attribute LC_PROBE454_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE454_MU_CNT : integer;
  attribute LC_PROBE454_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE454_PID : string;
  attribute LC_PROBE454_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000110";
  attribute LC_PROBE454_TYPE : integer;
  attribute LC_PROBE454_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE454_WIDTH : integer;
  attribute LC_PROBE454_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE455_IS_DATA : string;
  attribute LC_PROBE455_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE455_IS_TRIG : string;
  attribute LC_PROBE455_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE455_MU_CNT : integer;
  attribute LC_PROBE455_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE455_PID : string;
  attribute LC_PROBE455_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111000111";
  attribute LC_PROBE455_TYPE : integer;
  attribute LC_PROBE455_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE455_WIDTH : integer;
  attribute LC_PROBE455_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE456_IS_DATA : string;
  attribute LC_PROBE456_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE456_IS_TRIG : string;
  attribute LC_PROBE456_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE456_MU_CNT : integer;
  attribute LC_PROBE456_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE456_PID : string;
  attribute LC_PROBE456_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001000";
  attribute LC_PROBE456_TYPE : integer;
  attribute LC_PROBE456_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE456_WIDTH : integer;
  attribute LC_PROBE456_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE457_IS_DATA : string;
  attribute LC_PROBE457_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE457_IS_TRIG : string;
  attribute LC_PROBE457_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE457_MU_CNT : integer;
  attribute LC_PROBE457_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE457_PID : string;
  attribute LC_PROBE457_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001001";
  attribute LC_PROBE457_TYPE : integer;
  attribute LC_PROBE457_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE457_WIDTH : integer;
  attribute LC_PROBE457_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE458_IS_DATA : string;
  attribute LC_PROBE458_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE458_IS_TRIG : string;
  attribute LC_PROBE458_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE458_MU_CNT : integer;
  attribute LC_PROBE458_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE458_PID : string;
  attribute LC_PROBE458_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001010";
  attribute LC_PROBE458_TYPE : integer;
  attribute LC_PROBE458_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE458_WIDTH : integer;
  attribute LC_PROBE458_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE459_IS_DATA : string;
  attribute LC_PROBE459_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE459_IS_TRIG : string;
  attribute LC_PROBE459_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE459_MU_CNT : integer;
  attribute LC_PROBE459_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE459_PID : string;
  attribute LC_PROBE459_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001011";
  attribute LC_PROBE459_TYPE : integer;
  attribute LC_PROBE459_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE459_WIDTH : integer;
  attribute LC_PROBE459_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE45_IS_DATA : string;
  attribute LC_PROBE45_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE45_IS_TRIG : string;
  attribute LC_PROBE45_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE45_MU_CNT : integer;
  attribute LC_PROBE45_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE45_PID : string;
  attribute LC_PROBE45_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101101";
  attribute LC_PROBE45_TYPE : integer;
  attribute LC_PROBE45_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE45_WIDTH : integer;
  attribute LC_PROBE45_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE460_IS_DATA : string;
  attribute LC_PROBE460_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE460_IS_TRIG : string;
  attribute LC_PROBE460_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE460_MU_CNT : integer;
  attribute LC_PROBE460_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE460_PID : string;
  attribute LC_PROBE460_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001100";
  attribute LC_PROBE460_TYPE : integer;
  attribute LC_PROBE460_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE460_WIDTH : integer;
  attribute LC_PROBE460_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE461_IS_DATA : string;
  attribute LC_PROBE461_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE461_IS_TRIG : string;
  attribute LC_PROBE461_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE461_MU_CNT : integer;
  attribute LC_PROBE461_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE461_PID : string;
  attribute LC_PROBE461_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001101";
  attribute LC_PROBE461_TYPE : integer;
  attribute LC_PROBE461_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE461_WIDTH : integer;
  attribute LC_PROBE461_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE462_IS_DATA : string;
  attribute LC_PROBE462_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE462_IS_TRIG : string;
  attribute LC_PROBE462_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE462_MU_CNT : integer;
  attribute LC_PROBE462_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE462_PID : string;
  attribute LC_PROBE462_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001110";
  attribute LC_PROBE462_TYPE : integer;
  attribute LC_PROBE462_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE462_WIDTH : integer;
  attribute LC_PROBE462_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE463_IS_DATA : string;
  attribute LC_PROBE463_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE463_IS_TRIG : string;
  attribute LC_PROBE463_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE463_MU_CNT : integer;
  attribute LC_PROBE463_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE463_PID : string;
  attribute LC_PROBE463_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111001111";
  attribute LC_PROBE463_TYPE : integer;
  attribute LC_PROBE463_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE463_WIDTH : integer;
  attribute LC_PROBE463_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE464_IS_DATA : string;
  attribute LC_PROBE464_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE464_IS_TRIG : string;
  attribute LC_PROBE464_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE464_MU_CNT : integer;
  attribute LC_PROBE464_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE464_PID : string;
  attribute LC_PROBE464_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010000";
  attribute LC_PROBE464_TYPE : integer;
  attribute LC_PROBE464_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE464_WIDTH : integer;
  attribute LC_PROBE464_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE465_IS_DATA : string;
  attribute LC_PROBE465_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE465_IS_TRIG : string;
  attribute LC_PROBE465_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE465_MU_CNT : integer;
  attribute LC_PROBE465_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE465_PID : string;
  attribute LC_PROBE465_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010001";
  attribute LC_PROBE465_TYPE : integer;
  attribute LC_PROBE465_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE465_WIDTH : integer;
  attribute LC_PROBE465_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE466_IS_DATA : string;
  attribute LC_PROBE466_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE466_IS_TRIG : string;
  attribute LC_PROBE466_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE466_MU_CNT : integer;
  attribute LC_PROBE466_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE466_PID : string;
  attribute LC_PROBE466_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010010";
  attribute LC_PROBE466_TYPE : integer;
  attribute LC_PROBE466_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE466_WIDTH : integer;
  attribute LC_PROBE466_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE467_IS_DATA : string;
  attribute LC_PROBE467_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE467_IS_TRIG : string;
  attribute LC_PROBE467_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE467_MU_CNT : integer;
  attribute LC_PROBE467_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE467_PID : string;
  attribute LC_PROBE467_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010011";
  attribute LC_PROBE467_TYPE : integer;
  attribute LC_PROBE467_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE467_WIDTH : integer;
  attribute LC_PROBE467_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE468_IS_DATA : string;
  attribute LC_PROBE468_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE468_IS_TRIG : string;
  attribute LC_PROBE468_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE468_MU_CNT : integer;
  attribute LC_PROBE468_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE468_PID : string;
  attribute LC_PROBE468_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010100";
  attribute LC_PROBE468_TYPE : integer;
  attribute LC_PROBE468_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE468_WIDTH : integer;
  attribute LC_PROBE468_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE469_IS_DATA : string;
  attribute LC_PROBE469_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE469_IS_TRIG : string;
  attribute LC_PROBE469_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE469_MU_CNT : integer;
  attribute LC_PROBE469_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE469_PID : string;
  attribute LC_PROBE469_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010101";
  attribute LC_PROBE469_TYPE : integer;
  attribute LC_PROBE469_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE469_WIDTH : integer;
  attribute LC_PROBE469_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE46_IS_DATA : string;
  attribute LC_PROBE46_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE46_IS_TRIG : string;
  attribute LC_PROBE46_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE46_MU_CNT : integer;
  attribute LC_PROBE46_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE46_PID : string;
  attribute LC_PROBE46_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101110";
  attribute LC_PROBE46_TYPE : integer;
  attribute LC_PROBE46_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE46_WIDTH : integer;
  attribute LC_PROBE46_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE470_IS_DATA : string;
  attribute LC_PROBE470_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE470_IS_TRIG : string;
  attribute LC_PROBE470_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE470_MU_CNT : integer;
  attribute LC_PROBE470_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE470_PID : string;
  attribute LC_PROBE470_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010110";
  attribute LC_PROBE470_TYPE : integer;
  attribute LC_PROBE470_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE470_WIDTH : integer;
  attribute LC_PROBE470_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE471_IS_DATA : string;
  attribute LC_PROBE471_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE471_IS_TRIG : string;
  attribute LC_PROBE471_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE471_MU_CNT : integer;
  attribute LC_PROBE471_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE471_PID : string;
  attribute LC_PROBE471_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111010111";
  attribute LC_PROBE471_TYPE : integer;
  attribute LC_PROBE471_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE471_WIDTH : integer;
  attribute LC_PROBE471_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE472_IS_DATA : string;
  attribute LC_PROBE472_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE472_IS_TRIG : string;
  attribute LC_PROBE472_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE472_MU_CNT : integer;
  attribute LC_PROBE472_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE472_PID : string;
  attribute LC_PROBE472_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011000";
  attribute LC_PROBE472_TYPE : integer;
  attribute LC_PROBE472_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE472_WIDTH : integer;
  attribute LC_PROBE472_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE473_IS_DATA : string;
  attribute LC_PROBE473_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE473_IS_TRIG : string;
  attribute LC_PROBE473_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE473_MU_CNT : integer;
  attribute LC_PROBE473_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE473_PID : string;
  attribute LC_PROBE473_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011001";
  attribute LC_PROBE473_TYPE : integer;
  attribute LC_PROBE473_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE473_WIDTH : integer;
  attribute LC_PROBE473_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE474_IS_DATA : string;
  attribute LC_PROBE474_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE474_IS_TRIG : string;
  attribute LC_PROBE474_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE474_MU_CNT : integer;
  attribute LC_PROBE474_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE474_PID : string;
  attribute LC_PROBE474_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011010";
  attribute LC_PROBE474_TYPE : integer;
  attribute LC_PROBE474_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE474_WIDTH : integer;
  attribute LC_PROBE474_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE475_IS_DATA : string;
  attribute LC_PROBE475_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE475_IS_TRIG : string;
  attribute LC_PROBE475_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE475_MU_CNT : integer;
  attribute LC_PROBE475_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE475_PID : string;
  attribute LC_PROBE475_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011011";
  attribute LC_PROBE475_TYPE : integer;
  attribute LC_PROBE475_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE475_WIDTH : integer;
  attribute LC_PROBE475_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE476_IS_DATA : string;
  attribute LC_PROBE476_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE476_IS_TRIG : string;
  attribute LC_PROBE476_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE476_MU_CNT : integer;
  attribute LC_PROBE476_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE476_PID : string;
  attribute LC_PROBE476_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011100";
  attribute LC_PROBE476_TYPE : integer;
  attribute LC_PROBE476_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE476_WIDTH : integer;
  attribute LC_PROBE476_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE477_IS_DATA : string;
  attribute LC_PROBE477_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE477_IS_TRIG : string;
  attribute LC_PROBE477_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE477_MU_CNT : integer;
  attribute LC_PROBE477_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE477_PID : string;
  attribute LC_PROBE477_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011101";
  attribute LC_PROBE477_TYPE : integer;
  attribute LC_PROBE477_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE477_WIDTH : integer;
  attribute LC_PROBE477_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE478_IS_DATA : string;
  attribute LC_PROBE478_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE478_IS_TRIG : string;
  attribute LC_PROBE478_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE478_MU_CNT : integer;
  attribute LC_PROBE478_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE478_PID : string;
  attribute LC_PROBE478_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011110";
  attribute LC_PROBE478_TYPE : integer;
  attribute LC_PROBE478_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE478_WIDTH : integer;
  attribute LC_PROBE478_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE479_IS_DATA : string;
  attribute LC_PROBE479_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE479_IS_TRIG : string;
  attribute LC_PROBE479_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE479_MU_CNT : integer;
  attribute LC_PROBE479_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE479_PID : string;
  attribute LC_PROBE479_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111011111";
  attribute LC_PROBE479_TYPE : integer;
  attribute LC_PROBE479_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE479_WIDTH : integer;
  attribute LC_PROBE479_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE47_IS_DATA : string;
  attribute LC_PROBE47_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE47_IS_TRIG : string;
  attribute LC_PROBE47_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE47_MU_CNT : integer;
  attribute LC_PROBE47_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE47_PID : string;
  attribute LC_PROBE47_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000101111";
  attribute LC_PROBE47_TYPE : integer;
  attribute LC_PROBE47_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE47_WIDTH : integer;
  attribute LC_PROBE47_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE480_IS_DATA : string;
  attribute LC_PROBE480_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE480_IS_TRIG : string;
  attribute LC_PROBE480_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE480_MU_CNT : integer;
  attribute LC_PROBE480_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE480_PID : string;
  attribute LC_PROBE480_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100000";
  attribute LC_PROBE480_TYPE : integer;
  attribute LC_PROBE480_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE480_WIDTH : integer;
  attribute LC_PROBE480_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE481_IS_DATA : string;
  attribute LC_PROBE481_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE481_IS_TRIG : string;
  attribute LC_PROBE481_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE481_MU_CNT : integer;
  attribute LC_PROBE481_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE481_PID : string;
  attribute LC_PROBE481_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100001";
  attribute LC_PROBE481_TYPE : integer;
  attribute LC_PROBE481_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE481_WIDTH : integer;
  attribute LC_PROBE481_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE482_IS_DATA : string;
  attribute LC_PROBE482_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE482_IS_TRIG : string;
  attribute LC_PROBE482_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE482_MU_CNT : integer;
  attribute LC_PROBE482_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE482_PID : string;
  attribute LC_PROBE482_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100010";
  attribute LC_PROBE482_TYPE : integer;
  attribute LC_PROBE482_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE482_WIDTH : integer;
  attribute LC_PROBE482_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE483_IS_DATA : string;
  attribute LC_PROBE483_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE483_IS_TRIG : string;
  attribute LC_PROBE483_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE483_MU_CNT : integer;
  attribute LC_PROBE483_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE483_PID : string;
  attribute LC_PROBE483_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100011";
  attribute LC_PROBE483_TYPE : integer;
  attribute LC_PROBE483_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE483_WIDTH : integer;
  attribute LC_PROBE483_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE484_IS_DATA : string;
  attribute LC_PROBE484_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE484_IS_TRIG : string;
  attribute LC_PROBE484_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE484_MU_CNT : integer;
  attribute LC_PROBE484_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE484_PID : string;
  attribute LC_PROBE484_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100100";
  attribute LC_PROBE484_TYPE : integer;
  attribute LC_PROBE484_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE484_WIDTH : integer;
  attribute LC_PROBE484_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE485_IS_DATA : string;
  attribute LC_PROBE485_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE485_IS_TRIG : string;
  attribute LC_PROBE485_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE485_MU_CNT : integer;
  attribute LC_PROBE485_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE485_PID : string;
  attribute LC_PROBE485_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100101";
  attribute LC_PROBE485_TYPE : integer;
  attribute LC_PROBE485_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE485_WIDTH : integer;
  attribute LC_PROBE485_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE486_IS_DATA : string;
  attribute LC_PROBE486_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE486_IS_TRIG : string;
  attribute LC_PROBE486_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE486_MU_CNT : integer;
  attribute LC_PROBE486_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE486_PID : string;
  attribute LC_PROBE486_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100110";
  attribute LC_PROBE486_TYPE : integer;
  attribute LC_PROBE486_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE486_WIDTH : integer;
  attribute LC_PROBE486_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE487_IS_DATA : string;
  attribute LC_PROBE487_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE487_IS_TRIG : string;
  attribute LC_PROBE487_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE487_MU_CNT : integer;
  attribute LC_PROBE487_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE487_PID : string;
  attribute LC_PROBE487_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111100111";
  attribute LC_PROBE487_TYPE : integer;
  attribute LC_PROBE487_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE487_WIDTH : integer;
  attribute LC_PROBE487_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE488_IS_DATA : string;
  attribute LC_PROBE488_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE488_IS_TRIG : string;
  attribute LC_PROBE488_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE488_MU_CNT : integer;
  attribute LC_PROBE488_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE488_PID : string;
  attribute LC_PROBE488_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101000";
  attribute LC_PROBE488_TYPE : integer;
  attribute LC_PROBE488_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE488_WIDTH : integer;
  attribute LC_PROBE488_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE489_IS_DATA : string;
  attribute LC_PROBE489_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE489_IS_TRIG : string;
  attribute LC_PROBE489_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE489_MU_CNT : integer;
  attribute LC_PROBE489_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE489_PID : string;
  attribute LC_PROBE489_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101001";
  attribute LC_PROBE489_TYPE : integer;
  attribute LC_PROBE489_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE489_WIDTH : integer;
  attribute LC_PROBE489_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE48_IS_DATA : string;
  attribute LC_PROBE48_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE48_IS_TRIG : string;
  attribute LC_PROBE48_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE48_MU_CNT : integer;
  attribute LC_PROBE48_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE48_PID : string;
  attribute LC_PROBE48_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110000";
  attribute LC_PROBE48_TYPE : integer;
  attribute LC_PROBE48_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE48_WIDTH : integer;
  attribute LC_PROBE48_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE490_IS_DATA : string;
  attribute LC_PROBE490_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE490_IS_TRIG : string;
  attribute LC_PROBE490_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE490_MU_CNT : integer;
  attribute LC_PROBE490_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE490_PID : string;
  attribute LC_PROBE490_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101010";
  attribute LC_PROBE490_TYPE : integer;
  attribute LC_PROBE490_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE490_WIDTH : integer;
  attribute LC_PROBE490_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE491_IS_DATA : string;
  attribute LC_PROBE491_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE491_IS_TRIG : string;
  attribute LC_PROBE491_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE491_MU_CNT : integer;
  attribute LC_PROBE491_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE491_PID : string;
  attribute LC_PROBE491_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101011";
  attribute LC_PROBE491_TYPE : integer;
  attribute LC_PROBE491_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE491_WIDTH : integer;
  attribute LC_PROBE491_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE492_IS_DATA : string;
  attribute LC_PROBE492_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE492_IS_TRIG : string;
  attribute LC_PROBE492_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE492_MU_CNT : integer;
  attribute LC_PROBE492_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE492_PID : string;
  attribute LC_PROBE492_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101100";
  attribute LC_PROBE492_TYPE : integer;
  attribute LC_PROBE492_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE492_WIDTH : integer;
  attribute LC_PROBE492_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE493_IS_DATA : string;
  attribute LC_PROBE493_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE493_IS_TRIG : string;
  attribute LC_PROBE493_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE493_MU_CNT : integer;
  attribute LC_PROBE493_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE493_PID : string;
  attribute LC_PROBE493_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101101";
  attribute LC_PROBE493_TYPE : integer;
  attribute LC_PROBE493_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE493_WIDTH : integer;
  attribute LC_PROBE493_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE494_IS_DATA : string;
  attribute LC_PROBE494_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE494_IS_TRIG : string;
  attribute LC_PROBE494_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE494_MU_CNT : integer;
  attribute LC_PROBE494_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE494_PID : string;
  attribute LC_PROBE494_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101110";
  attribute LC_PROBE494_TYPE : integer;
  attribute LC_PROBE494_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE494_WIDTH : integer;
  attribute LC_PROBE494_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE495_IS_DATA : string;
  attribute LC_PROBE495_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE495_IS_TRIG : string;
  attribute LC_PROBE495_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE495_MU_CNT : integer;
  attribute LC_PROBE495_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE495_PID : string;
  attribute LC_PROBE495_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111101111";
  attribute LC_PROBE495_TYPE : integer;
  attribute LC_PROBE495_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE495_WIDTH : integer;
  attribute LC_PROBE495_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE496_IS_DATA : string;
  attribute LC_PROBE496_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE496_IS_TRIG : string;
  attribute LC_PROBE496_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE496_MU_CNT : integer;
  attribute LC_PROBE496_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE496_PID : string;
  attribute LC_PROBE496_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110000";
  attribute LC_PROBE496_TYPE : integer;
  attribute LC_PROBE496_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE496_WIDTH : integer;
  attribute LC_PROBE496_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE497_IS_DATA : string;
  attribute LC_PROBE497_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE497_IS_TRIG : string;
  attribute LC_PROBE497_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE497_MU_CNT : integer;
  attribute LC_PROBE497_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE497_PID : string;
  attribute LC_PROBE497_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110001";
  attribute LC_PROBE497_TYPE : integer;
  attribute LC_PROBE497_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE497_WIDTH : integer;
  attribute LC_PROBE497_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE498_IS_DATA : string;
  attribute LC_PROBE498_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE498_IS_TRIG : string;
  attribute LC_PROBE498_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE498_MU_CNT : integer;
  attribute LC_PROBE498_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE498_PID : string;
  attribute LC_PROBE498_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110010";
  attribute LC_PROBE498_TYPE : integer;
  attribute LC_PROBE498_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE498_WIDTH : integer;
  attribute LC_PROBE498_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE499_IS_DATA : string;
  attribute LC_PROBE499_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE499_IS_TRIG : string;
  attribute LC_PROBE499_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE499_MU_CNT : integer;
  attribute LC_PROBE499_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE499_PID : string;
  attribute LC_PROBE499_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110011";
  attribute LC_PROBE499_TYPE : integer;
  attribute LC_PROBE499_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE499_WIDTH : integer;
  attribute LC_PROBE499_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE49_IS_DATA : string;
  attribute LC_PROBE49_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE49_IS_TRIG : string;
  attribute LC_PROBE49_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE49_MU_CNT : integer;
  attribute LC_PROBE49_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE49_PID : string;
  attribute LC_PROBE49_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110001";
  attribute LC_PROBE49_TYPE : integer;
  attribute LC_PROBE49_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE49_WIDTH : integer;
  attribute LC_PROBE49_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE4_IS_DATA : string;
  attribute LC_PROBE4_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE4_IS_TRIG : string;
  attribute LC_PROBE4_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE4_MU_CNT : integer;
  attribute LC_PROBE4_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE4_PID : string;
  attribute LC_PROBE4_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000100";
  attribute LC_PROBE4_TYPE : integer;
  attribute LC_PROBE4_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE4_WIDTH : integer;
  attribute LC_PROBE4_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 32;
  attribute LC_PROBE500_IS_DATA : string;
  attribute LC_PROBE500_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE500_IS_TRIG : string;
  attribute LC_PROBE500_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE500_MU_CNT : integer;
  attribute LC_PROBE500_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE500_PID : string;
  attribute LC_PROBE500_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110100";
  attribute LC_PROBE500_TYPE : integer;
  attribute LC_PROBE500_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE500_WIDTH : integer;
  attribute LC_PROBE500_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE501_IS_DATA : string;
  attribute LC_PROBE501_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE501_IS_TRIG : string;
  attribute LC_PROBE501_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE501_MU_CNT : integer;
  attribute LC_PROBE501_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE501_PID : string;
  attribute LC_PROBE501_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110101";
  attribute LC_PROBE501_TYPE : integer;
  attribute LC_PROBE501_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE501_WIDTH : integer;
  attribute LC_PROBE501_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE502_IS_DATA : string;
  attribute LC_PROBE502_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE502_IS_TRIG : string;
  attribute LC_PROBE502_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE502_MU_CNT : integer;
  attribute LC_PROBE502_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE502_PID : string;
  attribute LC_PROBE502_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110110";
  attribute LC_PROBE502_TYPE : integer;
  attribute LC_PROBE502_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE502_WIDTH : integer;
  attribute LC_PROBE502_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE503_IS_DATA : string;
  attribute LC_PROBE503_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE503_IS_TRIG : string;
  attribute LC_PROBE503_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE503_MU_CNT : integer;
  attribute LC_PROBE503_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE503_PID : string;
  attribute LC_PROBE503_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111110111";
  attribute LC_PROBE503_TYPE : integer;
  attribute LC_PROBE503_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE503_WIDTH : integer;
  attribute LC_PROBE503_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE504_IS_DATA : string;
  attribute LC_PROBE504_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE504_IS_TRIG : string;
  attribute LC_PROBE504_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE504_MU_CNT : integer;
  attribute LC_PROBE504_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE504_PID : string;
  attribute LC_PROBE504_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111000";
  attribute LC_PROBE504_TYPE : integer;
  attribute LC_PROBE504_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE504_WIDTH : integer;
  attribute LC_PROBE504_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE505_IS_DATA : string;
  attribute LC_PROBE505_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE505_IS_TRIG : string;
  attribute LC_PROBE505_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE505_MU_CNT : integer;
  attribute LC_PROBE505_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE505_PID : string;
  attribute LC_PROBE505_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111001";
  attribute LC_PROBE505_TYPE : integer;
  attribute LC_PROBE505_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE505_WIDTH : integer;
  attribute LC_PROBE505_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE506_IS_DATA : string;
  attribute LC_PROBE506_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE506_IS_TRIG : string;
  attribute LC_PROBE506_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE506_MU_CNT : integer;
  attribute LC_PROBE506_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE506_PID : string;
  attribute LC_PROBE506_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111010";
  attribute LC_PROBE506_TYPE : integer;
  attribute LC_PROBE506_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE506_WIDTH : integer;
  attribute LC_PROBE506_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE507_IS_DATA : string;
  attribute LC_PROBE507_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE507_IS_TRIG : string;
  attribute LC_PROBE507_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE507_MU_CNT : integer;
  attribute LC_PROBE507_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE507_PID : string;
  attribute LC_PROBE507_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111011";
  attribute LC_PROBE507_TYPE : integer;
  attribute LC_PROBE507_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE507_WIDTH : integer;
  attribute LC_PROBE507_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE508_IS_DATA : string;
  attribute LC_PROBE508_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE508_IS_TRIG : string;
  attribute LC_PROBE508_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE508_MU_CNT : integer;
  attribute LC_PROBE508_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE508_PID : string;
  attribute LC_PROBE508_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111100";
  attribute LC_PROBE508_TYPE : integer;
  attribute LC_PROBE508_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE508_WIDTH : integer;
  attribute LC_PROBE508_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE509_IS_DATA : string;
  attribute LC_PROBE509_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE509_IS_TRIG : string;
  attribute LC_PROBE509_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE509_MU_CNT : integer;
  attribute LC_PROBE509_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE509_PID : string;
  attribute LC_PROBE509_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111101";
  attribute LC_PROBE509_TYPE : integer;
  attribute LC_PROBE509_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE509_WIDTH : integer;
  attribute LC_PROBE509_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE50_IS_DATA : string;
  attribute LC_PROBE50_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE50_IS_TRIG : string;
  attribute LC_PROBE50_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE50_MU_CNT : integer;
  attribute LC_PROBE50_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE50_PID : string;
  attribute LC_PROBE50_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110010";
  attribute LC_PROBE50_TYPE : integer;
  attribute LC_PROBE50_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE50_WIDTH : integer;
  attribute LC_PROBE50_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE510_IS_DATA : string;
  attribute LC_PROBE510_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE510_IS_TRIG : string;
  attribute LC_PROBE510_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE510_MU_CNT : integer;
  attribute LC_PROBE510_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE510_PID : string;
  attribute LC_PROBE510_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111110";
  attribute LC_PROBE510_TYPE : integer;
  attribute LC_PROBE510_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE510_WIDTH : integer;
  attribute LC_PROBE510_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE511_IS_DATA : string;
  attribute LC_PROBE511_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE511_IS_TRIG : string;
  attribute LC_PROBE511_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE511_MU_CNT : integer;
  attribute LC_PROBE511_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE511_PID : string;
  attribute LC_PROBE511_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000111111111";
  attribute LC_PROBE511_TYPE : integer;
  attribute LC_PROBE511_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE511_WIDTH : integer;
  attribute LC_PROBE511_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE512_IS_DATA : string;
  attribute LC_PROBE512_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE512_IS_TRIG : string;
  attribute LC_PROBE512_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE512_MU_CNT : integer;
  attribute LC_PROBE512_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE512_PID : string;
  attribute LC_PROBE512_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000000";
  attribute LC_PROBE512_TYPE : integer;
  attribute LC_PROBE512_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE512_WIDTH : integer;
  attribute LC_PROBE512_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE513_IS_DATA : string;
  attribute LC_PROBE513_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE513_IS_TRIG : string;
  attribute LC_PROBE513_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE513_MU_CNT : integer;
  attribute LC_PROBE513_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE513_PID : string;
  attribute LC_PROBE513_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000001";
  attribute LC_PROBE513_TYPE : integer;
  attribute LC_PROBE513_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE513_WIDTH : integer;
  attribute LC_PROBE513_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE514_IS_DATA : string;
  attribute LC_PROBE514_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE514_IS_TRIG : string;
  attribute LC_PROBE514_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE514_MU_CNT : integer;
  attribute LC_PROBE514_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE514_PID : string;
  attribute LC_PROBE514_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000010";
  attribute LC_PROBE514_TYPE : integer;
  attribute LC_PROBE514_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE514_WIDTH : integer;
  attribute LC_PROBE514_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE515_IS_DATA : string;
  attribute LC_PROBE515_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE515_IS_TRIG : string;
  attribute LC_PROBE515_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE515_MU_CNT : integer;
  attribute LC_PROBE515_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE515_PID : string;
  attribute LC_PROBE515_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000011";
  attribute LC_PROBE515_TYPE : integer;
  attribute LC_PROBE515_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE515_WIDTH : integer;
  attribute LC_PROBE515_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE516_IS_DATA : string;
  attribute LC_PROBE516_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE516_IS_TRIG : string;
  attribute LC_PROBE516_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE516_MU_CNT : integer;
  attribute LC_PROBE516_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE516_PID : string;
  attribute LC_PROBE516_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000100";
  attribute LC_PROBE516_TYPE : integer;
  attribute LC_PROBE516_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE516_WIDTH : integer;
  attribute LC_PROBE516_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE517_IS_DATA : string;
  attribute LC_PROBE517_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE517_IS_TRIG : string;
  attribute LC_PROBE517_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE517_MU_CNT : integer;
  attribute LC_PROBE517_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE517_PID : string;
  attribute LC_PROBE517_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000101";
  attribute LC_PROBE517_TYPE : integer;
  attribute LC_PROBE517_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE517_WIDTH : integer;
  attribute LC_PROBE517_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE518_IS_DATA : string;
  attribute LC_PROBE518_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE518_IS_TRIG : string;
  attribute LC_PROBE518_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE518_MU_CNT : integer;
  attribute LC_PROBE518_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE518_PID : string;
  attribute LC_PROBE518_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000110";
  attribute LC_PROBE518_TYPE : integer;
  attribute LC_PROBE518_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE518_WIDTH : integer;
  attribute LC_PROBE518_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE519_IS_DATA : string;
  attribute LC_PROBE519_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE519_IS_TRIG : string;
  attribute LC_PROBE519_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE519_MU_CNT : integer;
  attribute LC_PROBE519_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE519_PID : string;
  attribute LC_PROBE519_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000000111";
  attribute LC_PROBE519_TYPE : integer;
  attribute LC_PROBE519_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE519_WIDTH : integer;
  attribute LC_PROBE519_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE51_IS_DATA : string;
  attribute LC_PROBE51_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE51_IS_TRIG : string;
  attribute LC_PROBE51_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE51_MU_CNT : integer;
  attribute LC_PROBE51_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE51_PID : string;
  attribute LC_PROBE51_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110011";
  attribute LC_PROBE51_TYPE : integer;
  attribute LC_PROBE51_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE51_WIDTH : integer;
  attribute LC_PROBE51_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE520_IS_DATA : string;
  attribute LC_PROBE520_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE520_IS_TRIG : string;
  attribute LC_PROBE520_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE520_MU_CNT : integer;
  attribute LC_PROBE520_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE520_PID : string;
  attribute LC_PROBE520_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001000";
  attribute LC_PROBE520_TYPE : integer;
  attribute LC_PROBE520_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE520_WIDTH : integer;
  attribute LC_PROBE520_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE521_IS_DATA : string;
  attribute LC_PROBE521_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE521_IS_TRIG : string;
  attribute LC_PROBE521_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE521_MU_CNT : integer;
  attribute LC_PROBE521_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE521_PID : string;
  attribute LC_PROBE521_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001001";
  attribute LC_PROBE521_TYPE : integer;
  attribute LC_PROBE521_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE521_WIDTH : integer;
  attribute LC_PROBE521_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE522_IS_DATA : string;
  attribute LC_PROBE522_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE522_IS_TRIG : string;
  attribute LC_PROBE522_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE522_MU_CNT : integer;
  attribute LC_PROBE522_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE522_PID : string;
  attribute LC_PROBE522_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001010";
  attribute LC_PROBE522_TYPE : integer;
  attribute LC_PROBE522_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE522_WIDTH : integer;
  attribute LC_PROBE522_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE523_IS_DATA : string;
  attribute LC_PROBE523_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE523_IS_TRIG : string;
  attribute LC_PROBE523_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE523_MU_CNT : integer;
  attribute LC_PROBE523_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE523_PID : string;
  attribute LC_PROBE523_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001011";
  attribute LC_PROBE523_TYPE : integer;
  attribute LC_PROBE523_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE523_WIDTH : integer;
  attribute LC_PROBE523_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE524_IS_DATA : string;
  attribute LC_PROBE524_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE524_IS_TRIG : string;
  attribute LC_PROBE524_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE524_MU_CNT : integer;
  attribute LC_PROBE524_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE524_PID : string;
  attribute LC_PROBE524_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001100";
  attribute LC_PROBE524_TYPE : integer;
  attribute LC_PROBE524_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE524_WIDTH : integer;
  attribute LC_PROBE524_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE525_IS_DATA : string;
  attribute LC_PROBE525_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE525_IS_TRIG : string;
  attribute LC_PROBE525_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE525_MU_CNT : integer;
  attribute LC_PROBE525_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE525_PID : string;
  attribute LC_PROBE525_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001101";
  attribute LC_PROBE525_TYPE : integer;
  attribute LC_PROBE525_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE525_WIDTH : integer;
  attribute LC_PROBE525_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE526_IS_DATA : string;
  attribute LC_PROBE526_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE526_IS_TRIG : string;
  attribute LC_PROBE526_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE526_MU_CNT : integer;
  attribute LC_PROBE526_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE526_PID : string;
  attribute LC_PROBE526_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001110";
  attribute LC_PROBE526_TYPE : integer;
  attribute LC_PROBE526_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE526_WIDTH : integer;
  attribute LC_PROBE526_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE527_IS_DATA : string;
  attribute LC_PROBE527_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE527_IS_TRIG : string;
  attribute LC_PROBE527_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE527_MU_CNT : integer;
  attribute LC_PROBE527_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE527_PID : string;
  attribute LC_PROBE527_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000001111";
  attribute LC_PROBE527_TYPE : integer;
  attribute LC_PROBE527_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE527_WIDTH : integer;
  attribute LC_PROBE527_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE528_IS_DATA : string;
  attribute LC_PROBE528_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE528_IS_TRIG : string;
  attribute LC_PROBE528_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE528_MU_CNT : integer;
  attribute LC_PROBE528_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE528_PID : string;
  attribute LC_PROBE528_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010000";
  attribute LC_PROBE528_TYPE : integer;
  attribute LC_PROBE528_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE528_WIDTH : integer;
  attribute LC_PROBE528_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE529_IS_DATA : string;
  attribute LC_PROBE529_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE529_IS_TRIG : string;
  attribute LC_PROBE529_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE529_MU_CNT : integer;
  attribute LC_PROBE529_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE529_PID : string;
  attribute LC_PROBE529_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010001";
  attribute LC_PROBE529_TYPE : integer;
  attribute LC_PROBE529_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE529_WIDTH : integer;
  attribute LC_PROBE529_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE52_IS_DATA : string;
  attribute LC_PROBE52_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE52_IS_TRIG : string;
  attribute LC_PROBE52_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE52_MU_CNT : integer;
  attribute LC_PROBE52_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE52_PID : string;
  attribute LC_PROBE52_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110100";
  attribute LC_PROBE52_TYPE : integer;
  attribute LC_PROBE52_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE52_WIDTH : integer;
  attribute LC_PROBE52_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE530_IS_DATA : string;
  attribute LC_PROBE530_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE530_IS_TRIG : string;
  attribute LC_PROBE530_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE530_MU_CNT : integer;
  attribute LC_PROBE530_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE530_PID : string;
  attribute LC_PROBE530_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010010";
  attribute LC_PROBE530_TYPE : integer;
  attribute LC_PROBE530_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE530_WIDTH : integer;
  attribute LC_PROBE530_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE531_IS_DATA : string;
  attribute LC_PROBE531_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE531_IS_TRIG : string;
  attribute LC_PROBE531_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE531_MU_CNT : integer;
  attribute LC_PROBE531_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE531_PID : string;
  attribute LC_PROBE531_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010011";
  attribute LC_PROBE531_TYPE : integer;
  attribute LC_PROBE531_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE531_WIDTH : integer;
  attribute LC_PROBE531_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE532_IS_DATA : string;
  attribute LC_PROBE532_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE532_IS_TRIG : string;
  attribute LC_PROBE532_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE532_MU_CNT : integer;
  attribute LC_PROBE532_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE532_PID : string;
  attribute LC_PROBE532_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010100";
  attribute LC_PROBE532_TYPE : integer;
  attribute LC_PROBE532_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE532_WIDTH : integer;
  attribute LC_PROBE532_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE533_IS_DATA : string;
  attribute LC_PROBE533_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE533_IS_TRIG : string;
  attribute LC_PROBE533_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE533_MU_CNT : integer;
  attribute LC_PROBE533_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE533_PID : string;
  attribute LC_PROBE533_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010101";
  attribute LC_PROBE533_TYPE : integer;
  attribute LC_PROBE533_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE533_WIDTH : integer;
  attribute LC_PROBE533_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE534_IS_DATA : string;
  attribute LC_PROBE534_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE534_IS_TRIG : string;
  attribute LC_PROBE534_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE534_MU_CNT : integer;
  attribute LC_PROBE534_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE534_PID : string;
  attribute LC_PROBE534_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010110";
  attribute LC_PROBE534_TYPE : integer;
  attribute LC_PROBE534_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE534_WIDTH : integer;
  attribute LC_PROBE534_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE535_IS_DATA : string;
  attribute LC_PROBE535_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE535_IS_TRIG : string;
  attribute LC_PROBE535_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE535_MU_CNT : integer;
  attribute LC_PROBE535_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE535_PID : string;
  attribute LC_PROBE535_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000010111";
  attribute LC_PROBE535_TYPE : integer;
  attribute LC_PROBE535_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE535_WIDTH : integer;
  attribute LC_PROBE535_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE536_IS_DATA : string;
  attribute LC_PROBE536_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE536_IS_TRIG : string;
  attribute LC_PROBE536_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE536_MU_CNT : integer;
  attribute LC_PROBE536_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE536_PID : string;
  attribute LC_PROBE536_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011000";
  attribute LC_PROBE536_TYPE : integer;
  attribute LC_PROBE536_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE536_WIDTH : integer;
  attribute LC_PROBE536_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE537_IS_DATA : string;
  attribute LC_PROBE537_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE537_IS_TRIG : string;
  attribute LC_PROBE537_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE537_MU_CNT : integer;
  attribute LC_PROBE537_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE537_PID : string;
  attribute LC_PROBE537_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011001";
  attribute LC_PROBE537_TYPE : integer;
  attribute LC_PROBE537_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE537_WIDTH : integer;
  attribute LC_PROBE537_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE538_IS_DATA : string;
  attribute LC_PROBE538_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE538_IS_TRIG : string;
  attribute LC_PROBE538_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE538_MU_CNT : integer;
  attribute LC_PROBE538_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE538_PID : string;
  attribute LC_PROBE538_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011010";
  attribute LC_PROBE538_TYPE : integer;
  attribute LC_PROBE538_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE538_WIDTH : integer;
  attribute LC_PROBE538_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE539_IS_DATA : string;
  attribute LC_PROBE539_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE539_IS_TRIG : string;
  attribute LC_PROBE539_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE539_MU_CNT : integer;
  attribute LC_PROBE539_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE539_PID : string;
  attribute LC_PROBE539_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011011";
  attribute LC_PROBE539_TYPE : integer;
  attribute LC_PROBE539_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE539_WIDTH : integer;
  attribute LC_PROBE539_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE53_IS_DATA : string;
  attribute LC_PROBE53_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE53_IS_TRIG : string;
  attribute LC_PROBE53_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE53_MU_CNT : integer;
  attribute LC_PROBE53_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE53_PID : string;
  attribute LC_PROBE53_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110101";
  attribute LC_PROBE53_TYPE : integer;
  attribute LC_PROBE53_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE53_WIDTH : integer;
  attribute LC_PROBE53_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE540_IS_DATA : string;
  attribute LC_PROBE540_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE540_IS_TRIG : string;
  attribute LC_PROBE540_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE540_MU_CNT : integer;
  attribute LC_PROBE540_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE540_PID : string;
  attribute LC_PROBE540_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011100";
  attribute LC_PROBE540_TYPE : integer;
  attribute LC_PROBE540_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE540_WIDTH : integer;
  attribute LC_PROBE540_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE541_IS_DATA : string;
  attribute LC_PROBE541_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE541_IS_TRIG : string;
  attribute LC_PROBE541_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE541_MU_CNT : integer;
  attribute LC_PROBE541_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE541_PID : string;
  attribute LC_PROBE541_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011101";
  attribute LC_PROBE541_TYPE : integer;
  attribute LC_PROBE541_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE541_WIDTH : integer;
  attribute LC_PROBE541_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE542_IS_DATA : string;
  attribute LC_PROBE542_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE542_IS_TRIG : string;
  attribute LC_PROBE542_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE542_MU_CNT : integer;
  attribute LC_PROBE542_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE542_PID : string;
  attribute LC_PROBE542_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011110";
  attribute LC_PROBE542_TYPE : integer;
  attribute LC_PROBE542_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE542_WIDTH : integer;
  attribute LC_PROBE542_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE543_IS_DATA : string;
  attribute LC_PROBE543_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE543_IS_TRIG : string;
  attribute LC_PROBE543_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE543_MU_CNT : integer;
  attribute LC_PROBE543_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE543_PID : string;
  attribute LC_PROBE543_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000011111";
  attribute LC_PROBE543_TYPE : integer;
  attribute LC_PROBE543_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE543_WIDTH : integer;
  attribute LC_PROBE543_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE544_IS_DATA : string;
  attribute LC_PROBE544_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE544_IS_TRIG : string;
  attribute LC_PROBE544_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE544_MU_CNT : integer;
  attribute LC_PROBE544_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE544_PID : string;
  attribute LC_PROBE544_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100000";
  attribute LC_PROBE544_TYPE : integer;
  attribute LC_PROBE544_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE544_WIDTH : integer;
  attribute LC_PROBE544_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE545_IS_DATA : string;
  attribute LC_PROBE545_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE545_IS_TRIG : string;
  attribute LC_PROBE545_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE545_MU_CNT : integer;
  attribute LC_PROBE545_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE545_PID : string;
  attribute LC_PROBE545_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100001";
  attribute LC_PROBE545_TYPE : integer;
  attribute LC_PROBE545_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE545_WIDTH : integer;
  attribute LC_PROBE545_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE546_IS_DATA : string;
  attribute LC_PROBE546_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE546_IS_TRIG : string;
  attribute LC_PROBE546_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE546_MU_CNT : integer;
  attribute LC_PROBE546_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE546_PID : string;
  attribute LC_PROBE546_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100010";
  attribute LC_PROBE546_TYPE : integer;
  attribute LC_PROBE546_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE546_WIDTH : integer;
  attribute LC_PROBE546_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE547_IS_DATA : string;
  attribute LC_PROBE547_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE547_IS_TRIG : string;
  attribute LC_PROBE547_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE547_MU_CNT : integer;
  attribute LC_PROBE547_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE547_PID : string;
  attribute LC_PROBE547_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100011";
  attribute LC_PROBE547_TYPE : integer;
  attribute LC_PROBE547_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE547_WIDTH : integer;
  attribute LC_PROBE547_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE548_IS_DATA : string;
  attribute LC_PROBE548_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE548_IS_TRIG : string;
  attribute LC_PROBE548_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE548_MU_CNT : integer;
  attribute LC_PROBE548_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE548_PID : string;
  attribute LC_PROBE548_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100100";
  attribute LC_PROBE548_TYPE : integer;
  attribute LC_PROBE548_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE548_WIDTH : integer;
  attribute LC_PROBE548_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE549_IS_DATA : string;
  attribute LC_PROBE549_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE549_IS_TRIG : string;
  attribute LC_PROBE549_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE549_MU_CNT : integer;
  attribute LC_PROBE549_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE549_PID : string;
  attribute LC_PROBE549_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100101";
  attribute LC_PROBE549_TYPE : integer;
  attribute LC_PROBE549_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE549_WIDTH : integer;
  attribute LC_PROBE549_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE54_IS_DATA : string;
  attribute LC_PROBE54_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE54_IS_TRIG : string;
  attribute LC_PROBE54_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE54_MU_CNT : integer;
  attribute LC_PROBE54_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE54_PID : string;
  attribute LC_PROBE54_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110110";
  attribute LC_PROBE54_TYPE : integer;
  attribute LC_PROBE54_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE54_WIDTH : integer;
  attribute LC_PROBE54_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE550_IS_DATA : string;
  attribute LC_PROBE550_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE550_IS_TRIG : string;
  attribute LC_PROBE550_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE550_MU_CNT : integer;
  attribute LC_PROBE550_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE550_PID : string;
  attribute LC_PROBE550_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100110";
  attribute LC_PROBE550_TYPE : integer;
  attribute LC_PROBE550_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE550_WIDTH : integer;
  attribute LC_PROBE550_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE551_IS_DATA : string;
  attribute LC_PROBE551_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE551_IS_TRIG : string;
  attribute LC_PROBE551_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE551_MU_CNT : integer;
  attribute LC_PROBE551_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE551_PID : string;
  attribute LC_PROBE551_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000100111";
  attribute LC_PROBE551_TYPE : integer;
  attribute LC_PROBE551_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE551_WIDTH : integer;
  attribute LC_PROBE551_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE552_IS_DATA : string;
  attribute LC_PROBE552_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE552_IS_TRIG : string;
  attribute LC_PROBE552_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE552_MU_CNT : integer;
  attribute LC_PROBE552_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE552_PID : string;
  attribute LC_PROBE552_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101000";
  attribute LC_PROBE552_TYPE : integer;
  attribute LC_PROBE552_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE552_WIDTH : integer;
  attribute LC_PROBE552_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE553_IS_DATA : string;
  attribute LC_PROBE553_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE553_IS_TRIG : string;
  attribute LC_PROBE553_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE553_MU_CNT : integer;
  attribute LC_PROBE553_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE553_PID : string;
  attribute LC_PROBE553_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101001";
  attribute LC_PROBE553_TYPE : integer;
  attribute LC_PROBE553_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE553_WIDTH : integer;
  attribute LC_PROBE553_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE554_IS_DATA : string;
  attribute LC_PROBE554_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE554_IS_TRIG : string;
  attribute LC_PROBE554_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE554_MU_CNT : integer;
  attribute LC_PROBE554_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE554_PID : string;
  attribute LC_PROBE554_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101010";
  attribute LC_PROBE554_TYPE : integer;
  attribute LC_PROBE554_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE554_WIDTH : integer;
  attribute LC_PROBE554_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE555_IS_DATA : string;
  attribute LC_PROBE555_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE555_IS_TRIG : string;
  attribute LC_PROBE555_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE555_MU_CNT : integer;
  attribute LC_PROBE555_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE555_PID : string;
  attribute LC_PROBE555_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101011";
  attribute LC_PROBE555_TYPE : integer;
  attribute LC_PROBE555_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE555_WIDTH : integer;
  attribute LC_PROBE555_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE556_IS_DATA : string;
  attribute LC_PROBE556_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE556_IS_TRIG : string;
  attribute LC_PROBE556_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE556_MU_CNT : integer;
  attribute LC_PROBE556_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE556_PID : string;
  attribute LC_PROBE556_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101100";
  attribute LC_PROBE556_TYPE : integer;
  attribute LC_PROBE556_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE556_WIDTH : integer;
  attribute LC_PROBE556_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE557_IS_DATA : string;
  attribute LC_PROBE557_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE557_IS_TRIG : string;
  attribute LC_PROBE557_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE557_MU_CNT : integer;
  attribute LC_PROBE557_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE557_PID : string;
  attribute LC_PROBE557_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101101";
  attribute LC_PROBE557_TYPE : integer;
  attribute LC_PROBE557_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE557_WIDTH : integer;
  attribute LC_PROBE557_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE558_IS_DATA : string;
  attribute LC_PROBE558_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE558_IS_TRIG : string;
  attribute LC_PROBE558_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE558_MU_CNT : integer;
  attribute LC_PROBE558_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE558_PID : string;
  attribute LC_PROBE558_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101110";
  attribute LC_PROBE558_TYPE : integer;
  attribute LC_PROBE558_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE558_WIDTH : integer;
  attribute LC_PROBE558_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE559_IS_DATA : string;
  attribute LC_PROBE559_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE559_IS_TRIG : string;
  attribute LC_PROBE559_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE559_MU_CNT : integer;
  attribute LC_PROBE559_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE559_PID : string;
  attribute LC_PROBE559_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000101111";
  attribute LC_PROBE559_TYPE : integer;
  attribute LC_PROBE559_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE559_WIDTH : integer;
  attribute LC_PROBE559_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE55_IS_DATA : string;
  attribute LC_PROBE55_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE55_IS_TRIG : string;
  attribute LC_PROBE55_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE55_MU_CNT : integer;
  attribute LC_PROBE55_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE55_PID : string;
  attribute LC_PROBE55_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000110111";
  attribute LC_PROBE55_TYPE : integer;
  attribute LC_PROBE55_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE55_WIDTH : integer;
  attribute LC_PROBE55_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE560_IS_DATA : string;
  attribute LC_PROBE560_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE560_IS_TRIG : string;
  attribute LC_PROBE560_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE560_MU_CNT : integer;
  attribute LC_PROBE560_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE560_PID : string;
  attribute LC_PROBE560_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110000";
  attribute LC_PROBE560_TYPE : integer;
  attribute LC_PROBE560_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE560_WIDTH : integer;
  attribute LC_PROBE560_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE561_IS_DATA : string;
  attribute LC_PROBE561_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE561_IS_TRIG : string;
  attribute LC_PROBE561_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE561_MU_CNT : integer;
  attribute LC_PROBE561_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE561_PID : string;
  attribute LC_PROBE561_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110001";
  attribute LC_PROBE561_TYPE : integer;
  attribute LC_PROBE561_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE561_WIDTH : integer;
  attribute LC_PROBE561_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE562_IS_DATA : string;
  attribute LC_PROBE562_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE562_IS_TRIG : string;
  attribute LC_PROBE562_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE562_MU_CNT : integer;
  attribute LC_PROBE562_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE562_PID : string;
  attribute LC_PROBE562_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110010";
  attribute LC_PROBE562_TYPE : integer;
  attribute LC_PROBE562_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE562_WIDTH : integer;
  attribute LC_PROBE562_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE563_IS_DATA : string;
  attribute LC_PROBE563_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE563_IS_TRIG : string;
  attribute LC_PROBE563_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE563_MU_CNT : integer;
  attribute LC_PROBE563_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE563_PID : string;
  attribute LC_PROBE563_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110011";
  attribute LC_PROBE563_TYPE : integer;
  attribute LC_PROBE563_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE563_WIDTH : integer;
  attribute LC_PROBE563_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE564_IS_DATA : string;
  attribute LC_PROBE564_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE564_IS_TRIG : string;
  attribute LC_PROBE564_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE564_MU_CNT : integer;
  attribute LC_PROBE564_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE564_PID : string;
  attribute LC_PROBE564_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110100";
  attribute LC_PROBE564_TYPE : integer;
  attribute LC_PROBE564_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE564_WIDTH : integer;
  attribute LC_PROBE564_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE565_IS_DATA : string;
  attribute LC_PROBE565_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE565_IS_TRIG : string;
  attribute LC_PROBE565_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE565_MU_CNT : integer;
  attribute LC_PROBE565_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE565_PID : string;
  attribute LC_PROBE565_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110101";
  attribute LC_PROBE565_TYPE : integer;
  attribute LC_PROBE565_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE565_WIDTH : integer;
  attribute LC_PROBE565_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE566_IS_DATA : string;
  attribute LC_PROBE566_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE566_IS_TRIG : string;
  attribute LC_PROBE566_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE566_MU_CNT : integer;
  attribute LC_PROBE566_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE566_PID : string;
  attribute LC_PROBE566_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110110";
  attribute LC_PROBE566_TYPE : integer;
  attribute LC_PROBE566_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE566_WIDTH : integer;
  attribute LC_PROBE566_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE567_IS_DATA : string;
  attribute LC_PROBE567_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE567_IS_TRIG : string;
  attribute LC_PROBE567_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE567_MU_CNT : integer;
  attribute LC_PROBE567_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE567_PID : string;
  attribute LC_PROBE567_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000110111";
  attribute LC_PROBE567_TYPE : integer;
  attribute LC_PROBE567_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE567_WIDTH : integer;
  attribute LC_PROBE567_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE568_IS_DATA : string;
  attribute LC_PROBE568_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE568_IS_TRIG : string;
  attribute LC_PROBE568_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE568_MU_CNT : integer;
  attribute LC_PROBE568_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE568_PID : string;
  attribute LC_PROBE568_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111000";
  attribute LC_PROBE568_TYPE : integer;
  attribute LC_PROBE568_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE568_WIDTH : integer;
  attribute LC_PROBE568_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE569_IS_DATA : string;
  attribute LC_PROBE569_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE569_IS_TRIG : string;
  attribute LC_PROBE569_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE569_MU_CNT : integer;
  attribute LC_PROBE569_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE569_PID : string;
  attribute LC_PROBE569_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111001";
  attribute LC_PROBE569_TYPE : integer;
  attribute LC_PROBE569_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE569_WIDTH : integer;
  attribute LC_PROBE569_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE56_IS_DATA : string;
  attribute LC_PROBE56_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE56_IS_TRIG : string;
  attribute LC_PROBE56_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE56_MU_CNT : integer;
  attribute LC_PROBE56_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE56_PID : string;
  attribute LC_PROBE56_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111000";
  attribute LC_PROBE56_TYPE : integer;
  attribute LC_PROBE56_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE56_WIDTH : integer;
  attribute LC_PROBE56_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE570_IS_DATA : string;
  attribute LC_PROBE570_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE570_IS_TRIG : string;
  attribute LC_PROBE570_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE570_MU_CNT : integer;
  attribute LC_PROBE570_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE570_PID : string;
  attribute LC_PROBE570_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111010";
  attribute LC_PROBE570_TYPE : integer;
  attribute LC_PROBE570_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE570_WIDTH : integer;
  attribute LC_PROBE570_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE571_IS_DATA : string;
  attribute LC_PROBE571_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE571_IS_TRIG : string;
  attribute LC_PROBE571_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE571_MU_CNT : integer;
  attribute LC_PROBE571_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE571_PID : string;
  attribute LC_PROBE571_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111011";
  attribute LC_PROBE571_TYPE : integer;
  attribute LC_PROBE571_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE571_WIDTH : integer;
  attribute LC_PROBE571_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE572_IS_DATA : string;
  attribute LC_PROBE572_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE572_IS_TRIG : string;
  attribute LC_PROBE572_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE572_MU_CNT : integer;
  attribute LC_PROBE572_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE572_PID : string;
  attribute LC_PROBE572_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111100";
  attribute LC_PROBE572_TYPE : integer;
  attribute LC_PROBE572_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE572_WIDTH : integer;
  attribute LC_PROBE572_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE573_IS_DATA : string;
  attribute LC_PROBE573_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE573_IS_TRIG : string;
  attribute LC_PROBE573_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE573_MU_CNT : integer;
  attribute LC_PROBE573_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE573_PID : string;
  attribute LC_PROBE573_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111101";
  attribute LC_PROBE573_TYPE : integer;
  attribute LC_PROBE573_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE573_WIDTH : integer;
  attribute LC_PROBE573_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE574_IS_DATA : string;
  attribute LC_PROBE574_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE574_IS_TRIG : string;
  attribute LC_PROBE574_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE574_MU_CNT : integer;
  attribute LC_PROBE574_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE574_PID : string;
  attribute LC_PROBE574_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111110";
  attribute LC_PROBE574_TYPE : integer;
  attribute LC_PROBE574_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE574_WIDTH : integer;
  attribute LC_PROBE574_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE575_IS_DATA : string;
  attribute LC_PROBE575_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE575_IS_TRIG : string;
  attribute LC_PROBE575_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE575_MU_CNT : integer;
  attribute LC_PROBE575_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE575_PID : string;
  attribute LC_PROBE575_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001000111111";
  attribute LC_PROBE575_TYPE : integer;
  attribute LC_PROBE575_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE575_WIDTH : integer;
  attribute LC_PROBE575_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE576_IS_DATA : string;
  attribute LC_PROBE576_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE576_IS_TRIG : string;
  attribute LC_PROBE576_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE576_MU_CNT : integer;
  attribute LC_PROBE576_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE576_PID : string;
  attribute LC_PROBE576_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000000";
  attribute LC_PROBE576_TYPE : integer;
  attribute LC_PROBE576_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE576_WIDTH : integer;
  attribute LC_PROBE576_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE577_IS_DATA : string;
  attribute LC_PROBE577_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE577_IS_TRIG : string;
  attribute LC_PROBE577_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE577_MU_CNT : integer;
  attribute LC_PROBE577_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE577_PID : string;
  attribute LC_PROBE577_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000001";
  attribute LC_PROBE577_TYPE : integer;
  attribute LC_PROBE577_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE577_WIDTH : integer;
  attribute LC_PROBE577_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE578_IS_DATA : string;
  attribute LC_PROBE578_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE578_IS_TRIG : string;
  attribute LC_PROBE578_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE578_MU_CNT : integer;
  attribute LC_PROBE578_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE578_PID : string;
  attribute LC_PROBE578_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000010";
  attribute LC_PROBE578_TYPE : integer;
  attribute LC_PROBE578_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE578_WIDTH : integer;
  attribute LC_PROBE578_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE579_IS_DATA : string;
  attribute LC_PROBE579_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE579_IS_TRIG : string;
  attribute LC_PROBE579_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE579_MU_CNT : integer;
  attribute LC_PROBE579_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE579_PID : string;
  attribute LC_PROBE579_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000011";
  attribute LC_PROBE579_TYPE : integer;
  attribute LC_PROBE579_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE579_WIDTH : integer;
  attribute LC_PROBE579_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE57_IS_DATA : string;
  attribute LC_PROBE57_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE57_IS_TRIG : string;
  attribute LC_PROBE57_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE57_MU_CNT : integer;
  attribute LC_PROBE57_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE57_PID : string;
  attribute LC_PROBE57_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111001";
  attribute LC_PROBE57_TYPE : integer;
  attribute LC_PROBE57_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE57_WIDTH : integer;
  attribute LC_PROBE57_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE580_IS_DATA : string;
  attribute LC_PROBE580_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE580_IS_TRIG : string;
  attribute LC_PROBE580_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE580_MU_CNT : integer;
  attribute LC_PROBE580_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE580_PID : string;
  attribute LC_PROBE580_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000100";
  attribute LC_PROBE580_TYPE : integer;
  attribute LC_PROBE580_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE580_WIDTH : integer;
  attribute LC_PROBE580_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE581_IS_DATA : string;
  attribute LC_PROBE581_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE581_IS_TRIG : string;
  attribute LC_PROBE581_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE581_MU_CNT : integer;
  attribute LC_PROBE581_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE581_PID : string;
  attribute LC_PROBE581_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000101";
  attribute LC_PROBE581_TYPE : integer;
  attribute LC_PROBE581_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE581_WIDTH : integer;
  attribute LC_PROBE581_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE582_IS_DATA : string;
  attribute LC_PROBE582_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE582_IS_TRIG : string;
  attribute LC_PROBE582_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE582_MU_CNT : integer;
  attribute LC_PROBE582_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE582_PID : string;
  attribute LC_PROBE582_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000110";
  attribute LC_PROBE582_TYPE : integer;
  attribute LC_PROBE582_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE582_WIDTH : integer;
  attribute LC_PROBE582_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE583_IS_DATA : string;
  attribute LC_PROBE583_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE583_IS_TRIG : string;
  attribute LC_PROBE583_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE583_MU_CNT : integer;
  attribute LC_PROBE583_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE583_PID : string;
  attribute LC_PROBE583_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001000111";
  attribute LC_PROBE583_TYPE : integer;
  attribute LC_PROBE583_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE583_WIDTH : integer;
  attribute LC_PROBE583_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE584_IS_DATA : string;
  attribute LC_PROBE584_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE584_IS_TRIG : string;
  attribute LC_PROBE584_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE584_MU_CNT : integer;
  attribute LC_PROBE584_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE584_PID : string;
  attribute LC_PROBE584_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001000";
  attribute LC_PROBE584_TYPE : integer;
  attribute LC_PROBE584_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE584_WIDTH : integer;
  attribute LC_PROBE584_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE585_IS_DATA : string;
  attribute LC_PROBE585_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE585_IS_TRIG : string;
  attribute LC_PROBE585_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE585_MU_CNT : integer;
  attribute LC_PROBE585_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE585_PID : string;
  attribute LC_PROBE585_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001001";
  attribute LC_PROBE585_TYPE : integer;
  attribute LC_PROBE585_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE585_WIDTH : integer;
  attribute LC_PROBE585_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE586_IS_DATA : string;
  attribute LC_PROBE586_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE586_IS_TRIG : string;
  attribute LC_PROBE586_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE586_MU_CNT : integer;
  attribute LC_PROBE586_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE586_PID : string;
  attribute LC_PROBE586_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001010";
  attribute LC_PROBE586_TYPE : integer;
  attribute LC_PROBE586_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE586_WIDTH : integer;
  attribute LC_PROBE586_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE587_IS_DATA : string;
  attribute LC_PROBE587_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE587_IS_TRIG : string;
  attribute LC_PROBE587_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE587_MU_CNT : integer;
  attribute LC_PROBE587_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE587_PID : string;
  attribute LC_PROBE587_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001011";
  attribute LC_PROBE587_TYPE : integer;
  attribute LC_PROBE587_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE587_WIDTH : integer;
  attribute LC_PROBE587_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE588_IS_DATA : string;
  attribute LC_PROBE588_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE588_IS_TRIG : string;
  attribute LC_PROBE588_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE588_MU_CNT : integer;
  attribute LC_PROBE588_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE588_PID : string;
  attribute LC_PROBE588_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001100";
  attribute LC_PROBE588_TYPE : integer;
  attribute LC_PROBE588_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE588_WIDTH : integer;
  attribute LC_PROBE588_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE589_IS_DATA : string;
  attribute LC_PROBE589_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE589_IS_TRIG : string;
  attribute LC_PROBE589_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE589_MU_CNT : integer;
  attribute LC_PROBE589_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE589_PID : string;
  attribute LC_PROBE589_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001101";
  attribute LC_PROBE589_TYPE : integer;
  attribute LC_PROBE589_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE589_WIDTH : integer;
  attribute LC_PROBE589_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE58_IS_DATA : string;
  attribute LC_PROBE58_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE58_IS_TRIG : string;
  attribute LC_PROBE58_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE58_MU_CNT : integer;
  attribute LC_PROBE58_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE58_PID : string;
  attribute LC_PROBE58_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111010";
  attribute LC_PROBE58_TYPE : integer;
  attribute LC_PROBE58_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE58_WIDTH : integer;
  attribute LC_PROBE58_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE590_IS_DATA : string;
  attribute LC_PROBE590_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE590_IS_TRIG : string;
  attribute LC_PROBE590_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE590_MU_CNT : integer;
  attribute LC_PROBE590_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE590_PID : string;
  attribute LC_PROBE590_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001110";
  attribute LC_PROBE590_TYPE : integer;
  attribute LC_PROBE590_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE590_WIDTH : integer;
  attribute LC_PROBE590_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE591_IS_DATA : string;
  attribute LC_PROBE591_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE591_IS_TRIG : string;
  attribute LC_PROBE591_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE591_MU_CNT : integer;
  attribute LC_PROBE591_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE591_PID : string;
  attribute LC_PROBE591_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001001111";
  attribute LC_PROBE591_TYPE : integer;
  attribute LC_PROBE591_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE591_WIDTH : integer;
  attribute LC_PROBE591_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE592_IS_DATA : string;
  attribute LC_PROBE592_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE592_IS_TRIG : string;
  attribute LC_PROBE592_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE592_MU_CNT : integer;
  attribute LC_PROBE592_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE592_PID : string;
  attribute LC_PROBE592_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010000";
  attribute LC_PROBE592_TYPE : integer;
  attribute LC_PROBE592_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE592_WIDTH : integer;
  attribute LC_PROBE592_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE593_IS_DATA : string;
  attribute LC_PROBE593_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE593_IS_TRIG : string;
  attribute LC_PROBE593_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE593_MU_CNT : integer;
  attribute LC_PROBE593_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE593_PID : string;
  attribute LC_PROBE593_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010001";
  attribute LC_PROBE593_TYPE : integer;
  attribute LC_PROBE593_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE593_WIDTH : integer;
  attribute LC_PROBE593_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE594_IS_DATA : string;
  attribute LC_PROBE594_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE594_IS_TRIG : string;
  attribute LC_PROBE594_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE594_MU_CNT : integer;
  attribute LC_PROBE594_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE594_PID : string;
  attribute LC_PROBE594_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010010";
  attribute LC_PROBE594_TYPE : integer;
  attribute LC_PROBE594_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE594_WIDTH : integer;
  attribute LC_PROBE594_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE595_IS_DATA : string;
  attribute LC_PROBE595_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE595_IS_TRIG : string;
  attribute LC_PROBE595_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE595_MU_CNT : integer;
  attribute LC_PROBE595_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE595_PID : string;
  attribute LC_PROBE595_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010011";
  attribute LC_PROBE595_TYPE : integer;
  attribute LC_PROBE595_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE595_WIDTH : integer;
  attribute LC_PROBE595_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE596_IS_DATA : string;
  attribute LC_PROBE596_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE596_IS_TRIG : string;
  attribute LC_PROBE596_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE596_MU_CNT : integer;
  attribute LC_PROBE596_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE596_PID : string;
  attribute LC_PROBE596_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010100";
  attribute LC_PROBE596_TYPE : integer;
  attribute LC_PROBE596_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE596_WIDTH : integer;
  attribute LC_PROBE596_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE597_IS_DATA : string;
  attribute LC_PROBE597_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE597_IS_TRIG : string;
  attribute LC_PROBE597_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE597_MU_CNT : integer;
  attribute LC_PROBE597_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE597_PID : string;
  attribute LC_PROBE597_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010101";
  attribute LC_PROBE597_TYPE : integer;
  attribute LC_PROBE597_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE597_WIDTH : integer;
  attribute LC_PROBE597_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE598_IS_DATA : string;
  attribute LC_PROBE598_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE598_IS_TRIG : string;
  attribute LC_PROBE598_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE598_MU_CNT : integer;
  attribute LC_PROBE598_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE598_PID : string;
  attribute LC_PROBE598_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010110";
  attribute LC_PROBE598_TYPE : integer;
  attribute LC_PROBE598_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE598_WIDTH : integer;
  attribute LC_PROBE598_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE599_IS_DATA : string;
  attribute LC_PROBE599_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE599_IS_TRIG : string;
  attribute LC_PROBE599_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE599_MU_CNT : integer;
  attribute LC_PROBE599_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE599_PID : string;
  attribute LC_PROBE599_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001010111";
  attribute LC_PROBE599_TYPE : integer;
  attribute LC_PROBE599_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE599_WIDTH : integer;
  attribute LC_PROBE599_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE59_IS_DATA : string;
  attribute LC_PROBE59_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE59_IS_TRIG : string;
  attribute LC_PROBE59_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE59_MU_CNT : integer;
  attribute LC_PROBE59_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE59_PID : string;
  attribute LC_PROBE59_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111011";
  attribute LC_PROBE59_TYPE : integer;
  attribute LC_PROBE59_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE59_WIDTH : integer;
  attribute LC_PROBE59_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE5_IS_DATA : string;
  attribute LC_PROBE5_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE5_IS_TRIG : string;
  attribute LC_PROBE5_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b1";
  attribute LC_PROBE5_MU_CNT : integer;
  attribute LC_PROBE5_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE5_PID : string;
  attribute LC_PROBE5_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000101";
  attribute LC_PROBE5_TYPE : integer;
  attribute LC_PROBE5_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_PROBE5_WIDTH : integer;
  attribute LC_PROBE5_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 32;
  attribute LC_PROBE600_IS_DATA : string;
  attribute LC_PROBE600_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE600_IS_TRIG : string;
  attribute LC_PROBE600_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE600_MU_CNT : integer;
  attribute LC_PROBE600_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE600_PID : string;
  attribute LC_PROBE600_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011000";
  attribute LC_PROBE600_TYPE : integer;
  attribute LC_PROBE600_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE600_WIDTH : integer;
  attribute LC_PROBE600_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE601_IS_DATA : string;
  attribute LC_PROBE601_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE601_IS_TRIG : string;
  attribute LC_PROBE601_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE601_MU_CNT : integer;
  attribute LC_PROBE601_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE601_PID : string;
  attribute LC_PROBE601_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011001";
  attribute LC_PROBE601_TYPE : integer;
  attribute LC_PROBE601_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE601_WIDTH : integer;
  attribute LC_PROBE601_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE602_IS_DATA : string;
  attribute LC_PROBE602_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE602_IS_TRIG : string;
  attribute LC_PROBE602_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE602_MU_CNT : integer;
  attribute LC_PROBE602_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE602_PID : string;
  attribute LC_PROBE602_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011010";
  attribute LC_PROBE602_TYPE : integer;
  attribute LC_PROBE602_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE602_WIDTH : integer;
  attribute LC_PROBE602_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE603_IS_DATA : string;
  attribute LC_PROBE603_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE603_IS_TRIG : string;
  attribute LC_PROBE603_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE603_MU_CNT : integer;
  attribute LC_PROBE603_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE603_PID : string;
  attribute LC_PROBE603_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011011";
  attribute LC_PROBE603_TYPE : integer;
  attribute LC_PROBE603_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE603_WIDTH : integer;
  attribute LC_PROBE603_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE604_IS_DATA : string;
  attribute LC_PROBE604_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE604_IS_TRIG : string;
  attribute LC_PROBE604_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE604_MU_CNT : integer;
  attribute LC_PROBE604_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE604_PID : string;
  attribute LC_PROBE604_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011100";
  attribute LC_PROBE604_TYPE : integer;
  attribute LC_PROBE604_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE604_WIDTH : integer;
  attribute LC_PROBE604_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE605_IS_DATA : string;
  attribute LC_PROBE605_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE605_IS_TRIG : string;
  attribute LC_PROBE605_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE605_MU_CNT : integer;
  attribute LC_PROBE605_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE605_PID : string;
  attribute LC_PROBE605_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011101";
  attribute LC_PROBE605_TYPE : integer;
  attribute LC_PROBE605_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE605_WIDTH : integer;
  attribute LC_PROBE605_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE606_IS_DATA : string;
  attribute LC_PROBE606_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE606_IS_TRIG : string;
  attribute LC_PROBE606_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE606_MU_CNT : integer;
  attribute LC_PROBE606_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE606_PID : string;
  attribute LC_PROBE606_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011110";
  attribute LC_PROBE606_TYPE : integer;
  attribute LC_PROBE606_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE606_WIDTH : integer;
  attribute LC_PROBE606_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE607_IS_DATA : string;
  attribute LC_PROBE607_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE607_IS_TRIG : string;
  attribute LC_PROBE607_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE607_MU_CNT : integer;
  attribute LC_PROBE607_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE607_PID : string;
  attribute LC_PROBE607_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001011111";
  attribute LC_PROBE607_TYPE : integer;
  attribute LC_PROBE607_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE607_WIDTH : integer;
  attribute LC_PROBE607_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE608_IS_DATA : string;
  attribute LC_PROBE608_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE608_IS_TRIG : string;
  attribute LC_PROBE608_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE608_MU_CNT : integer;
  attribute LC_PROBE608_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE608_PID : string;
  attribute LC_PROBE608_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100000";
  attribute LC_PROBE608_TYPE : integer;
  attribute LC_PROBE608_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE608_WIDTH : integer;
  attribute LC_PROBE608_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE609_IS_DATA : string;
  attribute LC_PROBE609_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE609_IS_TRIG : string;
  attribute LC_PROBE609_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE609_MU_CNT : integer;
  attribute LC_PROBE609_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE609_PID : string;
  attribute LC_PROBE609_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100001";
  attribute LC_PROBE609_TYPE : integer;
  attribute LC_PROBE609_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE609_WIDTH : integer;
  attribute LC_PROBE609_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE60_IS_DATA : string;
  attribute LC_PROBE60_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE60_IS_TRIG : string;
  attribute LC_PROBE60_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE60_MU_CNT : integer;
  attribute LC_PROBE60_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE60_PID : string;
  attribute LC_PROBE60_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111100";
  attribute LC_PROBE60_TYPE : integer;
  attribute LC_PROBE60_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE60_WIDTH : integer;
  attribute LC_PROBE60_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE610_IS_DATA : string;
  attribute LC_PROBE610_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE610_IS_TRIG : string;
  attribute LC_PROBE610_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE610_MU_CNT : integer;
  attribute LC_PROBE610_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE610_PID : string;
  attribute LC_PROBE610_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100010";
  attribute LC_PROBE610_TYPE : integer;
  attribute LC_PROBE610_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE610_WIDTH : integer;
  attribute LC_PROBE610_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE611_IS_DATA : string;
  attribute LC_PROBE611_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE611_IS_TRIG : string;
  attribute LC_PROBE611_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE611_MU_CNT : integer;
  attribute LC_PROBE611_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE611_PID : string;
  attribute LC_PROBE611_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100011";
  attribute LC_PROBE611_TYPE : integer;
  attribute LC_PROBE611_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE611_WIDTH : integer;
  attribute LC_PROBE611_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE612_IS_DATA : string;
  attribute LC_PROBE612_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE612_IS_TRIG : string;
  attribute LC_PROBE612_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE612_MU_CNT : integer;
  attribute LC_PROBE612_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE612_PID : string;
  attribute LC_PROBE612_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100100";
  attribute LC_PROBE612_TYPE : integer;
  attribute LC_PROBE612_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE612_WIDTH : integer;
  attribute LC_PROBE612_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE613_IS_DATA : string;
  attribute LC_PROBE613_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE613_IS_TRIG : string;
  attribute LC_PROBE613_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE613_MU_CNT : integer;
  attribute LC_PROBE613_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE613_PID : string;
  attribute LC_PROBE613_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100101";
  attribute LC_PROBE613_TYPE : integer;
  attribute LC_PROBE613_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE613_WIDTH : integer;
  attribute LC_PROBE613_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE614_IS_DATA : string;
  attribute LC_PROBE614_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE614_IS_TRIG : string;
  attribute LC_PROBE614_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE614_MU_CNT : integer;
  attribute LC_PROBE614_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE614_PID : string;
  attribute LC_PROBE614_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100110";
  attribute LC_PROBE614_TYPE : integer;
  attribute LC_PROBE614_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE614_WIDTH : integer;
  attribute LC_PROBE614_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE615_IS_DATA : string;
  attribute LC_PROBE615_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE615_IS_TRIG : string;
  attribute LC_PROBE615_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE615_MU_CNT : integer;
  attribute LC_PROBE615_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE615_PID : string;
  attribute LC_PROBE615_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001100111";
  attribute LC_PROBE615_TYPE : integer;
  attribute LC_PROBE615_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE615_WIDTH : integer;
  attribute LC_PROBE615_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE616_IS_DATA : string;
  attribute LC_PROBE616_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE616_IS_TRIG : string;
  attribute LC_PROBE616_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE616_MU_CNT : integer;
  attribute LC_PROBE616_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE616_PID : string;
  attribute LC_PROBE616_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101000";
  attribute LC_PROBE616_TYPE : integer;
  attribute LC_PROBE616_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE616_WIDTH : integer;
  attribute LC_PROBE616_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE617_IS_DATA : string;
  attribute LC_PROBE617_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE617_IS_TRIG : string;
  attribute LC_PROBE617_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE617_MU_CNT : integer;
  attribute LC_PROBE617_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE617_PID : string;
  attribute LC_PROBE617_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101001";
  attribute LC_PROBE617_TYPE : integer;
  attribute LC_PROBE617_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE617_WIDTH : integer;
  attribute LC_PROBE617_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE618_IS_DATA : string;
  attribute LC_PROBE618_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE618_IS_TRIG : string;
  attribute LC_PROBE618_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE618_MU_CNT : integer;
  attribute LC_PROBE618_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE618_PID : string;
  attribute LC_PROBE618_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101010";
  attribute LC_PROBE618_TYPE : integer;
  attribute LC_PROBE618_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE618_WIDTH : integer;
  attribute LC_PROBE618_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE619_IS_DATA : string;
  attribute LC_PROBE619_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE619_IS_TRIG : string;
  attribute LC_PROBE619_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE619_MU_CNT : integer;
  attribute LC_PROBE619_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE619_PID : string;
  attribute LC_PROBE619_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101011";
  attribute LC_PROBE619_TYPE : integer;
  attribute LC_PROBE619_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE619_WIDTH : integer;
  attribute LC_PROBE619_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE61_IS_DATA : string;
  attribute LC_PROBE61_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE61_IS_TRIG : string;
  attribute LC_PROBE61_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE61_MU_CNT : integer;
  attribute LC_PROBE61_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE61_PID : string;
  attribute LC_PROBE61_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111101";
  attribute LC_PROBE61_TYPE : integer;
  attribute LC_PROBE61_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE61_WIDTH : integer;
  attribute LC_PROBE61_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE620_IS_DATA : string;
  attribute LC_PROBE620_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE620_IS_TRIG : string;
  attribute LC_PROBE620_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE620_MU_CNT : integer;
  attribute LC_PROBE620_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE620_PID : string;
  attribute LC_PROBE620_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101100";
  attribute LC_PROBE620_TYPE : integer;
  attribute LC_PROBE620_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE620_WIDTH : integer;
  attribute LC_PROBE620_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE621_IS_DATA : string;
  attribute LC_PROBE621_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE621_IS_TRIG : string;
  attribute LC_PROBE621_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE621_MU_CNT : integer;
  attribute LC_PROBE621_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE621_PID : string;
  attribute LC_PROBE621_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101101";
  attribute LC_PROBE621_TYPE : integer;
  attribute LC_PROBE621_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE621_WIDTH : integer;
  attribute LC_PROBE621_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE622_IS_DATA : string;
  attribute LC_PROBE622_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE622_IS_TRIG : string;
  attribute LC_PROBE622_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE622_MU_CNT : integer;
  attribute LC_PROBE622_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE622_PID : string;
  attribute LC_PROBE622_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101110";
  attribute LC_PROBE622_TYPE : integer;
  attribute LC_PROBE622_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE622_WIDTH : integer;
  attribute LC_PROBE622_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE623_IS_DATA : string;
  attribute LC_PROBE623_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE623_IS_TRIG : string;
  attribute LC_PROBE623_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE623_MU_CNT : integer;
  attribute LC_PROBE623_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE623_PID : string;
  attribute LC_PROBE623_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001101111";
  attribute LC_PROBE623_TYPE : integer;
  attribute LC_PROBE623_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE623_WIDTH : integer;
  attribute LC_PROBE623_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE624_IS_DATA : string;
  attribute LC_PROBE624_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE624_IS_TRIG : string;
  attribute LC_PROBE624_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE624_MU_CNT : integer;
  attribute LC_PROBE624_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE624_PID : string;
  attribute LC_PROBE624_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110000";
  attribute LC_PROBE624_TYPE : integer;
  attribute LC_PROBE624_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE624_WIDTH : integer;
  attribute LC_PROBE624_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE625_IS_DATA : string;
  attribute LC_PROBE625_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE625_IS_TRIG : string;
  attribute LC_PROBE625_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE625_MU_CNT : integer;
  attribute LC_PROBE625_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE625_PID : string;
  attribute LC_PROBE625_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110001";
  attribute LC_PROBE625_TYPE : integer;
  attribute LC_PROBE625_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE625_WIDTH : integer;
  attribute LC_PROBE625_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE626_IS_DATA : string;
  attribute LC_PROBE626_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE626_IS_TRIG : string;
  attribute LC_PROBE626_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE626_MU_CNT : integer;
  attribute LC_PROBE626_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE626_PID : string;
  attribute LC_PROBE626_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110010";
  attribute LC_PROBE626_TYPE : integer;
  attribute LC_PROBE626_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE626_WIDTH : integer;
  attribute LC_PROBE626_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE627_IS_DATA : string;
  attribute LC_PROBE627_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE627_IS_TRIG : string;
  attribute LC_PROBE627_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE627_MU_CNT : integer;
  attribute LC_PROBE627_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE627_PID : string;
  attribute LC_PROBE627_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110011";
  attribute LC_PROBE627_TYPE : integer;
  attribute LC_PROBE627_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE627_WIDTH : integer;
  attribute LC_PROBE627_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE628_IS_DATA : string;
  attribute LC_PROBE628_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE628_IS_TRIG : string;
  attribute LC_PROBE628_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE628_MU_CNT : integer;
  attribute LC_PROBE628_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE628_PID : string;
  attribute LC_PROBE628_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110100";
  attribute LC_PROBE628_TYPE : integer;
  attribute LC_PROBE628_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE628_WIDTH : integer;
  attribute LC_PROBE628_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE629_IS_DATA : string;
  attribute LC_PROBE629_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE629_IS_TRIG : string;
  attribute LC_PROBE629_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE629_MU_CNT : integer;
  attribute LC_PROBE629_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE629_PID : string;
  attribute LC_PROBE629_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110101";
  attribute LC_PROBE629_TYPE : integer;
  attribute LC_PROBE629_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE629_WIDTH : integer;
  attribute LC_PROBE629_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE62_IS_DATA : string;
  attribute LC_PROBE62_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE62_IS_TRIG : string;
  attribute LC_PROBE62_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE62_MU_CNT : integer;
  attribute LC_PROBE62_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE62_PID : string;
  attribute LC_PROBE62_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111110";
  attribute LC_PROBE62_TYPE : integer;
  attribute LC_PROBE62_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE62_WIDTH : integer;
  attribute LC_PROBE62_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE630_IS_DATA : string;
  attribute LC_PROBE630_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE630_IS_TRIG : string;
  attribute LC_PROBE630_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE630_MU_CNT : integer;
  attribute LC_PROBE630_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE630_PID : string;
  attribute LC_PROBE630_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110110";
  attribute LC_PROBE630_TYPE : integer;
  attribute LC_PROBE630_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE630_WIDTH : integer;
  attribute LC_PROBE630_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE631_IS_DATA : string;
  attribute LC_PROBE631_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE631_IS_TRIG : string;
  attribute LC_PROBE631_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE631_MU_CNT : integer;
  attribute LC_PROBE631_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE631_PID : string;
  attribute LC_PROBE631_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001110111";
  attribute LC_PROBE631_TYPE : integer;
  attribute LC_PROBE631_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE631_WIDTH : integer;
  attribute LC_PROBE631_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE632_IS_DATA : string;
  attribute LC_PROBE632_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE632_IS_TRIG : string;
  attribute LC_PROBE632_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE632_MU_CNT : integer;
  attribute LC_PROBE632_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE632_PID : string;
  attribute LC_PROBE632_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111000";
  attribute LC_PROBE632_TYPE : integer;
  attribute LC_PROBE632_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE632_WIDTH : integer;
  attribute LC_PROBE632_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE633_IS_DATA : string;
  attribute LC_PROBE633_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE633_IS_TRIG : string;
  attribute LC_PROBE633_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE633_MU_CNT : integer;
  attribute LC_PROBE633_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE633_PID : string;
  attribute LC_PROBE633_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111001";
  attribute LC_PROBE633_TYPE : integer;
  attribute LC_PROBE633_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE633_WIDTH : integer;
  attribute LC_PROBE633_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE634_IS_DATA : string;
  attribute LC_PROBE634_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE634_IS_TRIG : string;
  attribute LC_PROBE634_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE634_MU_CNT : integer;
  attribute LC_PROBE634_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE634_PID : string;
  attribute LC_PROBE634_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111010";
  attribute LC_PROBE634_TYPE : integer;
  attribute LC_PROBE634_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE634_WIDTH : integer;
  attribute LC_PROBE634_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE635_IS_DATA : string;
  attribute LC_PROBE635_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE635_IS_TRIG : string;
  attribute LC_PROBE635_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE635_MU_CNT : integer;
  attribute LC_PROBE635_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE635_PID : string;
  attribute LC_PROBE635_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111011";
  attribute LC_PROBE635_TYPE : integer;
  attribute LC_PROBE635_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE635_WIDTH : integer;
  attribute LC_PROBE635_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE636_IS_DATA : string;
  attribute LC_PROBE636_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE636_IS_TRIG : string;
  attribute LC_PROBE636_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE636_MU_CNT : integer;
  attribute LC_PROBE636_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE636_PID : string;
  attribute LC_PROBE636_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111100";
  attribute LC_PROBE636_TYPE : integer;
  attribute LC_PROBE636_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE636_WIDTH : integer;
  attribute LC_PROBE636_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE637_IS_DATA : string;
  attribute LC_PROBE637_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE637_IS_TRIG : string;
  attribute LC_PROBE637_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE637_MU_CNT : integer;
  attribute LC_PROBE637_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE637_PID : string;
  attribute LC_PROBE637_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111101";
  attribute LC_PROBE637_TYPE : integer;
  attribute LC_PROBE637_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE637_WIDTH : integer;
  attribute LC_PROBE637_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE638_IS_DATA : string;
  attribute LC_PROBE638_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE638_IS_TRIG : string;
  attribute LC_PROBE638_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE638_MU_CNT : integer;
  attribute LC_PROBE638_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE638_PID : string;
  attribute LC_PROBE638_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111110";
  attribute LC_PROBE638_TYPE : integer;
  attribute LC_PROBE638_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE638_WIDTH : integer;
  attribute LC_PROBE638_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE639_IS_DATA : string;
  attribute LC_PROBE639_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE639_IS_TRIG : string;
  attribute LC_PROBE639_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE639_MU_CNT : integer;
  attribute LC_PROBE639_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE639_PID : string;
  attribute LC_PROBE639_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001001111111";
  attribute LC_PROBE639_TYPE : integer;
  attribute LC_PROBE639_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE639_WIDTH : integer;
  attribute LC_PROBE639_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE63_IS_DATA : string;
  attribute LC_PROBE63_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE63_IS_TRIG : string;
  attribute LC_PROBE63_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE63_MU_CNT : integer;
  attribute LC_PROBE63_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE63_PID : string;
  attribute LC_PROBE63_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000111111";
  attribute LC_PROBE63_TYPE : integer;
  attribute LC_PROBE63_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE63_WIDTH : integer;
  attribute LC_PROBE63_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE640_IS_DATA : string;
  attribute LC_PROBE640_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE640_IS_TRIG : string;
  attribute LC_PROBE640_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE640_MU_CNT : integer;
  attribute LC_PROBE640_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE640_PID : string;
  attribute LC_PROBE640_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000000";
  attribute LC_PROBE640_TYPE : integer;
  attribute LC_PROBE640_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE640_WIDTH : integer;
  attribute LC_PROBE640_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE641_IS_DATA : string;
  attribute LC_PROBE641_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE641_IS_TRIG : string;
  attribute LC_PROBE641_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE641_MU_CNT : integer;
  attribute LC_PROBE641_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE641_PID : string;
  attribute LC_PROBE641_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000001";
  attribute LC_PROBE641_TYPE : integer;
  attribute LC_PROBE641_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE641_WIDTH : integer;
  attribute LC_PROBE641_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE642_IS_DATA : string;
  attribute LC_PROBE642_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE642_IS_TRIG : string;
  attribute LC_PROBE642_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE642_MU_CNT : integer;
  attribute LC_PROBE642_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE642_PID : string;
  attribute LC_PROBE642_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000010";
  attribute LC_PROBE642_TYPE : integer;
  attribute LC_PROBE642_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE642_WIDTH : integer;
  attribute LC_PROBE642_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE643_IS_DATA : string;
  attribute LC_PROBE643_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE643_IS_TRIG : string;
  attribute LC_PROBE643_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE643_MU_CNT : integer;
  attribute LC_PROBE643_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE643_PID : string;
  attribute LC_PROBE643_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000011";
  attribute LC_PROBE643_TYPE : integer;
  attribute LC_PROBE643_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE643_WIDTH : integer;
  attribute LC_PROBE643_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE644_IS_DATA : string;
  attribute LC_PROBE644_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE644_IS_TRIG : string;
  attribute LC_PROBE644_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE644_MU_CNT : integer;
  attribute LC_PROBE644_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE644_PID : string;
  attribute LC_PROBE644_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000100";
  attribute LC_PROBE644_TYPE : integer;
  attribute LC_PROBE644_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE644_WIDTH : integer;
  attribute LC_PROBE644_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE645_IS_DATA : string;
  attribute LC_PROBE645_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE645_IS_TRIG : string;
  attribute LC_PROBE645_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE645_MU_CNT : integer;
  attribute LC_PROBE645_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE645_PID : string;
  attribute LC_PROBE645_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000101";
  attribute LC_PROBE645_TYPE : integer;
  attribute LC_PROBE645_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE645_WIDTH : integer;
  attribute LC_PROBE645_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE646_IS_DATA : string;
  attribute LC_PROBE646_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE646_IS_TRIG : string;
  attribute LC_PROBE646_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE646_MU_CNT : integer;
  attribute LC_PROBE646_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE646_PID : string;
  attribute LC_PROBE646_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000110";
  attribute LC_PROBE646_TYPE : integer;
  attribute LC_PROBE646_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE646_WIDTH : integer;
  attribute LC_PROBE646_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE647_IS_DATA : string;
  attribute LC_PROBE647_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE647_IS_TRIG : string;
  attribute LC_PROBE647_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE647_MU_CNT : integer;
  attribute LC_PROBE647_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE647_PID : string;
  attribute LC_PROBE647_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010000111";
  attribute LC_PROBE647_TYPE : integer;
  attribute LC_PROBE647_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE647_WIDTH : integer;
  attribute LC_PROBE647_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE648_IS_DATA : string;
  attribute LC_PROBE648_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE648_IS_TRIG : string;
  attribute LC_PROBE648_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE648_MU_CNT : integer;
  attribute LC_PROBE648_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE648_PID : string;
  attribute LC_PROBE648_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001000";
  attribute LC_PROBE648_TYPE : integer;
  attribute LC_PROBE648_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE648_WIDTH : integer;
  attribute LC_PROBE648_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE649_IS_DATA : string;
  attribute LC_PROBE649_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE649_IS_TRIG : string;
  attribute LC_PROBE649_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE649_MU_CNT : integer;
  attribute LC_PROBE649_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE649_PID : string;
  attribute LC_PROBE649_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001001";
  attribute LC_PROBE649_TYPE : integer;
  attribute LC_PROBE649_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE649_WIDTH : integer;
  attribute LC_PROBE649_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE64_IS_DATA : string;
  attribute LC_PROBE64_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE64_IS_TRIG : string;
  attribute LC_PROBE64_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE64_MU_CNT : integer;
  attribute LC_PROBE64_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE64_PID : string;
  attribute LC_PROBE64_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000000";
  attribute LC_PROBE64_TYPE : integer;
  attribute LC_PROBE64_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE64_WIDTH : integer;
  attribute LC_PROBE64_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE650_IS_DATA : string;
  attribute LC_PROBE650_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE650_IS_TRIG : string;
  attribute LC_PROBE650_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE650_MU_CNT : integer;
  attribute LC_PROBE650_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE650_PID : string;
  attribute LC_PROBE650_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001010";
  attribute LC_PROBE650_TYPE : integer;
  attribute LC_PROBE650_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE650_WIDTH : integer;
  attribute LC_PROBE650_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE651_IS_DATA : string;
  attribute LC_PROBE651_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE651_IS_TRIG : string;
  attribute LC_PROBE651_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE651_MU_CNT : integer;
  attribute LC_PROBE651_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE651_PID : string;
  attribute LC_PROBE651_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001011";
  attribute LC_PROBE651_TYPE : integer;
  attribute LC_PROBE651_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE651_WIDTH : integer;
  attribute LC_PROBE651_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE652_IS_DATA : string;
  attribute LC_PROBE652_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE652_IS_TRIG : string;
  attribute LC_PROBE652_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE652_MU_CNT : integer;
  attribute LC_PROBE652_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE652_PID : string;
  attribute LC_PROBE652_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001100";
  attribute LC_PROBE652_TYPE : integer;
  attribute LC_PROBE652_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE652_WIDTH : integer;
  attribute LC_PROBE652_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE653_IS_DATA : string;
  attribute LC_PROBE653_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE653_IS_TRIG : string;
  attribute LC_PROBE653_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE653_MU_CNT : integer;
  attribute LC_PROBE653_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE653_PID : string;
  attribute LC_PROBE653_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001101";
  attribute LC_PROBE653_TYPE : integer;
  attribute LC_PROBE653_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE653_WIDTH : integer;
  attribute LC_PROBE653_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE654_IS_DATA : string;
  attribute LC_PROBE654_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE654_IS_TRIG : string;
  attribute LC_PROBE654_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE654_MU_CNT : integer;
  attribute LC_PROBE654_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE654_PID : string;
  attribute LC_PROBE654_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001110";
  attribute LC_PROBE654_TYPE : integer;
  attribute LC_PROBE654_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE654_WIDTH : integer;
  attribute LC_PROBE654_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE655_IS_DATA : string;
  attribute LC_PROBE655_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE655_IS_TRIG : string;
  attribute LC_PROBE655_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE655_MU_CNT : integer;
  attribute LC_PROBE655_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE655_PID : string;
  attribute LC_PROBE655_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010001111";
  attribute LC_PROBE655_TYPE : integer;
  attribute LC_PROBE655_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE655_WIDTH : integer;
  attribute LC_PROBE655_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE656_IS_DATA : string;
  attribute LC_PROBE656_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE656_IS_TRIG : string;
  attribute LC_PROBE656_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE656_MU_CNT : integer;
  attribute LC_PROBE656_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE656_PID : string;
  attribute LC_PROBE656_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010000";
  attribute LC_PROBE656_TYPE : integer;
  attribute LC_PROBE656_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE656_WIDTH : integer;
  attribute LC_PROBE656_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE657_IS_DATA : string;
  attribute LC_PROBE657_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE657_IS_TRIG : string;
  attribute LC_PROBE657_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE657_MU_CNT : integer;
  attribute LC_PROBE657_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE657_PID : string;
  attribute LC_PROBE657_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010001";
  attribute LC_PROBE657_TYPE : integer;
  attribute LC_PROBE657_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE657_WIDTH : integer;
  attribute LC_PROBE657_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE658_IS_DATA : string;
  attribute LC_PROBE658_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE658_IS_TRIG : string;
  attribute LC_PROBE658_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE658_MU_CNT : integer;
  attribute LC_PROBE658_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE658_PID : string;
  attribute LC_PROBE658_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010010";
  attribute LC_PROBE658_TYPE : integer;
  attribute LC_PROBE658_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE658_WIDTH : integer;
  attribute LC_PROBE658_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE659_IS_DATA : string;
  attribute LC_PROBE659_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE659_IS_TRIG : string;
  attribute LC_PROBE659_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE659_MU_CNT : integer;
  attribute LC_PROBE659_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE659_PID : string;
  attribute LC_PROBE659_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010011";
  attribute LC_PROBE659_TYPE : integer;
  attribute LC_PROBE659_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE659_WIDTH : integer;
  attribute LC_PROBE659_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE65_IS_DATA : string;
  attribute LC_PROBE65_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE65_IS_TRIG : string;
  attribute LC_PROBE65_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE65_MU_CNT : integer;
  attribute LC_PROBE65_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE65_PID : string;
  attribute LC_PROBE65_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000001";
  attribute LC_PROBE65_TYPE : integer;
  attribute LC_PROBE65_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE65_WIDTH : integer;
  attribute LC_PROBE65_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE660_IS_DATA : string;
  attribute LC_PROBE660_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE660_IS_TRIG : string;
  attribute LC_PROBE660_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE660_MU_CNT : integer;
  attribute LC_PROBE660_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE660_PID : string;
  attribute LC_PROBE660_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010100";
  attribute LC_PROBE660_TYPE : integer;
  attribute LC_PROBE660_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE660_WIDTH : integer;
  attribute LC_PROBE660_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE661_IS_DATA : string;
  attribute LC_PROBE661_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE661_IS_TRIG : string;
  attribute LC_PROBE661_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE661_MU_CNT : integer;
  attribute LC_PROBE661_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE661_PID : string;
  attribute LC_PROBE661_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010101";
  attribute LC_PROBE661_TYPE : integer;
  attribute LC_PROBE661_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE661_WIDTH : integer;
  attribute LC_PROBE661_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE662_IS_DATA : string;
  attribute LC_PROBE662_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE662_IS_TRIG : string;
  attribute LC_PROBE662_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE662_MU_CNT : integer;
  attribute LC_PROBE662_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE662_PID : string;
  attribute LC_PROBE662_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010110";
  attribute LC_PROBE662_TYPE : integer;
  attribute LC_PROBE662_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE662_WIDTH : integer;
  attribute LC_PROBE662_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE663_IS_DATA : string;
  attribute LC_PROBE663_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE663_IS_TRIG : string;
  attribute LC_PROBE663_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE663_MU_CNT : integer;
  attribute LC_PROBE663_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE663_PID : string;
  attribute LC_PROBE663_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010010111";
  attribute LC_PROBE663_TYPE : integer;
  attribute LC_PROBE663_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE663_WIDTH : integer;
  attribute LC_PROBE663_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE664_IS_DATA : string;
  attribute LC_PROBE664_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE664_IS_TRIG : string;
  attribute LC_PROBE664_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE664_MU_CNT : integer;
  attribute LC_PROBE664_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE664_PID : string;
  attribute LC_PROBE664_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011000";
  attribute LC_PROBE664_TYPE : integer;
  attribute LC_PROBE664_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE664_WIDTH : integer;
  attribute LC_PROBE664_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE665_IS_DATA : string;
  attribute LC_PROBE665_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE665_IS_TRIG : string;
  attribute LC_PROBE665_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE665_MU_CNT : integer;
  attribute LC_PROBE665_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE665_PID : string;
  attribute LC_PROBE665_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011001";
  attribute LC_PROBE665_TYPE : integer;
  attribute LC_PROBE665_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE665_WIDTH : integer;
  attribute LC_PROBE665_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE666_IS_DATA : string;
  attribute LC_PROBE666_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE666_IS_TRIG : string;
  attribute LC_PROBE666_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE666_MU_CNT : integer;
  attribute LC_PROBE666_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE666_PID : string;
  attribute LC_PROBE666_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011010";
  attribute LC_PROBE666_TYPE : integer;
  attribute LC_PROBE666_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE666_WIDTH : integer;
  attribute LC_PROBE666_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE667_IS_DATA : string;
  attribute LC_PROBE667_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE667_IS_TRIG : string;
  attribute LC_PROBE667_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE667_MU_CNT : integer;
  attribute LC_PROBE667_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE667_PID : string;
  attribute LC_PROBE667_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011011";
  attribute LC_PROBE667_TYPE : integer;
  attribute LC_PROBE667_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE667_WIDTH : integer;
  attribute LC_PROBE667_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE668_IS_DATA : string;
  attribute LC_PROBE668_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE668_IS_TRIG : string;
  attribute LC_PROBE668_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE668_MU_CNT : integer;
  attribute LC_PROBE668_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE668_PID : string;
  attribute LC_PROBE668_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011100";
  attribute LC_PROBE668_TYPE : integer;
  attribute LC_PROBE668_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE668_WIDTH : integer;
  attribute LC_PROBE668_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE669_IS_DATA : string;
  attribute LC_PROBE669_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE669_IS_TRIG : string;
  attribute LC_PROBE669_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE669_MU_CNT : integer;
  attribute LC_PROBE669_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE669_PID : string;
  attribute LC_PROBE669_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011101";
  attribute LC_PROBE669_TYPE : integer;
  attribute LC_PROBE669_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE669_WIDTH : integer;
  attribute LC_PROBE669_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE66_IS_DATA : string;
  attribute LC_PROBE66_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE66_IS_TRIG : string;
  attribute LC_PROBE66_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE66_MU_CNT : integer;
  attribute LC_PROBE66_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE66_PID : string;
  attribute LC_PROBE66_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000010";
  attribute LC_PROBE66_TYPE : integer;
  attribute LC_PROBE66_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE66_WIDTH : integer;
  attribute LC_PROBE66_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE670_IS_DATA : string;
  attribute LC_PROBE670_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE670_IS_TRIG : string;
  attribute LC_PROBE670_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE670_MU_CNT : integer;
  attribute LC_PROBE670_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE670_PID : string;
  attribute LC_PROBE670_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011110";
  attribute LC_PROBE670_TYPE : integer;
  attribute LC_PROBE670_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE670_WIDTH : integer;
  attribute LC_PROBE670_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE671_IS_DATA : string;
  attribute LC_PROBE671_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE671_IS_TRIG : string;
  attribute LC_PROBE671_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE671_MU_CNT : integer;
  attribute LC_PROBE671_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE671_PID : string;
  attribute LC_PROBE671_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010011111";
  attribute LC_PROBE671_TYPE : integer;
  attribute LC_PROBE671_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE671_WIDTH : integer;
  attribute LC_PROBE671_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE672_IS_DATA : string;
  attribute LC_PROBE672_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE672_IS_TRIG : string;
  attribute LC_PROBE672_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE672_MU_CNT : integer;
  attribute LC_PROBE672_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE672_PID : string;
  attribute LC_PROBE672_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100000";
  attribute LC_PROBE672_TYPE : integer;
  attribute LC_PROBE672_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE672_WIDTH : integer;
  attribute LC_PROBE672_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE673_IS_DATA : string;
  attribute LC_PROBE673_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE673_IS_TRIG : string;
  attribute LC_PROBE673_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE673_MU_CNT : integer;
  attribute LC_PROBE673_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE673_PID : string;
  attribute LC_PROBE673_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100001";
  attribute LC_PROBE673_TYPE : integer;
  attribute LC_PROBE673_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE673_WIDTH : integer;
  attribute LC_PROBE673_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE674_IS_DATA : string;
  attribute LC_PROBE674_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE674_IS_TRIG : string;
  attribute LC_PROBE674_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE674_MU_CNT : integer;
  attribute LC_PROBE674_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE674_PID : string;
  attribute LC_PROBE674_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100010";
  attribute LC_PROBE674_TYPE : integer;
  attribute LC_PROBE674_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE674_WIDTH : integer;
  attribute LC_PROBE674_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE675_IS_DATA : string;
  attribute LC_PROBE675_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE675_IS_TRIG : string;
  attribute LC_PROBE675_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE675_MU_CNT : integer;
  attribute LC_PROBE675_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE675_PID : string;
  attribute LC_PROBE675_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100011";
  attribute LC_PROBE675_TYPE : integer;
  attribute LC_PROBE675_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE675_WIDTH : integer;
  attribute LC_PROBE675_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE676_IS_DATA : string;
  attribute LC_PROBE676_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE676_IS_TRIG : string;
  attribute LC_PROBE676_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE676_MU_CNT : integer;
  attribute LC_PROBE676_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE676_PID : string;
  attribute LC_PROBE676_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100100";
  attribute LC_PROBE676_TYPE : integer;
  attribute LC_PROBE676_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE676_WIDTH : integer;
  attribute LC_PROBE676_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE677_IS_DATA : string;
  attribute LC_PROBE677_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE677_IS_TRIG : string;
  attribute LC_PROBE677_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE677_MU_CNT : integer;
  attribute LC_PROBE677_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE677_PID : string;
  attribute LC_PROBE677_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100101";
  attribute LC_PROBE677_TYPE : integer;
  attribute LC_PROBE677_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE677_WIDTH : integer;
  attribute LC_PROBE677_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE678_IS_DATA : string;
  attribute LC_PROBE678_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE678_IS_TRIG : string;
  attribute LC_PROBE678_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE678_MU_CNT : integer;
  attribute LC_PROBE678_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE678_PID : string;
  attribute LC_PROBE678_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100110";
  attribute LC_PROBE678_TYPE : integer;
  attribute LC_PROBE678_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE678_WIDTH : integer;
  attribute LC_PROBE678_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE679_IS_DATA : string;
  attribute LC_PROBE679_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE679_IS_TRIG : string;
  attribute LC_PROBE679_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE679_MU_CNT : integer;
  attribute LC_PROBE679_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE679_PID : string;
  attribute LC_PROBE679_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010100111";
  attribute LC_PROBE679_TYPE : integer;
  attribute LC_PROBE679_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE679_WIDTH : integer;
  attribute LC_PROBE679_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE67_IS_DATA : string;
  attribute LC_PROBE67_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE67_IS_TRIG : string;
  attribute LC_PROBE67_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE67_MU_CNT : integer;
  attribute LC_PROBE67_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE67_PID : string;
  attribute LC_PROBE67_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000011";
  attribute LC_PROBE67_TYPE : integer;
  attribute LC_PROBE67_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE67_WIDTH : integer;
  attribute LC_PROBE67_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE680_IS_DATA : string;
  attribute LC_PROBE680_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE680_IS_TRIG : string;
  attribute LC_PROBE680_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE680_MU_CNT : integer;
  attribute LC_PROBE680_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE680_PID : string;
  attribute LC_PROBE680_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101000";
  attribute LC_PROBE680_TYPE : integer;
  attribute LC_PROBE680_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE680_WIDTH : integer;
  attribute LC_PROBE680_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE681_IS_DATA : string;
  attribute LC_PROBE681_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE681_IS_TRIG : string;
  attribute LC_PROBE681_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE681_MU_CNT : integer;
  attribute LC_PROBE681_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE681_PID : string;
  attribute LC_PROBE681_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101001";
  attribute LC_PROBE681_TYPE : integer;
  attribute LC_PROBE681_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE681_WIDTH : integer;
  attribute LC_PROBE681_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE682_IS_DATA : string;
  attribute LC_PROBE682_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE682_IS_TRIG : string;
  attribute LC_PROBE682_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE682_MU_CNT : integer;
  attribute LC_PROBE682_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE682_PID : string;
  attribute LC_PROBE682_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101010";
  attribute LC_PROBE682_TYPE : integer;
  attribute LC_PROBE682_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE682_WIDTH : integer;
  attribute LC_PROBE682_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE683_IS_DATA : string;
  attribute LC_PROBE683_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE683_IS_TRIG : string;
  attribute LC_PROBE683_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE683_MU_CNT : integer;
  attribute LC_PROBE683_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE683_PID : string;
  attribute LC_PROBE683_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101011";
  attribute LC_PROBE683_TYPE : integer;
  attribute LC_PROBE683_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE683_WIDTH : integer;
  attribute LC_PROBE683_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE684_IS_DATA : string;
  attribute LC_PROBE684_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE684_IS_TRIG : string;
  attribute LC_PROBE684_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE684_MU_CNT : integer;
  attribute LC_PROBE684_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE684_PID : string;
  attribute LC_PROBE684_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101100";
  attribute LC_PROBE684_TYPE : integer;
  attribute LC_PROBE684_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE684_WIDTH : integer;
  attribute LC_PROBE684_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE685_IS_DATA : string;
  attribute LC_PROBE685_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE685_IS_TRIG : string;
  attribute LC_PROBE685_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE685_MU_CNT : integer;
  attribute LC_PROBE685_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE685_PID : string;
  attribute LC_PROBE685_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101101";
  attribute LC_PROBE685_TYPE : integer;
  attribute LC_PROBE685_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE685_WIDTH : integer;
  attribute LC_PROBE685_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE686_IS_DATA : string;
  attribute LC_PROBE686_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE686_IS_TRIG : string;
  attribute LC_PROBE686_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE686_MU_CNT : integer;
  attribute LC_PROBE686_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE686_PID : string;
  attribute LC_PROBE686_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101110";
  attribute LC_PROBE686_TYPE : integer;
  attribute LC_PROBE686_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE686_WIDTH : integer;
  attribute LC_PROBE686_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE687_IS_DATA : string;
  attribute LC_PROBE687_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE687_IS_TRIG : string;
  attribute LC_PROBE687_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE687_MU_CNT : integer;
  attribute LC_PROBE687_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE687_PID : string;
  attribute LC_PROBE687_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010101111";
  attribute LC_PROBE687_TYPE : integer;
  attribute LC_PROBE687_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE687_WIDTH : integer;
  attribute LC_PROBE687_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE688_IS_DATA : string;
  attribute LC_PROBE688_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE688_IS_TRIG : string;
  attribute LC_PROBE688_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE688_MU_CNT : integer;
  attribute LC_PROBE688_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE688_PID : string;
  attribute LC_PROBE688_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110000";
  attribute LC_PROBE688_TYPE : integer;
  attribute LC_PROBE688_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE688_WIDTH : integer;
  attribute LC_PROBE688_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE689_IS_DATA : string;
  attribute LC_PROBE689_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE689_IS_TRIG : string;
  attribute LC_PROBE689_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE689_MU_CNT : integer;
  attribute LC_PROBE689_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE689_PID : string;
  attribute LC_PROBE689_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110001";
  attribute LC_PROBE689_TYPE : integer;
  attribute LC_PROBE689_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE689_WIDTH : integer;
  attribute LC_PROBE689_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE68_IS_DATA : string;
  attribute LC_PROBE68_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE68_IS_TRIG : string;
  attribute LC_PROBE68_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE68_MU_CNT : integer;
  attribute LC_PROBE68_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE68_PID : string;
  attribute LC_PROBE68_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000100";
  attribute LC_PROBE68_TYPE : integer;
  attribute LC_PROBE68_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE68_WIDTH : integer;
  attribute LC_PROBE68_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE690_IS_DATA : string;
  attribute LC_PROBE690_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE690_IS_TRIG : string;
  attribute LC_PROBE690_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE690_MU_CNT : integer;
  attribute LC_PROBE690_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE690_PID : string;
  attribute LC_PROBE690_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110010";
  attribute LC_PROBE690_TYPE : integer;
  attribute LC_PROBE690_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE690_WIDTH : integer;
  attribute LC_PROBE690_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE691_IS_DATA : string;
  attribute LC_PROBE691_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE691_IS_TRIG : string;
  attribute LC_PROBE691_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE691_MU_CNT : integer;
  attribute LC_PROBE691_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE691_PID : string;
  attribute LC_PROBE691_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110011";
  attribute LC_PROBE691_TYPE : integer;
  attribute LC_PROBE691_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE691_WIDTH : integer;
  attribute LC_PROBE691_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE692_IS_DATA : string;
  attribute LC_PROBE692_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE692_IS_TRIG : string;
  attribute LC_PROBE692_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE692_MU_CNT : integer;
  attribute LC_PROBE692_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE692_PID : string;
  attribute LC_PROBE692_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110100";
  attribute LC_PROBE692_TYPE : integer;
  attribute LC_PROBE692_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE692_WIDTH : integer;
  attribute LC_PROBE692_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE693_IS_DATA : string;
  attribute LC_PROBE693_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE693_IS_TRIG : string;
  attribute LC_PROBE693_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE693_MU_CNT : integer;
  attribute LC_PROBE693_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE693_PID : string;
  attribute LC_PROBE693_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110101";
  attribute LC_PROBE693_TYPE : integer;
  attribute LC_PROBE693_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE693_WIDTH : integer;
  attribute LC_PROBE693_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE694_IS_DATA : string;
  attribute LC_PROBE694_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE694_IS_TRIG : string;
  attribute LC_PROBE694_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE694_MU_CNT : integer;
  attribute LC_PROBE694_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE694_PID : string;
  attribute LC_PROBE694_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110110";
  attribute LC_PROBE694_TYPE : integer;
  attribute LC_PROBE694_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE694_WIDTH : integer;
  attribute LC_PROBE694_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE695_IS_DATA : string;
  attribute LC_PROBE695_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE695_IS_TRIG : string;
  attribute LC_PROBE695_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE695_MU_CNT : integer;
  attribute LC_PROBE695_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE695_PID : string;
  attribute LC_PROBE695_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010110111";
  attribute LC_PROBE695_TYPE : integer;
  attribute LC_PROBE695_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE695_WIDTH : integer;
  attribute LC_PROBE695_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE696_IS_DATA : string;
  attribute LC_PROBE696_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE696_IS_TRIG : string;
  attribute LC_PROBE696_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE696_MU_CNT : integer;
  attribute LC_PROBE696_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE696_PID : string;
  attribute LC_PROBE696_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111000";
  attribute LC_PROBE696_TYPE : integer;
  attribute LC_PROBE696_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE696_WIDTH : integer;
  attribute LC_PROBE696_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE697_IS_DATA : string;
  attribute LC_PROBE697_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE697_IS_TRIG : string;
  attribute LC_PROBE697_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE697_MU_CNT : integer;
  attribute LC_PROBE697_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE697_PID : string;
  attribute LC_PROBE697_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111001";
  attribute LC_PROBE697_TYPE : integer;
  attribute LC_PROBE697_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE697_WIDTH : integer;
  attribute LC_PROBE697_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE698_IS_DATA : string;
  attribute LC_PROBE698_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE698_IS_TRIG : string;
  attribute LC_PROBE698_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE698_MU_CNT : integer;
  attribute LC_PROBE698_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE698_PID : string;
  attribute LC_PROBE698_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111010";
  attribute LC_PROBE698_TYPE : integer;
  attribute LC_PROBE698_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE698_WIDTH : integer;
  attribute LC_PROBE698_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE699_IS_DATA : string;
  attribute LC_PROBE699_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE699_IS_TRIG : string;
  attribute LC_PROBE699_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE699_MU_CNT : integer;
  attribute LC_PROBE699_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE699_PID : string;
  attribute LC_PROBE699_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111011";
  attribute LC_PROBE699_TYPE : integer;
  attribute LC_PROBE699_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE699_WIDTH : integer;
  attribute LC_PROBE699_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE69_IS_DATA : string;
  attribute LC_PROBE69_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE69_IS_TRIG : string;
  attribute LC_PROBE69_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE69_MU_CNT : integer;
  attribute LC_PROBE69_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE69_PID : string;
  attribute LC_PROBE69_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000101";
  attribute LC_PROBE69_TYPE : integer;
  attribute LC_PROBE69_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE69_WIDTH : integer;
  attribute LC_PROBE69_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE6_IS_DATA : string;
  attribute LC_PROBE6_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE6_IS_TRIG : string;
  attribute LC_PROBE6_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE6_MU_CNT : integer;
  attribute LC_PROBE6_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE6_PID : string;
  attribute LC_PROBE6_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000110";
  attribute LC_PROBE6_TYPE : integer;
  attribute LC_PROBE6_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE6_WIDTH : integer;
  attribute LC_PROBE6_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE700_IS_DATA : string;
  attribute LC_PROBE700_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE700_IS_TRIG : string;
  attribute LC_PROBE700_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE700_MU_CNT : integer;
  attribute LC_PROBE700_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE700_PID : string;
  attribute LC_PROBE700_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111100";
  attribute LC_PROBE700_TYPE : integer;
  attribute LC_PROBE700_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE700_WIDTH : integer;
  attribute LC_PROBE700_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE701_IS_DATA : string;
  attribute LC_PROBE701_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE701_IS_TRIG : string;
  attribute LC_PROBE701_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE701_MU_CNT : integer;
  attribute LC_PROBE701_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE701_PID : string;
  attribute LC_PROBE701_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111101";
  attribute LC_PROBE701_TYPE : integer;
  attribute LC_PROBE701_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE701_WIDTH : integer;
  attribute LC_PROBE701_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE702_IS_DATA : string;
  attribute LC_PROBE702_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE702_IS_TRIG : string;
  attribute LC_PROBE702_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE702_MU_CNT : integer;
  attribute LC_PROBE702_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE702_PID : string;
  attribute LC_PROBE702_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111110";
  attribute LC_PROBE702_TYPE : integer;
  attribute LC_PROBE702_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE702_WIDTH : integer;
  attribute LC_PROBE702_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE703_IS_DATA : string;
  attribute LC_PROBE703_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE703_IS_TRIG : string;
  attribute LC_PROBE703_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE703_MU_CNT : integer;
  attribute LC_PROBE703_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE703_PID : string;
  attribute LC_PROBE703_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001010111111";
  attribute LC_PROBE703_TYPE : integer;
  attribute LC_PROBE703_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE703_WIDTH : integer;
  attribute LC_PROBE703_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE704_IS_DATA : string;
  attribute LC_PROBE704_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE704_IS_TRIG : string;
  attribute LC_PROBE704_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE704_MU_CNT : integer;
  attribute LC_PROBE704_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE704_PID : string;
  attribute LC_PROBE704_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000000";
  attribute LC_PROBE704_TYPE : integer;
  attribute LC_PROBE704_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE704_WIDTH : integer;
  attribute LC_PROBE704_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE705_IS_DATA : string;
  attribute LC_PROBE705_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE705_IS_TRIG : string;
  attribute LC_PROBE705_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE705_MU_CNT : integer;
  attribute LC_PROBE705_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE705_PID : string;
  attribute LC_PROBE705_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000001";
  attribute LC_PROBE705_TYPE : integer;
  attribute LC_PROBE705_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE705_WIDTH : integer;
  attribute LC_PROBE705_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE706_IS_DATA : string;
  attribute LC_PROBE706_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE706_IS_TRIG : string;
  attribute LC_PROBE706_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE706_MU_CNT : integer;
  attribute LC_PROBE706_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE706_PID : string;
  attribute LC_PROBE706_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000010";
  attribute LC_PROBE706_TYPE : integer;
  attribute LC_PROBE706_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE706_WIDTH : integer;
  attribute LC_PROBE706_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE707_IS_DATA : string;
  attribute LC_PROBE707_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE707_IS_TRIG : string;
  attribute LC_PROBE707_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE707_MU_CNT : integer;
  attribute LC_PROBE707_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE707_PID : string;
  attribute LC_PROBE707_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000011";
  attribute LC_PROBE707_TYPE : integer;
  attribute LC_PROBE707_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE707_WIDTH : integer;
  attribute LC_PROBE707_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE708_IS_DATA : string;
  attribute LC_PROBE708_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE708_IS_TRIG : string;
  attribute LC_PROBE708_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE708_MU_CNT : integer;
  attribute LC_PROBE708_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE708_PID : string;
  attribute LC_PROBE708_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000100";
  attribute LC_PROBE708_TYPE : integer;
  attribute LC_PROBE708_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE708_WIDTH : integer;
  attribute LC_PROBE708_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE709_IS_DATA : string;
  attribute LC_PROBE709_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE709_IS_TRIG : string;
  attribute LC_PROBE709_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE709_MU_CNT : integer;
  attribute LC_PROBE709_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE709_PID : string;
  attribute LC_PROBE709_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000101";
  attribute LC_PROBE709_TYPE : integer;
  attribute LC_PROBE709_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE709_WIDTH : integer;
  attribute LC_PROBE709_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE70_IS_DATA : string;
  attribute LC_PROBE70_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE70_IS_TRIG : string;
  attribute LC_PROBE70_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE70_MU_CNT : integer;
  attribute LC_PROBE70_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE70_PID : string;
  attribute LC_PROBE70_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000110";
  attribute LC_PROBE70_TYPE : integer;
  attribute LC_PROBE70_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE70_WIDTH : integer;
  attribute LC_PROBE70_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE710_IS_DATA : string;
  attribute LC_PROBE710_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE710_IS_TRIG : string;
  attribute LC_PROBE710_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE710_MU_CNT : integer;
  attribute LC_PROBE710_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE710_PID : string;
  attribute LC_PROBE710_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000110";
  attribute LC_PROBE710_TYPE : integer;
  attribute LC_PROBE710_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE710_WIDTH : integer;
  attribute LC_PROBE710_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE711_IS_DATA : string;
  attribute LC_PROBE711_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE711_IS_TRIG : string;
  attribute LC_PROBE711_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE711_MU_CNT : integer;
  attribute LC_PROBE711_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE711_PID : string;
  attribute LC_PROBE711_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011000111";
  attribute LC_PROBE711_TYPE : integer;
  attribute LC_PROBE711_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE711_WIDTH : integer;
  attribute LC_PROBE711_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE712_IS_DATA : string;
  attribute LC_PROBE712_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE712_IS_TRIG : string;
  attribute LC_PROBE712_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE712_MU_CNT : integer;
  attribute LC_PROBE712_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE712_PID : string;
  attribute LC_PROBE712_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001000";
  attribute LC_PROBE712_TYPE : integer;
  attribute LC_PROBE712_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE712_WIDTH : integer;
  attribute LC_PROBE712_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE713_IS_DATA : string;
  attribute LC_PROBE713_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE713_IS_TRIG : string;
  attribute LC_PROBE713_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE713_MU_CNT : integer;
  attribute LC_PROBE713_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE713_PID : string;
  attribute LC_PROBE713_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001001";
  attribute LC_PROBE713_TYPE : integer;
  attribute LC_PROBE713_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE713_WIDTH : integer;
  attribute LC_PROBE713_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE714_IS_DATA : string;
  attribute LC_PROBE714_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE714_IS_TRIG : string;
  attribute LC_PROBE714_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE714_MU_CNT : integer;
  attribute LC_PROBE714_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE714_PID : string;
  attribute LC_PROBE714_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001010";
  attribute LC_PROBE714_TYPE : integer;
  attribute LC_PROBE714_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE714_WIDTH : integer;
  attribute LC_PROBE714_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE715_IS_DATA : string;
  attribute LC_PROBE715_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE715_IS_TRIG : string;
  attribute LC_PROBE715_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE715_MU_CNT : integer;
  attribute LC_PROBE715_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE715_PID : string;
  attribute LC_PROBE715_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001011";
  attribute LC_PROBE715_TYPE : integer;
  attribute LC_PROBE715_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE715_WIDTH : integer;
  attribute LC_PROBE715_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE716_IS_DATA : string;
  attribute LC_PROBE716_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE716_IS_TRIG : string;
  attribute LC_PROBE716_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE716_MU_CNT : integer;
  attribute LC_PROBE716_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE716_PID : string;
  attribute LC_PROBE716_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001100";
  attribute LC_PROBE716_TYPE : integer;
  attribute LC_PROBE716_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE716_WIDTH : integer;
  attribute LC_PROBE716_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE717_IS_DATA : string;
  attribute LC_PROBE717_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE717_IS_TRIG : string;
  attribute LC_PROBE717_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE717_MU_CNT : integer;
  attribute LC_PROBE717_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE717_PID : string;
  attribute LC_PROBE717_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001101";
  attribute LC_PROBE717_TYPE : integer;
  attribute LC_PROBE717_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE717_WIDTH : integer;
  attribute LC_PROBE717_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE718_IS_DATA : string;
  attribute LC_PROBE718_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE718_IS_TRIG : string;
  attribute LC_PROBE718_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE718_MU_CNT : integer;
  attribute LC_PROBE718_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE718_PID : string;
  attribute LC_PROBE718_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001110";
  attribute LC_PROBE718_TYPE : integer;
  attribute LC_PROBE718_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE718_WIDTH : integer;
  attribute LC_PROBE718_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE719_IS_DATA : string;
  attribute LC_PROBE719_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE719_IS_TRIG : string;
  attribute LC_PROBE719_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE719_MU_CNT : integer;
  attribute LC_PROBE719_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE719_PID : string;
  attribute LC_PROBE719_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011001111";
  attribute LC_PROBE719_TYPE : integer;
  attribute LC_PROBE719_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE719_WIDTH : integer;
  attribute LC_PROBE719_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE71_IS_DATA : string;
  attribute LC_PROBE71_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE71_IS_TRIG : string;
  attribute LC_PROBE71_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE71_MU_CNT : integer;
  attribute LC_PROBE71_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE71_PID : string;
  attribute LC_PROBE71_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001000111";
  attribute LC_PROBE71_TYPE : integer;
  attribute LC_PROBE71_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE71_WIDTH : integer;
  attribute LC_PROBE71_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE720_IS_DATA : string;
  attribute LC_PROBE720_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE720_IS_TRIG : string;
  attribute LC_PROBE720_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE720_MU_CNT : integer;
  attribute LC_PROBE720_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE720_PID : string;
  attribute LC_PROBE720_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010000";
  attribute LC_PROBE720_TYPE : integer;
  attribute LC_PROBE720_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE720_WIDTH : integer;
  attribute LC_PROBE720_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE721_IS_DATA : string;
  attribute LC_PROBE721_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE721_IS_TRIG : string;
  attribute LC_PROBE721_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE721_MU_CNT : integer;
  attribute LC_PROBE721_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE721_PID : string;
  attribute LC_PROBE721_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010001";
  attribute LC_PROBE721_TYPE : integer;
  attribute LC_PROBE721_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE721_WIDTH : integer;
  attribute LC_PROBE721_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE722_IS_DATA : string;
  attribute LC_PROBE722_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE722_IS_TRIG : string;
  attribute LC_PROBE722_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE722_MU_CNT : integer;
  attribute LC_PROBE722_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE722_PID : string;
  attribute LC_PROBE722_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010010";
  attribute LC_PROBE722_TYPE : integer;
  attribute LC_PROBE722_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE722_WIDTH : integer;
  attribute LC_PROBE722_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE723_IS_DATA : string;
  attribute LC_PROBE723_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE723_IS_TRIG : string;
  attribute LC_PROBE723_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE723_MU_CNT : integer;
  attribute LC_PROBE723_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE723_PID : string;
  attribute LC_PROBE723_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010011";
  attribute LC_PROBE723_TYPE : integer;
  attribute LC_PROBE723_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE723_WIDTH : integer;
  attribute LC_PROBE723_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE724_IS_DATA : string;
  attribute LC_PROBE724_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE724_IS_TRIG : string;
  attribute LC_PROBE724_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE724_MU_CNT : integer;
  attribute LC_PROBE724_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE724_PID : string;
  attribute LC_PROBE724_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010100";
  attribute LC_PROBE724_TYPE : integer;
  attribute LC_PROBE724_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE724_WIDTH : integer;
  attribute LC_PROBE724_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE725_IS_DATA : string;
  attribute LC_PROBE725_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE725_IS_TRIG : string;
  attribute LC_PROBE725_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE725_MU_CNT : integer;
  attribute LC_PROBE725_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE725_PID : string;
  attribute LC_PROBE725_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010101";
  attribute LC_PROBE725_TYPE : integer;
  attribute LC_PROBE725_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE725_WIDTH : integer;
  attribute LC_PROBE725_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE726_IS_DATA : string;
  attribute LC_PROBE726_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE726_IS_TRIG : string;
  attribute LC_PROBE726_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE726_MU_CNT : integer;
  attribute LC_PROBE726_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE726_PID : string;
  attribute LC_PROBE726_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010110";
  attribute LC_PROBE726_TYPE : integer;
  attribute LC_PROBE726_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE726_WIDTH : integer;
  attribute LC_PROBE726_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE727_IS_DATA : string;
  attribute LC_PROBE727_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE727_IS_TRIG : string;
  attribute LC_PROBE727_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE727_MU_CNT : integer;
  attribute LC_PROBE727_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE727_PID : string;
  attribute LC_PROBE727_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011010111";
  attribute LC_PROBE727_TYPE : integer;
  attribute LC_PROBE727_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE727_WIDTH : integer;
  attribute LC_PROBE727_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE728_IS_DATA : string;
  attribute LC_PROBE728_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE728_IS_TRIG : string;
  attribute LC_PROBE728_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE728_MU_CNT : integer;
  attribute LC_PROBE728_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE728_PID : string;
  attribute LC_PROBE728_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011000";
  attribute LC_PROBE728_TYPE : integer;
  attribute LC_PROBE728_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE728_WIDTH : integer;
  attribute LC_PROBE728_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE729_IS_DATA : string;
  attribute LC_PROBE729_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE729_IS_TRIG : string;
  attribute LC_PROBE729_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE729_MU_CNT : integer;
  attribute LC_PROBE729_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE729_PID : string;
  attribute LC_PROBE729_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011001";
  attribute LC_PROBE729_TYPE : integer;
  attribute LC_PROBE729_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE729_WIDTH : integer;
  attribute LC_PROBE729_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE72_IS_DATA : string;
  attribute LC_PROBE72_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE72_IS_TRIG : string;
  attribute LC_PROBE72_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE72_MU_CNT : integer;
  attribute LC_PROBE72_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE72_PID : string;
  attribute LC_PROBE72_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001000";
  attribute LC_PROBE72_TYPE : integer;
  attribute LC_PROBE72_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE72_WIDTH : integer;
  attribute LC_PROBE72_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE730_IS_DATA : string;
  attribute LC_PROBE730_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE730_IS_TRIG : string;
  attribute LC_PROBE730_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE730_MU_CNT : integer;
  attribute LC_PROBE730_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE730_PID : string;
  attribute LC_PROBE730_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011010";
  attribute LC_PROBE730_TYPE : integer;
  attribute LC_PROBE730_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE730_WIDTH : integer;
  attribute LC_PROBE730_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE731_IS_DATA : string;
  attribute LC_PROBE731_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE731_IS_TRIG : string;
  attribute LC_PROBE731_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE731_MU_CNT : integer;
  attribute LC_PROBE731_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE731_PID : string;
  attribute LC_PROBE731_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011011";
  attribute LC_PROBE731_TYPE : integer;
  attribute LC_PROBE731_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE731_WIDTH : integer;
  attribute LC_PROBE731_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE732_IS_DATA : string;
  attribute LC_PROBE732_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE732_IS_TRIG : string;
  attribute LC_PROBE732_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE732_MU_CNT : integer;
  attribute LC_PROBE732_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE732_PID : string;
  attribute LC_PROBE732_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011100";
  attribute LC_PROBE732_TYPE : integer;
  attribute LC_PROBE732_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE732_WIDTH : integer;
  attribute LC_PROBE732_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE733_IS_DATA : string;
  attribute LC_PROBE733_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE733_IS_TRIG : string;
  attribute LC_PROBE733_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE733_MU_CNT : integer;
  attribute LC_PROBE733_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE733_PID : string;
  attribute LC_PROBE733_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011101";
  attribute LC_PROBE733_TYPE : integer;
  attribute LC_PROBE733_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE733_WIDTH : integer;
  attribute LC_PROBE733_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE734_IS_DATA : string;
  attribute LC_PROBE734_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE734_IS_TRIG : string;
  attribute LC_PROBE734_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE734_MU_CNT : integer;
  attribute LC_PROBE734_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE734_PID : string;
  attribute LC_PROBE734_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011110";
  attribute LC_PROBE734_TYPE : integer;
  attribute LC_PROBE734_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE734_WIDTH : integer;
  attribute LC_PROBE734_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE735_IS_DATA : string;
  attribute LC_PROBE735_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE735_IS_TRIG : string;
  attribute LC_PROBE735_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE735_MU_CNT : integer;
  attribute LC_PROBE735_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE735_PID : string;
  attribute LC_PROBE735_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011011111";
  attribute LC_PROBE735_TYPE : integer;
  attribute LC_PROBE735_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE735_WIDTH : integer;
  attribute LC_PROBE735_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE736_IS_DATA : string;
  attribute LC_PROBE736_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE736_IS_TRIG : string;
  attribute LC_PROBE736_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE736_MU_CNT : integer;
  attribute LC_PROBE736_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE736_PID : string;
  attribute LC_PROBE736_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100000";
  attribute LC_PROBE736_TYPE : integer;
  attribute LC_PROBE736_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE736_WIDTH : integer;
  attribute LC_PROBE736_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE737_IS_DATA : string;
  attribute LC_PROBE737_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE737_IS_TRIG : string;
  attribute LC_PROBE737_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE737_MU_CNT : integer;
  attribute LC_PROBE737_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE737_PID : string;
  attribute LC_PROBE737_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100001";
  attribute LC_PROBE737_TYPE : integer;
  attribute LC_PROBE737_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE737_WIDTH : integer;
  attribute LC_PROBE737_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE738_IS_DATA : string;
  attribute LC_PROBE738_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE738_IS_TRIG : string;
  attribute LC_PROBE738_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE738_MU_CNT : integer;
  attribute LC_PROBE738_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE738_PID : string;
  attribute LC_PROBE738_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100010";
  attribute LC_PROBE738_TYPE : integer;
  attribute LC_PROBE738_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE738_WIDTH : integer;
  attribute LC_PROBE738_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE739_IS_DATA : string;
  attribute LC_PROBE739_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE739_IS_TRIG : string;
  attribute LC_PROBE739_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE739_MU_CNT : integer;
  attribute LC_PROBE739_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE739_PID : string;
  attribute LC_PROBE739_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100011";
  attribute LC_PROBE739_TYPE : integer;
  attribute LC_PROBE739_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE739_WIDTH : integer;
  attribute LC_PROBE739_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE73_IS_DATA : string;
  attribute LC_PROBE73_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE73_IS_TRIG : string;
  attribute LC_PROBE73_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE73_MU_CNT : integer;
  attribute LC_PROBE73_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE73_PID : string;
  attribute LC_PROBE73_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001001";
  attribute LC_PROBE73_TYPE : integer;
  attribute LC_PROBE73_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE73_WIDTH : integer;
  attribute LC_PROBE73_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE740_IS_DATA : string;
  attribute LC_PROBE740_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE740_IS_TRIG : string;
  attribute LC_PROBE740_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE740_MU_CNT : integer;
  attribute LC_PROBE740_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE740_PID : string;
  attribute LC_PROBE740_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100100";
  attribute LC_PROBE740_TYPE : integer;
  attribute LC_PROBE740_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE740_WIDTH : integer;
  attribute LC_PROBE740_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE741_IS_DATA : string;
  attribute LC_PROBE741_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE741_IS_TRIG : string;
  attribute LC_PROBE741_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE741_MU_CNT : integer;
  attribute LC_PROBE741_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE741_PID : string;
  attribute LC_PROBE741_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100101";
  attribute LC_PROBE741_TYPE : integer;
  attribute LC_PROBE741_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE741_WIDTH : integer;
  attribute LC_PROBE741_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE742_IS_DATA : string;
  attribute LC_PROBE742_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE742_IS_TRIG : string;
  attribute LC_PROBE742_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE742_MU_CNT : integer;
  attribute LC_PROBE742_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE742_PID : string;
  attribute LC_PROBE742_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100110";
  attribute LC_PROBE742_TYPE : integer;
  attribute LC_PROBE742_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE742_WIDTH : integer;
  attribute LC_PROBE742_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE743_IS_DATA : string;
  attribute LC_PROBE743_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE743_IS_TRIG : string;
  attribute LC_PROBE743_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE743_MU_CNT : integer;
  attribute LC_PROBE743_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE743_PID : string;
  attribute LC_PROBE743_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011100111";
  attribute LC_PROBE743_TYPE : integer;
  attribute LC_PROBE743_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE743_WIDTH : integer;
  attribute LC_PROBE743_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE744_IS_DATA : string;
  attribute LC_PROBE744_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE744_IS_TRIG : string;
  attribute LC_PROBE744_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE744_MU_CNT : integer;
  attribute LC_PROBE744_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE744_PID : string;
  attribute LC_PROBE744_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101000";
  attribute LC_PROBE744_TYPE : integer;
  attribute LC_PROBE744_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE744_WIDTH : integer;
  attribute LC_PROBE744_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE745_IS_DATA : string;
  attribute LC_PROBE745_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE745_IS_TRIG : string;
  attribute LC_PROBE745_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE745_MU_CNT : integer;
  attribute LC_PROBE745_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE745_PID : string;
  attribute LC_PROBE745_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101001";
  attribute LC_PROBE745_TYPE : integer;
  attribute LC_PROBE745_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE745_WIDTH : integer;
  attribute LC_PROBE745_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE746_IS_DATA : string;
  attribute LC_PROBE746_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE746_IS_TRIG : string;
  attribute LC_PROBE746_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE746_MU_CNT : integer;
  attribute LC_PROBE746_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE746_PID : string;
  attribute LC_PROBE746_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101010";
  attribute LC_PROBE746_TYPE : integer;
  attribute LC_PROBE746_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE746_WIDTH : integer;
  attribute LC_PROBE746_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE747_IS_DATA : string;
  attribute LC_PROBE747_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE747_IS_TRIG : string;
  attribute LC_PROBE747_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE747_MU_CNT : integer;
  attribute LC_PROBE747_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE747_PID : string;
  attribute LC_PROBE747_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101011";
  attribute LC_PROBE747_TYPE : integer;
  attribute LC_PROBE747_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE747_WIDTH : integer;
  attribute LC_PROBE747_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE748_IS_DATA : string;
  attribute LC_PROBE748_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE748_IS_TRIG : string;
  attribute LC_PROBE748_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE748_MU_CNT : integer;
  attribute LC_PROBE748_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE748_PID : string;
  attribute LC_PROBE748_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101100";
  attribute LC_PROBE748_TYPE : integer;
  attribute LC_PROBE748_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE748_WIDTH : integer;
  attribute LC_PROBE748_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE749_IS_DATA : string;
  attribute LC_PROBE749_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE749_IS_TRIG : string;
  attribute LC_PROBE749_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE749_MU_CNT : integer;
  attribute LC_PROBE749_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE749_PID : string;
  attribute LC_PROBE749_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101101";
  attribute LC_PROBE749_TYPE : integer;
  attribute LC_PROBE749_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE749_WIDTH : integer;
  attribute LC_PROBE749_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE74_IS_DATA : string;
  attribute LC_PROBE74_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE74_IS_TRIG : string;
  attribute LC_PROBE74_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE74_MU_CNT : integer;
  attribute LC_PROBE74_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE74_PID : string;
  attribute LC_PROBE74_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001010";
  attribute LC_PROBE74_TYPE : integer;
  attribute LC_PROBE74_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE74_WIDTH : integer;
  attribute LC_PROBE74_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE750_IS_DATA : string;
  attribute LC_PROBE750_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE750_IS_TRIG : string;
  attribute LC_PROBE750_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE750_MU_CNT : integer;
  attribute LC_PROBE750_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE750_PID : string;
  attribute LC_PROBE750_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101110";
  attribute LC_PROBE750_TYPE : integer;
  attribute LC_PROBE750_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE750_WIDTH : integer;
  attribute LC_PROBE750_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE751_IS_DATA : string;
  attribute LC_PROBE751_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE751_IS_TRIG : string;
  attribute LC_PROBE751_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE751_MU_CNT : integer;
  attribute LC_PROBE751_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE751_PID : string;
  attribute LC_PROBE751_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011101111";
  attribute LC_PROBE751_TYPE : integer;
  attribute LC_PROBE751_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE751_WIDTH : integer;
  attribute LC_PROBE751_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE752_IS_DATA : string;
  attribute LC_PROBE752_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE752_IS_TRIG : string;
  attribute LC_PROBE752_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE752_MU_CNT : integer;
  attribute LC_PROBE752_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE752_PID : string;
  attribute LC_PROBE752_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110000";
  attribute LC_PROBE752_TYPE : integer;
  attribute LC_PROBE752_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE752_WIDTH : integer;
  attribute LC_PROBE752_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE753_IS_DATA : string;
  attribute LC_PROBE753_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE753_IS_TRIG : string;
  attribute LC_PROBE753_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE753_MU_CNT : integer;
  attribute LC_PROBE753_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE753_PID : string;
  attribute LC_PROBE753_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110001";
  attribute LC_PROBE753_TYPE : integer;
  attribute LC_PROBE753_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE753_WIDTH : integer;
  attribute LC_PROBE753_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE754_IS_DATA : string;
  attribute LC_PROBE754_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE754_IS_TRIG : string;
  attribute LC_PROBE754_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE754_MU_CNT : integer;
  attribute LC_PROBE754_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE754_PID : string;
  attribute LC_PROBE754_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110010";
  attribute LC_PROBE754_TYPE : integer;
  attribute LC_PROBE754_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE754_WIDTH : integer;
  attribute LC_PROBE754_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE755_IS_DATA : string;
  attribute LC_PROBE755_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE755_IS_TRIG : string;
  attribute LC_PROBE755_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE755_MU_CNT : integer;
  attribute LC_PROBE755_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE755_PID : string;
  attribute LC_PROBE755_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110011";
  attribute LC_PROBE755_TYPE : integer;
  attribute LC_PROBE755_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE755_WIDTH : integer;
  attribute LC_PROBE755_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE756_IS_DATA : string;
  attribute LC_PROBE756_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE756_IS_TRIG : string;
  attribute LC_PROBE756_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE756_MU_CNT : integer;
  attribute LC_PROBE756_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE756_PID : string;
  attribute LC_PROBE756_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110100";
  attribute LC_PROBE756_TYPE : integer;
  attribute LC_PROBE756_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE756_WIDTH : integer;
  attribute LC_PROBE756_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE757_IS_DATA : string;
  attribute LC_PROBE757_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE757_IS_TRIG : string;
  attribute LC_PROBE757_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE757_MU_CNT : integer;
  attribute LC_PROBE757_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE757_PID : string;
  attribute LC_PROBE757_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110101";
  attribute LC_PROBE757_TYPE : integer;
  attribute LC_PROBE757_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE757_WIDTH : integer;
  attribute LC_PROBE757_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE758_IS_DATA : string;
  attribute LC_PROBE758_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE758_IS_TRIG : string;
  attribute LC_PROBE758_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE758_MU_CNT : integer;
  attribute LC_PROBE758_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE758_PID : string;
  attribute LC_PROBE758_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110110";
  attribute LC_PROBE758_TYPE : integer;
  attribute LC_PROBE758_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE758_WIDTH : integer;
  attribute LC_PROBE758_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE759_IS_DATA : string;
  attribute LC_PROBE759_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE759_IS_TRIG : string;
  attribute LC_PROBE759_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE759_MU_CNT : integer;
  attribute LC_PROBE759_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE759_PID : string;
  attribute LC_PROBE759_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011110111";
  attribute LC_PROBE759_TYPE : integer;
  attribute LC_PROBE759_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE759_WIDTH : integer;
  attribute LC_PROBE759_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE75_IS_DATA : string;
  attribute LC_PROBE75_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE75_IS_TRIG : string;
  attribute LC_PROBE75_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE75_MU_CNT : integer;
  attribute LC_PROBE75_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE75_PID : string;
  attribute LC_PROBE75_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001011";
  attribute LC_PROBE75_TYPE : integer;
  attribute LC_PROBE75_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE75_WIDTH : integer;
  attribute LC_PROBE75_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE760_IS_DATA : string;
  attribute LC_PROBE760_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE760_IS_TRIG : string;
  attribute LC_PROBE760_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE760_MU_CNT : integer;
  attribute LC_PROBE760_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE760_PID : string;
  attribute LC_PROBE760_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111000";
  attribute LC_PROBE760_TYPE : integer;
  attribute LC_PROBE760_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE760_WIDTH : integer;
  attribute LC_PROBE760_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE761_IS_DATA : string;
  attribute LC_PROBE761_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE761_IS_TRIG : string;
  attribute LC_PROBE761_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE761_MU_CNT : integer;
  attribute LC_PROBE761_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE761_PID : string;
  attribute LC_PROBE761_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111001";
  attribute LC_PROBE761_TYPE : integer;
  attribute LC_PROBE761_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE761_WIDTH : integer;
  attribute LC_PROBE761_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE762_IS_DATA : string;
  attribute LC_PROBE762_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE762_IS_TRIG : string;
  attribute LC_PROBE762_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE762_MU_CNT : integer;
  attribute LC_PROBE762_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE762_PID : string;
  attribute LC_PROBE762_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111010";
  attribute LC_PROBE762_TYPE : integer;
  attribute LC_PROBE762_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE762_WIDTH : integer;
  attribute LC_PROBE762_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE763_IS_DATA : string;
  attribute LC_PROBE763_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE763_IS_TRIG : string;
  attribute LC_PROBE763_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE763_MU_CNT : integer;
  attribute LC_PROBE763_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE763_PID : string;
  attribute LC_PROBE763_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111011";
  attribute LC_PROBE763_TYPE : integer;
  attribute LC_PROBE763_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE763_WIDTH : integer;
  attribute LC_PROBE763_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE764_IS_DATA : string;
  attribute LC_PROBE764_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE764_IS_TRIG : string;
  attribute LC_PROBE764_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE764_MU_CNT : integer;
  attribute LC_PROBE764_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE764_PID : string;
  attribute LC_PROBE764_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111100";
  attribute LC_PROBE764_TYPE : integer;
  attribute LC_PROBE764_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE764_WIDTH : integer;
  attribute LC_PROBE764_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE765_IS_DATA : string;
  attribute LC_PROBE765_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE765_IS_TRIG : string;
  attribute LC_PROBE765_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE765_MU_CNT : integer;
  attribute LC_PROBE765_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE765_PID : string;
  attribute LC_PROBE765_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111101";
  attribute LC_PROBE765_TYPE : integer;
  attribute LC_PROBE765_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE765_WIDTH : integer;
  attribute LC_PROBE765_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE766_IS_DATA : string;
  attribute LC_PROBE766_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE766_IS_TRIG : string;
  attribute LC_PROBE766_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE766_MU_CNT : integer;
  attribute LC_PROBE766_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE766_PID : string;
  attribute LC_PROBE766_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111110";
  attribute LC_PROBE766_TYPE : integer;
  attribute LC_PROBE766_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE766_WIDTH : integer;
  attribute LC_PROBE766_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE767_IS_DATA : string;
  attribute LC_PROBE767_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE767_IS_TRIG : string;
  attribute LC_PROBE767_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE767_MU_CNT : integer;
  attribute LC_PROBE767_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE767_PID : string;
  attribute LC_PROBE767_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001011111111";
  attribute LC_PROBE767_TYPE : integer;
  attribute LC_PROBE767_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE767_WIDTH : integer;
  attribute LC_PROBE767_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE768_IS_DATA : string;
  attribute LC_PROBE768_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE768_IS_TRIG : string;
  attribute LC_PROBE768_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE768_MU_CNT : integer;
  attribute LC_PROBE768_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE768_PID : string;
  attribute LC_PROBE768_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000000";
  attribute LC_PROBE768_TYPE : integer;
  attribute LC_PROBE768_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE768_WIDTH : integer;
  attribute LC_PROBE768_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE769_IS_DATA : string;
  attribute LC_PROBE769_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE769_IS_TRIG : string;
  attribute LC_PROBE769_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE769_MU_CNT : integer;
  attribute LC_PROBE769_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE769_PID : string;
  attribute LC_PROBE769_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000001";
  attribute LC_PROBE769_TYPE : integer;
  attribute LC_PROBE769_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE769_WIDTH : integer;
  attribute LC_PROBE769_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE76_IS_DATA : string;
  attribute LC_PROBE76_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE76_IS_TRIG : string;
  attribute LC_PROBE76_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE76_MU_CNT : integer;
  attribute LC_PROBE76_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE76_PID : string;
  attribute LC_PROBE76_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001100";
  attribute LC_PROBE76_TYPE : integer;
  attribute LC_PROBE76_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE76_WIDTH : integer;
  attribute LC_PROBE76_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE770_IS_DATA : string;
  attribute LC_PROBE770_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE770_IS_TRIG : string;
  attribute LC_PROBE770_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE770_MU_CNT : integer;
  attribute LC_PROBE770_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE770_PID : string;
  attribute LC_PROBE770_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000010";
  attribute LC_PROBE770_TYPE : integer;
  attribute LC_PROBE770_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE770_WIDTH : integer;
  attribute LC_PROBE770_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE771_IS_DATA : string;
  attribute LC_PROBE771_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE771_IS_TRIG : string;
  attribute LC_PROBE771_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE771_MU_CNT : integer;
  attribute LC_PROBE771_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE771_PID : string;
  attribute LC_PROBE771_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000011";
  attribute LC_PROBE771_TYPE : integer;
  attribute LC_PROBE771_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE771_WIDTH : integer;
  attribute LC_PROBE771_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE772_IS_DATA : string;
  attribute LC_PROBE772_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE772_IS_TRIG : string;
  attribute LC_PROBE772_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE772_MU_CNT : integer;
  attribute LC_PROBE772_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE772_PID : string;
  attribute LC_PROBE772_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000100";
  attribute LC_PROBE772_TYPE : integer;
  attribute LC_PROBE772_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE772_WIDTH : integer;
  attribute LC_PROBE772_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE773_IS_DATA : string;
  attribute LC_PROBE773_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE773_IS_TRIG : string;
  attribute LC_PROBE773_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE773_MU_CNT : integer;
  attribute LC_PROBE773_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE773_PID : string;
  attribute LC_PROBE773_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000101";
  attribute LC_PROBE773_TYPE : integer;
  attribute LC_PROBE773_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE773_WIDTH : integer;
  attribute LC_PROBE773_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE774_IS_DATA : string;
  attribute LC_PROBE774_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE774_IS_TRIG : string;
  attribute LC_PROBE774_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE774_MU_CNT : integer;
  attribute LC_PROBE774_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE774_PID : string;
  attribute LC_PROBE774_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000110";
  attribute LC_PROBE774_TYPE : integer;
  attribute LC_PROBE774_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE774_WIDTH : integer;
  attribute LC_PROBE774_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE775_IS_DATA : string;
  attribute LC_PROBE775_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE775_IS_TRIG : string;
  attribute LC_PROBE775_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE775_MU_CNT : integer;
  attribute LC_PROBE775_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE775_PID : string;
  attribute LC_PROBE775_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100000111";
  attribute LC_PROBE775_TYPE : integer;
  attribute LC_PROBE775_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE775_WIDTH : integer;
  attribute LC_PROBE775_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE776_IS_DATA : string;
  attribute LC_PROBE776_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE776_IS_TRIG : string;
  attribute LC_PROBE776_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE776_MU_CNT : integer;
  attribute LC_PROBE776_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE776_PID : string;
  attribute LC_PROBE776_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001000";
  attribute LC_PROBE776_TYPE : integer;
  attribute LC_PROBE776_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE776_WIDTH : integer;
  attribute LC_PROBE776_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE777_IS_DATA : string;
  attribute LC_PROBE777_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE777_IS_TRIG : string;
  attribute LC_PROBE777_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE777_MU_CNT : integer;
  attribute LC_PROBE777_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE777_PID : string;
  attribute LC_PROBE777_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001001";
  attribute LC_PROBE777_TYPE : integer;
  attribute LC_PROBE777_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE777_WIDTH : integer;
  attribute LC_PROBE777_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE778_IS_DATA : string;
  attribute LC_PROBE778_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE778_IS_TRIG : string;
  attribute LC_PROBE778_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE778_MU_CNT : integer;
  attribute LC_PROBE778_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE778_PID : string;
  attribute LC_PROBE778_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001010";
  attribute LC_PROBE778_TYPE : integer;
  attribute LC_PROBE778_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE778_WIDTH : integer;
  attribute LC_PROBE778_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE779_IS_DATA : string;
  attribute LC_PROBE779_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE779_IS_TRIG : string;
  attribute LC_PROBE779_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE779_MU_CNT : integer;
  attribute LC_PROBE779_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE779_PID : string;
  attribute LC_PROBE779_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001011";
  attribute LC_PROBE779_TYPE : integer;
  attribute LC_PROBE779_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE779_WIDTH : integer;
  attribute LC_PROBE779_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE77_IS_DATA : string;
  attribute LC_PROBE77_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE77_IS_TRIG : string;
  attribute LC_PROBE77_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE77_MU_CNT : integer;
  attribute LC_PROBE77_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE77_PID : string;
  attribute LC_PROBE77_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001101";
  attribute LC_PROBE77_TYPE : integer;
  attribute LC_PROBE77_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE77_WIDTH : integer;
  attribute LC_PROBE77_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE780_IS_DATA : string;
  attribute LC_PROBE780_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE780_IS_TRIG : string;
  attribute LC_PROBE780_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE780_MU_CNT : integer;
  attribute LC_PROBE780_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE780_PID : string;
  attribute LC_PROBE780_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001100";
  attribute LC_PROBE780_TYPE : integer;
  attribute LC_PROBE780_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE780_WIDTH : integer;
  attribute LC_PROBE780_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE781_IS_DATA : string;
  attribute LC_PROBE781_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE781_IS_TRIG : string;
  attribute LC_PROBE781_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE781_MU_CNT : integer;
  attribute LC_PROBE781_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE781_PID : string;
  attribute LC_PROBE781_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001101";
  attribute LC_PROBE781_TYPE : integer;
  attribute LC_PROBE781_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE781_WIDTH : integer;
  attribute LC_PROBE781_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE782_IS_DATA : string;
  attribute LC_PROBE782_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE782_IS_TRIG : string;
  attribute LC_PROBE782_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE782_MU_CNT : integer;
  attribute LC_PROBE782_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE782_PID : string;
  attribute LC_PROBE782_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001110";
  attribute LC_PROBE782_TYPE : integer;
  attribute LC_PROBE782_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE782_WIDTH : integer;
  attribute LC_PROBE782_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE783_IS_DATA : string;
  attribute LC_PROBE783_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE783_IS_TRIG : string;
  attribute LC_PROBE783_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE783_MU_CNT : integer;
  attribute LC_PROBE783_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE783_PID : string;
  attribute LC_PROBE783_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100001111";
  attribute LC_PROBE783_TYPE : integer;
  attribute LC_PROBE783_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE783_WIDTH : integer;
  attribute LC_PROBE783_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE784_IS_DATA : string;
  attribute LC_PROBE784_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE784_IS_TRIG : string;
  attribute LC_PROBE784_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE784_MU_CNT : integer;
  attribute LC_PROBE784_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE784_PID : string;
  attribute LC_PROBE784_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010000";
  attribute LC_PROBE784_TYPE : integer;
  attribute LC_PROBE784_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE784_WIDTH : integer;
  attribute LC_PROBE784_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE785_IS_DATA : string;
  attribute LC_PROBE785_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE785_IS_TRIG : string;
  attribute LC_PROBE785_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE785_MU_CNT : integer;
  attribute LC_PROBE785_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE785_PID : string;
  attribute LC_PROBE785_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010001";
  attribute LC_PROBE785_TYPE : integer;
  attribute LC_PROBE785_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE785_WIDTH : integer;
  attribute LC_PROBE785_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE786_IS_DATA : string;
  attribute LC_PROBE786_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE786_IS_TRIG : string;
  attribute LC_PROBE786_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE786_MU_CNT : integer;
  attribute LC_PROBE786_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE786_PID : string;
  attribute LC_PROBE786_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010010";
  attribute LC_PROBE786_TYPE : integer;
  attribute LC_PROBE786_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE786_WIDTH : integer;
  attribute LC_PROBE786_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE787_IS_DATA : string;
  attribute LC_PROBE787_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE787_IS_TRIG : string;
  attribute LC_PROBE787_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE787_MU_CNT : integer;
  attribute LC_PROBE787_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE787_PID : string;
  attribute LC_PROBE787_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010011";
  attribute LC_PROBE787_TYPE : integer;
  attribute LC_PROBE787_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE787_WIDTH : integer;
  attribute LC_PROBE787_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE788_IS_DATA : string;
  attribute LC_PROBE788_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE788_IS_TRIG : string;
  attribute LC_PROBE788_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE788_MU_CNT : integer;
  attribute LC_PROBE788_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE788_PID : string;
  attribute LC_PROBE788_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010100";
  attribute LC_PROBE788_TYPE : integer;
  attribute LC_PROBE788_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE788_WIDTH : integer;
  attribute LC_PROBE788_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE789_IS_DATA : string;
  attribute LC_PROBE789_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE789_IS_TRIG : string;
  attribute LC_PROBE789_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE789_MU_CNT : integer;
  attribute LC_PROBE789_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE789_PID : string;
  attribute LC_PROBE789_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010101";
  attribute LC_PROBE789_TYPE : integer;
  attribute LC_PROBE789_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE789_WIDTH : integer;
  attribute LC_PROBE789_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE78_IS_DATA : string;
  attribute LC_PROBE78_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE78_IS_TRIG : string;
  attribute LC_PROBE78_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE78_MU_CNT : integer;
  attribute LC_PROBE78_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE78_PID : string;
  attribute LC_PROBE78_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001110";
  attribute LC_PROBE78_TYPE : integer;
  attribute LC_PROBE78_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE78_WIDTH : integer;
  attribute LC_PROBE78_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE790_IS_DATA : string;
  attribute LC_PROBE790_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE790_IS_TRIG : string;
  attribute LC_PROBE790_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE790_MU_CNT : integer;
  attribute LC_PROBE790_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE790_PID : string;
  attribute LC_PROBE790_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010110";
  attribute LC_PROBE790_TYPE : integer;
  attribute LC_PROBE790_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE790_WIDTH : integer;
  attribute LC_PROBE790_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE791_IS_DATA : string;
  attribute LC_PROBE791_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE791_IS_TRIG : string;
  attribute LC_PROBE791_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE791_MU_CNT : integer;
  attribute LC_PROBE791_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE791_PID : string;
  attribute LC_PROBE791_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100010111";
  attribute LC_PROBE791_TYPE : integer;
  attribute LC_PROBE791_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE791_WIDTH : integer;
  attribute LC_PROBE791_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE792_IS_DATA : string;
  attribute LC_PROBE792_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE792_IS_TRIG : string;
  attribute LC_PROBE792_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE792_MU_CNT : integer;
  attribute LC_PROBE792_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE792_PID : string;
  attribute LC_PROBE792_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011000";
  attribute LC_PROBE792_TYPE : integer;
  attribute LC_PROBE792_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE792_WIDTH : integer;
  attribute LC_PROBE792_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE793_IS_DATA : string;
  attribute LC_PROBE793_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE793_IS_TRIG : string;
  attribute LC_PROBE793_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE793_MU_CNT : integer;
  attribute LC_PROBE793_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE793_PID : string;
  attribute LC_PROBE793_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011001";
  attribute LC_PROBE793_TYPE : integer;
  attribute LC_PROBE793_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE793_WIDTH : integer;
  attribute LC_PROBE793_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE794_IS_DATA : string;
  attribute LC_PROBE794_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE794_IS_TRIG : string;
  attribute LC_PROBE794_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE794_MU_CNT : integer;
  attribute LC_PROBE794_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE794_PID : string;
  attribute LC_PROBE794_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011010";
  attribute LC_PROBE794_TYPE : integer;
  attribute LC_PROBE794_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE794_WIDTH : integer;
  attribute LC_PROBE794_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE795_IS_DATA : string;
  attribute LC_PROBE795_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE795_IS_TRIG : string;
  attribute LC_PROBE795_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE795_MU_CNT : integer;
  attribute LC_PROBE795_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE795_PID : string;
  attribute LC_PROBE795_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011011";
  attribute LC_PROBE795_TYPE : integer;
  attribute LC_PROBE795_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE795_WIDTH : integer;
  attribute LC_PROBE795_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE796_IS_DATA : string;
  attribute LC_PROBE796_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE796_IS_TRIG : string;
  attribute LC_PROBE796_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE796_MU_CNT : integer;
  attribute LC_PROBE796_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE796_PID : string;
  attribute LC_PROBE796_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011100";
  attribute LC_PROBE796_TYPE : integer;
  attribute LC_PROBE796_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE796_WIDTH : integer;
  attribute LC_PROBE796_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE797_IS_DATA : string;
  attribute LC_PROBE797_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE797_IS_TRIG : string;
  attribute LC_PROBE797_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE797_MU_CNT : integer;
  attribute LC_PROBE797_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE797_PID : string;
  attribute LC_PROBE797_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011101";
  attribute LC_PROBE797_TYPE : integer;
  attribute LC_PROBE797_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE797_WIDTH : integer;
  attribute LC_PROBE797_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE798_IS_DATA : string;
  attribute LC_PROBE798_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE798_IS_TRIG : string;
  attribute LC_PROBE798_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE798_MU_CNT : integer;
  attribute LC_PROBE798_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE798_PID : string;
  attribute LC_PROBE798_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011110";
  attribute LC_PROBE798_TYPE : integer;
  attribute LC_PROBE798_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE798_WIDTH : integer;
  attribute LC_PROBE798_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE799_IS_DATA : string;
  attribute LC_PROBE799_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE799_IS_TRIG : string;
  attribute LC_PROBE799_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE799_MU_CNT : integer;
  attribute LC_PROBE799_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE799_PID : string;
  attribute LC_PROBE799_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100011111";
  attribute LC_PROBE799_TYPE : integer;
  attribute LC_PROBE799_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE799_WIDTH : integer;
  attribute LC_PROBE799_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE79_IS_DATA : string;
  attribute LC_PROBE79_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE79_IS_TRIG : string;
  attribute LC_PROBE79_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE79_MU_CNT : integer;
  attribute LC_PROBE79_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE79_PID : string;
  attribute LC_PROBE79_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001001111";
  attribute LC_PROBE79_TYPE : integer;
  attribute LC_PROBE79_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE79_WIDTH : integer;
  attribute LC_PROBE79_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE7_IS_DATA : string;
  attribute LC_PROBE7_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE7_IS_TRIG : string;
  attribute LC_PROBE7_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE7_MU_CNT : integer;
  attribute LC_PROBE7_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE7_PID : string;
  attribute LC_PROBE7_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000000111";
  attribute LC_PROBE7_TYPE : integer;
  attribute LC_PROBE7_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE7_WIDTH : integer;
  attribute LC_PROBE7_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE800_IS_DATA : string;
  attribute LC_PROBE800_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE800_IS_TRIG : string;
  attribute LC_PROBE800_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE800_MU_CNT : integer;
  attribute LC_PROBE800_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE800_PID : string;
  attribute LC_PROBE800_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100000";
  attribute LC_PROBE800_TYPE : integer;
  attribute LC_PROBE800_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE800_WIDTH : integer;
  attribute LC_PROBE800_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE801_IS_DATA : string;
  attribute LC_PROBE801_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE801_IS_TRIG : string;
  attribute LC_PROBE801_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE801_MU_CNT : integer;
  attribute LC_PROBE801_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE801_PID : string;
  attribute LC_PROBE801_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100001";
  attribute LC_PROBE801_TYPE : integer;
  attribute LC_PROBE801_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE801_WIDTH : integer;
  attribute LC_PROBE801_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE802_IS_DATA : string;
  attribute LC_PROBE802_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE802_IS_TRIG : string;
  attribute LC_PROBE802_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE802_MU_CNT : integer;
  attribute LC_PROBE802_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE802_PID : string;
  attribute LC_PROBE802_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100010";
  attribute LC_PROBE802_TYPE : integer;
  attribute LC_PROBE802_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE802_WIDTH : integer;
  attribute LC_PROBE802_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE803_IS_DATA : string;
  attribute LC_PROBE803_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE803_IS_TRIG : string;
  attribute LC_PROBE803_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE803_MU_CNT : integer;
  attribute LC_PROBE803_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE803_PID : string;
  attribute LC_PROBE803_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100011";
  attribute LC_PROBE803_TYPE : integer;
  attribute LC_PROBE803_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE803_WIDTH : integer;
  attribute LC_PROBE803_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE804_IS_DATA : string;
  attribute LC_PROBE804_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE804_IS_TRIG : string;
  attribute LC_PROBE804_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE804_MU_CNT : integer;
  attribute LC_PROBE804_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE804_PID : string;
  attribute LC_PROBE804_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100100";
  attribute LC_PROBE804_TYPE : integer;
  attribute LC_PROBE804_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE804_WIDTH : integer;
  attribute LC_PROBE804_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE805_IS_DATA : string;
  attribute LC_PROBE805_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE805_IS_TRIG : string;
  attribute LC_PROBE805_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE805_MU_CNT : integer;
  attribute LC_PROBE805_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE805_PID : string;
  attribute LC_PROBE805_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100101";
  attribute LC_PROBE805_TYPE : integer;
  attribute LC_PROBE805_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE805_WIDTH : integer;
  attribute LC_PROBE805_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE806_IS_DATA : string;
  attribute LC_PROBE806_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE806_IS_TRIG : string;
  attribute LC_PROBE806_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE806_MU_CNT : integer;
  attribute LC_PROBE806_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE806_PID : string;
  attribute LC_PROBE806_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100110";
  attribute LC_PROBE806_TYPE : integer;
  attribute LC_PROBE806_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE806_WIDTH : integer;
  attribute LC_PROBE806_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE807_IS_DATA : string;
  attribute LC_PROBE807_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE807_IS_TRIG : string;
  attribute LC_PROBE807_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE807_MU_CNT : integer;
  attribute LC_PROBE807_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE807_PID : string;
  attribute LC_PROBE807_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100100111";
  attribute LC_PROBE807_TYPE : integer;
  attribute LC_PROBE807_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE807_WIDTH : integer;
  attribute LC_PROBE807_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE808_IS_DATA : string;
  attribute LC_PROBE808_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE808_IS_TRIG : string;
  attribute LC_PROBE808_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE808_MU_CNT : integer;
  attribute LC_PROBE808_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE808_PID : string;
  attribute LC_PROBE808_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101000";
  attribute LC_PROBE808_TYPE : integer;
  attribute LC_PROBE808_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE808_WIDTH : integer;
  attribute LC_PROBE808_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE809_IS_DATA : string;
  attribute LC_PROBE809_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE809_IS_TRIG : string;
  attribute LC_PROBE809_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE809_MU_CNT : integer;
  attribute LC_PROBE809_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE809_PID : string;
  attribute LC_PROBE809_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101001";
  attribute LC_PROBE809_TYPE : integer;
  attribute LC_PROBE809_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE809_WIDTH : integer;
  attribute LC_PROBE809_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE80_IS_DATA : string;
  attribute LC_PROBE80_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE80_IS_TRIG : string;
  attribute LC_PROBE80_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE80_MU_CNT : integer;
  attribute LC_PROBE80_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE80_PID : string;
  attribute LC_PROBE80_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010000";
  attribute LC_PROBE80_TYPE : integer;
  attribute LC_PROBE80_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE80_WIDTH : integer;
  attribute LC_PROBE80_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE810_IS_DATA : string;
  attribute LC_PROBE810_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE810_IS_TRIG : string;
  attribute LC_PROBE810_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE810_MU_CNT : integer;
  attribute LC_PROBE810_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE810_PID : string;
  attribute LC_PROBE810_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101010";
  attribute LC_PROBE810_TYPE : integer;
  attribute LC_PROBE810_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE810_WIDTH : integer;
  attribute LC_PROBE810_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE811_IS_DATA : string;
  attribute LC_PROBE811_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE811_IS_TRIG : string;
  attribute LC_PROBE811_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE811_MU_CNT : integer;
  attribute LC_PROBE811_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE811_PID : string;
  attribute LC_PROBE811_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101011";
  attribute LC_PROBE811_TYPE : integer;
  attribute LC_PROBE811_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE811_WIDTH : integer;
  attribute LC_PROBE811_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE812_IS_DATA : string;
  attribute LC_PROBE812_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE812_IS_TRIG : string;
  attribute LC_PROBE812_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE812_MU_CNT : integer;
  attribute LC_PROBE812_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE812_PID : string;
  attribute LC_PROBE812_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101100";
  attribute LC_PROBE812_TYPE : integer;
  attribute LC_PROBE812_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE812_WIDTH : integer;
  attribute LC_PROBE812_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE813_IS_DATA : string;
  attribute LC_PROBE813_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE813_IS_TRIG : string;
  attribute LC_PROBE813_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE813_MU_CNT : integer;
  attribute LC_PROBE813_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE813_PID : string;
  attribute LC_PROBE813_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101101";
  attribute LC_PROBE813_TYPE : integer;
  attribute LC_PROBE813_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE813_WIDTH : integer;
  attribute LC_PROBE813_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE814_IS_DATA : string;
  attribute LC_PROBE814_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE814_IS_TRIG : string;
  attribute LC_PROBE814_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE814_MU_CNT : integer;
  attribute LC_PROBE814_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE814_PID : string;
  attribute LC_PROBE814_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101110";
  attribute LC_PROBE814_TYPE : integer;
  attribute LC_PROBE814_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE814_WIDTH : integer;
  attribute LC_PROBE814_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE815_IS_DATA : string;
  attribute LC_PROBE815_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE815_IS_TRIG : string;
  attribute LC_PROBE815_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE815_MU_CNT : integer;
  attribute LC_PROBE815_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE815_PID : string;
  attribute LC_PROBE815_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100101111";
  attribute LC_PROBE815_TYPE : integer;
  attribute LC_PROBE815_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE815_WIDTH : integer;
  attribute LC_PROBE815_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE816_IS_DATA : string;
  attribute LC_PROBE816_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE816_IS_TRIG : string;
  attribute LC_PROBE816_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE816_MU_CNT : integer;
  attribute LC_PROBE816_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE816_PID : string;
  attribute LC_PROBE816_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110000";
  attribute LC_PROBE816_TYPE : integer;
  attribute LC_PROBE816_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE816_WIDTH : integer;
  attribute LC_PROBE816_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE817_IS_DATA : string;
  attribute LC_PROBE817_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE817_IS_TRIG : string;
  attribute LC_PROBE817_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE817_MU_CNT : integer;
  attribute LC_PROBE817_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE817_PID : string;
  attribute LC_PROBE817_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110001";
  attribute LC_PROBE817_TYPE : integer;
  attribute LC_PROBE817_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE817_WIDTH : integer;
  attribute LC_PROBE817_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE818_IS_DATA : string;
  attribute LC_PROBE818_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE818_IS_TRIG : string;
  attribute LC_PROBE818_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE818_MU_CNT : integer;
  attribute LC_PROBE818_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE818_PID : string;
  attribute LC_PROBE818_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110010";
  attribute LC_PROBE818_TYPE : integer;
  attribute LC_PROBE818_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE818_WIDTH : integer;
  attribute LC_PROBE818_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE819_IS_DATA : string;
  attribute LC_PROBE819_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE819_IS_TRIG : string;
  attribute LC_PROBE819_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE819_MU_CNT : integer;
  attribute LC_PROBE819_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE819_PID : string;
  attribute LC_PROBE819_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110011";
  attribute LC_PROBE819_TYPE : integer;
  attribute LC_PROBE819_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE819_WIDTH : integer;
  attribute LC_PROBE819_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE81_IS_DATA : string;
  attribute LC_PROBE81_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE81_IS_TRIG : string;
  attribute LC_PROBE81_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE81_MU_CNT : integer;
  attribute LC_PROBE81_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE81_PID : string;
  attribute LC_PROBE81_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010001";
  attribute LC_PROBE81_TYPE : integer;
  attribute LC_PROBE81_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE81_WIDTH : integer;
  attribute LC_PROBE81_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE820_IS_DATA : string;
  attribute LC_PROBE820_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE820_IS_TRIG : string;
  attribute LC_PROBE820_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE820_MU_CNT : integer;
  attribute LC_PROBE820_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE820_PID : string;
  attribute LC_PROBE820_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110100";
  attribute LC_PROBE820_TYPE : integer;
  attribute LC_PROBE820_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE820_WIDTH : integer;
  attribute LC_PROBE820_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE821_IS_DATA : string;
  attribute LC_PROBE821_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE821_IS_TRIG : string;
  attribute LC_PROBE821_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE821_MU_CNT : integer;
  attribute LC_PROBE821_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE821_PID : string;
  attribute LC_PROBE821_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110101";
  attribute LC_PROBE821_TYPE : integer;
  attribute LC_PROBE821_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE821_WIDTH : integer;
  attribute LC_PROBE821_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE822_IS_DATA : string;
  attribute LC_PROBE822_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE822_IS_TRIG : string;
  attribute LC_PROBE822_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE822_MU_CNT : integer;
  attribute LC_PROBE822_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE822_PID : string;
  attribute LC_PROBE822_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110110";
  attribute LC_PROBE822_TYPE : integer;
  attribute LC_PROBE822_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE822_WIDTH : integer;
  attribute LC_PROBE822_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE823_IS_DATA : string;
  attribute LC_PROBE823_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE823_IS_TRIG : string;
  attribute LC_PROBE823_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE823_MU_CNT : integer;
  attribute LC_PROBE823_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE823_PID : string;
  attribute LC_PROBE823_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100110111";
  attribute LC_PROBE823_TYPE : integer;
  attribute LC_PROBE823_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE823_WIDTH : integer;
  attribute LC_PROBE823_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE824_IS_DATA : string;
  attribute LC_PROBE824_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE824_IS_TRIG : string;
  attribute LC_PROBE824_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE824_MU_CNT : integer;
  attribute LC_PROBE824_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE824_PID : string;
  attribute LC_PROBE824_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111000";
  attribute LC_PROBE824_TYPE : integer;
  attribute LC_PROBE824_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE824_WIDTH : integer;
  attribute LC_PROBE824_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE825_IS_DATA : string;
  attribute LC_PROBE825_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE825_IS_TRIG : string;
  attribute LC_PROBE825_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE825_MU_CNT : integer;
  attribute LC_PROBE825_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE825_PID : string;
  attribute LC_PROBE825_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111001";
  attribute LC_PROBE825_TYPE : integer;
  attribute LC_PROBE825_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE825_WIDTH : integer;
  attribute LC_PROBE825_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE826_IS_DATA : string;
  attribute LC_PROBE826_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE826_IS_TRIG : string;
  attribute LC_PROBE826_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE826_MU_CNT : integer;
  attribute LC_PROBE826_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE826_PID : string;
  attribute LC_PROBE826_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111010";
  attribute LC_PROBE826_TYPE : integer;
  attribute LC_PROBE826_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE826_WIDTH : integer;
  attribute LC_PROBE826_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE827_IS_DATA : string;
  attribute LC_PROBE827_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE827_IS_TRIG : string;
  attribute LC_PROBE827_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE827_MU_CNT : integer;
  attribute LC_PROBE827_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE827_PID : string;
  attribute LC_PROBE827_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111011";
  attribute LC_PROBE827_TYPE : integer;
  attribute LC_PROBE827_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE827_WIDTH : integer;
  attribute LC_PROBE827_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE828_IS_DATA : string;
  attribute LC_PROBE828_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE828_IS_TRIG : string;
  attribute LC_PROBE828_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE828_MU_CNT : integer;
  attribute LC_PROBE828_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE828_PID : string;
  attribute LC_PROBE828_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111100";
  attribute LC_PROBE828_TYPE : integer;
  attribute LC_PROBE828_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE828_WIDTH : integer;
  attribute LC_PROBE828_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE829_IS_DATA : string;
  attribute LC_PROBE829_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE829_IS_TRIG : string;
  attribute LC_PROBE829_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE829_MU_CNT : integer;
  attribute LC_PROBE829_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE829_PID : string;
  attribute LC_PROBE829_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111101";
  attribute LC_PROBE829_TYPE : integer;
  attribute LC_PROBE829_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE829_WIDTH : integer;
  attribute LC_PROBE829_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE82_IS_DATA : string;
  attribute LC_PROBE82_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE82_IS_TRIG : string;
  attribute LC_PROBE82_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE82_MU_CNT : integer;
  attribute LC_PROBE82_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE82_PID : string;
  attribute LC_PROBE82_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010010";
  attribute LC_PROBE82_TYPE : integer;
  attribute LC_PROBE82_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE82_WIDTH : integer;
  attribute LC_PROBE82_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE830_IS_DATA : string;
  attribute LC_PROBE830_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE830_IS_TRIG : string;
  attribute LC_PROBE830_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE830_MU_CNT : integer;
  attribute LC_PROBE830_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE830_PID : string;
  attribute LC_PROBE830_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111110";
  attribute LC_PROBE830_TYPE : integer;
  attribute LC_PROBE830_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE830_WIDTH : integer;
  attribute LC_PROBE830_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE831_IS_DATA : string;
  attribute LC_PROBE831_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE831_IS_TRIG : string;
  attribute LC_PROBE831_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE831_MU_CNT : integer;
  attribute LC_PROBE831_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE831_PID : string;
  attribute LC_PROBE831_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001100111111";
  attribute LC_PROBE831_TYPE : integer;
  attribute LC_PROBE831_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE831_WIDTH : integer;
  attribute LC_PROBE831_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE832_IS_DATA : string;
  attribute LC_PROBE832_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE832_IS_TRIG : string;
  attribute LC_PROBE832_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE832_MU_CNT : integer;
  attribute LC_PROBE832_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE832_PID : string;
  attribute LC_PROBE832_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000000";
  attribute LC_PROBE832_TYPE : integer;
  attribute LC_PROBE832_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE832_WIDTH : integer;
  attribute LC_PROBE832_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE833_IS_DATA : string;
  attribute LC_PROBE833_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE833_IS_TRIG : string;
  attribute LC_PROBE833_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE833_MU_CNT : integer;
  attribute LC_PROBE833_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE833_PID : string;
  attribute LC_PROBE833_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000001";
  attribute LC_PROBE833_TYPE : integer;
  attribute LC_PROBE833_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE833_WIDTH : integer;
  attribute LC_PROBE833_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE834_IS_DATA : string;
  attribute LC_PROBE834_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE834_IS_TRIG : string;
  attribute LC_PROBE834_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE834_MU_CNT : integer;
  attribute LC_PROBE834_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE834_PID : string;
  attribute LC_PROBE834_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000010";
  attribute LC_PROBE834_TYPE : integer;
  attribute LC_PROBE834_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE834_WIDTH : integer;
  attribute LC_PROBE834_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE835_IS_DATA : string;
  attribute LC_PROBE835_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE835_IS_TRIG : string;
  attribute LC_PROBE835_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE835_MU_CNT : integer;
  attribute LC_PROBE835_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE835_PID : string;
  attribute LC_PROBE835_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000011";
  attribute LC_PROBE835_TYPE : integer;
  attribute LC_PROBE835_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE835_WIDTH : integer;
  attribute LC_PROBE835_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE836_IS_DATA : string;
  attribute LC_PROBE836_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE836_IS_TRIG : string;
  attribute LC_PROBE836_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE836_MU_CNT : integer;
  attribute LC_PROBE836_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE836_PID : string;
  attribute LC_PROBE836_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000100";
  attribute LC_PROBE836_TYPE : integer;
  attribute LC_PROBE836_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE836_WIDTH : integer;
  attribute LC_PROBE836_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE837_IS_DATA : string;
  attribute LC_PROBE837_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE837_IS_TRIG : string;
  attribute LC_PROBE837_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE837_MU_CNT : integer;
  attribute LC_PROBE837_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE837_PID : string;
  attribute LC_PROBE837_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000101";
  attribute LC_PROBE837_TYPE : integer;
  attribute LC_PROBE837_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE837_WIDTH : integer;
  attribute LC_PROBE837_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE838_IS_DATA : string;
  attribute LC_PROBE838_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE838_IS_TRIG : string;
  attribute LC_PROBE838_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE838_MU_CNT : integer;
  attribute LC_PROBE838_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE838_PID : string;
  attribute LC_PROBE838_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000110";
  attribute LC_PROBE838_TYPE : integer;
  attribute LC_PROBE838_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE838_WIDTH : integer;
  attribute LC_PROBE838_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE839_IS_DATA : string;
  attribute LC_PROBE839_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE839_IS_TRIG : string;
  attribute LC_PROBE839_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE839_MU_CNT : integer;
  attribute LC_PROBE839_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE839_PID : string;
  attribute LC_PROBE839_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101000111";
  attribute LC_PROBE839_TYPE : integer;
  attribute LC_PROBE839_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE839_WIDTH : integer;
  attribute LC_PROBE839_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE83_IS_DATA : string;
  attribute LC_PROBE83_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE83_IS_TRIG : string;
  attribute LC_PROBE83_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE83_MU_CNT : integer;
  attribute LC_PROBE83_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE83_PID : string;
  attribute LC_PROBE83_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010011";
  attribute LC_PROBE83_TYPE : integer;
  attribute LC_PROBE83_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE83_WIDTH : integer;
  attribute LC_PROBE83_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE840_IS_DATA : string;
  attribute LC_PROBE840_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE840_IS_TRIG : string;
  attribute LC_PROBE840_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE840_MU_CNT : integer;
  attribute LC_PROBE840_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE840_PID : string;
  attribute LC_PROBE840_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001000";
  attribute LC_PROBE840_TYPE : integer;
  attribute LC_PROBE840_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE840_WIDTH : integer;
  attribute LC_PROBE840_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE841_IS_DATA : string;
  attribute LC_PROBE841_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE841_IS_TRIG : string;
  attribute LC_PROBE841_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE841_MU_CNT : integer;
  attribute LC_PROBE841_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE841_PID : string;
  attribute LC_PROBE841_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001001";
  attribute LC_PROBE841_TYPE : integer;
  attribute LC_PROBE841_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE841_WIDTH : integer;
  attribute LC_PROBE841_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE842_IS_DATA : string;
  attribute LC_PROBE842_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE842_IS_TRIG : string;
  attribute LC_PROBE842_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE842_MU_CNT : integer;
  attribute LC_PROBE842_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE842_PID : string;
  attribute LC_PROBE842_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001010";
  attribute LC_PROBE842_TYPE : integer;
  attribute LC_PROBE842_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE842_WIDTH : integer;
  attribute LC_PROBE842_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE843_IS_DATA : string;
  attribute LC_PROBE843_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE843_IS_TRIG : string;
  attribute LC_PROBE843_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE843_MU_CNT : integer;
  attribute LC_PROBE843_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE843_PID : string;
  attribute LC_PROBE843_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001011";
  attribute LC_PROBE843_TYPE : integer;
  attribute LC_PROBE843_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE843_WIDTH : integer;
  attribute LC_PROBE843_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE844_IS_DATA : string;
  attribute LC_PROBE844_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE844_IS_TRIG : string;
  attribute LC_PROBE844_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE844_MU_CNT : integer;
  attribute LC_PROBE844_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE844_PID : string;
  attribute LC_PROBE844_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001100";
  attribute LC_PROBE844_TYPE : integer;
  attribute LC_PROBE844_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE844_WIDTH : integer;
  attribute LC_PROBE844_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE845_IS_DATA : string;
  attribute LC_PROBE845_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE845_IS_TRIG : string;
  attribute LC_PROBE845_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE845_MU_CNT : integer;
  attribute LC_PROBE845_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE845_PID : string;
  attribute LC_PROBE845_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001101";
  attribute LC_PROBE845_TYPE : integer;
  attribute LC_PROBE845_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE845_WIDTH : integer;
  attribute LC_PROBE845_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE846_IS_DATA : string;
  attribute LC_PROBE846_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE846_IS_TRIG : string;
  attribute LC_PROBE846_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE846_MU_CNT : integer;
  attribute LC_PROBE846_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE846_PID : string;
  attribute LC_PROBE846_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001110";
  attribute LC_PROBE846_TYPE : integer;
  attribute LC_PROBE846_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE846_WIDTH : integer;
  attribute LC_PROBE846_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE847_IS_DATA : string;
  attribute LC_PROBE847_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE847_IS_TRIG : string;
  attribute LC_PROBE847_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE847_MU_CNT : integer;
  attribute LC_PROBE847_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE847_PID : string;
  attribute LC_PROBE847_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101001111";
  attribute LC_PROBE847_TYPE : integer;
  attribute LC_PROBE847_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE847_WIDTH : integer;
  attribute LC_PROBE847_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE848_IS_DATA : string;
  attribute LC_PROBE848_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE848_IS_TRIG : string;
  attribute LC_PROBE848_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE848_MU_CNT : integer;
  attribute LC_PROBE848_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE848_PID : string;
  attribute LC_PROBE848_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010000";
  attribute LC_PROBE848_TYPE : integer;
  attribute LC_PROBE848_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE848_WIDTH : integer;
  attribute LC_PROBE848_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE849_IS_DATA : string;
  attribute LC_PROBE849_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE849_IS_TRIG : string;
  attribute LC_PROBE849_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE849_MU_CNT : integer;
  attribute LC_PROBE849_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE849_PID : string;
  attribute LC_PROBE849_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010001";
  attribute LC_PROBE849_TYPE : integer;
  attribute LC_PROBE849_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE849_WIDTH : integer;
  attribute LC_PROBE849_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE84_IS_DATA : string;
  attribute LC_PROBE84_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE84_IS_TRIG : string;
  attribute LC_PROBE84_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE84_MU_CNT : integer;
  attribute LC_PROBE84_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE84_PID : string;
  attribute LC_PROBE84_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010100";
  attribute LC_PROBE84_TYPE : integer;
  attribute LC_PROBE84_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE84_WIDTH : integer;
  attribute LC_PROBE84_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE850_IS_DATA : string;
  attribute LC_PROBE850_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE850_IS_TRIG : string;
  attribute LC_PROBE850_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE850_MU_CNT : integer;
  attribute LC_PROBE850_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE850_PID : string;
  attribute LC_PROBE850_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010010";
  attribute LC_PROBE850_TYPE : integer;
  attribute LC_PROBE850_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE850_WIDTH : integer;
  attribute LC_PROBE850_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE851_IS_DATA : string;
  attribute LC_PROBE851_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE851_IS_TRIG : string;
  attribute LC_PROBE851_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE851_MU_CNT : integer;
  attribute LC_PROBE851_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE851_PID : string;
  attribute LC_PROBE851_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010011";
  attribute LC_PROBE851_TYPE : integer;
  attribute LC_PROBE851_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE851_WIDTH : integer;
  attribute LC_PROBE851_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE852_IS_DATA : string;
  attribute LC_PROBE852_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE852_IS_TRIG : string;
  attribute LC_PROBE852_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE852_MU_CNT : integer;
  attribute LC_PROBE852_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE852_PID : string;
  attribute LC_PROBE852_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010100";
  attribute LC_PROBE852_TYPE : integer;
  attribute LC_PROBE852_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE852_WIDTH : integer;
  attribute LC_PROBE852_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE853_IS_DATA : string;
  attribute LC_PROBE853_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE853_IS_TRIG : string;
  attribute LC_PROBE853_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE853_MU_CNT : integer;
  attribute LC_PROBE853_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE853_PID : string;
  attribute LC_PROBE853_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010101";
  attribute LC_PROBE853_TYPE : integer;
  attribute LC_PROBE853_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE853_WIDTH : integer;
  attribute LC_PROBE853_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE854_IS_DATA : string;
  attribute LC_PROBE854_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE854_IS_TRIG : string;
  attribute LC_PROBE854_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE854_MU_CNT : integer;
  attribute LC_PROBE854_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE854_PID : string;
  attribute LC_PROBE854_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010110";
  attribute LC_PROBE854_TYPE : integer;
  attribute LC_PROBE854_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE854_WIDTH : integer;
  attribute LC_PROBE854_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE855_IS_DATA : string;
  attribute LC_PROBE855_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE855_IS_TRIG : string;
  attribute LC_PROBE855_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE855_MU_CNT : integer;
  attribute LC_PROBE855_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE855_PID : string;
  attribute LC_PROBE855_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101010111";
  attribute LC_PROBE855_TYPE : integer;
  attribute LC_PROBE855_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE855_WIDTH : integer;
  attribute LC_PROBE855_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE856_IS_DATA : string;
  attribute LC_PROBE856_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE856_IS_TRIG : string;
  attribute LC_PROBE856_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE856_MU_CNT : integer;
  attribute LC_PROBE856_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE856_PID : string;
  attribute LC_PROBE856_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011000";
  attribute LC_PROBE856_TYPE : integer;
  attribute LC_PROBE856_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE856_WIDTH : integer;
  attribute LC_PROBE856_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE857_IS_DATA : string;
  attribute LC_PROBE857_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE857_IS_TRIG : string;
  attribute LC_PROBE857_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE857_MU_CNT : integer;
  attribute LC_PROBE857_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE857_PID : string;
  attribute LC_PROBE857_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011001";
  attribute LC_PROBE857_TYPE : integer;
  attribute LC_PROBE857_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE857_WIDTH : integer;
  attribute LC_PROBE857_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE858_IS_DATA : string;
  attribute LC_PROBE858_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE858_IS_TRIG : string;
  attribute LC_PROBE858_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE858_MU_CNT : integer;
  attribute LC_PROBE858_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE858_PID : string;
  attribute LC_PROBE858_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011010";
  attribute LC_PROBE858_TYPE : integer;
  attribute LC_PROBE858_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE858_WIDTH : integer;
  attribute LC_PROBE858_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE859_IS_DATA : string;
  attribute LC_PROBE859_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE859_IS_TRIG : string;
  attribute LC_PROBE859_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE859_MU_CNT : integer;
  attribute LC_PROBE859_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE859_PID : string;
  attribute LC_PROBE859_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011011";
  attribute LC_PROBE859_TYPE : integer;
  attribute LC_PROBE859_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE859_WIDTH : integer;
  attribute LC_PROBE859_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE85_IS_DATA : string;
  attribute LC_PROBE85_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE85_IS_TRIG : string;
  attribute LC_PROBE85_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE85_MU_CNT : integer;
  attribute LC_PROBE85_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE85_PID : string;
  attribute LC_PROBE85_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010101";
  attribute LC_PROBE85_TYPE : integer;
  attribute LC_PROBE85_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE85_WIDTH : integer;
  attribute LC_PROBE85_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE860_IS_DATA : string;
  attribute LC_PROBE860_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE860_IS_TRIG : string;
  attribute LC_PROBE860_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE860_MU_CNT : integer;
  attribute LC_PROBE860_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE860_PID : string;
  attribute LC_PROBE860_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011100";
  attribute LC_PROBE860_TYPE : integer;
  attribute LC_PROBE860_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE860_WIDTH : integer;
  attribute LC_PROBE860_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE861_IS_DATA : string;
  attribute LC_PROBE861_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE861_IS_TRIG : string;
  attribute LC_PROBE861_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE861_MU_CNT : integer;
  attribute LC_PROBE861_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE861_PID : string;
  attribute LC_PROBE861_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011101";
  attribute LC_PROBE861_TYPE : integer;
  attribute LC_PROBE861_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE861_WIDTH : integer;
  attribute LC_PROBE861_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE862_IS_DATA : string;
  attribute LC_PROBE862_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE862_IS_TRIG : string;
  attribute LC_PROBE862_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE862_MU_CNT : integer;
  attribute LC_PROBE862_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE862_PID : string;
  attribute LC_PROBE862_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011110";
  attribute LC_PROBE862_TYPE : integer;
  attribute LC_PROBE862_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE862_WIDTH : integer;
  attribute LC_PROBE862_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE863_IS_DATA : string;
  attribute LC_PROBE863_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE863_IS_TRIG : string;
  attribute LC_PROBE863_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE863_MU_CNT : integer;
  attribute LC_PROBE863_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE863_PID : string;
  attribute LC_PROBE863_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101011111";
  attribute LC_PROBE863_TYPE : integer;
  attribute LC_PROBE863_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE863_WIDTH : integer;
  attribute LC_PROBE863_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE864_IS_DATA : string;
  attribute LC_PROBE864_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE864_IS_TRIG : string;
  attribute LC_PROBE864_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE864_MU_CNT : integer;
  attribute LC_PROBE864_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE864_PID : string;
  attribute LC_PROBE864_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100000";
  attribute LC_PROBE864_TYPE : integer;
  attribute LC_PROBE864_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE864_WIDTH : integer;
  attribute LC_PROBE864_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE865_IS_DATA : string;
  attribute LC_PROBE865_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE865_IS_TRIG : string;
  attribute LC_PROBE865_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE865_MU_CNT : integer;
  attribute LC_PROBE865_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE865_PID : string;
  attribute LC_PROBE865_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100001";
  attribute LC_PROBE865_TYPE : integer;
  attribute LC_PROBE865_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE865_WIDTH : integer;
  attribute LC_PROBE865_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE866_IS_DATA : string;
  attribute LC_PROBE866_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE866_IS_TRIG : string;
  attribute LC_PROBE866_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE866_MU_CNT : integer;
  attribute LC_PROBE866_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE866_PID : string;
  attribute LC_PROBE866_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100010";
  attribute LC_PROBE866_TYPE : integer;
  attribute LC_PROBE866_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE866_WIDTH : integer;
  attribute LC_PROBE866_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE867_IS_DATA : string;
  attribute LC_PROBE867_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE867_IS_TRIG : string;
  attribute LC_PROBE867_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE867_MU_CNT : integer;
  attribute LC_PROBE867_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE867_PID : string;
  attribute LC_PROBE867_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100011";
  attribute LC_PROBE867_TYPE : integer;
  attribute LC_PROBE867_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE867_WIDTH : integer;
  attribute LC_PROBE867_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE868_IS_DATA : string;
  attribute LC_PROBE868_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE868_IS_TRIG : string;
  attribute LC_PROBE868_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE868_MU_CNT : integer;
  attribute LC_PROBE868_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE868_PID : string;
  attribute LC_PROBE868_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100100";
  attribute LC_PROBE868_TYPE : integer;
  attribute LC_PROBE868_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE868_WIDTH : integer;
  attribute LC_PROBE868_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE869_IS_DATA : string;
  attribute LC_PROBE869_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE869_IS_TRIG : string;
  attribute LC_PROBE869_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE869_MU_CNT : integer;
  attribute LC_PROBE869_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE869_PID : string;
  attribute LC_PROBE869_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100101";
  attribute LC_PROBE869_TYPE : integer;
  attribute LC_PROBE869_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE869_WIDTH : integer;
  attribute LC_PROBE869_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE86_IS_DATA : string;
  attribute LC_PROBE86_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE86_IS_TRIG : string;
  attribute LC_PROBE86_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE86_MU_CNT : integer;
  attribute LC_PROBE86_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE86_PID : string;
  attribute LC_PROBE86_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010110";
  attribute LC_PROBE86_TYPE : integer;
  attribute LC_PROBE86_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE86_WIDTH : integer;
  attribute LC_PROBE86_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE870_IS_DATA : string;
  attribute LC_PROBE870_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE870_IS_TRIG : string;
  attribute LC_PROBE870_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE870_MU_CNT : integer;
  attribute LC_PROBE870_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE870_PID : string;
  attribute LC_PROBE870_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100110";
  attribute LC_PROBE870_TYPE : integer;
  attribute LC_PROBE870_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE870_WIDTH : integer;
  attribute LC_PROBE870_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE871_IS_DATA : string;
  attribute LC_PROBE871_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE871_IS_TRIG : string;
  attribute LC_PROBE871_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE871_MU_CNT : integer;
  attribute LC_PROBE871_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE871_PID : string;
  attribute LC_PROBE871_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101100111";
  attribute LC_PROBE871_TYPE : integer;
  attribute LC_PROBE871_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE871_WIDTH : integer;
  attribute LC_PROBE871_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE872_IS_DATA : string;
  attribute LC_PROBE872_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE872_IS_TRIG : string;
  attribute LC_PROBE872_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE872_MU_CNT : integer;
  attribute LC_PROBE872_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE872_PID : string;
  attribute LC_PROBE872_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101000";
  attribute LC_PROBE872_TYPE : integer;
  attribute LC_PROBE872_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE872_WIDTH : integer;
  attribute LC_PROBE872_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE873_IS_DATA : string;
  attribute LC_PROBE873_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE873_IS_TRIG : string;
  attribute LC_PROBE873_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE873_MU_CNT : integer;
  attribute LC_PROBE873_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE873_PID : string;
  attribute LC_PROBE873_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101001";
  attribute LC_PROBE873_TYPE : integer;
  attribute LC_PROBE873_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE873_WIDTH : integer;
  attribute LC_PROBE873_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE874_IS_DATA : string;
  attribute LC_PROBE874_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE874_IS_TRIG : string;
  attribute LC_PROBE874_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE874_MU_CNT : integer;
  attribute LC_PROBE874_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE874_PID : string;
  attribute LC_PROBE874_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101010";
  attribute LC_PROBE874_TYPE : integer;
  attribute LC_PROBE874_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE874_WIDTH : integer;
  attribute LC_PROBE874_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE875_IS_DATA : string;
  attribute LC_PROBE875_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE875_IS_TRIG : string;
  attribute LC_PROBE875_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE875_MU_CNT : integer;
  attribute LC_PROBE875_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE875_PID : string;
  attribute LC_PROBE875_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101011";
  attribute LC_PROBE875_TYPE : integer;
  attribute LC_PROBE875_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE875_WIDTH : integer;
  attribute LC_PROBE875_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE876_IS_DATA : string;
  attribute LC_PROBE876_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE876_IS_TRIG : string;
  attribute LC_PROBE876_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE876_MU_CNT : integer;
  attribute LC_PROBE876_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE876_PID : string;
  attribute LC_PROBE876_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101100";
  attribute LC_PROBE876_TYPE : integer;
  attribute LC_PROBE876_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE876_WIDTH : integer;
  attribute LC_PROBE876_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE877_IS_DATA : string;
  attribute LC_PROBE877_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE877_IS_TRIG : string;
  attribute LC_PROBE877_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE877_MU_CNT : integer;
  attribute LC_PROBE877_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE877_PID : string;
  attribute LC_PROBE877_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101101";
  attribute LC_PROBE877_TYPE : integer;
  attribute LC_PROBE877_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE877_WIDTH : integer;
  attribute LC_PROBE877_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE878_IS_DATA : string;
  attribute LC_PROBE878_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE878_IS_TRIG : string;
  attribute LC_PROBE878_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE878_MU_CNT : integer;
  attribute LC_PROBE878_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE878_PID : string;
  attribute LC_PROBE878_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101110";
  attribute LC_PROBE878_TYPE : integer;
  attribute LC_PROBE878_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE878_WIDTH : integer;
  attribute LC_PROBE878_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE879_IS_DATA : string;
  attribute LC_PROBE879_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE879_IS_TRIG : string;
  attribute LC_PROBE879_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE879_MU_CNT : integer;
  attribute LC_PROBE879_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE879_PID : string;
  attribute LC_PROBE879_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101101111";
  attribute LC_PROBE879_TYPE : integer;
  attribute LC_PROBE879_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE879_WIDTH : integer;
  attribute LC_PROBE879_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE87_IS_DATA : string;
  attribute LC_PROBE87_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE87_IS_TRIG : string;
  attribute LC_PROBE87_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE87_MU_CNT : integer;
  attribute LC_PROBE87_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE87_PID : string;
  attribute LC_PROBE87_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001010111";
  attribute LC_PROBE87_TYPE : integer;
  attribute LC_PROBE87_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE87_WIDTH : integer;
  attribute LC_PROBE87_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE880_IS_DATA : string;
  attribute LC_PROBE880_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE880_IS_TRIG : string;
  attribute LC_PROBE880_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE880_MU_CNT : integer;
  attribute LC_PROBE880_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE880_PID : string;
  attribute LC_PROBE880_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110000";
  attribute LC_PROBE880_TYPE : integer;
  attribute LC_PROBE880_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE880_WIDTH : integer;
  attribute LC_PROBE880_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE881_IS_DATA : string;
  attribute LC_PROBE881_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE881_IS_TRIG : string;
  attribute LC_PROBE881_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE881_MU_CNT : integer;
  attribute LC_PROBE881_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE881_PID : string;
  attribute LC_PROBE881_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110001";
  attribute LC_PROBE881_TYPE : integer;
  attribute LC_PROBE881_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE881_WIDTH : integer;
  attribute LC_PROBE881_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE882_IS_DATA : string;
  attribute LC_PROBE882_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE882_IS_TRIG : string;
  attribute LC_PROBE882_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE882_MU_CNT : integer;
  attribute LC_PROBE882_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE882_PID : string;
  attribute LC_PROBE882_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110010";
  attribute LC_PROBE882_TYPE : integer;
  attribute LC_PROBE882_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE882_WIDTH : integer;
  attribute LC_PROBE882_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE883_IS_DATA : string;
  attribute LC_PROBE883_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE883_IS_TRIG : string;
  attribute LC_PROBE883_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE883_MU_CNT : integer;
  attribute LC_PROBE883_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE883_PID : string;
  attribute LC_PROBE883_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110011";
  attribute LC_PROBE883_TYPE : integer;
  attribute LC_PROBE883_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE883_WIDTH : integer;
  attribute LC_PROBE883_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE884_IS_DATA : string;
  attribute LC_PROBE884_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE884_IS_TRIG : string;
  attribute LC_PROBE884_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE884_MU_CNT : integer;
  attribute LC_PROBE884_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE884_PID : string;
  attribute LC_PROBE884_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110100";
  attribute LC_PROBE884_TYPE : integer;
  attribute LC_PROBE884_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE884_WIDTH : integer;
  attribute LC_PROBE884_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE885_IS_DATA : string;
  attribute LC_PROBE885_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE885_IS_TRIG : string;
  attribute LC_PROBE885_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE885_MU_CNT : integer;
  attribute LC_PROBE885_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE885_PID : string;
  attribute LC_PROBE885_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110101";
  attribute LC_PROBE885_TYPE : integer;
  attribute LC_PROBE885_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE885_WIDTH : integer;
  attribute LC_PROBE885_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE886_IS_DATA : string;
  attribute LC_PROBE886_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE886_IS_TRIG : string;
  attribute LC_PROBE886_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE886_MU_CNT : integer;
  attribute LC_PROBE886_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE886_PID : string;
  attribute LC_PROBE886_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110110";
  attribute LC_PROBE886_TYPE : integer;
  attribute LC_PROBE886_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE886_WIDTH : integer;
  attribute LC_PROBE886_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE887_IS_DATA : string;
  attribute LC_PROBE887_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE887_IS_TRIG : string;
  attribute LC_PROBE887_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE887_MU_CNT : integer;
  attribute LC_PROBE887_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE887_PID : string;
  attribute LC_PROBE887_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101110111";
  attribute LC_PROBE887_TYPE : integer;
  attribute LC_PROBE887_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE887_WIDTH : integer;
  attribute LC_PROBE887_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE888_IS_DATA : string;
  attribute LC_PROBE888_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE888_IS_TRIG : string;
  attribute LC_PROBE888_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE888_MU_CNT : integer;
  attribute LC_PROBE888_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE888_PID : string;
  attribute LC_PROBE888_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111000";
  attribute LC_PROBE888_TYPE : integer;
  attribute LC_PROBE888_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE888_WIDTH : integer;
  attribute LC_PROBE888_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE889_IS_DATA : string;
  attribute LC_PROBE889_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE889_IS_TRIG : string;
  attribute LC_PROBE889_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE889_MU_CNT : integer;
  attribute LC_PROBE889_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE889_PID : string;
  attribute LC_PROBE889_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111001";
  attribute LC_PROBE889_TYPE : integer;
  attribute LC_PROBE889_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE889_WIDTH : integer;
  attribute LC_PROBE889_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE88_IS_DATA : string;
  attribute LC_PROBE88_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE88_IS_TRIG : string;
  attribute LC_PROBE88_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE88_MU_CNT : integer;
  attribute LC_PROBE88_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE88_PID : string;
  attribute LC_PROBE88_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011000";
  attribute LC_PROBE88_TYPE : integer;
  attribute LC_PROBE88_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE88_WIDTH : integer;
  attribute LC_PROBE88_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE890_IS_DATA : string;
  attribute LC_PROBE890_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE890_IS_TRIG : string;
  attribute LC_PROBE890_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE890_MU_CNT : integer;
  attribute LC_PROBE890_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE890_PID : string;
  attribute LC_PROBE890_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111010";
  attribute LC_PROBE890_TYPE : integer;
  attribute LC_PROBE890_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE890_WIDTH : integer;
  attribute LC_PROBE890_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE891_IS_DATA : string;
  attribute LC_PROBE891_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE891_IS_TRIG : string;
  attribute LC_PROBE891_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE891_MU_CNT : integer;
  attribute LC_PROBE891_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE891_PID : string;
  attribute LC_PROBE891_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111011";
  attribute LC_PROBE891_TYPE : integer;
  attribute LC_PROBE891_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE891_WIDTH : integer;
  attribute LC_PROBE891_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE892_IS_DATA : string;
  attribute LC_PROBE892_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE892_IS_TRIG : string;
  attribute LC_PROBE892_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE892_MU_CNT : integer;
  attribute LC_PROBE892_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE892_PID : string;
  attribute LC_PROBE892_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111100";
  attribute LC_PROBE892_TYPE : integer;
  attribute LC_PROBE892_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE892_WIDTH : integer;
  attribute LC_PROBE892_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE893_IS_DATA : string;
  attribute LC_PROBE893_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE893_IS_TRIG : string;
  attribute LC_PROBE893_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE893_MU_CNT : integer;
  attribute LC_PROBE893_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE893_PID : string;
  attribute LC_PROBE893_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111101";
  attribute LC_PROBE893_TYPE : integer;
  attribute LC_PROBE893_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE893_WIDTH : integer;
  attribute LC_PROBE893_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE894_IS_DATA : string;
  attribute LC_PROBE894_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE894_IS_TRIG : string;
  attribute LC_PROBE894_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE894_MU_CNT : integer;
  attribute LC_PROBE894_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE894_PID : string;
  attribute LC_PROBE894_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111110";
  attribute LC_PROBE894_TYPE : integer;
  attribute LC_PROBE894_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE894_WIDTH : integer;
  attribute LC_PROBE894_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE895_IS_DATA : string;
  attribute LC_PROBE895_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE895_IS_TRIG : string;
  attribute LC_PROBE895_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE895_MU_CNT : integer;
  attribute LC_PROBE895_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE895_PID : string;
  attribute LC_PROBE895_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001101111111";
  attribute LC_PROBE895_TYPE : integer;
  attribute LC_PROBE895_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE895_WIDTH : integer;
  attribute LC_PROBE895_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE896_IS_DATA : string;
  attribute LC_PROBE896_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE896_IS_TRIG : string;
  attribute LC_PROBE896_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE896_MU_CNT : integer;
  attribute LC_PROBE896_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE896_PID : string;
  attribute LC_PROBE896_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000000";
  attribute LC_PROBE896_TYPE : integer;
  attribute LC_PROBE896_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE896_WIDTH : integer;
  attribute LC_PROBE896_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE897_IS_DATA : string;
  attribute LC_PROBE897_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE897_IS_TRIG : string;
  attribute LC_PROBE897_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE897_MU_CNT : integer;
  attribute LC_PROBE897_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE897_PID : string;
  attribute LC_PROBE897_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000001";
  attribute LC_PROBE897_TYPE : integer;
  attribute LC_PROBE897_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE897_WIDTH : integer;
  attribute LC_PROBE897_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE898_IS_DATA : string;
  attribute LC_PROBE898_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE898_IS_TRIG : string;
  attribute LC_PROBE898_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE898_MU_CNT : integer;
  attribute LC_PROBE898_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE898_PID : string;
  attribute LC_PROBE898_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000010";
  attribute LC_PROBE898_TYPE : integer;
  attribute LC_PROBE898_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE898_WIDTH : integer;
  attribute LC_PROBE898_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE899_IS_DATA : string;
  attribute LC_PROBE899_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE899_IS_TRIG : string;
  attribute LC_PROBE899_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE899_MU_CNT : integer;
  attribute LC_PROBE899_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE899_PID : string;
  attribute LC_PROBE899_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000011";
  attribute LC_PROBE899_TYPE : integer;
  attribute LC_PROBE899_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE899_WIDTH : integer;
  attribute LC_PROBE899_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE89_IS_DATA : string;
  attribute LC_PROBE89_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE89_IS_TRIG : string;
  attribute LC_PROBE89_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE89_MU_CNT : integer;
  attribute LC_PROBE89_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE89_PID : string;
  attribute LC_PROBE89_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011001";
  attribute LC_PROBE89_TYPE : integer;
  attribute LC_PROBE89_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE89_WIDTH : integer;
  attribute LC_PROBE89_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE8_IS_DATA : string;
  attribute LC_PROBE8_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE8_IS_TRIG : string;
  attribute LC_PROBE8_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE8_MU_CNT : integer;
  attribute LC_PROBE8_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE8_PID : string;
  attribute LC_PROBE8_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001000";
  attribute LC_PROBE8_TYPE : integer;
  attribute LC_PROBE8_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE8_WIDTH : integer;
  attribute LC_PROBE8_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE900_IS_DATA : string;
  attribute LC_PROBE900_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE900_IS_TRIG : string;
  attribute LC_PROBE900_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE900_MU_CNT : integer;
  attribute LC_PROBE900_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE900_PID : string;
  attribute LC_PROBE900_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000100";
  attribute LC_PROBE900_TYPE : integer;
  attribute LC_PROBE900_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE900_WIDTH : integer;
  attribute LC_PROBE900_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE901_IS_DATA : string;
  attribute LC_PROBE901_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE901_IS_TRIG : string;
  attribute LC_PROBE901_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE901_MU_CNT : integer;
  attribute LC_PROBE901_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE901_PID : string;
  attribute LC_PROBE901_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000101";
  attribute LC_PROBE901_TYPE : integer;
  attribute LC_PROBE901_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE901_WIDTH : integer;
  attribute LC_PROBE901_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE902_IS_DATA : string;
  attribute LC_PROBE902_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE902_IS_TRIG : string;
  attribute LC_PROBE902_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE902_MU_CNT : integer;
  attribute LC_PROBE902_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE902_PID : string;
  attribute LC_PROBE902_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000110";
  attribute LC_PROBE902_TYPE : integer;
  attribute LC_PROBE902_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE902_WIDTH : integer;
  attribute LC_PROBE902_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE903_IS_DATA : string;
  attribute LC_PROBE903_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE903_IS_TRIG : string;
  attribute LC_PROBE903_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE903_MU_CNT : integer;
  attribute LC_PROBE903_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE903_PID : string;
  attribute LC_PROBE903_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110000111";
  attribute LC_PROBE903_TYPE : integer;
  attribute LC_PROBE903_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE903_WIDTH : integer;
  attribute LC_PROBE903_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE904_IS_DATA : string;
  attribute LC_PROBE904_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE904_IS_TRIG : string;
  attribute LC_PROBE904_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE904_MU_CNT : integer;
  attribute LC_PROBE904_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE904_PID : string;
  attribute LC_PROBE904_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001000";
  attribute LC_PROBE904_TYPE : integer;
  attribute LC_PROBE904_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE904_WIDTH : integer;
  attribute LC_PROBE904_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE905_IS_DATA : string;
  attribute LC_PROBE905_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE905_IS_TRIG : string;
  attribute LC_PROBE905_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE905_MU_CNT : integer;
  attribute LC_PROBE905_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE905_PID : string;
  attribute LC_PROBE905_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001001";
  attribute LC_PROBE905_TYPE : integer;
  attribute LC_PROBE905_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE905_WIDTH : integer;
  attribute LC_PROBE905_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE906_IS_DATA : string;
  attribute LC_PROBE906_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE906_IS_TRIG : string;
  attribute LC_PROBE906_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE906_MU_CNT : integer;
  attribute LC_PROBE906_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE906_PID : string;
  attribute LC_PROBE906_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001010";
  attribute LC_PROBE906_TYPE : integer;
  attribute LC_PROBE906_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE906_WIDTH : integer;
  attribute LC_PROBE906_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE907_IS_DATA : string;
  attribute LC_PROBE907_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE907_IS_TRIG : string;
  attribute LC_PROBE907_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE907_MU_CNT : integer;
  attribute LC_PROBE907_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE907_PID : string;
  attribute LC_PROBE907_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001011";
  attribute LC_PROBE907_TYPE : integer;
  attribute LC_PROBE907_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE907_WIDTH : integer;
  attribute LC_PROBE907_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE908_IS_DATA : string;
  attribute LC_PROBE908_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE908_IS_TRIG : string;
  attribute LC_PROBE908_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE908_MU_CNT : integer;
  attribute LC_PROBE908_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE908_PID : string;
  attribute LC_PROBE908_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001100";
  attribute LC_PROBE908_TYPE : integer;
  attribute LC_PROBE908_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE908_WIDTH : integer;
  attribute LC_PROBE908_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE909_IS_DATA : string;
  attribute LC_PROBE909_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE909_IS_TRIG : string;
  attribute LC_PROBE909_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE909_MU_CNT : integer;
  attribute LC_PROBE909_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE909_PID : string;
  attribute LC_PROBE909_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001101";
  attribute LC_PROBE909_TYPE : integer;
  attribute LC_PROBE909_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE909_WIDTH : integer;
  attribute LC_PROBE909_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE90_IS_DATA : string;
  attribute LC_PROBE90_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE90_IS_TRIG : string;
  attribute LC_PROBE90_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE90_MU_CNT : integer;
  attribute LC_PROBE90_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE90_PID : string;
  attribute LC_PROBE90_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011010";
  attribute LC_PROBE90_TYPE : integer;
  attribute LC_PROBE90_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE90_WIDTH : integer;
  attribute LC_PROBE90_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE910_IS_DATA : string;
  attribute LC_PROBE910_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE910_IS_TRIG : string;
  attribute LC_PROBE910_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE910_MU_CNT : integer;
  attribute LC_PROBE910_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE910_PID : string;
  attribute LC_PROBE910_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001110";
  attribute LC_PROBE910_TYPE : integer;
  attribute LC_PROBE910_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE910_WIDTH : integer;
  attribute LC_PROBE910_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE911_IS_DATA : string;
  attribute LC_PROBE911_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE911_IS_TRIG : string;
  attribute LC_PROBE911_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE911_MU_CNT : integer;
  attribute LC_PROBE911_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE911_PID : string;
  attribute LC_PROBE911_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110001111";
  attribute LC_PROBE911_TYPE : integer;
  attribute LC_PROBE911_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE911_WIDTH : integer;
  attribute LC_PROBE911_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE912_IS_DATA : string;
  attribute LC_PROBE912_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE912_IS_TRIG : string;
  attribute LC_PROBE912_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE912_MU_CNT : integer;
  attribute LC_PROBE912_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE912_PID : string;
  attribute LC_PROBE912_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010000";
  attribute LC_PROBE912_TYPE : integer;
  attribute LC_PROBE912_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE912_WIDTH : integer;
  attribute LC_PROBE912_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE913_IS_DATA : string;
  attribute LC_PROBE913_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE913_IS_TRIG : string;
  attribute LC_PROBE913_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE913_MU_CNT : integer;
  attribute LC_PROBE913_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE913_PID : string;
  attribute LC_PROBE913_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010001";
  attribute LC_PROBE913_TYPE : integer;
  attribute LC_PROBE913_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE913_WIDTH : integer;
  attribute LC_PROBE913_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE914_IS_DATA : string;
  attribute LC_PROBE914_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE914_IS_TRIG : string;
  attribute LC_PROBE914_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE914_MU_CNT : integer;
  attribute LC_PROBE914_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE914_PID : string;
  attribute LC_PROBE914_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010010";
  attribute LC_PROBE914_TYPE : integer;
  attribute LC_PROBE914_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE914_WIDTH : integer;
  attribute LC_PROBE914_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE915_IS_DATA : string;
  attribute LC_PROBE915_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE915_IS_TRIG : string;
  attribute LC_PROBE915_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE915_MU_CNT : integer;
  attribute LC_PROBE915_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE915_PID : string;
  attribute LC_PROBE915_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010011";
  attribute LC_PROBE915_TYPE : integer;
  attribute LC_PROBE915_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE915_WIDTH : integer;
  attribute LC_PROBE915_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE916_IS_DATA : string;
  attribute LC_PROBE916_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE916_IS_TRIG : string;
  attribute LC_PROBE916_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE916_MU_CNT : integer;
  attribute LC_PROBE916_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE916_PID : string;
  attribute LC_PROBE916_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010100";
  attribute LC_PROBE916_TYPE : integer;
  attribute LC_PROBE916_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE916_WIDTH : integer;
  attribute LC_PROBE916_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE917_IS_DATA : string;
  attribute LC_PROBE917_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE917_IS_TRIG : string;
  attribute LC_PROBE917_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE917_MU_CNT : integer;
  attribute LC_PROBE917_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE917_PID : string;
  attribute LC_PROBE917_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010101";
  attribute LC_PROBE917_TYPE : integer;
  attribute LC_PROBE917_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE917_WIDTH : integer;
  attribute LC_PROBE917_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE918_IS_DATA : string;
  attribute LC_PROBE918_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE918_IS_TRIG : string;
  attribute LC_PROBE918_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE918_MU_CNT : integer;
  attribute LC_PROBE918_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE918_PID : string;
  attribute LC_PROBE918_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010110";
  attribute LC_PROBE918_TYPE : integer;
  attribute LC_PROBE918_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE918_WIDTH : integer;
  attribute LC_PROBE918_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE919_IS_DATA : string;
  attribute LC_PROBE919_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE919_IS_TRIG : string;
  attribute LC_PROBE919_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE919_MU_CNT : integer;
  attribute LC_PROBE919_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE919_PID : string;
  attribute LC_PROBE919_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110010111";
  attribute LC_PROBE919_TYPE : integer;
  attribute LC_PROBE919_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE919_WIDTH : integer;
  attribute LC_PROBE919_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE91_IS_DATA : string;
  attribute LC_PROBE91_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE91_IS_TRIG : string;
  attribute LC_PROBE91_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE91_MU_CNT : integer;
  attribute LC_PROBE91_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE91_PID : string;
  attribute LC_PROBE91_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011011";
  attribute LC_PROBE91_TYPE : integer;
  attribute LC_PROBE91_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE91_WIDTH : integer;
  attribute LC_PROBE91_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE920_IS_DATA : string;
  attribute LC_PROBE920_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE920_IS_TRIG : string;
  attribute LC_PROBE920_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE920_MU_CNT : integer;
  attribute LC_PROBE920_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE920_PID : string;
  attribute LC_PROBE920_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011000";
  attribute LC_PROBE920_TYPE : integer;
  attribute LC_PROBE920_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE920_WIDTH : integer;
  attribute LC_PROBE920_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE921_IS_DATA : string;
  attribute LC_PROBE921_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE921_IS_TRIG : string;
  attribute LC_PROBE921_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE921_MU_CNT : integer;
  attribute LC_PROBE921_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE921_PID : string;
  attribute LC_PROBE921_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011001";
  attribute LC_PROBE921_TYPE : integer;
  attribute LC_PROBE921_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE921_WIDTH : integer;
  attribute LC_PROBE921_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE922_IS_DATA : string;
  attribute LC_PROBE922_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE922_IS_TRIG : string;
  attribute LC_PROBE922_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE922_MU_CNT : integer;
  attribute LC_PROBE922_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE922_PID : string;
  attribute LC_PROBE922_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011010";
  attribute LC_PROBE922_TYPE : integer;
  attribute LC_PROBE922_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE922_WIDTH : integer;
  attribute LC_PROBE922_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE923_IS_DATA : string;
  attribute LC_PROBE923_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE923_IS_TRIG : string;
  attribute LC_PROBE923_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE923_MU_CNT : integer;
  attribute LC_PROBE923_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE923_PID : string;
  attribute LC_PROBE923_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011011";
  attribute LC_PROBE923_TYPE : integer;
  attribute LC_PROBE923_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE923_WIDTH : integer;
  attribute LC_PROBE923_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE924_IS_DATA : string;
  attribute LC_PROBE924_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE924_IS_TRIG : string;
  attribute LC_PROBE924_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE924_MU_CNT : integer;
  attribute LC_PROBE924_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE924_PID : string;
  attribute LC_PROBE924_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011100";
  attribute LC_PROBE924_TYPE : integer;
  attribute LC_PROBE924_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE924_WIDTH : integer;
  attribute LC_PROBE924_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE925_IS_DATA : string;
  attribute LC_PROBE925_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE925_IS_TRIG : string;
  attribute LC_PROBE925_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE925_MU_CNT : integer;
  attribute LC_PROBE925_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE925_PID : string;
  attribute LC_PROBE925_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011101";
  attribute LC_PROBE925_TYPE : integer;
  attribute LC_PROBE925_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE925_WIDTH : integer;
  attribute LC_PROBE925_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE926_IS_DATA : string;
  attribute LC_PROBE926_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE926_IS_TRIG : string;
  attribute LC_PROBE926_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE926_MU_CNT : integer;
  attribute LC_PROBE926_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE926_PID : string;
  attribute LC_PROBE926_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011110";
  attribute LC_PROBE926_TYPE : integer;
  attribute LC_PROBE926_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE926_WIDTH : integer;
  attribute LC_PROBE926_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE927_IS_DATA : string;
  attribute LC_PROBE927_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE927_IS_TRIG : string;
  attribute LC_PROBE927_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE927_MU_CNT : integer;
  attribute LC_PROBE927_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE927_PID : string;
  attribute LC_PROBE927_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110011111";
  attribute LC_PROBE927_TYPE : integer;
  attribute LC_PROBE927_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE927_WIDTH : integer;
  attribute LC_PROBE927_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE928_IS_DATA : string;
  attribute LC_PROBE928_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE928_IS_TRIG : string;
  attribute LC_PROBE928_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE928_MU_CNT : integer;
  attribute LC_PROBE928_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE928_PID : string;
  attribute LC_PROBE928_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100000";
  attribute LC_PROBE928_TYPE : integer;
  attribute LC_PROBE928_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE928_WIDTH : integer;
  attribute LC_PROBE928_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE929_IS_DATA : string;
  attribute LC_PROBE929_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE929_IS_TRIG : string;
  attribute LC_PROBE929_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE929_MU_CNT : integer;
  attribute LC_PROBE929_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE929_PID : string;
  attribute LC_PROBE929_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100001";
  attribute LC_PROBE929_TYPE : integer;
  attribute LC_PROBE929_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE929_WIDTH : integer;
  attribute LC_PROBE929_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE92_IS_DATA : string;
  attribute LC_PROBE92_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE92_IS_TRIG : string;
  attribute LC_PROBE92_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE92_MU_CNT : integer;
  attribute LC_PROBE92_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE92_PID : string;
  attribute LC_PROBE92_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011100";
  attribute LC_PROBE92_TYPE : integer;
  attribute LC_PROBE92_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE92_WIDTH : integer;
  attribute LC_PROBE92_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE930_IS_DATA : string;
  attribute LC_PROBE930_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE930_IS_TRIG : string;
  attribute LC_PROBE930_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE930_MU_CNT : integer;
  attribute LC_PROBE930_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE930_PID : string;
  attribute LC_PROBE930_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100010";
  attribute LC_PROBE930_TYPE : integer;
  attribute LC_PROBE930_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE930_WIDTH : integer;
  attribute LC_PROBE930_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE931_IS_DATA : string;
  attribute LC_PROBE931_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE931_IS_TRIG : string;
  attribute LC_PROBE931_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE931_MU_CNT : integer;
  attribute LC_PROBE931_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE931_PID : string;
  attribute LC_PROBE931_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100011";
  attribute LC_PROBE931_TYPE : integer;
  attribute LC_PROBE931_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE931_WIDTH : integer;
  attribute LC_PROBE931_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE932_IS_DATA : string;
  attribute LC_PROBE932_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE932_IS_TRIG : string;
  attribute LC_PROBE932_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE932_MU_CNT : integer;
  attribute LC_PROBE932_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE932_PID : string;
  attribute LC_PROBE932_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100100";
  attribute LC_PROBE932_TYPE : integer;
  attribute LC_PROBE932_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE932_WIDTH : integer;
  attribute LC_PROBE932_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE933_IS_DATA : string;
  attribute LC_PROBE933_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE933_IS_TRIG : string;
  attribute LC_PROBE933_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE933_MU_CNT : integer;
  attribute LC_PROBE933_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE933_PID : string;
  attribute LC_PROBE933_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100101";
  attribute LC_PROBE933_TYPE : integer;
  attribute LC_PROBE933_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE933_WIDTH : integer;
  attribute LC_PROBE933_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE934_IS_DATA : string;
  attribute LC_PROBE934_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE934_IS_TRIG : string;
  attribute LC_PROBE934_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE934_MU_CNT : integer;
  attribute LC_PROBE934_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE934_PID : string;
  attribute LC_PROBE934_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100110";
  attribute LC_PROBE934_TYPE : integer;
  attribute LC_PROBE934_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE934_WIDTH : integer;
  attribute LC_PROBE934_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE935_IS_DATA : string;
  attribute LC_PROBE935_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE935_IS_TRIG : string;
  attribute LC_PROBE935_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE935_MU_CNT : integer;
  attribute LC_PROBE935_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE935_PID : string;
  attribute LC_PROBE935_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110100111";
  attribute LC_PROBE935_TYPE : integer;
  attribute LC_PROBE935_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE935_WIDTH : integer;
  attribute LC_PROBE935_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE936_IS_DATA : string;
  attribute LC_PROBE936_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE936_IS_TRIG : string;
  attribute LC_PROBE936_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE936_MU_CNT : integer;
  attribute LC_PROBE936_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE936_PID : string;
  attribute LC_PROBE936_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101000";
  attribute LC_PROBE936_TYPE : integer;
  attribute LC_PROBE936_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE936_WIDTH : integer;
  attribute LC_PROBE936_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE937_IS_DATA : string;
  attribute LC_PROBE937_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE937_IS_TRIG : string;
  attribute LC_PROBE937_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE937_MU_CNT : integer;
  attribute LC_PROBE937_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE937_PID : string;
  attribute LC_PROBE937_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101001";
  attribute LC_PROBE937_TYPE : integer;
  attribute LC_PROBE937_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE937_WIDTH : integer;
  attribute LC_PROBE937_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE938_IS_DATA : string;
  attribute LC_PROBE938_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE938_IS_TRIG : string;
  attribute LC_PROBE938_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE938_MU_CNT : integer;
  attribute LC_PROBE938_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE938_PID : string;
  attribute LC_PROBE938_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101010";
  attribute LC_PROBE938_TYPE : integer;
  attribute LC_PROBE938_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE938_WIDTH : integer;
  attribute LC_PROBE938_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE939_IS_DATA : string;
  attribute LC_PROBE939_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE939_IS_TRIG : string;
  attribute LC_PROBE939_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE939_MU_CNT : integer;
  attribute LC_PROBE939_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE939_PID : string;
  attribute LC_PROBE939_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101011";
  attribute LC_PROBE939_TYPE : integer;
  attribute LC_PROBE939_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE939_WIDTH : integer;
  attribute LC_PROBE939_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE93_IS_DATA : string;
  attribute LC_PROBE93_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE93_IS_TRIG : string;
  attribute LC_PROBE93_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE93_MU_CNT : integer;
  attribute LC_PROBE93_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE93_PID : string;
  attribute LC_PROBE93_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011101";
  attribute LC_PROBE93_TYPE : integer;
  attribute LC_PROBE93_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE93_WIDTH : integer;
  attribute LC_PROBE93_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE940_IS_DATA : string;
  attribute LC_PROBE940_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE940_IS_TRIG : string;
  attribute LC_PROBE940_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE940_MU_CNT : integer;
  attribute LC_PROBE940_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE940_PID : string;
  attribute LC_PROBE940_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101100";
  attribute LC_PROBE940_TYPE : integer;
  attribute LC_PROBE940_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE940_WIDTH : integer;
  attribute LC_PROBE940_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE941_IS_DATA : string;
  attribute LC_PROBE941_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE941_IS_TRIG : string;
  attribute LC_PROBE941_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE941_MU_CNT : integer;
  attribute LC_PROBE941_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE941_PID : string;
  attribute LC_PROBE941_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101101";
  attribute LC_PROBE941_TYPE : integer;
  attribute LC_PROBE941_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE941_WIDTH : integer;
  attribute LC_PROBE941_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE942_IS_DATA : string;
  attribute LC_PROBE942_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE942_IS_TRIG : string;
  attribute LC_PROBE942_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE942_MU_CNT : integer;
  attribute LC_PROBE942_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE942_PID : string;
  attribute LC_PROBE942_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101110";
  attribute LC_PROBE942_TYPE : integer;
  attribute LC_PROBE942_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE942_WIDTH : integer;
  attribute LC_PROBE942_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE943_IS_DATA : string;
  attribute LC_PROBE943_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE943_IS_TRIG : string;
  attribute LC_PROBE943_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE943_MU_CNT : integer;
  attribute LC_PROBE943_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE943_PID : string;
  attribute LC_PROBE943_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110101111";
  attribute LC_PROBE943_TYPE : integer;
  attribute LC_PROBE943_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE943_WIDTH : integer;
  attribute LC_PROBE943_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE944_IS_DATA : string;
  attribute LC_PROBE944_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE944_IS_TRIG : string;
  attribute LC_PROBE944_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE944_MU_CNT : integer;
  attribute LC_PROBE944_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE944_PID : string;
  attribute LC_PROBE944_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110000";
  attribute LC_PROBE944_TYPE : integer;
  attribute LC_PROBE944_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE944_WIDTH : integer;
  attribute LC_PROBE944_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE945_IS_DATA : string;
  attribute LC_PROBE945_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE945_IS_TRIG : string;
  attribute LC_PROBE945_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE945_MU_CNT : integer;
  attribute LC_PROBE945_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE945_PID : string;
  attribute LC_PROBE945_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110001";
  attribute LC_PROBE945_TYPE : integer;
  attribute LC_PROBE945_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE945_WIDTH : integer;
  attribute LC_PROBE945_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE946_IS_DATA : string;
  attribute LC_PROBE946_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE946_IS_TRIG : string;
  attribute LC_PROBE946_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE946_MU_CNT : integer;
  attribute LC_PROBE946_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE946_PID : string;
  attribute LC_PROBE946_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110010";
  attribute LC_PROBE946_TYPE : integer;
  attribute LC_PROBE946_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE946_WIDTH : integer;
  attribute LC_PROBE946_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE947_IS_DATA : string;
  attribute LC_PROBE947_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE947_IS_TRIG : string;
  attribute LC_PROBE947_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE947_MU_CNT : integer;
  attribute LC_PROBE947_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE947_PID : string;
  attribute LC_PROBE947_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110011";
  attribute LC_PROBE947_TYPE : integer;
  attribute LC_PROBE947_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE947_WIDTH : integer;
  attribute LC_PROBE947_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE948_IS_DATA : string;
  attribute LC_PROBE948_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE948_IS_TRIG : string;
  attribute LC_PROBE948_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE948_MU_CNT : integer;
  attribute LC_PROBE948_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE948_PID : string;
  attribute LC_PROBE948_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110100";
  attribute LC_PROBE948_TYPE : integer;
  attribute LC_PROBE948_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE948_WIDTH : integer;
  attribute LC_PROBE948_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE949_IS_DATA : string;
  attribute LC_PROBE949_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE949_IS_TRIG : string;
  attribute LC_PROBE949_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE949_MU_CNT : integer;
  attribute LC_PROBE949_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE949_PID : string;
  attribute LC_PROBE949_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110101";
  attribute LC_PROBE949_TYPE : integer;
  attribute LC_PROBE949_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE949_WIDTH : integer;
  attribute LC_PROBE949_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE94_IS_DATA : string;
  attribute LC_PROBE94_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE94_IS_TRIG : string;
  attribute LC_PROBE94_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE94_MU_CNT : integer;
  attribute LC_PROBE94_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE94_PID : string;
  attribute LC_PROBE94_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011110";
  attribute LC_PROBE94_TYPE : integer;
  attribute LC_PROBE94_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE94_WIDTH : integer;
  attribute LC_PROBE94_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE950_IS_DATA : string;
  attribute LC_PROBE950_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE950_IS_TRIG : string;
  attribute LC_PROBE950_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE950_MU_CNT : integer;
  attribute LC_PROBE950_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE950_PID : string;
  attribute LC_PROBE950_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110110";
  attribute LC_PROBE950_TYPE : integer;
  attribute LC_PROBE950_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE950_WIDTH : integer;
  attribute LC_PROBE950_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE951_IS_DATA : string;
  attribute LC_PROBE951_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE951_IS_TRIG : string;
  attribute LC_PROBE951_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE951_MU_CNT : integer;
  attribute LC_PROBE951_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE951_PID : string;
  attribute LC_PROBE951_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110110111";
  attribute LC_PROBE951_TYPE : integer;
  attribute LC_PROBE951_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE951_WIDTH : integer;
  attribute LC_PROBE951_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE952_IS_DATA : string;
  attribute LC_PROBE952_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE952_IS_TRIG : string;
  attribute LC_PROBE952_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE952_MU_CNT : integer;
  attribute LC_PROBE952_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE952_PID : string;
  attribute LC_PROBE952_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111000";
  attribute LC_PROBE952_TYPE : integer;
  attribute LC_PROBE952_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE952_WIDTH : integer;
  attribute LC_PROBE952_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE953_IS_DATA : string;
  attribute LC_PROBE953_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE953_IS_TRIG : string;
  attribute LC_PROBE953_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE953_MU_CNT : integer;
  attribute LC_PROBE953_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE953_PID : string;
  attribute LC_PROBE953_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111001";
  attribute LC_PROBE953_TYPE : integer;
  attribute LC_PROBE953_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE953_WIDTH : integer;
  attribute LC_PROBE953_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE954_IS_DATA : string;
  attribute LC_PROBE954_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE954_IS_TRIG : string;
  attribute LC_PROBE954_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE954_MU_CNT : integer;
  attribute LC_PROBE954_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE954_PID : string;
  attribute LC_PROBE954_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111010";
  attribute LC_PROBE954_TYPE : integer;
  attribute LC_PROBE954_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE954_WIDTH : integer;
  attribute LC_PROBE954_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE955_IS_DATA : string;
  attribute LC_PROBE955_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE955_IS_TRIG : string;
  attribute LC_PROBE955_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE955_MU_CNT : integer;
  attribute LC_PROBE955_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE955_PID : string;
  attribute LC_PROBE955_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111011";
  attribute LC_PROBE955_TYPE : integer;
  attribute LC_PROBE955_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE955_WIDTH : integer;
  attribute LC_PROBE955_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE956_IS_DATA : string;
  attribute LC_PROBE956_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE956_IS_TRIG : string;
  attribute LC_PROBE956_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE956_MU_CNT : integer;
  attribute LC_PROBE956_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE956_PID : string;
  attribute LC_PROBE956_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111100";
  attribute LC_PROBE956_TYPE : integer;
  attribute LC_PROBE956_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE956_WIDTH : integer;
  attribute LC_PROBE956_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE957_IS_DATA : string;
  attribute LC_PROBE957_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE957_IS_TRIG : string;
  attribute LC_PROBE957_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE957_MU_CNT : integer;
  attribute LC_PROBE957_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE957_PID : string;
  attribute LC_PROBE957_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111101";
  attribute LC_PROBE957_TYPE : integer;
  attribute LC_PROBE957_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE957_WIDTH : integer;
  attribute LC_PROBE957_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE958_IS_DATA : string;
  attribute LC_PROBE958_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE958_IS_TRIG : string;
  attribute LC_PROBE958_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE958_MU_CNT : integer;
  attribute LC_PROBE958_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE958_PID : string;
  attribute LC_PROBE958_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111110";
  attribute LC_PROBE958_TYPE : integer;
  attribute LC_PROBE958_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE958_WIDTH : integer;
  attribute LC_PROBE958_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE959_IS_DATA : string;
  attribute LC_PROBE959_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE959_IS_TRIG : string;
  attribute LC_PROBE959_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE959_MU_CNT : integer;
  attribute LC_PROBE959_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE959_PID : string;
  attribute LC_PROBE959_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001110111111";
  attribute LC_PROBE959_TYPE : integer;
  attribute LC_PROBE959_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE959_WIDTH : integer;
  attribute LC_PROBE959_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE95_IS_DATA : string;
  attribute LC_PROBE95_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE95_IS_TRIG : string;
  attribute LC_PROBE95_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE95_MU_CNT : integer;
  attribute LC_PROBE95_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE95_PID : string;
  attribute LC_PROBE95_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001011111";
  attribute LC_PROBE95_TYPE : integer;
  attribute LC_PROBE95_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE95_WIDTH : integer;
  attribute LC_PROBE95_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE960_IS_DATA : string;
  attribute LC_PROBE960_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE960_IS_TRIG : string;
  attribute LC_PROBE960_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE960_MU_CNT : integer;
  attribute LC_PROBE960_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE960_PID : string;
  attribute LC_PROBE960_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000000";
  attribute LC_PROBE960_TYPE : integer;
  attribute LC_PROBE960_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE960_WIDTH : integer;
  attribute LC_PROBE960_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE961_IS_DATA : string;
  attribute LC_PROBE961_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE961_IS_TRIG : string;
  attribute LC_PROBE961_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE961_MU_CNT : integer;
  attribute LC_PROBE961_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE961_PID : string;
  attribute LC_PROBE961_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000001";
  attribute LC_PROBE961_TYPE : integer;
  attribute LC_PROBE961_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE961_WIDTH : integer;
  attribute LC_PROBE961_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE962_IS_DATA : string;
  attribute LC_PROBE962_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE962_IS_TRIG : string;
  attribute LC_PROBE962_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE962_MU_CNT : integer;
  attribute LC_PROBE962_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE962_PID : string;
  attribute LC_PROBE962_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000010";
  attribute LC_PROBE962_TYPE : integer;
  attribute LC_PROBE962_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE962_WIDTH : integer;
  attribute LC_PROBE962_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE963_IS_DATA : string;
  attribute LC_PROBE963_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE963_IS_TRIG : string;
  attribute LC_PROBE963_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE963_MU_CNT : integer;
  attribute LC_PROBE963_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE963_PID : string;
  attribute LC_PROBE963_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000011";
  attribute LC_PROBE963_TYPE : integer;
  attribute LC_PROBE963_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE963_WIDTH : integer;
  attribute LC_PROBE963_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE964_IS_DATA : string;
  attribute LC_PROBE964_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE964_IS_TRIG : string;
  attribute LC_PROBE964_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE964_MU_CNT : integer;
  attribute LC_PROBE964_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE964_PID : string;
  attribute LC_PROBE964_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000100";
  attribute LC_PROBE964_TYPE : integer;
  attribute LC_PROBE964_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE964_WIDTH : integer;
  attribute LC_PROBE964_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE965_IS_DATA : string;
  attribute LC_PROBE965_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE965_IS_TRIG : string;
  attribute LC_PROBE965_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE965_MU_CNT : integer;
  attribute LC_PROBE965_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE965_PID : string;
  attribute LC_PROBE965_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000101";
  attribute LC_PROBE965_TYPE : integer;
  attribute LC_PROBE965_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE965_WIDTH : integer;
  attribute LC_PROBE965_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE966_IS_DATA : string;
  attribute LC_PROBE966_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE966_IS_TRIG : string;
  attribute LC_PROBE966_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE966_MU_CNT : integer;
  attribute LC_PROBE966_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE966_PID : string;
  attribute LC_PROBE966_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000110";
  attribute LC_PROBE966_TYPE : integer;
  attribute LC_PROBE966_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE966_WIDTH : integer;
  attribute LC_PROBE966_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE967_IS_DATA : string;
  attribute LC_PROBE967_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE967_IS_TRIG : string;
  attribute LC_PROBE967_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE967_MU_CNT : integer;
  attribute LC_PROBE967_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE967_PID : string;
  attribute LC_PROBE967_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111000111";
  attribute LC_PROBE967_TYPE : integer;
  attribute LC_PROBE967_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE967_WIDTH : integer;
  attribute LC_PROBE967_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE968_IS_DATA : string;
  attribute LC_PROBE968_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE968_IS_TRIG : string;
  attribute LC_PROBE968_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE968_MU_CNT : integer;
  attribute LC_PROBE968_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE968_PID : string;
  attribute LC_PROBE968_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001000";
  attribute LC_PROBE968_TYPE : integer;
  attribute LC_PROBE968_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE968_WIDTH : integer;
  attribute LC_PROBE968_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE969_IS_DATA : string;
  attribute LC_PROBE969_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE969_IS_TRIG : string;
  attribute LC_PROBE969_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE969_MU_CNT : integer;
  attribute LC_PROBE969_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE969_PID : string;
  attribute LC_PROBE969_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001001";
  attribute LC_PROBE969_TYPE : integer;
  attribute LC_PROBE969_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE969_WIDTH : integer;
  attribute LC_PROBE969_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE96_IS_DATA : string;
  attribute LC_PROBE96_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE96_IS_TRIG : string;
  attribute LC_PROBE96_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE96_MU_CNT : integer;
  attribute LC_PROBE96_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE96_PID : string;
  attribute LC_PROBE96_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100000";
  attribute LC_PROBE96_TYPE : integer;
  attribute LC_PROBE96_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE96_WIDTH : integer;
  attribute LC_PROBE96_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE970_IS_DATA : string;
  attribute LC_PROBE970_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE970_IS_TRIG : string;
  attribute LC_PROBE970_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE970_MU_CNT : integer;
  attribute LC_PROBE970_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE970_PID : string;
  attribute LC_PROBE970_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001010";
  attribute LC_PROBE970_TYPE : integer;
  attribute LC_PROBE970_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE970_WIDTH : integer;
  attribute LC_PROBE970_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE971_IS_DATA : string;
  attribute LC_PROBE971_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE971_IS_TRIG : string;
  attribute LC_PROBE971_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE971_MU_CNT : integer;
  attribute LC_PROBE971_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE971_PID : string;
  attribute LC_PROBE971_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001011";
  attribute LC_PROBE971_TYPE : integer;
  attribute LC_PROBE971_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE971_WIDTH : integer;
  attribute LC_PROBE971_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE972_IS_DATA : string;
  attribute LC_PROBE972_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE972_IS_TRIG : string;
  attribute LC_PROBE972_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE972_MU_CNT : integer;
  attribute LC_PROBE972_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE972_PID : string;
  attribute LC_PROBE972_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001100";
  attribute LC_PROBE972_TYPE : integer;
  attribute LC_PROBE972_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE972_WIDTH : integer;
  attribute LC_PROBE972_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE973_IS_DATA : string;
  attribute LC_PROBE973_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE973_IS_TRIG : string;
  attribute LC_PROBE973_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE973_MU_CNT : integer;
  attribute LC_PROBE973_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE973_PID : string;
  attribute LC_PROBE973_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001101";
  attribute LC_PROBE973_TYPE : integer;
  attribute LC_PROBE973_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE973_WIDTH : integer;
  attribute LC_PROBE973_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE974_IS_DATA : string;
  attribute LC_PROBE974_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE974_IS_TRIG : string;
  attribute LC_PROBE974_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE974_MU_CNT : integer;
  attribute LC_PROBE974_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE974_PID : string;
  attribute LC_PROBE974_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001110";
  attribute LC_PROBE974_TYPE : integer;
  attribute LC_PROBE974_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE974_WIDTH : integer;
  attribute LC_PROBE974_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE975_IS_DATA : string;
  attribute LC_PROBE975_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE975_IS_TRIG : string;
  attribute LC_PROBE975_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE975_MU_CNT : integer;
  attribute LC_PROBE975_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE975_PID : string;
  attribute LC_PROBE975_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111001111";
  attribute LC_PROBE975_TYPE : integer;
  attribute LC_PROBE975_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE975_WIDTH : integer;
  attribute LC_PROBE975_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE976_IS_DATA : string;
  attribute LC_PROBE976_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE976_IS_TRIG : string;
  attribute LC_PROBE976_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE976_MU_CNT : integer;
  attribute LC_PROBE976_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE976_PID : string;
  attribute LC_PROBE976_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010000";
  attribute LC_PROBE976_TYPE : integer;
  attribute LC_PROBE976_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE976_WIDTH : integer;
  attribute LC_PROBE976_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE977_IS_DATA : string;
  attribute LC_PROBE977_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE977_IS_TRIG : string;
  attribute LC_PROBE977_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE977_MU_CNT : integer;
  attribute LC_PROBE977_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE977_PID : string;
  attribute LC_PROBE977_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010001";
  attribute LC_PROBE977_TYPE : integer;
  attribute LC_PROBE977_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE977_WIDTH : integer;
  attribute LC_PROBE977_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE978_IS_DATA : string;
  attribute LC_PROBE978_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE978_IS_TRIG : string;
  attribute LC_PROBE978_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE978_MU_CNT : integer;
  attribute LC_PROBE978_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE978_PID : string;
  attribute LC_PROBE978_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010010";
  attribute LC_PROBE978_TYPE : integer;
  attribute LC_PROBE978_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE978_WIDTH : integer;
  attribute LC_PROBE978_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE979_IS_DATA : string;
  attribute LC_PROBE979_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE979_IS_TRIG : string;
  attribute LC_PROBE979_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE979_MU_CNT : integer;
  attribute LC_PROBE979_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE979_PID : string;
  attribute LC_PROBE979_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010011";
  attribute LC_PROBE979_TYPE : integer;
  attribute LC_PROBE979_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE979_WIDTH : integer;
  attribute LC_PROBE979_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE97_IS_DATA : string;
  attribute LC_PROBE97_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE97_IS_TRIG : string;
  attribute LC_PROBE97_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE97_MU_CNT : integer;
  attribute LC_PROBE97_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE97_PID : string;
  attribute LC_PROBE97_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100001";
  attribute LC_PROBE97_TYPE : integer;
  attribute LC_PROBE97_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE97_WIDTH : integer;
  attribute LC_PROBE97_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE980_IS_DATA : string;
  attribute LC_PROBE980_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE980_IS_TRIG : string;
  attribute LC_PROBE980_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE980_MU_CNT : integer;
  attribute LC_PROBE980_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE980_PID : string;
  attribute LC_PROBE980_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010100";
  attribute LC_PROBE980_TYPE : integer;
  attribute LC_PROBE980_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE980_WIDTH : integer;
  attribute LC_PROBE980_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE981_IS_DATA : string;
  attribute LC_PROBE981_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE981_IS_TRIG : string;
  attribute LC_PROBE981_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE981_MU_CNT : integer;
  attribute LC_PROBE981_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE981_PID : string;
  attribute LC_PROBE981_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010101";
  attribute LC_PROBE981_TYPE : integer;
  attribute LC_PROBE981_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE981_WIDTH : integer;
  attribute LC_PROBE981_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE982_IS_DATA : string;
  attribute LC_PROBE982_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE982_IS_TRIG : string;
  attribute LC_PROBE982_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE982_MU_CNT : integer;
  attribute LC_PROBE982_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE982_PID : string;
  attribute LC_PROBE982_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010110";
  attribute LC_PROBE982_TYPE : integer;
  attribute LC_PROBE982_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE982_WIDTH : integer;
  attribute LC_PROBE982_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE983_IS_DATA : string;
  attribute LC_PROBE983_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE983_IS_TRIG : string;
  attribute LC_PROBE983_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE983_MU_CNT : integer;
  attribute LC_PROBE983_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE983_PID : string;
  attribute LC_PROBE983_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111010111";
  attribute LC_PROBE983_TYPE : integer;
  attribute LC_PROBE983_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE983_WIDTH : integer;
  attribute LC_PROBE983_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE984_IS_DATA : string;
  attribute LC_PROBE984_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE984_IS_TRIG : string;
  attribute LC_PROBE984_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE984_MU_CNT : integer;
  attribute LC_PROBE984_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE984_PID : string;
  attribute LC_PROBE984_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011000";
  attribute LC_PROBE984_TYPE : integer;
  attribute LC_PROBE984_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE984_WIDTH : integer;
  attribute LC_PROBE984_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE985_IS_DATA : string;
  attribute LC_PROBE985_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE985_IS_TRIG : string;
  attribute LC_PROBE985_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE985_MU_CNT : integer;
  attribute LC_PROBE985_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE985_PID : string;
  attribute LC_PROBE985_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011001";
  attribute LC_PROBE985_TYPE : integer;
  attribute LC_PROBE985_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE985_WIDTH : integer;
  attribute LC_PROBE985_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE986_IS_DATA : string;
  attribute LC_PROBE986_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE986_IS_TRIG : string;
  attribute LC_PROBE986_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE986_MU_CNT : integer;
  attribute LC_PROBE986_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE986_PID : string;
  attribute LC_PROBE986_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011010";
  attribute LC_PROBE986_TYPE : integer;
  attribute LC_PROBE986_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE986_WIDTH : integer;
  attribute LC_PROBE986_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE987_IS_DATA : string;
  attribute LC_PROBE987_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE987_IS_TRIG : string;
  attribute LC_PROBE987_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE987_MU_CNT : integer;
  attribute LC_PROBE987_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE987_PID : string;
  attribute LC_PROBE987_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011011";
  attribute LC_PROBE987_TYPE : integer;
  attribute LC_PROBE987_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE987_WIDTH : integer;
  attribute LC_PROBE987_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE988_IS_DATA : string;
  attribute LC_PROBE988_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE988_IS_TRIG : string;
  attribute LC_PROBE988_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE988_MU_CNT : integer;
  attribute LC_PROBE988_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE988_PID : string;
  attribute LC_PROBE988_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011100";
  attribute LC_PROBE988_TYPE : integer;
  attribute LC_PROBE988_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE988_WIDTH : integer;
  attribute LC_PROBE988_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE989_IS_DATA : string;
  attribute LC_PROBE989_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE989_IS_TRIG : string;
  attribute LC_PROBE989_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE989_MU_CNT : integer;
  attribute LC_PROBE989_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE989_PID : string;
  attribute LC_PROBE989_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011101";
  attribute LC_PROBE989_TYPE : integer;
  attribute LC_PROBE989_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE989_WIDTH : integer;
  attribute LC_PROBE989_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE98_IS_DATA : string;
  attribute LC_PROBE98_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE98_IS_TRIG : string;
  attribute LC_PROBE98_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE98_MU_CNT : integer;
  attribute LC_PROBE98_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE98_PID : string;
  attribute LC_PROBE98_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100010";
  attribute LC_PROBE98_TYPE : integer;
  attribute LC_PROBE98_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE98_WIDTH : integer;
  attribute LC_PROBE98_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE990_IS_DATA : string;
  attribute LC_PROBE990_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE990_IS_TRIG : string;
  attribute LC_PROBE990_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE990_MU_CNT : integer;
  attribute LC_PROBE990_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE990_PID : string;
  attribute LC_PROBE990_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011110";
  attribute LC_PROBE990_TYPE : integer;
  attribute LC_PROBE990_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE990_WIDTH : integer;
  attribute LC_PROBE990_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE991_IS_DATA : string;
  attribute LC_PROBE991_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE991_IS_TRIG : string;
  attribute LC_PROBE991_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE991_MU_CNT : integer;
  attribute LC_PROBE991_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE991_PID : string;
  attribute LC_PROBE991_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111011111";
  attribute LC_PROBE991_TYPE : integer;
  attribute LC_PROBE991_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE991_WIDTH : integer;
  attribute LC_PROBE991_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE992_IS_DATA : string;
  attribute LC_PROBE992_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE992_IS_TRIG : string;
  attribute LC_PROBE992_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE992_MU_CNT : integer;
  attribute LC_PROBE992_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE992_PID : string;
  attribute LC_PROBE992_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100000";
  attribute LC_PROBE992_TYPE : integer;
  attribute LC_PROBE992_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE992_WIDTH : integer;
  attribute LC_PROBE992_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE993_IS_DATA : string;
  attribute LC_PROBE993_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE993_IS_TRIG : string;
  attribute LC_PROBE993_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE993_MU_CNT : integer;
  attribute LC_PROBE993_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE993_PID : string;
  attribute LC_PROBE993_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100001";
  attribute LC_PROBE993_TYPE : integer;
  attribute LC_PROBE993_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE993_WIDTH : integer;
  attribute LC_PROBE993_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE994_IS_DATA : string;
  attribute LC_PROBE994_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE994_IS_TRIG : string;
  attribute LC_PROBE994_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE994_MU_CNT : integer;
  attribute LC_PROBE994_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE994_PID : string;
  attribute LC_PROBE994_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100010";
  attribute LC_PROBE994_TYPE : integer;
  attribute LC_PROBE994_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE994_WIDTH : integer;
  attribute LC_PROBE994_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE995_IS_DATA : string;
  attribute LC_PROBE995_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE995_IS_TRIG : string;
  attribute LC_PROBE995_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE995_MU_CNT : integer;
  attribute LC_PROBE995_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE995_PID : string;
  attribute LC_PROBE995_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100011";
  attribute LC_PROBE995_TYPE : integer;
  attribute LC_PROBE995_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE995_WIDTH : integer;
  attribute LC_PROBE995_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE996_IS_DATA : string;
  attribute LC_PROBE996_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE996_IS_TRIG : string;
  attribute LC_PROBE996_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE996_MU_CNT : integer;
  attribute LC_PROBE996_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE996_PID : string;
  attribute LC_PROBE996_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100100";
  attribute LC_PROBE996_TYPE : integer;
  attribute LC_PROBE996_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE996_WIDTH : integer;
  attribute LC_PROBE996_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE997_IS_DATA : string;
  attribute LC_PROBE997_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE997_IS_TRIG : string;
  attribute LC_PROBE997_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE997_MU_CNT : integer;
  attribute LC_PROBE997_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE997_PID : string;
  attribute LC_PROBE997_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100101";
  attribute LC_PROBE997_TYPE : integer;
  attribute LC_PROBE997_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE997_WIDTH : integer;
  attribute LC_PROBE997_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE998_IS_DATA : string;
  attribute LC_PROBE998_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE998_IS_TRIG : string;
  attribute LC_PROBE998_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE998_MU_CNT : integer;
  attribute LC_PROBE998_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE998_PID : string;
  attribute LC_PROBE998_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100110";
  attribute LC_PROBE998_TYPE : integer;
  attribute LC_PROBE998_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE998_WIDTH : integer;
  attribute LC_PROBE998_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE999_IS_DATA : string;
  attribute LC_PROBE999_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE999_IS_TRIG : string;
  attribute LC_PROBE999_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE999_MU_CNT : integer;
  attribute LC_PROBE999_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE999_PID : string;
  attribute LC_PROBE999_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000001111100111";
  attribute LC_PROBE999_TYPE : integer;
  attribute LC_PROBE999_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE999_WIDTH : integer;
  attribute LC_PROBE999_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE99_IS_DATA : string;
  attribute LC_PROBE99_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE99_IS_TRIG : string;
  attribute LC_PROBE99_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE99_MU_CNT : integer;
  attribute LC_PROBE99_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE99_PID : string;
  attribute LC_PROBE99_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000001100011";
  attribute LC_PROBE99_TYPE : integer;
  attribute LC_PROBE99_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE99_WIDTH : integer;
  attribute LC_PROBE99_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE9_IS_DATA : string;
  attribute LC_PROBE9_IS_DATA of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE9_IS_TRIG : string;
  attribute LC_PROBE9_IS_TRIG of ila_full_aurora_ila_v6_2_10_ila : entity is "1'b0";
  attribute LC_PROBE9_MU_CNT : integer;
  attribute LC_PROBE9_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE9_PID : string;
  attribute LC_PROBE9_PID of ila_full_aurora_ila_v6_2_10_ila : entity is "16'b0000000000001001";
  attribute LC_PROBE9_TYPE : integer;
  attribute LC_PROBE9_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBE9_WIDTH : integer;
  attribute LC_PROBE9_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_PROBES_WIDTH : integer;
  attribute LC_PROBES_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 138;
  attribute LC_PROBE_IS_DATA_STRING : string;
  attribute LC_PROBE_IS_DATA_STRING of ila_full_aurora_ila_v6_2_10_ila : entity is "1024'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111";
  attribute LC_PROBE_IS_TRIG_STRING : string;
  attribute LC_PROBE_IS_TRIG_STRING of ila_full_aurora_ila_v6_2_10_ila : entity is "4096' ";
  attribute LC_PROBE_WIDTH_STRING : string;
  attribute LC_PROBE_WIDTH_STRING of ila_full_aurora_ila_v6_2_10_ila : entity is "16384' ";
  attribute LC_TIME_TAG_MU_CNT : integer;
  attribute LC_TIME_TAG_MU_CNT of ila_full_aurora_ila_v6_2_10_ila : entity is 2;
  attribute LC_TIME_TAG_TYPE : integer;
  attribute LC_TIME_TAG_TYPE of ila_full_aurora_ila_v6_2_10_ila : entity is 0;
  attribute LC_TIME_TAG_WIDTH : integer;
  attribute LC_TIME_TAG_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 1;
  attribute LC_TRIG_WIDTH : integer;
  attribute LC_TRIG_WIDTH of ila_full_aurora_ila_v6_2_10_ila : entity is 138;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of ila_full_aurora_ila_v6_2_10_ila : entity is "ila_v6_2_10_ila";
  attribute dont_touch : string;
  attribute dont_touch of ila_full_aurora_ila_v6_2_10_ila : entity is "true";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of ila_full_aurora_ila_v6_2_10_ila : entity is "yes";
end ila_full_aurora_ila_v6_2_10_ila;

architecture STRUCTURE of ila_full_aurora_ila_v6_2_10_ila is
  signal \<const0>\ : STD_LOGIC;
  signal ack_reg1 : STD_LOGIC;
  attribute DONT_TOUCH_boolean : boolean;
  attribute DONT_TOUCH_boolean of ack_reg1 : signal is std.standard.true;
  signal ack_reg2 : STD_LOGIC;
  attribute DONT_TOUCH_boolean of ack_reg2 : signal is std.standard.true;
  signal clk1x : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of clk1x : signal is "true";
  signal dummy : STD_LOGIC;
  attribute DONT_TOUCH_boolean of dummy : signal is std.standard.true;
  signal sync_reg1 : STD_LOGIC;
  attribute DONT_TOUCH_boolean of sync_reg1 : signal is std.standard.true;
  signal sync_reg2 : STD_LOGIC;
  attribute DONT_TOUCH_boolean of sync_reg2 : signal is std.standard.true;
  signal trig_in_reg : STD_LOGIC;
  attribute DONT_TOUCH_boolean of trig_in_reg : signal is std.standard.true;
  signal trig_out_ack_reg : STD_LOGIC;
  attribute DONT_TOUCH_boolean of trig_out_ack_reg : signal is std.standard.true;
  attribute DONT_TOUCH_boolean of \ack_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \ack_reg1_reg[0]\ : label is "yes";
  attribute DONT_TOUCH_boolean of \ack_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \ack_reg2_reg[0]\ : label is "yes";
  attribute DONT_TOUCH_boolean of \sync_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_reg1_reg[0]\ : label is "yes";
  attribute DONT_TOUCH_boolean of \sync_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \sync_reg2_reg[0]\ : label is "yes";
  attribute DONT_TOUCH_boolean of trig_in_reg_reg : label is std.standard.true;
  attribute KEEP of trig_in_reg_reg : label is "yes";
  attribute DONT_TOUCH_boolean of trig_out_ack_reg_reg : label is std.standard.true;
  attribute KEEP of trig_out_ack_reg_reg : label is "yes";
  attribute dont_touch of sl_iport0 : signal is "true";
  attribute dont_touch of sl_oport0 : signal is "true";
begin
  clk1x <= clk;
  clkdiv_out <= \<const0>\;
  trig_in_ack <= \<const0>\;
  trig_out <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\ack_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk1x,
      CE => '1',
      D => trig_out_ack,
      Q => ack_reg1,
      R => '0'
    );
\ack_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk1x,
      CE => '1',
      D => ack_reg1,
      Q => ack_reg2,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => dummy
    );
ila_core_inst: entity work.ila_full_aurora_ila_v6_2_10_ila_core
     port map (
      \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ => clk1x,
      dummy_temp1_reg => dummy,
      \out\(36 downto 0) => sl_iport0(36 downto 0),
      probe0(63 downto 0) => probe0(63 downto 0),
      probe1(0) => probe1(0),
      probe2(0) => probe2(0),
      probe3(7 downto 0) => probe3(7 downto 0),
      probe4(31 downto 0) => probe4(31 downto 0),
      probe5(31 downto 0) => probe5(31 downto 0),
      sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
    );
\sync_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk1x,
      CE => '1',
      D => trig_in,
      Q => sync_reg1,
      R => '0'
    );
\sync_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk1x,
      CE => '1',
      D => sync_reg1,
      Q => sync_reg2,
      R => '0'
    );
trig_in_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => clk1x,
      CE => '1',
      D => sync_reg2,
      Q => trig_in_reg,
      R => '0'
    );
trig_out_ack_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => clk1x,
      CE => '1',
      D => ack_reg2,
      Q => trig_out_ack_reg,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ila_full_aurora is
  port (
    clk : in STD_LOGIC;
    probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    probe5 : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of ila_full_aurora : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of ila_full_aurora : entity is "ila_full_aurora,ila_v6_2_10_ila,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of ila_full_aurora : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of ila_full_aurora : entity is "ila,Vivado 2019.2";
end ila_full_aurora;

architecture STRUCTURE of ila_full_aurora is
  signal NLW_U0_clkdiv_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_trig_in_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_trig_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
  attribute C_ADV_TRIGGER : integer;
  attribute C_ADV_TRIGGER of U0 : label is 0;
  attribute C_BUILD_REVISION : integer;
  attribute C_BUILD_REVISION of U0 : label is 0;
  attribute C_CAPTURE_TYPE : integer;
  attribute C_CAPTURE_TYPE of U0 : label is 0;
  attribute C_CLKFBOUT_MULT_F : string;
  attribute C_CLKFBOUT_MULT_F of U0 : label is "10.000000";
  attribute C_CLKOUT0_DIVIDE_F : string;
  attribute C_CLKOUT0_DIVIDE_F of U0 : label is "10.000000";
  attribute C_CLK_FREQ : string;
  attribute C_CLK_FREQ of U0 : label is "200.000000";
  attribute C_CLK_PERIOD : string;
  attribute C_CLK_PERIOD of U0 : label is "10.000000";
  attribute C_CORE_INFO1 : integer;
  attribute C_CORE_INFO1 of U0 : label is 0;
  attribute C_CORE_INFO2 : integer;
  attribute C_CORE_INFO2 of U0 : label is 0;
  attribute C_CORE_MAJOR_VER : integer;
  attribute C_CORE_MAJOR_VER of U0 : label is 6;
  attribute C_CORE_MINOR_VER : integer;
  attribute C_CORE_MINOR_VER of U0 : label is 2;
  attribute C_CORE_TYPE : integer;
  attribute C_CORE_TYPE of U0 : label is 1;
  attribute C_CSE_DRV_VER : integer;
  attribute C_CSE_DRV_VER of U0 : label is 2;
  attribute C_DATA_DEPTH : integer;
  attribute C_DATA_DEPTH of U0 : label is 1024;
  attribute C_DDR_CLK_GEN : integer;
  attribute C_DDR_CLK_GEN of U0 : label is 1;
  attribute C_DIVCLK_DIVIDE : integer;
  attribute C_DIVCLK_DIVIDE of U0 : label is 3;
  attribute C_ENABLE_ILA_AXI_MON : integer;
  attribute C_ENABLE_ILA_AXI_MON of U0 : label is 0;
  attribute C_EN_DDR_ILA : integer;
  attribute C_EN_DDR_ILA of U0 : label is 0;
  attribute C_EN_STRG_QUAL : integer;
  attribute C_EN_STRG_QUAL of U0 : label is 0;
  attribute C_EN_TIME_TAG : integer;
  attribute C_EN_TIME_TAG of U0 : label is 0;
  attribute C_ILA_CLK_FREQ : integer;
  attribute C_ILA_CLK_FREQ of U0 : label is 2000000;
  attribute C_INPUT_PIPE_STAGES : integer;
  attribute C_INPUT_PIPE_STAGES of U0 : label is 0;
  attribute C_MAJOR_VERSION : integer;
  attribute C_MAJOR_VERSION of U0 : label is 2019;
  attribute C_MINOR_VERSION : integer;
  attribute C_MINOR_VERSION of U0 : label is 2;
  attribute C_MU_TYPE : integer;
  attribute C_MU_TYPE of U0 : label is 0;
  attribute C_NEXT_SLAVE : integer;
  attribute C_NEXT_SLAVE of U0 : label is 0;
  attribute C_NUM_MONITOR_SLOTS : integer;
  attribute C_NUM_MONITOR_SLOTS of U0 : label is 1;
  attribute C_NUM_OF_PROBES : integer;
  attribute C_NUM_OF_PROBES of U0 : label is 6;
  attribute C_PIPE_IFACE : integer;
  attribute C_PIPE_IFACE of U0 : label is 1;
  attribute C_PROBE0_MU_CNT : integer;
  attribute C_PROBE0_MU_CNT of U0 : label is 1;
  attribute C_PROBE0_TYPE : integer;
  attribute C_PROBE0_TYPE of U0 : label is 0;
  attribute C_PROBE0_WIDTH : integer;
  attribute C_PROBE0_WIDTH of U0 : label is 64;
  attribute C_PROBE1000_MU_CNT : integer;
  attribute C_PROBE1000_MU_CNT of U0 : label is 1;
  attribute C_PROBE1000_TYPE : integer;
  attribute C_PROBE1000_TYPE of U0 : label is 1;
  attribute C_PROBE1000_WIDTH : integer;
  attribute C_PROBE1000_WIDTH of U0 : label is 1;
  attribute C_PROBE1001_MU_CNT : integer;
  attribute C_PROBE1001_MU_CNT of U0 : label is 1;
  attribute C_PROBE1001_TYPE : integer;
  attribute C_PROBE1001_TYPE of U0 : label is 1;
  attribute C_PROBE1001_WIDTH : integer;
  attribute C_PROBE1001_WIDTH of U0 : label is 1;
  attribute C_PROBE1002_MU_CNT : integer;
  attribute C_PROBE1002_MU_CNT of U0 : label is 1;
  attribute C_PROBE1002_TYPE : integer;
  attribute C_PROBE1002_TYPE of U0 : label is 1;
  attribute C_PROBE1002_WIDTH : integer;
  attribute C_PROBE1002_WIDTH of U0 : label is 1;
  attribute C_PROBE1003_MU_CNT : integer;
  attribute C_PROBE1003_MU_CNT of U0 : label is 1;
  attribute C_PROBE1003_TYPE : integer;
  attribute C_PROBE1003_TYPE of U0 : label is 1;
  attribute C_PROBE1003_WIDTH : integer;
  attribute C_PROBE1003_WIDTH of U0 : label is 1;
  attribute C_PROBE1004_MU_CNT : integer;
  attribute C_PROBE1004_MU_CNT of U0 : label is 1;
  attribute C_PROBE1004_TYPE : integer;
  attribute C_PROBE1004_TYPE of U0 : label is 1;
  attribute C_PROBE1004_WIDTH : integer;
  attribute C_PROBE1004_WIDTH of U0 : label is 1;
  attribute C_PROBE1005_MU_CNT : integer;
  attribute C_PROBE1005_MU_CNT of U0 : label is 1;
  attribute C_PROBE1005_TYPE : integer;
  attribute C_PROBE1005_TYPE of U0 : label is 1;
  attribute C_PROBE1005_WIDTH : integer;
  attribute C_PROBE1005_WIDTH of U0 : label is 1;
  attribute C_PROBE1006_MU_CNT : integer;
  attribute C_PROBE1006_MU_CNT of U0 : label is 1;
  attribute C_PROBE1006_TYPE : integer;
  attribute C_PROBE1006_TYPE of U0 : label is 1;
  attribute C_PROBE1006_WIDTH : integer;
  attribute C_PROBE1006_WIDTH of U0 : label is 1;
  attribute C_PROBE1007_MU_CNT : integer;
  attribute C_PROBE1007_MU_CNT of U0 : label is 1;
  attribute C_PROBE1007_TYPE : integer;
  attribute C_PROBE1007_TYPE of U0 : label is 1;
  attribute C_PROBE1007_WIDTH : integer;
  attribute C_PROBE1007_WIDTH of U0 : label is 1;
  attribute C_PROBE1008_MU_CNT : integer;
  attribute C_PROBE1008_MU_CNT of U0 : label is 1;
  attribute C_PROBE1008_TYPE : integer;
  attribute C_PROBE1008_TYPE of U0 : label is 1;
  attribute C_PROBE1008_WIDTH : integer;
  attribute C_PROBE1008_WIDTH of U0 : label is 1;
  attribute C_PROBE1009_MU_CNT : integer;
  attribute C_PROBE1009_MU_CNT of U0 : label is 1;
  attribute C_PROBE1009_TYPE : integer;
  attribute C_PROBE1009_TYPE of U0 : label is 1;
  attribute C_PROBE1009_WIDTH : integer;
  attribute C_PROBE1009_WIDTH of U0 : label is 1;
  attribute C_PROBE100_MU_CNT : integer;
  attribute C_PROBE100_MU_CNT of U0 : label is 1;
  attribute C_PROBE100_TYPE : integer;
  attribute C_PROBE100_TYPE of U0 : label is 1;
  attribute C_PROBE100_WIDTH : integer;
  attribute C_PROBE100_WIDTH of U0 : label is 1;
  attribute C_PROBE1010_MU_CNT : integer;
  attribute C_PROBE1010_MU_CNT of U0 : label is 1;
  attribute C_PROBE1010_TYPE : integer;
  attribute C_PROBE1010_TYPE of U0 : label is 1;
  attribute C_PROBE1010_WIDTH : integer;
  attribute C_PROBE1010_WIDTH of U0 : label is 1;
  attribute C_PROBE1011_MU_CNT : integer;
  attribute C_PROBE1011_MU_CNT of U0 : label is 1;
  attribute C_PROBE1011_TYPE : integer;
  attribute C_PROBE1011_TYPE of U0 : label is 1;
  attribute C_PROBE1011_WIDTH : integer;
  attribute C_PROBE1011_WIDTH of U0 : label is 1;
  attribute C_PROBE1012_MU_CNT : integer;
  attribute C_PROBE1012_MU_CNT of U0 : label is 1;
  attribute C_PROBE1012_TYPE : integer;
  attribute C_PROBE1012_TYPE of U0 : label is 1;
  attribute C_PROBE1012_WIDTH : integer;
  attribute C_PROBE1012_WIDTH of U0 : label is 1;
  attribute C_PROBE1013_MU_CNT : integer;
  attribute C_PROBE1013_MU_CNT of U0 : label is 1;
  attribute C_PROBE1013_TYPE : integer;
  attribute C_PROBE1013_TYPE of U0 : label is 1;
  attribute C_PROBE1013_WIDTH : integer;
  attribute C_PROBE1013_WIDTH of U0 : label is 1;
  attribute C_PROBE1014_MU_CNT : integer;
  attribute C_PROBE1014_MU_CNT of U0 : label is 1;
  attribute C_PROBE1014_TYPE : integer;
  attribute C_PROBE1014_TYPE of U0 : label is 1;
  attribute C_PROBE1014_WIDTH : integer;
  attribute C_PROBE1014_WIDTH of U0 : label is 1;
  attribute C_PROBE1015_MU_CNT : integer;
  attribute C_PROBE1015_MU_CNT of U0 : label is 1;
  attribute C_PROBE1015_TYPE : integer;
  attribute C_PROBE1015_TYPE of U0 : label is 1;
  attribute C_PROBE1015_WIDTH : integer;
  attribute C_PROBE1015_WIDTH of U0 : label is 1;
  attribute C_PROBE1016_MU_CNT : integer;
  attribute C_PROBE1016_MU_CNT of U0 : label is 1;
  attribute C_PROBE1016_TYPE : integer;
  attribute C_PROBE1016_TYPE of U0 : label is 1;
  attribute C_PROBE1016_WIDTH : integer;
  attribute C_PROBE1016_WIDTH of U0 : label is 1;
  attribute C_PROBE1017_MU_CNT : integer;
  attribute C_PROBE1017_MU_CNT of U0 : label is 1;
  attribute C_PROBE1017_TYPE : integer;
  attribute C_PROBE1017_TYPE of U0 : label is 1;
  attribute C_PROBE1017_WIDTH : integer;
  attribute C_PROBE1017_WIDTH of U0 : label is 1;
  attribute C_PROBE1018_MU_CNT : integer;
  attribute C_PROBE1018_MU_CNT of U0 : label is 1;
  attribute C_PROBE1018_TYPE : integer;
  attribute C_PROBE1018_TYPE of U0 : label is 1;
  attribute C_PROBE1018_WIDTH : integer;
  attribute C_PROBE1018_WIDTH of U0 : label is 1;
  attribute C_PROBE1019_MU_CNT : integer;
  attribute C_PROBE1019_MU_CNT of U0 : label is 1;
  attribute C_PROBE1019_TYPE : integer;
  attribute C_PROBE1019_TYPE of U0 : label is 1;
  attribute C_PROBE1019_WIDTH : integer;
  attribute C_PROBE1019_WIDTH of U0 : label is 1;
  attribute C_PROBE101_MU_CNT : integer;
  attribute C_PROBE101_MU_CNT of U0 : label is 1;
  attribute C_PROBE101_TYPE : integer;
  attribute C_PROBE101_TYPE of U0 : label is 1;
  attribute C_PROBE101_WIDTH : integer;
  attribute C_PROBE101_WIDTH of U0 : label is 1;
  attribute C_PROBE1020_MU_CNT : integer;
  attribute C_PROBE1020_MU_CNT of U0 : label is 1;
  attribute C_PROBE1020_TYPE : integer;
  attribute C_PROBE1020_TYPE of U0 : label is 1;
  attribute C_PROBE1020_WIDTH : integer;
  attribute C_PROBE1020_WIDTH of U0 : label is 1;
  attribute C_PROBE1021_MU_CNT : integer;
  attribute C_PROBE1021_MU_CNT of U0 : label is 1;
  attribute C_PROBE1021_TYPE : integer;
  attribute C_PROBE1021_TYPE of U0 : label is 1;
  attribute C_PROBE1021_WIDTH : integer;
  attribute C_PROBE1021_WIDTH of U0 : label is 1;
  attribute C_PROBE1022_MU_CNT : integer;
  attribute C_PROBE1022_MU_CNT of U0 : label is 1;
  attribute C_PROBE1022_TYPE : integer;
  attribute C_PROBE1022_TYPE of U0 : label is 1;
  attribute C_PROBE1022_WIDTH : integer;
  attribute C_PROBE1022_WIDTH of U0 : label is 1;
  attribute C_PROBE1023_MU_CNT : integer;
  attribute C_PROBE1023_MU_CNT of U0 : label is 1;
  attribute C_PROBE1023_TYPE : integer;
  attribute C_PROBE1023_TYPE of U0 : label is 1;
  attribute C_PROBE1023_WIDTH : integer;
  attribute C_PROBE1023_WIDTH of U0 : label is 1;
  attribute C_PROBE102_MU_CNT : integer;
  attribute C_PROBE102_MU_CNT of U0 : label is 1;
  attribute C_PROBE102_TYPE : integer;
  attribute C_PROBE102_TYPE of U0 : label is 1;
  attribute C_PROBE102_WIDTH : integer;
  attribute C_PROBE102_WIDTH of U0 : label is 1;
  attribute C_PROBE103_MU_CNT : integer;
  attribute C_PROBE103_MU_CNT of U0 : label is 1;
  attribute C_PROBE103_TYPE : integer;
  attribute C_PROBE103_TYPE of U0 : label is 1;
  attribute C_PROBE103_WIDTH : integer;
  attribute C_PROBE103_WIDTH of U0 : label is 1;
  attribute C_PROBE104_MU_CNT : integer;
  attribute C_PROBE104_MU_CNT of U0 : label is 1;
  attribute C_PROBE104_TYPE : integer;
  attribute C_PROBE104_TYPE of U0 : label is 1;
  attribute C_PROBE104_WIDTH : integer;
  attribute C_PROBE104_WIDTH of U0 : label is 1;
  attribute C_PROBE105_MU_CNT : integer;
  attribute C_PROBE105_MU_CNT of U0 : label is 1;
  attribute C_PROBE105_TYPE : integer;
  attribute C_PROBE105_TYPE of U0 : label is 1;
  attribute C_PROBE105_WIDTH : integer;
  attribute C_PROBE105_WIDTH of U0 : label is 1;
  attribute C_PROBE106_MU_CNT : integer;
  attribute C_PROBE106_MU_CNT of U0 : label is 1;
  attribute C_PROBE106_TYPE : integer;
  attribute C_PROBE106_TYPE of U0 : label is 1;
  attribute C_PROBE106_WIDTH : integer;
  attribute C_PROBE106_WIDTH of U0 : label is 1;
  attribute C_PROBE107_MU_CNT : integer;
  attribute C_PROBE107_MU_CNT of U0 : label is 1;
  attribute C_PROBE107_TYPE : integer;
  attribute C_PROBE107_TYPE of U0 : label is 1;
  attribute C_PROBE107_WIDTH : integer;
  attribute C_PROBE107_WIDTH of U0 : label is 1;
  attribute C_PROBE108_MU_CNT : integer;
  attribute C_PROBE108_MU_CNT of U0 : label is 1;
  attribute C_PROBE108_TYPE : integer;
  attribute C_PROBE108_TYPE of U0 : label is 1;
  attribute C_PROBE108_WIDTH : integer;
  attribute C_PROBE108_WIDTH of U0 : label is 1;
  attribute C_PROBE109_MU_CNT : integer;
  attribute C_PROBE109_MU_CNT of U0 : label is 1;
  attribute C_PROBE109_TYPE : integer;
  attribute C_PROBE109_TYPE of U0 : label is 1;
  attribute C_PROBE109_WIDTH : integer;
  attribute C_PROBE109_WIDTH of U0 : label is 1;
  attribute C_PROBE10_MU_CNT : integer;
  attribute C_PROBE10_MU_CNT of U0 : label is 1;
  attribute C_PROBE10_TYPE : integer;
  attribute C_PROBE10_TYPE of U0 : label is 1;
  attribute C_PROBE10_WIDTH : integer;
  attribute C_PROBE10_WIDTH of U0 : label is 1;
  attribute C_PROBE110_MU_CNT : integer;
  attribute C_PROBE110_MU_CNT of U0 : label is 1;
  attribute C_PROBE110_TYPE : integer;
  attribute C_PROBE110_TYPE of U0 : label is 1;
  attribute C_PROBE110_WIDTH : integer;
  attribute C_PROBE110_WIDTH of U0 : label is 1;
  attribute C_PROBE111_MU_CNT : integer;
  attribute C_PROBE111_MU_CNT of U0 : label is 1;
  attribute C_PROBE111_TYPE : integer;
  attribute C_PROBE111_TYPE of U0 : label is 1;
  attribute C_PROBE111_WIDTH : integer;
  attribute C_PROBE111_WIDTH of U0 : label is 1;
  attribute C_PROBE112_MU_CNT : integer;
  attribute C_PROBE112_MU_CNT of U0 : label is 1;
  attribute C_PROBE112_TYPE : integer;
  attribute C_PROBE112_TYPE of U0 : label is 1;
  attribute C_PROBE112_WIDTH : integer;
  attribute C_PROBE112_WIDTH of U0 : label is 1;
  attribute C_PROBE113_MU_CNT : integer;
  attribute C_PROBE113_MU_CNT of U0 : label is 1;
  attribute C_PROBE113_TYPE : integer;
  attribute C_PROBE113_TYPE of U0 : label is 1;
  attribute C_PROBE113_WIDTH : integer;
  attribute C_PROBE113_WIDTH of U0 : label is 1;
  attribute C_PROBE114_MU_CNT : integer;
  attribute C_PROBE114_MU_CNT of U0 : label is 1;
  attribute C_PROBE114_TYPE : integer;
  attribute C_PROBE114_TYPE of U0 : label is 1;
  attribute C_PROBE114_WIDTH : integer;
  attribute C_PROBE114_WIDTH of U0 : label is 1;
  attribute C_PROBE115_MU_CNT : integer;
  attribute C_PROBE115_MU_CNT of U0 : label is 1;
  attribute C_PROBE115_TYPE : integer;
  attribute C_PROBE115_TYPE of U0 : label is 1;
  attribute C_PROBE115_WIDTH : integer;
  attribute C_PROBE115_WIDTH of U0 : label is 1;
  attribute C_PROBE116_MU_CNT : integer;
  attribute C_PROBE116_MU_CNT of U0 : label is 1;
  attribute C_PROBE116_TYPE : integer;
  attribute C_PROBE116_TYPE of U0 : label is 1;
  attribute C_PROBE116_WIDTH : integer;
  attribute C_PROBE116_WIDTH of U0 : label is 1;
  attribute C_PROBE117_MU_CNT : integer;
  attribute C_PROBE117_MU_CNT of U0 : label is 1;
  attribute C_PROBE117_TYPE : integer;
  attribute C_PROBE117_TYPE of U0 : label is 1;
  attribute C_PROBE117_WIDTH : integer;
  attribute C_PROBE117_WIDTH of U0 : label is 1;
  attribute C_PROBE118_MU_CNT : integer;
  attribute C_PROBE118_MU_CNT of U0 : label is 1;
  attribute C_PROBE118_TYPE : integer;
  attribute C_PROBE118_TYPE of U0 : label is 1;
  attribute C_PROBE118_WIDTH : integer;
  attribute C_PROBE118_WIDTH of U0 : label is 1;
  attribute C_PROBE119_MU_CNT : integer;
  attribute C_PROBE119_MU_CNT of U0 : label is 1;
  attribute C_PROBE119_TYPE : integer;
  attribute C_PROBE119_TYPE of U0 : label is 1;
  attribute C_PROBE119_WIDTH : integer;
  attribute C_PROBE119_WIDTH of U0 : label is 1;
  attribute C_PROBE11_MU_CNT : integer;
  attribute C_PROBE11_MU_CNT of U0 : label is 1;
  attribute C_PROBE11_TYPE : integer;
  attribute C_PROBE11_TYPE of U0 : label is 1;
  attribute C_PROBE11_WIDTH : integer;
  attribute C_PROBE11_WIDTH of U0 : label is 1;
  attribute C_PROBE120_MU_CNT : integer;
  attribute C_PROBE120_MU_CNT of U0 : label is 1;
  attribute C_PROBE120_TYPE : integer;
  attribute C_PROBE120_TYPE of U0 : label is 1;
  attribute C_PROBE120_WIDTH : integer;
  attribute C_PROBE120_WIDTH of U0 : label is 1;
  attribute C_PROBE121_MU_CNT : integer;
  attribute C_PROBE121_MU_CNT of U0 : label is 1;
  attribute C_PROBE121_TYPE : integer;
  attribute C_PROBE121_TYPE of U0 : label is 1;
  attribute C_PROBE121_WIDTH : integer;
  attribute C_PROBE121_WIDTH of U0 : label is 1;
  attribute C_PROBE122_MU_CNT : integer;
  attribute C_PROBE122_MU_CNT of U0 : label is 1;
  attribute C_PROBE122_TYPE : integer;
  attribute C_PROBE122_TYPE of U0 : label is 1;
  attribute C_PROBE122_WIDTH : integer;
  attribute C_PROBE122_WIDTH of U0 : label is 1;
  attribute C_PROBE123_MU_CNT : integer;
  attribute C_PROBE123_MU_CNT of U0 : label is 1;
  attribute C_PROBE123_TYPE : integer;
  attribute C_PROBE123_TYPE of U0 : label is 1;
  attribute C_PROBE123_WIDTH : integer;
  attribute C_PROBE123_WIDTH of U0 : label is 1;
  attribute C_PROBE124_MU_CNT : integer;
  attribute C_PROBE124_MU_CNT of U0 : label is 1;
  attribute C_PROBE124_TYPE : integer;
  attribute C_PROBE124_TYPE of U0 : label is 1;
  attribute C_PROBE124_WIDTH : integer;
  attribute C_PROBE124_WIDTH of U0 : label is 1;
  attribute C_PROBE125_MU_CNT : integer;
  attribute C_PROBE125_MU_CNT of U0 : label is 1;
  attribute C_PROBE125_TYPE : integer;
  attribute C_PROBE125_TYPE of U0 : label is 1;
  attribute C_PROBE125_WIDTH : integer;
  attribute C_PROBE125_WIDTH of U0 : label is 1;
  attribute C_PROBE126_MU_CNT : integer;
  attribute C_PROBE126_MU_CNT of U0 : label is 1;
  attribute C_PROBE126_TYPE : integer;
  attribute C_PROBE126_TYPE of U0 : label is 1;
  attribute C_PROBE126_WIDTH : integer;
  attribute C_PROBE126_WIDTH of U0 : label is 1;
  attribute C_PROBE127_MU_CNT : integer;
  attribute C_PROBE127_MU_CNT of U0 : label is 1;
  attribute C_PROBE127_TYPE : integer;
  attribute C_PROBE127_TYPE of U0 : label is 1;
  attribute C_PROBE127_WIDTH : integer;
  attribute C_PROBE127_WIDTH of U0 : label is 1;
  attribute C_PROBE128_MU_CNT : integer;
  attribute C_PROBE128_MU_CNT of U0 : label is 1;
  attribute C_PROBE128_TYPE : integer;
  attribute C_PROBE128_TYPE of U0 : label is 1;
  attribute C_PROBE128_WIDTH : integer;
  attribute C_PROBE128_WIDTH of U0 : label is 1;
  attribute C_PROBE129_MU_CNT : integer;
  attribute C_PROBE129_MU_CNT of U0 : label is 1;
  attribute C_PROBE129_TYPE : integer;
  attribute C_PROBE129_TYPE of U0 : label is 1;
  attribute C_PROBE129_WIDTH : integer;
  attribute C_PROBE129_WIDTH of U0 : label is 1;
  attribute C_PROBE12_MU_CNT : integer;
  attribute C_PROBE12_MU_CNT of U0 : label is 1;
  attribute C_PROBE12_TYPE : integer;
  attribute C_PROBE12_TYPE of U0 : label is 1;
  attribute C_PROBE12_WIDTH : integer;
  attribute C_PROBE12_WIDTH of U0 : label is 1;
  attribute C_PROBE130_MU_CNT : integer;
  attribute C_PROBE130_MU_CNT of U0 : label is 1;
  attribute C_PROBE130_TYPE : integer;
  attribute C_PROBE130_TYPE of U0 : label is 1;
  attribute C_PROBE130_WIDTH : integer;
  attribute C_PROBE130_WIDTH of U0 : label is 1;
  attribute C_PROBE131_MU_CNT : integer;
  attribute C_PROBE131_MU_CNT of U0 : label is 1;
  attribute C_PROBE131_TYPE : integer;
  attribute C_PROBE131_TYPE of U0 : label is 1;
  attribute C_PROBE131_WIDTH : integer;
  attribute C_PROBE131_WIDTH of U0 : label is 1;
  attribute C_PROBE132_MU_CNT : integer;
  attribute C_PROBE132_MU_CNT of U0 : label is 1;
  attribute C_PROBE132_TYPE : integer;
  attribute C_PROBE132_TYPE of U0 : label is 1;
  attribute C_PROBE132_WIDTH : integer;
  attribute C_PROBE132_WIDTH of U0 : label is 1;
  attribute C_PROBE133_MU_CNT : integer;
  attribute C_PROBE133_MU_CNT of U0 : label is 1;
  attribute C_PROBE133_TYPE : integer;
  attribute C_PROBE133_TYPE of U0 : label is 1;
  attribute C_PROBE133_WIDTH : integer;
  attribute C_PROBE133_WIDTH of U0 : label is 1;
  attribute C_PROBE134_MU_CNT : integer;
  attribute C_PROBE134_MU_CNT of U0 : label is 1;
  attribute C_PROBE134_TYPE : integer;
  attribute C_PROBE134_TYPE of U0 : label is 1;
  attribute C_PROBE134_WIDTH : integer;
  attribute C_PROBE134_WIDTH of U0 : label is 1;
  attribute C_PROBE135_MU_CNT : integer;
  attribute C_PROBE135_MU_CNT of U0 : label is 1;
  attribute C_PROBE135_TYPE : integer;
  attribute C_PROBE135_TYPE of U0 : label is 1;
  attribute C_PROBE135_WIDTH : integer;
  attribute C_PROBE135_WIDTH of U0 : label is 1;
  attribute C_PROBE136_MU_CNT : integer;
  attribute C_PROBE136_MU_CNT of U0 : label is 1;
  attribute C_PROBE136_TYPE : integer;
  attribute C_PROBE136_TYPE of U0 : label is 1;
  attribute C_PROBE136_WIDTH : integer;
  attribute C_PROBE136_WIDTH of U0 : label is 1;
  attribute C_PROBE137_MU_CNT : integer;
  attribute C_PROBE137_MU_CNT of U0 : label is 1;
  attribute C_PROBE137_TYPE : integer;
  attribute C_PROBE137_TYPE of U0 : label is 1;
  attribute C_PROBE137_WIDTH : integer;
  attribute C_PROBE137_WIDTH of U0 : label is 1;
  attribute C_PROBE138_MU_CNT : integer;
  attribute C_PROBE138_MU_CNT of U0 : label is 1;
  attribute C_PROBE138_TYPE : integer;
  attribute C_PROBE138_TYPE of U0 : label is 1;
  attribute C_PROBE138_WIDTH : integer;
  attribute C_PROBE138_WIDTH of U0 : label is 1;
  attribute C_PROBE139_MU_CNT : integer;
  attribute C_PROBE139_MU_CNT of U0 : label is 1;
  attribute C_PROBE139_TYPE : integer;
  attribute C_PROBE139_TYPE of U0 : label is 1;
  attribute C_PROBE139_WIDTH : integer;
  attribute C_PROBE139_WIDTH of U0 : label is 1;
  attribute C_PROBE13_MU_CNT : integer;
  attribute C_PROBE13_MU_CNT of U0 : label is 1;
  attribute C_PROBE13_TYPE : integer;
  attribute C_PROBE13_TYPE of U0 : label is 1;
  attribute C_PROBE13_WIDTH : integer;
  attribute C_PROBE13_WIDTH of U0 : label is 1;
  attribute C_PROBE140_MU_CNT : integer;
  attribute C_PROBE140_MU_CNT of U0 : label is 1;
  attribute C_PROBE140_TYPE : integer;
  attribute C_PROBE140_TYPE of U0 : label is 1;
  attribute C_PROBE140_WIDTH : integer;
  attribute C_PROBE140_WIDTH of U0 : label is 1;
  attribute C_PROBE141_MU_CNT : integer;
  attribute C_PROBE141_MU_CNT of U0 : label is 1;
  attribute C_PROBE141_TYPE : integer;
  attribute C_PROBE141_TYPE of U0 : label is 1;
  attribute C_PROBE141_WIDTH : integer;
  attribute C_PROBE141_WIDTH of U0 : label is 1;
  attribute C_PROBE142_MU_CNT : integer;
  attribute C_PROBE142_MU_CNT of U0 : label is 1;
  attribute C_PROBE142_TYPE : integer;
  attribute C_PROBE142_TYPE of U0 : label is 1;
  attribute C_PROBE142_WIDTH : integer;
  attribute C_PROBE142_WIDTH of U0 : label is 1;
  attribute C_PROBE143_MU_CNT : integer;
  attribute C_PROBE143_MU_CNT of U0 : label is 1;
  attribute C_PROBE143_TYPE : integer;
  attribute C_PROBE143_TYPE of U0 : label is 1;
  attribute C_PROBE143_WIDTH : integer;
  attribute C_PROBE143_WIDTH of U0 : label is 1;
  attribute C_PROBE144_MU_CNT : integer;
  attribute C_PROBE144_MU_CNT of U0 : label is 1;
  attribute C_PROBE144_TYPE : integer;
  attribute C_PROBE144_TYPE of U0 : label is 1;
  attribute C_PROBE144_WIDTH : integer;
  attribute C_PROBE144_WIDTH of U0 : label is 1;
  attribute C_PROBE145_MU_CNT : integer;
  attribute C_PROBE145_MU_CNT of U0 : label is 1;
  attribute C_PROBE145_TYPE : integer;
  attribute C_PROBE145_TYPE of U0 : label is 1;
  attribute C_PROBE145_WIDTH : integer;
  attribute C_PROBE145_WIDTH of U0 : label is 1;
  attribute C_PROBE146_MU_CNT : integer;
  attribute C_PROBE146_MU_CNT of U0 : label is 1;
  attribute C_PROBE146_TYPE : integer;
  attribute C_PROBE146_TYPE of U0 : label is 1;
  attribute C_PROBE146_WIDTH : integer;
  attribute C_PROBE146_WIDTH of U0 : label is 1;
  attribute C_PROBE147_MU_CNT : integer;
  attribute C_PROBE147_MU_CNT of U0 : label is 1;
  attribute C_PROBE147_TYPE : integer;
  attribute C_PROBE147_TYPE of U0 : label is 1;
  attribute C_PROBE147_WIDTH : integer;
  attribute C_PROBE147_WIDTH of U0 : label is 1;
  attribute C_PROBE148_MU_CNT : integer;
  attribute C_PROBE148_MU_CNT of U0 : label is 1;
  attribute C_PROBE148_TYPE : integer;
  attribute C_PROBE148_TYPE of U0 : label is 1;
  attribute C_PROBE148_WIDTH : integer;
  attribute C_PROBE148_WIDTH of U0 : label is 1;
  attribute C_PROBE149_MU_CNT : integer;
  attribute C_PROBE149_MU_CNT of U0 : label is 1;
  attribute C_PROBE149_TYPE : integer;
  attribute C_PROBE149_TYPE of U0 : label is 1;
  attribute C_PROBE149_WIDTH : integer;
  attribute C_PROBE149_WIDTH of U0 : label is 1;
  attribute C_PROBE14_MU_CNT : integer;
  attribute C_PROBE14_MU_CNT of U0 : label is 1;
  attribute C_PROBE14_TYPE : integer;
  attribute C_PROBE14_TYPE of U0 : label is 1;
  attribute C_PROBE14_WIDTH : integer;
  attribute C_PROBE14_WIDTH of U0 : label is 1;
  attribute C_PROBE150_MU_CNT : integer;
  attribute C_PROBE150_MU_CNT of U0 : label is 1;
  attribute C_PROBE150_TYPE : integer;
  attribute C_PROBE150_TYPE of U0 : label is 1;
  attribute C_PROBE150_WIDTH : integer;
  attribute C_PROBE150_WIDTH of U0 : label is 1;
  attribute C_PROBE151_MU_CNT : integer;
  attribute C_PROBE151_MU_CNT of U0 : label is 1;
  attribute C_PROBE151_TYPE : integer;
  attribute C_PROBE151_TYPE of U0 : label is 1;
  attribute C_PROBE151_WIDTH : integer;
  attribute C_PROBE151_WIDTH of U0 : label is 1;
  attribute C_PROBE152_MU_CNT : integer;
  attribute C_PROBE152_MU_CNT of U0 : label is 1;
  attribute C_PROBE152_TYPE : integer;
  attribute C_PROBE152_TYPE of U0 : label is 1;
  attribute C_PROBE152_WIDTH : integer;
  attribute C_PROBE152_WIDTH of U0 : label is 1;
  attribute C_PROBE153_MU_CNT : integer;
  attribute C_PROBE153_MU_CNT of U0 : label is 1;
  attribute C_PROBE153_TYPE : integer;
  attribute C_PROBE153_TYPE of U0 : label is 1;
  attribute C_PROBE153_WIDTH : integer;
  attribute C_PROBE153_WIDTH of U0 : label is 1;
  attribute C_PROBE154_MU_CNT : integer;
  attribute C_PROBE154_MU_CNT of U0 : label is 1;
  attribute C_PROBE154_TYPE : integer;
  attribute C_PROBE154_TYPE of U0 : label is 1;
  attribute C_PROBE154_WIDTH : integer;
  attribute C_PROBE154_WIDTH of U0 : label is 1;
  attribute C_PROBE155_MU_CNT : integer;
  attribute C_PROBE155_MU_CNT of U0 : label is 1;
  attribute C_PROBE155_TYPE : integer;
  attribute C_PROBE155_TYPE of U0 : label is 1;
  attribute C_PROBE155_WIDTH : integer;
  attribute C_PROBE155_WIDTH of U0 : label is 1;
  attribute C_PROBE156_MU_CNT : integer;
  attribute C_PROBE156_MU_CNT of U0 : label is 1;
  attribute C_PROBE156_TYPE : integer;
  attribute C_PROBE156_TYPE of U0 : label is 1;
  attribute C_PROBE156_WIDTH : integer;
  attribute C_PROBE156_WIDTH of U0 : label is 1;
  attribute C_PROBE157_MU_CNT : integer;
  attribute C_PROBE157_MU_CNT of U0 : label is 1;
  attribute C_PROBE157_TYPE : integer;
  attribute C_PROBE157_TYPE of U0 : label is 1;
  attribute C_PROBE157_WIDTH : integer;
  attribute C_PROBE157_WIDTH of U0 : label is 1;
  attribute C_PROBE158_MU_CNT : integer;
  attribute C_PROBE158_MU_CNT of U0 : label is 1;
  attribute C_PROBE158_TYPE : integer;
  attribute C_PROBE158_TYPE of U0 : label is 1;
  attribute C_PROBE158_WIDTH : integer;
  attribute C_PROBE158_WIDTH of U0 : label is 1;
  attribute C_PROBE159_MU_CNT : integer;
  attribute C_PROBE159_MU_CNT of U0 : label is 1;
  attribute C_PROBE159_TYPE : integer;
  attribute C_PROBE159_TYPE of U0 : label is 1;
  attribute C_PROBE159_WIDTH : integer;
  attribute C_PROBE159_WIDTH of U0 : label is 1;
  attribute C_PROBE15_MU_CNT : integer;
  attribute C_PROBE15_MU_CNT of U0 : label is 1;
  attribute C_PROBE15_TYPE : integer;
  attribute C_PROBE15_TYPE of U0 : label is 1;
  attribute C_PROBE15_WIDTH : integer;
  attribute C_PROBE15_WIDTH of U0 : label is 1;
  attribute C_PROBE160_MU_CNT : integer;
  attribute C_PROBE160_MU_CNT of U0 : label is 1;
  attribute C_PROBE160_TYPE : integer;
  attribute C_PROBE160_TYPE of U0 : label is 1;
  attribute C_PROBE160_WIDTH : integer;
  attribute C_PROBE160_WIDTH of U0 : label is 1;
  attribute C_PROBE161_MU_CNT : integer;
  attribute C_PROBE161_MU_CNT of U0 : label is 1;
  attribute C_PROBE161_TYPE : integer;
  attribute C_PROBE161_TYPE of U0 : label is 1;
  attribute C_PROBE161_WIDTH : integer;
  attribute C_PROBE161_WIDTH of U0 : label is 1;
  attribute C_PROBE162_MU_CNT : integer;
  attribute C_PROBE162_MU_CNT of U0 : label is 1;
  attribute C_PROBE162_TYPE : integer;
  attribute C_PROBE162_TYPE of U0 : label is 1;
  attribute C_PROBE162_WIDTH : integer;
  attribute C_PROBE162_WIDTH of U0 : label is 1;
  attribute C_PROBE163_MU_CNT : integer;
  attribute C_PROBE163_MU_CNT of U0 : label is 1;
  attribute C_PROBE163_TYPE : integer;
  attribute C_PROBE163_TYPE of U0 : label is 1;
  attribute C_PROBE163_WIDTH : integer;
  attribute C_PROBE163_WIDTH of U0 : label is 1;
  attribute C_PROBE164_MU_CNT : integer;
  attribute C_PROBE164_MU_CNT of U0 : label is 1;
  attribute C_PROBE164_TYPE : integer;
  attribute C_PROBE164_TYPE of U0 : label is 1;
  attribute C_PROBE164_WIDTH : integer;
  attribute C_PROBE164_WIDTH of U0 : label is 1;
  attribute C_PROBE165_MU_CNT : integer;
  attribute C_PROBE165_MU_CNT of U0 : label is 1;
  attribute C_PROBE165_TYPE : integer;
  attribute C_PROBE165_TYPE of U0 : label is 1;
  attribute C_PROBE165_WIDTH : integer;
  attribute C_PROBE165_WIDTH of U0 : label is 1;
  attribute C_PROBE166_MU_CNT : integer;
  attribute C_PROBE166_MU_CNT of U0 : label is 1;
  attribute C_PROBE166_TYPE : integer;
  attribute C_PROBE166_TYPE of U0 : label is 1;
  attribute C_PROBE166_WIDTH : integer;
  attribute C_PROBE166_WIDTH of U0 : label is 1;
  attribute C_PROBE167_MU_CNT : integer;
  attribute C_PROBE167_MU_CNT of U0 : label is 1;
  attribute C_PROBE167_TYPE : integer;
  attribute C_PROBE167_TYPE of U0 : label is 1;
  attribute C_PROBE167_WIDTH : integer;
  attribute C_PROBE167_WIDTH of U0 : label is 1;
  attribute C_PROBE168_MU_CNT : integer;
  attribute C_PROBE168_MU_CNT of U0 : label is 1;
  attribute C_PROBE168_TYPE : integer;
  attribute C_PROBE168_TYPE of U0 : label is 1;
  attribute C_PROBE168_WIDTH : integer;
  attribute C_PROBE168_WIDTH of U0 : label is 1;
  attribute C_PROBE169_MU_CNT : integer;
  attribute C_PROBE169_MU_CNT of U0 : label is 1;
  attribute C_PROBE169_TYPE : integer;
  attribute C_PROBE169_TYPE of U0 : label is 1;
  attribute C_PROBE169_WIDTH : integer;
  attribute C_PROBE169_WIDTH of U0 : label is 1;
  attribute C_PROBE16_MU_CNT : integer;
  attribute C_PROBE16_MU_CNT of U0 : label is 1;
  attribute C_PROBE16_TYPE : integer;
  attribute C_PROBE16_TYPE of U0 : label is 1;
  attribute C_PROBE16_WIDTH : integer;
  attribute C_PROBE16_WIDTH of U0 : label is 1;
  attribute C_PROBE170_MU_CNT : integer;
  attribute C_PROBE170_MU_CNT of U0 : label is 1;
  attribute C_PROBE170_TYPE : integer;
  attribute C_PROBE170_TYPE of U0 : label is 1;
  attribute C_PROBE170_WIDTH : integer;
  attribute C_PROBE170_WIDTH of U0 : label is 1;
  attribute C_PROBE171_MU_CNT : integer;
  attribute C_PROBE171_MU_CNT of U0 : label is 1;
  attribute C_PROBE171_TYPE : integer;
  attribute C_PROBE171_TYPE of U0 : label is 1;
  attribute C_PROBE171_WIDTH : integer;
  attribute C_PROBE171_WIDTH of U0 : label is 1;
  attribute C_PROBE172_MU_CNT : integer;
  attribute C_PROBE172_MU_CNT of U0 : label is 1;
  attribute C_PROBE172_TYPE : integer;
  attribute C_PROBE172_TYPE of U0 : label is 1;
  attribute C_PROBE172_WIDTH : integer;
  attribute C_PROBE172_WIDTH of U0 : label is 1;
  attribute C_PROBE173_MU_CNT : integer;
  attribute C_PROBE173_MU_CNT of U0 : label is 1;
  attribute C_PROBE173_TYPE : integer;
  attribute C_PROBE173_TYPE of U0 : label is 1;
  attribute C_PROBE173_WIDTH : integer;
  attribute C_PROBE173_WIDTH of U0 : label is 1;
  attribute C_PROBE174_MU_CNT : integer;
  attribute C_PROBE174_MU_CNT of U0 : label is 1;
  attribute C_PROBE174_TYPE : integer;
  attribute C_PROBE174_TYPE of U0 : label is 1;
  attribute C_PROBE174_WIDTH : integer;
  attribute C_PROBE174_WIDTH of U0 : label is 1;
  attribute C_PROBE175_MU_CNT : integer;
  attribute C_PROBE175_MU_CNT of U0 : label is 1;
  attribute C_PROBE175_TYPE : integer;
  attribute C_PROBE175_TYPE of U0 : label is 1;
  attribute C_PROBE175_WIDTH : integer;
  attribute C_PROBE175_WIDTH of U0 : label is 1;
  attribute C_PROBE176_MU_CNT : integer;
  attribute C_PROBE176_MU_CNT of U0 : label is 1;
  attribute C_PROBE176_TYPE : integer;
  attribute C_PROBE176_TYPE of U0 : label is 1;
  attribute C_PROBE176_WIDTH : integer;
  attribute C_PROBE176_WIDTH of U0 : label is 1;
  attribute C_PROBE177_MU_CNT : integer;
  attribute C_PROBE177_MU_CNT of U0 : label is 1;
  attribute C_PROBE177_TYPE : integer;
  attribute C_PROBE177_TYPE of U0 : label is 1;
  attribute C_PROBE177_WIDTH : integer;
  attribute C_PROBE177_WIDTH of U0 : label is 1;
  attribute C_PROBE178_MU_CNT : integer;
  attribute C_PROBE178_MU_CNT of U0 : label is 1;
  attribute C_PROBE178_TYPE : integer;
  attribute C_PROBE178_TYPE of U0 : label is 1;
  attribute C_PROBE178_WIDTH : integer;
  attribute C_PROBE178_WIDTH of U0 : label is 1;
  attribute C_PROBE179_MU_CNT : integer;
  attribute C_PROBE179_MU_CNT of U0 : label is 1;
  attribute C_PROBE179_TYPE : integer;
  attribute C_PROBE179_TYPE of U0 : label is 1;
  attribute C_PROBE179_WIDTH : integer;
  attribute C_PROBE179_WIDTH of U0 : label is 1;
  attribute C_PROBE17_MU_CNT : integer;
  attribute C_PROBE17_MU_CNT of U0 : label is 1;
  attribute C_PROBE17_TYPE : integer;
  attribute C_PROBE17_TYPE of U0 : label is 1;
  attribute C_PROBE17_WIDTH : integer;
  attribute C_PROBE17_WIDTH of U0 : label is 1;
  attribute C_PROBE180_MU_CNT : integer;
  attribute C_PROBE180_MU_CNT of U0 : label is 1;
  attribute C_PROBE180_TYPE : integer;
  attribute C_PROBE180_TYPE of U0 : label is 1;
  attribute C_PROBE180_WIDTH : integer;
  attribute C_PROBE180_WIDTH of U0 : label is 1;
  attribute C_PROBE181_MU_CNT : integer;
  attribute C_PROBE181_MU_CNT of U0 : label is 1;
  attribute C_PROBE181_TYPE : integer;
  attribute C_PROBE181_TYPE of U0 : label is 1;
  attribute C_PROBE181_WIDTH : integer;
  attribute C_PROBE181_WIDTH of U0 : label is 1;
  attribute C_PROBE182_MU_CNT : integer;
  attribute C_PROBE182_MU_CNT of U0 : label is 1;
  attribute C_PROBE182_TYPE : integer;
  attribute C_PROBE182_TYPE of U0 : label is 1;
  attribute C_PROBE182_WIDTH : integer;
  attribute C_PROBE182_WIDTH of U0 : label is 1;
  attribute C_PROBE183_MU_CNT : integer;
  attribute C_PROBE183_MU_CNT of U0 : label is 1;
  attribute C_PROBE183_TYPE : integer;
  attribute C_PROBE183_TYPE of U0 : label is 1;
  attribute C_PROBE183_WIDTH : integer;
  attribute C_PROBE183_WIDTH of U0 : label is 1;
  attribute C_PROBE184_MU_CNT : integer;
  attribute C_PROBE184_MU_CNT of U0 : label is 1;
  attribute C_PROBE184_TYPE : integer;
  attribute C_PROBE184_TYPE of U0 : label is 1;
  attribute C_PROBE184_WIDTH : integer;
  attribute C_PROBE184_WIDTH of U0 : label is 1;
  attribute C_PROBE185_MU_CNT : integer;
  attribute C_PROBE185_MU_CNT of U0 : label is 1;
  attribute C_PROBE185_TYPE : integer;
  attribute C_PROBE185_TYPE of U0 : label is 1;
  attribute C_PROBE185_WIDTH : integer;
  attribute C_PROBE185_WIDTH of U0 : label is 1;
  attribute C_PROBE186_MU_CNT : integer;
  attribute C_PROBE186_MU_CNT of U0 : label is 1;
  attribute C_PROBE186_TYPE : integer;
  attribute C_PROBE186_TYPE of U0 : label is 1;
  attribute C_PROBE186_WIDTH : integer;
  attribute C_PROBE186_WIDTH of U0 : label is 1;
  attribute C_PROBE187_MU_CNT : integer;
  attribute C_PROBE187_MU_CNT of U0 : label is 1;
  attribute C_PROBE187_TYPE : integer;
  attribute C_PROBE187_TYPE of U0 : label is 1;
  attribute C_PROBE187_WIDTH : integer;
  attribute C_PROBE187_WIDTH of U0 : label is 1;
  attribute C_PROBE188_MU_CNT : integer;
  attribute C_PROBE188_MU_CNT of U0 : label is 1;
  attribute C_PROBE188_TYPE : integer;
  attribute C_PROBE188_TYPE of U0 : label is 1;
  attribute C_PROBE188_WIDTH : integer;
  attribute C_PROBE188_WIDTH of U0 : label is 1;
  attribute C_PROBE189_MU_CNT : integer;
  attribute C_PROBE189_MU_CNT of U0 : label is 1;
  attribute C_PROBE189_TYPE : integer;
  attribute C_PROBE189_TYPE of U0 : label is 1;
  attribute C_PROBE189_WIDTH : integer;
  attribute C_PROBE189_WIDTH of U0 : label is 1;
  attribute C_PROBE18_MU_CNT : integer;
  attribute C_PROBE18_MU_CNT of U0 : label is 1;
  attribute C_PROBE18_TYPE : integer;
  attribute C_PROBE18_TYPE of U0 : label is 1;
  attribute C_PROBE18_WIDTH : integer;
  attribute C_PROBE18_WIDTH of U0 : label is 1;
  attribute C_PROBE190_MU_CNT : integer;
  attribute C_PROBE190_MU_CNT of U0 : label is 1;
  attribute C_PROBE190_TYPE : integer;
  attribute C_PROBE190_TYPE of U0 : label is 1;
  attribute C_PROBE190_WIDTH : integer;
  attribute C_PROBE190_WIDTH of U0 : label is 1;
  attribute C_PROBE191_MU_CNT : integer;
  attribute C_PROBE191_MU_CNT of U0 : label is 1;
  attribute C_PROBE191_TYPE : integer;
  attribute C_PROBE191_TYPE of U0 : label is 1;
  attribute C_PROBE191_WIDTH : integer;
  attribute C_PROBE191_WIDTH of U0 : label is 1;
  attribute C_PROBE192_MU_CNT : integer;
  attribute C_PROBE192_MU_CNT of U0 : label is 1;
  attribute C_PROBE192_TYPE : integer;
  attribute C_PROBE192_TYPE of U0 : label is 1;
  attribute C_PROBE192_WIDTH : integer;
  attribute C_PROBE192_WIDTH of U0 : label is 1;
  attribute C_PROBE193_MU_CNT : integer;
  attribute C_PROBE193_MU_CNT of U0 : label is 1;
  attribute C_PROBE193_TYPE : integer;
  attribute C_PROBE193_TYPE of U0 : label is 1;
  attribute C_PROBE193_WIDTH : integer;
  attribute C_PROBE193_WIDTH of U0 : label is 1;
  attribute C_PROBE194_MU_CNT : integer;
  attribute C_PROBE194_MU_CNT of U0 : label is 1;
  attribute C_PROBE194_TYPE : integer;
  attribute C_PROBE194_TYPE of U0 : label is 1;
  attribute C_PROBE194_WIDTH : integer;
  attribute C_PROBE194_WIDTH of U0 : label is 1;
  attribute C_PROBE195_MU_CNT : integer;
  attribute C_PROBE195_MU_CNT of U0 : label is 1;
  attribute C_PROBE195_TYPE : integer;
  attribute C_PROBE195_TYPE of U0 : label is 1;
  attribute C_PROBE195_WIDTH : integer;
  attribute C_PROBE195_WIDTH of U0 : label is 1;
  attribute C_PROBE196_MU_CNT : integer;
  attribute C_PROBE196_MU_CNT of U0 : label is 1;
  attribute C_PROBE196_TYPE : integer;
  attribute C_PROBE196_TYPE of U0 : label is 1;
  attribute C_PROBE196_WIDTH : integer;
  attribute C_PROBE196_WIDTH of U0 : label is 1;
  attribute C_PROBE197_MU_CNT : integer;
  attribute C_PROBE197_MU_CNT of U0 : label is 1;
  attribute C_PROBE197_TYPE : integer;
  attribute C_PROBE197_TYPE of U0 : label is 1;
  attribute C_PROBE197_WIDTH : integer;
  attribute C_PROBE197_WIDTH of U0 : label is 1;
  attribute C_PROBE198_MU_CNT : integer;
  attribute C_PROBE198_MU_CNT of U0 : label is 1;
  attribute C_PROBE198_TYPE : integer;
  attribute C_PROBE198_TYPE of U0 : label is 1;
  attribute C_PROBE198_WIDTH : integer;
  attribute C_PROBE198_WIDTH of U0 : label is 1;
  attribute C_PROBE199_MU_CNT : integer;
  attribute C_PROBE199_MU_CNT of U0 : label is 1;
  attribute C_PROBE199_TYPE : integer;
  attribute C_PROBE199_TYPE of U0 : label is 1;
  attribute C_PROBE199_WIDTH : integer;
  attribute C_PROBE199_WIDTH of U0 : label is 1;
  attribute C_PROBE19_MU_CNT : integer;
  attribute C_PROBE19_MU_CNT of U0 : label is 1;
  attribute C_PROBE19_TYPE : integer;
  attribute C_PROBE19_TYPE of U0 : label is 1;
  attribute C_PROBE19_WIDTH : integer;
  attribute C_PROBE19_WIDTH of U0 : label is 1;
  attribute C_PROBE1_MU_CNT : integer;
  attribute C_PROBE1_MU_CNT of U0 : label is 1;
  attribute C_PROBE1_TYPE : integer;
  attribute C_PROBE1_TYPE of U0 : label is 0;
  attribute C_PROBE1_WIDTH : integer;
  attribute C_PROBE1_WIDTH of U0 : label is 1;
  attribute C_PROBE200_MU_CNT : integer;
  attribute C_PROBE200_MU_CNT of U0 : label is 1;
  attribute C_PROBE200_TYPE : integer;
  attribute C_PROBE200_TYPE of U0 : label is 1;
  attribute C_PROBE200_WIDTH : integer;
  attribute C_PROBE200_WIDTH of U0 : label is 1;
  attribute C_PROBE201_MU_CNT : integer;
  attribute C_PROBE201_MU_CNT of U0 : label is 1;
  attribute C_PROBE201_TYPE : integer;
  attribute C_PROBE201_TYPE of U0 : label is 1;
  attribute C_PROBE201_WIDTH : integer;
  attribute C_PROBE201_WIDTH of U0 : label is 1;
  attribute C_PROBE202_MU_CNT : integer;
  attribute C_PROBE202_MU_CNT of U0 : label is 1;
  attribute C_PROBE202_TYPE : integer;
  attribute C_PROBE202_TYPE of U0 : label is 1;
  attribute C_PROBE202_WIDTH : integer;
  attribute C_PROBE202_WIDTH of U0 : label is 1;
  attribute C_PROBE203_MU_CNT : integer;
  attribute C_PROBE203_MU_CNT of U0 : label is 1;
  attribute C_PROBE203_TYPE : integer;
  attribute C_PROBE203_TYPE of U0 : label is 1;
  attribute C_PROBE203_WIDTH : integer;
  attribute C_PROBE203_WIDTH of U0 : label is 1;
  attribute C_PROBE204_MU_CNT : integer;
  attribute C_PROBE204_MU_CNT of U0 : label is 1;
  attribute C_PROBE204_TYPE : integer;
  attribute C_PROBE204_TYPE of U0 : label is 1;
  attribute C_PROBE204_WIDTH : integer;
  attribute C_PROBE204_WIDTH of U0 : label is 1;
  attribute C_PROBE205_MU_CNT : integer;
  attribute C_PROBE205_MU_CNT of U0 : label is 1;
  attribute C_PROBE205_TYPE : integer;
  attribute C_PROBE205_TYPE of U0 : label is 1;
  attribute C_PROBE205_WIDTH : integer;
  attribute C_PROBE205_WIDTH of U0 : label is 1;
  attribute C_PROBE206_MU_CNT : integer;
  attribute C_PROBE206_MU_CNT of U0 : label is 1;
  attribute C_PROBE206_TYPE : integer;
  attribute C_PROBE206_TYPE of U0 : label is 1;
  attribute C_PROBE206_WIDTH : integer;
  attribute C_PROBE206_WIDTH of U0 : label is 1;
  attribute C_PROBE207_MU_CNT : integer;
  attribute C_PROBE207_MU_CNT of U0 : label is 1;
  attribute C_PROBE207_TYPE : integer;
  attribute C_PROBE207_TYPE of U0 : label is 1;
  attribute C_PROBE207_WIDTH : integer;
  attribute C_PROBE207_WIDTH of U0 : label is 1;
  attribute C_PROBE208_MU_CNT : integer;
  attribute C_PROBE208_MU_CNT of U0 : label is 1;
  attribute C_PROBE208_TYPE : integer;
  attribute C_PROBE208_TYPE of U0 : label is 1;
  attribute C_PROBE208_WIDTH : integer;
  attribute C_PROBE208_WIDTH of U0 : label is 1;
  attribute C_PROBE209_MU_CNT : integer;
  attribute C_PROBE209_MU_CNT of U0 : label is 1;
  attribute C_PROBE209_TYPE : integer;
  attribute C_PROBE209_TYPE of U0 : label is 1;
  attribute C_PROBE209_WIDTH : integer;
  attribute C_PROBE209_WIDTH of U0 : label is 1;
  attribute C_PROBE20_MU_CNT : integer;
  attribute C_PROBE20_MU_CNT of U0 : label is 1;
  attribute C_PROBE20_TYPE : integer;
  attribute C_PROBE20_TYPE of U0 : label is 1;
  attribute C_PROBE20_WIDTH : integer;
  attribute C_PROBE20_WIDTH of U0 : label is 1;
  attribute C_PROBE210_MU_CNT : integer;
  attribute C_PROBE210_MU_CNT of U0 : label is 1;
  attribute C_PROBE210_TYPE : integer;
  attribute C_PROBE210_TYPE of U0 : label is 1;
  attribute C_PROBE210_WIDTH : integer;
  attribute C_PROBE210_WIDTH of U0 : label is 1;
  attribute C_PROBE211_MU_CNT : integer;
  attribute C_PROBE211_MU_CNT of U0 : label is 1;
  attribute C_PROBE211_TYPE : integer;
  attribute C_PROBE211_TYPE of U0 : label is 1;
  attribute C_PROBE211_WIDTH : integer;
  attribute C_PROBE211_WIDTH of U0 : label is 1;
  attribute C_PROBE212_MU_CNT : integer;
  attribute C_PROBE212_MU_CNT of U0 : label is 1;
  attribute C_PROBE212_TYPE : integer;
  attribute C_PROBE212_TYPE of U0 : label is 1;
  attribute C_PROBE212_WIDTH : integer;
  attribute C_PROBE212_WIDTH of U0 : label is 1;
  attribute C_PROBE213_MU_CNT : integer;
  attribute C_PROBE213_MU_CNT of U0 : label is 1;
  attribute C_PROBE213_TYPE : integer;
  attribute C_PROBE213_TYPE of U0 : label is 1;
  attribute C_PROBE213_WIDTH : integer;
  attribute C_PROBE213_WIDTH of U0 : label is 1;
  attribute C_PROBE214_MU_CNT : integer;
  attribute C_PROBE214_MU_CNT of U0 : label is 1;
  attribute C_PROBE214_TYPE : integer;
  attribute C_PROBE214_TYPE of U0 : label is 1;
  attribute C_PROBE214_WIDTH : integer;
  attribute C_PROBE214_WIDTH of U0 : label is 1;
  attribute C_PROBE215_MU_CNT : integer;
  attribute C_PROBE215_MU_CNT of U0 : label is 1;
  attribute C_PROBE215_TYPE : integer;
  attribute C_PROBE215_TYPE of U0 : label is 1;
  attribute C_PROBE215_WIDTH : integer;
  attribute C_PROBE215_WIDTH of U0 : label is 1;
  attribute C_PROBE216_MU_CNT : integer;
  attribute C_PROBE216_MU_CNT of U0 : label is 1;
  attribute C_PROBE216_TYPE : integer;
  attribute C_PROBE216_TYPE of U0 : label is 1;
  attribute C_PROBE216_WIDTH : integer;
  attribute C_PROBE216_WIDTH of U0 : label is 1;
  attribute C_PROBE217_MU_CNT : integer;
  attribute C_PROBE217_MU_CNT of U0 : label is 1;
  attribute C_PROBE217_TYPE : integer;
  attribute C_PROBE217_TYPE of U0 : label is 1;
  attribute C_PROBE217_WIDTH : integer;
  attribute C_PROBE217_WIDTH of U0 : label is 1;
  attribute C_PROBE218_MU_CNT : integer;
  attribute C_PROBE218_MU_CNT of U0 : label is 1;
  attribute C_PROBE218_TYPE : integer;
  attribute C_PROBE218_TYPE of U0 : label is 1;
  attribute C_PROBE218_WIDTH : integer;
  attribute C_PROBE218_WIDTH of U0 : label is 1;
  attribute C_PROBE219_MU_CNT : integer;
  attribute C_PROBE219_MU_CNT of U0 : label is 1;
  attribute C_PROBE219_TYPE : integer;
  attribute C_PROBE219_TYPE of U0 : label is 1;
  attribute C_PROBE219_WIDTH : integer;
  attribute C_PROBE219_WIDTH of U0 : label is 1;
  attribute C_PROBE21_MU_CNT : integer;
  attribute C_PROBE21_MU_CNT of U0 : label is 1;
  attribute C_PROBE21_TYPE : integer;
  attribute C_PROBE21_TYPE of U0 : label is 1;
  attribute C_PROBE21_WIDTH : integer;
  attribute C_PROBE21_WIDTH of U0 : label is 1;
  attribute C_PROBE220_MU_CNT : integer;
  attribute C_PROBE220_MU_CNT of U0 : label is 1;
  attribute C_PROBE220_TYPE : integer;
  attribute C_PROBE220_TYPE of U0 : label is 1;
  attribute C_PROBE220_WIDTH : integer;
  attribute C_PROBE220_WIDTH of U0 : label is 1;
  attribute C_PROBE221_MU_CNT : integer;
  attribute C_PROBE221_MU_CNT of U0 : label is 1;
  attribute C_PROBE221_TYPE : integer;
  attribute C_PROBE221_TYPE of U0 : label is 1;
  attribute C_PROBE221_WIDTH : integer;
  attribute C_PROBE221_WIDTH of U0 : label is 1;
  attribute C_PROBE222_MU_CNT : integer;
  attribute C_PROBE222_MU_CNT of U0 : label is 1;
  attribute C_PROBE222_TYPE : integer;
  attribute C_PROBE222_TYPE of U0 : label is 1;
  attribute C_PROBE222_WIDTH : integer;
  attribute C_PROBE222_WIDTH of U0 : label is 1;
  attribute C_PROBE223_MU_CNT : integer;
  attribute C_PROBE223_MU_CNT of U0 : label is 1;
  attribute C_PROBE223_TYPE : integer;
  attribute C_PROBE223_TYPE of U0 : label is 1;
  attribute C_PROBE223_WIDTH : integer;
  attribute C_PROBE223_WIDTH of U0 : label is 1;
  attribute C_PROBE224_MU_CNT : integer;
  attribute C_PROBE224_MU_CNT of U0 : label is 1;
  attribute C_PROBE224_TYPE : integer;
  attribute C_PROBE224_TYPE of U0 : label is 1;
  attribute C_PROBE224_WIDTH : integer;
  attribute C_PROBE224_WIDTH of U0 : label is 1;
  attribute C_PROBE225_MU_CNT : integer;
  attribute C_PROBE225_MU_CNT of U0 : label is 1;
  attribute C_PROBE225_TYPE : integer;
  attribute C_PROBE225_TYPE of U0 : label is 1;
  attribute C_PROBE225_WIDTH : integer;
  attribute C_PROBE225_WIDTH of U0 : label is 1;
  attribute C_PROBE226_MU_CNT : integer;
  attribute C_PROBE226_MU_CNT of U0 : label is 1;
  attribute C_PROBE226_TYPE : integer;
  attribute C_PROBE226_TYPE of U0 : label is 1;
  attribute C_PROBE226_WIDTH : integer;
  attribute C_PROBE226_WIDTH of U0 : label is 1;
  attribute C_PROBE227_MU_CNT : integer;
  attribute C_PROBE227_MU_CNT of U0 : label is 1;
  attribute C_PROBE227_TYPE : integer;
  attribute C_PROBE227_TYPE of U0 : label is 1;
  attribute C_PROBE227_WIDTH : integer;
  attribute C_PROBE227_WIDTH of U0 : label is 1;
  attribute C_PROBE228_MU_CNT : integer;
  attribute C_PROBE228_MU_CNT of U0 : label is 1;
  attribute C_PROBE228_TYPE : integer;
  attribute C_PROBE228_TYPE of U0 : label is 1;
  attribute C_PROBE228_WIDTH : integer;
  attribute C_PROBE228_WIDTH of U0 : label is 1;
  attribute C_PROBE229_MU_CNT : integer;
  attribute C_PROBE229_MU_CNT of U0 : label is 1;
  attribute C_PROBE229_TYPE : integer;
  attribute C_PROBE229_TYPE of U0 : label is 1;
  attribute C_PROBE229_WIDTH : integer;
  attribute C_PROBE229_WIDTH of U0 : label is 1;
  attribute C_PROBE22_MU_CNT : integer;
  attribute C_PROBE22_MU_CNT of U0 : label is 1;
  attribute C_PROBE22_TYPE : integer;
  attribute C_PROBE22_TYPE of U0 : label is 1;
  attribute C_PROBE22_WIDTH : integer;
  attribute C_PROBE22_WIDTH of U0 : label is 1;
  attribute C_PROBE230_MU_CNT : integer;
  attribute C_PROBE230_MU_CNT of U0 : label is 1;
  attribute C_PROBE230_TYPE : integer;
  attribute C_PROBE230_TYPE of U0 : label is 1;
  attribute C_PROBE230_WIDTH : integer;
  attribute C_PROBE230_WIDTH of U0 : label is 1;
  attribute C_PROBE231_MU_CNT : integer;
  attribute C_PROBE231_MU_CNT of U0 : label is 1;
  attribute C_PROBE231_TYPE : integer;
  attribute C_PROBE231_TYPE of U0 : label is 1;
  attribute C_PROBE231_WIDTH : integer;
  attribute C_PROBE231_WIDTH of U0 : label is 1;
  attribute C_PROBE232_MU_CNT : integer;
  attribute C_PROBE232_MU_CNT of U0 : label is 1;
  attribute C_PROBE232_TYPE : integer;
  attribute C_PROBE232_TYPE of U0 : label is 1;
  attribute C_PROBE232_WIDTH : integer;
  attribute C_PROBE232_WIDTH of U0 : label is 1;
  attribute C_PROBE233_MU_CNT : integer;
  attribute C_PROBE233_MU_CNT of U0 : label is 1;
  attribute C_PROBE233_TYPE : integer;
  attribute C_PROBE233_TYPE of U0 : label is 1;
  attribute C_PROBE233_WIDTH : integer;
  attribute C_PROBE233_WIDTH of U0 : label is 1;
  attribute C_PROBE234_MU_CNT : integer;
  attribute C_PROBE234_MU_CNT of U0 : label is 1;
  attribute C_PROBE234_TYPE : integer;
  attribute C_PROBE234_TYPE of U0 : label is 1;
  attribute C_PROBE234_WIDTH : integer;
  attribute C_PROBE234_WIDTH of U0 : label is 1;
  attribute C_PROBE235_MU_CNT : integer;
  attribute C_PROBE235_MU_CNT of U0 : label is 1;
  attribute C_PROBE235_TYPE : integer;
  attribute C_PROBE235_TYPE of U0 : label is 1;
  attribute C_PROBE235_WIDTH : integer;
  attribute C_PROBE235_WIDTH of U0 : label is 1;
  attribute C_PROBE236_MU_CNT : integer;
  attribute C_PROBE236_MU_CNT of U0 : label is 1;
  attribute C_PROBE236_TYPE : integer;
  attribute C_PROBE236_TYPE of U0 : label is 1;
  attribute C_PROBE236_WIDTH : integer;
  attribute C_PROBE236_WIDTH of U0 : label is 1;
  attribute C_PROBE237_MU_CNT : integer;
  attribute C_PROBE237_MU_CNT of U0 : label is 1;
  attribute C_PROBE237_TYPE : integer;
  attribute C_PROBE237_TYPE of U0 : label is 1;
  attribute C_PROBE237_WIDTH : integer;
  attribute C_PROBE237_WIDTH of U0 : label is 1;
  attribute C_PROBE238_MU_CNT : integer;
  attribute C_PROBE238_MU_CNT of U0 : label is 1;
  attribute C_PROBE238_TYPE : integer;
  attribute C_PROBE238_TYPE of U0 : label is 1;
  attribute C_PROBE238_WIDTH : integer;
  attribute C_PROBE238_WIDTH of U0 : label is 1;
  attribute C_PROBE239_MU_CNT : integer;
  attribute C_PROBE239_MU_CNT of U0 : label is 1;
  attribute C_PROBE239_TYPE : integer;
  attribute C_PROBE239_TYPE of U0 : label is 1;
  attribute C_PROBE239_WIDTH : integer;
  attribute C_PROBE239_WIDTH of U0 : label is 1;
  attribute C_PROBE23_MU_CNT : integer;
  attribute C_PROBE23_MU_CNT of U0 : label is 1;
  attribute C_PROBE23_TYPE : integer;
  attribute C_PROBE23_TYPE of U0 : label is 1;
  attribute C_PROBE23_WIDTH : integer;
  attribute C_PROBE23_WIDTH of U0 : label is 1;
  attribute C_PROBE240_MU_CNT : integer;
  attribute C_PROBE240_MU_CNT of U0 : label is 1;
  attribute C_PROBE240_TYPE : integer;
  attribute C_PROBE240_TYPE of U0 : label is 1;
  attribute C_PROBE240_WIDTH : integer;
  attribute C_PROBE240_WIDTH of U0 : label is 1;
  attribute C_PROBE241_MU_CNT : integer;
  attribute C_PROBE241_MU_CNT of U0 : label is 1;
  attribute C_PROBE241_TYPE : integer;
  attribute C_PROBE241_TYPE of U0 : label is 1;
  attribute C_PROBE241_WIDTH : integer;
  attribute C_PROBE241_WIDTH of U0 : label is 1;
  attribute C_PROBE242_MU_CNT : integer;
  attribute C_PROBE242_MU_CNT of U0 : label is 1;
  attribute C_PROBE242_TYPE : integer;
  attribute C_PROBE242_TYPE of U0 : label is 1;
  attribute C_PROBE242_WIDTH : integer;
  attribute C_PROBE242_WIDTH of U0 : label is 1;
  attribute C_PROBE243_MU_CNT : integer;
  attribute C_PROBE243_MU_CNT of U0 : label is 1;
  attribute C_PROBE243_TYPE : integer;
  attribute C_PROBE243_TYPE of U0 : label is 1;
  attribute C_PROBE243_WIDTH : integer;
  attribute C_PROBE243_WIDTH of U0 : label is 1;
  attribute C_PROBE244_MU_CNT : integer;
  attribute C_PROBE244_MU_CNT of U0 : label is 1;
  attribute C_PROBE244_TYPE : integer;
  attribute C_PROBE244_TYPE of U0 : label is 1;
  attribute C_PROBE244_WIDTH : integer;
  attribute C_PROBE244_WIDTH of U0 : label is 1;
  attribute C_PROBE245_MU_CNT : integer;
  attribute C_PROBE245_MU_CNT of U0 : label is 1;
  attribute C_PROBE245_TYPE : integer;
  attribute C_PROBE245_TYPE of U0 : label is 1;
  attribute C_PROBE245_WIDTH : integer;
  attribute C_PROBE245_WIDTH of U0 : label is 1;
  attribute C_PROBE246_MU_CNT : integer;
  attribute C_PROBE246_MU_CNT of U0 : label is 1;
  attribute C_PROBE246_TYPE : integer;
  attribute C_PROBE246_TYPE of U0 : label is 1;
  attribute C_PROBE246_WIDTH : integer;
  attribute C_PROBE246_WIDTH of U0 : label is 1;
  attribute C_PROBE247_MU_CNT : integer;
  attribute C_PROBE247_MU_CNT of U0 : label is 1;
  attribute C_PROBE247_TYPE : integer;
  attribute C_PROBE247_TYPE of U0 : label is 1;
  attribute C_PROBE247_WIDTH : integer;
  attribute C_PROBE247_WIDTH of U0 : label is 1;
  attribute C_PROBE248_MU_CNT : integer;
  attribute C_PROBE248_MU_CNT of U0 : label is 1;
  attribute C_PROBE248_TYPE : integer;
  attribute C_PROBE248_TYPE of U0 : label is 1;
  attribute C_PROBE248_WIDTH : integer;
  attribute C_PROBE248_WIDTH of U0 : label is 1;
  attribute C_PROBE249_MU_CNT : integer;
  attribute C_PROBE249_MU_CNT of U0 : label is 1;
  attribute C_PROBE249_TYPE : integer;
  attribute C_PROBE249_TYPE of U0 : label is 1;
  attribute C_PROBE249_WIDTH : integer;
  attribute C_PROBE249_WIDTH of U0 : label is 1;
  attribute C_PROBE24_MU_CNT : integer;
  attribute C_PROBE24_MU_CNT of U0 : label is 1;
  attribute C_PROBE24_TYPE : integer;
  attribute C_PROBE24_TYPE of U0 : label is 1;
  attribute C_PROBE24_WIDTH : integer;
  attribute C_PROBE24_WIDTH of U0 : label is 1;
  attribute C_PROBE250_MU_CNT : integer;
  attribute C_PROBE250_MU_CNT of U0 : label is 1;
  attribute C_PROBE250_TYPE : integer;
  attribute C_PROBE250_TYPE of U0 : label is 1;
  attribute C_PROBE250_WIDTH : integer;
  attribute C_PROBE250_WIDTH of U0 : label is 1;
  attribute C_PROBE251_MU_CNT : integer;
  attribute C_PROBE251_MU_CNT of U0 : label is 1;
  attribute C_PROBE251_TYPE : integer;
  attribute C_PROBE251_TYPE of U0 : label is 1;
  attribute C_PROBE251_WIDTH : integer;
  attribute C_PROBE251_WIDTH of U0 : label is 1;
  attribute C_PROBE252_MU_CNT : integer;
  attribute C_PROBE252_MU_CNT of U0 : label is 1;
  attribute C_PROBE252_TYPE : integer;
  attribute C_PROBE252_TYPE of U0 : label is 1;
  attribute C_PROBE252_WIDTH : integer;
  attribute C_PROBE252_WIDTH of U0 : label is 1;
  attribute C_PROBE253_MU_CNT : integer;
  attribute C_PROBE253_MU_CNT of U0 : label is 1;
  attribute C_PROBE253_TYPE : integer;
  attribute C_PROBE253_TYPE of U0 : label is 1;
  attribute C_PROBE253_WIDTH : integer;
  attribute C_PROBE253_WIDTH of U0 : label is 1;
  attribute C_PROBE254_MU_CNT : integer;
  attribute C_PROBE254_MU_CNT of U0 : label is 1;
  attribute C_PROBE254_TYPE : integer;
  attribute C_PROBE254_TYPE of U0 : label is 1;
  attribute C_PROBE254_WIDTH : integer;
  attribute C_PROBE254_WIDTH of U0 : label is 1;
  attribute C_PROBE255_MU_CNT : integer;
  attribute C_PROBE255_MU_CNT of U0 : label is 1;
  attribute C_PROBE255_TYPE : integer;
  attribute C_PROBE255_TYPE of U0 : label is 1;
  attribute C_PROBE255_WIDTH : integer;
  attribute C_PROBE255_WIDTH of U0 : label is 1;
  attribute C_PROBE256_MU_CNT : integer;
  attribute C_PROBE256_MU_CNT of U0 : label is 1;
  attribute C_PROBE256_TYPE : integer;
  attribute C_PROBE256_TYPE of U0 : label is 1;
  attribute C_PROBE256_WIDTH : integer;
  attribute C_PROBE256_WIDTH of U0 : label is 1;
  attribute C_PROBE257_MU_CNT : integer;
  attribute C_PROBE257_MU_CNT of U0 : label is 1;
  attribute C_PROBE257_TYPE : integer;
  attribute C_PROBE257_TYPE of U0 : label is 1;
  attribute C_PROBE257_WIDTH : integer;
  attribute C_PROBE257_WIDTH of U0 : label is 1;
  attribute C_PROBE258_MU_CNT : integer;
  attribute C_PROBE258_MU_CNT of U0 : label is 1;
  attribute C_PROBE258_TYPE : integer;
  attribute C_PROBE258_TYPE of U0 : label is 1;
  attribute C_PROBE258_WIDTH : integer;
  attribute C_PROBE258_WIDTH of U0 : label is 1;
  attribute C_PROBE259_MU_CNT : integer;
  attribute C_PROBE259_MU_CNT of U0 : label is 1;
  attribute C_PROBE259_TYPE : integer;
  attribute C_PROBE259_TYPE of U0 : label is 1;
  attribute C_PROBE259_WIDTH : integer;
  attribute C_PROBE259_WIDTH of U0 : label is 1;
  attribute C_PROBE25_MU_CNT : integer;
  attribute C_PROBE25_MU_CNT of U0 : label is 1;
  attribute C_PROBE25_TYPE : integer;
  attribute C_PROBE25_TYPE of U0 : label is 1;
  attribute C_PROBE25_WIDTH : integer;
  attribute C_PROBE25_WIDTH of U0 : label is 1;
  attribute C_PROBE260_MU_CNT : integer;
  attribute C_PROBE260_MU_CNT of U0 : label is 1;
  attribute C_PROBE260_TYPE : integer;
  attribute C_PROBE260_TYPE of U0 : label is 1;
  attribute C_PROBE260_WIDTH : integer;
  attribute C_PROBE260_WIDTH of U0 : label is 1;
  attribute C_PROBE261_MU_CNT : integer;
  attribute C_PROBE261_MU_CNT of U0 : label is 1;
  attribute C_PROBE261_TYPE : integer;
  attribute C_PROBE261_TYPE of U0 : label is 1;
  attribute C_PROBE261_WIDTH : integer;
  attribute C_PROBE261_WIDTH of U0 : label is 1;
  attribute C_PROBE262_MU_CNT : integer;
  attribute C_PROBE262_MU_CNT of U0 : label is 1;
  attribute C_PROBE262_TYPE : integer;
  attribute C_PROBE262_TYPE of U0 : label is 1;
  attribute C_PROBE262_WIDTH : integer;
  attribute C_PROBE262_WIDTH of U0 : label is 1;
  attribute C_PROBE263_MU_CNT : integer;
  attribute C_PROBE263_MU_CNT of U0 : label is 1;
  attribute C_PROBE263_TYPE : integer;
  attribute C_PROBE263_TYPE of U0 : label is 1;
  attribute C_PROBE263_WIDTH : integer;
  attribute C_PROBE263_WIDTH of U0 : label is 1;
  attribute C_PROBE264_MU_CNT : integer;
  attribute C_PROBE264_MU_CNT of U0 : label is 1;
  attribute C_PROBE264_TYPE : integer;
  attribute C_PROBE264_TYPE of U0 : label is 1;
  attribute C_PROBE264_WIDTH : integer;
  attribute C_PROBE264_WIDTH of U0 : label is 1;
  attribute C_PROBE265_MU_CNT : integer;
  attribute C_PROBE265_MU_CNT of U0 : label is 1;
  attribute C_PROBE265_TYPE : integer;
  attribute C_PROBE265_TYPE of U0 : label is 1;
  attribute C_PROBE265_WIDTH : integer;
  attribute C_PROBE265_WIDTH of U0 : label is 1;
  attribute C_PROBE266_MU_CNT : integer;
  attribute C_PROBE266_MU_CNT of U0 : label is 1;
  attribute C_PROBE266_TYPE : integer;
  attribute C_PROBE266_TYPE of U0 : label is 1;
  attribute C_PROBE266_WIDTH : integer;
  attribute C_PROBE266_WIDTH of U0 : label is 1;
  attribute C_PROBE267_MU_CNT : integer;
  attribute C_PROBE267_MU_CNT of U0 : label is 1;
  attribute C_PROBE267_TYPE : integer;
  attribute C_PROBE267_TYPE of U0 : label is 1;
  attribute C_PROBE267_WIDTH : integer;
  attribute C_PROBE267_WIDTH of U0 : label is 1;
  attribute C_PROBE268_MU_CNT : integer;
  attribute C_PROBE268_MU_CNT of U0 : label is 1;
  attribute C_PROBE268_TYPE : integer;
  attribute C_PROBE268_TYPE of U0 : label is 1;
  attribute C_PROBE268_WIDTH : integer;
  attribute C_PROBE268_WIDTH of U0 : label is 1;
  attribute C_PROBE269_MU_CNT : integer;
  attribute C_PROBE269_MU_CNT of U0 : label is 1;
  attribute C_PROBE269_TYPE : integer;
  attribute C_PROBE269_TYPE of U0 : label is 1;
  attribute C_PROBE269_WIDTH : integer;
  attribute C_PROBE269_WIDTH of U0 : label is 1;
  attribute C_PROBE26_MU_CNT : integer;
  attribute C_PROBE26_MU_CNT of U0 : label is 1;
  attribute C_PROBE26_TYPE : integer;
  attribute C_PROBE26_TYPE of U0 : label is 1;
  attribute C_PROBE26_WIDTH : integer;
  attribute C_PROBE26_WIDTH of U0 : label is 1;
  attribute C_PROBE270_MU_CNT : integer;
  attribute C_PROBE270_MU_CNT of U0 : label is 1;
  attribute C_PROBE270_TYPE : integer;
  attribute C_PROBE270_TYPE of U0 : label is 1;
  attribute C_PROBE270_WIDTH : integer;
  attribute C_PROBE270_WIDTH of U0 : label is 1;
  attribute C_PROBE271_MU_CNT : integer;
  attribute C_PROBE271_MU_CNT of U0 : label is 1;
  attribute C_PROBE271_TYPE : integer;
  attribute C_PROBE271_TYPE of U0 : label is 1;
  attribute C_PROBE271_WIDTH : integer;
  attribute C_PROBE271_WIDTH of U0 : label is 1;
  attribute C_PROBE272_MU_CNT : integer;
  attribute C_PROBE272_MU_CNT of U0 : label is 1;
  attribute C_PROBE272_TYPE : integer;
  attribute C_PROBE272_TYPE of U0 : label is 1;
  attribute C_PROBE272_WIDTH : integer;
  attribute C_PROBE272_WIDTH of U0 : label is 1;
  attribute C_PROBE273_MU_CNT : integer;
  attribute C_PROBE273_MU_CNT of U0 : label is 1;
  attribute C_PROBE273_TYPE : integer;
  attribute C_PROBE273_TYPE of U0 : label is 1;
  attribute C_PROBE273_WIDTH : integer;
  attribute C_PROBE273_WIDTH of U0 : label is 1;
  attribute C_PROBE274_MU_CNT : integer;
  attribute C_PROBE274_MU_CNT of U0 : label is 1;
  attribute C_PROBE274_TYPE : integer;
  attribute C_PROBE274_TYPE of U0 : label is 1;
  attribute C_PROBE274_WIDTH : integer;
  attribute C_PROBE274_WIDTH of U0 : label is 1;
  attribute C_PROBE275_MU_CNT : integer;
  attribute C_PROBE275_MU_CNT of U0 : label is 1;
  attribute C_PROBE275_TYPE : integer;
  attribute C_PROBE275_TYPE of U0 : label is 1;
  attribute C_PROBE275_WIDTH : integer;
  attribute C_PROBE275_WIDTH of U0 : label is 1;
  attribute C_PROBE276_MU_CNT : integer;
  attribute C_PROBE276_MU_CNT of U0 : label is 1;
  attribute C_PROBE276_TYPE : integer;
  attribute C_PROBE276_TYPE of U0 : label is 1;
  attribute C_PROBE276_WIDTH : integer;
  attribute C_PROBE276_WIDTH of U0 : label is 1;
  attribute C_PROBE277_MU_CNT : integer;
  attribute C_PROBE277_MU_CNT of U0 : label is 1;
  attribute C_PROBE277_TYPE : integer;
  attribute C_PROBE277_TYPE of U0 : label is 1;
  attribute C_PROBE277_WIDTH : integer;
  attribute C_PROBE277_WIDTH of U0 : label is 1;
  attribute C_PROBE278_MU_CNT : integer;
  attribute C_PROBE278_MU_CNT of U0 : label is 1;
  attribute C_PROBE278_TYPE : integer;
  attribute C_PROBE278_TYPE of U0 : label is 1;
  attribute C_PROBE278_WIDTH : integer;
  attribute C_PROBE278_WIDTH of U0 : label is 1;
  attribute C_PROBE279_MU_CNT : integer;
  attribute C_PROBE279_MU_CNT of U0 : label is 1;
  attribute C_PROBE279_TYPE : integer;
  attribute C_PROBE279_TYPE of U0 : label is 1;
  attribute C_PROBE279_WIDTH : integer;
  attribute C_PROBE279_WIDTH of U0 : label is 1;
  attribute C_PROBE27_MU_CNT : integer;
  attribute C_PROBE27_MU_CNT of U0 : label is 1;
  attribute C_PROBE27_TYPE : integer;
  attribute C_PROBE27_TYPE of U0 : label is 1;
  attribute C_PROBE27_WIDTH : integer;
  attribute C_PROBE27_WIDTH of U0 : label is 1;
  attribute C_PROBE280_MU_CNT : integer;
  attribute C_PROBE280_MU_CNT of U0 : label is 1;
  attribute C_PROBE280_TYPE : integer;
  attribute C_PROBE280_TYPE of U0 : label is 1;
  attribute C_PROBE280_WIDTH : integer;
  attribute C_PROBE280_WIDTH of U0 : label is 1;
  attribute C_PROBE281_MU_CNT : integer;
  attribute C_PROBE281_MU_CNT of U0 : label is 1;
  attribute C_PROBE281_TYPE : integer;
  attribute C_PROBE281_TYPE of U0 : label is 1;
  attribute C_PROBE281_WIDTH : integer;
  attribute C_PROBE281_WIDTH of U0 : label is 1;
  attribute C_PROBE282_MU_CNT : integer;
  attribute C_PROBE282_MU_CNT of U0 : label is 1;
  attribute C_PROBE282_TYPE : integer;
  attribute C_PROBE282_TYPE of U0 : label is 1;
  attribute C_PROBE282_WIDTH : integer;
  attribute C_PROBE282_WIDTH of U0 : label is 1;
  attribute C_PROBE283_MU_CNT : integer;
  attribute C_PROBE283_MU_CNT of U0 : label is 1;
  attribute C_PROBE283_TYPE : integer;
  attribute C_PROBE283_TYPE of U0 : label is 1;
  attribute C_PROBE283_WIDTH : integer;
  attribute C_PROBE283_WIDTH of U0 : label is 1;
  attribute C_PROBE284_MU_CNT : integer;
  attribute C_PROBE284_MU_CNT of U0 : label is 1;
  attribute C_PROBE284_TYPE : integer;
  attribute C_PROBE284_TYPE of U0 : label is 1;
  attribute C_PROBE284_WIDTH : integer;
  attribute C_PROBE284_WIDTH of U0 : label is 1;
  attribute C_PROBE285_MU_CNT : integer;
  attribute C_PROBE285_MU_CNT of U0 : label is 1;
  attribute C_PROBE285_TYPE : integer;
  attribute C_PROBE285_TYPE of U0 : label is 1;
  attribute C_PROBE285_WIDTH : integer;
  attribute C_PROBE285_WIDTH of U0 : label is 1;
  attribute C_PROBE286_MU_CNT : integer;
  attribute C_PROBE286_MU_CNT of U0 : label is 1;
  attribute C_PROBE286_TYPE : integer;
  attribute C_PROBE286_TYPE of U0 : label is 1;
  attribute C_PROBE286_WIDTH : integer;
  attribute C_PROBE286_WIDTH of U0 : label is 1;
  attribute C_PROBE287_MU_CNT : integer;
  attribute C_PROBE287_MU_CNT of U0 : label is 1;
  attribute C_PROBE287_TYPE : integer;
  attribute C_PROBE287_TYPE of U0 : label is 1;
  attribute C_PROBE287_WIDTH : integer;
  attribute C_PROBE287_WIDTH of U0 : label is 1;
  attribute C_PROBE288_MU_CNT : integer;
  attribute C_PROBE288_MU_CNT of U0 : label is 1;
  attribute C_PROBE288_TYPE : integer;
  attribute C_PROBE288_TYPE of U0 : label is 1;
  attribute C_PROBE288_WIDTH : integer;
  attribute C_PROBE288_WIDTH of U0 : label is 1;
  attribute C_PROBE289_MU_CNT : integer;
  attribute C_PROBE289_MU_CNT of U0 : label is 1;
  attribute C_PROBE289_TYPE : integer;
  attribute C_PROBE289_TYPE of U0 : label is 1;
  attribute C_PROBE289_WIDTH : integer;
  attribute C_PROBE289_WIDTH of U0 : label is 1;
  attribute C_PROBE28_MU_CNT : integer;
  attribute C_PROBE28_MU_CNT of U0 : label is 1;
  attribute C_PROBE28_TYPE : integer;
  attribute C_PROBE28_TYPE of U0 : label is 1;
  attribute C_PROBE28_WIDTH : integer;
  attribute C_PROBE28_WIDTH of U0 : label is 1;
  attribute C_PROBE290_MU_CNT : integer;
  attribute C_PROBE290_MU_CNT of U0 : label is 1;
  attribute C_PROBE290_TYPE : integer;
  attribute C_PROBE290_TYPE of U0 : label is 1;
  attribute C_PROBE290_WIDTH : integer;
  attribute C_PROBE290_WIDTH of U0 : label is 1;
  attribute C_PROBE291_MU_CNT : integer;
  attribute C_PROBE291_MU_CNT of U0 : label is 1;
  attribute C_PROBE291_TYPE : integer;
  attribute C_PROBE291_TYPE of U0 : label is 1;
  attribute C_PROBE291_WIDTH : integer;
  attribute C_PROBE291_WIDTH of U0 : label is 1;
  attribute C_PROBE292_MU_CNT : integer;
  attribute C_PROBE292_MU_CNT of U0 : label is 1;
  attribute C_PROBE292_TYPE : integer;
  attribute C_PROBE292_TYPE of U0 : label is 1;
  attribute C_PROBE292_WIDTH : integer;
  attribute C_PROBE292_WIDTH of U0 : label is 1;
  attribute C_PROBE293_MU_CNT : integer;
  attribute C_PROBE293_MU_CNT of U0 : label is 1;
  attribute C_PROBE293_TYPE : integer;
  attribute C_PROBE293_TYPE of U0 : label is 1;
  attribute C_PROBE293_WIDTH : integer;
  attribute C_PROBE293_WIDTH of U0 : label is 1;
  attribute C_PROBE294_MU_CNT : integer;
  attribute C_PROBE294_MU_CNT of U0 : label is 1;
  attribute C_PROBE294_TYPE : integer;
  attribute C_PROBE294_TYPE of U0 : label is 1;
  attribute C_PROBE294_WIDTH : integer;
  attribute C_PROBE294_WIDTH of U0 : label is 1;
  attribute C_PROBE295_MU_CNT : integer;
  attribute C_PROBE295_MU_CNT of U0 : label is 1;
  attribute C_PROBE295_TYPE : integer;
  attribute C_PROBE295_TYPE of U0 : label is 1;
  attribute C_PROBE295_WIDTH : integer;
  attribute C_PROBE295_WIDTH of U0 : label is 1;
  attribute C_PROBE296_MU_CNT : integer;
  attribute C_PROBE296_MU_CNT of U0 : label is 1;
  attribute C_PROBE296_TYPE : integer;
  attribute C_PROBE296_TYPE of U0 : label is 1;
  attribute C_PROBE296_WIDTH : integer;
  attribute C_PROBE296_WIDTH of U0 : label is 1;
  attribute C_PROBE297_MU_CNT : integer;
  attribute C_PROBE297_MU_CNT of U0 : label is 1;
  attribute C_PROBE297_TYPE : integer;
  attribute C_PROBE297_TYPE of U0 : label is 1;
  attribute C_PROBE297_WIDTH : integer;
  attribute C_PROBE297_WIDTH of U0 : label is 1;
  attribute C_PROBE298_MU_CNT : integer;
  attribute C_PROBE298_MU_CNT of U0 : label is 1;
  attribute C_PROBE298_TYPE : integer;
  attribute C_PROBE298_TYPE of U0 : label is 1;
  attribute C_PROBE298_WIDTH : integer;
  attribute C_PROBE298_WIDTH of U0 : label is 1;
  attribute C_PROBE299_MU_CNT : integer;
  attribute C_PROBE299_MU_CNT of U0 : label is 1;
  attribute C_PROBE299_TYPE : integer;
  attribute C_PROBE299_TYPE of U0 : label is 1;
  attribute C_PROBE299_WIDTH : integer;
  attribute C_PROBE299_WIDTH of U0 : label is 1;
  attribute C_PROBE29_MU_CNT : integer;
  attribute C_PROBE29_MU_CNT of U0 : label is 1;
  attribute C_PROBE29_TYPE : integer;
  attribute C_PROBE29_TYPE of U0 : label is 1;
  attribute C_PROBE29_WIDTH : integer;
  attribute C_PROBE29_WIDTH of U0 : label is 1;
  attribute C_PROBE2_MU_CNT : integer;
  attribute C_PROBE2_MU_CNT of U0 : label is 1;
  attribute C_PROBE2_TYPE : integer;
  attribute C_PROBE2_TYPE of U0 : label is 0;
  attribute C_PROBE2_WIDTH : integer;
  attribute C_PROBE2_WIDTH of U0 : label is 1;
  attribute C_PROBE300_MU_CNT : integer;
  attribute C_PROBE300_MU_CNT of U0 : label is 1;
  attribute C_PROBE300_TYPE : integer;
  attribute C_PROBE300_TYPE of U0 : label is 1;
  attribute C_PROBE300_WIDTH : integer;
  attribute C_PROBE300_WIDTH of U0 : label is 1;
  attribute C_PROBE301_MU_CNT : integer;
  attribute C_PROBE301_MU_CNT of U0 : label is 1;
  attribute C_PROBE301_TYPE : integer;
  attribute C_PROBE301_TYPE of U0 : label is 1;
  attribute C_PROBE301_WIDTH : integer;
  attribute C_PROBE301_WIDTH of U0 : label is 1;
  attribute C_PROBE302_MU_CNT : integer;
  attribute C_PROBE302_MU_CNT of U0 : label is 1;
  attribute C_PROBE302_TYPE : integer;
  attribute C_PROBE302_TYPE of U0 : label is 1;
  attribute C_PROBE302_WIDTH : integer;
  attribute C_PROBE302_WIDTH of U0 : label is 1;
  attribute C_PROBE303_MU_CNT : integer;
  attribute C_PROBE303_MU_CNT of U0 : label is 1;
  attribute C_PROBE303_TYPE : integer;
  attribute C_PROBE303_TYPE of U0 : label is 1;
  attribute C_PROBE303_WIDTH : integer;
  attribute C_PROBE303_WIDTH of U0 : label is 1;
  attribute C_PROBE304_MU_CNT : integer;
  attribute C_PROBE304_MU_CNT of U0 : label is 1;
  attribute C_PROBE304_TYPE : integer;
  attribute C_PROBE304_TYPE of U0 : label is 1;
  attribute C_PROBE304_WIDTH : integer;
  attribute C_PROBE304_WIDTH of U0 : label is 1;
  attribute C_PROBE305_MU_CNT : integer;
  attribute C_PROBE305_MU_CNT of U0 : label is 1;
  attribute C_PROBE305_TYPE : integer;
  attribute C_PROBE305_TYPE of U0 : label is 1;
  attribute C_PROBE305_WIDTH : integer;
  attribute C_PROBE305_WIDTH of U0 : label is 1;
  attribute C_PROBE306_MU_CNT : integer;
  attribute C_PROBE306_MU_CNT of U0 : label is 1;
  attribute C_PROBE306_TYPE : integer;
  attribute C_PROBE306_TYPE of U0 : label is 1;
  attribute C_PROBE306_WIDTH : integer;
  attribute C_PROBE306_WIDTH of U0 : label is 1;
  attribute C_PROBE307_MU_CNT : integer;
  attribute C_PROBE307_MU_CNT of U0 : label is 1;
  attribute C_PROBE307_TYPE : integer;
  attribute C_PROBE307_TYPE of U0 : label is 1;
  attribute C_PROBE307_WIDTH : integer;
  attribute C_PROBE307_WIDTH of U0 : label is 1;
  attribute C_PROBE308_MU_CNT : integer;
  attribute C_PROBE308_MU_CNT of U0 : label is 1;
  attribute C_PROBE308_TYPE : integer;
  attribute C_PROBE308_TYPE of U0 : label is 1;
  attribute C_PROBE308_WIDTH : integer;
  attribute C_PROBE308_WIDTH of U0 : label is 1;
  attribute C_PROBE309_MU_CNT : integer;
  attribute C_PROBE309_MU_CNT of U0 : label is 1;
  attribute C_PROBE309_TYPE : integer;
  attribute C_PROBE309_TYPE of U0 : label is 1;
  attribute C_PROBE309_WIDTH : integer;
  attribute C_PROBE309_WIDTH of U0 : label is 1;
  attribute C_PROBE30_MU_CNT : integer;
  attribute C_PROBE30_MU_CNT of U0 : label is 1;
  attribute C_PROBE30_TYPE : integer;
  attribute C_PROBE30_TYPE of U0 : label is 1;
  attribute C_PROBE30_WIDTH : integer;
  attribute C_PROBE30_WIDTH of U0 : label is 1;
  attribute C_PROBE310_MU_CNT : integer;
  attribute C_PROBE310_MU_CNT of U0 : label is 1;
  attribute C_PROBE310_TYPE : integer;
  attribute C_PROBE310_TYPE of U0 : label is 1;
  attribute C_PROBE310_WIDTH : integer;
  attribute C_PROBE310_WIDTH of U0 : label is 1;
  attribute C_PROBE311_MU_CNT : integer;
  attribute C_PROBE311_MU_CNT of U0 : label is 1;
  attribute C_PROBE311_TYPE : integer;
  attribute C_PROBE311_TYPE of U0 : label is 1;
  attribute C_PROBE311_WIDTH : integer;
  attribute C_PROBE311_WIDTH of U0 : label is 1;
  attribute C_PROBE312_MU_CNT : integer;
  attribute C_PROBE312_MU_CNT of U0 : label is 1;
  attribute C_PROBE312_TYPE : integer;
  attribute C_PROBE312_TYPE of U0 : label is 1;
  attribute C_PROBE312_WIDTH : integer;
  attribute C_PROBE312_WIDTH of U0 : label is 1;
  attribute C_PROBE313_MU_CNT : integer;
  attribute C_PROBE313_MU_CNT of U0 : label is 1;
  attribute C_PROBE313_TYPE : integer;
  attribute C_PROBE313_TYPE of U0 : label is 1;
  attribute C_PROBE313_WIDTH : integer;
  attribute C_PROBE313_WIDTH of U0 : label is 1;
  attribute C_PROBE314_MU_CNT : integer;
  attribute C_PROBE314_MU_CNT of U0 : label is 1;
  attribute C_PROBE314_TYPE : integer;
  attribute C_PROBE314_TYPE of U0 : label is 1;
  attribute C_PROBE314_WIDTH : integer;
  attribute C_PROBE314_WIDTH of U0 : label is 1;
  attribute C_PROBE315_MU_CNT : integer;
  attribute C_PROBE315_MU_CNT of U0 : label is 1;
  attribute C_PROBE315_TYPE : integer;
  attribute C_PROBE315_TYPE of U0 : label is 1;
  attribute C_PROBE315_WIDTH : integer;
  attribute C_PROBE315_WIDTH of U0 : label is 1;
  attribute C_PROBE316_MU_CNT : integer;
  attribute C_PROBE316_MU_CNT of U0 : label is 1;
  attribute C_PROBE316_TYPE : integer;
  attribute C_PROBE316_TYPE of U0 : label is 1;
  attribute C_PROBE316_WIDTH : integer;
  attribute C_PROBE316_WIDTH of U0 : label is 1;
  attribute C_PROBE317_MU_CNT : integer;
  attribute C_PROBE317_MU_CNT of U0 : label is 1;
  attribute C_PROBE317_TYPE : integer;
  attribute C_PROBE317_TYPE of U0 : label is 1;
  attribute C_PROBE317_WIDTH : integer;
  attribute C_PROBE317_WIDTH of U0 : label is 1;
  attribute C_PROBE318_MU_CNT : integer;
  attribute C_PROBE318_MU_CNT of U0 : label is 1;
  attribute C_PROBE318_TYPE : integer;
  attribute C_PROBE318_TYPE of U0 : label is 1;
  attribute C_PROBE318_WIDTH : integer;
  attribute C_PROBE318_WIDTH of U0 : label is 1;
  attribute C_PROBE319_MU_CNT : integer;
  attribute C_PROBE319_MU_CNT of U0 : label is 1;
  attribute C_PROBE319_TYPE : integer;
  attribute C_PROBE319_TYPE of U0 : label is 1;
  attribute C_PROBE319_WIDTH : integer;
  attribute C_PROBE319_WIDTH of U0 : label is 1;
  attribute C_PROBE31_MU_CNT : integer;
  attribute C_PROBE31_MU_CNT of U0 : label is 1;
  attribute C_PROBE31_TYPE : integer;
  attribute C_PROBE31_TYPE of U0 : label is 1;
  attribute C_PROBE31_WIDTH : integer;
  attribute C_PROBE31_WIDTH of U0 : label is 1;
  attribute C_PROBE320_MU_CNT : integer;
  attribute C_PROBE320_MU_CNT of U0 : label is 1;
  attribute C_PROBE320_TYPE : integer;
  attribute C_PROBE320_TYPE of U0 : label is 1;
  attribute C_PROBE320_WIDTH : integer;
  attribute C_PROBE320_WIDTH of U0 : label is 1;
  attribute C_PROBE321_MU_CNT : integer;
  attribute C_PROBE321_MU_CNT of U0 : label is 1;
  attribute C_PROBE321_TYPE : integer;
  attribute C_PROBE321_TYPE of U0 : label is 1;
  attribute C_PROBE321_WIDTH : integer;
  attribute C_PROBE321_WIDTH of U0 : label is 1;
  attribute C_PROBE322_MU_CNT : integer;
  attribute C_PROBE322_MU_CNT of U0 : label is 1;
  attribute C_PROBE322_TYPE : integer;
  attribute C_PROBE322_TYPE of U0 : label is 1;
  attribute C_PROBE322_WIDTH : integer;
  attribute C_PROBE322_WIDTH of U0 : label is 1;
  attribute C_PROBE323_MU_CNT : integer;
  attribute C_PROBE323_MU_CNT of U0 : label is 1;
  attribute C_PROBE323_TYPE : integer;
  attribute C_PROBE323_TYPE of U0 : label is 1;
  attribute C_PROBE323_WIDTH : integer;
  attribute C_PROBE323_WIDTH of U0 : label is 1;
  attribute C_PROBE324_MU_CNT : integer;
  attribute C_PROBE324_MU_CNT of U0 : label is 1;
  attribute C_PROBE324_TYPE : integer;
  attribute C_PROBE324_TYPE of U0 : label is 1;
  attribute C_PROBE324_WIDTH : integer;
  attribute C_PROBE324_WIDTH of U0 : label is 1;
  attribute C_PROBE325_MU_CNT : integer;
  attribute C_PROBE325_MU_CNT of U0 : label is 1;
  attribute C_PROBE325_TYPE : integer;
  attribute C_PROBE325_TYPE of U0 : label is 1;
  attribute C_PROBE325_WIDTH : integer;
  attribute C_PROBE325_WIDTH of U0 : label is 1;
  attribute C_PROBE326_MU_CNT : integer;
  attribute C_PROBE326_MU_CNT of U0 : label is 1;
  attribute C_PROBE326_TYPE : integer;
  attribute C_PROBE326_TYPE of U0 : label is 1;
  attribute C_PROBE326_WIDTH : integer;
  attribute C_PROBE326_WIDTH of U0 : label is 1;
  attribute C_PROBE327_MU_CNT : integer;
  attribute C_PROBE327_MU_CNT of U0 : label is 1;
  attribute C_PROBE327_TYPE : integer;
  attribute C_PROBE327_TYPE of U0 : label is 1;
  attribute C_PROBE327_WIDTH : integer;
  attribute C_PROBE327_WIDTH of U0 : label is 1;
  attribute C_PROBE328_MU_CNT : integer;
  attribute C_PROBE328_MU_CNT of U0 : label is 1;
  attribute C_PROBE328_TYPE : integer;
  attribute C_PROBE328_TYPE of U0 : label is 1;
  attribute C_PROBE328_WIDTH : integer;
  attribute C_PROBE328_WIDTH of U0 : label is 1;
  attribute C_PROBE329_MU_CNT : integer;
  attribute C_PROBE329_MU_CNT of U0 : label is 1;
  attribute C_PROBE329_TYPE : integer;
  attribute C_PROBE329_TYPE of U0 : label is 1;
  attribute C_PROBE329_WIDTH : integer;
  attribute C_PROBE329_WIDTH of U0 : label is 1;
  attribute C_PROBE32_MU_CNT : integer;
  attribute C_PROBE32_MU_CNT of U0 : label is 1;
  attribute C_PROBE32_TYPE : integer;
  attribute C_PROBE32_TYPE of U0 : label is 1;
  attribute C_PROBE32_WIDTH : integer;
  attribute C_PROBE32_WIDTH of U0 : label is 1;
  attribute C_PROBE330_MU_CNT : integer;
  attribute C_PROBE330_MU_CNT of U0 : label is 1;
  attribute C_PROBE330_TYPE : integer;
  attribute C_PROBE330_TYPE of U0 : label is 1;
  attribute C_PROBE330_WIDTH : integer;
  attribute C_PROBE330_WIDTH of U0 : label is 1;
  attribute C_PROBE331_MU_CNT : integer;
  attribute C_PROBE331_MU_CNT of U0 : label is 1;
  attribute C_PROBE331_TYPE : integer;
  attribute C_PROBE331_TYPE of U0 : label is 1;
  attribute C_PROBE331_WIDTH : integer;
  attribute C_PROBE331_WIDTH of U0 : label is 1;
  attribute C_PROBE332_MU_CNT : integer;
  attribute C_PROBE332_MU_CNT of U0 : label is 1;
  attribute C_PROBE332_TYPE : integer;
  attribute C_PROBE332_TYPE of U0 : label is 1;
  attribute C_PROBE332_WIDTH : integer;
  attribute C_PROBE332_WIDTH of U0 : label is 1;
  attribute C_PROBE333_MU_CNT : integer;
  attribute C_PROBE333_MU_CNT of U0 : label is 1;
  attribute C_PROBE333_TYPE : integer;
  attribute C_PROBE333_TYPE of U0 : label is 1;
  attribute C_PROBE333_WIDTH : integer;
  attribute C_PROBE333_WIDTH of U0 : label is 1;
  attribute C_PROBE334_MU_CNT : integer;
  attribute C_PROBE334_MU_CNT of U0 : label is 1;
  attribute C_PROBE334_TYPE : integer;
  attribute C_PROBE334_TYPE of U0 : label is 1;
  attribute C_PROBE334_WIDTH : integer;
  attribute C_PROBE334_WIDTH of U0 : label is 1;
  attribute C_PROBE335_MU_CNT : integer;
  attribute C_PROBE335_MU_CNT of U0 : label is 1;
  attribute C_PROBE335_TYPE : integer;
  attribute C_PROBE335_TYPE of U0 : label is 1;
  attribute C_PROBE335_WIDTH : integer;
  attribute C_PROBE335_WIDTH of U0 : label is 1;
  attribute C_PROBE336_MU_CNT : integer;
  attribute C_PROBE336_MU_CNT of U0 : label is 1;
  attribute C_PROBE336_TYPE : integer;
  attribute C_PROBE336_TYPE of U0 : label is 1;
  attribute C_PROBE336_WIDTH : integer;
  attribute C_PROBE336_WIDTH of U0 : label is 1;
  attribute C_PROBE337_MU_CNT : integer;
  attribute C_PROBE337_MU_CNT of U0 : label is 1;
  attribute C_PROBE337_TYPE : integer;
  attribute C_PROBE337_TYPE of U0 : label is 1;
  attribute C_PROBE337_WIDTH : integer;
  attribute C_PROBE337_WIDTH of U0 : label is 1;
  attribute C_PROBE338_MU_CNT : integer;
  attribute C_PROBE338_MU_CNT of U0 : label is 1;
  attribute C_PROBE338_TYPE : integer;
  attribute C_PROBE338_TYPE of U0 : label is 1;
  attribute C_PROBE338_WIDTH : integer;
  attribute C_PROBE338_WIDTH of U0 : label is 1;
  attribute C_PROBE339_MU_CNT : integer;
  attribute C_PROBE339_MU_CNT of U0 : label is 1;
  attribute C_PROBE339_TYPE : integer;
  attribute C_PROBE339_TYPE of U0 : label is 1;
  attribute C_PROBE339_WIDTH : integer;
  attribute C_PROBE339_WIDTH of U0 : label is 1;
  attribute C_PROBE33_MU_CNT : integer;
  attribute C_PROBE33_MU_CNT of U0 : label is 1;
  attribute C_PROBE33_TYPE : integer;
  attribute C_PROBE33_TYPE of U0 : label is 1;
  attribute C_PROBE33_WIDTH : integer;
  attribute C_PROBE33_WIDTH of U0 : label is 1;
  attribute C_PROBE340_MU_CNT : integer;
  attribute C_PROBE340_MU_CNT of U0 : label is 1;
  attribute C_PROBE340_TYPE : integer;
  attribute C_PROBE340_TYPE of U0 : label is 1;
  attribute C_PROBE340_WIDTH : integer;
  attribute C_PROBE340_WIDTH of U0 : label is 1;
  attribute C_PROBE341_MU_CNT : integer;
  attribute C_PROBE341_MU_CNT of U0 : label is 1;
  attribute C_PROBE341_TYPE : integer;
  attribute C_PROBE341_TYPE of U0 : label is 1;
  attribute C_PROBE341_WIDTH : integer;
  attribute C_PROBE341_WIDTH of U0 : label is 1;
  attribute C_PROBE342_MU_CNT : integer;
  attribute C_PROBE342_MU_CNT of U0 : label is 1;
  attribute C_PROBE342_TYPE : integer;
  attribute C_PROBE342_TYPE of U0 : label is 1;
  attribute C_PROBE342_WIDTH : integer;
  attribute C_PROBE342_WIDTH of U0 : label is 1;
  attribute C_PROBE343_MU_CNT : integer;
  attribute C_PROBE343_MU_CNT of U0 : label is 1;
  attribute C_PROBE343_TYPE : integer;
  attribute C_PROBE343_TYPE of U0 : label is 1;
  attribute C_PROBE343_WIDTH : integer;
  attribute C_PROBE343_WIDTH of U0 : label is 1;
  attribute C_PROBE344_MU_CNT : integer;
  attribute C_PROBE344_MU_CNT of U0 : label is 1;
  attribute C_PROBE344_TYPE : integer;
  attribute C_PROBE344_TYPE of U0 : label is 1;
  attribute C_PROBE344_WIDTH : integer;
  attribute C_PROBE344_WIDTH of U0 : label is 1;
  attribute C_PROBE345_MU_CNT : integer;
  attribute C_PROBE345_MU_CNT of U0 : label is 1;
  attribute C_PROBE345_TYPE : integer;
  attribute C_PROBE345_TYPE of U0 : label is 1;
  attribute C_PROBE345_WIDTH : integer;
  attribute C_PROBE345_WIDTH of U0 : label is 1;
  attribute C_PROBE346_MU_CNT : integer;
  attribute C_PROBE346_MU_CNT of U0 : label is 1;
  attribute C_PROBE346_TYPE : integer;
  attribute C_PROBE346_TYPE of U0 : label is 1;
  attribute C_PROBE346_WIDTH : integer;
  attribute C_PROBE346_WIDTH of U0 : label is 1;
  attribute C_PROBE347_MU_CNT : integer;
  attribute C_PROBE347_MU_CNT of U0 : label is 1;
  attribute C_PROBE347_TYPE : integer;
  attribute C_PROBE347_TYPE of U0 : label is 1;
  attribute C_PROBE347_WIDTH : integer;
  attribute C_PROBE347_WIDTH of U0 : label is 1;
  attribute C_PROBE348_MU_CNT : integer;
  attribute C_PROBE348_MU_CNT of U0 : label is 1;
  attribute C_PROBE348_TYPE : integer;
  attribute C_PROBE348_TYPE of U0 : label is 1;
  attribute C_PROBE348_WIDTH : integer;
  attribute C_PROBE348_WIDTH of U0 : label is 1;
  attribute C_PROBE349_MU_CNT : integer;
  attribute C_PROBE349_MU_CNT of U0 : label is 1;
  attribute C_PROBE349_TYPE : integer;
  attribute C_PROBE349_TYPE of U0 : label is 1;
  attribute C_PROBE349_WIDTH : integer;
  attribute C_PROBE349_WIDTH of U0 : label is 1;
  attribute C_PROBE34_MU_CNT : integer;
  attribute C_PROBE34_MU_CNT of U0 : label is 1;
  attribute C_PROBE34_TYPE : integer;
  attribute C_PROBE34_TYPE of U0 : label is 1;
  attribute C_PROBE34_WIDTH : integer;
  attribute C_PROBE34_WIDTH of U0 : label is 1;
  attribute C_PROBE350_MU_CNT : integer;
  attribute C_PROBE350_MU_CNT of U0 : label is 1;
  attribute C_PROBE350_TYPE : integer;
  attribute C_PROBE350_TYPE of U0 : label is 1;
  attribute C_PROBE350_WIDTH : integer;
  attribute C_PROBE350_WIDTH of U0 : label is 1;
  attribute C_PROBE351_MU_CNT : integer;
  attribute C_PROBE351_MU_CNT of U0 : label is 1;
  attribute C_PROBE351_TYPE : integer;
  attribute C_PROBE351_TYPE of U0 : label is 1;
  attribute C_PROBE351_WIDTH : integer;
  attribute C_PROBE351_WIDTH of U0 : label is 1;
  attribute C_PROBE352_MU_CNT : integer;
  attribute C_PROBE352_MU_CNT of U0 : label is 1;
  attribute C_PROBE352_TYPE : integer;
  attribute C_PROBE352_TYPE of U0 : label is 1;
  attribute C_PROBE352_WIDTH : integer;
  attribute C_PROBE352_WIDTH of U0 : label is 1;
  attribute C_PROBE353_MU_CNT : integer;
  attribute C_PROBE353_MU_CNT of U0 : label is 1;
  attribute C_PROBE353_TYPE : integer;
  attribute C_PROBE353_TYPE of U0 : label is 1;
  attribute C_PROBE353_WIDTH : integer;
  attribute C_PROBE353_WIDTH of U0 : label is 1;
  attribute C_PROBE354_MU_CNT : integer;
  attribute C_PROBE354_MU_CNT of U0 : label is 1;
  attribute C_PROBE354_TYPE : integer;
  attribute C_PROBE354_TYPE of U0 : label is 1;
  attribute C_PROBE354_WIDTH : integer;
  attribute C_PROBE354_WIDTH of U0 : label is 1;
  attribute C_PROBE355_MU_CNT : integer;
  attribute C_PROBE355_MU_CNT of U0 : label is 1;
  attribute C_PROBE355_TYPE : integer;
  attribute C_PROBE355_TYPE of U0 : label is 1;
  attribute C_PROBE355_WIDTH : integer;
  attribute C_PROBE355_WIDTH of U0 : label is 1;
  attribute C_PROBE356_MU_CNT : integer;
  attribute C_PROBE356_MU_CNT of U0 : label is 1;
  attribute C_PROBE356_TYPE : integer;
  attribute C_PROBE356_TYPE of U0 : label is 1;
  attribute C_PROBE356_WIDTH : integer;
  attribute C_PROBE356_WIDTH of U0 : label is 1;
  attribute C_PROBE357_MU_CNT : integer;
  attribute C_PROBE357_MU_CNT of U0 : label is 1;
  attribute C_PROBE357_TYPE : integer;
  attribute C_PROBE357_TYPE of U0 : label is 1;
  attribute C_PROBE357_WIDTH : integer;
  attribute C_PROBE357_WIDTH of U0 : label is 1;
  attribute C_PROBE358_MU_CNT : integer;
  attribute C_PROBE358_MU_CNT of U0 : label is 1;
  attribute C_PROBE358_TYPE : integer;
  attribute C_PROBE358_TYPE of U0 : label is 1;
  attribute C_PROBE358_WIDTH : integer;
  attribute C_PROBE358_WIDTH of U0 : label is 1;
  attribute C_PROBE359_MU_CNT : integer;
  attribute C_PROBE359_MU_CNT of U0 : label is 1;
  attribute C_PROBE359_TYPE : integer;
  attribute C_PROBE359_TYPE of U0 : label is 1;
  attribute C_PROBE359_WIDTH : integer;
  attribute C_PROBE359_WIDTH of U0 : label is 1;
  attribute C_PROBE35_MU_CNT : integer;
  attribute C_PROBE35_MU_CNT of U0 : label is 1;
  attribute C_PROBE35_TYPE : integer;
  attribute C_PROBE35_TYPE of U0 : label is 1;
  attribute C_PROBE35_WIDTH : integer;
  attribute C_PROBE35_WIDTH of U0 : label is 1;
  attribute C_PROBE360_MU_CNT : integer;
  attribute C_PROBE360_MU_CNT of U0 : label is 1;
  attribute C_PROBE360_TYPE : integer;
  attribute C_PROBE360_TYPE of U0 : label is 1;
  attribute C_PROBE360_WIDTH : integer;
  attribute C_PROBE360_WIDTH of U0 : label is 1;
  attribute C_PROBE361_MU_CNT : integer;
  attribute C_PROBE361_MU_CNT of U0 : label is 1;
  attribute C_PROBE361_TYPE : integer;
  attribute C_PROBE361_TYPE of U0 : label is 1;
  attribute C_PROBE361_WIDTH : integer;
  attribute C_PROBE361_WIDTH of U0 : label is 1;
  attribute C_PROBE362_MU_CNT : integer;
  attribute C_PROBE362_MU_CNT of U0 : label is 1;
  attribute C_PROBE362_TYPE : integer;
  attribute C_PROBE362_TYPE of U0 : label is 1;
  attribute C_PROBE362_WIDTH : integer;
  attribute C_PROBE362_WIDTH of U0 : label is 1;
  attribute C_PROBE363_MU_CNT : integer;
  attribute C_PROBE363_MU_CNT of U0 : label is 1;
  attribute C_PROBE363_TYPE : integer;
  attribute C_PROBE363_TYPE of U0 : label is 1;
  attribute C_PROBE363_WIDTH : integer;
  attribute C_PROBE363_WIDTH of U0 : label is 1;
  attribute C_PROBE364_MU_CNT : integer;
  attribute C_PROBE364_MU_CNT of U0 : label is 1;
  attribute C_PROBE364_TYPE : integer;
  attribute C_PROBE364_TYPE of U0 : label is 1;
  attribute C_PROBE364_WIDTH : integer;
  attribute C_PROBE364_WIDTH of U0 : label is 1;
  attribute C_PROBE365_MU_CNT : integer;
  attribute C_PROBE365_MU_CNT of U0 : label is 1;
  attribute C_PROBE365_TYPE : integer;
  attribute C_PROBE365_TYPE of U0 : label is 1;
  attribute C_PROBE365_WIDTH : integer;
  attribute C_PROBE365_WIDTH of U0 : label is 1;
  attribute C_PROBE366_MU_CNT : integer;
  attribute C_PROBE366_MU_CNT of U0 : label is 1;
  attribute C_PROBE366_TYPE : integer;
  attribute C_PROBE366_TYPE of U0 : label is 1;
  attribute C_PROBE366_WIDTH : integer;
  attribute C_PROBE366_WIDTH of U0 : label is 1;
  attribute C_PROBE367_MU_CNT : integer;
  attribute C_PROBE367_MU_CNT of U0 : label is 1;
  attribute C_PROBE367_TYPE : integer;
  attribute C_PROBE367_TYPE of U0 : label is 1;
  attribute C_PROBE367_WIDTH : integer;
  attribute C_PROBE367_WIDTH of U0 : label is 1;
  attribute C_PROBE368_MU_CNT : integer;
  attribute C_PROBE368_MU_CNT of U0 : label is 1;
  attribute C_PROBE368_TYPE : integer;
  attribute C_PROBE368_TYPE of U0 : label is 1;
  attribute C_PROBE368_WIDTH : integer;
  attribute C_PROBE368_WIDTH of U0 : label is 1;
  attribute C_PROBE369_MU_CNT : integer;
  attribute C_PROBE369_MU_CNT of U0 : label is 1;
  attribute C_PROBE369_TYPE : integer;
  attribute C_PROBE369_TYPE of U0 : label is 1;
  attribute C_PROBE369_WIDTH : integer;
  attribute C_PROBE369_WIDTH of U0 : label is 1;
  attribute C_PROBE36_MU_CNT : integer;
  attribute C_PROBE36_MU_CNT of U0 : label is 1;
  attribute C_PROBE36_TYPE : integer;
  attribute C_PROBE36_TYPE of U0 : label is 1;
  attribute C_PROBE36_WIDTH : integer;
  attribute C_PROBE36_WIDTH of U0 : label is 1;
  attribute C_PROBE370_MU_CNT : integer;
  attribute C_PROBE370_MU_CNT of U0 : label is 1;
  attribute C_PROBE370_TYPE : integer;
  attribute C_PROBE370_TYPE of U0 : label is 1;
  attribute C_PROBE370_WIDTH : integer;
  attribute C_PROBE370_WIDTH of U0 : label is 1;
  attribute C_PROBE371_MU_CNT : integer;
  attribute C_PROBE371_MU_CNT of U0 : label is 1;
  attribute C_PROBE371_TYPE : integer;
  attribute C_PROBE371_TYPE of U0 : label is 1;
  attribute C_PROBE371_WIDTH : integer;
  attribute C_PROBE371_WIDTH of U0 : label is 1;
  attribute C_PROBE372_MU_CNT : integer;
  attribute C_PROBE372_MU_CNT of U0 : label is 1;
  attribute C_PROBE372_TYPE : integer;
  attribute C_PROBE372_TYPE of U0 : label is 1;
  attribute C_PROBE372_WIDTH : integer;
  attribute C_PROBE372_WIDTH of U0 : label is 1;
  attribute C_PROBE373_MU_CNT : integer;
  attribute C_PROBE373_MU_CNT of U0 : label is 1;
  attribute C_PROBE373_TYPE : integer;
  attribute C_PROBE373_TYPE of U0 : label is 1;
  attribute C_PROBE373_WIDTH : integer;
  attribute C_PROBE373_WIDTH of U0 : label is 1;
  attribute C_PROBE374_MU_CNT : integer;
  attribute C_PROBE374_MU_CNT of U0 : label is 1;
  attribute C_PROBE374_TYPE : integer;
  attribute C_PROBE374_TYPE of U0 : label is 1;
  attribute C_PROBE374_WIDTH : integer;
  attribute C_PROBE374_WIDTH of U0 : label is 1;
  attribute C_PROBE375_MU_CNT : integer;
  attribute C_PROBE375_MU_CNT of U0 : label is 1;
  attribute C_PROBE375_TYPE : integer;
  attribute C_PROBE375_TYPE of U0 : label is 1;
  attribute C_PROBE375_WIDTH : integer;
  attribute C_PROBE375_WIDTH of U0 : label is 1;
  attribute C_PROBE376_MU_CNT : integer;
  attribute C_PROBE376_MU_CNT of U0 : label is 1;
  attribute C_PROBE376_TYPE : integer;
  attribute C_PROBE376_TYPE of U0 : label is 1;
  attribute C_PROBE376_WIDTH : integer;
  attribute C_PROBE376_WIDTH of U0 : label is 1;
  attribute C_PROBE377_MU_CNT : integer;
  attribute C_PROBE377_MU_CNT of U0 : label is 1;
  attribute C_PROBE377_TYPE : integer;
  attribute C_PROBE377_TYPE of U0 : label is 1;
  attribute C_PROBE377_WIDTH : integer;
  attribute C_PROBE377_WIDTH of U0 : label is 1;
  attribute C_PROBE378_MU_CNT : integer;
  attribute C_PROBE378_MU_CNT of U0 : label is 1;
  attribute C_PROBE378_TYPE : integer;
  attribute C_PROBE378_TYPE of U0 : label is 1;
  attribute C_PROBE378_WIDTH : integer;
  attribute C_PROBE378_WIDTH of U0 : label is 1;
  attribute C_PROBE379_MU_CNT : integer;
  attribute C_PROBE379_MU_CNT of U0 : label is 1;
  attribute C_PROBE379_TYPE : integer;
  attribute C_PROBE379_TYPE of U0 : label is 1;
  attribute C_PROBE379_WIDTH : integer;
  attribute C_PROBE379_WIDTH of U0 : label is 1;
  attribute C_PROBE37_MU_CNT : integer;
  attribute C_PROBE37_MU_CNT of U0 : label is 1;
  attribute C_PROBE37_TYPE : integer;
  attribute C_PROBE37_TYPE of U0 : label is 1;
  attribute C_PROBE37_WIDTH : integer;
  attribute C_PROBE37_WIDTH of U0 : label is 1;
  attribute C_PROBE380_MU_CNT : integer;
  attribute C_PROBE380_MU_CNT of U0 : label is 1;
  attribute C_PROBE380_TYPE : integer;
  attribute C_PROBE380_TYPE of U0 : label is 1;
  attribute C_PROBE380_WIDTH : integer;
  attribute C_PROBE380_WIDTH of U0 : label is 1;
  attribute C_PROBE381_MU_CNT : integer;
  attribute C_PROBE381_MU_CNT of U0 : label is 1;
  attribute C_PROBE381_TYPE : integer;
  attribute C_PROBE381_TYPE of U0 : label is 1;
  attribute C_PROBE381_WIDTH : integer;
  attribute C_PROBE381_WIDTH of U0 : label is 1;
  attribute C_PROBE382_MU_CNT : integer;
  attribute C_PROBE382_MU_CNT of U0 : label is 1;
  attribute C_PROBE382_TYPE : integer;
  attribute C_PROBE382_TYPE of U0 : label is 1;
  attribute C_PROBE382_WIDTH : integer;
  attribute C_PROBE382_WIDTH of U0 : label is 1;
  attribute C_PROBE383_MU_CNT : integer;
  attribute C_PROBE383_MU_CNT of U0 : label is 1;
  attribute C_PROBE383_TYPE : integer;
  attribute C_PROBE383_TYPE of U0 : label is 1;
  attribute C_PROBE383_WIDTH : integer;
  attribute C_PROBE383_WIDTH of U0 : label is 1;
  attribute C_PROBE384_MU_CNT : integer;
  attribute C_PROBE384_MU_CNT of U0 : label is 1;
  attribute C_PROBE384_TYPE : integer;
  attribute C_PROBE384_TYPE of U0 : label is 1;
  attribute C_PROBE384_WIDTH : integer;
  attribute C_PROBE384_WIDTH of U0 : label is 1;
  attribute C_PROBE385_MU_CNT : integer;
  attribute C_PROBE385_MU_CNT of U0 : label is 1;
  attribute C_PROBE385_TYPE : integer;
  attribute C_PROBE385_TYPE of U0 : label is 1;
  attribute C_PROBE385_WIDTH : integer;
  attribute C_PROBE385_WIDTH of U0 : label is 1;
  attribute C_PROBE386_MU_CNT : integer;
  attribute C_PROBE386_MU_CNT of U0 : label is 1;
  attribute C_PROBE386_TYPE : integer;
  attribute C_PROBE386_TYPE of U0 : label is 1;
  attribute C_PROBE386_WIDTH : integer;
  attribute C_PROBE386_WIDTH of U0 : label is 1;
  attribute C_PROBE387_MU_CNT : integer;
  attribute C_PROBE387_MU_CNT of U0 : label is 1;
  attribute C_PROBE387_TYPE : integer;
  attribute C_PROBE387_TYPE of U0 : label is 1;
  attribute C_PROBE387_WIDTH : integer;
  attribute C_PROBE387_WIDTH of U0 : label is 1;
  attribute C_PROBE388_MU_CNT : integer;
  attribute C_PROBE388_MU_CNT of U0 : label is 1;
  attribute C_PROBE388_TYPE : integer;
  attribute C_PROBE388_TYPE of U0 : label is 1;
  attribute C_PROBE388_WIDTH : integer;
  attribute C_PROBE388_WIDTH of U0 : label is 1;
  attribute C_PROBE389_MU_CNT : integer;
  attribute C_PROBE389_MU_CNT of U0 : label is 1;
  attribute C_PROBE389_TYPE : integer;
  attribute C_PROBE389_TYPE of U0 : label is 1;
  attribute C_PROBE389_WIDTH : integer;
  attribute C_PROBE389_WIDTH of U0 : label is 1;
  attribute C_PROBE38_MU_CNT : integer;
  attribute C_PROBE38_MU_CNT of U0 : label is 1;
  attribute C_PROBE38_TYPE : integer;
  attribute C_PROBE38_TYPE of U0 : label is 1;
  attribute C_PROBE38_WIDTH : integer;
  attribute C_PROBE38_WIDTH of U0 : label is 1;
  attribute C_PROBE390_MU_CNT : integer;
  attribute C_PROBE390_MU_CNT of U0 : label is 1;
  attribute C_PROBE390_TYPE : integer;
  attribute C_PROBE390_TYPE of U0 : label is 1;
  attribute C_PROBE390_WIDTH : integer;
  attribute C_PROBE390_WIDTH of U0 : label is 1;
  attribute C_PROBE391_MU_CNT : integer;
  attribute C_PROBE391_MU_CNT of U0 : label is 1;
  attribute C_PROBE391_TYPE : integer;
  attribute C_PROBE391_TYPE of U0 : label is 1;
  attribute C_PROBE391_WIDTH : integer;
  attribute C_PROBE391_WIDTH of U0 : label is 1;
  attribute C_PROBE392_MU_CNT : integer;
  attribute C_PROBE392_MU_CNT of U0 : label is 1;
  attribute C_PROBE392_TYPE : integer;
  attribute C_PROBE392_TYPE of U0 : label is 1;
  attribute C_PROBE392_WIDTH : integer;
  attribute C_PROBE392_WIDTH of U0 : label is 1;
  attribute C_PROBE393_MU_CNT : integer;
  attribute C_PROBE393_MU_CNT of U0 : label is 1;
  attribute C_PROBE393_TYPE : integer;
  attribute C_PROBE393_TYPE of U0 : label is 1;
  attribute C_PROBE393_WIDTH : integer;
  attribute C_PROBE393_WIDTH of U0 : label is 1;
  attribute C_PROBE394_MU_CNT : integer;
  attribute C_PROBE394_MU_CNT of U0 : label is 1;
  attribute C_PROBE394_TYPE : integer;
  attribute C_PROBE394_TYPE of U0 : label is 1;
  attribute C_PROBE394_WIDTH : integer;
  attribute C_PROBE394_WIDTH of U0 : label is 1;
  attribute C_PROBE395_MU_CNT : integer;
  attribute C_PROBE395_MU_CNT of U0 : label is 1;
  attribute C_PROBE395_TYPE : integer;
  attribute C_PROBE395_TYPE of U0 : label is 1;
  attribute C_PROBE395_WIDTH : integer;
  attribute C_PROBE395_WIDTH of U0 : label is 1;
  attribute C_PROBE396_MU_CNT : integer;
  attribute C_PROBE396_MU_CNT of U0 : label is 1;
  attribute C_PROBE396_TYPE : integer;
  attribute C_PROBE396_TYPE of U0 : label is 1;
  attribute C_PROBE396_WIDTH : integer;
  attribute C_PROBE396_WIDTH of U0 : label is 1;
  attribute C_PROBE397_MU_CNT : integer;
  attribute C_PROBE397_MU_CNT of U0 : label is 1;
  attribute C_PROBE397_TYPE : integer;
  attribute C_PROBE397_TYPE of U0 : label is 1;
  attribute C_PROBE397_WIDTH : integer;
  attribute C_PROBE397_WIDTH of U0 : label is 1;
  attribute C_PROBE398_MU_CNT : integer;
  attribute C_PROBE398_MU_CNT of U0 : label is 1;
  attribute C_PROBE398_TYPE : integer;
  attribute C_PROBE398_TYPE of U0 : label is 1;
  attribute C_PROBE398_WIDTH : integer;
  attribute C_PROBE398_WIDTH of U0 : label is 1;
  attribute C_PROBE399_MU_CNT : integer;
  attribute C_PROBE399_MU_CNT of U0 : label is 1;
  attribute C_PROBE399_TYPE : integer;
  attribute C_PROBE399_TYPE of U0 : label is 1;
  attribute C_PROBE399_WIDTH : integer;
  attribute C_PROBE399_WIDTH of U0 : label is 1;
  attribute C_PROBE39_MU_CNT : integer;
  attribute C_PROBE39_MU_CNT of U0 : label is 1;
  attribute C_PROBE39_TYPE : integer;
  attribute C_PROBE39_TYPE of U0 : label is 1;
  attribute C_PROBE39_WIDTH : integer;
  attribute C_PROBE39_WIDTH of U0 : label is 1;
  attribute C_PROBE3_MU_CNT : integer;
  attribute C_PROBE3_MU_CNT of U0 : label is 1;
  attribute C_PROBE3_TYPE : integer;
  attribute C_PROBE3_TYPE of U0 : label is 0;
  attribute C_PROBE3_WIDTH : integer;
  attribute C_PROBE3_WIDTH of U0 : label is 8;
  attribute C_PROBE400_MU_CNT : integer;
  attribute C_PROBE400_MU_CNT of U0 : label is 1;
  attribute C_PROBE400_TYPE : integer;
  attribute C_PROBE400_TYPE of U0 : label is 1;
  attribute C_PROBE400_WIDTH : integer;
  attribute C_PROBE400_WIDTH of U0 : label is 1;
  attribute C_PROBE401_MU_CNT : integer;
  attribute C_PROBE401_MU_CNT of U0 : label is 1;
  attribute C_PROBE401_TYPE : integer;
  attribute C_PROBE401_TYPE of U0 : label is 1;
  attribute C_PROBE401_WIDTH : integer;
  attribute C_PROBE401_WIDTH of U0 : label is 1;
  attribute C_PROBE402_MU_CNT : integer;
  attribute C_PROBE402_MU_CNT of U0 : label is 1;
  attribute C_PROBE402_TYPE : integer;
  attribute C_PROBE402_TYPE of U0 : label is 1;
  attribute C_PROBE402_WIDTH : integer;
  attribute C_PROBE402_WIDTH of U0 : label is 1;
  attribute C_PROBE403_MU_CNT : integer;
  attribute C_PROBE403_MU_CNT of U0 : label is 1;
  attribute C_PROBE403_TYPE : integer;
  attribute C_PROBE403_TYPE of U0 : label is 1;
  attribute C_PROBE403_WIDTH : integer;
  attribute C_PROBE403_WIDTH of U0 : label is 1;
  attribute C_PROBE404_MU_CNT : integer;
  attribute C_PROBE404_MU_CNT of U0 : label is 1;
  attribute C_PROBE404_TYPE : integer;
  attribute C_PROBE404_TYPE of U0 : label is 1;
  attribute C_PROBE404_WIDTH : integer;
  attribute C_PROBE404_WIDTH of U0 : label is 1;
  attribute C_PROBE405_MU_CNT : integer;
  attribute C_PROBE405_MU_CNT of U0 : label is 1;
  attribute C_PROBE405_TYPE : integer;
  attribute C_PROBE405_TYPE of U0 : label is 1;
  attribute C_PROBE405_WIDTH : integer;
  attribute C_PROBE405_WIDTH of U0 : label is 1;
  attribute C_PROBE406_MU_CNT : integer;
  attribute C_PROBE406_MU_CNT of U0 : label is 1;
  attribute C_PROBE406_TYPE : integer;
  attribute C_PROBE406_TYPE of U0 : label is 1;
  attribute C_PROBE406_WIDTH : integer;
  attribute C_PROBE406_WIDTH of U0 : label is 1;
  attribute C_PROBE407_MU_CNT : integer;
  attribute C_PROBE407_MU_CNT of U0 : label is 1;
  attribute C_PROBE407_TYPE : integer;
  attribute C_PROBE407_TYPE of U0 : label is 1;
  attribute C_PROBE407_WIDTH : integer;
  attribute C_PROBE407_WIDTH of U0 : label is 1;
  attribute C_PROBE408_MU_CNT : integer;
  attribute C_PROBE408_MU_CNT of U0 : label is 1;
  attribute C_PROBE408_TYPE : integer;
  attribute C_PROBE408_TYPE of U0 : label is 1;
  attribute C_PROBE408_WIDTH : integer;
  attribute C_PROBE408_WIDTH of U0 : label is 1;
  attribute C_PROBE409_MU_CNT : integer;
  attribute C_PROBE409_MU_CNT of U0 : label is 1;
  attribute C_PROBE409_TYPE : integer;
  attribute C_PROBE409_TYPE of U0 : label is 1;
  attribute C_PROBE409_WIDTH : integer;
  attribute C_PROBE409_WIDTH of U0 : label is 1;
  attribute C_PROBE40_MU_CNT : integer;
  attribute C_PROBE40_MU_CNT of U0 : label is 1;
  attribute C_PROBE40_TYPE : integer;
  attribute C_PROBE40_TYPE of U0 : label is 1;
  attribute C_PROBE40_WIDTH : integer;
  attribute C_PROBE40_WIDTH of U0 : label is 1;
  attribute C_PROBE410_MU_CNT : integer;
  attribute C_PROBE410_MU_CNT of U0 : label is 1;
  attribute C_PROBE410_TYPE : integer;
  attribute C_PROBE410_TYPE of U0 : label is 1;
  attribute C_PROBE410_WIDTH : integer;
  attribute C_PROBE410_WIDTH of U0 : label is 1;
  attribute C_PROBE411_MU_CNT : integer;
  attribute C_PROBE411_MU_CNT of U0 : label is 1;
  attribute C_PROBE411_TYPE : integer;
  attribute C_PROBE411_TYPE of U0 : label is 1;
  attribute C_PROBE411_WIDTH : integer;
  attribute C_PROBE411_WIDTH of U0 : label is 1;
  attribute C_PROBE412_MU_CNT : integer;
  attribute C_PROBE412_MU_CNT of U0 : label is 1;
  attribute C_PROBE412_TYPE : integer;
  attribute C_PROBE412_TYPE of U0 : label is 1;
  attribute C_PROBE412_WIDTH : integer;
  attribute C_PROBE412_WIDTH of U0 : label is 1;
  attribute C_PROBE413_MU_CNT : integer;
  attribute C_PROBE413_MU_CNT of U0 : label is 1;
  attribute C_PROBE413_TYPE : integer;
  attribute C_PROBE413_TYPE of U0 : label is 1;
  attribute C_PROBE413_WIDTH : integer;
  attribute C_PROBE413_WIDTH of U0 : label is 1;
  attribute C_PROBE414_MU_CNT : integer;
  attribute C_PROBE414_MU_CNT of U0 : label is 1;
  attribute C_PROBE414_TYPE : integer;
  attribute C_PROBE414_TYPE of U0 : label is 1;
  attribute C_PROBE414_WIDTH : integer;
  attribute C_PROBE414_WIDTH of U0 : label is 1;
  attribute C_PROBE415_MU_CNT : integer;
  attribute C_PROBE415_MU_CNT of U0 : label is 1;
  attribute C_PROBE415_TYPE : integer;
  attribute C_PROBE415_TYPE of U0 : label is 1;
  attribute C_PROBE415_WIDTH : integer;
  attribute C_PROBE415_WIDTH of U0 : label is 1;
  attribute C_PROBE416_MU_CNT : integer;
  attribute C_PROBE416_MU_CNT of U0 : label is 1;
  attribute C_PROBE416_TYPE : integer;
  attribute C_PROBE416_TYPE of U0 : label is 1;
  attribute C_PROBE416_WIDTH : integer;
  attribute C_PROBE416_WIDTH of U0 : label is 1;
  attribute C_PROBE417_MU_CNT : integer;
  attribute C_PROBE417_MU_CNT of U0 : label is 1;
  attribute C_PROBE417_TYPE : integer;
  attribute C_PROBE417_TYPE of U0 : label is 1;
  attribute C_PROBE417_WIDTH : integer;
  attribute C_PROBE417_WIDTH of U0 : label is 1;
  attribute C_PROBE418_MU_CNT : integer;
  attribute C_PROBE418_MU_CNT of U0 : label is 1;
  attribute C_PROBE418_TYPE : integer;
  attribute C_PROBE418_TYPE of U0 : label is 1;
  attribute C_PROBE418_WIDTH : integer;
  attribute C_PROBE418_WIDTH of U0 : label is 1;
  attribute C_PROBE419_MU_CNT : integer;
  attribute C_PROBE419_MU_CNT of U0 : label is 1;
  attribute C_PROBE419_TYPE : integer;
  attribute C_PROBE419_TYPE of U0 : label is 1;
  attribute C_PROBE419_WIDTH : integer;
  attribute C_PROBE419_WIDTH of U0 : label is 1;
  attribute C_PROBE41_MU_CNT : integer;
  attribute C_PROBE41_MU_CNT of U0 : label is 1;
  attribute C_PROBE41_TYPE : integer;
  attribute C_PROBE41_TYPE of U0 : label is 1;
  attribute C_PROBE41_WIDTH : integer;
  attribute C_PROBE41_WIDTH of U0 : label is 1;
  attribute C_PROBE420_MU_CNT : integer;
  attribute C_PROBE420_MU_CNT of U0 : label is 1;
  attribute C_PROBE420_TYPE : integer;
  attribute C_PROBE420_TYPE of U0 : label is 1;
  attribute C_PROBE420_WIDTH : integer;
  attribute C_PROBE420_WIDTH of U0 : label is 1;
  attribute C_PROBE421_MU_CNT : integer;
  attribute C_PROBE421_MU_CNT of U0 : label is 1;
  attribute C_PROBE421_TYPE : integer;
  attribute C_PROBE421_TYPE of U0 : label is 1;
  attribute C_PROBE421_WIDTH : integer;
  attribute C_PROBE421_WIDTH of U0 : label is 1;
  attribute C_PROBE422_MU_CNT : integer;
  attribute C_PROBE422_MU_CNT of U0 : label is 1;
  attribute C_PROBE422_TYPE : integer;
  attribute C_PROBE422_TYPE of U0 : label is 1;
  attribute C_PROBE422_WIDTH : integer;
  attribute C_PROBE422_WIDTH of U0 : label is 1;
  attribute C_PROBE423_MU_CNT : integer;
  attribute C_PROBE423_MU_CNT of U0 : label is 1;
  attribute C_PROBE423_TYPE : integer;
  attribute C_PROBE423_TYPE of U0 : label is 1;
  attribute C_PROBE423_WIDTH : integer;
  attribute C_PROBE423_WIDTH of U0 : label is 1;
  attribute C_PROBE424_MU_CNT : integer;
  attribute C_PROBE424_MU_CNT of U0 : label is 1;
  attribute C_PROBE424_TYPE : integer;
  attribute C_PROBE424_TYPE of U0 : label is 1;
  attribute C_PROBE424_WIDTH : integer;
  attribute C_PROBE424_WIDTH of U0 : label is 1;
  attribute C_PROBE425_MU_CNT : integer;
  attribute C_PROBE425_MU_CNT of U0 : label is 1;
  attribute C_PROBE425_TYPE : integer;
  attribute C_PROBE425_TYPE of U0 : label is 1;
  attribute C_PROBE425_WIDTH : integer;
  attribute C_PROBE425_WIDTH of U0 : label is 1;
  attribute C_PROBE426_MU_CNT : integer;
  attribute C_PROBE426_MU_CNT of U0 : label is 1;
  attribute C_PROBE426_TYPE : integer;
  attribute C_PROBE426_TYPE of U0 : label is 1;
  attribute C_PROBE426_WIDTH : integer;
  attribute C_PROBE426_WIDTH of U0 : label is 1;
  attribute C_PROBE427_MU_CNT : integer;
  attribute C_PROBE427_MU_CNT of U0 : label is 1;
  attribute C_PROBE427_TYPE : integer;
  attribute C_PROBE427_TYPE of U0 : label is 1;
  attribute C_PROBE427_WIDTH : integer;
  attribute C_PROBE427_WIDTH of U0 : label is 1;
  attribute C_PROBE428_MU_CNT : integer;
  attribute C_PROBE428_MU_CNT of U0 : label is 1;
  attribute C_PROBE428_TYPE : integer;
  attribute C_PROBE428_TYPE of U0 : label is 1;
  attribute C_PROBE428_WIDTH : integer;
  attribute C_PROBE428_WIDTH of U0 : label is 1;
  attribute C_PROBE429_MU_CNT : integer;
  attribute C_PROBE429_MU_CNT of U0 : label is 1;
  attribute C_PROBE429_TYPE : integer;
  attribute C_PROBE429_TYPE of U0 : label is 1;
  attribute C_PROBE429_WIDTH : integer;
  attribute C_PROBE429_WIDTH of U0 : label is 1;
  attribute C_PROBE42_MU_CNT : integer;
  attribute C_PROBE42_MU_CNT of U0 : label is 1;
  attribute C_PROBE42_TYPE : integer;
  attribute C_PROBE42_TYPE of U0 : label is 1;
  attribute C_PROBE42_WIDTH : integer;
  attribute C_PROBE42_WIDTH of U0 : label is 1;
  attribute C_PROBE430_MU_CNT : integer;
  attribute C_PROBE430_MU_CNT of U0 : label is 1;
  attribute C_PROBE430_TYPE : integer;
  attribute C_PROBE430_TYPE of U0 : label is 1;
  attribute C_PROBE430_WIDTH : integer;
  attribute C_PROBE430_WIDTH of U0 : label is 1;
  attribute C_PROBE431_MU_CNT : integer;
  attribute C_PROBE431_MU_CNT of U0 : label is 1;
  attribute C_PROBE431_TYPE : integer;
  attribute C_PROBE431_TYPE of U0 : label is 1;
  attribute C_PROBE431_WIDTH : integer;
  attribute C_PROBE431_WIDTH of U0 : label is 1;
  attribute C_PROBE432_MU_CNT : integer;
  attribute C_PROBE432_MU_CNT of U0 : label is 1;
  attribute C_PROBE432_TYPE : integer;
  attribute C_PROBE432_TYPE of U0 : label is 1;
  attribute C_PROBE432_WIDTH : integer;
  attribute C_PROBE432_WIDTH of U0 : label is 1;
  attribute C_PROBE433_MU_CNT : integer;
  attribute C_PROBE433_MU_CNT of U0 : label is 1;
  attribute C_PROBE433_TYPE : integer;
  attribute C_PROBE433_TYPE of U0 : label is 1;
  attribute C_PROBE433_WIDTH : integer;
  attribute C_PROBE433_WIDTH of U0 : label is 1;
  attribute C_PROBE434_MU_CNT : integer;
  attribute C_PROBE434_MU_CNT of U0 : label is 1;
  attribute C_PROBE434_TYPE : integer;
  attribute C_PROBE434_TYPE of U0 : label is 1;
  attribute C_PROBE434_WIDTH : integer;
  attribute C_PROBE434_WIDTH of U0 : label is 1;
  attribute C_PROBE435_MU_CNT : integer;
  attribute C_PROBE435_MU_CNT of U0 : label is 1;
  attribute C_PROBE435_TYPE : integer;
  attribute C_PROBE435_TYPE of U0 : label is 1;
  attribute C_PROBE435_WIDTH : integer;
  attribute C_PROBE435_WIDTH of U0 : label is 1;
  attribute C_PROBE436_MU_CNT : integer;
  attribute C_PROBE436_MU_CNT of U0 : label is 1;
  attribute C_PROBE436_TYPE : integer;
  attribute C_PROBE436_TYPE of U0 : label is 1;
  attribute C_PROBE436_WIDTH : integer;
  attribute C_PROBE436_WIDTH of U0 : label is 1;
  attribute C_PROBE437_MU_CNT : integer;
  attribute C_PROBE437_MU_CNT of U0 : label is 1;
  attribute C_PROBE437_TYPE : integer;
  attribute C_PROBE437_TYPE of U0 : label is 1;
  attribute C_PROBE437_WIDTH : integer;
  attribute C_PROBE437_WIDTH of U0 : label is 1;
  attribute C_PROBE438_MU_CNT : integer;
  attribute C_PROBE438_MU_CNT of U0 : label is 1;
  attribute C_PROBE438_TYPE : integer;
  attribute C_PROBE438_TYPE of U0 : label is 1;
  attribute C_PROBE438_WIDTH : integer;
  attribute C_PROBE438_WIDTH of U0 : label is 1;
  attribute C_PROBE439_MU_CNT : integer;
  attribute C_PROBE439_MU_CNT of U0 : label is 1;
  attribute C_PROBE439_TYPE : integer;
  attribute C_PROBE439_TYPE of U0 : label is 1;
  attribute C_PROBE439_WIDTH : integer;
  attribute C_PROBE439_WIDTH of U0 : label is 1;
  attribute C_PROBE43_MU_CNT : integer;
  attribute C_PROBE43_MU_CNT of U0 : label is 1;
  attribute C_PROBE43_TYPE : integer;
  attribute C_PROBE43_TYPE of U0 : label is 1;
  attribute C_PROBE43_WIDTH : integer;
  attribute C_PROBE43_WIDTH of U0 : label is 1;
  attribute C_PROBE440_MU_CNT : integer;
  attribute C_PROBE440_MU_CNT of U0 : label is 1;
  attribute C_PROBE440_TYPE : integer;
  attribute C_PROBE440_TYPE of U0 : label is 1;
  attribute C_PROBE440_WIDTH : integer;
  attribute C_PROBE440_WIDTH of U0 : label is 1;
  attribute C_PROBE441_MU_CNT : integer;
  attribute C_PROBE441_MU_CNT of U0 : label is 1;
  attribute C_PROBE441_TYPE : integer;
  attribute C_PROBE441_TYPE of U0 : label is 1;
  attribute C_PROBE441_WIDTH : integer;
  attribute C_PROBE441_WIDTH of U0 : label is 1;
  attribute C_PROBE442_MU_CNT : integer;
  attribute C_PROBE442_MU_CNT of U0 : label is 1;
  attribute C_PROBE442_TYPE : integer;
  attribute C_PROBE442_TYPE of U0 : label is 1;
  attribute C_PROBE442_WIDTH : integer;
  attribute C_PROBE442_WIDTH of U0 : label is 1;
  attribute C_PROBE443_MU_CNT : integer;
  attribute C_PROBE443_MU_CNT of U0 : label is 1;
  attribute C_PROBE443_TYPE : integer;
  attribute C_PROBE443_TYPE of U0 : label is 1;
  attribute C_PROBE443_WIDTH : integer;
  attribute C_PROBE443_WIDTH of U0 : label is 1;
  attribute C_PROBE444_MU_CNT : integer;
  attribute C_PROBE444_MU_CNT of U0 : label is 1;
  attribute C_PROBE444_TYPE : integer;
  attribute C_PROBE444_TYPE of U0 : label is 1;
  attribute C_PROBE444_WIDTH : integer;
  attribute C_PROBE444_WIDTH of U0 : label is 1;
  attribute C_PROBE445_MU_CNT : integer;
  attribute C_PROBE445_MU_CNT of U0 : label is 1;
  attribute C_PROBE445_TYPE : integer;
  attribute C_PROBE445_TYPE of U0 : label is 1;
  attribute C_PROBE445_WIDTH : integer;
  attribute C_PROBE445_WIDTH of U0 : label is 1;
  attribute C_PROBE446_MU_CNT : integer;
  attribute C_PROBE446_MU_CNT of U0 : label is 1;
  attribute C_PROBE446_TYPE : integer;
  attribute C_PROBE446_TYPE of U0 : label is 1;
  attribute C_PROBE446_WIDTH : integer;
  attribute C_PROBE446_WIDTH of U0 : label is 1;
  attribute C_PROBE447_MU_CNT : integer;
  attribute C_PROBE447_MU_CNT of U0 : label is 1;
  attribute C_PROBE447_TYPE : integer;
  attribute C_PROBE447_TYPE of U0 : label is 1;
  attribute C_PROBE447_WIDTH : integer;
  attribute C_PROBE447_WIDTH of U0 : label is 1;
  attribute C_PROBE448_MU_CNT : integer;
  attribute C_PROBE448_MU_CNT of U0 : label is 1;
  attribute C_PROBE448_TYPE : integer;
  attribute C_PROBE448_TYPE of U0 : label is 1;
  attribute C_PROBE448_WIDTH : integer;
  attribute C_PROBE448_WIDTH of U0 : label is 1;
  attribute C_PROBE449_MU_CNT : integer;
  attribute C_PROBE449_MU_CNT of U0 : label is 1;
  attribute C_PROBE449_TYPE : integer;
  attribute C_PROBE449_TYPE of U0 : label is 1;
  attribute C_PROBE449_WIDTH : integer;
  attribute C_PROBE449_WIDTH of U0 : label is 1;
  attribute C_PROBE44_MU_CNT : integer;
  attribute C_PROBE44_MU_CNT of U0 : label is 1;
  attribute C_PROBE44_TYPE : integer;
  attribute C_PROBE44_TYPE of U0 : label is 1;
  attribute C_PROBE44_WIDTH : integer;
  attribute C_PROBE44_WIDTH of U0 : label is 1;
  attribute C_PROBE450_MU_CNT : integer;
  attribute C_PROBE450_MU_CNT of U0 : label is 1;
  attribute C_PROBE450_TYPE : integer;
  attribute C_PROBE450_TYPE of U0 : label is 1;
  attribute C_PROBE450_WIDTH : integer;
  attribute C_PROBE450_WIDTH of U0 : label is 1;
  attribute C_PROBE451_MU_CNT : integer;
  attribute C_PROBE451_MU_CNT of U0 : label is 1;
  attribute C_PROBE451_TYPE : integer;
  attribute C_PROBE451_TYPE of U0 : label is 1;
  attribute C_PROBE451_WIDTH : integer;
  attribute C_PROBE451_WIDTH of U0 : label is 1;
  attribute C_PROBE452_MU_CNT : integer;
  attribute C_PROBE452_MU_CNT of U0 : label is 1;
  attribute C_PROBE452_TYPE : integer;
  attribute C_PROBE452_TYPE of U0 : label is 1;
  attribute C_PROBE452_WIDTH : integer;
  attribute C_PROBE452_WIDTH of U0 : label is 1;
  attribute C_PROBE453_MU_CNT : integer;
  attribute C_PROBE453_MU_CNT of U0 : label is 1;
  attribute C_PROBE453_TYPE : integer;
  attribute C_PROBE453_TYPE of U0 : label is 1;
  attribute C_PROBE453_WIDTH : integer;
  attribute C_PROBE453_WIDTH of U0 : label is 1;
  attribute C_PROBE454_MU_CNT : integer;
  attribute C_PROBE454_MU_CNT of U0 : label is 1;
  attribute C_PROBE454_TYPE : integer;
  attribute C_PROBE454_TYPE of U0 : label is 1;
  attribute C_PROBE454_WIDTH : integer;
  attribute C_PROBE454_WIDTH of U0 : label is 1;
  attribute C_PROBE455_MU_CNT : integer;
  attribute C_PROBE455_MU_CNT of U0 : label is 1;
  attribute C_PROBE455_TYPE : integer;
  attribute C_PROBE455_TYPE of U0 : label is 1;
  attribute C_PROBE455_WIDTH : integer;
  attribute C_PROBE455_WIDTH of U0 : label is 1;
  attribute C_PROBE456_MU_CNT : integer;
  attribute C_PROBE456_MU_CNT of U0 : label is 1;
  attribute C_PROBE456_TYPE : integer;
  attribute C_PROBE456_TYPE of U0 : label is 1;
  attribute C_PROBE456_WIDTH : integer;
  attribute C_PROBE456_WIDTH of U0 : label is 1;
  attribute C_PROBE457_MU_CNT : integer;
  attribute C_PROBE457_MU_CNT of U0 : label is 1;
  attribute C_PROBE457_TYPE : integer;
  attribute C_PROBE457_TYPE of U0 : label is 1;
  attribute C_PROBE457_WIDTH : integer;
  attribute C_PROBE457_WIDTH of U0 : label is 1;
  attribute C_PROBE458_MU_CNT : integer;
  attribute C_PROBE458_MU_CNT of U0 : label is 1;
  attribute C_PROBE458_TYPE : integer;
  attribute C_PROBE458_TYPE of U0 : label is 1;
  attribute C_PROBE458_WIDTH : integer;
  attribute C_PROBE458_WIDTH of U0 : label is 1;
  attribute C_PROBE459_MU_CNT : integer;
  attribute C_PROBE459_MU_CNT of U0 : label is 1;
  attribute C_PROBE459_TYPE : integer;
  attribute C_PROBE459_TYPE of U0 : label is 1;
  attribute C_PROBE459_WIDTH : integer;
  attribute C_PROBE459_WIDTH of U0 : label is 1;
  attribute C_PROBE45_MU_CNT : integer;
  attribute C_PROBE45_MU_CNT of U0 : label is 1;
  attribute C_PROBE45_TYPE : integer;
  attribute C_PROBE45_TYPE of U0 : label is 1;
  attribute C_PROBE45_WIDTH : integer;
  attribute C_PROBE45_WIDTH of U0 : label is 1;
  attribute C_PROBE460_MU_CNT : integer;
  attribute C_PROBE460_MU_CNT of U0 : label is 1;
  attribute C_PROBE460_TYPE : integer;
  attribute C_PROBE460_TYPE of U0 : label is 1;
  attribute C_PROBE460_WIDTH : integer;
  attribute C_PROBE460_WIDTH of U0 : label is 1;
  attribute C_PROBE461_MU_CNT : integer;
  attribute C_PROBE461_MU_CNT of U0 : label is 1;
  attribute C_PROBE461_TYPE : integer;
  attribute C_PROBE461_TYPE of U0 : label is 1;
  attribute C_PROBE461_WIDTH : integer;
  attribute C_PROBE461_WIDTH of U0 : label is 1;
  attribute C_PROBE462_MU_CNT : integer;
  attribute C_PROBE462_MU_CNT of U0 : label is 1;
  attribute C_PROBE462_TYPE : integer;
  attribute C_PROBE462_TYPE of U0 : label is 1;
  attribute C_PROBE462_WIDTH : integer;
  attribute C_PROBE462_WIDTH of U0 : label is 1;
  attribute C_PROBE463_MU_CNT : integer;
  attribute C_PROBE463_MU_CNT of U0 : label is 1;
  attribute C_PROBE463_TYPE : integer;
  attribute C_PROBE463_TYPE of U0 : label is 1;
  attribute C_PROBE463_WIDTH : integer;
  attribute C_PROBE463_WIDTH of U0 : label is 1;
  attribute C_PROBE464_MU_CNT : integer;
  attribute C_PROBE464_MU_CNT of U0 : label is 1;
  attribute C_PROBE464_TYPE : integer;
  attribute C_PROBE464_TYPE of U0 : label is 1;
  attribute C_PROBE464_WIDTH : integer;
  attribute C_PROBE464_WIDTH of U0 : label is 1;
  attribute C_PROBE465_MU_CNT : integer;
  attribute C_PROBE465_MU_CNT of U0 : label is 1;
  attribute C_PROBE465_TYPE : integer;
  attribute C_PROBE465_TYPE of U0 : label is 1;
  attribute C_PROBE465_WIDTH : integer;
  attribute C_PROBE465_WIDTH of U0 : label is 1;
  attribute C_PROBE466_MU_CNT : integer;
  attribute C_PROBE466_MU_CNT of U0 : label is 1;
  attribute C_PROBE466_TYPE : integer;
  attribute C_PROBE466_TYPE of U0 : label is 1;
  attribute C_PROBE466_WIDTH : integer;
  attribute C_PROBE466_WIDTH of U0 : label is 1;
  attribute C_PROBE467_MU_CNT : integer;
  attribute C_PROBE467_MU_CNT of U0 : label is 1;
  attribute C_PROBE467_TYPE : integer;
  attribute C_PROBE467_TYPE of U0 : label is 1;
  attribute C_PROBE467_WIDTH : integer;
  attribute C_PROBE467_WIDTH of U0 : label is 1;
  attribute C_PROBE468_MU_CNT : integer;
  attribute C_PROBE468_MU_CNT of U0 : label is 1;
  attribute C_PROBE468_TYPE : integer;
  attribute C_PROBE468_TYPE of U0 : label is 1;
  attribute C_PROBE468_WIDTH : integer;
  attribute C_PROBE468_WIDTH of U0 : label is 1;
  attribute C_PROBE469_MU_CNT : integer;
  attribute C_PROBE469_MU_CNT of U0 : label is 1;
  attribute C_PROBE469_TYPE : integer;
  attribute C_PROBE469_TYPE of U0 : label is 1;
  attribute C_PROBE469_WIDTH : integer;
  attribute C_PROBE469_WIDTH of U0 : label is 1;
  attribute C_PROBE46_MU_CNT : integer;
  attribute C_PROBE46_MU_CNT of U0 : label is 1;
  attribute C_PROBE46_TYPE : integer;
  attribute C_PROBE46_TYPE of U0 : label is 1;
  attribute C_PROBE46_WIDTH : integer;
  attribute C_PROBE46_WIDTH of U0 : label is 1;
  attribute C_PROBE470_MU_CNT : integer;
  attribute C_PROBE470_MU_CNT of U0 : label is 1;
  attribute C_PROBE470_TYPE : integer;
  attribute C_PROBE470_TYPE of U0 : label is 1;
  attribute C_PROBE470_WIDTH : integer;
  attribute C_PROBE470_WIDTH of U0 : label is 1;
  attribute C_PROBE471_MU_CNT : integer;
  attribute C_PROBE471_MU_CNT of U0 : label is 1;
  attribute C_PROBE471_TYPE : integer;
  attribute C_PROBE471_TYPE of U0 : label is 1;
  attribute C_PROBE471_WIDTH : integer;
  attribute C_PROBE471_WIDTH of U0 : label is 1;
  attribute C_PROBE472_MU_CNT : integer;
  attribute C_PROBE472_MU_CNT of U0 : label is 1;
  attribute C_PROBE472_TYPE : integer;
  attribute C_PROBE472_TYPE of U0 : label is 1;
  attribute C_PROBE472_WIDTH : integer;
  attribute C_PROBE472_WIDTH of U0 : label is 1;
  attribute C_PROBE473_MU_CNT : integer;
  attribute C_PROBE473_MU_CNT of U0 : label is 1;
  attribute C_PROBE473_TYPE : integer;
  attribute C_PROBE473_TYPE of U0 : label is 1;
  attribute C_PROBE473_WIDTH : integer;
  attribute C_PROBE473_WIDTH of U0 : label is 1;
  attribute C_PROBE474_MU_CNT : integer;
  attribute C_PROBE474_MU_CNT of U0 : label is 1;
  attribute C_PROBE474_TYPE : integer;
  attribute C_PROBE474_TYPE of U0 : label is 1;
  attribute C_PROBE474_WIDTH : integer;
  attribute C_PROBE474_WIDTH of U0 : label is 1;
  attribute C_PROBE475_MU_CNT : integer;
  attribute C_PROBE475_MU_CNT of U0 : label is 1;
  attribute C_PROBE475_TYPE : integer;
  attribute C_PROBE475_TYPE of U0 : label is 1;
  attribute C_PROBE475_WIDTH : integer;
  attribute C_PROBE475_WIDTH of U0 : label is 1;
  attribute C_PROBE476_MU_CNT : integer;
  attribute C_PROBE476_MU_CNT of U0 : label is 1;
  attribute C_PROBE476_TYPE : integer;
  attribute C_PROBE476_TYPE of U0 : label is 1;
  attribute C_PROBE476_WIDTH : integer;
  attribute C_PROBE476_WIDTH of U0 : label is 1;
  attribute C_PROBE477_MU_CNT : integer;
  attribute C_PROBE477_MU_CNT of U0 : label is 1;
  attribute C_PROBE477_TYPE : integer;
  attribute C_PROBE477_TYPE of U0 : label is 1;
  attribute C_PROBE477_WIDTH : integer;
  attribute C_PROBE477_WIDTH of U0 : label is 1;
  attribute C_PROBE478_MU_CNT : integer;
  attribute C_PROBE478_MU_CNT of U0 : label is 1;
  attribute C_PROBE478_TYPE : integer;
  attribute C_PROBE478_TYPE of U0 : label is 1;
  attribute C_PROBE478_WIDTH : integer;
  attribute C_PROBE478_WIDTH of U0 : label is 1;
  attribute C_PROBE479_MU_CNT : integer;
  attribute C_PROBE479_MU_CNT of U0 : label is 1;
  attribute C_PROBE479_TYPE : integer;
  attribute C_PROBE479_TYPE of U0 : label is 1;
  attribute C_PROBE479_WIDTH : integer;
  attribute C_PROBE479_WIDTH of U0 : label is 1;
  attribute C_PROBE47_MU_CNT : integer;
  attribute C_PROBE47_MU_CNT of U0 : label is 1;
  attribute C_PROBE47_TYPE : integer;
  attribute C_PROBE47_TYPE of U0 : label is 1;
  attribute C_PROBE47_WIDTH : integer;
  attribute C_PROBE47_WIDTH of U0 : label is 1;
  attribute C_PROBE480_MU_CNT : integer;
  attribute C_PROBE480_MU_CNT of U0 : label is 1;
  attribute C_PROBE480_TYPE : integer;
  attribute C_PROBE480_TYPE of U0 : label is 1;
  attribute C_PROBE480_WIDTH : integer;
  attribute C_PROBE480_WIDTH of U0 : label is 1;
  attribute C_PROBE481_MU_CNT : integer;
  attribute C_PROBE481_MU_CNT of U0 : label is 1;
  attribute C_PROBE481_TYPE : integer;
  attribute C_PROBE481_TYPE of U0 : label is 1;
  attribute C_PROBE481_WIDTH : integer;
  attribute C_PROBE481_WIDTH of U0 : label is 1;
  attribute C_PROBE482_MU_CNT : integer;
  attribute C_PROBE482_MU_CNT of U0 : label is 1;
  attribute C_PROBE482_TYPE : integer;
  attribute C_PROBE482_TYPE of U0 : label is 1;
  attribute C_PROBE482_WIDTH : integer;
  attribute C_PROBE482_WIDTH of U0 : label is 1;
  attribute C_PROBE483_MU_CNT : integer;
  attribute C_PROBE483_MU_CNT of U0 : label is 1;
  attribute C_PROBE483_TYPE : integer;
  attribute C_PROBE483_TYPE of U0 : label is 1;
  attribute C_PROBE483_WIDTH : integer;
  attribute C_PROBE483_WIDTH of U0 : label is 1;
  attribute C_PROBE484_MU_CNT : integer;
  attribute C_PROBE484_MU_CNT of U0 : label is 1;
  attribute C_PROBE484_TYPE : integer;
  attribute C_PROBE484_TYPE of U0 : label is 1;
  attribute C_PROBE484_WIDTH : integer;
  attribute C_PROBE484_WIDTH of U0 : label is 1;
  attribute C_PROBE485_MU_CNT : integer;
  attribute C_PROBE485_MU_CNT of U0 : label is 1;
  attribute C_PROBE485_TYPE : integer;
  attribute C_PROBE485_TYPE of U0 : label is 1;
  attribute C_PROBE485_WIDTH : integer;
  attribute C_PROBE485_WIDTH of U0 : label is 1;
  attribute C_PROBE486_MU_CNT : integer;
  attribute C_PROBE486_MU_CNT of U0 : label is 1;
  attribute C_PROBE486_TYPE : integer;
  attribute C_PROBE486_TYPE of U0 : label is 1;
  attribute C_PROBE486_WIDTH : integer;
  attribute C_PROBE486_WIDTH of U0 : label is 1;
  attribute C_PROBE487_MU_CNT : integer;
  attribute C_PROBE487_MU_CNT of U0 : label is 1;
  attribute C_PROBE487_TYPE : integer;
  attribute C_PROBE487_TYPE of U0 : label is 1;
  attribute C_PROBE487_WIDTH : integer;
  attribute C_PROBE487_WIDTH of U0 : label is 1;
  attribute C_PROBE488_MU_CNT : integer;
  attribute C_PROBE488_MU_CNT of U0 : label is 1;
  attribute C_PROBE488_TYPE : integer;
  attribute C_PROBE488_TYPE of U0 : label is 1;
  attribute C_PROBE488_WIDTH : integer;
  attribute C_PROBE488_WIDTH of U0 : label is 1;
  attribute C_PROBE489_MU_CNT : integer;
  attribute C_PROBE489_MU_CNT of U0 : label is 1;
  attribute C_PROBE489_TYPE : integer;
  attribute C_PROBE489_TYPE of U0 : label is 1;
  attribute C_PROBE489_WIDTH : integer;
  attribute C_PROBE489_WIDTH of U0 : label is 1;
  attribute C_PROBE48_MU_CNT : integer;
  attribute C_PROBE48_MU_CNT of U0 : label is 1;
  attribute C_PROBE48_TYPE : integer;
  attribute C_PROBE48_TYPE of U0 : label is 1;
  attribute C_PROBE48_WIDTH : integer;
  attribute C_PROBE48_WIDTH of U0 : label is 1;
  attribute C_PROBE490_MU_CNT : integer;
  attribute C_PROBE490_MU_CNT of U0 : label is 1;
  attribute C_PROBE490_TYPE : integer;
  attribute C_PROBE490_TYPE of U0 : label is 1;
  attribute C_PROBE490_WIDTH : integer;
  attribute C_PROBE490_WIDTH of U0 : label is 1;
  attribute C_PROBE491_MU_CNT : integer;
  attribute C_PROBE491_MU_CNT of U0 : label is 1;
  attribute C_PROBE491_TYPE : integer;
  attribute C_PROBE491_TYPE of U0 : label is 1;
  attribute C_PROBE491_WIDTH : integer;
  attribute C_PROBE491_WIDTH of U0 : label is 1;
  attribute C_PROBE492_MU_CNT : integer;
  attribute C_PROBE492_MU_CNT of U0 : label is 1;
  attribute C_PROBE492_TYPE : integer;
  attribute C_PROBE492_TYPE of U0 : label is 1;
  attribute C_PROBE492_WIDTH : integer;
  attribute C_PROBE492_WIDTH of U0 : label is 1;
  attribute C_PROBE493_MU_CNT : integer;
  attribute C_PROBE493_MU_CNT of U0 : label is 1;
  attribute C_PROBE493_TYPE : integer;
  attribute C_PROBE493_TYPE of U0 : label is 1;
  attribute C_PROBE493_WIDTH : integer;
  attribute C_PROBE493_WIDTH of U0 : label is 1;
  attribute C_PROBE494_MU_CNT : integer;
  attribute C_PROBE494_MU_CNT of U0 : label is 1;
  attribute C_PROBE494_TYPE : integer;
  attribute C_PROBE494_TYPE of U0 : label is 1;
  attribute C_PROBE494_WIDTH : integer;
  attribute C_PROBE494_WIDTH of U0 : label is 1;
  attribute C_PROBE495_MU_CNT : integer;
  attribute C_PROBE495_MU_CNT of U0 : label is 1;
  attribute C_PROBE495_TYPE : integer;
  attribute C_PROBE495_TYPE of U0 : label is 1;
  attribute C_PROBE495_WIDTH : integer;
  attribute C_PROBE495_WIDTH of U0 : label is 1;
  attribute C_PROBE496_MU_CNT : integer;
  attribute C_PROBE496_MU_CNT of U0 : label is 1;
  attribute C_PROBE496_TYPE : integer;
  attribute C_PROBE496_TYPE of U0 : label is 1;
  attribute C_PROBE496_WIDTH : integer;
  attribute C_PROBE496_WIDTH of U0 : label is 1;
  attribute C_PROBE497_MU_CNT : integer;
  attribute C_PROBE497_MU_CNT of U0 : label is 1;
  attribute C_PROBE497_TYPE : integer;
  attribute C_PROBE497_TYPE of U0 : label is 1;
  attribute C_PROBE497_WIDTH : integer;
  attribute C_PROBE497_WIDTH of U0 : label is 1;
  attribute C_PROBE498_MU_CNT : integer;
  attribute C_PROBE498_MU_CNT of U0 : label is 1;
  attribute C_PROBE498_TYPE : integer;
  attribute C_PROBE498_TYPE of U0 : label is 1;
  attribute C_PROBE498_WIDTH : integer;
  attribute C_PROBE498_WIDTH of U0 : label is 1;
  attribute C_PROBE499_MU_CNT : integer;
  attribute C_PROBE499_MU_CNT of U0 : label is 1;
  attribute C_PROBE499_TYPE : integer;
  attribute C_PROBE499_TYPE of U0 : label is 1;
  attribute C_PROBE499_WIDTH : integer;
  attribute C_PROBE499_WIDTH of U0 : label is 1;
  attribute C_PROBE49_MU_CNT : integer;
  attribute C_PROBE49_MU_CNT of U0 : label is 1;
  attribute C_PROBE49_TYPE : integer;
  attribute C_PROBE49_TYPE of U0 : label is 1;
  attribute C_PROBE49_WIDTH : integer;
  attribute C_PROBE49_WIDTH of U0 : label is 1;
  attribute C_PROBE4_MU_CNT : integer;
  attribute C_PROBE4_MU_CNT of U0 : label is 1;
  attribute C_PROBE4_TYPE : integer;
  attribute C_PROBE4_TYPE of U0 : label is 0;
  attribute C_PROBE4_WIDTH : integer;
  attribute C_PROBE4_WIDTH of U0 : label is 32;
  attribute C_PROBE500_MU_CNT : integer;
  attribute C_PROBE500_MU_CNT of U0 : label is 1;
  attribute C_PROBE500_TYPE : integer;
  attribute C_PROBE500_TYPE of U0 : label is 1;
  attribute C_PROBE500_WIDTH : integer;
  attribute C_PROBE500_WIDTH of U0 : label is 1;
  attribute C_PROBE501_MU_CNT : integer;
  attribute C_PROBE501_MU_CNT of U0 : label is 1;
  attribute C_PROBE501_TYPE : integer;
  attribute C_PROBE501_TYPE of U0 : label is 1;
  attribute C_PROBE501_WIDTH : integer;
  attribute C_PROBE501_WIDTH of U0 : label is 1;
  attribute C_PROBE502_MU_CNT : integer;
  attribute C_PROBE502_MU_CNT of U0 : label is 1;
  attribute C_PROBE502_TYPE : integer;
  attribute C_PROBE502_TYPE of U0 : label is 1;
  attribute C_PROBE502_WIDTH : integer;
  attribute C_PROBE502_WIDTH of U0 : label is 1;
  attribute C_PROBE503_MU_CNT : integer;
  attribute C_PROBE503_MU_CNT of U0 : label is 1;
  attribute C_PROBE503_TYPE : integer;
  attribute C_PROBE503_TYPE of U0 : label is 1;
  attribute C_PROBE503_WIDTH : integer;
  attribute C_PROBE503_WIDTH of U0 : label is 1;
  attribute C_PROBE504_MU_CNT : integer;
  attribute C_PROBE504_MU_CNT of U0 : label is 1;
  attribute C_PROBE504_TYPE : integer;
  attribute C_PROBE504_TYPE of U0 : label is 1;
  attribute C_PROBE504_WIDTH : integer;
  attribute C_PROBE504_WIDTH of U0 : label is 1;
  attribute C_PROBE505_MU_CNT : integer;
  attribute C_PROBE505_MU_CNT of U0 : label is 1;
  attribute C_PROBE505_TYPE : integer;
  attribute C_PROBE505_TYPE of U0 : label is 1;
  attribute C_PROBE505_WIDTH : integer;
  attribute C_PROBE505_WIDTH of U0 : label is 1;
  attribute C_PROBE506_MU_CNT : integer;
  attribute C_PROBE506_MU_CNT of U0 : label is 1;
  attribute C_PROBE506_TYPE : integer;
  attribute C_PROBE506_TYPE of U0 : label is 1;
  attribute C_PROBE506_WIDTH : integer;
  attribute C_PROBE506_WIDTH of U0 : label is 1;
  attribute C_PROBE507_MU_CNT : integer;
  attribute C_PROBE507_MU_CNT of U0 : label is 1;
  attribute C_PROBE507_TYPE : integer;
  attribute C_PROBE507_TYPE of U0 : label is 1;
  attribute C_PROBE507_WIDTH : integer;
  attribute C_PROBE507_WIDTH of U0 : label is 1;
  attribute C_PROBE508_MU_CNT : integer;
  attribute C_PROBE508_MU_CNT of U0 : label is 1;
  attribute C_PROBE508_TYPE : integer;
  attribute C_PROBE508_TYPE of U0 : label is 1;
  attribute C_PROBE508_WIDTH : integer;
  attribute C_PROBE508_WIDTH of U0 : label is 1;
  attribute C_PROBE509_MU_CNT : integer;
  attribute C_PROBE509_MU_CNT of U0 : label is 1;
  attribute C_PROBE509_TYPE : integer;
  attribute C_PROBE509_TYPE of U0 : label is 1;
  attribute C_PROBE509_WIDTH : integer;
  attribute C_PROBE509_WIDTH of U0 : label is 1;
  attribute C_PROBE50_MU_CNT : integer;
  attribute C_PROBE50_MU_CNT of U0 : label is 1;
  attribute C_PROBE50_TYPE : integer;
  attribute C_PROBE50_TYPE of U0 : label is 1;
  attribute C_PROBE50_WIDTH : integer;
  attribute C_PROBE50_WIDTH of U0 : label is 1;
  attribute C_PROBE510_MU_CNT : integer;
  attribute C_PROBE510_MU_CNT of U0 : label is 1;
  attribute C_PROBE510_TYPE : integer;
  attribute C_PROBE510_TYPE of U0 : label is 1;
  attribute C_PROBE510_WIDTH : integer;
  attribute C_PROBE510_WIDTH of U0 : label is 1;
  attribute C_PROBE511_MU_CNT : integer;
  attribute C_PROBE511_MU_CNT of U0 : label is 1;
  attribute C_PROBE511_TYPE : integer;
  attribute C_PROBE511_TYPE of U0 : label is 1;
  attribute C_PROBE511_WIDTH : integer;
  attribute C_PROBE511_WIDTH of U0 : label is 1;
  attribute C_PROBE512_MU_CNT : integer;
  attribute C_PROBE512_MU_CNT of U0 : label is 1;
  attribute C_PROBE512_TYPE : integer;
  attribute C_PROBE512_TYPE of U0 : label is 1;
  attribute C_PROBE512_WIDTH : integer;
  attribute C_PROBE512_WIDTH of U0 : label is 1;
  attribute C_PROBE513_MU_CNT : integer;
  attribute C_PROBE513_MU_CNT of U0 : label is 1;
  attribute C_PROBE513_TYPE : integer;
  attribute C_PROBE513_TYPE of U0 : label is 1;
  attribute C_PROBE513_WIDTH : integer;
  attribute C_PROBE513_WIDTH of U0 : label is 1;
  attribute C_PROBE514_MU_CNT : integer;
  attribute C_PROBE514_MU_CNT of U0 : label is 1;
  attribute C_PROBE514_TYPE : integer;
  attribute C_PROBE514_TYPE of U0 : label is 1;
  attribute C_PROBE514_WIDTH : integer;
  attribute C_PROBE514_WIDTH of U0 : label is 1;
  attribute C_PROBE515_MU_CNT : integer;
  attribute C_PROBE515_MU_CNT of U0 : label is 1;
  attribute C_PROBE515_TYPE : integer;
  attribute C_PROBE515_TYPE of U0 : label is 1;
  attribute C_PROBE515_WIDTH : integer;
  attribute C_PROBE515_WIDTH of U0 : label is 1;
  attribute C_PROBE516_MU_CNT : integer;
  attribute C_PROBE516_MU_CNT of U0 : label is 1;
  attribute C_PROBE516_TYPE : integer;
  attribute C_PROBE516_TYPE of U0 : label is 1;
  attribute C_PROBE516_WIDTH : integer;
  attribute C_PROBE516_WIDTH of U0 : label is 1;
  attribute C_PROBE517_MU_CNT : integer;
  attribute C_PROBE517_MU_CNT of U0 : label is 1;
  attribute C_PROBE517_TYPE : integer;
  attribute C_PROBE517_TYPE of U0 : label is 1;
  attribute C_PROBE517_WIDTH : integer;
  attribute C_PROBE517_WIDTH of U0 : label is 1;
  attribute C_PROBE518_MU_CNT : integer;
  attribute C_PROBE518_MU_CNT of U0 : label is 1;
  attribute C_PROBE518_TYPE : integer;
  attribute C_PROBE518_TYPE of U0 : label is 1;
  attribute C_PROBE518_WIDTH : integer;
  attribute C_PROBE518_WIDTH of U0 : label is 1;
  attribute C_PROBE519_MU_CNT : integer;
  attribute C_PROBE519_MU_CNT of U0 : label is 1;
  attribute C_PROBE519_TYPE : integer;
  attribute C_PROBE519_TYPE of U0 : label is 1;
  attribute C_PROBE519_WIDTH : integer;
  attribute C_PROBE519_WIDTH of U0 : label is 1;
  attribute C_PROBE51_MU_CNT : integer;
  attribute C_PROBE51_MU_CNT of U0 : label is 1;
  attribute C_PROBE51_TYPE : integer;
  attribute C_PROBE51_TYPE of U0 : label is 1;
  attribute C_PROBE51_WIDTH : integer;
  attribute C_PROBE51_WIDTH of U0 : label is 1;
  attribute C_PROBE520_MU_CNT : integer;
  attribute C_PROBE520_MU_CNT of U0 : label is 1;
  attribute C_PROBE520_TYPE : integer;
  attribute C_PROBE520_TYPE of U0 : label is 1;
  attribute C_PROBE520_WIDTH : integer;
  attribute C_PROBE520_WIDTH of U0 : label is 1;
  attribute C_PROBE521_MU_CNT : integer;
  attribute C_PROBE521_MU_CNT of U0 : label is 1;
  attribute C_PROBE521_TYPE : integer;
  attribute C_PROBE521_TYPE of U0 : label is 1;
  attribute C_PROBE521_WIDTH : integer;
  attribute C_PROBE521_WIDTH of U0 : label is 1;
  attribute C_PROBE522_MU_CNT : integer;
  attribute C_PROBE522_MU_CNT of U0 : label is 1;
  attribute C_PROBE522_TYPE : integer;
  attribute C_PROBE522_TYPE of U0 : label is 1;
  attribute C_PROBE522_WIDTH : integer;
  attribute C_PROBE522_WIDTH of U0 : label is 1;
  attribute C_PROBE523_MU_CNT : integer;
  attribute C_PROBE523_MU_CNT of U0 : label is 1;
  attribute C_PROBE523_TYPE : integer;
  attribute C_PROBE523_TYPE of U0 : label is 1;
  attribute C_PROBE523_WIDTH : integer;
  attribute C_PROBE523_WIDTH of U0 : label is 1;
  attribute C_PROBE524_MU_CNT : integer;
  attribute C_PROBE524_MU_CNT of U0 : label is 1;
  attribute C_PROBE524_TYPE : integer;
  attribute C_PROBE524_TYPE of U0 : label is 1;
  attribute C_PROBE524_WIDTH : integer;
  attribute C_PROBE524_WIDTH of U0 : label is 1;
  attribute C_PROBE525_MU_CNT : integer;
  attribute C_PROBE525_MU_CNT of U0 : label is 1;
  attribute C_PROBE525_TYPE : integer;
  attribute C_PROBE525_TYPE of U0 : label is 1;
  attribute C_PROBE525_WIDTH : integer;
  attribute C_PROBE525_WIDTH of U0 : label is 1;
  attribute C_PROBE526_MU_CNT : integer;
  attribute C_PROBE526_MU_CNT of U0 : label is 1;
  attribute C_PROBE526_TYPE : integer;
  attribute C_PROBE526_TYPE of U0 : label is 1;
  attribute C_PROBE526_WIDTH : integer;
  attribute C_PROBE526_WIDTH of U0 : label is 1;
  attribute C_PROBE527_MU_CNT : integer;
  attribute C_PROBE527_MU_CNT of U0 : label is 1;
  attribute C_PROBE527_TYPE : integer;
  attribute C_PROBE527_TYPE of U0 : label is 1;
  attribute C_PROBE527_WIDTH : integer;
  attribute C_PROBE527_WIDTH of U0 : label is 1;
  attribute C_PROBE528_MU_CNT : integer;
  attribute C_PROBE528_MU_CNT of U0 : label is 1;
  attribute C_PROBE528_TYPE : integer;
  attribute C_PROBE528_TYPE of U0 : label is 1;
  attribute C_PROBE528_WIDTH : integer;
  attribute C_PROBE528_WIDTH of U0 : label is 1;
  attribute C_PROBE529_MU_CNT : integer;
  attribute C_PROBE529_MU_CNT of U0 : label is 1;
  attribute C_PROBE529_TYPE : integer;
  attribute C_PROBE529_TYPE of U0 : label is 1;
  attribute C_PROBE529_WIDTH : integer;
  attribute C_PROBE529_WIDTH of U0 : label is 1;
  attribute C_PROBE52_MU_CNT : integer;
  attribute C_PROBE52_MU_CNT of U0 : label is 1;
  attribute C_PROBE52_TYPE : integer;
  attribute C_PROBE52_TYPE of U0 : label is 1;
  attribute C_PROBE52_WIDTH : integer;
  attribute C_PROBE52_WIDTH of U0 : label is 1;
  attribute C_PROBE530_MU_CNT : integer;
  attribute C_PROBE530_MU_CNT of U0 : label is 1;
  attribute C_PROBE530_TYPE : integer;
  attribute C_PROBE530_TYPE of U0 : label is 1;
  attribute C_PROBE530_WIDTH : integer;
  attribute C_PROBE530_WIDTH of U0 : label is 1;
  attribute C_PROBE531_MU_CNT : integer;
  attribute C_PROBE531_MU_CNT of U0 : label is 1;
  attribute C_PROBE531_TYPE : integer;
  attribute C_PROBE531_TYPE of U0 : label is 1;
  attribute C_PROBE531_WIDTH : integer;
  attribute C_PROBE531_WIDTH of U0 : label is 1;
  attribute C_PROBE532_MU_CNT : integer;
  attribute C_PROBE532_MU_CNT of U0 : label is 1;
  attribute C_PROBE532_TYPE : integer;
  attribute C_PROBE532_TYPE of U0 : label is 1;
  attribute C_PROBE532_WIDTH : integer;
  attribute C_PROBE532_WIDTH of U0 : label is 1;
  attribute C_PROBE533_MU_CNT : integer;
  attribute C_PROBE533_MU_CNT of U0 : label is 1;
  attribute C_PROBE533_TYPE : integer;
  attribute C_PROBE533_TYPE of U0 : label is 1;
  attribute C_PROBE533_WIDTH : integer;
  attribute C_PROBE533_WIDTH of U0 : label is 1;
  attribute C_PROBE534_MU_CNT : integer;
  attribute C_PROBE534_MU_CNT of U0 : label is 1;
  attribute C_PROBE534_TYPE : integer;
  attribute C_PROBE534_TYPE of U0 : label is 1;
  attribute C_PROBE534_WIDTH : integer;
  attribute C_PROBE534_WIDTH of U0 : label is 1;
  attribute C_PROBE535_MU_CNT : integer;
  attribute C_PROBE535_MU_CNT of U0 : label is 1;
  attribute C_PROBE535_TYPE : integer;
  attribute C_PROBE535_TYPE of U0 : label is 1;
  attribute C_PROBE535_WIDTH : integer;
  attribute C_PROBE535_WIDTH of U0 : label is 1;
  attribute C_PROBE536_MU_CNT : integer;
  attribute C_PROBE536_MU_CNT of U0 : label is 1;
  attribute C_PROBE536_TYPE : integer;
  attribute C_PROBE536_TYPE of U0 : label is 1;
  attribute C_PROBE536_WIDTH : integer;
  attribute C_PROBE536_WIDTH of U0 : label is 1;
  attribute C_PROBE537_MU_CNT : integer;
  attribute C_PROBE537_MU_CNT of U0 : label is 1;
  attribute C_PROBE537_TYPE : integer;
  attribute C_PROBE537_TYPE of U0 : label is 1;
  attribute C_PROBE537_WIDTH : integer;
  attribute C_PROBE537_WIDTH of U0 : label is 1;
  attribute C_PROBE538_MU_CNT : integer;
  attribute C_PROBE538_MU_CNT of U0 : label is 1;
  attribute C_PROBE538_TYPE : integer;
  attribute C_PROBE538_TYPE of U0 : label is 1;
  attribute C_PROBE538_WIDTH : integer;
  attribute C_PROBE538_WIDTH of U0 : label is 1;
  attribute C_PROBE539_MU_CNT : integer;
  attribute C_PROBE539_MU_CNT of U0 : label is 1;
  attribute C_PROBE539_TYPE : integer;
  attribute C_PROBE539_TYPE of U0 : label is 1;
  attribute C_PROBE539_WIDTH : integer;
  attribute C_PROBE539_WIDTH of U0 : label is 1;
  attribute C_PROBE53_MU_CNT : integer;
  attribute C_PROBE53_MU_CNT of U0 : label is 1;
  attribute C_PROBE53_TYPE : integer;
  attribute C_PROBE53_TYPE of U0 : label is 1;
  attribute C_PROBE53_WIDTH : integer;
  attribute C_PROBE53_WIDTH of U0 : label is 1;
  attribute C_PROBE540_MU_CNT : integer;
  attribute C_PROBE540_MU_CNT of U0 : label is 1;
  attribute C_PROBE540_TYPE : integer;
  attribute C_PROBE540_TYPE of U0 : label is 1;
  attribute C_PROBE540_WIDTH : integer;
  attribute C_PROBE540_WIDTH of U0 : label is 1;
  attribute C_PROBE541_MU_CNT : integer;
  attribute C_PROBE541_MU_CNT of U0 : label is 1;
  attribute C_PROBE541_TYPE : integer;
  attribute C_PROBE541_TYPE of U0 : label is 1;
  attribute C_PROBE541_WIDTH : integer;
  attribute C_PROBE541_WIDTH of U0 : label is 1;
  attribute C_PROBE542_MU_CNT : integer;
  attribute C_PROBE542_MU_CNT of U0 : label is 1;
  attribute C_PROBE542_TYPE : integer;
  attribute C_PROBE542_TYPE of U0 : label is 1;
  attribute C_PROBE542_WIDTH : integer;
  attribute C_PROBE542_WIDTH of U0 : label is 1;
  attribute C_PROBE543_MU_CNT : integer;
  attribute C_PROBE543_MU_CNT of U0 : label is 1;
  attribute C_PROBE543_TYPE : integer;
  attribute C_PROBE543_TYPE of U0 : label is 1;
  attribute C_PROBE543_WIDTH : integer;
  attribute C_PROBE543_WIDTH of U0 : label is 1;
  attribute C_PROBE544_MU_CNT : integer;
  attribute C_PROBE544_MU_CNT of U0 : label is 1;
  attribute C_PROBE544_TYPE : integer;
  attribute C_PROBE544_TYPE of U0 : label is 1;
  attribute C_PROBE544_WIDTH : integer;
  attribute C_PROBE544_WIDTH of U0 : label is 1;
  attribute C_PROBE545_MU_CNT : integer;
  attribute C_PROBE545_MU_CNT of U0 : label is 1;
  attribute C_PROBE545_TYPE : integer;
  attribute C_PROBE545_TYPE of U0 : label is 1;
  attribute C_PROBE545_WIDTH : integer;
  attribute C_PROBE545_WIDTH of U0 : label is 1;
  attribute C_PROBE546_MU_CNT : integer;
  attribute C_PROBE546_MU_CNT of U0 : label is 1;
  attribute C_PROBE546_TYPE : integer;
  attribute C_PROBE546_TYPE of U0 : label is 1;
  attribute C_PROBE546_WIDTH : integer;
  attribute C_PROBE546_WIDTH of U0 : label is 1;
  attribute C_PROBE547_MU_CNT : integer;
  attribute C_PROBE547_MU_CNT of U0 : label is 1;
  attribute C_PROBE547_TYPE : integer;
  attribute C_PROBE547_TYPE of U0 : label is 1;
  attribute C_PROBE547_WIDTH : integer;
  attribute C_PROBE547_WIDTH of U0 : label is 1;
  attribute C_PROBE548_MU_CNT : integer;
  attribute C_PROBE548_MU_CNT of U0 : label is 1;
  attribute C_PROBE548_TYPE : integer;
  attribute C_PROBE548_TYPE of U0 : label is 1;
  attribute C_PROBE548_WIDTH : integer;
  attribute C_PROBE548_WIDTH of U0 : label is 1;
  attribute C_PROBE549_MU_CNT : integer;
  attribute C_PROBE549_MU_CNT of U0 : label is 1;
  attribute C_PROBE549_TYPE : integer;
  attribute C_PROBE549_TYPE of U0 : label is 1;
  attribute C_PROBE549_WIDTH : integer;
  attribute C_PROBE549_WIDTH of U0 : label is 1;
  attribute C_PROBE54_MU_CNT : integer;
  attribute C_PROBE54_MU_CNT of U0 : label is 1;
  attribute C_PROBE54_TYPE : integer;
  attribute C_PROBE54_TYPE of U0 : label is 1;
  attribute C_PROBE54_WIDTH : integer;
  attribute C_PROBE54_WIDTH of U0 : label is 1;
  attribute C_PROBE550_MU_CNT : integer;
  attribute C_PROBE550_MU_CNT of U0 : label is 1;
  attribute C_PROBE550_TYPE : integer;
  attribute C_PROBE550_TYPE of U0 : label is 1;
  attribute C_PROBE550_WIDTH : integer;
  attribute C_PROBE550_WIDTH of U0 : label is 1;
  attribute C_PROBE551_MU_CNT : integer;
  attribute C_PROBE551_MU_CNT of U0 : label is 1;
  attribute C_PROBE551_TYPE : integer;
  attribute C_PROBE551_TYPE of U0 : label is 1;
  attribute C_PROBE551_WIDTH : integer;
  attribute C_PROBE551_WIDTH of U0 : label is 1;
  attribute C_PROBE552_MU_CNT : integer;
  attribute C_PROBE552_MU_CNT of U0 : label is 1;
  attribute C_PROBE552_TYPE : integer;
  attribute C_PROBE552_TYPE of U0 : label is 1;
  attribute C_PROBE552_WIDTH : integer;
  attribute C_PROBE552_WIDTH of U0 : label is 1;
  attribute C_PROBE553_MU_CNT : integer;
  attribute C_PROBE553_MU_CNT of U0 : label is 1;
  attribute C_PROBE553_TYPE : integer;
  attribute C_PROBE553_TYPE of U0 : label is 1;
  attribute C_PROBE553_WIDTH : integer;
  attribute C_PROBE553_WIDTH of U0 : label is 1;
  attribute C_PROBE554_MU_CNT : integer;
  attribute C_PROBE554_MU_CNT of U0 : label is 1;
  attribute C_PROBE554_TYPE : integer;
  attribute C_PROBE554_TYPE of U0 : label is 1;
  attribute C_PROBE554_WIDTH : integer;
  attribute C_PROBE554_WIDTH of U0 : label is 1;
  attribute C_PROBE555_MU_CNT : integer;
  attribute C_PROBE555_MU_CNT of U0 : label is 1;
  attribute C_PROBE555_TYPE : integer;
  attribute C_PROBE555_TYPE of U0 : label is 1;
  attribute C_PROBE555_WIDTH : integer;
  attribute C_PROBE555_WIDTH of U0 : label is 1;
  attribute C_PROBE556_MU_CNT : integer;
  attribute C_PROBE556_MU_CNT of U0 : label is 1;
  attribute C_PROBE556_TYPE : integer;
  attribute C_PROBE556_TYPE of U0 : label is 1;
  attribute C_PROBE556_WIDTH : integer;
  attribute C_PROBE556_WIDTH of U0 : label is 1;
  attribute C_PROBE557_MU_CNT : integer;
  attribute C_PROBE557_MU_CNT of U0 : label is 1;
  attribute C_PROBE557_TYPE : integer;
  attribute C_PROBE557_TYPE of U0 : label is 1;
  attribute C_PROBE557_WIDTH : integer;
  attribute C_PROBE557_WIDTH of U0 : label is 1;
  attribute C_PROBE558_MU_CNT : integer;
  attribute C_PROBE558_MU_CNT of U0 : label is 1;
  attribute C_PROBE558_TYPE : integer;
  attribute C_PROBE558_TYPE of U0 : label is 1;
  attribute C_PROBE558_WIDTH : integer;
  attribute C_PROBE558_WIDTH of U0 : label is 1;
  attribute C_PROBE559_MU_CNT : integer;
  attribute C_PROBE559_MU_CNT of U0 : label is 1;
  attribute C_PROBE559_TYPE : integer;
  attribute C_PROBE559_TYPE of U0 : label is 1;
  attribute C_PROBE559_WIDTH : integer;
  attribute C_PROBE559_WIDTH of U0 : label is 1;
  attribute C_PROBE55_MU_CNT : integer;
  attribute C_PROBE55_MU_CNT of U0 : label is 1;
  attribute C_PROBE55_TYPE : integer;
  attribute C_PROBE55_TYPE of U0 : label is 1;
  attribute C_PROBE55_WIDTH : integer;
  attribute C_PROBE55_WIDTH of U0 : label is 1;
  attribute C_PROBE560_MU_CNT : integer;
  attribute C_PROBE560_MU_CNT of U0 : label is 1;
  attribute C_PROBE560_TYPE : integer;
  attribute C_PROBE560_TYPE of U0 : label is 1;
  attribute C_PROBE560_WIDTH : integer;
  attribute C_PROBE560_WIDTH of U0 : label is 1;
  attribute C_PROBE561_MU_CNT : integer;
  attribute C_PROBE561_MU_CNT of U0 : label is 1;
  attribute C_PROBE561_TYPE : integer;
  attribute C_PROBE561_TYPE of U0 : label is 1;
  attribute C_PROBE561_WIDTH : integer;
  attribute C_PROBE561_WIDTH of U0 : label is 1;
  attribute C_PROBE562_MU_CNT : integer;
  attribute C_PROBE562_MU_CNT of U0 : label is 1;
  attribute C_PROBE562_TYPE : integer;
  attribute C_PROBE562_TYPE of U0 : label is 1;
  attribute C_PROBE562_WIDTH : integer;
  attribute C_PROBE562_WIDTH of U0 : label is 1;
  attribute C_PROBE563_MU_CNT : integer;
  attribute C_PROBE563_MU_CNT of U0 : label is 1;
  attribute C_PROBE563_TYPE : integer;
  attribute C_PROBE563_TYPE of U0 : label is 1;
  attribute C_PROBE563_WIDTH : integer;
  attribute C_PROBE563_WIDTH of U0 : label is 1;
  attribute C_PROBE564_MU_CNT : integer;
  attribute C_PROBE564_MU_CNT of U0 : label is 1;
  attribute C_PROBE564_TYPE : integer;
  attribute C_PROBE564_TYPE of U0 : label is 1;
  attribute C_PROBE564_WIDTH : integer;
  attribute C_PROBE564_WIDTH of U0 : label is 1;
  attribute C_PROBE565_MU_CNT : integer;
  attribute C_PROBE565_MU_CNT of U0 : label is 1;
  attribute C_PROBE565_TYPE : integer;
  attribute C_PROBE565_TYPE of U0 : label is 1;
  attribute C_PROBE565_WIDTH : integer;
  attribute C_PROBE565_WIDTH of U0 : label is 1;
  attribute C_PROBE566_MU_CNT : integer;
  attribute C_PROBE566_MU_CNT of U0 : label is 1;
  attribute C_PROBE566_TYPE : integer;
  attribute C_PROBE566_TYPE of U0 : label is 1;
  attribute C_PROBE566_WIDTH : integer;
  attribute C_PROBE566_WIDTH of U0 : label is 1;
  attribute C_PROBE567_MU_CNT : integer;
  attribute C_PROBE567_MU_CNT of U0 : label is 1;
  attribute C_PROBE567_TYPE : integer;
  attribute C_PROBE567_TYPE of U0 : label is 1;
  attribute C_PROBE567_WIDTH : integer;
  attribute C_PROBE567_WIDTH of U0 : label is 1;
  attribute C_PROBE568_MU_CNT : integer;
  attribute C_PROBE568_MU_CNT of U0 : label is 1;
  attribute C_PROBE568_TYPE : integer;
  attribute C_PROBE568_TYPE of U0 : label is 1;
  attribute C_PROBE568_WIDTH : integer;
  attribute C_PROBE568_WIDTH of U0 : label is 1;
  attribute C_PROBE569_MU_CNT : integer;
  attribute C_PROBE569_MU_CNT of U0 : label is 1;
  attribute C_PROBE569_TYPE : integer;
  attribute C_PROBE569_TYPE of U0 : label is 1;
  attribute C_PROBE569_WIDTH : integer;
  attribute C_PROBE569_WIDTH of U0 : label is 1;
  attribute C_PROBE56_MU_CNT : integer;
  attribute C_PROBE56_MU_CNT of U0 : label is 1;
  attribute C_PROBE56_TYPE : integer;
  attribute C_PROBE56_TYPE of U0 : label is 1;
  attribute C_PROBE56_WIDTH : integer;
  attribute C_PROBE56_WIDTH of U0 : label is 1;
  attribute C_PROBE570_MU_CNT : integer;
  attribute C_PROBE570_MU_CNT of U0 : label is 1;
  attribute C_PROBE570_TYPE : integer;
  attribute C_PROBE570_TYPE of U0 : label is 1;
  attribute C_PROBE570_WIDTH : integer;
  attribute C_PROBE570_WIDTH of U0 : label is 1;
  attribute C_PROBE571_MU_CNT : integer;
  attribute C_PROBE571_MU_CNT of U0 : label is 1;
  attribute C_PROBE571_TYPE : integer;
  attribute C_PROBE571_TYPE of U0 : label is 1;
  attribute C_PROBE571_WIDTH : integer;
  attribute C_PROBE571_WIDTH of U0 : label is 1;
  attribute C_PROBE572_MU_CNT : integer;
  attribute C_PROBE572_MU_CNT of U0 : label is 1;
  attribute C_PROBE572_TYPE : integer;
  attribute C_PROBE572_TYPE of U0 : label is 1;
  attribute C_PROBE572_WIDTH : integer;
  attribute C_PROBE572_WIDTH of U0 : label is 1;
  attribute C_PROBE573_MU_CNT : integer;
  attribute C_PROBE573_MU_CNT of U0 : label is 1;
  attribute C_PROBE573_TYPE : integer;
  attribute C_PROBE573_TYPE of U0 : label is 1;
  attribute C_PROBE573_WIDTH : integer;
  attribute C_PROBE573_WIDTH of U0 : label is 1;
  attribute C_PROBE574_MU_CNT : integer;
  attribute C_PROBE574_MU_CNT of U0 : label is 1;
  attribute C_PROBE574_TYPE : integer;
  attribute C_PROBE574_TYPE of U0 : label is 1;
  attribute C_PROBE574_WIDTH : integer;
  attribute C_PROBE574_WIDTH of U0 : label is 1;
  attribute C_PROBE575_MU_CNT : integer;
  attribute C_PROBE575_MU_CNT of U0 : label is 1;
  attribute C_PROBE575_TYPE : integer;
  attribute C_PROBE575_TYPE of U0 : label is 1;
  attribute C_PROBE575_WIDTH : integer;
  attribute C_PROBE575_WIDTH of U0 : label is 1;
  attribute C_PROBE576_MU_CNT : integer;
  attribute C_PROBE576_MU_CNT of U0 : label is 1;
  attribute C_PROBE576_TYPE : integer;
  attribute C_PROBE576_TYPE of U0 : label is 1;
  attribute C_PROBE576_WIDTH : integer;
  attribute C_PROBE576_WIDTH of U0 : label is 1;
  attribute C_PROBE577_MU_CNT : integer;
  attribute C_PROBE577_MU_CNT of U0 : label is 1;
  attribute C_PROBE577_TYPE : integer;
  attribute C_PROBE577_TYPE of U0 : label is 1;
  attribute C_PROBE577_WIDTH : integer;
  attribute C_PROBE577_WIDTH of U0 : label is 1;
  attribute C_PROBE578_MU_CNT : integer;
  attribute C_PROBE578_MU_CNT of U0 : label is 1;
  attribute C_PROBE578_TYPE : integer;
  attribute C_PROBE578_TYPE of U0 : label is 1;
  attribute C_PROBE578_WIDTH : integer;
  attribute C_PROBE578_WIDTH of U0 : label is 1;
  attribute C_PROBE579_MU_CNT : integer;
  attribute C_PROBE579_MU_CNT of U0 : label is 1;
  attribute C_PROBE579_TYPE : integer;
  attribute C_PROBE579_TYPE of U0 : label is 1;
  attribute C_PROBE579_WIDTH : integer;
  attribute C_PROBE579_WIDTH of U0 : label is 1;
  attribute C_PROBE57_MU_CNT : integer;
  attribute C_PROBE57_MU_CNT of U0 : label is 1;
  attribute C_PROBE57_TYPE : integer;
  attribute C_PROBE57_TYPE of U0 : label is 1;
  attribute C_PROBE57_WIDTH : integer;
  attribute C_PROBE57_WIDTH of U0 : label is 1;
  attribute C_PROBE580_MU_CNT : integer;
  attribute C_PROBE580_MU_CNT of U0 : label is 1;
  attribute C_PROBE580_TYPE : integer;
  attribute C_PROBE580_TYPE of U0 : label is 1;
  attribute C_PROBE580_WIDTH : integer;
  attribute C_PROBE580_WIDTH of U0 : label is 1;
  attribute C_PROBE581_MU_CNT : integer;
  attribute C_PROBE581_MU_CNT of U0 : label is 1;
  attribute C_PROBE581_TYPE : integer;
  attribute C_PROBE581_TYPE of U0 : label is 1;
  attribute C_PROBE581_WIDTH : integer;
  attribute C_PROBE581_WIDTH of U0 : label is 1;
  attribute C_PROBE582_MU_CNT : integer;
  attribute C_PROBE582_MU_CNT of U0 : label is 1;
  attribute C_PROBE582_TYPE : integer;
  attribute C_PROBE582_TYPE of U0 : label is 1;
  attribute C_PROBE582_WIDTH : integer;
  attribute C_PROBE582_WIDTH of U0 : label is 1;
  attribute C_PROBE583_MU_CNT : integer;
  attribute C_PROBE583_MU_CNT of U0 : label is 1;
  attribute C_PROBE583_TYPE : integer;
  attribute C_PROBE583_TYPE of U0 : label is 1;
  attribute C_PROBE583_WIDTH : integer;
  attribute C_PROBE583_WIDTH of U0 : label is 1;
  attribute C_PROBE584_MU_CNT : integer;
  attribute C_PROBE584_MU_CNT of U0 : label is 1;
  attribute C_PROBE584_TYPE : integer;
  attribute C_PROBE584_TYPE of U0 : label is 1;
  attribute C_PROBE584_WIDTH : integer;
  attribute C_PROBE584_WIDTH of U0 : label is 1;
  attribute C_PROBE585_MU_CNT : integer;
  attribute C_PROBE585_MU_CNT of U0 : label is 1;
  attribute C_PROBE585_TYPE : integer;
  attribute C_PROBE585_TYPE of U0 : label is 1;
  attribute C_PROBE585_WIDTH : integer;
  attribute C_PROBE585_WIDTH of U0 : label is 1;
  attribute C_PROBE586_MU_CNT : integer;
  attribute C_PROBE586_MU_CNT of U0 : label is 1;
  attribute C_PROBE586_TYPE : integer;
  attribute C_PROBE586_TYPE of U0 : label is 1;
  attribute C_PROBE586_WIDTH : integer;
  attribute C_PROBE586_WIDTH of U0 : label is 1;
  attribute C_PROBE587_MU_CNT : integer;
  attribute C_PROBE587_MU_CNT of U0 : label is 1;
  attribute C_PROBE587_TYPE : integer;
  attribute C_PROBE587_TYPE of U0 : label is 1;
  attribute C_PROBE587_WIDTH : integer;
  attribute C_PROBE587_WIDTH of U0 : label is 1;
  attribute C_PROBE588_MU_CNT : integer;
  attribute C_PROBE588_MU_CNT of U0 : label is 1;
  attribute C_PROBE588_TYPE : integer;
  attribute C_PROBE588_TYPE of U0 : label is 1;
  attribute C_PROBE588_WIDTH : integer;
  attribute C_PROBE588_WIDTH of U0 : label is 1;
  attribute C_PROBE589_MU_CNT : integer;
  attribute C_PROBE589_MU_CNT of U0 : label is 1;
  attribute C_PROBE589_TYPE : integer;
  attribute C_PROBE589_TYPE of U0 : label is 1;
  attribute C_PROBE589_WIDTH : integer;
  attribute C_PROBE589_WIDTH of U0 : label is 1;
  attribute C_PROBE58_MU_CNT : integer;
  attribute C_PROBE58_MU_CNT of U0 : label is 1;
  attribute C_PROBE58_TYPE : integer;
  attribute C_PROBE58_TYPE of U0 : label is 1;
  attribute C_PROBE58_WIDTH : integer;
  attribute C_PROBE58_WIDTH of U0 : label is 1;
  attribute C_PROBE590_MU_CNT : integer;
  attribute C_PROBE590_MU_CNT of U0 : label is 1;
  attribute C_PROBE590_TYPE : integer;
  attribute C_PROBE590_TYPE of U0 : label is 1;
  attribute C_PROBE590_WIDTH : integer;
  attribute C_PROBE590_WIDTH of U0 : label is 1;
  attribute C_PROBE591_MU_CNT : integer;
  attribute C_PROBE591_MU_CNT of U0 : label is 1;
  attribute C_PROBE591_TYPE : integer;
  attribute C_PROBE591_TYPE of U0 : label is 1;
  attribute C_PROBE591_WIDTH : integer;
  attribute C_PROBE591_WIDTH of U0 : label is 1;
  attribute C_PROBE592_MU_CNT : integer;
  attribute C_PROBE592_MU_CNT of U0 : label is 1;
  attribute C_PROBE592_TYPE : integer;
  attribute C_PROBE592_TYPE of U0 : label is 1;
  attribute C_PROBE592_WIDTH : integer;
  attribute C_PROBE592_WIDTH of U0 : label is 1;
  attribute C_PROBE593_MU_CNT : integer;
  attribute C_PROBE593_MU_CNT of U0 : label is 1;
  attribute C_PROBE593_TYPE : integer;
  attribute C_PROBE593_TYPE of U0 : label is 1;
  attribute C_PROBE593_WIDTH : integer;
  attribute C_PROBE593_WIDTH of U0 : label is 1;
  attribute C_PROBE594_MU_CNT : integer;
  attribute C_PROBE594_MU_CNT of U0 : label is 1;
  attribute C_PROBE594_TYPE : integer;
  attribute C_PROBE594_TYPE of U0 : label is 1;
  attribute C_PROBE594_WIDTH : integer;
  attribute C_PROBE594_WIDTH of U0 : label is 1;
  attribute C_PROBE595_MU_CNT : integer;
  attribute C_PROBE595_MU_CNT of U0 : label is 1;
  attribute C_PROBE595_TYPE : integer;
  attribute C_PROBE595_TYPE of U0 : label is 1;
  attribute C_PROBE595_WIDTH : integer;
  attribute C_PROBE595_WIDTH of U0 : label is 1;
  attribute C_PROBE596_MU_CNT : integer;
  attribute C_PROBE596_MU_CNT of U0 : label is 1;
  attribute C_PROBE596_TYPE : integer;
  attribute C_PROBE596_TYPE of U0 : label is 1;
  attribute C_PROBE596_WIDTH : integer;
  attribute C_PROBE596_WIDTH of U0 : label is 1;
  attribute C_PROBE597_MU_CNT : integer;
  attribute C_PROBE597_MU_CNT of U0 : label is 1;
  attribute C_PROBE597_TYPE : integer;
  attribute C_PROBE597_TYPE of U0 : label is 1;
  attribute C_PROBE597_WIDTH : integer;
  attribute C_PROBE597_WIDTH of U0 : label is 1;
  attribute C_PROBE598_MU_CNT : integer;
  attribute C_PROBE598_MU_CNT of U0 : label is 1;
  attribute C_PROBE598_TYPE : integer;
  attribute C_PROBE598_TYPE of U0 : label is 1;
  attribute C_PROBE598_WIDTH : integer;
  attribute C_PROBE598_WIDTH of U0 : label is 1;
  attribute C_PROBE599_MU_CNT : integer;
  attribute C_PROBE599_MU_CNT of U0 : label is 1;
  attribute C_PROBE599_TYPE : integer;
  attribute C_PROBE599_TYPE of U0 : label is 1;
  attribute C_PROBE599_WIDTH : integer;
  attribute C_PROBE599_WIDTH of U0 : label is 1;
  attribute C_PROBE59_MU_CNT : integer;
  attribute C_PROBE59_MU_CNT of U0 : label is 1;
  attribute C_PROBE59_TYPE : integer;
  attribute C_PROBE59_TYPE of U0 : label is 1;
  attribute C_PROBE59_WIDTH : integer;
  attribute C_PROBE59_WIDTH of U0 : label is 1;
  attribute C_PROBE5_MU_CNT : integer;
  attribute C_PROBE5_MU_CNT of U0 : label is 1;
  attribute C_PROBE5_TYPE : integer;
  attribute C_PROBE5_TYPE of U0 : label is 0;
  attribute C_PROBE5_WIDTH : integer;
  attribute C_PROBE5_WIDTH of U0 : label is 32;
  attribute C_PROBE600_MU_CNT : integer;
  attribute C_PROBE600_MU_CNT of U0 : label is 1;
  attribute C_PROBE600_TYPE : integer;
  attribute C_PROBE600_TYPE of U0 : label is 1;
  attribute C_PROBE600_WIDTH : integer;
  attribute C_PROBE600_WIDTH of U0 : label is 1;
  attribute C_PROBE601_MU_CNT : integer;
  attribute C_PROBE601_MU_CNT of U0 : label is 1;
  attribute C_PROBE601_TYPE : integer;
  attribute C_PROBE601_TYPE of U0 : label is 1;
  attribute C_PROBE601_WIDTH : integer;
  attribute C_PROBE601_WIDTH of U0 : label is 1;
  attribute C_PROBE602_MU_CNT : integer;
  attribute C_PROBE602_MU_CNT of U0 : label is 1;
  attribute C_PROBE602_TYPE : integer;
  attribute C_PROBE602_TYPE of U0 : label is 1;
  attribute C_PROBE602_WIDTH : integer;
  attribute C_PROBE602_WIDTH of U0 : label is 1;
  attribute C_PROBE603_MU_CNT : integer;
  attribute C_PROBE603_MU_CNT of U0 : label is 1;
  attribute C_PROBE603_TYPE : integer;
  attribute C_PROBE603_TYPE of U0 : label is 1;
  attribute C_PROBE603_WIDTH : integer;
  attribute C_PROBE603_WIDTH of U0 : label is 1;
  attribute C_PROBE604_MU_CNT : integer;
  attribute C_PROBE604_MU_CNT of U0 : label is 1;
  attribute C_PROBE604_TYPE : integer;
  attribute C_PROBE604_TYPE of U0 : label is 1;
  attribute C_PROBE604_WIDTH : integer;
  attribute C_PROBE604_WIDTH of U0 : label is 1;
  attribute C_PROBE605_MU_CNT : integer;
  attribute C_PROBE605_MU_CNT of U0 : label is 1;
  attribute C_PROBE605_TYPE : integer;
  attribute C_PROBE605_TYPE of U0 : label is 1;
  attribute C_PROBE605_WIDTH : integer;
  attribute C_PROBE605_WIDTH of U0 : label is 1;
  attribute C_PROBE606_MU_CNT : integer;
  attribute C_PROBE606_MU_CNT of U0 : label is 1;
  attribute C_PROBE606_TYPE : integer;
  attribute C_PROBE606_TYPE of U0 : label is 1;
  attribute C_PROBE606_WIDTH : integer;
  attribute C_PROBE606_WIDTH of U0 : label is 1;
  attribute C_PROBE607_MU_CNT : integer;
  attribute C_PROBE607_MU_CNT of U0 : label is 1;
  attribute C_PROBE607_TYPE : integer;
  attribute C_PROBE607_TYPE of U0 : label is 1;
  attribute C_PROBE607_WIDTH : integer;
  attribute C_PROBE607_WIDTH of U0 : label is 1;
  attribute C_PROBE608_MU_CNT : integer;
  attribute C_PROBE608_MU_CNT of U0 : label is 1;
  attribute C_PROBE608_TYPE : integer;
  attribute C_PROBE608_TYPE of U0 : label is 1;
  attribute C_PROBE608_WIDTH : integer;
  attribute C_PROBE608_WIDTH of U0 : label is 1;
  attribute C_PROBE609_MU_CNT : integer;
  attribute C_PROBE609_MU_CNT of U0 : label is 1;
  attribute C_PROBE609_TYPE : integer;
  attribute C_PROBE609_TYPE of U0 : label is 1;
  attribute C_PROBE609_WIDTH : integer;
  attribute C_PROBE609_WIDTH of U0 : label is 1;
  attribute C_PROBE60_MU_CNT : integer;
  attribute C_PROBE60_MU_CNT of U0 : label is 1;
  attribute C_PROBE60_TYPE : integer;
  attribute C_PROBE60_TYPE of U0 : label is 1;
  attribute C_PROBE60_WIDTH : integer;
  attribute C_PROBE60_WIDTH of U0 : label is 1;
  attribute C_PROBE610_MU_CNT : integer;
  attribute C_PROBE610_MU_CNT of U0 : label is 1;
  attribute C_PROBE610_TYPE : integer;
  attribute C_PROBE610_TYPE of U0 : label is 1;
  attribute C_PROBE610_WIDTH : integer;
  attribute C_PROBE610_WIDTH of U0 : label is 1;
  attribute C_PROBE611_MU_CNT : integer;
  attribute C_PROBE611_MU_CNT of U0 : label is 1;
  attribute C_PROBE611_TYPE : integer;
  attribute C_PROBE611_TYPE of U0 : label is 1;
  attribute C_PROBE611_WIDTH : integer;
  attribute C_PROBE611_WIDTH of U0 : label is 1;
  attribute C_PROBE612_MU_CNT : integer;
  attribute C_PROBE612_MU_CNT of U0 : label is 1;
  attribute C_PROBE612_TYPE : integer;
  attribute C_PROBE612_TYPE of U0 : label is 1;
  attribute C_PROBE612_WIDTH : integer;
  attribute C_PROBE612_WIDTH of U0 : label is 1;
  attribute C_PROBE613_MU_CNT : integer;
  attribute C_PROBE613_MU_CNT of U0 : label is 1;
  attribute C_PROBE613_TYPE : integer;
  attribute C_PROBE613_TYPE of U0 : label is 1;
  attribute C_PROBE613_WIDTH : integer;
  attribute C_PROBE613_WIDTH of U0 : label is 1;
  attribute C_PROBE614_MU_CNT : integer;
  attribute C_PROBE614_MU_CNT of U0 : label is 1;
  attribute C_PROBE614_TYPE : integer;
  attribute C_PROBE614_TYPE of U0 : label is 1;
  attribute C_PROBE614_WIDTH : integer;
  attribute C_PROBE614_WIDTH of U0 : label is 1;
  attribute C_PROBE615_MU_CNT : integer;
  attribute C_PROBE615_MU_CNT of U0 : label is 1;
  attribute C_PROBE615_TYPE : integer;
  attribute C_PROBE615_TYPE of U0 : label is 1;
  attribute C_PROBE615_WIDTH : integer;
  attribute C_PROBE615_WIDTH of U0 : label is 1;
  attribute C_PROBE616_MU_CNT : integer;
  attribute C_PROBE616_MU_CNT of U0 : label is 1;
  attribute C_PROBE616_TYPE : integer;
  attribute C_PROBE616_TYPE of U0 : label is 1;
  attribute C_PROBE616_WIDTH : integer;
  attribute C_PROBE616_WIDTH of U0 : label is 1;
  attribute C_PROBE617_MU_CNT : integer;
  attribute C_PROBE617_MU_CNT of U0 : label is 1;
  attribute C_PROBE617_TYPE : integer;
  attribute C_PROBE617_TYPE of U0 : label is 1;
  attribute C_PROBE617_WIDTH : integer;
  attribute C_PROBE617_WIDTH of U0 : label is 1;
  attribute C_PROBE618_MU_CNT : integer;
  attribute C_PROBE618_MU_CNT of U0 : label is 1;
  attribute C_PROBE618_TYPE : integer;
  attribute C_PROBE618_TYPE of U0 : label is 1;
  attribute C_PROBE618_WIDTH : integer;
  attribute C_PROBE618_WIDTH of U0 : label is 1;
  attribute C_PROBE619_MU_CNT : integer;
  attribute C_PROBE619_MU_CNT of U0 : label is 1;
  attribute C_PROBE619_TYPE : integer;
  attribute C_PROBE619_TYPE of U0 : label is 1;
  attribute C_PROBE619_WIDTH : integer;
  attribute C_PROBE619_WIDTH of U0 : label is 1;
  attribute C_PROBE61_MU_CNT : integer;
  attribute C_PROBE61_MU_CNT of U0 : label is 1;
  attribute C_PROBE61_TYPE : integer;
  attribute C_PROBE61_TYPE of U0 : label is 1;
  attribute C_PROBE61_WIDTH : integer;
  attribute C_PROBE61_WIDTH of U0 : label is 1;
  attribute C_PROBE620_MU_CNT : integer;
  attribute C_PROBE620_MU_CNT of U0 : label is 1;
  attribute C_PROBE620_TYPE : integer;
  attribute C_PROBE620_TYPE of U0 : label is 1;
  attribute C_PROBE620_WIDTH : integer;
  attribute C_PROBE620_WIDTH of U0 : label is 1;
  attribute C_PROBE621_MU_CNT : integer;
  attribute C_PROBE621_MU_CNT of U0 : label is 1;
  attribute C_PROBE621_TYPE : integer;
  attribute C_PROBE621_TYPE of U0 : label is 1;
  attribute C_PROBE621_WIDTH : integer;
  attribute C_PROBE621_WIDTH of U0 : label is 1;
  attribute C_PROBE622_MU_CNT : integer;
  attribute C_PROBE622_MU_CNT of U0 : label is 1;
  attribute C_PROBE622_TYPE : integer;
  attribute C_PROBE622_TYPE of U0 : label is 1;
  attribute C_PROBE622_WIDTH : integer;
  attribute C_PROBE622_WIDTH of U0 : label is 1;
  attribute C_PROBE623_MU_CNT : integer;
  attribute C_PROBE623_MU_CNT of U0 : label is 1;
  attribute C_PROBE623_TYPE : integer;
  attribute C_PROBE623_TYPE of U0 : label is 1;
  attribute C_PROBE623_WIDTH : integer;
  attribute C_PROBE623_WIDTH of U0 : label is 1;
  attribute C_PROBE624_MU_CNT : integer;
  attribute C_PROBE624_MU_CNT of U0 : label is 1;
  attribute C_PROBE624_TYPE : integer;
  attribute C_PROBE624_TYPE of U0 : label is 1;
  attribute C_PROBE624_WIDTH : integer;
  attribute C_PROBE624_WIDTH of U0 : label is 1;
  attribute C_PROBE625_MU_CNT : integer;
  attribute C_PROBE625_MU_CNT of U0 : label is 1;
  attribute C_PROBE625_TYPE : integer;
  attribute C_PROBE625_TYPE of U0 : label is 1;
  attribute C_PROBE625_WIDTH : integer;
  attribute C_PROBE625_WIDTH of U0 : label is 1;
  attribute C_PROBE626_MU_CNT : integer;
  attribute C_PROBE626_MU_CNT of U0 : label is 1;
  attribute C_PROBE626_TYPE : integer;
  attribute C_PROBE626_TYPE of U0 : label is 1;
  attribute C_PROBE626_WIDTH : integer;
  attribute C_PROBE626_WIDTH of U0 : label is 1;
  attribute C_PROBE627_MU_CNT : integer;
  attribute C_PROBE627_MU_CNT of U0 : label is 1;
  attribute C_PROBE627_TYPE : integer;
  attribute C_PROBE627_TYPE of U0 : label is 1;
  attribute C_PROBE627_WIDTH : integer;
  attribute C_PROBE627_WIDTH of U0 : label is 1;
  attribute C_PROBE628_MU_CNT : integer;
  attribute C_PROBE628_MU_CNT of U0 : label is 1;
  attribute C_PROBE628_TYPE : integer;
  attribute C_PROBE628_TYPE of U0 : label is 1;
  attribute C_PROBE628_WIDTH : integer;
  attribute C_PROBE628_WIDTH of U0 : label is 1;
  attribute C_PROBE629_MU_CNT : integer;
  attribute C_PROBE629_MU_CNT of U0 : label is 1;
  attribute C_PROBE629_TYPE : integer;
  attribute C_PROBE629_TYPE of U0 : label is 1;
  attribute C_PROBE629_WIDTH : integer;
  attribute C_PROBE629_WIDTH of U0 : label is 1;
  attribute C_PROBE62_MU_CNT : integer;
  attribute C_PROBE62_MU_CNT of U0 : label is 1;
  attribute C_PROBE62_TYPE : integer;
  attribute C_PROBE62_TYPE of U0 : label is 1;
  attribute C_PROBE62_WIDTH : integer;
  attribute C_PROBE62_WIDTH of U0 : label is 1;
  attribute C_PROBE630_MU_CNT : integer;
  attribute C_PROBE630_MU_CNT of U0 : label is 1;
  attribute C_PROBE630_TYPE : integer;
  attribute C_PROBE630_TYPE of U0 : label is 1;
  attribute C_PROBE630_WIDTH : integer;
  attribute C_PROBE630_WIDTH of U0 : label is 1;
  attribute C_PROBE631_MU_CNT : integer;
  attribute C_PROBE631_MU_CNT of U0 : label is 1;
  attribute C_PROBE631_TYPE : integer;
  attribute C_PROBE631_TYPE of U0 : label is 1;
  attribute C_PROBE631_WIDTH : integer;
  attribute C_PROBE631_WIDTH of U0 : label is 1;
  attribute C_PROBE632_MU_CNT : integer;
  attribute C_PROBE632_MU_CNT of U0 : label is 1;
  attribute C_PROBE632_TYPE : integer;
  attribute C_PROBE632_TYPE of U0 : label is 1;
  attribute C_PROBE632_WIDTH : integer;
  attribute C_PROBE632_WIDTH of U0 : label is 1;
  attribute C_PROBE633_MU_CNT : integer;
  attribute C_PROBE633_MU_CNT of U0 : label is 1;
  attribute C_PROBE633_TYPE : integer;
  attribute C_PROBE633_TYPE of U0 : label is 1;
  attribute C_PROBE633_WIDTH : integer;
  attribute C_PROBE633_WIDTH of U0 : label is 1;
  attribute C_PROBE634_MU_CNT : integer;
  attribute C_PROBE634_MU_CNT of U0 : label is 1;
  attribute C_PROBE634_TYPE : integer;
  attribute C_PROBE634_TYPE of U0 : label is 1;
  attribute C_PROBE634_WIDTH : integer;
  attribute C_PROBE634_WIDTH of U0 : label is 1;
  attribute C_PROBE635_MU_CNT : integer;
  attribute C_PROBE635_MU_CNT of U0 : label is 1;
  attribute C_PROBE635_TYPE : integer;
  attribute C_PROBE635_TYPE of U0 : label is 1;
  attribute C_PROBE635_WIDTH : integer;
  attribute C_PROBE635_WIDTH of U0 : label is 1;
  attribute C_PROBE636_MU_CNT : integer;
  attribute C_PROBE636_MU_CNT of U0 : label is 1;
  attribute C_PROBE636_TYPE : integer;
  attribute C_PROBE636_TYPE of U0 : label is 1;
  attribute C_PROBE636_WIDTH : integer;
  attribute C_PROBE636_WIDTH of U0 : label is 1;
  attribute C_PROBE637_MU_CNT : integer;
  attribute C_PROBE637_MU_CNT of U0 : label is 1;
  attribute C_PROBE637_TYPE : integer;
  attribute C_PROBE637_TYPE of U0 : label is 1;
  attribute C_PROBE637_WIDTH : integer;
  attribute C_PROBE637_WIDTH of U0 : label is 1;
  attribute C_PROBE638_MU_CNT : integer;
  attribute C_PROBE638_MU_CNT of U0 : label is 1;
  attribute C_PROBE638_TYPE : integer;
  attribute C_PROBE638_TYPE of U0 : label is 1;
  attribute C_PROBE638_WIDTH : integer;
  attribute C_PROBE638_WIDTH of U0 : label is 1;
  attribute C_PROBE639_MU_CNT : integer;
  attribute C_PROBE639_MU_CNT of U0 : label is 1;
  attribute C_PROBE639_TYPE : integer;
  attribute C_PROBE639_TYPE of U0 : label is 1;
  attribute C_PROBE639_WIDTH : integer;
  attribute C_PROBE639_WIDTH of U0 : label is 1;
  attribute C_PROBE63_MU_CNT : integer;
  attribute C_PROBE63_MU_CNT of U0 : label is 1;
  attribute C_PROBE63_TYPE : integer;
  attribute C_PROBE63_TYPE of U0 : label is 1;
  attribute C_PROBE63_WIDTH : integer;
  attribute C_PROBE63_WIDTH of U0 : label is 1;
  attribute C_PROBE640_MU_CNT : integer;
  attribute C_PROBE640_MU_CNT of U0 : label is 1;
  attribute C_PROBE640_TYPE : integer;
  attribute C_PROBE640_TYPE of U0 : label is 1;
  attribute C_PROBE640_WIDTH : integer;
  attribute C_PROBE640_WIDTH of U0 : label is 1;
  attribute C_PROBE641_MU_CNT : integer;
  attribute C_PROBE641_MU_CNT of U0 : label is 1;
  attribute C_PROBE641_TYPE : integer;
  attribute C_PROBE641_TYPE of U0 : label is 1;
  attribute C_PROBE641_WIDTH : integer;
  attribute C_PROBE641_WIDTH of U0 : label is 1;
  attribute C_PROBE642_MU_CNT : integer;
  attribute C_PROBE642_MU_CNT of U0 : label is 1;
  attribute C_PROBE642_TYPE : integer;
  attribute C_PROBE642_TYPE of U0 : label is 1;
  attribute C_PROBE642_WIDTH : integer;
  attribute C_PROBE642_WIDTH of U0 : label is 1;
  attribute C_PROBE643_MU_CNT : integer;
  attribute C_PROBE643_MU_CNT of U0 : label is 1;
  attribute C_PROBE643_TYPE : integer;
  attribute C_PROBE643_TYPE of U0 : label is 1;
  attribute C_PROBE643_WIDTH : integer;
  attribute C_PROBE643_WIDTH of U0 : label is 1;
  attribute C_PROBE644_MU_CNT : integer;
  attribute C_PROBE644_MU_CNT of U0 : label is 1;
  attribute C_PROBE644_TYPE : integer;
  attribute C_PROBE644_TYPE of U0 : label is 1;
  attribute C_PROBE644_WIDTH : integer;
  attribute C_PROBE644_WIDTH of U0 : label is 1;
  attribute C_PROBE645_MU_CNT : integer;
  attribute C_PROBE645_MU_CNT of U0 : label is 1;
  attribute C_PROBE645_TYPE : integer;
  attribute C_PROBE645_TYPE of U0 : label is 1;
  attribute C_PROBE645_WIDTH : integer;
  attribute C_PROBE645_WIDTH of U0 : label is 1;
  attribute C_PROBE646_MU_CNT : integer;
  attribute C_PROBE646_MU_CNT of U0 : label is 1;
  attribute C_PROBE646_TYPE : integer;
  attribute C_PROBE646_TYPE of U0 : label is 1;
  attribute C_PROBE646_WIDTH : integer;
  attribute C_PROBE646_WIDTH of U0 : label is 1;
  attribute C_PROBE647_MU_CNT : integer;
  attribute C_PROBE647_MU_CNT of U0 : label is 1;
  attribute C_PROBE647_TYPE : integer;
  attribute C_PROBE647_TYPE of U0 : label is 1;
  attribute C_PROBE647_WIDTH : integer;
  attribute C_PROBE647_WIDTH of U0 : label is 1;
  attribute C_PROBE648_MU_CNT : integer;
  attribute C_PROBE648_MU_CNT of U0 : label is 1;
  attribute C_PROBE648_TYPE : integer;
  attribute C_PROBE648_TYPE of U0 : label is 1;
  attribute C_PROBE648_WIDTH : integer;
  attribute C_PROBE648_WIDTH of U0 : label is 1;
  attribute C_PROBE649_MU_CNT : integer;
  attribute C_PROBE649_MU_CNT of U0 : label is 1;
  attribute C_PROBE649_TYPE : integer;
  attribute C_PROBE649_TYPE of U0 : label is 1;
  attribute C_PROBE649_WIDTH : integer;
  attribute C_PROBE649_WIDTH of U0 : label is 1;
  attribute C_PROBE64_MU_CNT : integer;
  attribute C_PROBE64_MU_CNT of U0 : label is 1;
  attribute C_PROBE64_TYPE : integer;
  attribute C_PROBE64_TYPE of U0 : label is 1;
  attribute C_PROBE64_WIDTH : integer;
  attribute C_PROBE64_WIDTH of U0 : label is 1;
  attribute C_PROBE650_MU_CNT : integer;
  attribute C_PROBE650_MU_CNT of U0 : label is 1;
  attribute C_PROBE650_TYPE : integer;
  attribute C_PROBE650_TYPE of U0 : label is 1;
  attribute C_PROBE650_WIDTH : integer;
  attribute C_PROBE650_WIDTH of U0 : label is 1;
  attribute C_PROBE651_MU_CNT : integer;
  attribute C_PROBE651_MU_CNT of U0 : label is 1;
  attribute C_PROBE651_TYPE : integer;
  attribute C_PROBE651_TYPE of U0 : label is 1;
  attribute C_PROBE651_WIDTH : integer;
  attribute C_PROBE651_WIDTH of U0 : label is 1;
  attribute C_PROBE652_MU_CNT : integer;
  attribute C_PROBE652_MU_CNT of U0 : label is 1;
  attribute C_PROBE652_TYPE : integer;
  attribute C_PROBE652_TYPE of U0 : label is 1;
  attribute C_PROBE652_WIDTH : integer;
  attribute C_PROBE652_WIDTH of U0 : label is 1;
  attribute C_PROBE653_MU_CNT : integer;
  attribute C_PROBE653_MU_CNT of U0 : label is 1;
  attribute C_PROBE653_TYPE : integer;
  attribute C_PROBE653_TYPE of U0 : label is 1;
  attribute C_PROBE653_WIDTH : integer;
  attribute C_PROBE653_WIDTH of U0 : label is 1;
  attribute C_PROBE654_MU_CNT : integer;
  attribute C_PROBE654_MU_CNT of U0 : label is 1;
  attribute C_PROBE654_TYPE : integer;
  attribute C_PROBE654_TYPE of U0 : label is 1;
  attribute C_PROBE654_WIDTH : integer;
  attribute C_PROBE654_WIDTH of U0 : label is 1;
  attribute C_PROBE655_MU_CNT : integer;
  attribute C_PROBE655_MU_CNT of U0 : label is 1;
  attribute C_PROBE655_TYPE : integer;
  attribute C_PROBE655_TYPE of U0 : label is 1;
  attribute C_PROBE655_WIDTH : integer;
  attribute C_PROBE655_WIDTH of U0 : label is 1;
  attribute C_PROBE656_MU_CNT : integer;
  attribute C_PROBE656_MU_CNT of U0 : label is 1;
  attribute C_PROBE656_TYPE : integer;
  attribute C_PROBE656_TYPE of U0 : label is 1;
  attribute C_PROBE656_WIDTH : integer;
  attribute C_PROBE656_WIDTH of U0 : label is 1;
  attribute C_PROBE657_MU_CNT : integer;
  attribute C_PROBE657_MU_CNT of U0 : label is 1;
  attribute C_PROBE657_TYPE : integer;
  attribute C_PROBE657_TYPE of U0 : label is 1;
  attribute C_PROBE657_WIDTH : integer;
  attribute C_PROBE657_WIDTH of U0 : label is 1;
  attribute C_PROBE658_MU_CNT : integer;
  attribute C_PROBE658_MU_CNT of U0 : label is 1;
  attribute C_PROBE658_TYPE : integer;
  attribute C_PROBE658_TYPE of U0 : label is 1;
  attribute C_PROBE658_WIDTH : integer;
  attribute C_PROBE658_WIDTH of U0 : label is 1;
  attribute C_PROBE659_MU_CNT : integer;
  attribute C_PROBE659_MU_CNT of U0 : label is 1;
  attribute C_PROBE659_TYPE : integer;
  attribute C_PROBE659_TYPE of U0 : label is 1;
  attribute C_PROBE659_WIDTH : integer;
  attribute C_PROBE659_WIDTH of U0 : label is 1;
  attribute C_PROBE65_MU_CNT : integer;
  attribute C_PROBE65_MU_CNT of U0 : label is 1;
  attribute C_PROBE65_TYPE : integer;
  attribute C_PROBE65_TYPE of U0 : label is 1;
  attribute C_PROBE65_WIDTH : integer;
  attribute C_PROBE65_WIDTH of U0 : label is 1;
  attribute C_PROBE660_MU_CNT : integer;
  attribute C_PROBE660_MU_CNT of U0 : label is 1;
  attribute C_PROBE660_TYPE : integer;
  attribute C_PROBE660_TYPE of U0 : label is 1;
  attribute C_PROBE660_WIDTH : integer;
  attribute C_PROBE660_WIDTH of U0 : label is 1;
  attribute C_PROBE661_MU_CNT : integer;
  attribute C_PROBE661_MU_CNT of U0 : label is 1;
  attribute C_PROBE661_TYPE : integer;
  attribute C_PROBE661_TYPE of U0 : label is 1;
  attribute C_PROBE661_WIDTH : integer;
  attribute C_PROBE661_WIDTH of U0 : label is 1;
  attribute C_PROBE662_MU_CNT : integer;
  attribute C_PROBE662_MU_CNT of U0 : label is 1;
  attribute C_PROBE662_TYPE : integer;
  attribute C_PROBE662_TYPE of U0 : label is 1;
  attribute C_PROBE662_WIDTH : integer;
  attribute C_PROBE662_WIDTH of U0 : label is 1;
  attribute C_PROBE663_MU_CNT : integer;
  attribute C_PROBE663_MU_CNT of U0 : label is 1;
  attribute C_PROBE663_TYPE : integer;
  attribute C_PROBE663_TYPE of U0 : label is 1;
  attribute C_PROBE663_WIDTH : integer;
  attribute C_PROBE663_WIDTH of U0 : label is 1;
  attribute C_PROBE664_MU_CNT : integer;
  attribute C_PROBE664_MU_CNT of U0 : label is 1;
  attribute C_PROBE664_TYPE : integer;
  attribute C_PROBE664_TYPE of U0 : label is 1;
  attribute C_PROBE664_WIDTH : integer;
  attribute C_PROBE664_WIDTH of U0 : label is 1;
  attribute C_PROBE665_MU_CNT : integer;
  attribute C_PROBE665_MU_CNT of U0 : label is 1;
  attribute C_PROBE665_TYPE : integer;
  attribute C_PROBE665_TYPE of U0 : label is 1;
  attribute C_PROBE665_WIDTH : integer;
  attribute C_PROBE665_WIDTH of U0 : label is 1;
  attribute C_PROBE666_MU_CNT : integer;
  attribute C_PROBE666_MU_CNT of U0 : label is 1;
  attribute C_PROBE666_TYPE : integer;
  attribute C_PROBE666_TYPE of U0 : label is 1;
  attribute C_PROBE666_WIDTH : integer;
  attribute C_PROBE666_WIDTH of U0 : label is 1;
  attribute C_PROBE667_MU_CNT : integer;
  attribute C_PROBE667_MU_CNT of U0 : label is 1;
  attribute C_PROBE667_TYPE : integer;
  attribute C_PROBE667_TYPE of U0 : label is 1;
  attribute C_PROBE667_WIDTH : integer;
  attribute C_PROBE667_WIDTH of U0 : label is 1;
  attribute C_PROBE668_MU_CNT : integer;
  attribute C_PROBE668_MU_CNT of U0 : label is 1;
  attribute C_PROBE668_TYPE : integer;
  attribute C_PROBE668_TYPE of U0 : label is 1;
  attribute C_PROBE668_WIDTH : integer;
  attribute C_PROBE668_WIDTH of U0 : label is 1;
  attribute C_PROBE669_MU_CNT : integer;
  attribute C_PROBE669_MU_CNT of U0 : label is 1;
  attribute C_PROBE669_TYPE : integer;
  attribute C_PROBE669_TYPE of U0 : label is 1;
  attribute C_PROBE669_WIDTH : integer;
  attribute C_PROBE669_WIDTH of U0 : label is 1;
  attribute C_PROBE66_MU_CNT : integer;
  attribute C_PROBE66_MU_CNT of U0 : label is 1;
  attribute C_PROBE66_TYPE : integer;
  attribute C_PROBE66_TYPE of U0 : label is 1;
  attribute C_PROBE66_WIDTH : integer;
  attribute C_PROBE66_WIDTH of U0 : label is 1;
  attribute C_PROBE670_MU_CNT : integer;
  attribute C_PROBE670_MU_CNT of U0 : label is 1;
  attribute C_PROBE670_TYPE : integer;
  attribute C_PROBE670_TYPE of U0 : label is 1;
  attribute C_PROBE670_WIDTH : integer;
  attribute C_PROBE670_WIDTH of U0 : label is 1;
  attribute C_PROBE671_MU_CNT : integer;
  attribute C_PROBE671_MU_CNT of U0 : label is 1;
  attribute C_PROBE671_TYPE : integer;
  attribute C_PROBE671_TYPE of U0 : label is 1;
  attribute C_PROBE671_WIDTH : integer;
  attribute C_PROBE671_WIDTH of U0 : label is 1;
  attribute C_PROBE672_MU_CNT : integer;
  attribute C_PROBE672_MU_CNT of U0 : label is 1;
  attribute C_PROBE672_TYPE : integer;
  attribute C_PROBE672_TYPE of U0 : label is 1;
  attribute C_PROBE672_WIDTH : integer;
  attribute C_PROBE672_WIDTH of U0 : label is 1;
  attribute C_PROBE673_MU_CNT : integer;
  attribute C_PROBE673_MU_CNT of U0 : label is 1;
  attribute C_PROBE673_TYPE : integer;
  attribute C_PROBE673_TYPE of U0 : label is 1;
  attribute C_PROBE673_WIDTH : integer;
  attribute C_PROBE673_WIDTH of U0 : label is 1;
  attribute C_PROBE674_MU_CNT : integer;
  attribute C_PROBE674_MU_CNT of U0 : label is 1;
  attribute C_PROBE674_TYPE : integer;
  attribute C_PROBE674_TYPE of U0 : label is 1;
  attribute C_PROBE674_WIDTH : integer;
  attribute C_PROBE674_WIDTH of U0 : label is 1;
  attribute C_PROBE675_MU_CNT : integer;
  attribute C_PROBE675_MU_CNT of U0 : label is 1;
  attribute C_PROBE675_TYPE : integer;
  attribute C_PROBE675_TYPE of U0 : label is 1;
  attribute C_PROBE675_WIDTH : integer;
  attribute C_PROBE675_WIDTH of U0 : label is 1;
  attribute C_PROBE676_MU_CNT : integer;
  attribute C_PROBE676_MU_CNT of U0 : label is 1;
  attribute C_PROBE676_TYPE : integer;
  attribute C_PROBE676_TYPE of U0 : label is 1;
  attribute C_PROBE676_WIDTH : integer;
  attribute C_PROBE676_WIDTH of U0 : label is 1;
  attribute C_PROBE677_MU_CNT : integer;
  attribute C_PROBE677_MU_CNT of U0 : label is 1;
  attribute C_PROBE677_TYPE : integer;
  attribute C_PROBE677_TYPE of U0 : label is 1;
  attribute C_PROBE677_WIDTH : integer;
  attribute C_PROBE677_WIDTH of U0 : label is 1;
  attribute C_PROBE678_MU_CNT : integer;
  attribute C_PROBE678_MU_CNT of U0 : label is 1;
  attribute C_PROBE678_TYPE : integer;
  attribute C_PROBE678_TYPE of U0 : label is 1;
  attribute C_PROBE678_WIDTH : integer;
  attribute C_PROBE678_WIDTH of U0 : label is 1;
  attribute C_PROBE679_MU_CNT : integer;
  attribute C_PROBE679_MU_CNT of U0 : label is 1;
  attribute C_PROBE679_TYPE : integer;
  attribute C_PROBE679_TYPE of U0 : label is 1;
  attribute C_PROBE679_WIDTH : integer;
  attribute C_PROBE679_WIDTH of U0 : label is 1;
  attribute C_PROBE67_MU_CNT : integer;
  attribute C_PROBE67_MU_CNT of U0 : label is 1;
  attribute C_PROBE67_TYPE : integer;
  attribute C_PROBE67_TYPE of U0 : label is 1;
  attribute C_PROBE67_WIDTH : integer;
  attribute C_PROBE67_WIDTH of U0 : label is 1;
  attribute C_PROBE680_MU_CNT : integer;
  attribute C_PROBE680_MU_CNT of U0 : label is 1;
  attribute C_PROBE680_TYPE : integer;
  attribute C_PROBE680_TYPE of U0 : label is 1;
  attribute C_PROBE680_WIDTH : integer;
  attribute C_PROBE680_WIDTH of U0 : label is 1;
  attribute C_PROBE681_MU_CNT : integer;
  attribute C_PROBE681_MU_CNT of U0 : label is 1;
  attribute C_PROBE681_TYPE : integer;
  attribute C_PROBE681_TYPE of U0 : label is 1;
  attribute C_PROBE681_WIDTH : integer;
  attribute C_PROBE681_WIDTH of U0 : label is 1;
  attribute C_PROBE682_MU_CNT : integer;
  attribute C_PROBE682_MU_CNT of U0 : label is 1;
  attribute C_PROBE682_TYPE : integer;
  attribute C_PROBE682_TYPE of U0 : label is 1;
  attribute C_PROBE682_WIDTH : integer;
  attribute C_PROBE682_WIDTH of U0 : label is 1;
  attribute C_PROBE683_MU_CNT : integer;
  attribute C_PROBE683_MU_CNT of U0 : label is 1;
  attribute C_PROBE683_TYPE : integer;
  attribute C_PROBE683_TYPE of U0 : label is 1;
  attribute C_PROBE683_WIDTH : integer;
  attribute C_PROBE683_WIDTH of U0 : label is 1;
  attribute C_PROBE684_MU_CNT : integer;
  attribute C_PROBE684_MU_CNT of U0 : label is 1;
  attribute C_PROBE684_TYPE : integer;
  attribute C_PROBE684_TYPE of U0 : label is 1;
  attribute C_PROBE684_WIDTH : integer;
  attribute C_PROBE684_WIDTH of U0 : label is 1;
  attribute C_PROBE685_MU_CNT : integer;
  attribute C_PROBE685_MU_CNT of U0 : label is 1;
  attribute C_PROBE685_TYPE : integer;
  attribute C_PROBE685_TYPE of U0 : label is 1;
  attribute C_PROBE685_WIDTH : integer;
  attribute C_PROBE685_WIDTH of U0 : label is 1;
  attribute C_PROBE686_MU_CNT : integer;
  attribute C_PROBE686_MU_CNT of U0 : label is 1;
  attribute C_PROBE686_TYPE : integer;
  attribute C_PROBE686_TYPE of U0 : label is 1;
  attribute C_PROBE686_WIDTH : integer;
  attribute C_PROBE686_WIDTH of U0 : label is 1;
  attribute C_PROBE687_MU_CNT : integer;
  attribute C_PROBE687_MU_CNT of U0 : label is 1;
  attribute C_PROBE687_TYPE : integer;
  attribute C_PROBE687_TYPE of U0 : label is 1;
  attribute C_PROBE687_WIDTH : integer;
  attribute C_PROBE687_WIDTH of U0 : label is 1;
  attribute C_PROBE688_MU_CNT : integer;
  attribute C_PROBE688_MU_CNT of U0 : label is 1;
  attribute C_PROBE688_TYPE : integer;
  attribute C_PROBE688_TYPE of U0 : label is 1;
  attribute C_PROBE688_WIDTH : integer;
  attribute C_PROBE688_WIDTH of U0 : label is 1;
  attribute C_PROBE689_MU_CNT : integer;
  attribute C_PROBE689_MU_CNT of U0 : label is 1;
  attribute C_PROBE689_TYPE : integer;
  attribute C_PROBE689_TYPE of U0 : label is 1;
  attribute C_PROBE689_WIDTH : integer;
  attribute C_PROBE689_WIDTH of U0 : label is 1;
  attribute C_PROBE68_MU_CNT : integer;
  attribute C_PROBE68_MU_CNT of U0 : label is 1;
  attribute C_PROBE68_TYPE : integer;
  attribute C_PROBE68_TYPE of U0 : label is 1;
  attribute C_PROBE68_WIDTH : integer;
  attribute C_PROBE68_WIDTH of U0 : label is 1;
  attribute C_PROBE690_MU_CNT : integer;
  attribute C_PROBE690_MU_CNT of U0 : label is 1;
  attribute C_PROBE690_TYPE : integer;
  attribute C_PROBE690_TYPE of U0 : label is 1;
  attribute C_PROBE690_WIDTH : integer;
  attribute C_PROBE690_WIDTH of U0 : label is 1;
  attribute C_PROBE691_MU_CNT : integer;
  attribute C_PROBE691_MU_CNT of U0 : label is 1;
  attribute C_PROBE691_TYPE : integer;
  attribute C_PROBE691_TYPE of U0 : label is 1;
  attribute C_PROBE691_WIDTH : integer;
  attribute C_PROBE691_WIDTH of U0 : label is 1;
  attribute C_PROBE692_MU_CNT : integer;
  attribute C_PROBE692_MU_CNT of U0 : label is 1;
  attribute C_PROBE692_TYPE : integer;
  attribute C_PROBE692_TYPE of U0 : label is 1;
  attribute C_PROBE692_WIDTH : integer;
  attribute C_PROBE692_WIDTH of U0 : label is 1;
  attribute C_PROBE693_MU_CNT : integer;
  attribute C_PROBE693_MU_CNT of U0 : label is 1;
  attribute C_PROBE693_TYPE : integer;
  attribute C_PROBE693_TYPE of U0 : label is 1;
  attribute C_PROBE693_WIDTH : integer;
  attribute C_PROBE693_WIDTH of U0 : label is 1;
  attribute C_PROBE694_MU_CNT : integer;
  attribute C_PROBE694_MU_CNT of U0 : label is 1;
  attribute C_PROBE694_TYPE : integer;
  attribute C_PROBE694_TYPE of U0 : label is 1;
  attribute C_PROBE694_WIDTH : integer;
  attribute C_PROBE694_WIDTH of U0 : label is 1;
  attribute C_PROBE695_MU_CNT : integer;
  attribute C_PROBE695_MU_CNT of U0 : label is 1;
  attribute C_PROBE695_TYPE : integer;
  attribute C_PROBE695_TYPE of U0 : label is 1;
  attribute C_PROBE695_WIDTH : integer;
  attribute C_PROBE695_WIDTH of U0 : label is 1;
  attribute C_PROBE696_MU_CNT : integer;
  attribute C_PROBE696_MU_CNT of U0 : label is 1;
  attribute C_PROBE696_TYPE : integer;
  attribute C_PROBE696_TYPE of U0 : label is 1;
  attribute C_PROBE696_WIDTH : integer;
  attribute C_PROBE696_WIDTH of U0 : label is 1;
  attribute C_PROBE697_MU_CNT : integer;
  attribute C_PROBE697_MU_CNT of U0 : label is 1;
  attribute C_PROBE697_TYPE : integer;
  attribute C_PROBE697_TYPE of U0 : label is 1;
  attribute C_PROBE697_WIDTH : integer;
  attribute C_PROBE697_WIDTH of U0 : label is 1;
  attribute C_PROBE698_MU_CNT : integer;
  attribute C_PROBE698_MU_CNT of U0 : label is 1;
  attribute C_PROBE698_TYPE : integer;
  attribute C_PROBE698_TYPE of U0 : label is 1;
  attribute C_PROBE698_WIDTH : integer;
  attribute C_PROBE698_WIDTH of U0 : label is 1;
  attribute C_PROBE699_MU_CNT : integer;
  attribute C_PROBE699_MU_CNT of U0 : label is 1;
  attribute C_PROBE699_TYPE : integer;
  attribute C_PROBE699_TYPE of U0 : label is 1;
  attribute C_PROBE699_WIDTH : integer;
  attribute C_PROBE699_WIDTH of U0 : label is 1;
  attribute C_PROBE69_MU_CNT : integer;
  attribute C_PROBE69_MU_CNT of U0 : label is 1;
  attribute C_PROBE69_TYPE : integer;
  attribute C_PROBE69_TYPE of U0 : label is 1;
  attribute C_PROBE69_WIDTH : integer;
  attribute C_PROBE69_WIDTH of U0 : label is 1;
  attribute C_PROBE6_MU_CNT : integer;
  attribute C_PROBE6_MU_CNT of U0 : label is 1;
  attribute C_PROBE6_TYPE : integer;
  attribute C_PROBE6_TYPE of U0 : label is 1;
  attribute C_PROBE6_WIDTH : integer;
  attribute C_PROBE6_WIDTH of U0 : label is 1;
  attribute C_PROBE700_MU_CNT : integer;
  attribute C_PROBE700_MU_CNT of U0 : label is 1;
  attribute C_PROBE700_TYPE : integer;
  attribute C_PROBE700_TYPE of U0 : label is 1;
  attribute C_PROBE700_WIDTH : integer;
  attribute C_PROBE700_WIDTH of U0 : label is 1;
  attribute C_PROBE701_MU_CNT : integer;
  attribute C_PROBE701_MU_CNT of U0 : label is 1;
  attribute C_PROBE701_TYPE : integer;
  attribute C_PROBE701_TYPE of U0 : label is 1;
  attribute C_PROBE701_WIDTH : integer;
  attribute C_PROBE701_WIDTH of U0 : label is 1;
  attribute C_PROBE702_MU_CNT : integer;
  attribute C_PROBE702_MU_CNT of U0 : label is 1;
  attribute C_PROBE702_TYPE : integer;
  attribute C_PROBE702_TYPE of U0 : label is 1;
  attribute C_PROBE702_WIDTH : integer;
  attribute C_PROBE702_WIDTH of U0 : label is 1;
  attribute C_PROBE703_MU_CNT : integer;
  attribute C_PROBE703_MU_CNT of U0 : label is 1;
  attribute C_PROBE703_TYPE : integer;
  attribute C_PROBE703_TYPE of U0 : label is 1;
  attribute C_PROBE703_WIDTH : integer;
  attribute C_PROBE703_WIDTH of U0 : label is 1;
  attribute C_PROBE704_MU_CNT : integer;
  attribute C_PROBE704_MU_CNT of U0 : label is 1;
  attribute C_PROBE704_TYPE : integer;
  attribute C_PROBE704_TYPE of U0 : label is 1;
  attribute C_PROBE704_WIDTH : integer;
  attribute C_PROBE704_WIDTH of U0 : label is 1;
  attribute C_PROBE705_MU_CNT : integer;
  attribute C_PROBE705_MU_CNT of U0 : label is 1;
  attribute C_PROBE705_TYPE : integer;
  attribute C_PROBE705_TYPE of U0 : label is 1;
  attribute C_PROBE705_WIDTH : integer;
  attribute C_PROBE705_WIDTH of U0 : label is 1;
  attribute C_PROBE706_MU_CNT : integer;
  attribute C_PROBE706_MU_CNT of U0 : label is 1;
  attribute C_PROBE706_TYPE : integer;
  attribute C_PROBE706_TYPE of U0 : label is 1;
  attribute C_PROBE706_WIDTH : integer;
  attribute C_PROBE706_WIDTH of U0 : label is 1;
  attribute C_PROBE707_MU_CNT : integer;
  attribute C_PROBE707_MU_CNT of U0 : label is 1;
  attribute C_PROBE707_TYPE : integer;
  attribute C_PROBE707_TYPE of U0 : label is 1;
  attribute C_PROBE707_WIDTH : integer;
  attribute C_PROBE707_WIDTH of U0 : label is 1;
  attribute C_PROBE708_MU_CNT : integer;
  attribute C_PROBE708_MU_CNT of U0 : label is 1;
  attribute C_PROBE708_TYPE : integer;
  attribute C_PROBE708_TYPE of U0 : label is 1;
  attribute C_PROBE708_WIDTH : integer;
  attribute C_PROBE708_WIDTH of U0 : label is 1;
  attribute C_PROBE709_MU_CNT : integer;
  attribute C_PROBE709_MU_CNT of U0 : label is 1;
  attribute C_PROBE709_TYPE : integer;
  attribute C_PROBE709_TYPE of U0 : label is 1;
  attribute C_PROBE709_WIDTH : integer;
  attribute C_PROBE709_WIDTH of U0 : label is 1;
  attribute C_PROBE70_MU_CNT : integer;
  attribute C_PROBE70_MU_CNT of U0 : label is 1;
  attribute C_PROBE70_TYPE : integer;
  attribute C_PROBE70_TYPE of U0 : label is 1;
  attribute C_PROBE70_WIDTH : integer;
  attribute C_PROBE70_WIDTH of U0 : label is 1;
  attribute C_PROBE710_MU_CNT : integer;
  attribute C_PROBE710_MU_CNT of U0 : label is 1;
  attribute C_PROBE710_TYPE : integer;
  attribute C_PROBE710_TYPE of U0 : label is 1;
  attribute C_PROBE710_WIDTH : integer;
  attribute C_PROBE710_WIDTH of U0 : label is 1;
  attribute C_PROBE711_MU_CNT : integer;
  attribute C_PROBE711_MU_CNT of U0 : label is 1;
  attribute C_PROBE711_TYPE : integer;
  attribute C_PROBE711_TYPE of U0 : label is 1;
  attribute C_PROBE711_WIDTH : integer;
  attribute C_PROBE711_WIDTH of U0 : label is 1;
  attribute C_PROBE712_MU_CNT : integer;
  attribute C_PROBE712_MU_CNT of U0 : label is 1;
  attribute C_PROBE712_TYPE : integer;
  attribute C_PROBE712_TYPE of U0 : label is 1;
  attribute C_PROBE712_WIDTH : integer;
  attribute C_PROBE712_WIDTH of U0 : label is 1;
  attribute C_PROBE713_MU_CNT : integer;
  attribute C_PROBE713_MU_CNT of U0 : label is 1;
  attribute C_PROBE713_TYPE : integer;
  attribute C_PROBE713_TYPE of U0 : label is 1;
  attribute C_PROBE713_WIDTH : integer;
  attribute C_PROBE713_WIDTH of U0 : label is 1;
  attribute C_PROBE714_MU_CNT : integer;
  attribute C_PROBE714_MU_CNT of U0 : label is 1;
  attribute C_PROBE714_TYPE : integer;
  attribute C_PROBE714_TYPE of U0 : label is 1;
  attribute C_PROBE714_WIDTH : integer;
  attribute C_PROBE714_WIDTH of U0 : label is 1;
  attribute C_PROBE715_MU_CNT : integer;
  attribute C_PROBE715_MU_CNT of U0 : label is 1;
  attribute C_PROBE715_TYPE : integer;
  attribute C_PROBE715_TYPE of U0 : label is 1;
  attribute C_PROBE715_WIDTH : integer;
  attribute C_PROBE715_WIDTH of U0 : label is 1;
  attribute C_PROBE716_MU_CNT : integer;
  attribute C_PROBE716_MU_CNT of U0 : label is 1;
  attribute C_PROBE716_TYPE : integer;
  attribute C_PROBE716_TYPE of U0 : label is 1;
  attribute C_PROBE716_WIDTH : integer;
  attribute C_PROBE716_WIDTH of U0 : label is 1;
  attribute C_PROBE717_MU_CNT : integer;
  attribute C_PROBE717_MU_CNT of U0 : label is 1;
  attribute C_PROBE717_TYPE : integer;
  attribute C_PROBE717_TYPE of U0 : label is 1;
  attribute C_PROBE717_WIDTH : integer;
  attribute C_PROBE717_WIDTH of U0 : label is 1;
  attribute C_PROBE718_MU_CNT : integer;
  attribute C_PROBE718_MU_CNT of U0 : label is 1;
  attribute C_PROBE718_TYPE : integer;
  attribute C_PROBE718_TYPE of U0 : label is 1;
  attribute C_PROBE718_WIDTH : integer;
  attribute C_PROBE718_WIDTH of U0 : label is 1;
  attribute C_PROBE719_MU_CNT : integer;
  attribute C_PROBE719_MU_CNT of U0 : label is 1;
  attribute C_PROBE719_TYPE : integer;
  attribute C_PROBE719_TYPE of U0 : label is 1;
  attribute C_PROBE719_WIDTH : integer;
  attribute C_PROBE719_WIDTH of U0 : label is 1;
  attribute C_PROBE71_MU_CNT : integer;
  attribute C_PROBE71_MU_CNT of U0 : label is 1;
  attribute C_PROBE71_TYPE : integer;
  attribute C_PROBE71_TYPE of U0 : label is 1;
  attribute C_PROBE71_WIDTH : integer;
  attribute C_PROBE71_WIDTH of U0 : label is 1;
  attribute C_PROBE720_MU_CNT : integer;
  attribute C_PROBE720_MU_CNT of U0 : label is 1;
  attribute C_PROBE720_TYPE : integer;
  attribute C_PROBE720_TYPE of U0 : label is 1;
  attribute C_PROBE720_WIDTH : integer;
  attribute C_PROBE720_WIDTH of U0 : label is 1;
  attribute C_PROBE721_MU_CNT : integer;
  attribute C_PROBE721_MU_CNT of U0 : label is 1;
  attribute C_PROBE721_TYPE : integer;
  attribute C_PROBE721_TYPE of U0 : label is 1;
  attribute C_PROBE721_WIDTH : integer;
  attribute C_PROBE721_WIDTH of U0 : label is 1;
  attribute C_PROBE722_MU_CNT : integer;
  attribute C_PROBE722_MU_CNT of U0 : label is 1;
  attribute C_PROBE722_TYPE : integer;
  attribute C_PROBE722_TYPE of U0 : label is 1;
  attribute C_PROBE722_WIDTH : integer;
  attribute C_PROBE722_WIDTH of U0 : label is 1;
  attribute C_PROBE723_MU_CNT : integer;
  attribute C_PROBE723_MU_CNT of U0 : label is 1;
  attribute C_PROBE723_TYPE : integer;
  attribute C_PROBE723_TYPE of U0 : label is 1;
  attribute C_PROBE723_WIDTH : integer;
  attribute C_PROBE723_WIDTH of U0 : label is 1;
  attribute C_PROBE724_MU_CNT : integer;
  attribute C_PROBE724_MU_CNT of U0 : label is 1;
  attribute C_PROBE724_TYPE : integer;
  attribute C_PROBE724_TYPE of U0 : label is 1;
  attribute C_PROBE724_WIDTH : integer;
  attribute C_PROBE724_WIDTH of U0 : label is 1;
  attribute C_PROBE725_MU_CNT : integer;
  attribute C_PROBE725_MU_CNT of U0 : label is 1;
  attribute C_PROBE725_TYPE : integer;
  attribute C_PROBE725_TYPE of U0 : label is 1;
  attribute C_PROBE725_WIDTH : integer;
  attribute C_PROBE725_WIDTH of U0 : label is 1;
  attribute C_PROBE726_MU_CNT : integer;
  attribute C_PROBE726_MU_CNT of U0 : label is 1;
  attribute C_PROBE726_TYPE : integer;
  attribute C_PROBE726_TYPE of U0 : label is 1;
  attribute C_PROBE726_WIDTH : integer;
  attribute C_PROBE726_WIDTH of U0 : label is 1;
  attribute C_PROBE727_MU_CNT : integer;
  attribute C_PROBE727_MU_CNT of U0 : label is 1;
  attribute C_PROBE727_TYPE : integer;
  attribute C_PROBE727_TYPE of U0 : label is 1;
  attribute C_PROBE727_WIDTH : integer;
  attribute C_PROBE727_WIDTH of U0 : label is 1;
  attribute C_PROBE728_MU_CNT : integer;
  attribute C_PROBE728_MU_CNT of U0 : label is 1;
  attribute C_PROBE728_TYPE : integer;
  attribute C_PROBE728_TYPE of U0 : label is 1;
  attribute C_PROBE728_WIDTH : integer;
  attribute C_PROBE728_WIDTH of U0 : label is 1;
  attribute C_PROBE729_MU_CNT : integer;
  attribute C_PROBE729_MU_CNT of U0 : label is 1;
  attribute C_PROBE729_TYPE : integer;
  attribute C_PROBE729_TYPE of U0 : label is 1;
  attribute C_PROBE729_WIDTH : integer;
  attribute C_PROBE729_WIDTH of U0 : label is 1;
  attribute C_PROBE72_MU_CNT : integer;
  attribute C_PROBE72_MU_CNT of U0 : label is 1;
  attribute C_PROBE72_TYPE : integer;
  attribute C_PROBE72_TYPE of U0 : label is 1;
  attribute C_PROBE72_WIDTH : integer;
  attribute C_PROBE72_WIDTH of U0 : label is 1;
  attribute C_PROBE730_MU_CNT : integer;
  attribute C_PROBE730_MU_CNT of U0 : label is 1;
  attribute C_PROBE730_TYPE : integer;
  attribute C_PROBE730_TYPE of U0 : label is 1;
  attribute C_PROBE730_WIDTH : integer;
  attribute C_PROBE730_WIDTH of U0 : label is 1;
  attribute C_PROBE731_MU_CNT : integer;
  attribute C_PROBE731_MU_CNT of U0 : label is 1;
  attribute C_PROBE731_TYPE : integer;
  attribute C_PROBE731_TYPE of U0 : label is 1;
  attribute C_PROBE731_WIDTH : integer;
  attribute C_PROBE731_WIDTH of U0 : label is 1;
  attribute C_PROBE732_MU_CNT : integer;
  attribute C_PROBE732_MU_CNT of U0 : label is 1;
  attribute C_PROBE732_TYPE : integer;
  attribute C_PROBE732_TYPE of U0 : label is 1;
  attribute C_PROBE732_WIDTH : integer;
  attribute C_PROBE732_WIDTH of U0 : label is 1;
  attribute C_PROBE733_MU_CNT : integer;
  attribute C_PROBE733_MU_CNT of U0 : label is 1;
  attribute C_PROBE733_TYPE : integer;
  attribute C_PROBE733_TYPE of U0 : label is 1;
  attribute C_PROBE733_WIDTH : integer;
  attribute C_PROBE733_WIDTH of U0 : label is 1;
  attribute C_PROBE734_MU_CNT : integer;
  attribute C_PROBE734_MU_CNT of U0 : label is 1;
  attribute C_PROBE734_TYPE : integer;
  attribute C_PROBE734_TYPE of U0 : label is 1;
  attribute C_PROBE734_WIDTH : integer;
  attribute C_PROBE734_WIDTH of U0 : label is 1;
  attribute C_PROBE735_MU_CNT : integer;
  attribute C_PROBE735_MU_CNT of U0 : label is 1;
  attribute C_PROBE735_TYPE : integer;
  attribute C_PROBE735_TYPE of U0 : label is 1;
  attribute C_PROBE735_WIDTH : integer;
  attribute C_PROBE735_WIDTH of U0 : label is 1;
  attribute C_PROBE736_MU_CNT : integer;
  attribute C_PROBE736_MU_CNT of U0 : label is 1;
  attribute C_PROBE736_TYPE : integer;
  attribute C_PROBE736_TYPE of U0 : label is 1;
  attribute C_PROBE736_WIDTH : integer;
  attribute C_PROBE736_WIDTH of U0 : label is 1;
  attribute C_PROBE737_MU_CNT : integer;
  attribute C_PROBE737_MU_CNT of U0 : label is 1;
  attribute C_PROBE737_TYPE : integer;
  attribute C_PROBE737_TYPE of U0 : label is 1;
  attribute C_PROBE737_WIDTH : integer;
  attribute C_PROBE737_WIDTH of U0 : label is 1;
  attribute C_PROBE738_MU_CNT : integer;
  attribute C_PROBE738_MU_CNT of U0 : label is 1;
  attribute C_PROBE738_TYPE : integer;
  attribute C_PROBE738_TYPE of U0 : label is 1;
  attribute C_PROBE738_WIDTH : integer;
  attribute C_PROBE738_WIDTH of U0 : label is 1;
  attribute C_PROBE739_MU_CNT : integer;
  attribute C_PROBE739_MU_CNT of U0 : label is 1;
  attribute C_PROBE739_TYPE : integer;
  attribute C_PROBE739_TYPE of U0 : label is 1;
  attribute C_PROBE739_WIDTH : integer;
  attribute C_PROBE739_WIDTH of U0 : label is 1;
  attribute C_PROBE73_MU_CNT : integer;
  attribute C_PROBE73_MU_CNT of U0 : label is 1;
  attribute C_PROBE73_TYPE : integer;
  attribute C_PROBE73_TYPE of U0 : label is 1;
  attribute C_PROBE73_WIDTH : integer;
  attribute C_PROBE73_WIDTH of U0 : label is 1;
  attribute C_PROBE740_MU_CNT : integer;
  attribute C_PROBE740_MU_CNT of U0 : label is 1;
  attribute C_PROBE740_TYPE : integer;
  attribute C_PROBE740_TYPE of U0 : label is 1;
  attribute C_PROBE740_WIDTH : integer;
  attribute C_PROBE740_WIDTH of U0 : label is 1;
  attribute C_PROBE741_MU_CNT : integer;
  attribute C_PROBE741_MU_CNT of U0 : label is 1;
  attribute C_PROBE741_TYPE : integer;
  attribute C_PROBE741_TYPE of U0 : label is 1;
  attribute C_PROBE741_WIDTH : integer;
  attribute C_PROBE741_WIDTH of U0 : label is 1;
  attribute C_PROBE742_MU_CNT : integer;
  attribute C_PROBE742_MU_CNT of U0 : label is 1;
  attribute C_PROBE742_TYPE : integer;
  attribute C_PROBE742_TYPE of U0 : label is 1;
  attribute C_PROBE742_WIDTH : integer;
  attribute C_PROBE742_WIDTH of U0 : label is 1;
  attribute C_PROBE743_MU_CNT : integer;
  attribute C_PROBE743_MU_CNT of U0 : label is 1;
  attribute C_PROBE743_TYPE : integer;
  attribute C_PROBE743_TYPE of U0 : label is 1;
  attribute C_PROBE743_WIDTH : integer;
  attribute C_PROBE743_WIDTH of U0 : label is 1;
  attribute C_PROBE744_MU_CNT : integer;
  attribute C_PROBE744_MU_CNT of U0 : label is 1;
  attribute C_PROBE744_TYPE : integer;
  attribute C_PROBE744_TYPE of U0 : label is 1;
  attribute C_PROBE744_WIDTH : integer;
  attribute C_PROBE744_WIDTH of U0 : label is 1;
  attribute C_PROBE745_MU_CNT : integer;
  attribute C_PROBE745_MU_CNT of U0 : label is 1;
  attribute C_PROBE745_TYPE : integer;
  attribute C_PROBE745_TYPE of U0 : label is 1;
  attribute C_PROBE745_WIDTH : integer;
  attribute C_PROBE745_WIDTH of U0 : label is 1;
  attribute C_PROBE746_MU_CNT : integer;
  attribute C_PROBE746_MU_CNT of U0 : label is 1;
  attribute C_PROBE746_TYPE : integer;
  attribute C_PROBE746_TYPE of U0 : label is 1;
  attribute C_PROBE746_WIDTH : integer;
  attribute C_PROBE746_WIDTH of U0 : label is 1;
  attribute C_PROBE747_MU_CNT : integer;
  attribute C_PROBE747_MU_CNT of U0 : label is 1;
  attribute C_PROBE747_TYPE : integer;
  attribute C_PROBE747_TYPE of U0 : label is 1;
  attribute C_PROBE747_WIDTH : integer;
  attribute C_PROBE747_WIDTH of U0 : label is 1;
  attribute C_PROBE748_MU_CNT : integer;
  attribute C_PROBE748_MU_CNT of U0 : label is 1;
  attribute C_PROBE748_TYPE : integer;
  attribute C_PROBE748_TYPE of U0 : label is 1;
  attribute C_PROBE748_WIDTH : integer;
  attribute C_PROBE748_WIDTH of U0 : label is 1;
  attribute C_PROBE749_MU_CNT : integer;
  attribute C_PROBE749_MU_CNT of U0 : label is 1;
  attribute C_PROBE749_TYPE : integer;
  attribute C_PROBE749_TYPE of U0 : label is 1;
  attribute C_PROBE749_WIDTH : integer;
  attribute C_PROBE749_WIDTH of U0 : label is 1;
  attribute C_PROBE74_MU_CNT : integer;
  attribute C_PROBE74_MU_CNT of U0 : label is 1;
  attribute C_PROBE74_TYPE : integer;
  attribute C_PROBE74_TYPE of U0 : label is 1;
  attribute C_PROBE74_WIDTH : integer;
  attribute C_PROBE74_WIDTH of U0 : label is 1;
  attribute C_PROBE750_MU_CNT : integer;
  attribute C_PROBE750_MU_CNT of U0 : label is 1;
  attribute C_PROBE750_TYPE : integer;
  attribute C_PROBE750_TYPE of U0 : label is 1;
  attribute C_PROBE750_WIDTH : integer;
  attribute C_PROBE750_WIDTH of U0 : label is 1;
  attribute C_PROBE751_MU_CNT : integer;
  attribute C_PROBE751_MU_CNT of U0 : label is 1;
  attribute C_PROBE751_TYPE : integer;
  attribute C_PROBE751_TYPE of U0 : label is 1;
  attribute C_PROBE751_WIDTH : integer;
  attribute C_PROBE751_WIDTH of U0 : label is 1;
  attribute C_PROBE752_MU_CNT : integer;
  attribute C_PROBE752_MU_CNT of U0 : label is 1;
  attribute C_PROBE752_TYPE : integer;
  attribute C_PROBE752_TYPE of U0 : label is 1;
  attribute C_PROBE752_WIDTH : integer;
  attribute C_PROBE752_WIDTH of U0 : label is 1;
  attribute C_PROBE753_MU_CNT : integer;
  attribute C_PROBE753_MU_CNT of U0 : label is 1;
  attribute C_PROBE753_TYPE : integer;
  attribute C_PROBE753_TYPE of U0 : label is 1;
  attribute C_PROBE753_WIDTH : integer;
  attribute C_PROBE753_WIDTH of U0 : label is 1;
  attribute C_PROBE754_MU_CNT : integer;
  attribute C_PROBE754_MU_CNT of U0 : label is 1;
  attribute C_PROBE754_TYPE : integer;
  attribute C_PROBE754_TYPE of U0 : label is 1;
  attribute C_PROBE754_WIDTH : integer;
  attribute C_PROBE754_WIDTH of U0 : label is 1;
  attribute C_PROBE755_MU_CNT : integer;
  attribute C_PROBE755_MU_CNT of U0 : label is 1;
  attribute C_PROBE755_TYPE : integer;
  attribute C_PROBE755_TYPE of U0 : label is 1;
  attribute C_PROBE755_WIDTH : integer;
  attribute C_PROBE755_WIDTH of U0 : label is 1;
  attribute C_PROBE756_MU_CNT : integer;
  attribute C_PROBE756_MU_CNT of U0 : label is 1;
  attribute C_PROBE756_TYPE : integer;
  attribute C_PROBE756_TYPE of U0 : label is 1;
  attribute C_PROBE756_WIDTH : integer;
  attribute C_PROBE756_WIDTH of U0 : label is 1;
  attribute C_PROBE757_MU_CNT : integer;
  attribute C_PROBE757_MU_CNT of U0 : label is 1;
  attribute C_PROBE757_TYPE : integer;
  attribute C_PROBE757_TYPE of U0 : label is 1;
  attribute C_PROBE757_WIDTH : integer;
  attribute C_PROBE757_WIDTH of U0 : label is 1;
  attribute C_PROBE758_MU_CNT : integer;
  attribute C_PROBE758_MU_CNT of U0 : label is 1;
  attribute C_PROBE758_TYPE : integer;
  attribute C_PROBE758_TYPE of U0 : label is 1;
  attribute C_PROBE758_WIDTH : integer;
  attribute C_PROBE758_WIDTH of U0 : label is 1;
  attribute C_PROBE759_MU_CNT : integer;
  attribute C_PROBE759_MU_CNT of U0 : label is 1;
  attribute C_PROBE759_TYPE : integer;
  attribute C_PROBE759_TYPE of U0 : label is 1;
  attribute C_PROBE759_WIDTH : integer;
  attribute C_PROBE759_WIDTH of U0 : label is 1;
  attribute C_PROBE75_MU_CNT : integer;
  attribute C_PROBE75_MU_CNT of U0 : label is 1;
  attribute C_PROBE75_TYPE : integer;
  attribute C_PROBE75_TYPE of U0 : label is 1;
  attribute C_PROBE75_WIDTH : integer;
  attribute C_PROBE75_WIDTH of U0 : label is 1;
  attribute C_PROBE760_MU_CNT : integer;
  attribute C_PROBE760_MU_CNT of U0 : label is 1;
  attribute C_PROBE760_TYPE : integer;
  attribute C_PROBE760_TYPE of U0 : label is 1;
  attribute C_PROBE760_WIDTH : integer;
  attribute C_PROBE760_WIDTH of U0 : label is 1;
  attribute C_PROBE761_MU_CNT : integer;
  attribute C_PROBE761_MU_CNT of U0 : label is 1;
  attribute C_PROBE761_TYPE : integer;
  attribute C_PROBE761_TYPE of U0 : label is 1;
  attribute C_PROBE761_WIDTH : integer;
  attribute C_PROBE761_WIDTH of U0 : label is 1;
  attribute C_PROBE762_MU_CNT : integer;
  attribute C_PROBE762_MU_CNT of U0 : label is 1;
  attribute C_PROBE762_TYPE : integer;
  attribute C_PROBE762_TYPE of U0 : label is 1;
  attribute C_PROBE762_WIDTH : integer;
  attribute C_PROBE762_WIDTH of U0 : label is 1;
  attribute C_PROBE763_MU_CNT : integer;
  attribute C_PROBE763_MU_CNT of U0 : label is 1;
  attribute C_PROBE763_TYPE : integer;
  attribute C_PROBE763_TYPE of U0 : label is 1;
  attribute C_PROBE763_WIDTH : integer;
  attribute C_PROBE763_WIDTH of U0 : label is 1;
  attribute C_PROBE764_MU_CNT : integer;
  attribute C_PROBE764_MU_CNT of U0 : label is 1;
  attribute C_PROBE764_TYPE : integer;
  attribute C_PROBE764_TYPE of U0 : label is 1;
  attribute C_PROBE764_WIDTH : integer;
  attribute C_PROBE764_WIDTH of U0 : label is 1;
  attribute C_PROBE765_MU_CNT : integer;
  attribute C_PROBE765_MU_CNT of U0 : label is 1;
  attribute C_PROBE765_TYPE : integer;
  attribute C_PROBE765_TYPE of U0 : label is 1;
  attribute C_PROBE765_WIDTH : integer;
  attribute C_PROBE765_WIDTH of U0 : label is 1;
  attribute C_PROBE766_MU_CNT : integer;
  attribute C_PROBE766_MU_CNT of U0 : label is 1;
  attribute C_PROBE766_TYPE : integer;
  attribute C_PROBE766_TYPE of U0 : label is 1;
  attribute C_PROBE766_WIDTH : integer;
  attribute C_PROBE766_WIDTH of U0 : label is 1;
  attribute C_PROBE767_MU_CNT : integer;
  attribute C_PROBE767_MU_CNT of U0 : label is 1;
  attribute C_PROBE767_TYPE : integer;
  attribute C_PROBE767_TYPE of U0 : label is 1;
  attribute C_PROBE767_WIDTH : integer;
  attribute C_PROBE767_WIDTH of U0 : label is 1;
  attribute C_PROBE768_MU_CNT : integer;
  attribute C_PROBE768_MU_CNT of U0 : label is 1;
  attribute C_PROBE768_TYPE : integer;
  attribute C_PROBE768_TYPE of U0 : label is 1;
  attribute C_PROBE768_WIDTH : integer;
  attribute C_PROBE768_WIDTH of U0 : label is 1;
  attribute C_PROBE769_MU_CNT : integer;
  attribute C_PROBE769_MU_CNT of U0 : label is 1;
  attribute C_PROBE769_TYPE : integer;
  attribute C_PROBE769_TYPE of U0 : label is 1;
  attribute C_PROBE769_WIDTH : integer;
  attribute C_PROBE769_WIDTH of U0 : label is 1;
  attribute C_PROBE76_MU_CNT : integer;
  attribute C_PROBE76_MU_CNT of U0 : label is 1;
  attribute C_PROBE76_TYPE : integer;
  attribute C_PROBE76_TYPE of U0 : label is 1;
  attribute C_PROBE76_WIDTH : integer;
  attribute C_PROBE76_WIDTH of U0 : label is 1;
  attribute C_PROBE770_MU_CNT : integer;
  attribute C_PROBE770_MU_CNT of U0 : label is 1;
  attribute C_PROBE770_TYPE : integer;
  attribute C_PROBE770_TYPE of U0 : label is 1;
  attribute C_PROBE770_WIDTH : integer;
  attribute C_PROBE770_WIDTH of U0 : label is 1;
  attribute C_PROBE771_MU_CNT : integer;
  attribute C_PROBE771_MU_CNT of U0 : label is 1;
  attribute C_PROBE771_TYPE : integer;
  attribute C_PROBE771_TYPE of U0 : label is 1;
  attribute C_PROBE771_WIDTH : integer;
  attribute C_PROBE771_WIDTH of U0 : label is 1;
  attribute C_PROBE772_MU_CNT : integer;
  attribute C_PROBE772_MU_CNT of U0 : label is 1;
  attribute C_PROBE772_TYPE : integer;
  attribute C_PROBE772_TYPE of U0 : label is 1;
  attribute C_PROBE772_WIDTH : integer;
  attribute C_PROBE772_WIDTH of U0 : label is 1;
  attribute C_PROBE773_MU_CNT : integer;
  attribute C_PROBE773_MU_CNT of U0 : label is 1;
  attribute C_PROBE773_TYPE : integer;
  attribute C_PROBE773_TYPE of U0 : label is 1;
  attribute C_PROBE773_WIDTH : integer;
  attribute C_PROBE773_WIDTH of U0 : label is 1;
  attribute C_PROBE774_MU_CNT : integer;
  attribute C_PROBE774_MU_CNT of U0 : label is 1;
  attribute C_PROBE774_TYPE : integer;
  attribute C_PROBE774_TYPE of U0 : label is 1;
  attribute C_PROBE774_WIDTH : integer;
  attribute C_PROBE774_WIDTH of U0 : label is 1;
  attribute C_PROBE775_MU_CNT : integer;
  attribute C_PROBE775_MU_CNT of U0 : label is 1;
  attribute C_PROBE775_TYPE : integer;
  attribute C_PROBE775_TYPE of U0 : label is 1;
  attribute C_PROBE775_WIDTH : integer;
  attribute C_PROBE775_WIDTH of U0 : label is 1;
  attribute C_PROBE776_MU_CNT : integer;
  attribute C_PROBE776_MU_CNT of U0 : label is 1;
  attribute C_PROBE776_TYPE : integer;
  attribute C_PROBE776_TYPE of U0 : label is 1;
  attribute C_PROBE776_WIDTH : integer;
  attribute C_PROBE776_WIDTH of U0 : label is 1;
  attribute C_PROBE777_MU_CNT : integer;
  attribute C_PROBE777_MU_CNT of U0 : label is 1;
  attribute C_PROBE777_TYPE : integer;
  attribute C_PROBE777_TYPE of U0 : label is 1;
  attribute C_PROBE777_WIDTH : integer;
  attribute C_PROBE777_WIDTH of U0 : label is 1;
  attribute C_PROBE778_MU_CNT : integer;
  attribute C_PROBE778_MU_CNT of U0 : label is 1;
  attribute C_PROBE778_TYPE : integer;
  attribute C_PROBE778_TYPE of U0 : label is 1;
  attribute C_PROBE778_WIDTH : integer;
  attribute C_PROBE778_WIDTH of U0 : label is 1;
  attribute C_PROBE779_MU_CNT : integer;
  attribute C_PROBE779_MU_CNT of U0 : label is 1;
  attribute C_PROBE779_TYPE : integer;
  attribute C_PROBE779_TYPE of U0 : label is 1;
  attribute C_PROBE779_WIDTH : integer;
  attribute C_PROBE779_WIDTH of U0 : label is 1;
  attribute C_PROBE77_MU_CNT : integer;
  attribute C_PROBE77_MU_CNT of U0 : label is 1;
  attribute C_PROBE77_TYPE : integer;
  attribute C_PROBE77_TYPE of U0 : label is 1;
  attribute C_PROBE77_WIDTH : integer;
  attribute C_PROBE77_WIDTH of U0 : label is 1;
  attribute C_PROBE780_MU_CNT : integer;
  attribute C_PROBE780_MU_CNT of U0 : label is 1;
  attribute C_PROBE780_TYPE : integer;
  attribute C_PROBE780_TYPE of U0 : label is 1;
  attribute C_PROBE780_WIDTH : integer;
  attribute C_PROBE780_WIDTH of U0 : label is 1;
  attribute C_PROBE781_MU_CNT : integer;
  attribute C_PROBE781_MU_CNT of U0 : label is 1;
  attribute C_PROBE781_TYPE : integer;
  attribute C_PROBE781_TYPE of U0 : label is 1;
  attribute C_PROBE781_WIDTH : integer;
  attribute C_PROBE781_WIDTH of U0 : label is 1;
  attribute C_PROBE782_MU_CNT : integer;
  attribute C_PROBE782_MU_CNT of U0 : label is 1;
  attribute C_PROBE782_TYPE : integer;
  attribute C_PROBE782_TYPE of U0 : label is 1;
  attribute C_PROBE782_WIDTH : integer;
  attribute C_PROBE782_WIDTH of U0 : label is 1;
  attribute C_PROBE783_MU_CNT : integer;
  attribute C_PROBE783_MU_CNT of U0 : label is 1;
  attribute C_PROBE783_TYPE : integer;
  attribute C_PROBE783_TYPE of U0 : label is 1;
  attribute C_PROBE783_WIDTH : integer;
  attribute C_PROBE783_WIDTH of U0 : label is 1;
  attribute C_PROBE784_MU_CNT : integer;
  attribute C_PROBE784_MU_CNT of U0 : label is 1;
  attribute C_PROBE784_TYPE : integer;
  attribute C_PROBE784_TYPE of U0 : label is 1;
  attribute C_PROBE784_WIDTH : integer;
  attribute C_PROBE784_WIDTH of U0 : label is 1;
  attribute C_PROBE785_MU_CNT : integer;
  attribute C_PROBE785_MU_CNT of U0 : label is 1;
  attribute C_PROBE785_TYPE : integer;
  attribute C_PROBE785_TYPE of U0 : label is 1;
  attribute C_PROBE785_WIDTH : integer;
  attribute C_PROBE785_WIDTH of U0 : label is 1;
  attribute C_PROBE786_MU_CNT : integer;
  attribute C_PROBE786_MU_CNT of U0 : label is 1;
  attribute C_PROBE786_TYPE : integer;
  attribute C_PROBE786_TYPE of U0 : label is 1;
  attribute C_PROBE786_WIDTH : integer;
  attribute C_PROBE786_WIDTH of U0 : label is 1;
  attribute C_PROBE787_MU_CNT : integer;
  attribute C_PROBE787_MU_CNT of U0 : label is 1;
  attribute C_PROBE787_TYPE : integer;
  attribute C_PROBE787_TYPE of U0 : label is 1;
  attribute C_PROBE787_WIDTH : integer;
  attribute C_PROBE787_WIDTH of U0 : label is 1;
  attribute C_PROBE788_MU_CNT : integer;
  attribute C_PROBE788_MU_CNT of U0 : label is 1;
  attribute C_PROBE788_TYPE : integer;
  attribute C_PROBE788_TYPE of U0 : label is 1;
  attribute C_PROBE788_WIDTH : integer;
  attribute C_PROBE788_WIDTH of U0 : label is 1;
  attribute C_PROBE789_MU_CNT : integer;
  attribute C_PROBE789_MU_CNT of U0 : label is 1;
  attribute C_PROBE789_TYPE : integer;
  attribute C_PROBE789_TYPE of U0 : label is 1;
  attribute C_PROBE789_WIDTH : integer;
  attribute C_PROBE789_WIDTH of U0 : label is 1;
  attribute C_PROBE78_MU_CNT : integer;
  attribute C_PROBE78_MU_CNT of U0 : label is 1;
  attribute C_PROBE78_TYPE : integer;
  attribute C_PROBE78_TYPE of U0 : label is 1;
  attribute C_PROBE78_WIDTH : integer;
  attribute C_PROBE78_WIDTH of U0 : label is 1;
  attribute C_PROBE790_MU_CNT : integer;
  attribute C_PROBE790_MU_CNT of U0 : label is 1;
  attribute C_PROBE790_TYPE : integer;
  attribute C_PROBE790_TYPE of U0 : label is 1;
  attribute C_PROBE790_WIDTH : integer;
  attribute C_PROBE790_WIDTH of U0 : label is 1;
  attribute C_PROBE791_MU_CNT : integer;
  attribute C_PROBE791_MU_CNT of U0 : label is 1;
  attribute C_PROBE791_TYPE : integer;
  attribute C_PROBE791_TYPE of U0 : label is 1;
  attribute C_PROBE791_WIDTH : integer;
  attribute C_PROBE791_WIDTH of U0 : label is 1;
  attribute C_PROBE792_MU_CNT : integer;
  attribute C_PROBE792_MU_CNT of U0 : label is 1;
  attribute C_PROBE792_TYPE : integer;
  attribute C_PROBE792_TYPE of U0 : label is 1;
  attribute C_PROBE792_WIDTH : integer;
  attribute C_PROBE792_WIDTH of U0 : label is 1;
  attribute C_PROBE793_MU_CNT : integer;
  attribute C_PROBE793_MU_CNT of U0 : label is 1;
  attribute C_PROBE793_TYPE : integer;
  attribute C_PROBE793_TYPE of U0 : label is 1;
  attribute C_PROBE793_WIDTH : integer;
  attribute C_PROBE793_WIDTH of U0 : label is 1;
  attribute C_PROBE794_MU_CNT : integer;
  attribute C_PROBE794_MU_CNT of U0 : label is 1;
  attribute C_PROBE794_TYPE : integer;
  attribute C_PROBE794_TYPE of U0 : label is 1;
  attribute C_PROBE794_WIDTH : integer;
  attribute C_PROBE794_WIDTH of U0 : label is 1;
  attribute C_PROBE795_MU_CNT : integer;
  attribute C_PROBE795_MU_CNT of U0 : label is 1;
  attribute C_PROBE795_TYPE : integer;
  attribute C_PROBE795_TYPE of U0 : label is 1;
  attribute C_PROBE795_WIDTH : integer;
  attribute C_PROBE795_WIDTH of U0 : label is 1;
  attribute C_PROBE796_MU_CNT : integer;
  attribute C_PROBE796_MU_CNT of U0 : label is 1;
  attribute C_PROBE796_TYPE : integer;
  attribute C_PROBE796_TYPE of U0 : label is 1;
  attribute C_PROBE796_WIDTH : integer;
  attribute C_PROBE796_WIDTH of U0 : label is 1;
  attribute C_PROBE797_MU_CNT : integer;
  attribute C_PROBE797_MU_CNT of U0 : label is 1;
  attribute C_PROBE797_TYPE : integer;
  attribute C_PROBE797_TYPE of U0 : label is 1;
  attribute C_PROBE797_WIDTH : integer;
  attribute C_PROBE797_WIDTH of U0 : label is 1;
  attribute C_PROBE798_MU_CNT : integer;
  attribute C_PROBE798_MU_CNT of U0 : label is 1;
  attribute C_PROBE798_TYPE : integer;
  attribute C_PROBE798_TYPE of U0 : label is 1;
  attribute C_PROBE798_WIDTH : integer;
  attribute C_PROBE798_WIDTH of U0 : label is 1;
  attribute C_PROBE799_MU_CNT : integer;
  attribute C_PROBE799_MU_CNT of U0 : label is 1;
  attribute C_PROBE799_TYPE : integer;
  attribute C_PROBE799_TYPE of U0 : label is 1;
  attribute C_PROBE799_WIDTH : integer;
  attribute C_PROBE799_WIDTH of U0 : label is 1;
  attribute C_PROBE79_MU_CNT : integer;
  attribute C_PROBE79_MU_CNT of U0 : label is 1;
  attribute C_PROBE79_TYPE : integer;
  attribute C_PROBE79_TYPE of U0 : label is 1;
  attribute C_PROBE79_WIDTH : integer;
  attribute C_PROBE79_WIDTH of U0 : label is 1;
  attribute C_PROBE7_MU_CNT : integer;
  attribute C_PROBE7_MU_CNT of U0 : label is 1;
  attribute C_PROBE7_TYPE : integer;
  attribute C_PROBE7_TYPE of U0 : label is 1;
  attribute C_PROBE7_WIDTH : integer;
  attribute C_PROBE7_WIDTH of U0 : label is 1;
  attribute C_PROBE800_MU_CNT : integer;
  attribute C_PROBE800_MU_CNT of U0 : label is 1;
  attribute C_PROBE800_TYPE : integer;
  attribute C_PROBE800_TYPE of U0 : label is 1;
  attribute C_PROBE800_WIDTH : integer;
  attribute C_PROBE800_WIDTH of U0 : label is 1;
  attribute C_PROBE801_MU_CNT : integer;
  attribute C_PROBE801_MU_CNT of U0 : label is 1;
  attribute C_PROBE801_TYPE : integer;
  attribute C_PROBE801_TYPE of U0 : label is 1;
  attribute C_PROBE801_WIDTH : integer;
  attribute C_PROBE801_WIDTH of U0 : label is 1;
  attribute C_PROBE802_MU_CNT : integer;
  attribute C_PROBE802_MU_CNT of U0 : label is 1;
  attribute C_PROBE802_TYPE : integer;
  attribute C_PROBE802_TYPE of U0 : label is 1;
  attribute C_PROBE802_WIDTH : integer;
  attribute C_PROBE802_WIDTH of U0 : label is 1;
  attribute C_PROBE803_MU_CNT : integer;
  attribute C_PROBE803_MU_CNT of U0 : label is 1;
  attribute C_PROBE803_TYPE : integer;
  attribute C_PROBE803_TYPE of U0 : label is 1;
  attribute C_PROBE803_WIDTH : integer;
  attribute C_PROBE803_WIDTH of U0 : label is 1;
  attribute C_PROBE804_MU_CNT : integer;
  attribute C_PROBE804_MU_CNT of U0 : label is 1;
  attribute C_PROBE804_TYPE : integer;
  attribute C_PROBE804_TYPE of U0 : label is 1;
  attribute C_PROBE804_WIDTH : integer;
  attribute C_PROBE804_WIDTH of U0 : label is 1;
  attribute C_PROBE805_MU_CNT : integer;
  attribute C_PROBE805_MU_CNT of U0 : label is 1;
  attribute C_PROBE805_TYPE : integer;
  attribute C_PROBE805_TYPE of U0 : label is 1;
  attribute C_PROBE805_WIDTH : integer;
  attribute C_PROBE805_WIDTH of U0 : label is 1;
  attribute C_PROBE806_MU_CNT : integer;
  attribute C_PROBE806_MU_CNT of U0 : label is 1;
  attribute C_PROBE806_TYPE : integer;
  attribute C_PROBE806_TYPE of U0 : label is 1;
  attribute C_PROBE806_WIDTH : integer;
  attribute C_PROBE806_WIDTH of U0 : label is 1;
  attribute C_PROBE807_MU_CNT : integer;
  attribute C_PROBE807_MU_CNT of U0 : label is 1;
  attribute C_PROBE807_TYPE : integer;
  attribute C_PROBE807_TYPE of U0 : label is 1;
  attribute C_PROBE807_WIDTH : integer;
  attribute C_PROBE807_WIDTH of U0 : label is 1;
  attribute C_PROBE808_MU_CNT : integer;
  attribute C_PROBE808_MU_CNT of U0 : label is 1;
  attribute C_PROBE808_TYPE : integer;
  attribute C_PROBE808_TYPE of U0 : label is 1;
  attribute C_PROBE808_WIDTH : integer;
  attribute C_PROBE808_WIDTH of U0 : label is 1;
  attribute C_PROBE809_MU_CNT : integer;
  attribute C_PROBE809_MU_CNT of U0 : label is 1;
  attribute C_PROBE809_TYPE : integer;
  attribute C_PROBE809_TYPE of U0 : label is 1;
  attribute C_PROBE809_WIDTH : integer;
  attribute C_PROBE809_WIDTH of U0 : label is 1;
  attribute C_PROBE80_MU_CNT : integer;
  attribute C_PROBE80_MU_CNT of U0 : label is 1;
  attribute C_PROBE80_TYPE : integer;
  attribute C_PROBE80_TYPE of U0 : label is 1;
  attribute C_PROBE80_WIDTH : integer;
  attribute C_PROBE80_WIDTH of U0 : label is 1;
  attribute C_PROBE810_MU_CNT : integer;
  attribute C_PROBE810_MU_CNT of U0 : label is 1;
  attribute C_PROBE810_TYPE : integer;
  attribute C_PROBE810_TYPE of U0 : label is 1;
  attribute C_PROBE810_WIDTH : integer;
  attribute C_PROBE810_WIDTH of U0 : label is 1;
  attribute C_PROBE811_MU_CNT : integer;
  attribute C_PROBE811_MU_CNT of U0 : label is 1;
  attribute C_PROBE811_TYPE : integer;
  attribute C_PROBE811_TYPE of U0 : label is 1;
  attribute C_PROBE811_WIDTH : integer;
  attribute C_PROBE811_WIDTH of U0 : label is 1;
  attribute C_PROBE812_MU_CNT : integer;
  attribute C_PROBE812_MU_CNT of U0 : label is 1;
  attribute C_PROBE812_TYPE : integer;
  attribute C_PROBE812_TYPE of U0 : label is 1;
  attribute C_PROBE812_WIDTH : integer;
  attribute C_PROBE812_WIDTH of U0 : label is 1;
  attribute C_PROBE813_MU_CNT : integer;
  attribute C_PROBE813_MU_CNT of U0 : label is 1;
  attribute C_PROBE813_TYPE : integer;
  attribute C_PROBE813_TYPE of U0 : label is 1;
  attribute C_PROBE813_WIDTH : integer;
  attribute C_PROBE813_WIDTH of U0 : label is 1;
  attribute C_PROBE814_MU_CNT : integer;
  attribute C_PROBE814_MU_CNT of U0 : label is 1;
  attribute C_PROBE814_TYPE : integer;
  attribute C_PROBE814_TYPE of U0 : label is 1;
  attribute C_PROBE814_WIDTH : integer;
  attribute C_PROBE814_WIDTH of U0 : label is 1;
  attribute C_PROBE815_MU_CNT : integer;
  attribute C_PROBE815_MU_CNT of U0 : label is 1;
  attribute C_PROBE815_TYPE : integer;
  attribute C_PROBE815_TYPE of U0 : label is 1;
  attribute C_PROBE815_WIDTH : integer;
  attribute C_PROBE815_WIDTH of U0 : label is 1;
  attribute C_PROBE816_MU_CNT : integer;
  attribute C_PROBE816_MU_CNT of U0 : label is 1;
  attribute C_PROBE816_TYPE : integer;
  attribute C_PROBE816_TYPE of U0 : label is 1;
  attribute C_PROBE816_WIDTH : integer;
  attribute C_PROBE816_WIDTH of U0 : label is 1;
  attribute C_PROBE817_MU_CNT : integer;
  attribute C_PROBE817_MU_CNT of U0 : label is 1;
  attribute C_PROBE817_TYPE : integer;
  attribute C_PROBE817_TYPE of U0 : label is 1;
  attribute C_PROBE817_WIDTH : integer;
  attribute C_PROBE817_WIDTH of U0 : label is 1;
  attribute C_PROBE818_MU_CNT : integer;
  attribute C_PROBE818_MU_CNT of U0 : label is 1;
  attribute C_PROBE818_TYPE : integer;
  attribute C_PROBE818_TYPE of U0 : label is 1;
  attribute C_PROBE818_WIDTH : integer;
  attribute C_PROBE818_WIDTH of U0 : label is 1;
  attribute C_PROBE819_MU_CNT : integer;
  attribute C_PROBE819_MU_CNT of U0 : label is 1;
  attribute C_PROBE819_TYPE : integer;
  attribute C_PROBE819_TYPE of U0 : label is 1;
  attribute C_PROBE819_WIDTH : integer;
  attribute C_PROBE819_WIDTH of U0 : label is 1;
  attribute C_PROBE81_MU_CNT : integer;
  attribute C_PROBE81_MU_CNT of U0 : label is 1;
  attribute C_PROBE81_TYPE : integer;
  attribute C_PROBE81_TYPE of U0 : label is 1;
  attribute C_PROBE81_WIDTH : integer;
  attribute C_PROBE81_WIDTH of U0 : label is 1;
  attribute C_PROBE820_MU_CNT : integer;
  attribute C_PROBE820_MU_CNT of U0 : label is 1;
  attribute C_PROBE820_TYPE : integer;
  attribute C_PROBE820_TYPE of U0 : label is 1;
  attribute C_PROBE820_WIDTH : integer;
  attribute C_PROBE820_WIDTH of U0 : label is 1;
  attribute C_PROBE821_MU_CNT : integer;
  attribute C_PROBE821_MU_CNT of U0 : label is 1;
  attribute C_PROBE821_TYPE : integer;
  attribute C_PROBE821_TYPE of U0 : label is 1;
  attribute C_PROBE821_WIDTH : integer;
  attribute C_PROBE821_WIDTH of U0 : label is 1;
  attribute C_PROBE822_MU_CNT : integer;
  attribute C_PROBE822_MU_CNT of U0 : label is 1;
  attribute C_PROBE822_TYPE : integer;
  attribute C_PROBE822_TYPE of U0 : label is 1;
  attribute C_PROBE822_WIDTH : integer;
  attribute C_PROBE822_WIDTH of U0 : label is 1;
  attribute C_PROBE823_MU_CNT : integer;
  attribute C_PROBE823_MU_CNT of U0 : label is 1;
  attribute C_PROBE823_TYPE : integer;
  attribute C_PROBE823_TYPE of U0 : label is 1;
  attribute C_PROBE823_WIDTH : integer;
  attribute C_PROBE823_WIDTH of U0 : label is 1;
  attribute C_PROBE824_MU_CNT : integer;
  attribute C_PROBE824_MU_CNT of U0 : label is 1;
  attribute C_PROBE824_TYPE : integer;
  attribute C_PROBE824_TYPE of U0 : label is 1;
  attribute C_PROBE824_WIDTH : integer;
  attribute C_PROBE824_WIDTH of U0 : label is 1;
  attribute C_PROBE825_MU_CNT : integer;
  attribute C_PROBE825_MU_CNT of U0 : label is 1;
  attribute C_PROBE825_TYPE : integer;
  attribute C_PROBE825_TYPE of U0 : label is 1;
  attribute C_PROBE825_WIDTH : integer;
  attribute C_PROBE825_WIDTH of U0 : label is 1;
  attribute C_PROBE826_MU_CNT : integer;
  attribute C_PROBE826_MU_CNT of U0 : label is 1;
  attribute C_PROBE826_TYPE : integer;
  attribute C_PROBE826_TYPE of U0 : label is 1;
  attribute C_PROBE826_WIDTH : integer;
  attribute C_PROBE826_WIDTH of U0 : label is 1;
  attribute C_PROBE827_MU_CNT : integer;
  attribute C_PROBE827_MU_CNT of U0 : label is 1;
  attribute C_PROBE827_TYPE : integer;
  attribute C_PROBE827_TYPE of U0 : label is 1;
  attribute C_PROBE827_WIDTH : integer;
  attribute C_PROBE827_WIDTH of U0 : label is 1;
  attribute C_PROBE828_MU_CNT : integer;
  attribute C_PROBE828_MU_CNT of U0 : label is 1;
  attribute C_PROBE828_TYPE : integer;
  attribute C_PROBE828_TYPE of U0 : label is 1;
  attribute C_PROBE828_WIDTH : integer;
  attribute C_PROBE828_WIDTH of U0 : label is 1;
  attribute C_PROBE829_MU_CNT : integer;
  attribute C_PROBE829_MU_CNT of U0 : label is 1;
  attribute C_PROBE829_TYPE : integer;
  attribute C_PROBE829_TYPE of U0 : label is 1;
  attribute C_PROBE829_WIDTH : integer;
  attribute C_PROBE829_WIDTH of U0 : label is 1;
  attribute C_PROBE82_MU_CNT : integer;
  attribute C_PROBE82_MU_CNT of U0 : label is 1;
  attribute C_PROBE82_TYPE : integer;
  attribute C_PROBE82_TYPE of U0 : label is 1;
  attribute C_PROBE82_WIDTH : integer;
  attribute C_PROBE82_WIDTH of U0 : label is 1;
  attribute C_PROBE830_MU_CNT : integer;
  attribute C_PROBE830_MU_CNT of U0 : label is 1;
  attribute C_PROBE830_TYPE : integer;
  attribute C_PROBE830_TYPE of U0 : label is 1;
  attribute C_PROBE830_WIDTH : integer;
  attribute C_PROBE830_WIDTH of U0 : label is 1;
  attribute C_PROBE831_MU_CNT : integer;
  attribute C_PROBE831_MU_CNT of U0 : label is 1;
  attribute C_PROBE831_TYPE : integer;
  attribute C_PROBE831_TYPE of U0 : label is 1;
  attribute C_PROBE831_WIDTH : integer;
  attribute C_PROBE831_WIDTH of U0 : label is 1;
  attribute C_PROBE832_MU_CNT : integer;
  attribute C_PROBE832_MU_CNT of U0 : label is 1;
  attribute C_PROBE832_TYPE : integer;
  attribute C_PROBE832_TYPE of U0 : label is 1;
  attribute C_PROBE832_WIDTH : integer;
  attribute C_PROBE832_WIDTH of U0 : label is 1;
  attribute C_PROBE833_MU_CNT : integer;
  attribute C_PROBE833_MU_CNT of U0 : label is 1;
  attribute C_PROBE833_TYPE : integer;
  attribute C_PROBE833_TYPE of U0 : label is 1;
  attribute C_PROBE833_WIDTH : integer;
  attribute C_PROBE833_WIDTH of U0 : label is 1;
  attribute C_PROBE834_MU_CNT : integer;
  attribute C_PROBE834_MU_CNT of U0 : label is 1;
  attribute C_PROBE834_TYPE : integer;
  attribute C_PROBE834_TYPE of U0 : label is 1;
  attribute C_PROBE834_WIDTH : integer;
  attribute C_PROBE834_WIDTH of U0 : label is 1;
  attribute C_PROBE835_MU_CNT : integer;
  attribute C_PROBE835_MU_CNT of U0 : label is 1;
  attribute C_PROBE835_TYPE : integer;
  attribute C_PROBE835_TYPE of U0 : label is 1;
  attribute C_PROBE835_WIDTH : integer;
  attribute C_PROBE835_WIDTH of U0 : label is 1;
  attribute C_PROBE836_MU_CNT : integer;
  attribute C_PROBE836_MU_CNT of U0 : label is 1;
  attribute C_PROBE836_TYPE : integer;
  attribute C_PROBE836_TYPE of U0 : label is 1;
  attribute C_PROBE836_WIDTH : integer;
  attribute C_PROBE836_WIDTH of U0 : label is 1;
  attribute C_PROBE837_MU_CNT : integer;
  attribute C_PROBE837_MU_CNT of U0 : label is 1;
  attribute C_PROBE837_TYPE : integer;
  attribute C_PROBE837_TYPE of U0 : label is 1;
  attribute C_PROBE837_WIDTH : integer;
  attribute C_PROBE837_WIDTH of U0 : label is 1;
  attribute C_PROBE838_MU_CNT : integer;
  attribute C_PROBE838_MU_CNT of U0 : label is 1;
  attribute C_PROBE838_TYPE : integer;
  attribute C_PROBE838_TYPE of U0 : label is 1;
  attribute C_PROBE838_WIDTH : integer;
  attribute C_PROBE838_WIDTH of U0 : label is 1;
  attribute C_PROBE839_MU_CNT : integer;
  attribute C_PROBE839_MU_CNT of U0 : label is 1;
  attribute C_PROBE839_TYPE : integer;
  attribute C_PROBE839_TYPE of U0 : label is 1;
  attribute C_PROBE839_WIDTH : integer;
  attribute C_PROBE839_WIDTH of U0 : label is 1;
  attribute C_PROBE83_MU_CNT : integer;
  attribute C_PROBE83_MU_CNT of U0 : label is 1;
  attribute C_PROBE83_TYPE : integer;
  attribute C_PROBE83_TYPE of U0 : label is 1;
  attribute C_PROBE83_WIDTH : integer;
  attribute C_PROBE83_WIDTH of U0 : label is 1;
  attribute C_PROBE840_MU_CNT : integer;
  attribute C_PROBE840_MU_CNT of U0 : label is 1;
  attribute C_PROBE840_TYPE : integer;
  attribute C_PROBE840_TYPE of U0 : label is 1;
  attribute C_PROBE840_WIDTH : integer;
  attribute C_PROBE840_WIDTH of U0 : label is 1;
  attribute C_PROBE841_MU_CNT : integer;
  attribute C_PROBE841_MU_CNT of U0 : label is 1;
  attribute C_PROBE841_TYPE : integer;
  attribute C_PROBE841_TYPE of U0 : label is 1;
  attribute C_PROBE841_WIDTH : integer;
  attribute C_PROBE841_WIDTH of U0 : label is 1;
  attribute C_PROBE842_MU_CNT : integer;
  attribute C_PROBE842_MU_CNT of U0 : label is 1;
  attribute C_PROBE842_TYPE : integer;
  attribute C_PROBE842_TYPE of U0 : label is 1;
  attribute C_PROBE842_WIDTH : integer;
  attribute C_PROBE842_WIDTH of U0 : label is 1;
  attribute C_PROBE843_MU_CNT : integer;
  attribute C_PROBE843_MU_CNT of U0 : label is 1;
  attribute C_PROBE843_TYPE : integer;
  attribute C_PROBE843_TYPE of U0 : label is 1;
  attribute C_PROBE843_WIDTH : integer;
  attribute C_PROBE843_WIDTH of U0 : label is 1;
  attribute C_PROBE844_MU_CNT : integer;
  attribute C_PROBE844_MU_CNT of U0 : label is 1;
  attribute C_PROBE844_TYPE : integer;
  attribute C_PROBE844_TYPE of U0 : label is 1;
  attribute C_PROBE844_WIDTH : integer;
  attribute C_PROBE844_WIDTH of U0 : label is 1;
  attribute C_PROBE845_MU_CNT : integer;
  attribute C_PROBE845_MU_CNT of U0 : label is 1;
  attribute C_PROBE845_TYPE : integer;
  attribute C_PROBE845_TYPE of U0 : label is 1;
  attribute C_PROBE845_WIDTH : integer;
  attribute C_PROBE845_WIDTH of U0 : label is 1;
  attribute C_PROBE846_MU_CNT : integer;
  attribute C_PROBE846_MU_CNT of U0 : label is 1;
  attribute C_PROBE846_TYPE : integer;
  attribute C_PROBE846_TYPE of U0 : label is 1;
  attribute C_PROBE846_WIDTH : integer;
  attribute C_PROBE846_WIDTH of U0 : label is 1;
  attribute C_PROBE847_MU_CNT : integer;
  attribute C_PROBE847_MU_CNT of U0 : label is 1;
  attribute C_PROBE847_TYPE : integer;
  attribute C_PROBE847_TYPE of U0 : label is 1;
  attribute C_PROBE847_WIDTH : integer;
  attribute C_PROBE847_WIDTH of U0 : label is 1;
  attribute C_PROBE848_MU_CNT : integer;
  attribute C_PROBE848_MU_CNT of U0 : label is 1;
  attribute C_PROBE848_TYPE : integer;
  attribute C_PROBE848_TYPE of U0 : label is 1;
  attribute C_PROBE848_WIDTH : integer;
  attribute C_PROBE848_WIDTH of U0 : label is 1;
  attribute C_PROBE849_MU_CNT : integer;
  attribute C_PROBE849_MU_CNT of U0 : label is 1;
  attribute C_PROBE849_TYPE : integer;
  attribute C_PROBE849_TYPE of U0 : label is 1;
  attribute C_PROBE849_WIDTH : integer;
  attribute C_PROBE849_WIDTH of U0 : label is 1;
  attribute C_PROBE84_MU_CNT : integer;
  attribute C_PROBE84_MU_CNT of U0 : label is 1;
  attribute C_PROBE84_TYPE : integer;
  attribute C_PROBE84_TYPE of U0 : label is 1;
  attribute C_PROBE84_WIDTH : integer;
  attribute C_PROBE84_WIDTH of U0 : label is 1;
  attribute C_PROBE850_MU_CNT : integer;
  attribute C_PROBE850_MU_CNT of U0 : label is 1;
  attribute C_PROBE850_TYPE : integer;
  attribute C_PROBE850_TYPE of U0 : label is 1;
  attribute C_PROBE850_WIDTH : integer;
  attribute C_PROBE850_WIDTH of U0 : label is 1;
  attribute C_PROBE851_MU_CNT : integer;
  attribute C_PROBE851_MU_CNT of U0 : label is 1;
  attribute C_PROBE851_TYPE : integer;
  attribute C_PROBE851_TYPE of U0 : label is 1;
  attribute C_PROBE851_WIDTH : integer;
  attribute C_PROBE851_WIDTH of U0 : label is 1;
  attribute C_PROBE852_MU_CNT : integer;
  attribute C_PROBE852_MU_CNT of U0 : label is 1;
  attribute C_PROBE852_TYPE : integer;
  attribute C_PROBE852_TYPE of U0 : label is 1;
  attribute C_PROBE852_WIDTH : integer;
  attribute C_PROBE852_WIDTH of U0 : label is 1;
  attribute C_PROBE853_MU_CNT : integer;
  attribute C_PROBE853_MU_CNT of U0 : label is 1;
  attribute C_PROBE853_TYPE : integer;
  attribute C_PROBE853_TYPE of U0 : label is 1;
  attribute C_PROBE853_WIDTH : integer;
  attribute C_PROBE853_WIDTH of U0 : label is 1;
  attribute C_PROBE854_MU_CNT : integer;
  attribute C_PROBE854_MU_CNT of U0 : label is 1;
  attribute C_PROBE854_TYPE : integer;
  attribute C_PROBE854_TYPE of U0 : label is 1;
  attribute C_PROBE854_WIDTH : integer;
  attribute C_PROBE854_WIDTH of U0 : label is 1;
  attribute C_PROBE855_MU_CNT : integer;
  attribute C_PROBE855_MU_CNT of U0 : label is 1;
  attribute C_PROBE855_TYPE : integer;
  attribute C_PROBE855_TYPE of U0 : label is 1;
  attribute C_PROBE855_WIDTH : integer;
  attribute C_PROBE855_WIDTH of U0 : label is 1;
  attribute C_PROBE856_MU_CNT : integer;
  attribute C_PROBE856_MU_CNT of U0 : label is 1;
  attribute C_PROBE856_TYPE : integer;
  attribute C_PROBE856_TYPE of U0 : label is 1;
  attribute C_PROBE856_WIDTH : integer;
  attribute C_PROBE856_WIDTH of U0 : label is 1;
  attribute C_PROBE857_MU_CNT : integer;
  attribute C_PROBE857_MU_CNT of U0 : label is 1;
  attribute C_PROBE857_TYPE : integer;
  attribute C_PROBE857_TYPE of U0 : label is 1;
  attribute C_PROBE857_WIDTH : integer;
  attribute C_PROBE857_WIDTH of U0 : label is 1;
  attribute C_PROBE858_MU_CNT : integer;
  attribute C_PROBE858_MU_CNT of U0 : label is 1;
  attribute C_PROBE858_TYPE : integer;
  attribute C_PROBE858_TYPE of U0 : label is 1;
  attribute C_PROBE858_WIDTH : integer;
  attribute C_PROBE858_WIDTH of U0 : label is 1;
  attribute C_PROBE859_MU_CNT : integer;
  attribute C_PROBE859_MU_CNT of U0 : label is 1;
  attribute C_PROBE859_TYPE : integer;
  attribute C_PROBE859_TYPE of U0 : label is 1;
  attribute C_PROBE859_WIDTH : integer;
  attribute C_PROBE859_WIDTH of U0 : label is 1;
  attribute C_PROBE85_MU_CNT : integer;
  attribute C_PROBE85_MU_CNT of U0 : label is 1;
  attribute C_PROBE85_TYPE : integer;
  attribute C_PROBE85_TYPE of U0 : label is 1;
  attribute C_PROBE85_WIDTH : integer;
  attribute C_PROBE85_WIDTH of U0 : label is 1;
  attribute C_PROBE860_MU_CNT : integer;
  attribute C_PROBE860_MU_CNT of U0 : label is 1;
  attribute C_PROBE860_TYPE : integer;
  attribute C_PROBE860_TYPE of U0 : label is 1;
  attribute C_PROBE860_WIDTH : integer;
  attribute C_PROBE860_WIDTH of U0 : label is 1;
  attribute C_PROBE861_MU_CNT : integer;
  attribute C_PROBE861_MU_CNT of U0 : label is 1;
  attribute C_PROBE861_TYPE : integer;
  attribute C_PROBE861_TYPE of U0 : label is 1;
  attribute C_PROBE861_WIDTH : integer;
  attribute C_PROBE861_WIDTH of U0 : label is 1;
  attribute C_PROBE862_MU_CNT : integer;
  attribute C_PROBE862_MU_CNT of U0 : label is 1;
  attribute C_PROBE862_TYPE : integer;
  attribute C_PROBE862_TYPE of U0 : label is 1;
  attribute C_PROBE862_WIDTH : integer;
  attribute C_PROBE862_WIDTH of U0 : label is 1;
  attribute C_PROBE863_MU_CNT : integer;
  attribute C_PROBE863_MU_CNT of U0 : label is 1;
  attribute C_PROBE863_TYPE : integer;
  attribute C_PROBE863_TYPE of U0 : label is 1;
  attribute C_PROBE863_WIDTH : integer;
  attribute C_PROBE863_WIDTH of U0 : label is 1;
  attribute C_PROBE864_MU_CNT : integer;
  attribute C_PROBE864_MU_CNT of U0 : label is 1;
  attribute C_PROBE864_TYPE : integer;
  attribute C_PROBE864_TYPE of U0 : label is 1;
  attribute C_PROBE864_WIDTH : integer;
  attribute C_PROBE864_WIDTH of U0 : label is 1;
  attribute C_PROBE865_MU_CNT : integer;
  attribute C_PROBE865_MU_CNT of U0 : label is 1;
  attribute C_PROBE865_TYPE : integer;
  attribute C_PROBE865_TYPE of U0 : label is 1;
  attribute C_PROBE865_WIDTH : integer;
  attribute C_PROBE865_WIDTH of U0 : label is 1;
  attribute C_PROBE866_MU_CNT : integer;
  attribute C_PROBE866_MU_CNT of U0 : label is 1;
  attribute C_PROBE866_TYPE : integer;
  attribute C_PROBE866_TYPE of U0 : label is 1;
  attribute C_PROBE866_WIDTH : integer;
  attribute C_PROBE866_WIDTH of U0 : label is 1;
  attribute C_PROBE867_MU_CNT : integer;
  attribute C_PROBE867_MU_CNT of U0 : label is 1;
  attribute C_PROBE867_TYPE : integer;
  attribute C_PROBE867_TYPE of U0 : label is 1;
  attribute C_PROBE867_WIDTH : integer;
  attribute C_PROBE867_WIDTH of U0 : label is 1;
  attribute C_PROBE868_MU_CNT : integer;
  attribute C_PROBE868_MU_CNT of U0 : label is 1;
  attribute C_PROBE868_TYPE : integer;
  attribute C_PROBE868_TYPE of U0 : label is 1;
  attribute C_PROBE868_WIDTH : integer;
  attribute C_PROBE868_WIDTH of U0 : label is 1;
  attribute C_PROBE869_MU_CNT : integer;
  attribute C_PROBE869_MU_CNT of U0 : label is 1;
  attribute C_PROBE869_TYPE : integer;
  attribute C_PROBE869_TYPE of U0 : label is 1;
  attribute C_PROBE869_WIDTH : integer;
  attribute C_PROBE869_WIDTH of U0 : label is 1;
  attribute C_PROBE86_MU_CNT : integer;
  attribute C_PROBE86_MU_CNT of U0 : label is 1;
  attribute C_PROBE86_TYPE : integer;
  attribute C_PROBE86_TYPE of U0 : label is 1;
  attribute C_PROBE86_WIDTH : integer;
  attribute C_PROBE86_WIDTH of U0 : label is 1;
  attribute C_PROBE870_MU_CNT : integer;
  attribute C_PROBE870_MU_CNT of U0 : label is 1;
  attribute C_PROBE870_TYPE : integer;
  attribute C_PROBE870_TYPE of U0 : label is 1;
  attribute C_PROBE870_WIDTH : integer;
  attribute C_PROBE870_WIDTH of U0 : label is 1;
  attribute C_PROBE871_MU_CNT : integer;
  attribute C_PROBE871_MU_CNT of U0 : label is 1;
  attribute C_PROBE871_TYPE : integer;
  attribute C_PROBE871_TYPE of U0 : label is 1;
  attribute C_PROBE871_WIDTH : integer;
  attribute C_PROBE871_WIDTH of U0 : label is 1;
  attribute C_PROBE872_MU_CNT : integer;
  attribute C_PROBE872_MU_CNT of U0 : label is 1;
  attribute C_PROBE872_TYPE : integer;
  attribute C_PROBE872_TYPE of U0 : label is 1;
  attribute C_PROBE872_WIDTH : integer;
  attribute C_PROBE872_WIDTH of U0 : label is 1;
  attribute C_PROBE873_MU_CNT : integer;
  attribute C_PROBE873_MU_CNT of U0 : label is 1;
  attribute C_PROBE873_TYPE : integer;
  attribute C_PROBE873_TYPE of U0 : label is 1;
  attribute C_PROBE873_WIDTH : integer;
  attribute C_PROBE873_WIDTH of U0 : label is 1;
  attribute C_PROBE874_MU_CNT : integer;
  attribute C_PROBE874_MU_CNT of U0 : label is 1;
  attribute C_PROBE874_TYPE : integer;
  attribute C_PROBE874_TYPE of U0 : label is 1;
  attribute C_PROBE874_WIDTH : integer;
  attribute C_PROBE874_WIDTH of U0 : label is 1;
  attribute C_PROBE875_MU_CNT : integer;
  attribute C_PROBE875_MU_CNT of U0 : label is 1;
  attribute C_PROBE875_TYPE : integer;
  attribute C_PROBE875_TYPE of U0 : label is 1;
  attribute C_PROBE875_WIDTH : integer;
  attribute C_PROBE875_WIDTH of U0 : label is 1;
  attribute C_PROBE876_MU_CNT : integer;
  attribute C_PROBE876_MU_CNT of U0 : label is 1;
  attribute C_PROBE876_TYPE : integer;
  attribute C_PROBE876_TYPE of U0 : label is 1;
  attribute C_PROBE876_WIDTH : integer;
  attribute C_PROBE876_WIDTH of U0 : label is 1;
  attribute C_PROBE877_MU_CNT : integer;
  attribute C_PROBE877_MU_CNT of U0 : label is 1;
  attribute C_PROBE877_TYPE : integer;
  attribute C_PROBE877_TYPE of U0 : label is 1;
  attribute C_PROBE877_WIDTH : integer;
  attribute C_PROBE877_WIDTH of U0 : label is 1;
  attribute C_PROBE878_MU_CNT : integer;
  attribute C_PROBE878_MU_CNT of U0 : label is 1;
  attribute C_PROBE878_TYPE : integer;
  attribute C_PROBE878_TYPE of U0 : label is 1;
  attribute C_PROBE878_WIDTH : integer;
  attribute C_PROBE878_WIDTH of U0 : label is 1;
  attribute C_PROBE879_MU_CNT : integer;
  attribute C_PROBE879_MU_CNT of U0 : label is 1;
  attribute C_PROBE879_TYPE : integer;
  attribute C_PROBE879_TYPE of U0 : label is 1;
  attribute C_PROBE879_WIDTH : integer;
  attribute C_PROBE879_WIDTH of U0 : label is 1;
  attribute C_PROBE87_MU_CNT : integer;
  attribute C_PROBE87_MU_CNT of U0 : label is 1;
  attribute C_PROBE87_TYPE : integer;
  attribute C_PROBE87_TYPE of U0 : label is 1;
  attribute C_PROBE87_WIDTH : integer;
  attribute C_PROBE87_WIDTH of U0 : label is 1;
  attribute C_PROBE880_MU_CNT : integer;
  attribute C_PROBE880_MU_CNT of U0 : label is 1;
  attribute C_PROBE880_TYPE : integer;
  attribute C_PROBE880_TYPE of U0 : label is 1;
  attribute C_PROBE880_WIDTH : integer;
  attribute C_PROBE880_WIDTH of U0 : label is 1;
  attribute C_PROBE881_MU_CNT : integer;
  attribute C_PROBE881_MU_CNT of U0 : label is 1;
  attribute C_PROBE881_TYPE : integer;
  attribute C_PROBE881_TYPE of U0 : label is 1;
  attribute C_PROBE881_WIDTH : integer;
  attribute C_PROBE881_WIDTH of U0 : label is 1;
  attribute C_PROBE882_MU_CNT : integer;
  attribute C_PROBE882_MU_CNT of U0 : label is 1;
  attribute C_PROBE882_TYPE : integer;
  attribute C_PROBE882_TYPE of U0 : label is 1;
  attribute C_PROBE882_WIDTH : integer;
  attribute C_PROBE882_WIDTH of U0 : label is 1;
  attribute C_PROBE883_MU_CNT : integer;
  attribute C_PROBE883_MU_CNT of U0 : label is 1;
  attribute C_PROBE883_TYPE : integer;
  attribute C_PROBE883_TYPE of U0 : label is 1;
  attribute C_PROBE883_WIDTH : integer;
  attribute C_PROBE883_WIDTH of U0 : label is 1;
  attribute C_PROBE884_MU_CNT : integer;
  attribute C_PROBE884_MU_CNT of U0 : label is 1;
  attribute C_PROBE884_TYPE : integer;
  attribute C_PROBE884_TYPE of U0 : label is 1;
  attribute C_PROBE884_WIDTH : integer;
  attribute C_PROBE884_WIDTH of U0 : label is 1;
  attribute C_PROBE885_MU_CNT : integer;
  attribute C_PROBE885_MU_CNT of U0 : label is 1;
  attribute C_PROBE885_TYPE : integer;
  attribute C_PROBE885_TYPE of U0 : label is 1;
  attribute C_PROBE885_WIDTH : integer;
  attribute C_PROBE885_WIDTH of U0 : label is 1;
  attribute C_PROBE886_MU_CNT : integer;
  attribute C_PROBE886_MU_CNT of U0 : label is 1;
  attribute C_PROBE886_TYPE : integer;
  attribute C_PROBE886_TYPE of U0 : label is 1;
  attribute C_PROBE886_WIDTH : integer;
  attribute C_PROBE886_WIDTH of U0 : label is 1;
  attribute C_PROBE887_MU_CNT : integer;
  attribute C_PROBE887_MU_CNT of U0 : label is 1;
  attribute C_PROBE887_TYPE : integer;
  attribute C_PROBE887_TYPE of U0 : label is 1;
  attribute C_PROBE887_WIDTH : integer;
  attribute C_PROBE887_WIDTH of U0 : label is 1;
  attribute C_PROBE888_MU_CNT : integer;
  attribute C_PROBE888_MU_CNT of U0 : label is 1;
  attribute C_PROBE888_TYPE : integer;
  attribute C_PROBE888_TYPE of U0 : label is 1;
  attribute C_PROBE888_WIDTH : integer;
  attribute C_PROBE888_WIDTH of U0 : label is 1;
  attribute C_PROBE889_MU_CNT : integer;
  attribute C_PROBE889_MU_CNT of U0 : label is 1;
  attribute C_PROBE889_TYPE : integer;
  attribute C_PROBE889_TYPE of U0 : label is 1;
  attribute C_PROBE889_WIDTH : integer;
  attribute C_PROBE889_WIDTH of U0 : label is 1;
  attribute C_PROBE88_MU_CNT : integer;
  attribute C_PROBE88_MU_CNT of U0 : label is 1;
  attribute C_PROBE88_TYPE : integer;
  attribute C_PROBE88_TYPE of U0 : label is 1;
  attribute C_PROBE88_WIDTH : integer;
  attribute C_PROBE88_WIDTH of U0 : label is 1;
  attribute C_PROBE890_MU_CNT : integer;
  attribute C_PROBE890_MU_CNT of U0 : label is 1;
  attribute C_PROBE890_TYPE : integer;
  attribute C_PROBE890_TYPE of U0 : label is 1;
  attribute C_PROBE890_WIDTH : integer;
  attribute C_PROBE890_WIDTH of U0 : label is 1;
  attribute C_PROBE891_MU_CNT : integer;
  attribute C_PROBE891_MU_CNT of U0 : label is 1;
  attribute C_PROBE891_TYPE : integer;
  attribute C_PROBE891_TYPE of U0 : label is 1;
  attribute C_PROBE891_WIDTH : integer;
  attribute C_PROBE891_WIDTH of U0 : label is 1;
  attribute C_PROBE892_MU_CNT : integer;
  attribute C_PROBE892_MU_CNT of U0 : label is 1;
  attribute C_PROBE892_TYPE : integer;
  attribute C_PROBE892_TYPE of U0 : label is 1;
  attribute C_PROBE892_WIDTH : integer;
  attribute C_PROBE892_WIDTH of U0 : label is 1;
  attribute C_PROBE893_MU_CNT : integer;
  attribute C_PROBE893_MU_CNT of U0 : label is 1;
  attribute C_PROBE893_TYPE : integer;
  attribute C_PROBE893_TYPE of U0 : label is 1;
  attribute C_PROBE893_WIDTH : integer;
  attribute C_PROBE893_WIDTH of U0 : label is 1;
  attribute C_PROBE894_MU_CNT : integer;
  attribute C_PROBE894_MU_CNT of U0 : label is 1;
  attribute C_PROBE894_TYPE : integer;
  attribute C_PROBE894_TYPE of U0 : label is 1;
  attribute C_PROBE894_WIDTH : integer;
  attribute C_PROBE894_WIDTH of U0 : label is 1;
  attribute C_PROBE895_MU_CNT : integer;
  attribute C_PROBE895_MU_CNT of U0 : label is 1;
  attribute C_PROBE895_TYPE : integer;
  attribute C_PROBE895_TYPE of U0 : label is 1;
  attribute C_PROBE895_WIDTH : integer;
  attribute C_PROBE895_WIDTH of U0 : label is 1;
  attribute C_PROBE896_MU_CNT : integer;
  attribute C_PROBE896_MU_CNT of U0 : label is 1;
  attribute C_PROBE896_TYPE : integer;
  attribute C_PROBE896_TYPE of U0 : label is 1;
  attribute C_PROBE896_WIDTH : integer;
  attribute C_PROBE896_WIDTH of U0 : label is 1;
  attribute C_PROBE897_MU_CNT : integer;
  attribute C_PROBE897_MU_CNT of U0 : label is 1;
  attribute C_PROBE897_TYPE : integer;
  attribute C_PROBE897_TYPE of U0 : label is 1;
  attribute C_PROBE897_WIDTH : integer;
  attribute C_PROBE897_WIDTH of U0 : label is 1;
  attribute C_PROBE898_MU_CNT : integer;
  attribute C_PROBE898_MU_CNT of U0 : label is 1;
  attribute C_PROBE898_TYPE : integer;
  attribute C_PROBE898_TYPE of U0 : label is 1;
  attribute C_PROBE898_WIDTH : integer;
  attribute C_PROBE898_WIDTH of U0 : label is 1;
  attribute C_PROBE899_MU_CNT : integer;
  attribute C_PROBE899_MU_CNT of U0 : label is 1;
  attribute C_PROBE899_TYPE : integer;
  attribute C_PROBE899_TYPE of U0 : label is 1;
  attribute C_PROBE899_WIDTH : integer;
  attribute C_PROBE899_WIDTH of U0 : label is 1;
  attribute C_PROBE89_MU_CNT : integer;
  attribute C_PROBE89_MU_CNT of U0 : label is 1;
  attribute C_PROBE89_TYPE : integer;
  attribute C_PROBE89_TYPE of U0 : label is 1;
  attribute C_PROBE89_WIDTH : integer;
  attribute C_PROBE89_WIDTH of U0 : label is 1;
  attribute C_PROBE8_MU_CNT : integer;
  attribute C_PROBE8_MU_CNT of U0 : label is 1;
  attribute C_PROBE8_TYPE : integer;
  attribute C_PROBE8_TYPE of U0 : label is 1;
  attribute C_PROBE8_WIDTH : integer;
  attribute C_PROBE8_WIDTH of U0 : label is 1;
  attribute C_PROBE900_MU_CNT : integer;
  attribute C_PROBE900_MU_CNT of U0 : label is 1;
  attribute C_PROBE900_TYPE : integer;
  attribute C_PROBE900_TYPE of U0 : label is 1;
  attribute C_PROBE900_WIDTH : integer;
  attribute C_PROBE900_WIDTH of U0 : label is 1;
  attribute C_PROBE901_MU_CNT : integer;
  attribute C_PROBE901_MU_CNT of U0 : label is 1;
  attribute C_PROBE901_TYPE : integer;
  attribute C_PROBE901_TYPE of U0 : label is 1;
  attribute C_PROBE901_WIDTH : integer;
  attribute C_PROBE901_WIDTH of U0 : label is 1;
  attribute C_PROBE902_MU_CNT : integer;
  attribute C_PROBE902_MU_CNT of U0 : label is 1;
  attribute C_PROBE902_TYPE : integer;
  attribute C_PROBE902_TYPE of U0 : label is 1;
  attribute C_PROBE902_WIDTH : integer;
  attribute C_PROBE902_WIDTH of U0 : label is 1;
  attribute C_PROBE903_MU_CNT : integer;
  attribute C_PROBE903_MU_CNT of U0 : label is 1;
  attribute C_PROBE903_TYPE : integer;
  attribute C_PROBE903_TYPE of U0 : label is 1;
  attribute C_PROBE903_WIDTH : integer;
  attribute C_PROBE903_WIDTH of U0 : label is 1;
  attribute C_PROBE904_MU_CNT : integer;
  attribute C_PROBE904_MU_CNT of U0 : label is 1;
  attribute C_PROBE904_TYPE : integer;
  attribute C_PROBE904_TYPE of U0 : label is 1;
  attribute C_PROBE904_WIDTH : integer;
  attribute C_PROBE904_WIDTH of U0 : label is 1;
  attribute C_PROBE905_MU_CNT : integer;
  attribute C_PROBE905_MU_CNT of U0 : label is 1;
  attribute C_PROBE905_TYPE : integer;
  attribute C_PROBE905_TYPE of U0 : label is 1;
  attribute C_PROBE905_WIDTH : integer;
  attribute C_PROBE905_WIDTH of U0 : label is 1;
  attribute C_PROBE906_MU_CNT : integer;
  attribute C_PROBE906_MU_CNT of U0 : label is 1;
  attribute C_PROBE906_TYPE : integer;
  attribute C_PROBE906_TYPE of U0 : label is 1;
  attribute C_PROBE906_WIDTH : integer;
  attribute C_PROBE906_WIDTH of U0 : label is 1;
  attribute C_PROBE907_MU_CNT : integer;
  attribute C_PROBE907_MU_CNT of U0 : label is 1;
  attribute C_PROBE907_TYPE : integer;
  attribute C_PROBE907_TYPE of U0 : label is 1;
  attribute C_PROBE907_WIDTH : integer;
  attribute C_PROBE907_WIDTH of U0 : label is 1;
  attribute C_PROBE908_MU_CNT : integer;
  attribute C_PROBE908_MU_CNT of U0 : label is 1;
  attribute C_PROBE908_TYPE : integer;
  attribute C_PROBE908_TYPE of U0 : label is 1;
  attribute C_PROBE908_WIDTH : integer;
  attribute C_PROBE908_WIDTH of U0 : label is 1;
  attribute C_PROBE909_MU_CNT : integer;
  attribute C_PROBE909_MU_CNT of U0 : label is 1;
  attribute C_PROBE909_TYPE : integer;
  attribute C_PROBE909_TYPE of U0 : label is 1;
  attribute C_PROBE909_WIDTH : integer;
  attribute C_PROBE909_WIDTH of U0 : label is 1;
  attribute C_PROBE90_MU_CNT : integer;
  attribute C_PROBE90_MU_CNT of U0 : label is 1;
  attribute C_PROBE90_TYPE : integer;
  attribute C_PROBE90_TYPE of U0 : label is 1;
  attribute C_PROBE90_WIDTH : integer;
  attribute C_PROBE90_WIDTH of U0 : label is 1;
  attribute C_PROBE910_MU_CNT : integer;
  attribute C_PROBE910_MU_CNT of U0 : label is 1;
  attribute C_PROBE910_TYPE : integer;
  attribute C_PROBE910_TYPE of U0 : label is 1;
  attribute C_PROBE910_WIDTH : integer;
  attribute C_PROBE910_WIDTH of U0 : label is 1;
  attribute C_PROBE911_MU_CNT : integer;
  attribute C_PROBE911_MU_CNT of U0 : label is 1;
  attribute C_PROBE911_TYPE : integer;
  attribute C_PROBE911_TYPE of U0 : label is 1;
  attribute C_PROBE911_WIDTH : integer;
  attribute C_PROBE911_WIDTH of U0 : label is 1;
  attribute C_PROBE912_MU_CNT : integer;
  attribute C_PROBE912_MU_CNT of U0 : label is 1;
  attribute C_PROBE912_TYPE : integer;
  attribute C_PROBE912_TYPE of U0 : label is 1;
  attribute C_PROBE912_WIDTH : integer;
  attribute C_PROBE912_WIDTH of U0 : label is 1;
  attribute C_PROBE913_MU_CNT : integer;
  attribute C_PROBE913_MU_CNT of U0 : label is 1;
  attribute C_PROBE913_TYPE : integer;
  attribute C_PROBE913_TYPE of U0 : label is 1;
  attribute C_PROBE913_WIDTH : integer;
  attribute C_PROBE913_WIDTH of U0 : label is 1;
  attribute C_PROBE914_MU_CNT : integer;
  attribute C_PROBE914_MU_CNT of U0 : label is 1;
  attribute C_PROBE914_TYPE : integer;
  attribute C_PROBE914_TYPE of U0 : label is 1;
  attribute C_PROBE914_WIDTH : integer;
  attribute C_PROBE914_WIDTH of U0 : label is 1;
  attribute C_PROBE915_MU_CNT : integer;
  attribute C_PROBE915_MU_CNT of U0 : label is 1;
  attribute C_PROBE915_TYPE : integer;
  attribute C_PROBE915_TYPE of U0 : label is 1;
  attribute C_PROBE915_WIDTH : integer;
  attribute C_PROBE915_WIDTH of U0 : label is 1;
  attribute C_PROBE916_MU_CNT : integer;
  attribute C_PROBE916_MU_CNT of U0 : label is 1;
  attribute C_PROBE916_TYPE : integer;
  attribute C_PROBE916_TYPE of U0 : label is 1;
  attribute C_PROBE916_WIDTH : integer;
  attribute C_PROBE916_WIDTH of U0 : label is 1;
  attribute C_PROBE917_MU_CNT : integer;
  attribute C_PROBE917_MU_CNT of U0 : label is 1;
  attribute C_PROBE917_TYPE : integer;
  attribute C_PROBE917_TYPE of U0 : label is 1;
  attribute C_PROBE917_WIDTH : integer;
  attribute C_PROBE917_WIDTH of U0 : label is 1;
  attribute C_PROBE918_MU_CNT : integer;
  attribute C_PROBE918_MU_CNT of U0 : label is 1;
  attribute C_PROBE918_TYPE : integer;
  attribute C_PROBE918_TYPE of U0 : label is 1;
  attribute C_PROBE918_WIDTH : integer;
  attribute C_PROBE918_WIDTH of U0 : label is 1;
  attribute C_PROBE919_MU_CNT : integer;
  attribute C_PROBE919_MU_CNT of U0 : label is 1;
  attribute C_PROBE919_TYPE : integer;
  attribute C_PROBE919_TYPE of U0 : label is 1;
  attribute C_PROBE919_WIDTH : integer;
  attribute C_PROBE919_WIDTH of U0 : label is 1;
  attribute C_PROBE91_MU_CNT : integer;
  attribute C_PROBE91_MU_CNT of U0 : label is 1;
  attribute C_PROBE91_TYPE : integer;
  attribute C_PROBE91_TYPE of U0 : label is 1;
  attribute C_PROBE91_WIDTH : integer;
  attribute C_PROBE91_WIDTH of U0 : label is 1;
  attribute C_PROBE920_MU_CNT : integer;
  attribute C_PROBE920_MU_CNT of U0 : label is 1;
  attribute C_PROBE920_TYPE : integer;
  attribute C_PROBE920_TYPE of U0 : label is 1;
  attribute C_PROBE920_WIDTH : integer;
  attribute C_PROBE920_WIDTH of U0 : label is 1;
  attribute C_PROBE921_MU_CNT : integer;
  attribute C_PROBE921_MU_CNT of U0 : label is 1;
  attribute C_PROBE921_TYPE : integer;
  attribute C_PROBE921_TYPE of U0 : label is 1;
  attribute C_PROBE921_WIDTH : integer;
  attribute C_PROBE921_WIDTH of U0 : label is 1;
  attribute C_PROBE922_MU_CNT : integer;
  attribute C_PROBE922_MU_CNT of U0 : label is 1;
  attribute C_PROBE922_TYPE : integer;
  attribute C_PROBE922_TYPE of U0 : label is 1;
  attribute C_PROBE922_WIDTH : integer;
  attribute C_PROBE922_WIDTH of U0 : label is 1;
  attribute C_PROBE923_MU_CNT : integer;
  attribute C_PROBE923_MU_CNT of U0 : label is 1;
  attribute C_PROBE923_TYPE : integer;
  attribute C_PROBE923_TYPE of U0 : label is 1;
  attribute C_PROBE923_WIDTH : integer;
  attribute C_PROBE923_WIDTH of U0 : label is 1;
  attribute C_PROBE924_MU_CNT : integer;
  attribute C_PROBE924_MU_CNT of U0 : label is 1;
  attribute C_PROBE924_TYPE : integer;
  attribute C_PROBE924_TYPE of U0 : label is 1;
  attribute C_PROBE924_WIDTH : integer;
  attribute C_PROBE924_WIDTH of U0 : label is 1;
  attribute C_PROBE925_MU_CNT : integer;
  attribute C_PROBE925_MU_CNT of U0 : label is 1;
  attribute C_PROBE925_TYPE : integer;
  attribute C_PROBE925_TYPE of U0 : label is 1;
  attribute C_PROBE925_WIDTH : integer;
  attribute C_PROBE925_WIDTH of U0 : label is 1;
  attribute C_PROBE926_MU_CNT : integer;
  attribute C_PROBE926_MU_CNT of U0 : label is 1;
  attribute C_PROBE926_TYPE : integer;
  attribute C_PROBE926_TYPE of U0 : label is 1;
  attribute C_PROBE926_WIDTH : integer;
  attribute C_PROBE926_WIDTH of U0 : label is 1;
  attribute C_PROBE927_MU_CNT : integer;
  attribute C_PROBE927_MU_CNT of U0 : label is 1;
  attribute C_PROBE927_TYPE : integer;
  attribute C_PROBE927_TYPE of U0 : label is 1;
  attribute C_PROBE927_WIDTH : integer;
  attribute C_PROBE927_WIDTH of U0 : label is 1;
  attribute C_PROBE928_MU_CNT : integer;
  attribute C_PROBE928_MU_CNT of U0 : label is 1;
  attribute C_PROBE928_TYPE : integer;
  attribute C_PROBE928_TYPE of U0 : label is 1;
  attribute C_PROBE928_WIDTH : integer;
  attribute C_PROBE928_WIDTH of U0 : label is 1;
  attribute C_PROBE929_MU_CNT : integer;
  attribute C_PROBE929_MU_CNT of U0 : label is 1;
  attribute C_PROBE929_TYPE : integer;
  attribute C_PROBE929_TYPE of U0 : label is 1;
  attribute C_PROBE929_WIDTH : integer;
  attribute C_PROBE929_WIDTH of U0 : label is 1;
  attribute C_PROBE92_MU_CNT : integer;
  attribute C_PROBE92_MU_CNT of U0 : label is 1;
  attribute C_PROBE92_TYPE : integer;
  attribute C_PROBE92_TYPE of U0 : label is 1;
  attribute C_PROBE92_WIDTH : integer;
  attribute C_PROBE92_WIDTH of U0 : label is 1;
  attribute C_PROBE930_MU_CNT : integer;
  attribute C_PROBE930_MU_CNT of U0 : label is 1;
  attribute C_PROBE930_TYPE : integer;
  attribute C_PROBE930_TYPE of U0 : label is 1;
  attribute C_PROBE930_WIDTH : integer;
  attribute C_PROBE930_WIDTH of U0 : label is 1;
  attribute C_PROBE931_MU_CNT : integer;
  attribute C_PROBE931_MU_CNT of U0 : label is 1;
  attribute C_PROBE931_TYPE : integer;
  attribute C_PROBE931_TYPE of U0 : label is 1;
  attribute C_PROBE931_WIDTH : integer;
  attribute C_PROBE931_WIDTH of U0 : label is 1;
  attribute C_PROBE932_MU_CNT : integer;
  attribute C_PROBE932_MU_CNT of U0 : label is 1;
  attribute C_PROBE932_TYPE : integer;
  attribute C_PROBE932_TYPE of U0 : label is 1;
  attribute C_PROBE932_WIDTH : integer;
  attribute C_PROBE932_WIDTH of U0 : label is 1;
  attribute C_PROBE933_MU_CNT : integer;
  attribute C_PROBE933_MU_CNT of U0 : label is 1;
  attribute C_PROBE933_TYPE : integer;
  attribute C_PROBE933_TYPE of U0 : label is 1;
  attribute C_PROBE933_WIDTH : integer;
  attribute C_PROBE933_WIDTH of U0 : label is 1;
  attribute C_PROBE934_MU_CNT : integer;
  attribute C_PROBE934_MU_CNT of U0 : label is 1;
  attribute C_PROBE934_TYPE : integer;
  attribute C_PROBE934_TYPE of U0 : label is 1;
  attribute C_PROBE934_WIDTH : integer;
  attribute C_PROBE934_WIDTH of U0 : label is 1;
  attribute C_PROBE935_MU_CNT : integer;
  attribute C_PROBE935_MU_CNT of U0 : label is 1;
  attribute C_PROBE935_TYPE : integer;
  attribute C_PROBE935_TYPE of U0 : label is 1;
  attribute C_PROBE935_WIDTH : integer;
  attribute C_PROBE935_WIDTH of U0 : label is 1;
  attribute C_PROBE936_MU_CNT : integer;
  attribute C_PROBE936_MU_CNT of U0 : label is 1;
  attribute C_PROBE936_TYPE : integer;
  attribute C_PROBE936_TYPE of U0 : label is 1;
  attribute C_PROBE936_WIDTH : integer;
  attribute C_PROBE936_WIDTH of U0 : label is 1;
  attribute C_PROBE937_MU_CNT : integer;
  attribute C_PROBE937_MU_CNT of U0 : label is 1;
  attribute C_PROBE937_TYPE : integer;
  attribute C_PROBE937_TYPE of U0 : label is 1;
  attribute C_PROBE937_WIDTH : integer;
  attribute C_PROBE937_WIDTH of U0 : label is 1;
  attribute C_PROBE938_MU_CNT : integer;
  attribute C_PROBE938_MU_CNT of U0 : label is 1;
  attribute C_PROBE938_TYPE : integer;
  attribute C_PROBE938_TYPE of U0 : label is 1;
  attribute C_PROBE938_WIDTH : integer;
  attribute C_PROBE938_WIDTH of U0 : label is 1;
  attribute C_PROBE939_MU_CNT : integer;
  attribute C_PROBE939_MU_CNT of U0 : label is 1;
  attribute C_PROBE939_TYPE : integer;
  attribute C_PROBE939_TYPE of U0 : label is 1;
  attribute C_PROBE939_WIDTH : integer;
  attribute C_PROBE939_WIDTH of U0 : label is 1;
  attribute C_PROBE93_MU_CNT : integer;
  attribute C_PROBE93_MU_CNT of U0 : label is 1;
  attribute C_PROBE93_TYPE : integer;
  attribute C_PROBE93_TYPE of U0 : label is 1;
  attribute C_PROBE93_WIDTH : integer;
  attribute C_PROBE93_WIDTH of U0 : label is 1;
  attribute C_PROBE940_MU_CNT : integer;
  attribute C_PROBE940_MU_CNT of U0 : label is 1;
  attribute C_PROBE940_TYPE : integer;
  attribute C_PROBE940_TYPE of U0 : label is 1;
  attribute C_PROBE940_WIDTH : integer;
  attribute C_PROBE940_WIDTH of U0 : label is 1;
  attribute C_PROBE941_MU_CNT : integer;
  attribute C_PROBE941_MU_CNT of U0 : label is 1;
  attribute C_PROBE941_TYPE : integer;
  attribute C_PROBE941_TYPE of U0 : label is 1;
  attribute C_PROBE941_WIDTH : integer;
  attribute C_PROBE941_WIDTH of U0 : label is 1;
  attribute C_PROBE942_MU_CNT : integer;
  attribute C_PROBE942_MU_CNT of U0 : label is 1;
  attribute C_PROBE942_TYPE : integer;
  attribute C_PROBE942_TYPE of U0 : label is 1;
  attribute C_PROBE942_WIDTH : integer;
  attribute C_PROBE942_WIDTH of U0 : label is 1;
  attribute C_PROBE943_MU_CNT : integer;
  attribute C_PROBE943_MU_CNT of U0 : label is 1;
  attribute C_PROBE943_TYPE : integer;
  attribute C_PROBE943_TYPE of U0 : label is 1;
  attribute C_PROBE943_WIDTH : integer;
  attribute C_PROBE943_WIDTH of U0 : label is 1;
  attribute C_PROBE944_MU_CNT : integer;
  attribute C_PROBE944_MU_CNT of U0 : label is 1;
  attribute C_PROBE944_TYPE : integer;
  attribute C_PROBE944_TYPE of U0 : label is 1;
  attribute C_PROBE944_WIDTH : integer;
  attribute C_PROBE944_WIDTH of U0 : label is 1;
  attribute C_PROBE945_MU_CNT : integer;
  attribute C_PROBE945_MU_CNT of U0 : label is 1;
  attribute C_PROBE945_TYPE : integer;
  attribute C_PROBE945_TYPE of U0 : label is 1;
  attribute C_PROBE945_WIDTH : integer;
  attribute C_PROBE945_WIDTH of U0 : label is 1;
  attribute C_PROBE946_MU_CNT : integer;
  attribute C_PROBE946_MU_CNT of U0 : label is 1;
  attribute C_PROBE946_TYPE : integer;
  attribute C_PROBE946_TYPE of U0 : label is 1;
  attribute C_PROBE946_WIDTH : integer;
  attribute C_PROBE946_WIDTH of U0 : label is 1;
  attribute C_PROBE947_MU_CNT : integer;
  attribute C_PROBE947_MU_CNT of U0 : label is 1;
  attribute C_PROBE947_TYPE : integer;
  attribute C_PROBE947_TYPE of U0 : label is 1;
  attribute C_PROBE947_WIDTH : integer;
  attribute C_PROBE947_WIDTH of U0 : label is 1;
  attribute C_PROBE948_MU_CNT : integer;
  attribute C_PROBE948_MU_CNT of U0 : label is 1;
  attribute C_PROBE948_TYPE : integer;
  attribute C_PROBE948_TYPE of U0 : label is 1;
  attribute C_PROBE948_WIDTH : integer;
  attribute C_PROBE948_WIDTH of U0 : label is 1;
  attribute C_PROBE949_MU_CNT : integer;
  attribute C_PROBE949_MU_CNT of U0 : label is 1;
  attribute C_PROBE949_TYPE : integer;
  attribute C_PROBE949_TYPE of U0 : label is 1;
  attribute C_PROBE949_WIDTH : integer;
  attribute C_PROBE949_WIDTH of U0 : label is 1;
  attribute C_PROBE94_MU_CNT : integer;
  attribute C_PROBE94_MU_CNT of U0 : label is 1;
  attribute C_PROBE94_TYPE : integer;
  attribute C_PROBE94_TYPE of U0 : label is 1;
  attribute C_PROBE94_WIDTH : integer;
  attribute C_PROBE94_WIDTH of U0 : label is 1;
  attribute C_PROBE950_MU_CNT : integer;
  attribute C_PROBE950_MU_CNT of U0 : label is 1;
  attribute C_PROBE950_TYPE : integer;
  attribute C_PROBE950_TYPE of U0 : label is 1;
  attribute C_PROBE950_WIDTH : integer;
  attribute C_PROBE950_WIDTH of U0 : label is 1;
  attribute C_PROBE951_MU_CNT : integer;
  attribute C_PROBE951_MU_CNT of U0 : label is 1;
  attribute C_PROBE951_TYPE : integer;
  attribute C_PROBE951_TYPE of U0 : label is 1;
  attribute C_PROBE951_WIDTH : integer;
  attribute C_PROBE951_WIDTH of U0 : label is 1;
  attribute C_PROBE952_MU_CNT : integer;
  attribute C_PROBE952_MU_CNT of U0 : label is 1;
  attribute C_PROBE952_TYPE : integer;
  attribute C_PROBE952_TYPE of U0 : label is 1;
  attribute C_PROBE952_WIDTH : integer;
  attribute C_PROBE952_WIDTH of U0 : label is 1;
  attribute C_PROBE953_MU_CNT : integer;
  attribute C_PROBE953_MU_CNT of U0 : label is 1;
  attribute C_PROBE953_TYPE : integer;
  attribute C_PROBE953_TYPE of U0 : label is 1;
  attribute C_PROBE953_WIDTH : integer;
  attribute C_PROBE953_WIDTH of U0 : label is 1;
  attribute C_PROBE954_MU_CNT : integer;
  attribute C_PROBE954_MU_CNT of U0 : label is 1;
  attribute C_PROBE954_TYPE : integer;
  attribute C_PROBE954_TYPE of U0 : label is 1;
  attribute C_PROBE954_WIDTH : integer;
  attribute C_PROBE954_WIDTH of U0 : label is 1;
  attribute C_PROBE955_MU_CNT : integer;
  attribute C_PROBE955_MU_CNT of U0 : label is 1;
  attribute C_PROBE955_TYPE : integer;
  attribute C_PROBE955_TYPE of U0 : label is 1;
  attribute C_PROBE955_WIDTH : integer;
  attribute C_PROBE955_WIDTH of U0 : label is 1;
  attribute C_PROBE956_MU_CNT : integer;
  attribute C_PROBE956_MU_CNT of U0 : label is 1;
  attribute C_PROBE956_TYPE : integer;
  attribute C_PROBE956_TYPE of U0 : label is 1;
  attribute C_PROBE956_WIDTH : integer;
  attribute C_PROBE956_WIDTH of U0 : label is 1;
  attribute C_PROBE957_MU_CNT : integer;
  attribute C_PROBE957_MU_CNT of U0 : label is 1;
  attribute C_PROBE957_TYPE : integer;
  attribute C_PROBE957_TYPE of U0 : label is 1;
  attribute C_PROBE957_WIDTH : integer;
  attribute C_PROBE957_WIDTH of U0 : label is 1;
  attribute C_PROBE958_MU_CNT : integer;
  attribute C_PROBE958_MU_CNT of U0 : label is 1;
  attribute C_PROBE958_TYPE : integer;
  attribute C_PROBE958_TYPE of U0 : label is 1;
  attribute C_PROBE958_WIDTH : integer;
  attribute C_PROBE958_WIDTH of U0 : label is 1;
  attribute C_PROBE959_MU_CNT : integer;
  attribute C_PROBE959_MU_CNT of U0 : label is 1;
  attribute C_PROBE959_TYPE : integer;
  attribute C_PROBE959_TYPE of U0 : label is 1;
  attribute C_PROBE959_WIDTH : integer;
  attribute C_PROBE959_WIDTH of U0 : label is 1;
  attribute C_PROBE95_MU_CNT : integer;
  attribute C_PROBE95_MU_CNT of U0 : label is 1;
  attribute C_PROBE95_TYPE : integer;
  attribute C_PROBE95_TYPE of U0 : label is 1;
  attribute C_PROBE95_WIDTH : integer;
  attribute C_PROBE95_WIDTH of U0 : label is 1;
  attribute C_PROBE960_MU_CNT : integer;
  attribute C_PROBE960_MU_CNT of U0 : label is 1;
  attribute C_PROBE960_TYPE : integer;
  attribute C_PROBE960_TYPE of U0 : label is 1;
  attribute C_PROBE960_WIDTH : integer;
  attribute C_PROBE960_WIDTH of U0 : label is 1;
  attribute C_PROBE961_MU_CNT : integer;
  attribute C_PROBE961_MU_CNT of U0 : label is 1;
  attribute C_PROBE961_TYPE : integer;
  attribute C_PROBE961_TYPE of U0 : label is 1;
  attribute C_PROBE961_WIDTH : integer;
  attribute C_PROBE961_WIDTH of U0 : label is 1;
  attribute C_PROBE962_MU_CNT : integer;
  attribute C_PROBE962_MU_CNT of U0 : label is 1;
  attribute C_PROBE962_TYPE : integer;
  attribute C_PROBE962_TYPE of U0 : label is 1;
  attribute C_PROBE962_WIDTH : integer;
  attribute C_PROBE962_WIDTH of U0 : label is 1;
  attribute C_PROBE963_MU_CNT : integer;
  attribute C_PROBE963_MU_CNT of U0 : label is 1;
  attribute C_PROBE963_TYPE : integer;
  attribute C_PROBE963_TYPE of U0 : label is 1;
  attribute C_PROBE963_WIDTH : integer;
  attribute C_PROBE963_WIDTH of U0 : label is 1;
  attribute C_PROBE964_MU_CNT : integer;
  attribute C_PROBE964_MU_CNT of U0 : label is 1;
  attribute C_PROBE964_TYPE : integer;
  attribute C_PROBE964_TYPE of U0 : label is 1;
  attribute C_PROBE964_WIDTH : integer;
  attribute C_PROBE964_WIDTH of U0 : label is 1;
  attribute C_PROBE965_MU_CNT : integer;
  attribute C_PROBE965_MU_CNT of U0 : label is 1;
  attribute C_PROBE965_TYPE : integer;
  attribute C_PROBE965_TYPE of U0 : label is 1;
  attribute C_PROBE965_WIDTH : integer;
  attribute C_PROBE965_WIDTH of U0 : label is 1;
  attribute C_PROBE966_MU_CNT : integer;
  attribute C_PROBE966_MU_CNT of U0 : label is 1;
  attribute C_PROBE966_TYPE : integer;
  attribute C_PROBE966_TYPE of U0 : label is 1;
  attribute C_PROBE966_WIDTH : integer;
  attribute C_PROBE966_WIDTH of U0 : label is 1;
  attribute C_PROBE967_MU_CNT : integer;
  attribute C_PROBE967_MU_CNT of U0 : label is 1;
  attribute C_PROBE967_TYPE : integer;
  attribute C_PROBE967_TYPE of U0 : label is 1;
  attribute C_PROBE967_WIDTH : integer;
  attribute C_PROBE967_WIDTH of U0 : label is 1;
  attribute C_PROBE968_MU_CNT : integer;
  attribute C_PROBE968_MU_CNT of U0 : label is 1;
  attribute C_PROBE968_TYPE : integer;
  attribute C_PROBE968_TYPE of U0 : label is 1;
  attribute C_PROBE968_WIDTH : integer;
  attribute C_PROBE968_WIDTH of U0 : label is 1;
  attribute C_PROBE969_MU_CNT : integer;
  attribute C_PROBE969_MU_CNT of U0 : label is 1;
  attribute C_PROBE969_TYPE : integer;
  attribute C_PROBE969_TYPE of U0 : label is 1;
  attribute C_PROBE969_WIDTH : integer;
  attribute C_PROBE969_WIDTH of U0 : label is 1;
  attribute C_PROBE96_MU_CNT : integer;
  attribute C_PROBE96_MU_CNT of U0 : label is 1;
  attribute C_PROBE96_TYPE : integer;
  attribute C_PROBE96_TYPE of U0 : label is 1;
  attribute C_PROBE96_WIDTH : integer;
  attribute C_PROBE96_WIDTH of U0 : label is 1;
  attribute C_PROBE970_MU_CNT : integer;
  attribute C_PROBE970_MU_CNT of U0 : label is 1;
  attribute C_PROBE970_TYPE : integer;
  attribute C_PROBE970_TYPE of U0 : label is 1;
  attribute C_PROBE970_WIDTH : integer;
  attribute C_PROBE970_WIDTH of U0 : label is 1;
  attribute C_PROBE971_MU_CNT : integer;
  attribute C_PROBE971_MU_CNT of U0 : label is 1;
  attribute C_PROBE971_TYPE : integer;
  attribute C_PROBE971_TYPE of U0 : label is 1;
  attribute C_PROBE971_WIDTH : integer;
  attribute C_PROBE971_WIDTH of U0 : label is 1;
  attribute C_PROBE972_MU_CNT : integer;
  attribute C_PROBE972_MU_CNT of U0 : label is 1;
  attribute C_PROBE972_TYPE : integer;
  attribute C_PROBE972_TYPE of U0 : label is 1;
  attribute C_PROBE972_WIDTH : integer;
  attribute C_PROBE972_WIDTH of U0 : label is 1;
  attribute C_PROBE973_MU_CNT : integer;
  attribute C_PROBE973_MU_CNT of U0 : label is 1;
  attribute C_PROBE973_TYPE : integer;
  attribute C_PROBE973_TYPE of U0 : label is 1;
  attribute C_PROBE973_WIDTH : integer;
  attribute C_PROBE973_WIDTH of U0 : label is 1;
  attribute C_PROBE974_MU_CNT : integer;
  attribute C_PROBE974_MU_CNT of U0 : label is 1;
  attribute C_PROBE974_TYPE : integer;
  attribute C_PROBE974_TYPE of U0 : label is 1;
  attribute C_PROBE974_WIDTH : integer;
  attribute C_PROBE974_WIDTH of U0 : label is 1;
  attribute C_PROBE975_MU_CNT : integer;
  attribute C_PROBE975_MU_CNT of U0 : label is 1;
  attribute C_PROBE975_TYPE : integer;
  attribute C_PROBE975_TYPE of U0 : label is 1;
  attribute C_PROBE975_WIDTH : integer;
  attribute C_PROBE975_WIDTH of U0 : label is 1;
  attribute C_PROBE976_MU_CNT : integer;
  attribute C_PROBE976_MU_CNT of U0 : label is 1;
  attribute C_PROBE976_TYPE : integer;
  attribute C_PROBE976_TYPE of U0 : label is 1;
  attribute C_PROBE976_WIDTH : integer;
  attribute C_PROBE976_WIDTH of U0 : label is 1;
  attribute C_PROBE977_MU_CNT : integer;
  attribute C_PROBE977_MU_CNT of U0 : label is 1;
  attribute C_PROBE977_TYPE : integer;
  attribute C_PROBE977_TYPE of U0 : label is 1;
  attribute C_PROBE977_WIDTH : integer;
  attribute C_PROBE977_WIDTH of U0 : label is 1;
  attribute C_PROBE978_MU_CNT : integer;
  attribute C_PROBE978_MU_CNT of U0 : label is 1;
  attribute C_PROBE978_TYPE : integer;
  attribute C_PROBE978_TYPE of U0 : label is 1;
  attribute C_PROBE978_WIDTH : integer;
  attribute C_PROBE978_WIDTH of U0 : label is 1;
  attribute C_PROBE979_MU_CNT : integer;
  attribute C_PROBE979_MU_CNT of U0 : label is 1;
  attribute C_PROBE979_TYPE : integer;
  attribute C_PROBE979_TYPE of U0 : label is 1;
  attribute C_PROBE979_WIDTH : integer;
  attribute C_PROBE979_WIDTH of U0 : label is 1;
  attribute C_PROBE97_MU_CNT : integer;
  attribute C_PROBE97_MU_CNT of U0 : label is 1;
  attribute C_PROBE97_TYPE : integer;
  attribute C_PROBE97_TYPE of U0 : label is 1;
  attribute C_PROBE97_WIDTH : integer;
  attribute C_PROBE97_WIDTH of U0 : label is 1;
  attribute C_PROBE980_MU_CNT : integer;
  attribute C_PROBE980_MU_CNT of U0 : label is 1;
  attribute C_PROBE980_TYPE : integer;
  attribute C_PROBE980_TYPE of U0 : label is 1;
  attribute C_PROBE980_WIDTH : integer;
  attribute C_PROBE980_WIDTH of U0 : label is 1;
  attribute C_PROBE981_MU_CNT : integer;
  attribute C_PROBE981_MU_CNT of U0 : label is 1;
  attribute C_PROBE981_TYPE : integer;
  attribute C_PROBE981_TYPE of U0 : label is 1;
  attribute C_PROBE981_WIDTH : integer;
  attribute C_PROBE981_WIDTH of U0 : label is 1;
  attribute C_PROBE982_MU_CNT : integer;
  attribute C_PROBE982_MU_CNT of U0 : label is 1;
  attribute C_PROBE982_TYPE : integer;
  attribute C_PROBE982_TYPE of U0 : label is 1;
  attribute C_PROBE982_WIDTH : integer;
  attribute C_PROBE982_WIDTH of U0 : label is 1;
  attribute C_PROBE983_MU_CNT : integer;
  attribute C_PROBE983_MU_CNT of U0 : label is 1;
  attribute C_PROBE983_TYPE : integer;
  attribute C_PROBE983_TYPE of U0 : label is 1;
  attribute C_PROBE983_WIDTH : integer;
  attribute C_PROBE983_WIDTH of U0 : label is 1;
  attribute C_PROBE984_MU_CNT : integer;
  attribute C_PROBE984_MU_CNT of U0 : label is 1;
  attribute C_PROBE984_TYPE : integer;
  attribute C_PROBE984_TYPE of U0 : label is 1;
  attribute C_PROBE984_WIDTH : integer;
  attribute C_PROBE984_WIDTH of U0 : label is 1;
  attribute C_PROBE985_MU_CNT : integer;
  attribute C_PROBE985_MU_CNT of U0 : label is 1;
  attribute C_PROBE985_TYPE : integer;
  attribute C_PROBE985_TYPE of U0 : label is 1;
  attribute C_PROBE985_WIDTH : integer;
  attribute C_PROBE985_WIDTH of U0 : label is 1;
  attribute C_PROBE986_MU_CNT : integer;
  attribute C_PROBE986_MU_CNT of U0 : label is 1;
  attribute C_PROBE986_TYPE : integer;
  attribute C_PROBE986_TYPE of U0 : label is 1;
  attribute C_PROBE986_WIDTH : integer;
  attribute C_PROBE986_WIDTH of U0 : label is 1;
  attribute C_PROBE987_MU_CNT : integer;
  attribute C_PROBE987_MU_CNT of U0 : label is 1;
  attribute C_PROBE987_TYPE : integer;
  attribute C_PROBE987_TYPE of U0 : label is 1;
  attribute C_PROBE987_WIDTH : integer;
  attribute C_PROBE987_WIDTH of U0 : label is 1;
  attribute C_PROBE988_MU_CNT : integer;
  attribute C_PROBE988_MU_CNT of U0 : label is 1;
  attribute C_PROBE988_TYPE : integer;
  attribute C_PROBE988_TYPE of U0 : label is 1;
  attribute C_PROBE988_WIDTH : integer;
  attribute C_PROBE988_WIDTH of U0 : label is 1;
  attribute C_PROBE989_MU_CNT : integer;
  attribute C_PROBE989_MU_CNT of U0 : label is 1;
  attribute C_PROBE989_TYPE : integer;
  attribute C_PROBE989_TYPE of U0 : label is 1;
  attribute C_PROBE989_WIDTH : integer;
  attribute C_PROBE989_WIDTH of U0 : label is 1;
  attribute C_PROBE98_MU_CNT : integer;
  attribute C_PROBE98_MU_CNT of U0 : label is 1;
  attribute C_PROBE98_TYPE : integer;
  attribute C_PROBE98_TYPE of U0 : label is 1;
  attribute C_PROBE98_WIDTH : integer;
  attribute C_PROBE98_WIDTH of U0 : label is 1;
  attribute C_PROBE990_MU_CNT : integer;
  attribute C_PROBE990_MU_CNT of U0 : label is 1;
  attribute C_PROBE990_TYPE : integer;
  attribute C_PROBE990_TYPE of U0 : label is 1;
  attribute C_PROBE990_WIDTH : integer;
  attribute C_PROBE990_WIDTH of U0 : label is 1;
  attribute C_PROBE991_MU_CNT : integer;
  attribute C_PROBE991_MU_CNT of U0 : label is 1;
  attribute C_PROBE991_TYPE : integer;
  attribute C_PROBE991_TYPE of U0 : label is 1;
  attribute C_PROBE991_WIDTH : integer;
  attribute C_PROBE991_WIDTH of U0 : label is 1;
  attribute C_PROBE992_MU_CNT : integer;
  attribute C_PROBE992_MU_CNT of U0 : label is 1;
  attribute C_PROBE992_TYPE : integer;
  attribute C_PROBE992_TYPE of U0 : label is 1;
  attribute C_PROBE992_WIDTH : integer;
  attribute C_PROBE992_WIDTH of U0 : label is 1;
  attribute C_PROBE993_MU_CNT : integer;
  attribute C_PROBE993_MU_CNT of U0 : label is 1;
  attribute C_PROBE993_TYPE : integer;
  attribute C_PROBE993_TYPE of U0 : label is 1;
  attribute C_PROBE993_WIDTH : integer;
  attribute C_PROBE993_WIDTH of U0 : label is 1;
  attribute C_PROBE994_MU_CNT : integer;
  attribute C_PROBE994_MU_CNT of U0 : label is 1;
  attribute C_PROBE994_TYPE : integer;
  attribute C_PROBE994_TYPE of U0 : label is 1;
  attribute C_PROBE994_WIDTH : integer;
  attribute C_PROBE994_WIDTH of U0 : label is 1;
  attribute C_PROBE995_MU_CNT : integer;
  attribute C_PROBE995_MU_CNT of U0 : label is 1;
  attribute C_PROBE995_TYPE : integer;
  attribute C_PROBE995_TYPE of U0 : label is 1;
  attribute C_PROBE995_WIDTH : integer;
  attribute C_PROBE995_WIDTH of U0 : label is 1;
  attribute C_PROBE996_MU_CNT : integer;
  attribute C_PROBE996_MU_CNT of U0 : label is 1;
  attribute C_PROBE996_TYPE : integer;
  attribute C_PROBE996_TYPE of U0 : label is 1;
  attribute C_PROBE996_WIDTH : integer;
  attribute C_PROBE996_WIDTH of U0 : label is 1;
  attribute C_PROBE997_MU_CNT : integer;
  attribute C_PROBE997_MU_CNT of U0 : label is 1;
  attribute C_PROBE997_TYPE : integer;
  attribute C_PROBE997_TYPE of U0 : label is 1;
  attribute C_PROBE997_WIDTH : integer;
  attribute C_PROBE997_WIDTH of U0 : label is 1;
  attribute C_PROBE998_MU_CNT : integer;
  attribute C_PROBE998_MU_CNT of U0 : label is 1;
  attribute C_PROBE998_TYPE : integer;
  attribute C_PROBE998_TYPE of U0 : label is 1;
  attribute C_PROBE998_WIDTH : integer;
  attribute C_PROBE998_WIDTH of U0 : label is 1;
  attribute C_PROBE999_MU_CNT : integer;
  attribute C_PROBE999_MU_CNT of U0 : label is 1;
  attribute C_PROBE999_TYPE : integer;
  attribute C_PROBE999_TYPE of U0 : label is 1;
  attribute C_PROBE999_WIDTH : integer;
  attribute C_PROBE999_WIDTH of U0 : label is 1;
  attribute C_PROBE99_MU_CNT : integer;
  attribute C_PROBE99_MU_CNT of U0 : label is 1;
  attribute C_PROBE99_TYPE : integer;
  attribute C_PROBE99_TYPE of U0 : label is 1;
  attribute C_PROBE99_WIDTH : integer;
  attribute C_PROBE99_WIDTH of U0 : label is 1;
  attribute C_PROBE9_MU_CNT : integer;
  attribute C_PROBE9_MU_CNT of U0 : label is 1;
  attribute C_PROBE9_TYPE : integer;
  attribute C_PROBE9_TYPE of U0 : label is 1;
  attribute C_PROBE9_WIDTH : integer;
  attribute C_PROBE9_WIDTH of U0 : label is 1;
  attribute C_RAM_STYLE : string;
  attribute C_RAM_STYLE of U0 : label is "SUBCORE";
  attribute C_SLOT_0_AXIS_TDEST_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TDEST_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXIS_TID_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TID_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXIS_TUSER_WIDTH : integer;
  attribute C_SLOT_0_AXIS_TUSER_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_ARUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_ARUSER_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_AWUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_AWUSER_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_BUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_BUSER_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_ID_WIDTH : integer;
  attribute C_SLOT_0_AXI_ID_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_PROTOCOL : string;
  attribute C_SLOT_0_AXI_PROTOCOL of U0 : label is "AXI4";
  attribute C_SLOT_0_AXI_RUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_RUSER_WIDTH of U0 : label is 1;
  attribute C_SLOT_0_AXI_WUSER_WIDTH : integer;
  attribute C_SLOT_0_AXI_WUSER_WIDTH of U0 : label is 1;
  attribute C_TC_TYPE : integer;
  attribute C_TC_TYPE of U0 : label is 0;
  attribute C_TIME_TAG_WIDTH : integer;
  attribute C_TIME_TAG_WIDTH of U0 : label is 32;
  attribute C_TRIGIN_EN : integer;
  attribute C_TRIGIN_EN of U0 : label is 0;
  attribute C_TRIGOUT_EN : integer;
  attribute C_TRIGOUT_EN of U0 : label is 0;
  attribute C_USE_TEST_REG : integer;
  attribute C_USE_TEST_REG of U0 : label is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "virtex7";
  attribute C_XLNX_HW_PROBE_INFO : string;
  attribute C_XLNX_HW_PROBE_INFO of U0 : label is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY1 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY1 of U0 : label is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY2 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY2 of U0 : label is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY3 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY3 of U0 : label is "DEFAULT";
  attribute C_XLNX_HW_PROBE_INFO_DUMMY4 : string;
  attribute C_XLNX_HW_PROBE_INFO_DUMMY4 of U0 : label is "DEFAULT";
  attribute C_XSDB_SLAVE_TYPE : integer;
  attribute C_XSDB_SLAVE_TYPE of U0 : label is 17;
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute IS_DEBUG_CORE : string;
  attribute IS_DEBUG_CORE of U0 : label is "TRUE";
  attribute LC_COMPUTED_DATA_WIDTH : integer;
  attribute LC_COMPUTED_DATA_WIDTH of U0 : label is 138;
  attribute LC_DATA_WIDTH : integer;
  attribute LC_DATA_WIDTH of U0 : label is 138;
  attribute LC_MATCH_TPID_VEC : string;
  attribute LC_MATCH_TPID_VEC of U0 : label is "1536'b000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
  attribute LC_MU_CNT_STRING : string;
  attribute LC_MU_CNT_STRING of U0 : label is "4096' ";
  attribute LC_MU_COUNT : integer;
  attribute LC_MU_COUNT of U0 : label is 6;
  attribute LC_MU_COUNT_EN : integer;
  attribute LC_MU_COUNT_EN of U0 : label is 6;
  attribute LC_NUM_OF_PROBES : integer;
  attribute LC_NUM_OF_PROBES of U0 : label is 6;
  attribute LC_NUM_PROBES : integer;
  attribute LC_NUM_PROBES of U0 : label is 6;
  attribute LC_NUM_TRIG_EQS : integer;
  attribute LC_NUM_TRIG_EQS of U0 : label is 1;
  attribute LC_PROBE0_IS_DATA : string;
  attribute LC_PROBE0_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE0_IS_TRIG : string;
  attribute LC_PROBE0_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE0_MU_CNT : integer;
  attribute LC_PROBE0_MU_CNT of U0 : label is 1;
  attribute LC_PROBE0_PID : string;
  attribute LC_PROBE0_PID of U0 : label is "16'b0000000000000000";
  attribute LC_PROBE0_TYPE : integer;
  attribute LC_PROBE0_TYPE of U0 : label is 0;
  attribute LC_PROBE0_WIDTH : integer;
  attribute LC_PROBE0_WIDTH of U0 : label is 64;
  attribute LC_PROBE1000_IS_DATA : string;
  attribute LC_PROBE1000_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1000_IS_TRIG : string;
  attribute LC_PROBE1000_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1000_MU_CNT : integer;
  attribute LC_PROBE1000_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1000_PID : string;
  attribute LC_PROBE1000_PID of U0 : label is "16'b0000001111101000";
  attribute LC_PROBE1000_TYPE : integer;
  attribute LC_PROBE1000_TYPE of U0 : label is 1;
  attribute LC_PROBE1000_WIDTH : integer;
  attribute LC_PROBE1000_WIDTH of U0 : label is 1;
  attribute LC_PROBE1001_IS_DATA : string;
  attribute LC_PROBE1001_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1001_IS_TRIG : string;
  attribute LC_PROBE1001_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1001_MU_CNT : integer;
  attribute LC_PROBE1001_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1001_PID : string;
  attribute LC_PROBE1001_PID of U0 : label is "16'b0000001111101001";
  attribute LC_PROBE1001_TYPE : integer;
  attribute LC_PROBE1001_TYPE of U0 : label is 1;
  attribute LC_PROBE1001_WIDTH : integer;
  attribute LC_PROBE1001_WIDTH of U0 : label is 1;
  attribute LC_PROBE1002_IS_DATA : string;
  attribute LC_PROBE1002_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1002_IS_TRIG : string;
  attribute LC_PROBE1002_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1002_MU_CNT : integer;
  attribute LC_PROBE1002_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1002_PID : string;
  attribute LC_PROBE1002_PID of U0 : label is "16'b0000001111101010";
  attribute LC_PROBE1002_TYPE : integer;
  attribute LC_PROBE1002_TYPE of U0 : label is 1;
  attribute LC_PROBE1002_WIDTH : integer;
  attribute LC_PROBE1002_WIDTH of U0 : label is 1;
  attribute LC_PROBE1003_IS_DATA : string;
  attribute LC_PROBE1003_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1003_IS_TRIG : string;
  attribute LC_PROBE1003_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1003_MU_CNT : integer;
  attribute LC_PROBE1003_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1003_PID : string;
  attribute LC_PROBE1003_PID of U0 : label is "16'b0000001111101011";
  attribute LC_PROBE1003_TYPE : integer;
  attribute LC_PROBE1003_TYPE of U0 : label is 1;
  attribute LC_PROBE1003_WIDTH : integer;
  attribute LC_PROBE1003_WIDTH of U0 : label is 1;
  attribute LC_PROBE1004_IS_DATA : string;
  attribute LC_PROBE1004_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1004_IS_TRIG : string;
  attribute LC_PROBE1004_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1004_MU_CNT : integer;
  attribute LC_PROBE1004_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1004_PID : string;
  attribute LC_PROBE1004_PID of U0 : label is "16'b0000001111101100";
  attribute LC_PROBE1004_TYPE : integer;
  attribute LC_PROBE1004_TYPE of U0 : label is 1;
  attribute LC_PROBE1004_WIDTH : integer;
  attribute LC_PROBE1004_WIDTH of U0 : label is 1;
  attribute LC_PROBE1005_IS_DATA : string;
  attribute LC_PROBE1005_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1005_IS_TRIG : string;
  attribute LC_PROBE1005_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1005_MU_CNT : integer;
  attribute LC_PROBE1005_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1005_PID : string;
  attribute LC_PROBE1005_PID of U0 : label is "16'b0000001111101101";
  attribute LC_PROBE1005_TYPE : integer;
  attribute LC_PROBE1005_TYPE of U0 : label is 1;
  attribute LC_PROBE1005_WIDTH : integer;
  attribute LC_PROBE1005_WIDTH of U0 : label is 1;
  attribute LC_PROBE1006_IS_DATA : string;
  attribute LC_PROBE1006_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1006_IS_TRIG : string;
  attribute LC_PROBE1006_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1006_MU_CNT : integer;
  attribute LC_PROBE1006_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1006_PID : string;
  attribute LC_PROBE1006_PID of U0 : label is "16'b0000001111101110";
  attribute LC_PROBE1006_TYPE : integer;
  attribute LC_PROBE1006_TYPE of U0 : label is 1;
  attribute LC_PROBE1006_WIDTH : integer;
  attribute LC_PROBE1006_WIDTH of U0 : label is 1;
  attribute LC_PROBE1007_IS_DATA : string;
  attribute LC_PROBE1007_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1007_IS_TRIG : string;
  attribute LC_PROBE1007_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1007_MU_CNT : integer;
  attribute LC_PROBE1007_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1007_PID : string;
  attribute LC_PROBE1007_PID of U0 : label is "16'b0000001111101111";
  attribute LC_PROBE1007_TYPE : integer;
  attribute LC_PROBE1007_TYPE of U0 : label is 1;
  attribute LC_PROBE1007_WIDTH : integer;
  attribute LC_PROBE1007_WIDTH of U0 : label is 1;
  attribute LC_PROBE1008_IS_DATA : string;
  attribute LC_PROBE1008_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1008_IS_TRIG : string;
  attribute LC_PROBE1008_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1008_MU_CNT : integer;
  attribute LC_PROBE1008_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1008_PID : string;
  attribute LC_PROBE1008_PID of U0 : label is "16'b0000001111110000";
  attribute LC_PROBE1008_TYPE : integer;
  attribute LC_PROBE1008_TYPE of U0 : label is 1;
  attribute LC_PROBE1008_WIDTH : integer;
  attribute LC_PROBE1008_WIDTH of U0 : label is 1;
  attribute LC_PROBE1009_IS_DATA : string;
  attribute LC_PROBE1009_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1009_IS_TRIG : string;
  attribute LC_PROBE1009_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1009_MU_CNT : integer;
  attribute LC_PROBE1009_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1009_PID : string;
  attribute LC_PROBE1009_PID of U0 : label is "16'b0000001111110001";
  attribute LC_PROBE1009_TYPE : integer;
  attribute LC_PROBE1009_TYPE of U0 : label is 1;
  attribute LC_PROBE1009_WIDTH : integer;
  attribute LC_PROBE1009_WIDTH of U0 : label is 1;
  attribute LC_PROBE100_IS_DATA : string;
  attribute LC_PROBE100_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE100_IS_TRIG : string;
  attribute LC_PROBE100_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE100_MU_CNT : integer;
  attribute LC_PROBE100_MU_CNT of U0 : label is 1;
  attribute LC_PROBE100_PID : string;
  attribute LC_PROBE100_PID of U0 : label is "16'b0000000001100100";
  attribute LC_PROBE100_TYPE : integer;
  attribute LC_PROBE100_TYPE of U0 : label is 1;
  attribute LC_PROBE100_WIDTH : integer;
  attribute LC_PROBE100_WIDTH of U0 : label is 1;
  attribute LC_PROBE1010_IS_DATA : string;
  attribute LC_PROBE1010_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1010_IS_TRIG : string;
  attribute LC_PROBE1010_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1010_MU_CNT : integer;
  attribute LC_PROBE1010_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1010_PID : string;
  attribute LC_PROBE1010_PID of U0 : label is "16'b0000001111110010";
  attribute LC_PROBE1010_TYPE : integer;
  attribute LC_PROBE1010_TYPE of U0 : label is 1;
  attribute LC_PROBE1010_WIDTH : integer;
  attribute LC_PROBE1010_WIDTH of U0 : label is 1;
  attribute LC_PROBE1011_IS_DATA : string;
  attribute LC_PROBE1011_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1011_IS_TRIG : string;
  attribute LC_PROBE1011_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1011_MU_CNT : integer;
  attribute LC_PROBE1011_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1011_PID : string;
  attribute LC_PROBE1011_PID of U0 : label is "16'b0000001111110011";
  attribute LC_PROBE1011_TYPE : integer;
  attribute LC_PROBE1011_TYPE of U0 : label is 1;
  attribute LC_PROBE1011_WIDTH : integer;
  attribute LC_PROBE1011_WIDTH of U0 : label is 1;
  attribute LC_PROBE1012_IS_DATA : string;
  attribute LC_PROBE1012_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1012_IS_TRIG : string;
  attribute LC_PROBE1012_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1012_MU_CNT : integer;
  attribute LC_PROBE1012_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1012_PID : string;
  attribute LC_PROBE1012_PID of U0 : label is "16'b0000001111110100";
  attribute LC_PROBE1012_TYPE : integer;
  attribute LC_PROBE1012_TYPE of U0 : label is 1;
  attribute LC_PROBE1012_WIDTH : integer;
  attribute LC_PROBE1012_WIDTH of U0 : label is 1;
  attribute LC_PROBE1013_IS_DATA : string;
  attribute LC_PROBE1013_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1013_IS_TRIG : string;
  attribute LC_PROBE1013_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1013_MU_CNT : integer;
  attribute LC_PROBE1013_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1013_PID : string;
  attribute LC_PROBE1013_PID of U0 : label is "16'b0000001111110101";
  attribute LC_PROBE1013_TYPE : integer;
  attribute LC_PROBE1013_TYPE of U0 : label is 1;
  attribute LC_PROBE1013_WIDTH : integer;
  attribute LC_PROBE1013_WIDTH of U0 : label is 1;
  attribute LC_PROBE1014_IS_DATA : string;
  attribute LC_PROBE1014_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1014_IS_TRIG : string;
  attribute LC_PROBE1014_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1014_MU_CNT : integer;
  attribute LC_PROBE1014_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1014_PID : string;
  attribute LC_PROBE1014_PID of U0 : label is "16'b0000001111110110";
  attribute LC_PROBE1014_TYPE : integer;
  attribute LC_PROBE1014_TYPE of U0 : label is 1;
  attribute LC_PROBE1014_WIDTH : integer;
  attribute LC_PROBE1014_WIDTH of U0 : label is 1;
  attribute LC_PROBE1015_IS_DATA : string;
  attribute LC_PROBE1015_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1015_IS_TRIG : string;
  attribute LC_PROBE1015_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1015_MU_CNT : integer;
  attribute LC_PROBE1015_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1015_PID : string;
  attribute LC_PROBE1015_PID of U0 : label is "16'b0000001111110111";
  attribute LC_PROBE1015_TYPE : integer;
  attribute LC_PROBE1015_TYPE of U0 : label is 1;
  attribute LC_PROBE1015_WIDTH : integer;
  attribute LC_PROBE1015_WIDTH of U0 : label is 1;
  attribute LC_PROBE1016_IS_DATA : string;
  attribute LC_PROBE1016_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1016_IS_TRIG : string;
  attribute LC_PROBE1016_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1016_MU_CNT : integer;
  attribute LC_PROBE1016_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1016_PID : string;
  attribute LC_PROBE1016_PID of U0 : label is "16'b0000001111111000";
  attribute LC_PROBE1016_TYPE : integer;
  attribute LC_PROBE1016_TYPE of U0 : label is 1;
  attribute LC_PROBE1016_WIDTH : integer;
  attribute LC_PROBE1016_WIDTH of U0 : label is 1;
  attribute LC_PROBE1017_IS_DATA : string;
  attribute LC_PROBE1017_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1017_IS_TRIG : string;
  attribute LC_PROBE1017_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1017_MU_CNT : integer;
  attribute LC_PROBE1017_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1017_PID : string;
  attribute LC_PROBE1017_PID of U0 : label is "16'b0000001111111001";
  attribute LC_PROBE1017_TYPE : integer;
  attribute LC_PROBE1017_TYPE of U0 : label is 1;
  attribute LC_PROBE1017_WIDTH : integer;
  attribute LC_PROBE1017_WIDTH of U0 : label is 1;
  attribute LC_PROBE1018_IS_DATA : string;
  attribute LC_PROBE1018_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1018_IS_TRIG : string;
  attribute LC_PROBE1018_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1018_MU_CNT : integer;
  attribute LC_PROBE1018_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1018_PID : string;
  attribute LC_PROBE1018_PID of U0 : label is "16'b0000001111111010";
  attribute LC_PROBE1018_TYPE : integer;
  attribute LC_PROBE1018_TYPE of U0 : label is 1;
  attribute LC_PROBE1018_WIDTH : integer;
  attribute LC_PROBE1018_WIDTH of U0 : label is 1;
  attribute LC_PROBE1019_IS_DATA : string;
  attribute LC_PROBE1019_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1019_IS_TRIG : string;
  attribute LC_PROBE1019_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1019_MU_CNT : integer;
  attribute LC_PROBE1019_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1019_PID : string;
  attribute LC_PROBE1019_PID of U0 : label is "16'b0000001111111011";
  attribute LC_PROBE1019_TYPE : integer;
  attribute LC_PROBE1019_TYPE of U0 : label is 1;
  attribute LC_PROBE1019_WIDTH : integer;
  attribute LC_PROBE1019_WIDTH of U0 : label is 1;
  attribute LC_PROBE101_IS_DATA : string;
  attribute LC_PROBE101_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE101_IS_TRIG : string;
  attribute LC_PROBE101_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE101_MU_CNT : integer;
  attribute LC_PROBE101_MU_CNT of U0 : label is 1;
  attribute LC_PROBE101_PID : string;
  attribute LC_PROBE101_PID of U0 : label is "16'b0000000001100101";
  attribute LC_PROBE101_TYPE : integer;
  attribute LC_PROBE101_TYPE of U0 : label is 1;
  attribute LC_PROBE101_WIDTH : integer;
  attribute LC_PROBE101_WIDTH of U0 : label is 1;
  attribute LC_PROBE1020_IS_DATA : string;
  attribute LC_PROBE1020_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1020_IS_TRIG : string;
  attribute LC_PROBE1020_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1020_MU_CNT : integer;
  attribute LC_PROBE1020_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1020_PID : string;
  attribute LC_PROBE1020_PID of U0 : label is "16'b0000001111111100";
  attribute LC_PROBE1020_TYPE : integer;
  attribute LC_PROBE1020_TYPE of U0 : label is 1;
  attribute LC_PROBE1020_WIDTH : integer;
  attribute LC_PROBE1020_WIDTH of U0 : label is 1;
  attribute LC_PROBE1021_IS_DATA : string;
  attribute LC_PROBE1021_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1021_IS_TRIG : string;
  attribute LC_PROBE1021_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1021_MU_CNT : integer;
  attribute LC_PROBE1021_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1021_PID : string;
  attribute LC_PROBE1021_PID of U0 : label is "16'b0000001111111101";
  attribute LC_PROBE1021_TYPE : integer;
  attribute LC_PROBE1021_TYPE of U0 : label is 1;
  attribute LC_PROBE1021_WIDTH : integer;
  attribute LC_PROBE1021_WIDTH of U0 : label is 1;
  attribute LC_PROBE1022_IS_DATA : string;
  attribute LC_PROBE1022_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1022_IS_TRIG : string;
  attribute LC_PROBE1022_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1022_MU_CNT : integer;
  attribute LC_PROBE1022_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1022_PID : string;
  attribute LC_PROBE1022_PID of U0 : label is "16'b0000001111111110";
  attribute LC_PROBE1022_TYPE : integer;
  attribute LC_PROBE1022_TYPE of U0 : label is 1;
  attribute LC_PROBE1022_WIDTH : integer;
  attribute LC_PROBE1022_WIDTH of U0 : label is 1;
  attribute LC_PROBE1023_IS_DATA : string;
  attribute LC_PROBE1023_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE1023_IS_TRIG : string;
  attribute LC_PROBE1023_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE1023_MU_CNT : integer;
  attribute LC_PROBE1023_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1023_PID : string;
  attribute LC_PROBE1023_PID of U0 : label is "16'b0000001111111111";
  attribute LC_PROBE1023_TYPE : integer;
  attribute LC_PROBE1023_TYPE of U0 : label is 1;
  attribute LC_PROBE1023_WIDTH : integer;
  attribute LC_PROBE1023_WIDTH of U0 : label is 1;
  attribute LC_PROBE102_IS_DATA : string;
  attribute LC_PROBE102_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE102_IS_TRIG : string;
  attribute LC_PROBE102_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE102_MU_CNT : integer;
  attribute LC_PROBE102_MU_CNT of U0 : label is 1;
  attribute LC_PROBE102_PID : string;
  attribute LC_PROBE102_PID of U0 : label is "16'b0000000001100110";
  attribute LC_PROBE102_TYPE : integer;
  attribute LC_PROBE102_TYPE of U0 : label is 1;
  attribute LC_PROBE102_WIDTH : integer;
  attribute LC_PROBE102_WIDTH of U0 : label is 1;
  attribute LC_PROBE103_IS_DATA : string;
  attribute LC_PROBE103_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE103_IS_TRIG : string;
  attribute LC_PROBE103_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE103_MU_CNT : integer;
  attribute LC_PROBE103_MU_CNT of U0 : label is 1;
  attribute LC_PROBE103_PID : string;
  attribute LC_PROBE103_PID of U0 : label is "16'b0000000001100111";
  attribute LC_PROBE103_TYPE : integer;
  attribute LC_PROBE103_TYPE of U0 : label is 1;
  attribute LC_PROBE103_WIDTH : integer;
  attribute LC_PROBE103_WIDTH of U0 : label is 1;
  attribute LC_PROBE104_IS_DATA : string;
  attribute LC_PROBE104_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE104_IS_TRIG : string;
  attribute LC_PROBE104_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE104_MU_CNT : integer;
  attribute LC_PROBE104_MU_CNT of U0 : label is 1;
  attribute LC_PROBE104_PID : string;
  attribute LC_PROBE104_PID of U0 : label is "16'b0000000001101000";
  attribute LC_PROBE104_TYPE : integer;
  attribute LC_PROBE104_TYPE of U0 : label is 1;
  attribute LC_PROBE104_WIDTH : integer;
  attribute LC_PROBE104_WIDTH of U0 : label is 1;
  attribute LC_PROBE105_IS_DATA : string;
  attribute LC_PROBE105_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE105_IS_TRIG : string;
  attribute LC_PROBE105_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE105_MU_CNT : integer;
  attribute LC_PROBE105_MU_CNT of U0 : label is 1;
  attribute LC_PROBE105_PID : string;
  attribute LC_PROBE105_PID of U0 : label is "16'b0000000001101001";
  attribute LC_PROBE105_TYPE : integer;
  attribute LC_PROBE105_TYPE of U0 : label is 1;
  attribute LC_PROBE105_WIDTH : integer;
  attribute LC_PROBE105_WIDTH of U0 : label is 1;
  attribute LC_PROBE106_IS_DATA : string;
  attribute LC_PROBE106_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE106_IS_TRIG : string;
  attribute LC_PROBE106_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE106_MU_CNT : integer;
  attribute LC_PROBE106_MU_CNT of U0 : label is 1;
  attribute LC_PROBE106_PID : string;
  attribute LC_PROBE106_PID of U0 : label is "16'b0000000001101010";
  attribute LC_PROBE106_TYPE : integer;
  attribute LC_PROBE106_TYPE of U0 : label is 1;
  attribute LC_PROBE106_WIDTH : integer;
  attribute LC_PROBE106_WIDTH of U0 : label is 1;
  attribute LC_PROBE107_IS_DATA : string;
  attribute LC_PROBE107_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE107_IS_TRIG : string;
  attribute LC_PROBE107_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE107_MU_CNT : integer;
  attribute LC_PROBE107_MU_CNT of U0 : label is 1;
  attribute LC_PROBE107_PID : string;
  attribute LC_PROBE107_PID of U0 : label is "16'b0000000001101011";
  attribute LC_PROBE107_TYPE : integer;
  attribute LC_PROBE107_TYPE of U0 : label is 1;
  attribute LC_PROBE107_WIDTH : integer;
  attribute LC_PROBE107_WIDTH of U0 : label is 1;
  attribute LC_PROBE108_IS_DATA : string;
  attribute LC_PROBE108_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE108_IS_TRIG : string;
  attribute LC_PROBE108_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE108_MU_CNT : integer;
  attribute LC_PROBE108_MU_CNT of U0 : label is 1;
  attribute LC_PROBE108_PID : string;
  attribute LC_PROBE108_PID of U0 : label is "16'b0000000001101100";
  attribute LC_PROBE108_TYPE : integer;
  attribute LC_PROBE108_TYPE of U0 : label is 1;
  attribute LC_PROBE108_WIDTH : integer;
  attribute LC_PROBE108_WIDTH of U0 : label is 1;
  attribute LC_PROBE109_IS_DATA : string;
  attribute LC_PROBE109_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE109_IS_TRIG : string;
  attribute LC_PROBE109_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE109_MU_CNT : integer;
  attribute LC_PROBE109_MU_CNT of U0 : label is 1;
  attribute LC_PROBE109_PID : string;
  attribute LC_PROBE109_PID of U0 : label is "16'b0000000001101101";
  attribute LC_PROBE109_TYPE : integer;
  attribute LC_PROBE109_TYPE of U0 : label is 1;
  attribute LC_PROBE109_WIDTH : integer;
  attribute LC_PROBE109_WIDTH of U0 : label is 1;
  attribute LC_PROBE10_IS_DATA : string;
  attribute LC_PROBE10_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE10_IS_TRIG : string;
  attribute LC_PROBE10_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE10_MU_CNT : integer;
  attribute LC_PROBE10_MU_CNT of U0 : label is 1;
  attribute LC_PROBE10_PID : string;
  attribute LC_PROBE10_PID of U0 : label is "16'b0000000000001010";
  attribute LC_PROBE10_TYPE : integer;
  attribute LC_PROBE10_TYPE of U0 : label is 1;
  attribute LC_PROBE10_WIDTH : integer;
  attribute LC_PROBE10_WIDTH of U0 : label is 1;
  attribute LC_PROBE110_IS_DATA : string;
  attribute LC_PROBE110_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE110_IS_TRIG : string;
  attribute LC_PROBE110_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE110_MU_CNT : integer;
  attribute LC_PROBE110_MU_CNT of U0 : label is 1;
  attribute LC_PROBE110_PID : string;
  attribute LC_PROBE110_PID of U0 : label is "16'b0000000001101110";
  attribute LC_PROBE110_TYPE : integer;
  attribute LC_PROBE110_TYPE of U0 : label is 1;
  attribute LC_PROBE110_WIDTH : integer;
  attribute LC_PROBE110_WIDTH of U0 : label is 1;
  attribute LC_PROBE111_IS_DATA : string;
  attribute LC_PROBE111_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE111_IS_TRIG : string;
  attribute LC_PROBE111_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE111_MU_CNT : integer;
  attribute LC_PROBE111_MU_CNT of U0 : label is 1;
  attribute LC_PROBE111_PID : string;
  attribute LC_PROBE111_PID of U0 : label is "16'b0000000001101111";
  attribute LC_PROBE111_TYPE : integer;
  attribute LC_PROBE111_TYPE of U0 : label is 1;
  attribute LC_PROBE111_WIDTH : integer;
  attribute LC_PROBE111_WIDTH of U0 : label is 1;
  attribute LC_PROBE112_IS_DATA : string;
  attribute LC_PROBE112_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE112_IS_TRIG : string;
  attribute LC_PROBE112_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE112_MU_CNT : integer;
  attribute LC_PROBE112_MU_CNT of U0 : label is 1;
  attribute LC_PROBE112_PID : string;
  attribute LC_PROBE112_PID of U0 : label is "16'b0000000001110000";
  attribute LC_PROBE112_TYPE : integer;
  attribute LC_PROBE112_TYPE of U0 : label is 1;
  attribute LC_PROBE112_WIDTH : integer;
  attribute LC_PROBE112_WIDTH of U0 : label is 1;
  attribute LC_PROBE113_IS_DATA : string;
  attribute LC_PROBE113_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE113_IS_TRIG : string;
  attribute LC_PROBE113_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE113_MU_CNT : integer;
  attribute LC_PROBE113_MU_CNT of U0 : label is 1;
  attribute LC_PROBE113_PID : string;
  attribute LC_PROBE113_PID of U0 : label is "16'b0000000001110001";
  attribute LC_PROBE113_TYPE : integer;
  attribute LC_PROBE113_TYPE of U0 : label is 1;
  attribute LC_PROBE113_WIDTH : integer;
  attribute LC_PROBE113_WIDTH of U0 : label is 1;
  attribute LC_PROBE114_IS_DATA : string;
  attribute LC_PROBE114_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE114_IS_TRIG : string;
  attribute LC_PROBE114_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE114_MU_CNT : integer;
  attribute LC_PROBE114_MU_CNT of U0 : label is 1;
  attribute LC_PROBE114_PID : string;
  attribute LC_PROBE114_PID of U0 : label is "16'b0000000001110010";
  attribute LC_PROBE114_TYPE : integer;
  attribute LC_PROBE114_TYPE of U0 : label is 1;
  attribute LC_PROBE114_WIDTH : integer;
  attribute LC_PROBE114_WIDTH of U0 : label is 1;
  attribute LC_PROBE115_IS_DATA : string;
  attribute LC_PROBE115_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE115_IS_TRIG : string;
  attribute LC_PROBE115_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE115_MU_CNT : integer;
  attribute LC_PROBE115_MU_CNT of U0 : label is 1;
  attribute LC_PROBE115_PID : string;
  attribute LC_PROBE115_PID of U0 : label is "16'b0000000001110011";
  attribute LC_PROBE115_TYPE : integer;
  attribute LC_PROBE115_TYPE of U0 : label is 1;
  attribute LC_PROBE115_WIDTH : integer;
  attribute LC_PROBE115_WIDTH of U0 : label is 1;
  attribute LC_PROBE116_IS_DATA : string;
  attribute LC_PROBE116_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE116_IS_TRIG : string;
  attribute LC_PROBE116_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE116_MU_CNT : integer;
  attribute LC_PROBE116_MU_CNT of U0 : label is 1;
  attribute LC_PROBE116_PID : string;
  attribute LC_PROBE116_PID of U0 : label is "16'b0000000001110100";
  attribute LC_PROBE116_TYPE : integer;
  attribute LC_PROBE116_TYPE of U0 : label is 1;
  attribute LC_PROBE116_WIDTH : integer;
  attribute LC_PROBE116_WIDTH of U0 : label is 1;
  attribute LC_PROBE117_IS_DATA : string;
  attribute LC_PROBE117_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE117_IS_TRIG : string;
  attribute LC_PROBE117_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE117_MU_CNT : integer;
  attribute LC_PROBE117_MU_CNT of U0 : label is 1;
  attribute LC_PROBE117_PID : string;
  attribute LC_PROBE117_PID of U0 : label is "16'b0000000001110101";
  attribute LC_PROBE117_TYPE : integer;
  attribute LC_PROBE117_TYPE of U0 : label is 1;
  attribute LC_PROBE117_WIDTH : integer;
  attribute LC_PROBE117_WIDTH of U0 : label is 1;
  attribute LC_PROBE118_IS_DATA : string;
  attribute LC_PROBE118_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE118_IS_TRIG : string;
  attribute LC_PROBE118_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE118_MU_CNT : integer;
  attribute LC_PROBE118_MU_CNT of U0 : label is 1;
  attribute LC_PROBE118_PID : string;
  attribute LC_PROBE118_PID of U0 : label is "16'b0000000001110110";
  attribute LC_PROBE118_TYPE : integer;
  attribute LC_PROBE118_TYPE of U0 : label is 1;
  attribute LC_PROBE118_WIDTH : integer;
  attribute LC_PROBE118_WIDTH of U0 : label is 1;
  attribute LC_PROBE119_IS_DATA : string;
  attribute LC_PROBE119_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE119_IS_TRIG : string;
  attribute LC_PROBE119_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE119_MU_CNT : integer;
  attribute LC_PROBE119_MU_CNT of U0 : label is 1;
  attribute LC_PROBE119_PID : string;
  attribute LC_PROBE119_PID of U0 : label is "16'b0000000001110111";
  attribute LC_PROBE119_TYPE : integer;
  attribute LC_PROBE119_TYPE of U0 : label is 1;
  attribute LC_PROBE119_WIDTH : integer;
  attribute LC_PROBE119_WIDTH of U0 : label is 1;
  attribute LC_PROBE11_IS_DATA : string;
  attribute LC_PROBE11_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE11_IS_TRIG : string;
  attribute LC_PROBE11_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE11_MU_CNT : integer;
  attribute LC_PROBE11_MU_CNT of U0 : label is 1;
  attribute LC_PROBE11_PID : string;
  attribute LC_PROBE11_PID of U0 : label is "16'b0000000000001011";
  attribute LC_PROBE11_TYPE : integer;
  attribute LC_PROBE11_TYPE of U0 : label is 1;
  attribute LC_PROBE11_WIDTH : integer;
  attribute LC_PROBE11_WIDTH of U0 : label is 1;
  attribute LC_PROBE120_IS_DATA : string;
  attribute LC_PROBE120_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE120_IS_TRIG : string;
  attribute LC_PROBE120_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE120_MU_CNT : integer;
  attribute LC_PROBE120_MU_CNT of U0 : label is 1;
  attribute LC_PROBE120_PID : string;
  attribute LC_PROBE120_PID of U0 : label is "16'b0000000001111000";
  attribute LC_PROBE120_TYPE : integer;
  attribute LC_PROBE120_TYPE of U0 : label is 1;
  attribute LC_PROBE120_WIDTH : integer;
  attribute LC_PROBE120_WIDTH of U0 : label is 1;
  attribute LC_PROBE121_IS_DATA : string;
  attribute LC_PROBE121_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE121_IS_TRIG : string;
  attribute LC_PROBE121_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE121_MU_CNT : integer;
  attribute LC_PROBE121_MU_CNT of U0 : label is 1;
  attribute LC_PROBE121_PID : string;
  attribute LC_PROBE121_PID of U0 : label is "16'b0000000001111001";
  attribute LC_PROBE121_TYPE : integer;
  attribute LC_PROBE121_TYPE of U0 : label is 1;
  attribute LC_PROBE121_WIDTH : integer;
  attribute LC_PROBE121_WIDTH of U0 : label is 1;
  attribute LC_PROBE122_IS_DATA : string;
  attribute LC_PROBE122_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE122_IS_TRIG : string;
  attribute LC_PROBE122_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE122_MU_CNT : integer;
  attribute LC_PROBE122_MU_CNT of U0 : label is 1;
  attribute LC_PROBE122_PID : string;
  attribute LC_PROBE122_PID of U0 : label is "16'b0000000001111010";
  attribute LC_PROBE122_TYPE : integer;
  attribute LC_PROBE122_TYPE of U0 : label is 1;
  attribute LC_PROBE122_WIDTH : integer;
  attribute LC_PROBE122_WIDTH of U0 : label is 1;
  attribute LC_PROBE123_IS_DATA : string;
  attribute LC_PROBE123_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE123_IS_TRIG : string;
  attribute LC_PROBE123_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE123_MU_CNT : integer;
  attribute LC_PROBE123_MU_CNT of U0 : label is 1;
  attribute LC_PROBE123_PID : string;
  attribute LC_PROBE123_PID of U0 : label is "16'b0000000001111011";
  attribute LC_PROBE123_TYPE : integer;
  attribute LC_PROBE123_TYPE of U0 : label is 1;
  attribute LC_PROBE123_WIDTH : integer;
  attribute LC_PROBE123_WIDTH of U0 : label is 1;
  attribute LC_PROBE124_IS_DATA : string;
  attribute LC_PROBE124_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE124_IS_TRIG : string;
  attribute LC_PROBE124_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE124_MU_CNT : integer;
  attribute LC_PROBE124_MU_CNT of U0 : label is 1;
  attribute LC_PROBE124_PID : string;
  attribute LC_PROBE124_PID of U0 : label is "16'b0000000001111100";
  attribute LC_PROBE124_TYPE : integer;
  attribute LC_PROBE124_TYPE of U0 : label is 1;
  attribute LC_PROBE124_WIDTH : integer;
  attribute LC_PROBE124_WIDTH of U0 : label is 1;
  attribute LC_PROBE125_IS_DATA : string;
  attribute LC_PROBE125_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE125_IS_TRIG : string;
  attribute LC_PROBE125_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE125_MU_CNT : integer;
  attribute LC_PROBE125_MU_CNT of U0 : label is 1;
  attribute LC_PROBE125_PID : string;
  attribute LC_PROBE125_PID of U0 : label is "16'b0000000001111101";
  attribute LC_PROBE125_TYPE : integer;
  attribute LC_PROBE125_TYPE of U0 : label is 1;
  attribute LC_PROBE125_WIDTH : integer;
  attribute LC_PROBE125_WIDTH of U0 : label is 1;
  attribute LC_PROBE126_IS_DATA : string;
  attribute LC_PROBE126_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE126_IS_TRIG : string;
  attribute LC_PROBE126_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE126_MU_CNT : integer;
  attribute LC_PROBE126_MU_CNT of U0 : label is 1;
  attribute LC_PROBE126_PID : string;
  attribute LC_PROBE126_PID of U0 : label is "16'b0000000001111110";
  attribute LC_PROBE126_TYPE : integer;
  attribute LC_PROBE126_TYPE of U0 : label is 1;
  attribute LC_PROBE126_WIDTH : integer;
  attribute LC_PROBE126_WIDTH of U0 : label is 1;
  attribute LC_PROBE127_IS_DATA : string;
  attribute LC_PROBE127_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE127_IS_TRIG : string;
  attribute LC_PROBE127_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE127_MU_CNT : integer;
  attribute LC_PROBE127_MU_CNT of U0 : label is 1;
  attribute LC_PROBE127_PID : string;
  attribute LC_PROBE127_PID of U0 : label is "16'b0000000001111111";
  attribute LC_PROBE127_TYPE : integer;
  attribute LC_PROBE127_TYPE of U0 : label is 1;
  attribute LC_PROBE127_WIDTH : integer;
  attribute LC_PROBE127_WIDTH of U0 : label is 1;
  attribute LC_PROBE128_IS_DATA : string;
  attribute LC_PROBE128_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE128_IS_TRIG : string;
  attribute LC_PROBE128_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE128_MU_CNT : integer;
  attribute LC_PROBE128_MU_CNT of U0 : label is 1;
  attribute LC_PROBE128_PID : string;
  attribute LC_PROBE128_PID of U0 : label is "16'b0000000010000000";
  attribute LC_PROBE128_TYPE : integer;
  attribute LC_PROBE128_TYPE of U0 : label is 1;
  attribute LC_PROBE128_WIDTH : integer;
  attribute LC_PROBE128_WIDTH of U0 : label is 1;
  attribute LC_PROBE129_IS_DATA : string;
  attribute LC_PROBE129_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE129_IS_TRIG : string;
  attribute LC_PROBE129_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE129_MU_CNT : integer;
  attribute LC_PROBE129_MU_CNT of U0 : label is 1;
  attribute LC_PROBE129_PID : string;
  attribute LC_PROBE129_PID of U0 : label is "16'b0000000010000001";
  attribute LC_PROBE129_TYPE : integer;
  attribute LC_PROBE129_TYPE of U0 : label is 1;
  attribute LC_PROBE129_WIDTH : integer;
  attribute LC_PROBE129_WIDTH of U0 : label is 1;
  attribute LC_PROBE12_IS_DATA : string;
  attribute LC_PROBE12_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE12_IS_TRIG : string;
  attribute LC_PROBE12_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE12_MU_CNT : integer;
  attribute LC_PROBE12_MU_CNT of U0 : label is 1;
  attribute LC_PROBE12_PID : string;
  attribute LC_PROBE12_PID of U0 : label is "16'b0000000000001100";
  attribute LC_PROBE12_TYPE : integer;
  attribute LC_PROBE12_TYPE of U0 : label is 1;
  attribute LC_PROBE12_WIDTH : integer;
  attribute LC_PROBE12_WIDTH of U0 : label is 1;
  attribute LC_PROBE130_IS_DATA : string;
  attribute LC_PROBE130_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE130_IS_TRIG : string;
  attribute LC_PROBE130_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE130_MU_CNT : integer;
  attribute LC_PROBE130_MU_CNT of U0 : label is 1;
  attribute LC_PROBE130_PID : string;
  attribute LC_PROBE130_PID of U0 : label is "16'b0000000010000010";
  attribute LC_PROBE130_TYPE : integer;
  attribute LC_PROBE130_TYPE of U0 : label is 1;
  attribute LC_PROBE130_WIDTH : integer;
  attribute LC_PROBE130_WIDTH of U0 : label is 1;
  attribute LC_PROBE131_IS_DATA : string;
  attribute LC_PROBE131_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE131_IS_TRIG : string;
  attribute LC_PROBE131_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE131_MU_CNT : integer;
  attribute LC_PROBE131_MU_CNT of U0 : label is 1;
  attribute LC_PROBE131_PID : string;
  attribute LC_PROBE131_PID of U0 : label is "16'b0000000010000011";
  attribute LC_PROBE131_TYPE : integer;
  attribute LC_PROBE131_TYPE of U0 : label is 1;
  attribute LC_PROBE131_WIDTH : integer;
  attribute LC_PROBE131_WIDTH of U0 : label is 1;
  attribute LC_PROBE132_IS_DATA : string;
  attribute LC_PROBE132_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE132_IS_TRIG : string;
  attribute LC_PROBE132_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE132_MU_CNT : integer;
  attribute LC_PROBE132_MU_CNT of U0 : label is 1;
  attribute LC_PROBE132_PID : string;
  attribute LC_PROBE132_PID of U0 : label is "16'b0000000010000100";
  attribute LC_PROBE132_TYPE : integer;
  attribute LC_PROBE132_TYPE of U0 : label is 1;
  attribute LC_PROBE132_WIDTH : integer;
  attribute LC_PROBE132_WIDTH of U0 : label is 1;
  attribute LC_PROBE133_IS_DATA : string;
  attribute LC_PROBE133_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE133_IS_TRIG : string;
  attribute LC_PROBE133_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE133_MU_CNT : integer;
  attribute LC_PROBE133_MU_CNT of U0 : label is 1;
  attribute LC_PROBE133_PID : string;
  attribute LC_PROBE133_PID of U0 : label is "16'b0000000010000101";
  attribute LC_PROBE133_TYPE : integer;
  attribute LC_PROBE133_TYPE of U0 : label is 1;
  attribute LC_PROBE133_WIDTH : integer;
  attribute LC_PROBE133_WIDTH of U0 : label is 1;
  attribute LC_PROBE134_IS_DATA : string;
  attribute LC_PROBE134_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE134_IS_TRIG : string;
  attribute LC_PROBE134_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE134_MU_CNT : integer;
  attribute LC_PROBE134_MU_CNT of U0 : label is 1;
  attribute LC_PROBE134_PID : string;
  attribute LC_PROBE134_PID of U0 : label is "16'b0000000010000110";
  attribute LC_PROBE134_TYPE : integer;
  attribute LC_PROBE134_TYPE of U0 : label is 1;
  attribute LC_PROBE134_WIDTH : integer;
  attribute LC_PROBE134_WIDTH of U0 : label is 1;
  attribute LC_PROBE135_IS_DATA : string;
  attribute LC_PROBE135_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE135_IS_TRIG : string;
  attribute LC_PROBE135_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE135_MU_CNT : integer;
  attribute LC_PROBE135_MU_CNT of U0 : label is 1;
  attribute LC_PROBE135_PID : string;
  attribute LC_PROBE135_PID of U0 : label is "16'b0000000010000111";
  attribute LC_PROBE135_TYPE : integer;
  attribute LC_PROBE135_TYPE of U0 : label is 1;
  attribute LC_PROBE135_WIDTH : integer;
  attribute LC_PROBE135_WIDTH of U0 : label is 1;
  attribute LC_PROBE136_IS_DATA : string;
  attribute LC_PROBE136_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE136_IS_TRIG : string;
  attribute LC_PROBE136_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE136_MU_CNT : integer;
  attribute LC_PROBE136_MU_CNT of U0 : label is 1;
  attribute LC_PROBE136_PID : string;
  attribute LC_PROBE136_PID of U0 : label is "16'b0000000010001000";
  attribute LC_PROBE136_TYPE : integer;
  attribute LC_PROBE136_TYPE of U0 : label is 1;
  attribute LC_PROBE136_WIDTH : integer;
  attribute LC_PROBE136_WIDTH of U0 : label is 1;
  attribute LC_PROBE137_IS_DATA : string;
  attribute LC_PROBE137_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE137_IS_TRIG : string;
  attribute LC_PROBE137_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE137_MU_CNT : integer;
  attribute LC_PROBE137_MU_CNT of U0 : label is 1;
  attribute LC_PROBE137_PID : string;
  attribute LC_PROBE137_PID of U0 : label is "16'b0000000010001001";
  attribute LC_PROBE137_TYPE : integer;
  attribute LC_PROBE137_TYPE of U0 : label is 1;
  attribute LC_PROBE137_WIDTH : integer;
  attribute LC_PROBE137_WIDTH of U0 : label is 1;
  attribute LC_PROBE138_IS_DATA : string;
  attribute LC_PROBE138_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE138_IS_TRIG : string;
  attribute LC_PROBE138_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE138_MU_CNT : integer;
  attribute LC_PROBE138_MU_CNT of U0 : label is 1;
  attribute LC_PROBE138_PID : string;
  attribute LC_PROBE138_PID of U0 : label is "16'b0000000010001010";
  attribute LC_PROBE138_TYPE : integer;
  attribute LC_PROBE138_TYPE of U0 : label is 1;
  attribute LC_PROBE138_WIDTH : integer;
  attribute LC_PROBE138_WIDTH of U0 : label is 1;
  attribute LC_PROBE139_IS_DATA : string;
  attribute LC_PROBE139_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE139_IS_TRIG : string;
  attribute LC_PROBE139_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE139_MU_CNT : integer;
  attribute LC_PROBE139_MU_CNT of U0 : label is 1;
  attribute LC_PROBE139_PID : string;
  attribute LC_PROBE139_PID of U0 : label is "16'b0000000010001011";
  attribute LC_PROBE139_TYPE : integer;
  attribute LC_PROBE139_TYPE of U0 : label is 1;
  attribute LC_PROBE139_WIDTH : integer;
  attribute LC_PROBE139_WIDTH of U0 : label is 1;
  attribute LC_PROBE13_IS_DATA : string;
  attribute LC_PROBE13_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE13_IS_TRIG : string;
  attribute LC_PROBE13_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE13_MU_CNT : integer;
  attribute LC_PROBE13_MU_CNT of U0 : label is 1;
  attribute LC_PROBE13_PID : string;
  attribute LC_PROBE13_PID of U0 : label is "16'b0000000000001101";
  attribute LC_PROBE13_TYPE : integer;
  attribute LC_PROBE13_TYPE of U0 : label is 1;
  attribute LC_PROBE13_WIDTH : integer;
  attribute LC_PROBE13_WIDTH of U0 : label is 1;
  attribute LC_PROBE140_IS_DATA : string;
  attribute LC_PROBE140_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE140_IS_TRIG : string;
  attribute LC_PROBE140_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE140_MU_CNT : integer;
  attribute LC_PROBE140_MU_CNT of U0 : label is 1;
  attribute LC_PROBE140_PID : string;
  attribute LC_PROBE140_PID of U0 : label is "16'b0000000010001100";
  attribute LC_PROBE140_TYPE : integer;
  attribute LC_PROBE140_TYPE of U0 : label is 1;
  attribute LC_PROBE140_WIDTH : integer;
  attribute LC_PROBE140_WIDTH of U0 : label is 1;
  attribute LC_PROBE141_IS_DATA : string;
  attribute LC_PROBE141_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE141_IS_TRIG : string;
  attribute LC_PROBE141_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE141_MU_CNT : integer;
  attribute LC_PROBE141_MU_CNT of U0 : label is 1;
  attribute LC_PROBE141_PID : string;
  attribute LC_PROBE141_PID of U0 : label is "16'b0000000010001101";
  attribute LC_PROBE141_TYPE : integer;
  attribute LC_PROBE141_TYPE of U0 : label is 1;
  attribute LC_PROBE141_WIDTH : integer;
  attribute LC_PROBE141_WIDTH of U0 : label is 1;
  attribute LC_PROBE142_IS_DATA : string;
  attribute LC_PROBE142_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE142_IS_TRIG : string;
  attribute LC_PROBE142_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE142_MU_CNT : integer;
  attribute LC_PROBE142_MU_CNT of U0 : label is 1;
  attribute LC_PROBE142_PID : string;
  attribute LC_PROBE142_PID of U0 : label is "16'b0000000010001110";
  attribute LC_PROBE142_TYPE : integer;
  attribute LC_PROBE142_TYPE of U0 : label is 1;
  attribute LC_PROBE142_WIDTH : integer;
  attribute LC_PROBE142_WIDTH of U0 : label is 1;
  attribute LC_PROBE143_IS_DATA : string;
  attribute LC_PROBE143_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE143_IS_TRIG : string;
  attribute LC_PROBE143_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE143_MU_CNT : integer;
  attribute LC_PROBE143_MU_CNT of U0 : label is 1;
  attribute LC_PROBE143_PID : string;
  attribute LC_PROBE143_PID of U0 : label is "16'b0000000010001111";
  attribute LC_PROBE143_TYPE : integer;
  attribute LC_PROBE143_TYPE of U0 : label is 1;
  attribute LC_PROBE143_WIDTH : integer;
  attribute LC_PROBE143_WIDTH of U0 : label is 1;
  attribute LC_PROBE144_IS_DATA : string;
  attribute LC_PROBE144_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE144_IS_TRIG : string;
  attribute LC_PROBE144_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE144_MU_CNT : integer;
  attribute LC_PROBE144_MU_CNT of U0 : label is 1;
  attribute LC_PROBE144_PID : string;
  attribute LC_PROBE144_PID of U0 : label is "16'b0000000010010000";
  attribute LC_PROBE144_TYPE : integer;
  attribute LC_PROBE144_TYPE of U0 : label is 1;
  attribute LC_PROBE144_WIDTH : integer;
  attribute LC_PROBE144_WIDTH of U0 : label is 1;
  attribute LC_PROBE145_IS_DATA : string;
  attribute LC_PROBE145_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE145_IS_TRIG : string;
  attribute LC_PROBE145_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE145_MU_CNT : integer;
  attribute LC_PROBE145_MU_CNT of U0 : label is 1;
  attribute LC_PROBE145_PID : string;
  attribute LC_PROBE145_PID of U0 : label is "16'b0000000010010001";
  attribute LC_PROBE145_TYPE : integer;
  attribute LC_PROBE145_TYPE of U0 : label is 1;
  attribute LC_PROBE145_WIDTH : integer;
  attribute LC_PROBE145_WIDTH of U0 : label is 1;
  attribute LC_PROBE146_IS_DATA : string;
  attribute LC_PROBE146_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE146_IS_TRIG : string;
  attribute LC_PROBE146_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE146_MU_CNT : integer;
  attribute LC_PROBE146_MU_CNT of U0 : label is 1;
  attribute LC_PROBE146_PID : string;
  attribute LC_PROBE146_PID of U0 : label is "16'b0000000010010010";
  attribute LC_PROBE146_TYPE : integer;
  attribute LC_PROBE146_TYPE of U0 : label is 1;
  attribute LC_PROBE146_WIDTH : integer;
  attribute LC_PROBE146_WIDTH of U0 : label is 1;
  attribute LC_PROBE147_IS_DATA : string;
  attribute LC_PROBE147_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE147_IS_TRIG : string;
  attribute LC_PROBE147_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE147_MU_CNT : integer;
  attribute LC_PROBE147_MU_CNT of U0 : label is 1;
  attribute LC_PROBE147_PID : string;
  attribute LC_PROBE147_PID of U0 : label is "16'b0000000010010011";
  attribute LC_PROBE147_TYPE : integer;
  attribute LC_PROBE147_TYPE of U0 : label is 1;
  attribute LC_PROBE147_WIDTH : integer;
  attribute LC_PROBE147_WIDTH of U0 : label is 1;
  attribute LC_PROBE148_IS_DATA : string;
  attribute LC_PROBE148_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE148_IS_TRIG : string;
  attribute LC_PROBE148_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE148_MU_CNT : integer;
  attribute LC_PROBE148_MU_CNT of U0 : label is 1;
  attribute LC_PROBE148_PID : string;
  attribute LC_PROBE148_PID of U0 : label is "16'b0000000010010100";
  attribute LC_PROBE148_TYPE : integer;
  attribute LC_PROBE148_TYPE of U0 : label is 1;
  attribute LC_PROBE148_WIDTH : integer;
  attribute LC_PROBE148_WIDTH of U0 : label is 1;
  attribute LC_PROBE149_IS_DATA : string;
  attribute LC_PROBE149_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE149_IS_TRIG : string;
  attribute LC_PROBE149_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE149_MU_CNT : integer;
  attribute LC_PROBE149_MU_CNT of U0 : label is 1;
  attribute LC_PROBE149_PID : string;
  attribute LC_PROBE149_PID of U0 : label is "16'b0000000010010101";
  attribute LC_PROBE149_TYPE : integer;
  attribute LC_PROBE149_TYPE of U0 : label is 1;
  attribute LC_PROBE149_WIDTH : integer;
  attribute LC_PROBE149_WIDTH of U0 : label is 1;
  attribute LC_PROBE14_IS_DATA : string;
  attribute LC_PROBE14_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE14_IS_TRIG : string;
  attribute LC_PROBE14_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE14_MU_CNT : integer;
  attribute LC_PROBE14_MU_CNT of U0 : label is 1;
  attribute LC_PROBE14_PID : string;
  attribute LC_PROBE14_PID of U0 : label is "16'b0000000000001110";
  attribute LC_PROBE14_TYPE : integer;
  attribute LC_PROBE14_TYPE of U0 : label is 1;
  attribute LC_PROBE14_WIDTH : integer;
  attribute LC_PROBE14_WIDTH of U0 : label is 1;
  attribute LC_PROBE150_IS_DATA : string;
  attribute LC_PROBE150_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE150_IS_TRIG : string;
  attribute LC_PROBE150_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE150_MU_CNT : integer;
  attribute LC_PROBE150_MU_CNT of U0 : label is 1;
  attribute LC_PROBE150_PID : string;
  attribute LC_PROBE150_PID of U0 : label is "16'b0000000010010110";
  attribute LC_PROBE150_TYPE : integer;
  attribute LC_PROBE150_TYPE of U0 : label is 1;
  attribute LC_PROBE150_WIDTH : integer;
  attribute LC_PROBE150_WIDTH of U0 : label is 1;
  attribute LC_PROBE151_IS_DATA : string;
  attribute LC_PROBE151_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE151_IS_TRIG : string;
  attribute LC_PROBE151_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE151_MU_CNT : integer;
  attribute LC_PROBE151_MU_CNT of U0 : label is 1;
  attribute LC_PROBE151_PID : string;
  attribute LC_PROBE151_PID of U0 : label is "16'b0000000010010111";
  attribute LC_PROBE151_TYPE : integer;
  attribute LC_PROBE151_TYPE of U0 : label is 1;
  attribute LC_PROBE151_WIDTH : integer;
  attribute LC_PROBE151_WIDTH of U0 : label is 1;
  attribute LC_PROBE152_IS_DATA : string;
  attribute LC_PROBE152_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE152_IS_TRIG : string;
  attribute LC_PROBE152_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE152_MU_CNT : integer;
  attribute LC_PROBE152_MU_CNT of U0 : label is 1;
  attribute LC_PROBE152_PID : string;
  attribute LC_PROBE152_PID of U0 : label is "16'b0000000010011000";
  attribute LC_PROBE152_TYPE : integer;
  attribute LC_PROBE152_TYPE of U0 : label is 1;
  attribute LC_PROBE152_WIDTH : integer;
  attribute LC_PROBE152_WIDTH of U0 : label is 1;
  attribute LC_PROBE153_IS_DATA : string;
  attribute LC_PROBE153_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE153_IS_TRIG : string;
  attribute LC_PROBE153_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE153_MU_CNT : integer;
  attribute LC_PROBE153_MU_CNT of U0 : label is 1;
  attribute LC_PROBE153_PID : string;
  attribute LC_PROBE153_PID of U0 : label is "16'b0000000010011001";
  attribute LC_PROBE153_TYPE : integer;
  attribute LC_PROBE153_TYPE of U0 : label is 1;
  attribute LC_PROBE153_WIDTH : integer;
  attribute LC_PROBE153_WIDTH of U0 : label is 1;
  attribute LC_PROBE154_IS_DATA : string;
  attribute LC_PROBE154_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE154_IS_TRIG : string;
  attribute LC_PROBE154_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE154_MU_CNT : integer;
  attribute LC_PROBE154_MU_CNT of U0 : label is 1;
  attribute LC_PROBE154_PID : string;
  attribute LC_PROBE154_PID of U0 : label is "16'b0000000010011010";
  attribute LC_PROBE154_TYPE : integer;
  attribute LC_PROBE154_TYPE of U0 : label is 1;
  attribute LC_PROBE154_WIDTH : integer;
  attribute LC_PROBE154_WIDTH of U0 : label is 1;
  attribute LC_PROBE155_IS_DATA : string;
  attribute LC_PROBE155_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE155_IS_TRIG : string;
  attribute LC_PROBE155_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE155_MU_CNT : integer;
  attribute LC_PROBE155_MU_CNT of U0 : label is 1;
  attribute LC_PROBE155_PID : string;
  attribute LC_PROBE155_PID of U0 : label is "16'b0000000010011011";
  attribute LC_PROBE155_TYPE : integer;
  attribute LC_PROBE155_TYPE of U0 : label is 1;
  attribute LC_PROBE155_WIDTH : integer;
  attribute LC_PROBE155_WIDTH of U0 : label is 1;
  attribute LC_PROBE156_IS_DATA : string;
  attribute LC_PROBE156_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE156_IS_TRIG : string;
  attribute LC_PROBE156_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE156_MU_CNT : integer;
  attribute LC_PROBE156_MU_CNT of U0 : label is 1;
  attribute LC_PROBE156_PID : string;
  attribute LC_PROBE156_PID of U0 : label is "16'b0000000010011100";
  attribute LC_PROBE156_TYPE : integer;
  attribute LC_PROBE156_TYPE of U0 : label is 1;
  attribute LC_PROBE156_WIDTH : integer;
  attribute LC_PROBE156_WIDTH of U0 : label is 1;
  attribute LC_PROBE157_IS_DATA : string;
  attribute LC_PROBE157_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE157_IS_TRIG : string;
  attribute LC_PROBE157_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE157_MU_CNT : integer;
  attribute LC_PROBE157_MU_CNT of U0 : label is 1;
  attribute LC_PROBE157_PID : string;
  attribute LC_PROBE157_PID of U0 : label is "16'b0000000010011101";
  attribute LC_PROBE157_TYPE : integer;
  attribute LC_PROBE157_TYPE of U0 : label is 1;
  attribute LC_PROBE157_WIDTH : integer;
  attribute LC_PROBE157_WIDTH of U0 : label is 1;
  attribute LC_PROBE158_IS_DATA : string;
  attribute LC_PROBE158_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE158_IS_TRIG : string;
  attribute LC_PROBE158_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE158_MU_CNT : integer;
  attribute LC_PROBE158_MU_CNT of U0 : label is 1;
  attribute LC_PROBE158_PID : string;
  attribute LC_PROBE158_PID of U0 : label is "16'b0000000010011110";
  attribute LC_PROBE158_TYPE : integer;
  attribute LC_PROBE158_TYPE of U0 : label is 1;
  attribute LC_PROBE158_WIDTH : integer;
  attribute LC_PROBE158_WIDTH of U0 : label is 1;
  attribute LC_PROBE159_IS_DATA : string;
  attribute LC_PROBE159_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE159_IS_TRIG : string;
  attribute LC_PROBE159_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE159_MU_CNT : integer;
  attribute LC_PROBE159_MU_CNT of U0 : label is 1;
  attribute LC_PROBE159_PID : string;
  attribute LC_PROBE159_PID of U0 : label is "16'b0000000010011111";
  attribute LC_PROBE159_TYPE : integer;
  attribute LC_PROBE159_TYPE of U0 : label is 1;
  attribute LC_PROBE159_WIDTH : integer;
  attribute LC_PROBE159_WIDTH of U0 : label is 1;
  attribute LC_PROBE15_IS_DATA : string;
  attribute LC_PROBE15_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE15_IS_TRIG : string;
  attribute LC_PROBE15_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE15_MU_CNT : integer;
  attribute LC_PROBE15_MU_CNT of U0 : label is 1;
  attribute LC_PROBE15_PID : string;
  attribute LC_PROBE15_PID of U0 : label is "16'b0000000000001111";
  attribute LC_PROBE15_TYPE : integer;
  attribute LC_PROBE15_TYPE of U0 : label is 1;
  attribute LC_PROBE15_WIDTH : integer;
  attribute LC_PROBE15_WIDTH of U0 : label is 1;
  attribute LC_PROBE160_IS_DATA : string;
  attribute LC_PROBE160_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE160_IS_TRIG : string;
  attribute LC_PROBE160_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE160_MU_CNT : integer;
  attribute LC_PROBE160_MU_CNT of U0 : label is 1;
  attribute LC_PROBE160_PID : string;
  attribute LC_PROBE160_PID of U0 : label is "16'b0000000010100000";
  attribute LC_PROBE160_TYPE : integer;
  attribute LC_PROBE160_TYPE of U0 : label is 1;
  attribute LC_PROBE160_WIDTH : integer;
  attribute LC_PROBE160_WIDTH of U0 : label is 1;
  attribute LC_PROBE161_IS_DATA : string;
  attribute LC_PROBE161_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE161_IS_TRIG : string;
  attribute LC_PROBE161_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE161_MU_CNT : integer;
  attribute LC_PROBE161_MU_CNT of U0 : label is 1;
  attribute LC_PROBE161_PID : string;
  attribute LC_PROBE161_PID of U0 : label is "16'b0000000010100001";
  attribute LC_PROBE161_TYPE : integer;
  attribute LC_PROBE161_TYPE of U0 : label is 1;
  attribute LC_PROBE161_WIDTH : integer;
  attribute LC_PROBE161_WIDTH of U0 : label is 1;
  attribute LC_PROBE162_IS_DATA : string;
  attribute LC_PROBE162_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE162_IS_TRIG : string;
  attribute LC_PROBE162_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE162_MU_CNT : integer;
  attribute LC_PROBE162_MU_CNT of U0 : label is 1;
  attribute LC_PROBE162_PID : string;
  attribute LC_PROBE162_PID of U0 : label is "16'b0000000010100010";
  attribute LC_PROBE162_TYPE : integer;
  attribute LC_PROBE162_TYPE of U0 : label is 1;
  attribute LC_PROBE162_WIDTH : integer;
  attribute LC_PROBE162_WIDTH of U0 : label is 1;
  attribute LC_PROBE163_IS_DATA : string;
  attribute LC_PROBE163_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE163_IS_TRIG : string;
  attribute LC_PROBE163_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE163_MU_CNT : integer;
  attribute LC_PROBE163_MU_CNT of U0 : label is 1;
  attribute LC_PROBE163_PID : string;
  attribute LC_PROBE163_PID of U0 : label is "16'b0000000010100011";
  attribute LC_PROBE163_TYPE : integer;
  attribute LC_PROBE163_TYPE of U0 : label is 1;
  attribute LC_PROBE163_WIDTH : integer;
  attribute LC_PROBE163_WIDTH of U0 : label is 1;
  attribute LC_PROBE164_IS_DATA : string;
  attribute LC_PROBE164_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE164_IS_TRIG : string;
  attribute LC_PROBE164_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE164_MU_CNT : integer;
  attribute LC_PROBE164_MU_CNT of U0 : label is 1;
  attribute LC_PROBE164_PID : string;
  attribute LC_PROBE164_PID of U0 : label is "16'b0000000010100100";
  attribute LC_PROBE164_TYPE : integer;
  attribute LC_PROBE164_TYPE of U0 : label is 1;
  attribute LC_PROBE164_WIDTH : integer;
  attribute LC_PROBE164_WIDTH of U0 : label is 1;
  attribute LC_PROBE165_IS_DATA : string;
  attribute LC_PROBE165_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE165_IS_TRIG : string;
  attribute LC_PROBE165_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE165_MU_CNT : integer;
  attribute LC_PROBE165_MU_CNT of U0 : label is 1;
  attribute LC_PROBE165_PID : string;
  attribute LC_PROBE165_PID of U0 : label is "16'b0000000010100101";
  attribute LC_PROBE165_TYPE : integer;
  attribute LC_PROBE165_TYPE of U0 : label is 1;
  attribute LC_PROBE165_WIDTH : integer;
  attribute LC_PROBE165_WIDTH of U0 : label is 1;
  attribute LC_PROBE166_IS_DATA : string;
  attribute LC_PROBE166_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE166_IS_TRIG : string;
  attribute LC_PROBE166_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE166_MU_CNT : integer;
  attribute LC_PROBE166_MU_CNT of U0 : label is 1;
  attribute LC_PROBE166_PID : string;
  attribute LC_PROBE166_PID of U0 : label is "16'b0000000010100110";
  attribute LC_PROBE166_TYPE : integer;
  attribute LC_PROBE166_TYPE of U0 : label is 1;
  attribute LC_PROBE166_WIDTH : integer;
  attribute LC_PROBE166_WIDTH of U0 : label is 1;
  attribute LC_PROBE167_IS_DATA : string;
  attribute LC_PROBE167_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE167_IS_TRIG : string;
  attribute LC_PROBE167_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE167_MU_CNT : integer;
  attribute LC_PROBE167_MU_CNT of U0 : label is 1;
  attribute LC_PROBE167_PID : string;
  attribute LC_PROBE167_PID of U0 : label is "16'b0000000010100111";
  attribute LC_PROBE167_TYPE : integer;
  attribute LC_PROBE167_TYPE of U0 : label is 1;
  attribute LC_PROBE167_WIDTH : integer;
  attribute LC_PROBE167_WIDTH of U0 : label is 1;
  attribute LC_PROBE168_IS_DATA : string;
  attribute LC_PROBE168_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE168_IS_TRIG : string;
  attribute LC_PROBE168_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE168_MU_CNT : integer;
  attribute LC_PROBE168_MU_CNT of U0 : label is 1;
  attribute LC_PROBE168_PID : string;
  attribute LC_PROBE168_PID of U0 : label is "16'b0000000010101000";
  attribute LC_PROBE168_TYPE : integer;
  attribute LC_PROBE168_TYPE of U0 : label is 1;
  attribute LC_PROBE168_WIDTH : integer;
  attribute LC_PROBE168_WIDTH of U0 : label is 1;
  attribute LC_PROBE169_IS_DATA : string;
  attribute LC_PROBE169_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE169_IS_TRIG : string;
  attribute LC_PROBE169_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE169_MU_CNT : integer;
  attribute LC_PROBE169_MU_CNT of U0 : label is 1;
  attribute LC_PROBE169_PID : string;
  attribute LC_PROBE169_PID of U0 : label is "16'b0000000010101001";
  attribute LC_PROBE169_TYPE : integer;
  attribute LC_PROBE169_TYPE of U0 : label is 1;
  attribute LC_PROBE169_WIDTH : integer;
  attribute LC_PROBE169_WIDTH of U0 : label is 1;
  attribute LC_PROBE16_IS_DATA : string;
  attribute LC_PROBE16_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE16_IS_TRIG : string;
  attribute LC_PROBE16_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE16_MU_CNT : integer;
  attribute LC_PROBE16_MU_CNT of U0 : label is 1;
  attribute LC_PROBE16_PID : string;
  attribute LC_PROBE16_PID of U0 : label is "16'b0000000000010000";
  attribute LC_PROBE16_TYPE : integer;
  attribute LC_PROBE16_TYPE of U0 : label is 1;
  attribute LC_PROBE16_WIDTH : integer;
  attribute LC_PROBE16_WIDTH of U0 : label is 1;
  attribute LC_PROBE170_IS_DATA : string;
  attribute LC_PROBE170_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE170_IS_TRIG : string;
  attribute LC_PROBE170_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE170_MU_CNT : integer;
  attribute LC_PROBE170_MU_CNT of U0 : label is 1;
  attribute LC_PROBE170_PID : string;
  attribute LC_PROBE170_PID of U0 : label is "16'b0000000010101010";
  attribute LC_PROBE170_TYPE : integer;
  attribute LC_PROBE170_TYPE of U0 : label is 1;
  attribute LC_PROBE170_WIDTH : integer;
  attribute LC_PROBE170_WIDTH of U0 : label is 1;
  attribute LC_PROBE171_IS_DATA : string;
  attribute LC_PROBE171_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE171_IS_TRIG : string;
  attribute LC_PROBE171_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE171_MU_CNT : integer;
  attribute LC_PROBE171_MU_CNT of U0 : label is 1;
  attribute LC_PROBE171_PID : string;
  attribute LC_PROBE171_PID of U0 : label is "16'b0000000010101011";
  attribute LC_PROBE171_TYPE : integer;
  attribute LC_PROBE171_TYPE of U0 : label is 1;
  attribute LC_PROBE171_WIDTH : integer;
  attribute LC_PROBE171_WIDTH of U0 : label is 1;
  attribute LC_PROBE172_IS_DATA : string;
  attribute LC_PROBE172_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE172_IS_TRIG : string;
  attribute LC_PROBE172_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE172_MU_CNT : integer;
  attribute LC_PROBE172_MU_CNT of U0 : label is 1;
  attribute LC_PROBE172_PID : string;
  attribute LC_PROBE172_PID of U0 : label is "16'b0000000010101100";
  attribute LC_PROBE172_TYPE : integer;
  attribute LC_PROBE172_TYPE of U0 : label is 1;
  attribute LC_PROBE172_WIDTH : integer;
  attribute LC_PROBE172_WIDTH of U0 : label is 1;
  attribute LC_PROBE173_IS_DATA : string;
  attribute LC_PROBE173_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE173_IS_TRIG : string;
  attribute LC_PROBE173_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE173_MU_CNT : integer;
  attribute LC_PROBE173_MU_CNT of U0 : label is 1;
  attribute LC_PROBE173_PID : string;
  attribute LC_PROBE173_PID of U0 : label is "16'b0000000010101101";
  attribute LC_PROBE173_TYPE : integer;
  attribute LC_PROBE173_TYPE of U0 : label is 1;
  attribute LC_PROBE173_WIDTH : integer;
  attribute LC_PROBE173_WIDTH of U0 : label is 1;
  attribute LC_PROBE174_IS_DATA : string;
  attribute LC_PROBE174_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE174_IS_TRIG : string;
  attribute LC_PROBE174_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE174_MU_CNT : integer;
  attribute LC_PROBE174_MU_CNT of U0 : label is 1;
  attribute LC_PROBE174_PID : string;
  attribute LC_PROBE174_PID of U0 : label is "16'b0000000010101110";
  attribute LC_PROBE174_TYPE : integer;
  attribute LC_PROBE174_TYPE of U0 : label is 1;
  attribute LC_PROBE174_WIDTH : integer;
  attribute LC_PROBE174_WIDTH of U0 : label is 1;
  attribute LC_PROBE175_IS_DATA : string;
  attribute LC_PROBE175_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE175_IS_TRIG : string;
  attribute LC_PROBE175_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE175_MU_CNT : integer;
  attribute LC_PROBE175_MU_CNT of U0 : label is 1;
  attribute LC_PROBE175_PID : string;
  attribute LC_PROBE175_PID of U0 : label is "16'b0000000010101111";
  attribute LC_PROBE175_TYPE : integer;
  attribute LC_PROBE175_TYPE of U0 : label is 1;
  attribute LC_PROBE175_WIDTH : integer;
  attribute LC_PROBE175_WIDTH of U0 : label is 1;
  attribute LC_PROBE176_IS_DATA : string;
  attribute LC_PROBE176_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE176_IS_TRIG : string;
  attribute LC_PROBE176_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE176_MU_CNT : integer;
  attribute LC_PROBE176_MU_CNT of U0 : label is 1;
  attribute LC_PROBE176_PID : string;
  attribute LC_PROBE176_PID of U0 : label is "16'b0000000010110000";
  attribute LC_PROBE176_TYPE : integer;
  attribute LC_PROBE176_TYPE of U0 : label is 1;
  attribute LC_PROBE176_WIDTH : integer;
  attribute LC_PROBE176_WIDTH of U0 : label is 1;
  attribute LC_PROBE177_IS_DATA : string;
  attribute LC_PROBE177_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE177_IS_TRIG : string;
  attribute LC_PROBE177_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE177_MU_CNT : integer;
  attribute LC_PROBE177_MU_CNT of U0 : label is 1;
  attribute LC_PROBE177_PID : string;
  attribute LC_PROBE177_PID of U0 : label is "16'b0000000010110001";
  attribute LC_PROBE177_TYPE : integer;
  attribute LC_PROBE177_TYPE of U0 : label is 1;
  attribute LC_PROBE177_WIDTH : integer;
  attribute LC_PROBE177_WIDTH of U0 : label is 1;
  attribute LC_PROBE178_IS_DATA : string;
  attribute LC_PROBE178_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE178_IS_TRIG : string;
  attribute LC_PROBE178_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE178_MU_CNT : integer;
  attribute LC_PROBE178_MU_CNT of U0 : label is 1;
  attribute LC_PROBE178_PID : string;
  attribute LC_PROBE178_PID of U0 : label is "16'b0000000010110010";
  attribute LC_PROBE178_TYPE : integer;
  attribute LC_PROBE178_TYPE of U0 : label is 1;
  attribute LC_PROBE178_WIDTH : integer;
  attribute LC_PROBE178_WIDTH of U0 : label is 1;
  attribute LC_PROBE179_IS_DATA : string;
  attribute LC_PROBE179_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE179_IS_TRIG : string;
  attribute LC_PROBE179_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE179_MU_CNT : integer;
  attribute LC_PROBE179_MU_CNT of U0 : label is 1;
  attribute LC_PROBE179_PID : string;
  attribute LC_PROBE179_PID of U0 : label is "16'b0000000010110011";
  attribute LC_PROBE179_TYPE : integer;
  attribute LC_PROBE179_TYPE of U0 : label is 1;
  attribute LC_PROBE179_WIDTH : integer;
  attribute LC_PROBE179_WIDTH of U0 : label is 1;
  attribute LC_PROBE17_IS_DATA : string;
  attribute LC_PROBE17_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE17_IS_TRIG : string;
  attribute LC_PROBE17_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE17_MU_CNT : integer;
  attribute LC_PROBE17_MU_CNT of U0 : label is 1;
  attribute LC_PROBE17_PID : string;
  attribute LC_PROBE17_PID of U0 : label is "16'b0000000000010001";
  attribute LC_PROBE17_TYPE : integer;
  attribute LC_PROBE17_TYPE of U0 : label is 1;
  attribute LC_PROBE17_WIDTH : integer;
  attribute LC_PROBE17_WIDTH of U0 : label is 1;
  attribute LC_PROBE180_IS_DATA : string;
  attribute LC_PROBE180_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE180_IS_TRIG : string;
  attribute LC_PROBE180_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE180_MU_CNT : integer;
  attribute LC_PROBE180_MU_CNT of U0 : label is 1;
  attribute LC_PROBE180_PID : string;
  attribute LC_PROBE180_PID of U0 : label is "16'b0000000010110100";
  attribute LC_PROBE180_TYPE : integer;
  attribute LC_PROBE180_TYPE of U0 : label is 1;
  attribute LC_PROBE180_WIDTH : integer;
  attribute LC_PROBE180_WIDTH of U0 : label is 1;
  attribute LC_PROBE181_IS_DATA : string;
  attribute LC_PROBE181_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE181_IS_TRIG : string;
  attribute LC_PROBE181_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE181_MU_CNT : integer;
  attribute LC_PROBE181_MU_CNT of U0 : label is 1;
  attribute LC_PROBE181_PID : string;
  attribute LC_PROBE181_PID of U0 : label is "16'b0000000010110101";
  attribute LC_PROBE181_TYPE : integer;
  attribute LC_PROBE181_TYPE of U0 : label is 1;
  attribute LC_PROBE181_WIDTH : integer;
  attribute LC_PROBE181_WIDTH of U0 : label is 1;
  attribute LC_PROBE182_IS_DATA : string;
  attribute LC_PROBE182_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE182_IS_TRIG : string;
  attribute LC_PROBE182_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE182_MU_CNT : integer;
  attribute LC_PROBE182_MU_CNT of U0 : label is 1;
  attribute LC_PROBE182_PID : string;
  attribute LC_PROBE182_PID of U0 : label is "16'b0000000010110110";
  attribute LC_PROBE182_TYPE : integer;
  attribute LC_PROBE182_TYPE of U0 : label is 1;
  attribute LC_PROBE182_WIDTH : integer;
  attribute LC_PROBE182_WIDTH of U0 : label is 1;
  attribute LC_PROBE183_IS_DATA : string;
  attribute LC_PROBE183_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE183_IS_TRIG : string;
  attribute LC_PROBE183_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE183_MU_CNT : integer;
  attribute LC_PROBE183_MU_CNT of U0 : label is 1;
  attribute LC_PROBE183_PID : string;
  attribute LC_PROBE183_PID of U0 : label is "16'b0000000010110111";
  attribute LC_PROBE183_TYPE : integer;
  attribute LC_PROBE183_TYPE of U0 : label is 1;
  attribute LC_PROBE183_WIDTH : integer;
  attribute LC_PROBE183_WIDTH of U0 : label is 1;
  attribute LC_PROBE184_IS_DATA : string;
  attribute LC_PROBE184_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE184_IS_TRIG : string;
  attribute LC_PROBE184_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE184_MU_CNT : integer;
  attribute LC_PROBE184_MU_CNT of U0 : label is 1;
  attribute LC_PROBE184_PID : string;
  attribute LC_PROBE184_PID of U0 : label is "16'b0000000010111000";
  attribute LC_PROBE184_TYPE : integer;
  attribute LC_PROBE184_TYPE of U0 : label is 1;
  attribute LC_PROBE184_WIDTH : integer;
  attribute LC_PROBE184_WIDTH of U0 : label is 1;
  attribute LC_PROBE185_IS_DATA : string;
  attribute LC_PROBE185_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE185_IS_TRIG : string;
  attribute LC_PROBE185_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE185_MU_CNT : integer;
  attribute LC_PROBE185_MU_CNT of U0 : label is 1;
  attribute LC_PROBE185_PID : string;
  attribute LC_PROBE185_PID of U0 : label is "16'b0000000010111001";
  attribute LC_PROBE185_TYPE : integer;
  attribute LC_PROBE185_TYPE of U0 : label is 1;
  attribute LC_PROBE185_WIDTH : integer;
  attribute LC_PROBE185_WIDTH of U0 : label is 1;
  attribute LC_PROBE186_IS_DATA : string;
  attribute LC_PROBE186_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE186_IS_TRIG : string;
  attribute LC_PROBE186_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE186_MU_CNT : integer;
  attribute LC_PROBE186_MU_CNT of U0 : label is 1;
  attribute LC_PROBE186_PID : string;
  attribute LC_PROBE186_PID of U0 : label is "16'b0000000010111010";
  attribute LC_PROBE186_TYPE : integer;
  attribute LC_PROBE186_TYPE of U0 : label is 1;
  attribute LC_PROBE186_WIDTH : integer;
  attribute LC_PROBE186_WIDTH of U0 : label is 1;
  attribute LC_PROBE187_IS_DATA : string;
  attribute LC_PROBE187_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE187_IS_TRIG : string;
  attribute LC_PROBE187_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE187_MU_CNT : integer;
  attribute LC_PROBE187_MU_CNT of U0 : label is 1;
  attribute LC_PROBE187_PID : string;
  attribute LC_PROBE187_PID of U0 : label is "16'b0000000010111011";
  attribute LC_PROBE187_TYPE : integer;
  attribute LC_PROBE187_TYPE of U0 : label is 1;
  attribute LC_PROBE187_WIDTH : integer;
  attribute LC_PROBE187_WIDTH of U0 : label is 1;
  attribute LC_PROBE188_IS_DATA : string;
  attribute LC_PROBE188_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE188_IS_TRIG : string;
  attribute LC_PROBE188_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE188_MU_CNT : integer;
  attribute LC_PROBE188_MU_CNT of U0 : label is 1;
  attribute LC_PROBE188_PID : string;
  attribute LC_PROBE188_PID of U0 : label is "16'b0000000010111100";
  attribute LC_PROBE188_TYPE : integer;
  attribute LC_PROBE188_TYPE of U0 : label is 1;
  attribute LC_PROBE188_WIDTH : integer;
  attribute LC_PROBE188_WIDTH of U0 : label is 1;
  attribute LC_PROBE189_IS_DATA : string;
  attribute LC_PROBE189_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE189_IS_TRIG : string;
  attribute LC_PROBE189_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE189_MU_CNT : integer;
  attribute LC_PROBE189_MU_CNT of U0 : label is 1;
  attribute LC_PROBE189_PID : string;
  attribute LC_PROBE189_PID of U0 : label is "16'b0000000010111101";
  attribute LC_PROBE189_TYPE : integer;
  attribute LC_PROBE189_TYPE of U0 : label is 1;
  attribute LC_PROBE189_WIDTH : integer;
  attribute LC_PROBE189_WIDTH of U0 : label is 1;
  attribute LC_PROBE18_IS_DATA : string;
  attribute LC_PROBE18_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE18_IS_TRIG : string;
  attribute LC_PROBE18_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE18_MU_CNT : integer;
  attribute LC_PROBE18_MU_CNT of U0 : label is 1;
  attribute LC_PROBE18_PID : string;
  attribute LC_PROBE18_PID of U0 : label is "16'b0000000000010010";
  attribute LC_PROBE18_TYPE : integer;
  attribute LC_PROBE18_TYPE of U0 : label is 1;
  attribute LC_PROBE18_WIDTH : integer;
  attribute LC_PROBE18_WIDTH of U0 : label is 1;
  attribute LC_PROBE190_IS_DATA : string;
  attribute LC_PROBE190_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE190_IS_TRIG : string;
  attribute LC_PROBE190_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE190_MU_CNT : integer;
  attribute LC_PROBE190_MU_CNT of U0 : label is 1;
  attribute LC_PROBE190_PID : string;
  attribute LC_PROBE190_PID of U0 : label is "16'b0000000010111110";
  attribute LC_PROBE190_TYPE : integer;
  attribute LC_PROBE190_TYPE of U0 : label is 1;
  attribute LC_PROBE190_WIDTH : integer;
  attribute LC_PROBE190_WIDTH of U0 : label is 1;
  attribute LC_PROBE191_IS_DATA : string;
  attribute LC_PROBE191_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE191_IS_TRIG : string;
  attribute LC_PROBE191_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE191_MU_CNT : integer;
  attribute LC_PROBE191_MU_CNT of U0 : label is 1;
  attribute LC_PROBE191_PID : string;
  attribute LC_PROBE191_PID of U0 : label is "16'b0000000010111111";
  attribute LC_PROBE191_TYPE : integer;
  attribute LC_PROBE191_TYPE of U0 : label is 1;
  attribute LC_PROBE191_WIDTH : integer;
  attribute LC_PROBE191_WIDTH of U0 : label is 1;
  attribute LC_PROBE192_IS_DATA : string;
  attribute LC_PROBE192_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE192_IS_TRIG : string;
  attribute LC_PROBE192_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE192_MU_CNT : integer;
  attribute LC_PROBE192_MU_CNT of U0 : label is 1;
  attribute LC_PROBE192_PID : string;
  attribute LC_PROBE192_PID of U0 : label is "16'b0000000011000000";
  attribute LC_PROBE192_TYPE : integer;
  attribute LC_PROBE192_TYPE of U0 : label is 1;
  attribute LC_PROBE192_WIDTH : integer;
  attribute LC_PROBE192_WIDTH of U0 : label is 1;
  attribute LC_PROBE193_IS_DATA : string;
  attribute LC_PROBE193_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE193_IS_TRIG : string;
  attribute LC_PROBE193_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE193_MU_CNT : integer;
  attribute LC_PROBE193_MU_CNT of U0 : label is 1;
  attribute LC_PROBE193_PID : string;
  attribute LC_PROBE193_PID of U0 : label is "16'b0000000011000001";
  attribute LC_PROBE193_TYPE : integer;
  attribute LC_PROBE193_TYPE of U0 : label is 1;
  attribute LC_PROBE193_WIDTH : integer;
  attribute LC_PROBE193_WIDTH of U0 : label is 1;
  attribute LC_PROBE194_IS_DATA : string;
  attribute LC_PROBE194_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE194_IS_TRIG : string;
  attribute LC_PROBE194_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE194_MU_CNT : integer;
  attribute LC_PROBE194_MU_CNT of U0 : label is 1;
  attribute LC_PROBE194_PID : string;
  attribute LC_PROBE194_PID of U0 : label is "16'b0000000011000010";
  attribute LC_PROBE194_TYPE : integer;
  attribute LC_PROBE194_TYPE of U0 : label is 1;
  attribute LC_PROBE194_WIDTH : integer;
  attribute LC_PROBE194_WIDTH of U0 : label is 1;
  attribute LC_PROBE195_IS_DATA : string;
  attribute LC_PROBE195_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE195_IS_TRIG : string;
  attribute LC_PROBE195_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE195_MU_CNT : integer;
  attribute LC_PROBE195_MU_CNT of U0 : label is 1;
  attribute LC_PROBE195_PID : string;
  attribute LC_PROBE195_PID of U0 : label is "16'b0000000011000011";
  attribute LC_PROBE195_TYPE : integer;
  attribute LC_PROBE195_TYPE of U0 : label is 1;
  attribute LC_PROBE195_WIDTH : integer;
  attribute LC_PROBE195_WIDTH of U0 : label is 1;
  attribute LC_PROBE196_IS_DATA : string;
  attribute LC_PROBE196_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE196_IS_TRIG : string;
  attribute LC_PROBE196_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE196_MU_CNT : integer;
  attribute LC_PROBE196_MU_CNT of U0 : label is 1;
  attribute LC_PROBE196_PID : string;
  attribute LC_PROBE196_PID of U0 : label is "16'b0000000011000100";
  attribute LC_PROBE196_TYPE : integer;
  attribute LC_PROBE196_TYPE of U0 : label is 1;
  attribute LC_PROBE196_WIDTH : integer;
  attribute LC_PROBE196_WIDTH of U0 : label is 1;
  attribute LC_PROBE197_IS_DATA : string;
  attribute LC_PROBE197_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE197_IS_TRIG : string;
  attribute LC_PROBE197_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE197_MU_CNT : integer;
  attribute LC_PROBE197_MU_CNT of U0 : label is 1;
  attribute LC_PROBE197_PID : string;
  attribute LC_PROBE197_PID of U0 : label is "16'b0000000011000101";
  attribute LC_PROBE197_TYPE : integer;
  attribute LC_PROBE197_TYPE of U0 : label is 1;
  attribute LC_PROBE197_WIDTH : integer;
  attribute LC_PROBE197_WIDTH of U0 : label is 1;
  attribute LC_PROBE198_IS_DATA : string;
  attribute LC_PROBE198_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE198_IS_TRIG : string;
  attribute LC_PROBE198_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE198_MU_CNT : integer;
  attribute LC_PROBE198_MU_CNT of U0 : label is 1;
  attribute LC_PROBE198_PID : string;
  attribute LC_PROBE198_PID of U0 : label is "16'b0000000011000110";
  attribute LC_PROBE198_TYPE : integer;
  attribute LC_PROBE198_TYPE of U0 : label is 1;
  attribute LC_PROBE198_WIDTH : integer;
  attribute LC_PROBE198_WIDTH of U0 : label is 1;
  attribute LC_PROBE199_IS_DATA : string;
  attribute LC_PROBE199_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE199_IS_TRIG : string;
  attribute LC_PROBE199_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE199_MU_CNT : integer;
  attribute LC_PROBE199_MU_CNT of U0 : label is 1;
  attribute LC_PROBE199_PID : string;
  attribute LC_PROBE199_PID of U0 : label is "16'b0000000011000111";
  attribute LC_PROBE199_TYPE : integer;
  attribute LC_PROBE199_TYPE of U0 : label is 1;
  attribute LC_PROBE199_WIDTH : integer;
  attribute LC_PROBE199_WIDTH of U0 : label is 1;
  attribute LC_PROBE19_IS_DATA : string;
  attribute LC_PROBE19_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE19_IS_TRIG : string;
  attribute LC_PROBE19_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE19_MU_CNT : integer;
  attribute LC_PROBE19_MU_CNT of U0 : label is 1;
  attribute LC_PROBE19_PID : string;
  attribute LC_PROBE19_PID of U0 : label is "16'b0000000000010011";
  attribute LC_PROBE19_TYPE : integer;
  attribute LC_PROBE19_TYPE of U0 : label is 1;
  attribute LC_PROBE19_WIDTH : integer;
  attribute LC_PROBE19_WIDTH of U0 : label is 1;
  attribute LC_PROBE1_IS_DATA : string;
  attribute LC_PROBE1_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE1_IS_TRIG : string;
  attribute LC_PROBE1_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE1_MU_CNT : integer;
  attribute LC_PROBE1_MU_CNT of U0 : label is 1;
  attribute LC_PROBE1_PID : string;
  attribute LC_PROBE1_PID of U0 : label is "16'b0000000000000001";
  attribute LC_PROBE1_TYPE : integer;
  attribute LC_PROBE1_TYPE of U0 : label is 0;
  attribute LC_PROBE1_WIDTH : integer;
  attribute LC_PROBE1_WIDTH of U0 : label is 1;
  attribute LC_PROBE200_IS_DATA : string;
  attribute LC_PROBE200_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE200_IS_TRIG : string;
  attribute LC_PROBE200_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE200_MU_CNT : integer;
  attribute LC_PROBE200_MU_CNT of U0 : label is 1;
  attribute LC_PROBE200_PID : string;
  attribute LC_PROBE200_PID of U0 : label is "16'b0000000011001000";
  attribute LC_PROBE200_TYPE : integer;
  attribute LC_PROBE200_TYPE of U0 : label is 1;
  attribute LC_PROBE200_WIDTH : integer;
  attribute LC_PROBE200_WIDTH of U0 : label is 1;
  attribute LC_PROBE201_IS_DATA : string;
  attribute LC_PROBE201_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE201_IS_TRIG : string;
  attribute LC_PROBE201_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE201_MU_CNT : integer;
  attribute LC_PROBE201_MU_CNT of U0 : label is 1;
  attribute LC_PROBE201_PID : string;
  attribute LC_PROBE201_PID of U0 : label is "16'b0000000011001001";
  attribute LC_PROBE201_TYPE : integer;
  attribute LC_PROBE201_TYPE of U0 : label is 1;
  attribute LC_PROBE201_WIDTH : integer;
  attribute LC_PROBE201_WIDTH of U0 : label is 1;
  attribute LC_PROBE202_IS_DATA : string;
  attribute LC_PROBE202_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE202_IS_TRIG : string;
  attribute LC_PROBE202_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE202_MU_CNT : integer;
  attribute LC_PROBE202_MU_CNT of U0 : label is 1;
  attribute LC_PROBE202_PID : string;
  attribute LC_PROBE202_PID of U0 : label is "16'b0000000011001010";
  attribute LC_PROBE202_TYPE : integer;
  attribute LC_PROBE202_TYPE of U0 : label is 1;
  attribute LC_PROBE202_WIDTH : integer;
  attribute LC_PROBE202_WIDTH of U0 : label is 1;
  attribute LC_PROBE203_IS_DATA : string;
  attribute LC_PROBE203_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE203_IS_TRIG : string;
  attribute LC_PROBE203_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE203_MU_CNT : integer;
  attribute LC_PROBE203_MU_CNT of U0 : label is 1;
  attribute LC_PROBE203_PID : string;
  attribute LC_PROBE203_PID of U0 : label is "16'b0000000011001011";
  attribute LC_PROBE203_TYPE : integer;
  attribute LC_PROBE203_TYPE of U0 : label is 1;
  attribute LC_PROBE203_WIDTH : integer;
  attribute LC_PROBE203_WIDTH of U0 : label is 1;
  attribute LC_PROBE204_IS_DATA : string;
  attribute LC_PROBE204_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE204_IS_TRIG : string;
  attribute LC_PROBE204_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE204_MU_CNT : integer;
  attribute LC_PROBE204_MU_CNT of U0 : label is 1;
  attribute LC_PROBE204_PID : string;
  attribute LC_PROBE204_PID of U0 : label is "16'b0000000011001100";
  attribute LC_PROBE204_TYPE : integer;
  attribute LC_PROBE204_TYPE of U0 : label is 1;
  attribute LC_PROBE204_WIDTH : integer;
  attribute LC_PROBE204_WIDTH of U0 : label is 1;
  attribute LC_PROBE205_IS_DATA : string;
  attribute LC_PROBE205_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE205_IS_TRIG : string;
  attribute LC_PROBE205_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE205_MU_CNT : integer;
  attribute LC_PROBE205_MU_CNT of U0 : label is 1;
  attribute LC_PROBE205_PID : string;
  attribute LC_PROBE205_PID of U0 : label is "16'b0000000011001101";
  attribute LC_PROBE205_TYPE : integer;
  attribute LC_PROBE205_TYPE of U0 : label is 1;
  attribute LC_PROBE205_WIDTH : integer;
  attribute LC_PROBE205_WIDTH of U0 : label is 1;
  attribute LC_PROBE206_IS_DATA : string;
  attribute LC_PROBE206_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE206_IS_TRIG : string;
  attribute LC_PROBE206_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE206_MU_CNT : integer;
  attribute LC_PROBE206_MU_CNT of U0 : label is 1;
  attribute LC_PROBE206_PID : string;
  attribute LC_PROBE206_PID of U0 : label is "16'b0000000011001110";
  attribute LC_PROBE206_TYPE : integer;
  attribute LC_PROBE206_TYPE of U0 : label is 1;
  attribute LC_PROBE206_WIDTH : integer;
  attribute LC_PROBE206_WIDTH of U0 : label is 1;
  attribute LC_PROBE207_IS_DATA : string;
  attribute LC_PROBE207_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE207_IS_TRIG : string;
  attribute LC_PROBE207_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE207_MU_CNT : integer;
  attribute LC_PROBE207_MU_CNT of U0 : label is 1;
  attribute LC_PROBE207_PID : string;
  attribute LC_PROBE207_PID of U0 : label is "16'b0000000011001111";
  attribute LC_PROBE207_TYPE : integer;
  attribute LC_PROBE207_TYPE of U0 : label is 1;
  attribute LC_PROBE207_WIDTH : integer;
  attribute LC_PROBE207_WIDTH of U0 : label is 1;
  attribute LC_PROBE208_IS_DATA : string;
  attribute LC_PROBE208_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE208_IS_TRIG : string;
  attribute LC_PROBE208_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE208_MU_CNT : integer;
  attribute LC_PROBE208_MU_CNT of U0 : label is 1;
  attribute LC_PROBE208_PID : string;
  attribute LC_PROBE208_PID of U0 : label is "16'b0000000011010000";
  attribute LC_PROBE208_TYPE : integer;
  attribute LC_PROBE208_TYPE of U0 : label is 1;
  attribute LC_PROBE208_WIDTH : integer;
  attribute LC_PROBE208_WIDTH of U0 : label is 1;
  attribute LC_PROBE209_IS_DATA : string;
  attribute LC_PROBE209_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE209_IS_TRIG : string;
  attribute LC_PROBE209_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE209_MU_CNT : integer;
  attribute LC_PROBE209_MU_CNT of U0 : label is 1;
  attribute LC_PROBE209_PID : string;
  attribute LC_PROBE209_PID of U0 : label is "16'b0000000011010001";
  attribute LC_PROBE209_TYPE : integer;
  attribute LC_PROBE209_TYPE of U0 : label is 1;
  attribute LC_PROBE209_WIDTH : integer;
  attribute LC_PROBE209_WIDTH of U0 : label is 1;
  attribute LC_PROBE20_IS_DATA : string;
  attribute LC_PROBE20_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE20_IS_TRIG : string;
  attribute LC_PROBE20_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE20_MU_CNT : integer;
  attribute LC_PROBE20_MU_CNT of U0 : label is 1;
  attribute LC_PROBE20_PID : string;
  attribute LC_PROBE20_PID of U0 : label is "16'b0000000000010100";
  attribute LC_PROBE20_TYPE : integer;
  attribute LC_PROBE20_TYPE of U0 : label is 1;
  attribute LC_PROBE20_WIDTH : integer;
  attribute LC_PROBE20_WIDTH of U0 : label is 1;
  attribute LC_PROBE210_IS_DATA : string;
  attribute LC_PROBE210_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE210_IS_TRIG : string;
  attribute LC_PROBE210_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE210_MU_CNT : integer;
  attribute LC_PROBE210_MU_CNT of U0 : label is 1;
  attribute LC_PROBE210_PID : string;
  attribute LC_PROBE210_PID of U0 : label is "16'b0000000011010010";
  attribute LC_PROBE210_TYPE : integer;
  attribute LC_PROBE210_TYPE of U0 : label is 1;
  attribute LC_PROBE210_WIDTH : integer;
  attribute LC_PROBE210_WIDTH of U0 : label is 1;
  attribute LC_PROBE211_IS_DATA : string;
  attribute LC_PROBE211_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE211_IS_TRIG : string;
  attribute LC_PROBE211_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE211_MU_CNT : integer;
  attribute LC_PROBE211_MU_CNT of U0 : label is 1;
  attribute LC_PROBE211_PID : string;
  attribute LC_PROBE211_PID of U0 : label is "16'b0000000011010011";
  attribute LC_PROBE211_TYPE : integer;
  attribute LC_PROBE211_TYPE of U0 : label is 1;
  attribute LC_PROBE211_WIDTH : integer;
  attribute LC_PROBE211_WIDTH of U0 : label is 1;
  attribute LC_PROBE212_IS_DATA : string;
  attribute LC_PROBE212_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE212_IS_TRIG : string;
  attribute LC_PROBE212_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE212_MU_CNT : integer;
  attribute LC_PROBE212_MU_CNT of U0 : label is 1;
  attribute LC_PROBE212_PID : string;
  attribute LC_PROBE212_PID of U0 : label is "16'b0000000011010100";
  attribute LC_PROBE212_TYPE : integer;
  attribute LC_PROBE212_TYPE of U0 : label is 1;
  attribute LC_PROBE212_WIDTH : integer;
  attribute LC_PROBE212_WIDTH of U0 : label is 1;
  attribute LC_PROBE213_IS_DATA : string;
  attribute LC_PROBE213_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE213_IS_TRIG : string;
  attribute LC_PROBE213_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE213_MU_CNT : integer;
  attribute LC_PROBE213_MU_CNT of U0 : label is 1;
  attribute LC_PROBE213_PID : string;
  attribute LC_PROBE213_PID of U0 : label is "16'b0000000011010101";
  attribute LC_PROBE213_TYPE : integer;
  attribute LC_PROBE213_TYPE of U0 : label is 1;
  attribute LC_PROBE213_WIDTH : integer;
  attribute LC_PROBE213_WIDTH of U0 : label is 1;
  attribute LC_PROBE214_IS_DATA : string;
  attribute LC_PROBE214_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE214_IS_TRIG : string;
  attribute LC_PROBE214_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE214_MU_CNT : integer;
  attribute LC_PROBE214_MU_CNT of U0 : label is 1;
  attribute LC_PROBE214_PID : string;
  attribute LC_PROBE214_PID of U0 : label is "16'b0000000011010110";
  attribute LC_PROBE214_TYPE : integer;
  attribute LC_PROBE214_TYPE of U0 : label is 1;
  attribute LC_PROBE214_WIDTH : integer;
  attribute LC_PROBE214_WIDTH of U0 : label is 1;
  attribute LC_PROBE215_IS_DATA : string;
  attribute LC_PROBE215_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE215_IS_TRIG : string;
  attribute LC_PROBE215_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE215_MU_CNT : integer;
  attribute LC_PROBE215_MU_CNT of U0 : label is 1;
  attribute LC_PROBE215_PID : string;
  attribute LC_PROBE215_PID of U0 : label is "16'b0000000011010111";
  attribute LC_PROBE215_TYPE : integer;
  attribute LC_PROBE215_TYPE of U0 : label is 1;
  attribute LC_PROBE215_WIDTH : integer;
  attribute LC_PROBE215_WIDTH of U0 : label is 1;
  attribute LC_PROBE216_IS_DATA : string;
  attribute LC_PROBE216_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE216_IS_TRIG : string;
  attribute LC_PROBE216_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE216_MU_CNT : integer;
  attribute LC_PROBE216_MU_CNT of U0 : label is 1;
  attribute LC_PROBE216_PID : string;
  attribute LC_PROBE216_PID of U0 : label is "16'b0000000011011000";
  attribute LC_PROBE216_TYPE : integer;
  attribute LC_PROBE216_TYPE of U0 : label is 1;
  attribute LC_PROBE216_WIDTH : integer;
  attribute LC_PROBE216_WIDTH of U0 : label is 1;
  attribute LC_PROBE217_IS_DATA : string;
  attribute LC_PROBE217_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE217_IS_TRIG : string;
  attribute LC_PROBE217_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE217_MU_CNT : integer;
  attribute LC_PROBE217_MU_CNT of U0 : label is 1;
  attribute LC_PROBE217_PID : string;
  attribute LC_PROBE217_PID of U0 : label is "16'b0000000011011001";
  attribute LC_PROBE217_TYPE : integer;
  attribute LC_PROBE217_TYPE of U0 : label is 1;
  attribute LC_PROBE217_WIDTH : integer;
  attribute LC_PROBE217_WIDTH of U0 : label is 1;
  attribute LC_PROBE218_IS_DATA : string;
  attribute LC_PROBE218_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE218_IS_TRIG : string;
  attribute LC_PROBE218_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE218_MU_CNT : integer;
  attribute LC_PROBE218_MU_CNT of U0 : label is 1;
  attribute LC_PROBE218_PID : string;
  attribute LC_PROBE218_PID of U0 : label is "16'b0000000011011010";
  attribute LC_PROBE218_TYPE : integer;
  attribute LC_PROBE218_TYPE of U0 : label is 1;
  attribute LC_PROBE218_WIDTH : integer;
  attribute LC_PROBE218_WIDTH of U0 : label is 1;
  attribute LC_PROBE219_IS_DATA : string;
  attribute LC_PROBE219_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE219_IS_TRIG : string;
  attribute LC_PROBE219_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE219_MU_CNT : integer;
  attribute LC_PROBE219_MU_CNT of U0 : label is 1;
  attribute LC_PROBE219_PID : string;
  attribute LC_PROBE219_PID of U0 : label is "16'b0000000011011011";
  attribute LC_PROBE219_TYPE : integer;
  attribute LC_PROBE219_TYPE of U0 : label is 1;
  attribute LC_PROBE219_WIDTH : integer;
  attribute LC_PROBE219_WIDTH of U0 : label is 1;
  attribute LC_PROBE21_IS_DATA : string;
  attribute LC_PROBE21_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE21_IS_TRIG : string;
  attribute LC_PROBE21_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE21_MU_CNT : integer;
  attribute LC_PROBE21_MU_CNT of U0 : label is 1;
  attribute LC_PROBE21_PID : string;
  attribute LC_PROBE21_PID of U0 : label is "16'b0000000000010101";
  attribute LC_PROBE21_TYPE : integer;
  attribute LC_PROBE21_TYPE of U0 : label is 1;
  attribute LC_PROBE21_WIDTH : integer;
  attribute LC_PROBE21_WIDTH of U0 : label is 1;
  attribute LC_PROBE220_IS_DATA : string;
  attribute LC_PROBE220_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE220_IS_TRIG : string;
  attribute LC_PROBE220_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE220_MU_CNT : integer;
  attribute LC_PROBE220_MU_CNT of U0 : label is 1;
  attribute LC_PROBE220_PID : string;
  attribute LC_PROBE220_PID of U0 : label is "16'b0000000011011100";
  attribute LC_PROBE220_TYPE : integer;
  attribute LC_PROBE220_TYPE of U0 : label is 1;
  attribute LC_PROBE220_WIDTH : integer;
  attribute LC_PROBE220_WIDTH of U0 : label is 1;
  attribute LC_PROBE221_IS_DATA : string;
  attribute LC_PROBE221_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE221_IS_TRIG : string;
  attribute LC_PROBE221_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE221_MU_CNT : integer;
  attribute LC_PROBE221_MU_CNT of U0 : label is 1;
  attribute LC_PROBE221_PID : string;
  attribute LC_PROBE221_PID of U0 : label is "16'b0000000011011101";
  attribute LC_PROBE221_TYPE : integer;
  attribute LC_PROBE221_TYPE of U0 : label is 1;
  attribute LC_PROBE221_WIDTH : integer;
  attribute LC_PROBE221_WIDTH of U0 : label is 1;
  attribute LC_PROBE222_IS_DATA : string;
  attribute LC_PROBE222_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE222_IS_TRIG : string;
  attribute LC_PROBE222_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE222_MU_CNT : integer;
  attribute LC_PROBE222_MU_CNT of U0 : label is 1;
  attribute LC_PROBE222_PID : string;
  attribute LC_PROBE222_PID of U0 : label is "16'b0000000011011110";
  attribute LC_PROBE222_TYPE : integer;
  attribute LC_PROBE222_TYPE of U0 : label is 1;
  attribute LC_PROBE222_WIDTH : integer;
  attribute LC_PROBE222_WIDTH of U0 : label is 1;
  attribute LC_PROBE223_IS_DATA : string;
  attribute LC_PROBE223_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE223_IS_TRIG : string;
  attribute LC_PROBE223_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE223_MU_CNT : integer;
  attribute LC_PROBE223_MU_CNT of U0 : label is 1;
  attribute LC_PROBE223_PID : string;
  attribute LC_PROBE223_PID of U0 : label is "16'b0000000011011111";
  attribute LC_PROBE223_TYPE : integer;
  attribute LC_PROBE223_TYPE of U0 : label is 1;
  attribute LC_PROBE223_WIDTH : integer;
  attribute LC_PROBE223_WIDTH of U0 : label is 1;
  attribute LC_PROBE224_IS_DATA : string;
  attribute LC_PROBE224_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE224_IS_TRIG : string;
  attribute LC_PROBE224_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE224_MU_CNT : integer;
  attribute LC_PROBE224_MU_CNT of U0 : label is 1;
  attribute LC_PROBE224_PID : string;
  attribute LC_PROBE224_PID of U0 : label is "16'b0000000011100000";
  attribute LC_PROBE224_TYPE : integer;
  attribute LC_PROBE224_TYPE of U0 : label is 1;
  attribute LC_PROBE224_WIDTH : integer;
  attribute LC_PROBE224_WIDTH of U0 : label is 1;
  attribute LC_PROBE225_IS_DATA : string;
  attribute LC_PROBE225_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE225_IS_TRIG : string;
  attribute LC_PROBE225_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE225_MU_CNT : integer;
  attribute LC_PROBE225_MU_CNT of U0 : label is 1;
  attribute LC_PROBE225_PID : string;
  attribute LC_PROBE225_PID of U0 : label is "16'b0000000011100001";
  attribute LC_PROBE225_TYPE : integer;
  attribute LC_PROBE225_TYPE of U0 : label is 1;
  attribute LC_PROBE225_WIDTH : integer;
  attribute LC_PROBE225_WIDTH of U0 : label is 1;
  attribute LC_PROBE226_IS_DATA : string;
  attribute LC_PROBE226_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE226_IS_TRIG : string;
  attribute LC_PROBE226_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE226_MU_CNT : integer;
  attribute LC_PROBE226_MU_CNT of U0 : label is 1;
  attribute LC_PROBE226_PID : string;
  attribute LC_PROBE226_PID of U0 : label is "16'b0000000011100010";
  attribute LC_PROBE226_TYPE : integer;
  attribute LC_PROBE226_TYPE of U0 : label is 1;
  attribute LC_PROBE226_WIDTH : integer;
  attribute LC_PROBE226_WIDTH of U0 : label is 1;
  attribute LC_PROBE227_IS_DATA : string;
  attribute LC_PROBE227_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE227_IS_TRIG : string;
  attribute LC_PROBE227_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE227_MU_CNT : integer;
  attribute LC_PROBE227_MU_CNT of U0 : label is 1;
  attribute LC_PROBE227_PID : string;
  attribute LC_PROBE227_PID of U0 : label is "16'b0000000011100011";
  attribute LC_PROBE227_TYPE : integer;
  attribute LC_PROBE227_TYPE of U0 : label is 1;
  attribute LC_PROBE227_WIDTH : integer;
  attribute LC_PROBE227_WIDTH of U0 : label is 1;
  attribute LC_PROBE228_IS_DATA : string;
  attribute LC_PROBE228_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE228_IS_TRIG : string;
  attribute LC_PROBE228_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE228_MU_CNT : integer;
  attribute LC_PROBE228_MU_CNT of U0 : label is 1;
  attribute LC_PROBE228_PID : string;
  attribute LC_PROBE228_PID of U0 : label is "16'b0000000011100100";
  attribute LC_PROBE228_TYPE : integer;
  attribute LC_PROBE228_TYPE of U0 : label is 1;
  attribute LC_PROBE228_WIDTH : integer;
  attribute LC_PROBE228_WIDTH of U0 : label is 1;
  attribute LC_PROBE229_IS_DATA : string;
  attribute LC_PROBE229_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE229_IS_TRIG : string;
  attribute LC_PROBE229_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE229_MU_CNT : integer;
  attribute LC_PROBE229_MU_CNT of U0 : label is 1;
  attribute LC_PROBE229_PID : string;
  attribute LC_PROBE229_PID of U0 : label is "16'b0000000011100101";
  attribute LC_PROBE229_TYPE : integer;
  attribute LC_PROBE229_TYPE of U0 : label is 1;
  attribute LC_PROBE229_WIDTH : integer;
  attribute LC_PROBE229_WIDTH of U0 : label is 1;
  attribute LC_PROBE22_IS_DATA : string;
  attribute LC_PROBE22_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE22_IS_TRIG : string;
  attribute LC_PROBE22_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE22_MU_CNT : integer;
  attribute LC_PROBE22_MU_CNT of U0 : label is 1;
  attribute LC_PROBE22_PID : string;
  attribute LC_PROBE22_PID of U0 : label is "16'b0000000000010110";
  attribute LC_PROBE22_TYPE : integer;
  attribute LC_PROBE22_TYPE of U0 : label is 1;
  attribute LC_PROBE22_WIDTH : integer;
  attribute LC_PROBE22_WIDTH of U0 : label is 1;
  attribute LC_PROBE230_IS_DATA : string;
  attribute LC_PROBE230_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE230_IS_TRIG : string;
  attribute LC_PROBE230_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE230_MU_CNT : integer;
  attribute LC_PROBE230_MU_CNT of U0 : label is 1;
  attribute LC_PROBE230_PID : string;
  attribute LC_PROBE230_PID of U0 : label is "16'b0000000011100110";
  attribute LC_PROBE230_TYPE : integer;
  attribute LC_PROBE230_TYPE of U0 : label is 1;
  attribute LC_PROBE230_WIDTH : integer;
  attribute LC_PROBE230_WIDTH of U0 : label is 1;
  attribute LC_PROBE231_IS_DATA : string;
  attribute LC_PROBE231_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE231_IS_TRIG : string;
  attribute LC_PROBE231_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE231_MU_CNT : integer;
  attribute LC_PROBE231_MU_CNT of U0 : label is 1;
  attribute LC_PROBE231_PID : string;
  attribute LC_PROBE231_PID of U0 : label is "16'b0000000011100111";
  attribute LC_PROBE231_TYPE : integer;
  attribute LC_PROBE231_TYPE of U0 : label is 1;
  attribute LC_PROBE231_WIDTH : integer;
  attribute LC_PROBE231_WIDTH of U0 : label is 1;
  attribute LC_PROBE232_IS_DATA : string;
  attribute LC_PROBE232_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE232_IS_TRIG : string;
  attribute LC_PROBE232_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE232_MU_CNT : integer;
  attribute LC_PROBE232_MU_CNT of U0 : label is 1;
  attribute LC_PROBE232_PID : string;
  attribute LC_PROBE232_PID of U0 : label is "16'b0000000011101000";
  attribute LC_PROBE232_TYPE : integer;
  attribute LC_PROBE232_TYPE of U0 : label is 1;
  attribute LC_PROBE232_WIDTH : integer;
  attribute LC_PROBE232_WIDTH of U0 : label is 1;
  attribute LC_PROBE233_IS_DATA : string;
  attribute LC_PROBE233_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE233_IS_TRIG : string;
  attribute LC_PROBE233_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE233_MU_CNT : integer;
  attribute LC_PROBE233_MU_CNT of U0 : label is 1;
  attribute LC_PROBE233_PID : string;
  attribute LC_PROBE233_PID of U0 : label is "16'b0000000011101001";
  attribute LC_PROBE233_TYPE : integer;
  attribute LC_PROBE233_TYPE of U0 : label is 1;
  attribute LC_PROBE233_WIDTH : integer;
  attribute LC_PROBE233_WIDTH of U0 : label is 1;
  attribute LC_PROBE234_IS_DATA : string;
  attribute LC_PROBE234_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE234_IS_TRIG : string;
  attribute LC_PROBE234_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE234_MU_CNT : integer;
  attribute LC_PROBE234_MU_CNT of U0 : label is 1;
  attribute LC_PROBE234_PID : string;
  attribute LC_PROBE234_PID of U0 : label is "16'b0000000011101010";
  attribute LC_PROBE234_TYPE : integer;
  attribute LC_PROBE234_TYPE of U0 : label is 1;
  attribute LC_PROBE234_WIDTH : integer;
  attribute LC_PROBE234_WIDTH of U0 : label is 1;
  attribute LC_PROBE235_IS_DATA : string;
  attribute LC_PROBE235_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE235_IS_TRIG : string;
  attribute LC_PROBE235_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE235_MU_CNT : integer;
  attribute LC_PROBE235_MU_CNT of U0 : label is 1;
  attribute LC_PROBE235_PID : string;
  attribute LC_PROBE235_PID of U0 : label is "16'b0000000011101011";
  attribute LC_PROBE235_TYPE : integer;
  attribute LC_PROBE235_TYPE of U0 : label is 1;
  attribute LC_PROBE235_WIDTH : integer;
  attribute LC_PROBE235_WIDTH of U0 : label is 1;
  attribute LC_PROBE236_IS_DATA : string;
  attribute LC_PROBE236_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE236_IS_TRIG : string;
  attribute LC_PROBE236_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE236_MU_CNT : integer;
  attribute LC_PROBE236_MU_CNT of U0 : label is 1;
  attribute LC_PROBE236_PID : string;
  attribute LC_PROBE236_PID of U0 : label is "16'b0000000011101100";
  attribute LC_PROBE236_TYPE : integer;
  attribute LC_PROBE236_TYPE of U0 : label is 1;
  attribute LC_PROBE236_WIDTH : integer;
  attribute LC_PROBE236_WIDTH of U0 : label is 1;
  attribute LC_PROBE237_IS_DATA : string;
  attribute LC_PROBE237_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE237_IS_TRIG : string;
  attribute LC_PROBE237_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE237_MU_CNT : integer;
  attribute LC_PROBE237_MU_CNT of U0 : label is 1;
  attribute LC_PROBE237_PID : string;
  attribute LC_PROBE237_PID of U0 : label is "16'b0000000011101101";
  attribute LC_PROBE237_TYPE : integer;
  attribute LC_PROBE237_TYPE of U0 : label is 1;
  attribute LC_PROBE237_WIDTH : integer;
  attribute LC_PROBE237_WIDTH of U0 : label is 1;
  attribute LC_PROBE238_IS_DATA : string;
  attribute LC_PROBE238_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE238_IS_TRIG : string;
  attribute LC_PROBE238_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE238_MU_CNT : integer;
  attribute LC_PROBE238_MU_CNT of U0 : label is 1;
  attribute LC_PROBE238_PID : string;
  attribute LC_PROBE238_PID of U0 : label is "16'b0000000011101110";
  attribute LC_PROBE238_TYPE : integer;
  attribute LC_PROBE238_TYPE of U0 : label is 1;
  attribute LC_PROBE238_WIDTH : integer;
  attribute LC_PROBE238_WIDTH of U0 : label is 1;
  attribute LC_PROBE239_IS_DATA : string;
  attribute LC_PROBE239_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE239_IS_TRIG : string;
  attribute LC_PROBE239_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE239_MU_CNT : integer;
  attribute LC_PROBE239_MU_CNT of U0 : label is 1;
  attribute LC_PROBE239_PID : string;
  attribute LC_PROBE239_PID of U0 : label is "16'b0000000011101111";
  attribute LC_PROBE239_TYPE : integer;
  attribute LC_PROBE239_TYPE of U0 : label is 1;
  attribute LC_PROBE239_WIDTH : integer;
  attribute LC_PROBE239_WIDTH of U0 : label is 1;
  attribute LC_PROBE23_IS_DATA : string;
  attribute LC_PROBE23_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE23_IS_TRIG : string;
  attribute LC_PROBE23_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE23_MU_CNT : integer;
  attribute LC_PROBE23_MU_CNT of U0 : label is 1;
  attribute LC_PROBE23_PID : string;
  attribute LC_PROBE23_PID of U0 : label is "16'b0000000000010111";
  attribute LC_PROBE23_TYPE : integer;
  attribute LC_PROBE23_TYPE of U0 : label is 1;
  attribute LC_PROBE23_WIDTH : integer;
  attribute LC_PROBE23_WIDTH of U0 : label is 1;
  attribute LC_PROBE240_IS_DATA : string;
  attribute LC_PROBE240_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE240_IS_TRIG : string;
  attribute LC_PROBE240_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE240_MU_CNT : integer;
  attribute LC_PROBE240_MU_CNT of U0 : label is 1;
  attribute LC_PROBE240_PID : string;
  attribute LC_PROBE240_PID of U0 : label is "16'b0000000011110000";
  attribute LC_PROBE240_TYPE : integer;
  attribute LC_PROBE240_TYPE of U0 : label is 1;
  attribute LC_PROBE240_WIDTH : integer;
  attribute LC_PROBE240_WIDTH of U0 : label is 1;
  attribute LC_PROBE241_IS_DATA : string;
  attribute LC_PROBE241_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE241_IS_TRIG : string;
  attribute LC_PROBE241_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE241_MU_CNT : integer;
  attribute LC_PROBE241_MU_CNT of U0 : label is 1;
  attribute LC_PROBE241_PID : string;
  attribute LC_PROBE241_PID of U0 : label is "16'b0000000011110001";
  attribute LC_PROBE241_TYPE : integer;
  attribute LC_PROBE241_TYPE of U0 : label is 1;
  attribute LC_PROBE241_WIDTH : integer;
  attribute LC_PROBE241_WIDTH of U0 : label is 1;
  attribute LC_PROBE242_IS_DATA : string;
  attribute LC_PROBE242_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE242_IS_TRIG : string;
  attribute LC_PROBE242_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE242_MU_CNT : integer;
  attribute LC_PROBE242_MU_CNT of U0 : label is 1;
  attribute LC_PROBE242_PID : string;
  attribute LC_PROBE242_PID of U0 : label is "16'b0000000011110010";
  attribute LC_PROBE242_TYPE : integer;
  attribute LC_PROBE242_TYPE of U0 : label is 1;
  attribute LC_PROBE242_WIDTH : integer;
  attribute LC_PROBE242_WIDTH of U0 : label is 1;
  attribute LC_PROBE243_IS_DATA : string;
  attribute LC_PROBE243_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE243_IS_TRIG : string;
  attribute LC_PROBE243_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE243_MU_CNT : integer;
  attribute LC_PROBE243_MU_CNT of U0 : label is 1;
  attribute LC_PROBE243_PID : string;
  attribute LC_PROBE243_PID of U0 : label is "16'b0000000011110011";
  attribute LC_PROBE243_TYPE : integer;
  attribute LC_PROBE243_TYPE of U0 : label is 1;
  attribute LC_PROBE243_WIDTH : integer;
  attribute LC_PROBE243_WIDTH of U0 : label is 1;
  attribute LC_PROBE244_IS_DATA : string;
  attribute LC_PROBE244_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE244_IS_TRIG : string;
  attribute LC_PROBE244_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE244_MU_CNT : integer;
  attribute LC_PROBE244_MU_CNT of U0 : label is 1;
  attribute LC_PROBE244_PID : string;
  attribute LC_PROBE244_PID of U0 : label is "16'b0000000011110100";
  attribute LC_PROBE244_TYPE : integer;
  attribute LC_PROBE244_TYPE of U0 : label is 1;
  attribute LC_PROBE244_WIDTH : integer;
  attribute LC_PROBE244_WIDTH of U0 : label is 1;
  attribute LC_PROBE245_IS_DATA : string;
  attribute LC_PROBE245_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE245_IS_TRIG : string;
  attribute LC_PROBE245_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE245_MU_CNT : integer;
  attribute LC_PROBE245_MU_CNT of U0 : label is 1;
  attribute LC_PROBE245_PID : string;
  attribute LC_PROBE245_PID of U0 : label is "16'b0000000011110101";
  attribute LC_PROBE245_TYPE : integer;
  attribute LC_PROBE245_TYPE of U0 : label is 1;
  attribute LC_PROBE245_WIDTH : integer;
  attribute LC_PROBE245_WIDTH of U0 : label is 1;
  attribute LC_PROBE246_IS_DATA : string;
  attribute LC_PROBE246_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE246_IS_TRIG : string;
  attribute LC_PROBE246_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE246_MU_CNT : integer;
  attribute LC_PROBE246_MU_CNT of U0 : label is 1;
  attribute LC_PROBE246_PID : string;
  attribute LC_PROBE246_PID of U0 : label is "16'b0000000011110110";
  attribute LC_PROBE246_TYPE : integer;
  attribute LC_PROBE246_TYPE of U0 : label is 1;
  attribute LC_PROBE246_WIDTH : integer;
  attribute LC_PROBE246_WIDTH of U0 : label is 1;
  attribute LC_PROBE247_IS_DATA : string;
  attribute LC_PROBE247_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE247_IS_TRIG : string;
  attribute LC_PROBE247_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE247_MU_CNT : integer;
  attribute LC_PROBE247_MU_CNT of U0 : label is 1;
  attribute LC_PROBE247_PID : string;
  attribute LC_PROBE247_PID of U0 : label is "16'b0000000011110111";
  attribute LC_PROBE247_TYPE : integer;
  attribute LC_PROBE247_TYPE of U0 : label is 1;
  attribute LC_PROBE247_WIDTH : integer;
  attribute LC_PROBE247_WIDTH of U0 : label is 1;
  attribute LC_PROBE248_IS_DATA : string;
  attribute LC_PROBE248_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE248_IS_TRIG : string;
  attribute LC_PROBE248_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE248_MU_CNT : integer;
  attribute LC_PROBE248_MU_CNT of U0 : label is 1;
  attribute LC_PROBE248_PID : string;
  attribute LC_PROBE248_PID of U0 : label is "16'b0000000011111000";
  attribute LC_PROBE248_TYPE : integer;
  attribute LC_PROBE248_TYPE of U0 : label is 1;
  attribute LC_PROBE248_WIDTH : integer;
  attribute LC_PROBE248_WIDTH of U0 : label is 1;
  attribute LC_PROBE249_IS_DATA : string;
  attribute LC_PROBE249_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE249_IS_TRIG : string;
  attribute LC_PROBE249_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE249_MU_CNT : integer;
  attribute LC_PROBE249_MU_CNT of U0 : label is 1;
  attribute LC_PROBE249_PID : string;
  attribute LC_PROBE249_PID of U0 : label is "16'b0000000011111001";
  attribute LC_PROBE249_TYPE : integer;
  attribute LC_PROBE249_TYPE of U0 : label is 1;
  attribute LC_PROBE249_WIDTH : integer;
  attribute LC_PROBE249_WIDTH of U0 : label is 1;
  attribute LC_PROBE24_IS_DATA : string;
  attribute LC_PROBE24_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE24_IS_TRIG : string;
  attribute LC_PROBE24_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE24_MU_CNT : integer;
  attribute LC_PROBE24_MU_CNT of U0 : label is 1;
  attribute LC_PROBE24_PID : string;
  attribute LC_PROBE24_PID of U0 : label is "16'b0000000000011000";
  attribute LC_PROBE24_TYPE : integer;
  attribute LC_PROBE24_TYPE of U0 : label is 1;
  attribute LC_PROBE24_WIDTH : integer;
  attribute LC_PROBE24_WIDTH of U0 : label is 1;
  attribute LC_PROBE250_IS_DATA : string;
  attribute LC_PROBE250_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE250_IS_TRIG : string;
  attribute LC_PROBE250_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE250_MU_CNT : integer;
  attribute LC_PROBE250_MU_CNT of U0 : label is 1;
  attribute LC_PROBE250_PID : string;
  attribute LC_PROBE250_PID of U0 : label is "16'b0000000011111010";
  attribute LC_PROBE250_TYPE : integer;
  attribute LC_PROBE250_TYPE of U0 : label is 1;
  attribute LC_PROBE250_WIDTH : integer;
  attribute LC_PROBE250_WIDTH of U0 : label is 1;
  attribute LC_PROBE251_IS_DATA : string;
  attribute LC_PROBE251_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE251_IS_TRIG : string;
  attribute LC_PROBE251_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE251_MU_CNT : integer;
  attribute LC_PROBE251_MU_CNT of U0 : label is 1;
  attribute LC_PROBE251_PID : string;
  attribute LC_PROBE251_PID of U0 : label is "16'b0000000011111011";
  attribute LC_PROBE251_TYPE : integer;
  attribute LC_PROBE251_TYPE of U0 : label is 1;
  attribute LC_PROBE251_WIDTH : integer;
  attribute LC_PROBE251_WIDTH of U0 : label is 1;
  attribute LC_PROBE252_IS_DATA : string;
  attribute LC_PROBE252_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE252_IS_TRIG : string;
  attribute LC_PROBE252_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE252_MU_CNT : integer;
  attribute LC_PROBE252_MU_CNT of U0 : label is 1;
  attribute LC_PROBE252_PID : string;
  attribute LC_PROBE252_PID of U0 : label is "16'b0000000011111100";
  attribute LC_PROBE252_TYPE : integer;
  attribute LC_PROBE252_TYPE of U0 : label is 1;
  attribute LC_PROBE252_WIDTH : integer;
  attribute LC_PROBE252_WIDTH of U0 : label is 1;
  attribute LC_PROBE253_IS_DATA : string;
  attribute LC_PROBE253_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE253_IS_TRIG : string;
  attribute LC_PROBE253_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE253_MU_CNT : integer;
  attribute LC_PROBE253_MU_CNT of U0 : label is 1;
  attribute LC_PROBE253_PID : string;
  attribute LC_PROBE253_PID of U0 : label is "16'b0000000011111101";
  attribute LC_PROBE253_TYPE : integer;
  attribute LC_PROBE253_TYPE of U0 : label is 1;
  attribute LC_PROBE253_WIDTH : integer;
  attribute LC_PROBE253_WIDTH of U0 : label is 1;
  attribute LC_PROBE254_IS_DATA : string;
  attribute LC_PROBE254_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE254_IS_TRIG : string;
  attribute LC_PROBE254_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE254_MU_CNT : integer;
  attribute LC_PROBE254_MU_CNT of U0 : label is 1;
  attribute LC_PROBE254_PID : string;
  attribute LC_PROBE254_PID of U0 : label is "16'b0000000011111110";
  attribute LC_PROBE254_TYPE : integer;
  attribute LC_PROBE254_TYPE of U0 : label is 1;
  attribute LC_PROBE254_WIDTH : integer;
  attribute LC_PROBE254_WIDTH of U0 : label is 1;
  attribute LC_PROBE255_IS_DATA : string;
  attribute LC_PROBE255_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE255_IS_TRIG : string;
  attribute LC_PROBE255_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE255_MU_CNT : integer;
  attribute LC_PROBE255_MU_CNT of U0 : label is 1;
  attribute LC_PROBE255_PID : string;
  attribute LC_PROBE255_PID of U0 : label is "16'b0000000011111111";
  attribute LC_PROBE255_TYPE : integer;
  attribute LC_PROBE255_TYPE of U0 : label is 1;
  attribute LC_PROBE255_WIDTH : integer;
  attribute LC_PROBE255_WIDTH of U0 : label is 1;
  attribute LC_PROBE256_IS_DATA : string;
  attribute LC_PROBE256_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE256_IS_TRIG : string;
  attribute LC_PROBE256_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE256_MU_CNT : integer;
  attribute LC_PROBE256_MU_CNT of U0 : label is 1;
  attribute LC_PROBE256_PID : string;
  attribute LC_PROBE256_PID of U0 : label is "16'b0000000100000000";
  attribute LC_PROBE256_TYPE : integer;
  attribute LC_PROBE256_TYPE of U0 : label is 1;
  attribute LC_PROBE256_WIDTH : integer;
  attribute LC_PROBE256_WIDTH of U0 : label is 1;
  attribute LC_PROBE257_IS_DATA : string;
  attribute LC_PROBE257_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE257_IS_TRIG : string;
  attribute LC_PROBE257_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE257_MU_CNT : integer;
  attribute LC_PROBE257_MU_CNT of U0 : label is 1;
  attribute LC_PROBE257_PID : string;
  attribute LC_PROBE257_PID of U0 : label is "16'b0000000100000001";
  attribute LC_PROBE257_TYPE : integer;
  attribute LC_PROBE257_TYPE of U0 : label is 1;
  attribute LC_PROBE257_WIDTH : integer;
  attribute LC_PROBE257_WIDTH of U0 : label is 1;
  attribute LC_PROBE258_IS_DATA : string;
  attribute LC_PROBE258_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE258_IS_TRIG : string;
  attribute LC_PROBE258_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE258_MU_CNT : integer;
  attribute LC_PROBE258_MU_CNT of U0 : label is 1;
  attribute LC_PROBE258_PID : string;
  attribute LC_PROBE258_PID of U0 : label is "16'b0000000100000010";
  attribute LC_PROBE258_TYPE : integer;
  attribute LC_PROBE258_TYPE of U0 : label is 1;
  attribute LC_PROBE258_WIDTH : integer;
  attribute LC_PROBE258_WIDTH of U0 : label is 1;
  attribute LC_PROBE259_IS_DATA : string;
  attribute LC_PROBE259_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE259_IS_TRIG : string;
  attribute LC_PROBE259_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE259_MU_CNT : integer;
  attribute LC_PROBE259_MU_CNT of U0 : label is 1;
  attribute LC_PROBE259_PID : string;
  attribute LC_PROBE259_PID of U0 : label is "16'b0000000100000011";
  attribute LC_PROBE259_TYPE : integer;
  attribute LC_PROBE259_TYPE of U0 : label is 1;
  attribute LC_PROBE259_WIDTH : integer;
  attribute LC_PROBE259_WIDTH of U0 : label is 1;
  attribute LC_PROBE25_IS_DATA : string;
  attribute LC_PROBE25_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE25_IS_TRIG : string;
  attribute LC_PROBE25_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE25_MU_CNT : integer;
  attribute LC_PROBE25_MU_CNT of U0 : label is 1;
  attribute LC_PROBE25_PID : string;
  attribute LC_PROBE25_PID of U0 : label is "16'b0000000000011001";
  attribute LC_PROBE25_TYPE : integer;
  attribute LC_PROBE25_TYPE of U0 : label is 1;
  attribute LC_PROBE25_WIDTH : integer;
  attribute LC_PROBE25_WIDTH of U0 : label is 1;
  attribute LC_PROBE260_IS_DATA : string;
  attribute LC_PROBE260_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE260_IS_TRIG : string;
  attribute LC_PROBE260_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE260_MU_CNT : integer;
  attribute LC_PROBE260_MU_CNT of U0 : label is 1;
  attribute LC_PROBE260_PID : string;
  attribute LC_PROBE260_PID of U0 : label is "16'b0000000100000100";
  attribute LC_PROBE260_TYPE : integer;
  attribute LC_PROBE260_TYPE of U0 : label is 1;
  attribute LC_PROBE260_WIDTH : integer;
  attribute LC_PROBE260_WIDTH of U0 : label is 1;
  attribute LC_PROBE261_IS_DATA : string;
  attribute LC_PROBE261_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE261_IS_TRIG : string;
  attribute LC_PROBE261_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE261_MU_CNT : integer;
  attribute LC_PROBE261_MU_CNT of U0 : label is 1;
  attribute LC_PROBE261_PID : string;
  attribute LC_PROBE261_PID of U0 : label is "16'b0000000100000101";
  attribute LC_PROBE261_TYPE : integer;
  attribute LC_PROBE261_TYPE of U0 : label is 1;
  attribute LC_PROBE261_WIDTH : integer;
  attribute LC_PROBE261_WIDTH of U0 : label is 1;
  attribute LC_PROBE262_IS_DATA : string;
  attribute LC_PROBE262_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE262_IS_TRIG : string;
  attribute LC_PROBE262_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE262_MU_CNT : integer;
  attribute LC_PROBE262_MU_CNT of U0 : label is 1;
  attribute LC_PROBE262_PID : string;
  attribute LC_PROBE262_PID of U0 : label is "16'b0000000100000110";
  attribute LC_PROBE262_TYPE : integer;
  attribute LC_PROBE262_TYPE of U0 : label is 1;
  attribute LC_PROBE262_WIDTH : integer;
  attribute LC_PROBE262_WIDTH of U0 : label is 1;
  attribute LC_PROBE263_IS_DATA : string;
  attribute LC_PROBE263_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE263_IS_TRIG : string;
  attribute LC_PROBE263_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE263_MU_CNT : integer;
  attribute LC_PROBE263_MU_CNT of U0 : label is 1;
  attribute LC_PROBE263_PID : string;
  attribute LC_PROBE263_PID of U0 : label is "16'b0000000100000111";
  attribute LC_PROBE263_TYPE : integer;
  attribute LC_PROBE263_TYPE of U0 : label is 1;
  attribute LC_PROBE263_WIDTH : integer;
  attribute LC_PROBE263_WIDTH of U0 : label is 1;
  attribute LC_PROBE264_IS_DATA : string;
  attribute LC_PROBE264_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE264_IS_TRIG : string;
  attribute LC_PROBE264_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE264_MU_CNT : integer;
  attribute LC_PROBE264_MU_CNT of U0 : label is 1;
  attribute LC_PROBE264_PID : string;
  attribute LC_PROBE264_PID of U0 : label is "16'b0000000100001000";
  attribute LC_PROBE264_TYPE : integer;
  attribute LC_PROBE264_TYPE of U0 : label is 1;
  attribute LC_PROBE264_WIDTH : integer;
  attribute LC_PROBE264_WIDTH of U0 : label is 1;
  attribute LC_PROBE265_IS_DATA : string;
  attribute LC_PROBE265_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE265_IS_TRIG : string;
  attribute LC_PROBE265_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE265_MU_CNT : integer;
  attribute LC_PROBE265_MU_CNT of U0 : label is 1;
  attribute LC_PROBE265_PID : string;
  attribute LC_PROBE265_PID of U0 : label is "16'b0000000100001001";
  attribute LC_PROBE265_TYPE : integer;
  attribute LC_PROBE265_TYPE of U0 : label is 1;
  attribute LC_PROBE265_WIDTH : integer;
  attribute LC_PROBE265_WIDTH of U0 : label is 1;
  attribute LC_PROBE266_IS_DATA : string;
  attribute LC_PROBE266_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE266_IS_TRIG : string;
  attribute LC_PROBE266_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE266_MU_CNT : integer;
  attribute LC_PROBE266_MU_CNT of U0 : label is 1;
  attribute LC_PROBE266_PID : string;
  attribute LC_PROBE266_PID of U0 : label is "16'b0000000100001010";
  attribute LC_PROBE266_TYPE : integer;
  attribute LC_PROBE266_TYPE of U0 : label is 1;
  attribute LC_PROBE266_WIDTH : integer;
  attribute LC_PROBE266_WIDTH of U0 : label is 1;
  attribute LC_PROBE267_IS_DATA : string;
  attribute LC_PROBE267_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE267_IS_TRIG : string;
  attribute LC_PROBE267_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE267_MU_CNT : integer;
  attribute LC_PROBE267_MU_CNT of U0 : label is 1;
  attribute LC_PROBE267_PID : string;
  attribute LC_PROBE267_PID of U0 : label is "16'b0000000100001011";
  attribute LC_PROBE267_TYPE : integer;
  attribute LC_PROBE267_TYPE of U0 : label is 1;
  attribute LC_PROBE267_WIDTH : integer;
  attribute LC_PROBE267_WIDTH of U0 : label is 1;
  attribute LC_PROBE268_IS_DATA : string;
  attribute LC_PROBE268_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE268_IS_TRIG : string;
  attribute LC_PROBE268_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE268_MU_CNT : integer;
  attribute LC_PROBE268_MU_CNT of U0 : label is 1;
  attribute LC_PROBE268_PID : string;
  attribute LC_PROBE268_PID of U0 : label is "16'b0000000100001100";
  attribute LC_PROBE268_TYPE : integer;
  attribute LC_PROBE268_TYPE of U0 : label is 1;
  attribute LC_PROBE268_WIDTH : integer;
  attribute LC_PROBE268_WIDTH of U0 : label is 1;
  attribute LC_PROBE269_IS_DATA : string;
  attribute LC_PROBE269_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE269_IS_TRIG : string;
  attribute LC_PROBE269_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE269_MU_CNT : integer;
  attribute LC_PROBE269_MU_CNT of U0 : label is 1;
  attribute LC_PROBE269_PID : string;
  attribute LC_PROBE269_PID of U0 : label is "16'b0000000100001101";
  attribute LC_PROBE269_TYPE : integer;
  attribute LC_PROBE269_TYPE of U0 : label is 1;
  attribute LC_PROBE269_WIDTH : integer;
  attribute LC_PROBE269_WIDTH of U0 : label is 1;
  attribute LC_PROBE26_IS_DATA : string;
  attribute LC_PROBE26_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE26_IS_TRIG : string;
  attribute LC_PROBE26_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE26_MU_CNT : integer;
  attribute LC_PROBE26_MU_CNT of U0 : label is 1;
  attribute LC_PROBE26_PID : string;
  attribute LC_PROBE26_PID of U0 : label is "16'b0000000000011010";
  attribute LC_PROBE26_TYPE : integer;
  attribute LC_PROBE26_TYPE of U0 : label is 1;
  attribute LC_PROBE26_WIDTH : integer;
  attribute LC_PROBE26_WIDTH of U0 : label is 1;
  attribute LC_PROBE270_IS_DATA : string;
  attribute LC_PROBE270_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE270_IS_TRIG : string;
  attribute LC_PROBE270_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE270_MU_CNT : integer;
  attribute LC_PROBE270_MU_CNT of U0 : label is 1;
  attribute LC_PROBE270_PID : string;
  attribute LC_PROBE270_PID of U0 : label is "16'b0000000100001110";
  attribute LC_PROBE270_TYPE : integer;
  attribute LC_PROBE270_TYPE of U0 : label is 1;
  attribute LC_PROBE270_WIDTH : integer;
  attribute LC_PROBE270_WIDTH of U0 : label is 1;
  attribute LC_PROBE271_IS_DATA : string;
  attribute LC_PROBE271_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE271_IS_TRIG : string;
  attribute LC_PROBE271_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE271_MU_CNT : integer;
  attribute LC_PROBE271_MU_CNT of U0 : label is 1;
  attribute LC_PROBE271_PID : string;
  attribute LC_PROBE271_PID of U0 : label is "16'b0000000100001111";
  attribute LC_PROBE271_TYPE : integer;
  attribute LC_PROBE271_TYPE of U0 : label is 1;
  attribute LC_PROBE271_WIDTH : integer;
  attribute LC_PROBE271_WIDTH of U0 : label is 1;
  attribute LC_PROBE272_IS_DATA : string;
  attribute LC_PROBE272_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE272_IS_TRIG : string;
  attribute LC_PROBE272_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE272_MU_CNT : integer;
  attribute LC_PROBE272_MU_CNT of U0 : label is 1;
  attribute LC_PROBE272_PID : string;
  attribute LC_PROBE272_PID of U0 : label is "16'b0000000100010000";
  attribute LC_PROBE272_TYPE : integer;
  attribute LC_PROBE272_TYPE of U0 : label is 1;
  attribute LC_PROBE272_WIDTH : integer;
  attribute LC_PROBE272_WIDTH of U0 : label is 1;
  attribute LC_PROBE273_IS_DATA : string;
  attribute LC_PROBE273_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE273_IS_TRIG : string;
  attribute LC_PROBE273_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE273_MU_CNT : integer;
  attribute LC_PROBE273_MU_CNT of U0 : label is 1;
  attribute LC_PROBE273_PID : string;
  attribute LC_PROBE273_PID of U0 : label is "16'b0000000100010001";
  attribute LC_PROBE273_TYPE : integer;
  attribute LC_PROBE273_TYPE of U0 : label is 1;
  attribute LC_PROBE273_WIDTH : integer;
  attribute LC_PROBE273_WIDTH of U0 : label is 1;
  attribute LC_PROBE274_IS_DATA : string;
  attribute LC_PROBE274_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE274_IS_TRIG : string;
  attribute LC_PROBE274_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE274_MU_CNT : integer;
  attribute LC_PROBE274_MU_CNT of U0 : label is 1;
  attribute LC_PROBE274_PID : string;
  attribute LC_PROBE274_PID of U0 : label is "16'b0000000100010010";
  attribute LC_PROBE274_TYPE : integer;
  attribute LC_PROBE274_TYPE of U0 : label is 1;
  attribute LC_PROBE274_WIDTH : integer;
  attribute LC_PROBE274_WIDTH of U0 : label is 1;
  attribute LC_PROBE275_IS_DATA : string;
  attribute LC_PROBE275_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE275_IS_TRIG : string;
  attribute LC_PROBE275_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE275_MU_CNT : integer;
  attribute LC_PROBE275_MU_CNT of U0 : label is 1;
  attribute LC_PROBE275_PID : string;
  attribute LC_PROBE275_PID of U0 : label is "16'b0000000100010011";
  attribute LC_PROBE275_TYPE : integer;
  attribute LC_PROBE275_TYPE of U0 : label is 1;
  attribute LC_PROBE275_WIDTH : integer;
  attribute LC_PROBE275_WIDTH of U0 : label is 1;
  attribute LC_PROBE276_IS_DATA : string;
  attribute LC_PROBE276_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE276_IS_TRIG : string;
  attribute LC_PROBE276_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE276_MU_CNT : integer;
  attribute LC_PROBE276_MU_CNT of U0 : label is 1;
  attribute LC_PROBE276_PID : string;
  attribute LC_PROBE276_PID of U0 : label is "16'b0000000100010100";
  attribute LC_PROBE276_TYPE : integer;
  attribute LC_PROBE276_TYPE of U0 : label is 1;
  attribute LC_PROBE276_WIDTH : integer;
  attribute LC_PROBE276_WIDTH of U0 : label is 1;
  attribute LC_PROBE277_IS_DATA : string;
  attribute LC_PROBE277_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE277_IS_TRIG : string;
  attribute LC_PROBE277_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE277_MU_CNT : integer;
  attribute LC_PROBE277_MU_CNT of U0 : label is 1;
  attribute LC_PROBE277_PID : string;
  attribute LC_PROBE277_PID of U0 : label is "16'b0000000100010101";
  attribute LC_PROBE277_TYPE : integer;
  attribute LC_PROBE277_TYPE of U0 : label is 1;
  attribute LC_PROBE277_WIDTH : integer;
  attribute LC_PROBE277_WIDTH of U0 : label is 1;
  attribute LC_PROBE278_IS_DATA : string;
  attribute LC_PROBE278_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE278_IS_TRIG : string;
  attribute LC_PROBE278_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE278_MU_CNT : integer;
  attribute LC_PROBE278_MU_CNT of U0 : label is 1;
  attribute LC_PROBE278_PID : string;
  attribute LC_PROBE278_PID of U0 : label is "16'b0000000100010110";
  attribute LC_PROBE278_TYPE : integer;
  attribute LC_PROBE278_TYPE of U0 : label is 1;
  attribute LC_PROBE278_WIDTH : integer;
  attribute LC_PROBE278_WIDTH of U0 : label is 1;
  attribute LC_PROBE279_IS_DATA : string;
  attribute LC_PROBE279_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE279_IS_TRIG : string;
  attribute LC_PROBE279_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE279_MU_CNT : integer;
  attribute LC_PROBE279_MU_CNT of U0 : label is 1;
  attribute LC_PROBE279_PID : string;
  attribute LC_PROBE279_PID of U0 : label is "16'b0000000100010111";
  attribute LC_PROBE279_TYPE : integer;
  attribute LC_PROBE279_TYPE of U0 : label is 1;
  attribute LC_PROBE279_WIDTH : integer;
  attribute LC_PROBE279_WIDTH of U0 : label is 1;
  attribute LC_PROBE27_IS_DATA : string;
  attribute LC_PROBE27_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE27_IS_TRIG : string;
  attribute LC_PROBE27_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE27_MU_CNT : integer;
  attribute LC_PROBE27_MU_CNT of U0 : label is 1;
  attribute LC_PROBE27_PID : string;
  attribute LC_PROBE27_PID of U0 : label is "16'b0000000000011011";
  attribute LC_PROBE27_TYPE : integer;
  attribute LC_PROBE27_TYPE of U0 : label is 1;
  attribute LC_PROBE27_WIDTH : integer;
  attribute LC_PROBE27_WIDTH of U0 : label is 1;
  attribute LC_PROBE280_IS_DATA : string;
  attribute LC_PROBE280_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE280_IS_TRIG : string;
  attribute LC_PROBE280_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE280_MU_CNT : integer;
  attribute LC_PROBE280_MU_CNT of U0 : label is 1;
  attribute LC_PROBE280_PID : string;
  attribute LC_PROBE280_PID of U0 : label is "16'b0000000100011000";
  attribute LC_PROBE280_TYPE : integer;
  attribute LC_PROBE280_TYPE of U0 : label is 1;
  attribute LC_PROBE280_WIDTH : integer;
  attribute LC_PROBE280_WIDTH of U0 : label is 1;
  attribute LC_PROBE281_IS_DATA : string;
  attribute LC_PROBE281_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE281_IS_TRIG : string;
  attribute LC_PROBE281_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE281_MU_CNT : integer;
  attribute LC_PROBE281_MU_CNT of U0 : label is 1;
  attribute LC_PROBE281_PID : string;
  attribute LC_PROBE281_PID of U0 : label is "16'b0000000100011001";
  attribute LC_PROBE281_TYPE : integer;
  attribute LC_PROBE281_TYPE of U0 : label is 1;
  attribute LC_PROBE281_WIDTH : integer;
  attribute LC_PROBE281_WIDTH of U0 : label is 1;
  attribute LC_PROBE282_IS_DATA : string;
  attribute LC_PROBE282_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE282_IS_TRIG : string;
  attribute LC_PROBE282_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE282_MU_CNT : integer;
  attribute LC_PROBE282_MU_CNT of U0 : label is 1;
  attribute LC_PROBE282_PID : string;
  attribute LC_PROBE282_PID of U0 : label is "16'b0000000100011010";
  attribute LC_PROBE282_TYPE : integer;
  attribute LC_PROBE282_TYPE of U0 : label is 1;
  attribute LC_PROBE282_WIDTH : integer;
  attribute LC_PROBE282_WIDTH of U0 : label is 1;
  attribute LC_PROBE283_IS_DATA : string;
  attribute LC_PROBE283_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE283_IS_TRIG : string;
  attribute LC_PROBE283_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE283_MU_CNT : integer;
  attribute LC_PROBE283_MU_CNT of U0 : label is 1;
  attribute LC_PROBE283_PID : string;
  attribute LC_PROBE283_PID of U0 : label is "16'b0000000100011011";
  attribute LC_PROBE283_TYPE : integer;
  attribute LC_PROBE283_TYPE of U0 : label is 1;
  attribute LC_PROBE283_WIDTH : integer;
  attribute LC_PROBE283_WIDTH of U0 : label is 1;
  attribute LC_PROBE284_IS_DATA : string;
  attribute LC_PROBE284_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE284_IS_TRIG : string;
  attribute LC_PROBE284_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE284_MU_CNT : integer;
  attribute LC_PROBE284_MU_CNT of U0 : label is 1;
  attribute LC_PROBE284_PID : string;
  attribute LC_PROBE284_PID of U0 : label is "16'b0000000100011100";
  attribute LC_PROBE284_TYPE : integer;
  attribute LC_PROBE284_TYPE of U0 : label is 1;
  attribute LC_PROBE284_WIDTH : integer;
  attribute LC_PROBE284_WIDTH of U0 : label is 1;
  attribute LC_PROBE285_IS_DATA : string;
  attribute LC_PROBE285_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE285_IS_TRIG : string;
  attribute LC_PROBE285_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE285_MU_CNT : integer;
  attribute LC_PROBE285_MU_CNT of U0 : label is 1;
  attribute LC_PROBE285_PID : string;
  attribute LC_PROBE285_PID of U0 : label is "16'b0000000100011101";
  attribute LC_PROBE285_TYPE : integer;
  attribute LC_PROBE285_TYPE of U0 : label is 1;
  attribute LC_PROBE285_WIDTH : integer;
  attribute LC_PROBE285_WIDTH of U0 : label is 1;
  attribute LC_PROBE286_IS_DATA : string;
  attribute LC_PROBE286_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE286_IS_TRIG : string;
  attribute LC_PROBE286_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE286_MU_CNT : integer;
  attribute LC_PROBE286_MU_CNT of U0 : label is 1;
  attribute LC_PROBE286_PID : string;
  attribute LC_PROBE286_PID of U0 : label is "16'b0000000100011110";
  attribute LC_PROBE286_TYPE : integer;
  attribute LC_PROBE286_TYPE of U0 : label is 1;
  attribute LC_PROBE286_WIDTH : integer;
  attribute LC_PROBE286_WIDTH of U0 : label is 1;
  attribute LC_PROBE287_IS_DATA : string;
  attribute LC_PROBE287_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE287_IS_TRIG : string;
  attribute LC_PROBE287_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE287_MU_CNT : integer;
  attribute LC_PROBE287_MU_CNT of U0 : label is 1;
  attribute LC_PROBE287_PID : string;
  attribute LC_PROBE287_PID of U0 : label is "16'b0000000100011111";
  attribute LC_PROBE287_TYPE : integer;
  attribute LC_PROBE287_TYPE of U0 : label is 1;
  attribute LC_PROBE287_WIDTH : integer;
  attribute LC_PROBE287_WIDTH of U0 : label is 1;
  attribute LC_PROBE288_IS_DATA : string;
  attribute LC_PROBE288_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE288_IS_TRIG : string;
  attribute LC_PROBE288_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE288_MU_CNT : integer;
  attribute LC_PROBE288_MU_CNT of U0 : label is 1;
  attribute LC_PROBE288_PID : string;
  attribute LC_PROBE288_PID of U0 : label is "16'b0000000100100000";
  attribute LC_PROBE288_TYPE : integer;
  attribute LC_PROBE288_TYPE of U0 : label is 1;
  attribute LC_PROBE288_WIDTH : integer;
  attribute LC_PROBE288_WIDTH of U0 : label is 1;
  attribute LC_PROBE289_IS_DATA : string;
  attribute LC_PROBE289_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE289_IS_TRIG : string;
  attribute LC_PROBE289_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE289_MU_CNT : integer;
  attribute LC_PROBE289_MU_CNT of U0 : label is 1;
  attribute LC_PROBE289_PID : string;
  attribute LC_PROBE289_PID of U0 : label is "16'b0000000100100001";
  attribute LC_PROBE289_TYPE : integer;
  attribute LC_PROBE289_TYPE of U0 : label is 1;
  attribute LC_PROBE289_WIDTH : integer;
  attribute LC_PROBE289_WIDTH of U0 : label is 1;
  attribute LC_PROBE28_IS_DATA : string;
  attribute LC_PROBE28_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE28_IS_TRIG : string;
  attribute LC_PROBE28_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE28_MU_CNT : integer;
  attribute LC_PROBE28_MU_CNT of U0 : label is 1;
  attribute LC_PROBE28_PID : string;
  attribute LC_PROBE28_PID of U0 : label is "16'b0000000000011100";
  attribute LC_PROBE28_TYPE : integer;
  attribute LC_PROBE28_TYPE of U0 : label is 1;
  attribute LC_PROBE28_WIDTH : integer;
  attribute LC_PROBE28_WIDTH of U0 : label is 1;
  attribute LC_PROBE290_IS_DATA : string;
  attribute LC_PROBE290_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE290_IS_TRIG : string;
  attribute LC_PROBE290_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE290_MU_CNT : integer;
  attribute LC_PROBE290_MU_CNT of U0 : label is 1;
  attribute LC_PROBE290_PID : string;
  attribute LC_PROBE290_PID of U0 : label is "16'b0000000100100010";
  attribute LC_PROBE290_TYPE : integer;
  attribute LC_PROBE290_TYPE of U0 : label is 1;
  attribute LC_PROBE290_WIDTH : integer;
  attribute LC_PROBE290_WIDTH of U0 : label is 1;
  attribute LC_PROBE291_IS_DATA : string;
  attribute LC_PROBE291_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE291_IS_TRIG : string;
  attribute LC_PROBE291_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE291_MU_CNT : integer;
  attribute LC_PROBE291_MU_CNT of U0 : label is 1;
  attribute LC_PROBE291_PID : string;
  attribute LC_PROBE291_PID of U0 : label is "16'b0000000100100011";
  attribute LC_PROBE291_TYPE : integer;
  attribute LC_PROBE291_TYPE of U0 : label is 1;
  attribute LC_PROBE291_WIDTH : integer;
  attribute LC_PROBE291_WIDTH of U0 : label is 1;
  attribute LC_PROBE292_IS_DATA : string;
  attribute LC_PROBE292_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE292_IS_TRIG : string;
  attribute LC_PROBE292_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE292_MU_CNT : integer;
  attribute LC_PROBE292_MU_CNT of U0 : label is 1;
  attribute LC_PROBE292_PID : string;
  attribute LC_PROBE292_PID of U0 : label is "16'b0000000100100100";
  attribute LC_PROBE292_TYPE : integer;
  attribute LC_PROBE292_TYPE of U0 : label is 1;
  attribute LC_PROBE292_WIDTH : integer;
  attribute LC_PROBE292_WIDTH of U0 : label is 1;
  attribute LC_PROBE293_IS_DATA : string;
  attribute LC_PROBE293_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE293_IS_TRIG : string;
  attribute LC_PROBE293_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE293_MU_CNT : integer;
  attribute LC_PROBE293_MU_CNT of U0 : label is 1;
  attribute LC_PROBE293_PID : string;
  attribute LC_PROBE293_PID of U0 : label is "16'b0000000100100101";
  attribute LC_PROBE293_TYPE : integer;
  attribute LC_PROBE293_TYPE of U0 : label is 1;
  attribute LC_PROBE293_WIDTH : integer;
  attribute LC_PROBE293_WIDTH of U0 : label is 1;
  attribute LC_PROBE294_IS_DATA : string;
  attribute LC_PROBE294_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE294_IS_TRIG : string;
  attribute LC_PROBE294_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE294_MU_CNT : integer;
  attribute LC_PROBE294_MU_CNT of U0 : label is 1;
  attribute LC_PROBE294_PID : string;
  attribute LC_PROBE294_PID of U0 : label is "16'b0000000100100110";
  attribute LC_PROBE294_TYPE : integer;
  attribute LC_PROBE294_TYPE of U0 : label is 1;
  attribute LC_PROBE294_WIDTH : integer;
  attribute LC_PROBE294_WIDTH of U0 : label is 1;
  attribute LC_PROBE295_IS_DATA : string;
  attribute LC_PROBE295_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE295_IS_TRIG : string;
  attribute LC_PROBE295_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE295_MU_CNT : integer;
  attribute LC_PROBE295_MU_CNT of U0 : label is 1;
  attribute LC_PROBE295_PID : string;
  attribute LC_PROBE295_PID of U0 : label is "16'b0000000100100111";
  attribute LC_PROBE295_TYPE : integer;
  attribute LC_PROBE295_TYPE of U0 : label is 1;
  attribute LC_PROBE295_WIDTH : integer;
  attribute LC_PROBE295_WIDTH of U0 : label is 1;
  attribute LC_PROBE296_IS_DATA : string;
  attribute LC_PROBE296_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE296_IS_TRIG : string;
  attribute LC_PROBE296_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE296_MU_CNT : integer;
  attribute LC_PROBE296_MU_CNT of U0 : label is 1;
  attribute LC_PROBE296_PID : string;
  attribute LC_PROBE296_PID of U0 : label is "16'b0000000100101000";
  attribute LC_PROBE296_TYPE : integer;
  attribute LC_PROBE296_TYPE of U0 : label is 1;
  attribute LC_PROBE296_WIDTH : integer;
  attribute LC_PROBE296_WIDTH of U0 : label is 1;
  attribute LC_PROBE297_IS_DATA : string;
  attribute LC_PROBE297_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE297_IS_TRIG : string;
  attribute LC_PROBE297_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE297_MU_CNT : integer;
  attribute LC_PROBE297_MU_CNT of U0 : label is 1;
  attribute LC_PROBE297_PID : string;
  attribute LC_PROBE297_PID of U0 : label is "16'b0000000100101001";
  attribute LC_PROBE297_TYPE : integer;
  attribute LC_PROBE297_TYPE of U0 : label is 1;
  attribute LC_PROBE297_WIDTH : integer;
  attribute LC_PROBE297_WIDTH of U0 : label is 1;
  attribute LC_PROBE298_IS_DATA : string;
  attribute LC_PROBE298_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE298_IS_TRIG : string;
  attribute LC_PROBE298_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE298_MU_CNT : integer;
  attribute LC_PROBE298_MU_CNT of U0 : label is 1;
  attribute LC_PROBE298_PID : string;
  attribute LC_PROBE298_PID of U0 : label is "16'b0000000100101010";
  attribute LC_PROBE298_TYPE : integer;
  attribute LC_PROBE298_TYPE of U0 : label is 1;
  attribute LC_PROBE298_WIDTH : integer;
  attribute LC_PROBE298_WIDTH of U0 : label is 1;
  attribute LC_PROBE299_IS_DATA : string;
  attribute LC_PROBE299_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE299_IS_TRIG : string;
  attribute LC_PROBE299_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE299_MU_CNT : integer;
  attribute LC_PROBE299_MU_CNT of U0 : label is 1;
  attribute LC_PROBE299_PID : string;
  attribute LC_PROBE299_PID of U0 : label is "16'b0000000100101011";
  attribute LC_PROBE299_TYPE : integer;
  attribute LC_PROBE299_TYPE of U0 : label is 1;
  attribute LC_PROBE299_WIDTH : integer;
  attribute LC_PROBE299_WIDTH of U0 : label is 1;
  attribute LC_PROBE29_IS_DATA : string;
  attribute LC_PROBE29_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE29_IS_TRIG : string;
  attribute LC_PROBE29_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE29_MU_CNT : integer;
  attribute LC_PROBE29_MU_CNT of U0 : label is 1;
  attribute LC_PROBE29_PID : string;
  attribute LC_PROBE29_PID of U0 : label is "16'b0000000000011101";
  attribute LC_PROBE29_TYPE : integer;
  attribute LC_PROBE29_TYPE of U0 : label is 1;
  attribute LC_PROBE29_WIDTH : integer;
  attribute LC_PROBE29_WIDTH of U0 : label is 1;
  attribute LC_PROBE2_IS_DATA : string;
  attribute LC_PROBE2_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE2_IS_TRIG : string;
  attribute LC_PROBE2_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE2_MU_CNT : integer;
  attribute LC_PROBE2_MU_CNT of U0 : label is 1;
  attribute LC_PROBE2_PID : string;
  attribute LC_PROBE2_PID of U0 : label is "16'b0000000000000010";
  attribute LC_PROBE2_TYPE : integer;
  attribute LC_PROBE2_TYPE of U0 : label is 0;
  attribute LC_PROBE2_WIDTH : integer;
  attribute LC_PROBE2_WIDTH of U0 : label is 1;
  attribute LC_PROBE300_IS_DATA : string;
  attribute LC_PROBE300_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE300_IS_TRIG : string;
  attribute LC_PROBE300_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE300_MU_CNT : integer;
  attribute LC_PROBE300_MU_CNT of U0 : label is 1;
  attribute LC_PROBE300_PID : string;
  attribute LC_PROBE300_PID of U0 : label is "16'b0000000100101100";
  attribute LC_PROBE300_TYPE : integer;
  attribute LC_PROBE300_TYPE of U0 : label is 1;
  attribute LC_PROBE300_WIDTH : integer;
  attribute LC_PROBE300_WIDTH of U0 : label is 1;
  attribute LC_PROBE301_IS_DATA : string;
  attribute LC_PROBE301_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE301_IS_TRIG : string;
  attribute LC_PROBE301_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE301_MU_CNT : integer;
  attribute LC_PROBE301_MU_CNT of U0 : label is 1;
  attribute LC_PROBE301_PID : string;
  attribute LC_PROBE301_PID of U0 : label is "16'b0000000100101101";
  attribute LC_PROBE301_TYPE : integer;
  attribute LC_PROBE301_TYPE of U0 : label is 1;
  attribute LC_PROBE301_WIDTH : integer;
  attribute LC_PROBE301_WIDTH of U0 : label is 1;
  attribute LC_PROBE302_IS_DATA : string;
  attribute LC_PROBE302_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE302_IS_TRIG : string;
  attribute LC_PROBE302_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE302_MU_CNT : integer;
  attribute LC_PROBE302_MU_CNT of U0 : label is 1;
  attribute LC_PROBE302_PID : string;
  attribute LC_PROBE302_PID of U0 : label is "16'b0000000100101110";
  attribute LC_PROBE302_TYPE : integer;
  attribute LC_PROBE302_TYPE of U0 : label is 1;
  attribute LC_PROBE302_WIDTH : integer;
  attribute LC_PROBE302_WIDTH of U0 : label is 1;
  attribute LC_PROBE303_IS_DATA : string;
  attribute LC_PROBE303_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE303_IS_TRIG : string;
  attribute LC_PROBE303_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE303_MU_CNT : integer;
  attribute LC_PROBE303_MU_CNT of U0 : label is 1;
  attribute LC_PROBE303_PID : string;
  attribute LC_PROBE303_PID of U0 : label is "16'b0000000100101111";
  attribute LC_PROBE303_TYPE : integer;
  attribute LC_PROBE303_TYPE of U0 : label is 1;
  attribute LC_PROBE303_WIDTH : integer;
  attribute LC_PROBE303_WIDTH of U0 : label is 1;
  attribute LC_PROBE304_IS_DATA : string;
  attribute LC_PROBE304_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE304_IS_TRIG : string;
  attribute LC_PROBE304_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE304_MU_CNT : integer;
  attribute LC_PROBE304_MU_CNT of U0 : label is 1;
  attribute LC_PROBE304_PID : string;
  attribute LC_PROBE304_PID of U0 : label is "16'b0000000100110000";
  attribute LC_PROBE304_TYPE : integer;
  attribute LC_PROBE304_TYPE of U0 : label is 1;
  attribute LC_PROBE304_WIDTH : integer;
  attribute LC_PROBE304_WIDTH of U0 : label is 1;
  attribute LC_PROBE305_IS_DATA : string;
  attribute LC_PROBE305_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE305_IS_TRIG : string;
  attribute LC_PROBE305_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE305_MU_CNT : integer;
  attribute LC_PROBE305_MU_CNT of U0 : label is 1;
  attribute LC_PROBE305_PID : string;
  attribute LC_PROBE305_PID of U0 : label is "16'b0000000100110001";
  attribute LC_PROBE305_TYPE : integer;
  attribute LC_PROBE305_TYPE of U0 : label is 1;
  attribute LC_PROBE305_WIDTH : integer;
  attribute LC_PROBE305_WIDTH of U0 : label is 1;
  attribute LC_PROBE306_IS_DATA : string;
  attribute LC_PROBE306_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE306_IS_TRIG : string;
  attribute LC_PROBE306_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE306_MU_CNT : integer;
  attribute LC_PROBE306_MU_CNT of U0 : label is 1;
  attribute LC_PROBE306_PID : string;
  attribute LC_PROBE306_PID of U0 : label is "16'b0000000100110010";
  attribute LC_PROBE306_TYPE : integer;
  attribute LC_PROBE306_TYPE of U0 : label is 1;
  attribute LC_PROBE306_WIDTH : integer;
  attribute LC_PROBE306_WIDTH of U0 : label is 1;
  attribute LC_PROBE307_IS_DATA : string;
  attribute LC_PROBE307_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE307_IS_TRIG : string;
  attribute LC_PROBE307_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE307_MU_CNT : integer;
  attribute LC_PROBE307_MU_CNT of U0 : label is 1;
  attribute LC_PROBE307_PID : string;
  attribute LC_PROBE307_PID of U0 : label is "16'b0000000100110011";
  attribute LC_PROBE307_TYPE : integer;
  attribute LC_PROBE307_TYPE of U0 : label is 1;
  attribute LC_PROBE307_WIDTH : integer;
  attribute LC_PROBE307_WIDTH of U0 : label is 1;
  attribute LC_PROBE308_IS_DATA : string;
  attribute LC_PROBE308_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE308_IS_TRIG : string;
  attribute LC_PROBE308_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE308_MU_CNT : integer;
  attribute LC_PROBE308_MU_CNT of U0 : label is 1;
  attribute LC_PROBE308_PID : string;
  attribute LC_PROBE308_PID of U0 : label is "16'b0000000100110100";
  attribute LC_PROBE308_TYPE : integer;
  attribute LC_PROBE308_TYPE of U0 : label is 1;
  attribute LC_PROBE308_WIDTH : integer;
  attribute LC_PROBE308_WIDTH of U0 : label is 1;
  attribute LC_PROBE309_IS_DATA : string;
  attribute LC_PROBE309_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE309_IS_TRIG : string;
  attribute LC_PROBE309_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE309_MU_CNT : integer;
  attribute LC_PROBE309_MU_CNT of U0 : label is 1;
  attribute LC_PROBE309_PID : string;
  attribute LC_PROBE309_PID of U0 : label is "16'b0000000100110101";
  attribute LC_PROBE309_TYPE : integer;
  attribute LC_PROBE309_TYPE of U0 : label is 1;
  attribute LC_PROBE309_WIDTH : integer;
  attribute LC_PROBE309_WIDTH of U0 : label is 1;
  attribute LC_PROBE30_IS_DATA : string;
  attribute LC_PROBE30_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE30_IS_TRIG : string;
  attribute LC_PROBE30_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE30_MU_CNT : integer;
  attribute LC_PROBE30_MU_CNT of U0 : label is 1;
  attribute LC_PROBE30_PID : string;
  attribute LC_PROBE30_PID of U0 : label is "16'b0000000000011110";
  attribute LC_PROBE30_TYPE : integer;
  attribute LC_PROBE30_TYPE of U0 : label is 1;
  attribute LC_PROBE30_WIDTH : integer;
  attribute LC_PROBE30_WIDTH of U0 : label is 1;
  attribute LC_PROBE310_IS_DATA : string;
  attribute LC_PROBE310_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE310_IS_TRIG : string;
  attribute LC_PROBE310_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE310_MU_CNT : integer;
  attribute LC_PROBE310_MU_CNT of U0 : label is 1;
  attribute LC_PROBE310_PID : string;
  attribute LC_PROBE310_PID of U0 : label is "16'b0000000100110110";
  attribute LC_PROBE310_TYPE : integer;
  attribute LC_PROBE310_TYPE of U0 : label is 1;
  attribute LC_PROBE310_WIDTH : integer;
  attribute LC_PROBE310_WIDTH of U0 : label is 1;
  attribute LC_PROBE311_IS_DATA : string;
  attribute LC_PROBE311_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE311_IS_TRIG : string;
  attribute LC_PROBE311_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE311_MU_CNT : integer;
  attribute LC_PROBE311_MU_CNT of U0 : label is 1;
  attribute LC_PROBE311_PID : string;
  attribute LC_PROBE311_PID of U0 : label is "16'b0000000100110111";
  attribute LC_PROBE311_TYPE : integer;
  attribute LC_PROBE311_TYPE of U0 : label is 1;
  attribute LC_PROBE311_WIDTH : integer;
  attribute LC_PROBE311_WIDTH of U0 : label is 1;
  attribute LC_PROBE312_IS_DATA : string;
  attribute LC_PROBE312_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE312_IS_TRIG : string;
  attribute LC_PROBE312_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE312_MU_CNT : integer;
  attribute LC_PROBE312_MU_CNT of U0 : label is 1;
  attribute LC_PROBE312_PID : string;
  attribute LC_PROBE312_PID of U0 : label is "16'b0000000100111000";
  attribute LC_PROBE312_TYPE : integer;
  attribute LC_PROBE312_TYPE of U0 : label is 1;
  attribute LC_PROBE312_WIDTH : integer;
  attribute LC_PROBE312_WIDTH of U0 : label is 1;
  attribute LC_PROBE313_IS_DATA : string;
  attribute LC_PROBE313_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE313_IS_TRIG : string;
  attribute LC_PROBE313_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE313_MU_CNT : integer;
  attribute LC_PROBE313_MU_CNT of U0 : label is 1;
  attribute LC_PROBE313_PID : string;
  attribute LC_PROBE313_PID of U0 : label is "16'b0000000100111001";
  attribute LC_PROBE313_TYPE : integer;
  attribute LC_PROBE313_TYPE of U0 : label is 1;
  attribute LC_PROBE313_WIDTH : integer;
  attribute LC_PROBE313_WIDTH of U0 : label is 1;
  attribute LC_PROBE314_IS_DATA : string;
  attribute LC_PROBE314_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE314_IS_TRIG : string;
  attribute LC_PROBE314_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE314_MU_CNT : integer;
  attribute LC_PROBE314_MU_CNT of U0 : label is 1;
  attribute LC_PROBE314_PID : string;
  attribute LC_PROBE314_PID of U0 : label is "16'b0000000100111010";
  attribute LC_PROBE314_TYPE : integer;
  attribute LC_PROBE314_TYPE of U0 : label is 1;
  attribute LC_PROBE314_WIDTH : integer;
  attribute LC_PROBE314_WIDTH of U0 : label is 1;
  attribute LC_PROBE315_IS_DATA : string;
  attribute LC_PROBE315_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE315_IS_TRIG : string;
  attribute LC_PROBE315_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE315_MU_CNT : integer;
  attribute LC_PROBE315_MU_CNT of U0 : label is 1;
  attribute LC_PROBE315_PID : string;
  attribute LC_PROBE315_PID of U0 : label is "16'b0000000100111011";
  attribute LC_PROBE315_TYPE : integer;
  attribute LC_PROBE315_TYPE of U0 : label is 1;
  attribute LC_PROBE315_WIDTH : integer;
  attribute LC_PROBE315_WIDTH of U0 : label is 1;
  attribute LC_PROBE316_IS_DATA : string;
  attribute LC_PROBE316_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE316_IS_TRIG : string;
  attribute LC_PROBE316_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE316_MU_CNT : integer;
  attribute LC_PROBE316_MU_CNT of U0 : label is 1;
  attribute LC_PROBE316_PID : string;
  attribute LC_PROBE316_PID of U0 : label is "16'b0000000100111100";
  attribute LC_PROBE316_TYPE : integer;
  attribute LC_PROBE316_TYPE of U0 : label is 1;
  attribute LC_PROBE316_WIDTH : integer;
  attribute LC_PROBE316_WIDTH of U0 : label is 1;
  attribute LC_PROBE317_IS_DATA : string;
  attribute LC_PROBE317_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE317_IS_TRIG : string;
  attribute LC_PROBE317_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE317_MU_CNT : integer;
  attribute LC_PROBE317_MU_CNT of U0 : label is 1;
  attribute LC_PROBE317_PID : string;
  attribute LC_PROBE317_PID of U0 : label is "16'b0000000100111101";
  attribute LC_PROBE317_TYPE : integer;
  attribute LC_PROBE317_TYPE of U0 : label is 1;
  attribute LC_PROBE317_WIDTH : integer;
  attribute LC_PROBE317_WIDTH of U0 : label is 1;
  attribute LC_PROBE318_IS_DATA : string;
  attribute LC_PROBE318_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE318_IS_TRIG : string;
  attribute LC_PROBE318_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE318_MU_CNT : integer;
  attribute LC_PROBE318_MU_CNT of U0 : label is 1;
  attribute LC_PROBE318_PID : string;
  attribute LC_PROBE318_PID of U0 : label is "16'b0000000100111110";
  attribute LC_PROBE318_TYPE : integer;
  attribute LC_PROBE318_TYPE of U0 : label is 1;
  attribute LC_PROBE318_WIDTH : integer;
  attribute LC_PROBE318_WIDTH of U0 : label is 1;
  attribute LC_PROBE319_IS_DATA : string;
  attribute LC_PROBE319_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE319_IS_TRIG : string;
  attribute LC_PROBE319_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE319_MU_CNT : integer;
  attribute LC_PROBE319_MU_CNT of U0 : label is 1;
  attribute LC_PROBE319_PID : string;
  attribute LC_PROBE319_PID of U0 : label is "16'b0000000100111111";
  attribute LC_PROBE319_TYPE : integer;
  attribute LC_PROBE319_TYPE of U0 : label is 1;
  attribute LC_PROBE319_WIDTH : integer;
  attribute LC_PROBE319_WIDTH of U0 : label is 1;
  attribute LC_PROBE31_IS_DATA : string;
  attribute LC_PROBE31_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE31_IS_TRIG : string;
  attribute LC_PROBE31_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE31_MU_CNT : integer;
  attribute LC_PROBE31_MU_CNT of U0 : label is 1;
  attribute LC_PROBE31_PID : string;
  attribute LC_PROBE31_PID of U0 : label is "16'b0000000000011111";
  attribute LC_PROBE31_TYPE : integer;
  attribute LC_PROBE31_TYPE of U0 : label is 1;
  attribute LC_PROBE31_WIDTH : integer;
  attribute LC_PROBE31_WIDTH of U0 : label is 1;
  attribute LC_PROBE320_IS_DATA : string;
  attribute LC_PROBE320_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE320_IS_TRIG : string;
  attribute LC_PROBE320_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE320_MU_CNT : integer;
  attribute LC_PROBE320_MU_CNT of U0 : label is 1;
  attribute LC_PROBE320_PID : string;
  attribute LC_PROBE320_PID of U0 : label is "16'b0000000101000000";
  attribute LC_PROBE320_TYPE : integer;
  attribute LC_PROBE320_TYPE of U0 : label is 1;
  attribute LC_PROBE320_WIDTH : integer;
  attribute LC_PROBE320_WIDTH of U0 : label is 1;
  attribute LC_PROBE321_IS_DATA : string;
  attribute LC_PROBE321_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE321_IS_TRIG : string;
  attribute LC_PROBE321_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE321_MU_CNT : integer;
  attribute LC_PROBE321_MU_CNT of U0 : label is 1;
  attribute LC_PROBE321_PID : string;
  attribute LC_PROBE321_PID of U0 : label is "16'b0000000101000001";
  attribute LC_PROBE321_TYPE : integer;
  attribute LC_PROBE321_TYPE of U0 : label is 1;
  attribute LC_PROBE321_WIDTH : integer;
  attribute LC_PROBE321_WIDTH of U0 : label is 1;
  attribute LC_PROBE322_IS_DATA : string;
  attribute LC_PROBE322_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE322_IS_TRIG : string;
  attribute LC_PROBE322_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE322_MU_CNT : integer;
  attribute LC_PROBE322_MU_CNT of U0 : label is 1;
  attribute LC_PROBE322_PID : string;
  attribute LC_PROBE322_PID of U0 : label is "16'b0000000101000010";
  attribute LC_PROBE322_TYPE : integer;
  attribute LC_PROBE322_TYPE of U0 : label is 1;
  attribute LC_PROBE322_WIDTH : integer;
  attribute LC_PROBE322_WIDTH of U0 : label is 1;
  attribute LC_PROBE323_IS_DATA : string;
  attribute LC_PROBE323_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE323_IS_TRIG : string;
  attribute LC_PROBE323_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE323_MU_CNT : integer;
  attribute LC_PROBE323_MU_CNT of U0 : label is 1;
  attribute LC_PROBE323_PID : string;
  attribute LC_PROBE323_PID of U0 : label is "16'b0000000101000011";
  attribute LC_PROBE323_TYPE : integer;
  attribute LC_PROBE323_TYPE of U0 : label is 1;
  attribute LC_PROBE323_WIDTH : integer;
  attribute LC_PROBE323_WIDTH of U0 : label is 1;
  attribute LC_PROBE324_IS_DATA : string;
  attribute LC_PROBE324_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE324_IS_TRIG : string;
  attribute LC_PROBE324_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE324_MU_CNT : integer;
  attribute LC_PROBE324_MU_CNT of U0 : label is 1;
  attribute LC_PROBE324_PID : string;
  attribute LC_PROBE324_PID of U0 : label is "16'b0000000101000100";
  attribute LC_PROBE324_TYPE : integer;
  attribute LC_PROBE324_TYPE of U0 : label is 1;
  attribute LC_PROBE324_WIDTH : integer;
  attribute LC_PROBE324_WIDTH of U0 : label is 1;
  attribute LC_PROBE325_IS_DATA : string;
  attribute LC_PROBE325_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE325_IS_TRIG : string;
  attribute LC_PROBE325_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE325_MU_CNT : integer;
  attribute LC_PROBE325_MU_CNT of U0 : label is 1;
  attribute LC_PROBE325_PID : string;
  attribute LC_PROBE325_PID of U0 : label is "16'b0000000101000101";
  attribute LC_PROBE325_TYPE : integer;
  attribute LC_PROBE325_TYPE of U0 : label is 1;
  attribute LC_PROBE325_WIDTH : integer;
  attribute LC_PROBE325_WIDTH of U0 : label is 1;
  attribute LC_PROBE326_IS_DATA : string;
  attribute LC_PROBE326_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE326_IS_TRIG : string;
  attribute LC_PROBE326_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE326_MU_CNT : integer;
  attribute LC_PROBE326_MU_CNT of U0 : label is 1;
  attribute LC_PROBE326_PID : string;
  attribute LC_PROBE326_PID of U0 : label is "16'b0000000101000110";
  attribute LC_PROBE326_TYPE : integer;
  attribute LC_PROBE326_TYPE of U0 : label is 1;
  attribute LC_PROBE326_WIDTH : integer;
  attribute LC_PROBE326_WIDTH of U0 : label is 1;
  attribute LC_PROBE327_IS_DATA : string;
  attribute LC_PROBE327_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE327_IS_TRIG : string;
  attribute LC_PROBE327_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE327_MU_CNT : integer;
  attribute LC_PROBE327_MU_CNT of U0 : label is 1;
  attribute LC_PROBE327_PID : string;
  attribute LC_PROBE327_PID of U0 : label is "16'b0000000101000111";
  attribute LC_PROBE327_TYPE : integer;
  attribute LC_PROBE327_TYPE of U0 : label is 1;
  attribute LC_PROBE327_WIDTH : integer;
  attribute LC_PROBE327_WIDTH of U0 : label is 1;
  attribute LC_PROBE328_IS_DATA : string;
  attribute LC_PROBE328_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE328_IS_TRIG : string;
  attribute LC_PROBE328_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE328_MU_CNT : integer;
  attribute LC_PROBE328_MU_CNT of U0 : label is 1;
  attribute LC_PROBE328_PID : string;
  attribute LC_PROBE328_PID of U0 : label is "16'b0000000101001000";
  attribute LC_PROBE328_TYPE : integer;
  attribute LC_PROBE328_TYPE of U0 : label is 1;
  attribute LC_PROBE328_WIDTH : integer;
  attribute LC_PROBE328_WIDTH of U0 : label is 1;
  attribute LC_PROBE329_IS_DATA : string;
  attribute LC_PROBE329_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE329_IS_TRIG : string;
  attribute LC_PROBE329_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE329_MU_CNT : integer;
  attribute LC_PROBE329_MU_CNT of U0 : label is 1;
  attribute LC_PROBE329_PID : string;
  attribute LC_PROBE329_PID of U0 : label is "16'b0000000101001001";
  attribute LC_PROBE329_TYPE : integer;
  attribute LC_PROBE329_TYPE of U0 : label is 1;
  attribute LC_PROBE329_WIDTH : integer;
  attribute LC_PROBE329_WIDTH of U0 : label is 1;
  attribute LC_PROBE32_IS_DATA : string;
  attribute LC_PROBE32_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE32_IS_TRIG : string;
  attribute LC_PROBE32_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE32_MU_CNT : integer;
  attribute LC_PROBE32_MU_CNT of U0 : label is 1;
  attribute LC_PROBE32_PID : string;
  attribute LC_PROBE32_PID of U0 : label is "16'b0000000000100000";
  attribute LC_PROBE32_TYPE : integer;
  attribute LC_PROBE32_TYPE of U0 : label is 1;
  attribute LC_PROBE32_WIDTH : integer;
  attribute LC_PROBE32_WIDTH of U0 : label is 1;
  attribute LC_PROBE330_IS_DATA : string;
  attribute LC_PROBE330_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE330_IS_TRIG : string;
  attribute LC_PROBE330_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE330_MU_CNT : integer;
  attribute LC_PROBE330_MU_CNT of U0 : label is 1;
  attribute LC_PROBE330_PID : string;
  attribute LC_PROBE330_PID of U0 : label is "16'b0000000101001010";
  attribute LC_PROBE330_TYPE : integer;
  attribute LC_PROBE330_TYPE of U0 : label is 1;
  attribute LC_PROBE330_WIDTH : integer;
  attribute LC_PROBE330_WIDTH of U0 : label is 1;
  attribute LC_PROBE331_IS_DATA : string;
  attribute LC_PROBE331_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE331_IS_TRIG : string;
  attribute LC_PROBE331_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE331_MU_CNT : integer;
  attribute LC_PROBE331_MU_CNT of U0 : label is 1;
  attribute LC_PROBE331_PID : string;
  attribute LC_PROBE331_PID of U0 : label is "16'b0000000101001011";
  attribute LC_PROBE331_TYPE : integer;
  attribute LC_PROBE331_TYPE of U0 : label is 1;
  attribute LC_PROBE331_WIDTH : integer;
  attribute LC_PROBE331_WIDTH of U0 : label is 1;
  attribute LC_PROBE332_IS_DATA : string;
  attribute LC_PROBE332_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE332_IS_TRIG : string;
  attribute LC_PROBE332_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE332_MU_CNT : integer;
  attribute LC_PROBE332_MU_CNT of U0 : label is 1;
  attribute LC_PROBE332_PID : string;
  attribute LC_PROBE332_PID of U0 : label is "16'b0000000101001100";
  attribute LC_PROBE332_TYPE : integer;
  attribute LC_PROBE332_TYPE of U0 : label is 1;
  attribute LC_PROBE332_WIDTH : integer;
  attribute LC_PROBE332_WIDTH of U0 : label is 1;
  attribute LC_PROBE333_IS_DATA : string;
  attribute LC_PROBE333_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE333_IS_TRIG : string;
  attribute LC_PROBE333_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE333_MU_CNT : integer;
  attribute LC_PROBE333_MU_CNT of U0 : label is 1;
  attribute LC_PROBE333_PID : string;
  attribute LC_PROBE333_PID of U0 : label is "16'b0000000101001101";
  attribute LC_PROBE333_TYPE : integer;
  attribute LC_PROBE333_TYPE of U0 : label is 1;
  attribute LC_PROBE333_WIDTH : integer;
  attribute LC_PROBE333_WIDTH of U0 : label is 1;
  attribute LC_PROBE334_IS_DATA : string;
  attribute LC_PROBE334_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE334_IS_TRIG : string;
  attribute LC_PROBE334_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE334_MU_CNT : integer;
  attribute LC_PROBE334_MU_CNT of U0 : label is 1;
  attribute LC_PROBE334_PID : string;
  attribute LC_PROBE334_PID of U0 : label is "16'b0000000101001110";
  attribute LC_PROBE334_TYPE : integer;
  attribute LC_PROBE334_TYPE of U0 : label is 1;
  attribute LC_PROBE334_WIDTH : integer;
  attribute LC_PROBE334_WIDTH of U0 : label is 1;
  attribute LC_PROBE335_IS_DATA : string;
  attribute LC_PROBE335_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE335_IS_TRIG : string;
  attribute LC_PROBE335_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE335_MU_CNT : integer;
  attribute LC_PROBE335_MU_CNT of U0 : label is 1;
  attribute LC_PROBE335_PID : string;
  attribute LC_PROBE335_PID of U0 : label is "16'b0000000101001111";
  attribute LC_PROBE335_TYPE : integer;
  attribute LC_PROBE335_TYPE of U0 : label is 1;
  attribute LC_PROBE335_WIDTH : integer;
  attribute LC_PROBE335_WIDTH of U0 : label is 1;
  attribute LC_PROBE336_IS_DATA : string;
  attribute LC_PROBE336_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE336_IS_TRIG : string;
  attribute LC_PROBE336_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE336_MU_CNT : integer;
  attribute LC_PROBE336_MU_CNT of U0 : label is 1;
  attribute LC_PROBE336_PID : string;
  attribute LC_PROBE336_PID of U0 : label is "16'b0000000101010000";
  attribute LC_PROBE336_TYPE : integer;
  attribute LC_PROBE336_TYPE of U0 : label is 1;
  attribute LC_PROBE336_WIDTH : integer;
  attribute LC_PROBE336_WIDTH of U0 : label is 1;
  attribute LC_PROBE337_IS_DATA : string;
  attribute LC_PROBE337_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE337_IS_TRIG : string;
  attribute LC_PROBE337_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE337_MU_CNT : integer;
  attribute LC_PROBE337_MU_CNT of U0 : label is 1;
  attribute LC_PROBE337_PID : string;
  attribute LC_PROBE337_PID of U0 : label is "16'b0000000101010001";
  attribute LC_PROBE337_TYPE : integer;
  attribute LC_PROBE337_TYPE of U0 : label is 1;
  attribute LC_PROBE337_WIDTH : integer;
  attribute LC_PROBE337_WIDTH of U0 : label is 1;
  attribute LC_PROBE338_IS_DATA : string;
  attribute LC_PROBE338_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE338_IS_TRIG : string;
  attribute LC_PROBE338_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE338_MU_CNT : integer;
  attribute LC_PROBE338_MU_CNT of U0 : label is 1;
  attribute LC_PROBE338_PID : string;
  attribute LC_PROBE338_PID of U0 : label is "16'b0000000101010010";
  attribute LC_PROBE338_TYPE : integer;
  attribute LC_PROBE338_TYPE of U0 : label is 1;
  attribute LC_PROBE338_WIDTH : integer;
  attribute LC_PROBE338_WIDTH of U0 : label is 1;
  attribute LC_PROBE339_IS_DATA : string;
  attribute LC_PROBE339_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE339_IS_TRIG : string;
  attribute LC_PROBE339_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE339_MU_CNT : integer;
  attribute LC_PROBE339_MU_CNT of U0 : label is 1;
  attribute LC_PROBE339_PID : string;
  attribute LC_PROBE339_PID of U0 : label is "16'b0000000101010011";
  attribute LC_PROBE339_TYPE : integer;
  attribute LC_PROBE339_TYPE of U0 : label is 1;
  attribute LC_PROBE339_WIDTH : integer;
  attribute LC_PROBE339_WIDTH of U0 : label is 1;
  attribute LC_PROBE33_IS_DATA : string;
  attribute LC_PROBE33_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE33_IS_TRIG : string;
  attribute LC_PROBE33_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE33_MU_CNT : integer;
  attribute LC_PROBE33_MU_CNT of U0 : label is 1;
  attribute LC_PROBE33_PID : string;
  attribute LC_PROBE33_PID of U0 : label is "16'b0000000000100001";
  attribute LC_PROBE33_TYPE : integer;
  attribute LC_PROBE33_TYPE of U0 : label is 1;
  attribute LC_PROBE33_WIDTH : integer;
  attribute LC_PROBE33_WIDTH of U0 : label is 1;
  attribute LC_PROBE340_IS_DATA : string;
  attribute LC_PROBE340_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE340_IS_TRIG : string;
  attribute LC_PROBE340_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE340_MU_CNT : integer;
  attribute LC_PROBE340_MU_CNT of U0 : label is 1;
  attribute LC_PROBE340_PID : string;
  attribute LC_PROBE340_PID of U0 : label is "16'b0000000101010100";
  attribute LC_PROBE340_TYPE : integer;
  attribute LC_PROBE340_TYPE of U0 : label is 1;
  attribute LC_PROBE340_WIDTH : integer;
  attribute LC_PROBE340_WIDTH of U0 : label is 1;
  attribute LC_PROBE341_IS_DATA : string;
  attribute LC_PROBE341_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE341_IS_TRIG : string;
  attribute LC_PROBE341_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE341_MU_CNT : integer;
  attribute LC_PROBE341_MU_CNT of U0 : label is 1;
  attribute LC_PROBE341_PID : string;
  attribute LC_PROBE341_PID of U0 : label is "16'b0000000101010101";
  attribute LC_PROBE341_TYPE : integer;
  attribute LC_PROBE341_TYPE of U0 : label is 1;
  attribute LC_PROBE341_WIDTH : integer;
  attribute LC_PROBE341_WIDTH of U0 : label is 1;
  attribute LC_PROBE342_IS_DATA : string;
  attribute LC_PROBE342_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE342_IS_TRIG : string;
  attribute LC_PROBE342_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE342_MU_CNT : integer;
  attribute LC_PROBE342_MU_CNT of U0 : label is 1;
  attribute LC_PROBE342_PID : string;
  attribute LC_PROBE342_PID of U0 : label is "16'b0000000101010110";
  attribute LC_PROBE342_TYPE : integer;
  attribute LC_PROBE342_TYPE of U0 : label is 1;
  attribute LC_PROBE342_WIDTH : integer;
  attribute LC_PROBE342_WIDTH of U0 : label is 1;
  attribute LC_PROBE343_IS_DATA : string;
  attribute LC_PROBE343_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE343_IS_TRIG : string;
  attribute LC_PROBE343_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE343_MU_CNT : integer;
  attribute LC_PROBE343_MU_CNT of U0 : label is 1;
  attribute LC_PROBE343_PID : string;
  attribute LC_PROBE343_PID of U0 : label is "16'b0000000101010111";
  attribute LC_PROBE343_TYPE : integer;
  attribute LC_PROBE343_TYPE of U0 : label is 1;
  attribute LC_PROBE343_WIDTH : integer;
  attribute LC_PROBE343_WIDTH of U0 : label is 1;
  attribute LC_PROBE344_IS_DATA : string;
  attribute LC_PROBE344_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE344_IS_TRIG : string;
  attribute LC_PROBE344_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE344_MU_CNT : integer;
  attribute LC_PROBE344_MU_CNT of U0 : label is 1;
  attribute LC_PROBE344_PID : string;
  attribute LC_PROBE344_PID of U0 : label is "16'b0000000101011000";
  attribute LC_PROBE344_TYPE : integer;
  attribute LC_PROBE344_TYPE of U0 : label is 1;
  attribute LC_PROBE344_WIDTH : integer;
  attribute LC_PROBE344_WIDTH of U0 : label is 1;
  attribute LC_PROBE345_IS_DATA : string;
  attribute LC_PROBE345_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE345_IS_TRIG : string;
  attribute LC_PROBE345_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE345_MU_CNT : integer;
  attribute LC_PROBE345_MU_CNT of U0 : label is 1;
  attribute LC_PROBE345_PID : string;
  attribute LC_PROBE345_PID of U0 : label is "16'b0000000101011001";
  attribute LC_PROBE345_TYPE : integer;
  attribute LC_PROBE345_TYPE of U0 : label is 1;
  attribute LC_PROBE345_WIDTH : integer;
  attribute LC_PROBE345_WIDTH of U0 : label is 1;
  attribute LC_PROBE346_IS_DATA : string;
  attribute LC_PROBE346_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE346_IS_TRIG : string;
  attribute LC_PROBE346_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE346_MU_CNT : integer;
  attribute LC_PROBE346_MU_CNT of U0 : label is 1;
  attribute LC_PROBE346_PID : string;
  attribute LC_PROBE346_PID of U0 : label is "16'b0000000101011010";
  attribute LC_PROBE346_TYPE : integer;
  attribute LC_PROBE346_TYPE of U0 : label is 1;
  attribute LC_PROBE346_WIDTH : integer;
  attribute LC_PROBE346_WIDTH of U0 : label is 1;
  attribute LC_PROBE347_IS_DATA : string;
  attribute LC_PROBE347_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE347_IS_TRIG : string;
  attribute LC_PROBE347_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE347_MU_CNT : integer;
  attribute LC_PROBE347_MU_CNT of U0 : label is 1;
  attribute LC_PROBE347_PID : string;
  attribute LC_PROBE347_PID of U0 : label is "16'b0000000101011011";
  attribute LC_PROBE347_TYPE : integer;
  attribute LC_PROBE347_TYPE of U0 : label is 1;
  attribute LC_PROBE347_WIDTH : integer;
  attribute LC_PROBE347_WIDTH of U0 : label is 1;
  attribute LC_PROBE348_IS_DATA : string;
  attribute LC_PROBE348_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE348_IS_TRIG : string;
  attribute LC_PROBE348_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE348_MU_CNT : integer;
  attribute LC_PROBE348_MU_CNT of U0 : label is 1;
  attribute LC_PROBE348_PID : string;
  attribute LC_PROBE348_PID of U0 : label is "16'b0000000101011100";
  attribute LC_PROBE348_TYPE : integer;
  attribute LC_PROBE348_TYPE of U0 : label is 1;
  attribute LC_PROBE348_WIDTH : integer;
  attribute LC_PROBE348_WIDTH of U0 : label is 1;
  attribute LC_PROBE349_IS_DATA : string;
  attribute LC_PROBE349_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE349_IS_TRIG : string;
  attribute LC_PROBE349_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE349_MU_CNT : integer;
  attribute LC_PROBE349_MU_CNT of U0 : label is 1;
  attribute LC_PROBE349_PID : string;
  attribute LC_PROBE349_PID of U0 : label is "16'b0000000101011101";
  attribute LC_PROBE349_TYPE : integer;
  attribute LC_PROBE349_TYPE of U0 : label is 1;
  attribute LC_PROBE349_WIDTH : integer;
  attribute LC_PROBE349_WIDTH of U0 : label is 1;
  attribute LC_PROBE34_IS_DATA : string;
  attribute LC_PROBE34_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE34_IS_TRIG : string;
  attribute LC_PROBE34_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE34_MU_CNT : integer;
  attribute LC_PROBE34_MU_CNT of U0 : label is 1;
  attribute LC_PROBE34_PID : string;
  attribute LC_PROBE34_PID of U0 : label is "16'b0000000000100010";
  attribute LC_PROBE34_TYPE : integer;
  attribute LC_PROBE34_TYPE of U0 : label is 1;
  attribute LC_PROBE34_WIDTH : integer;
  attribute LC_PROBE34_WIDTH of U0 : label is 1;
  attribute LC_PROBE350_IS_DATA : string;
  attribute LC_PROBE350_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE350_IS_TRIG : string;
  attribute LC_PROBE350_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE350_MU_CNT : integer;
  attribute LC_PROBE350_MU_CNT of U0 : label is 1;
  attribute LC_PROBE350_PID : string;
  attribute LC_PROBE350_PID of U0 : label is "16'b0000000101011110";
  attribute LC_PROBE350_TYPE : integer;
  attribute LC_PROBE350_TYPE of U0 : label is 1;
  attribute LC_PROBE350_WIDTH : integer;
  attribute LC_PROBE350_WIDTH of U0 : label is 1;
  attribute LC_PROBE351_IS_DATA : string;
  attribute LC_PROBE351_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE351_IS_TRIG : string;
  attribute LC_PROBE351_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE351_MU_CNT : integer;
  attribute LC_PROBE351_MU_CNT of U0 : label is 1;
  attribute LC_PROBE351_PID : string;
  attribute LC_PROBE351_PID of U0 : label is "16'b0000000101011111";
  attribute LC_PROBE351_TYPE : integer;
  attribute LC_PROBE351_TYPE of U0 : label is 1;
  attribute LC_PROBE351_WIDTH : integer;
  attribute LC_PROBE351_WIDTH of U0 : label is 1;
  attribute LC_PROBE352_IS_DATA : string;
  attribute LC_PROBE352_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE352_IS_TRIG : string;
  attribute LC_PROBE352_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE352_MU_CNT : integer;
  attribute LC_PROBE352_MU_CNT of U0 : label is 1;
  attribute LC_PROBE352_PID : string;
  attribute LC_PROBE352_PID of U0 : label is "16'b0000000101100000";
  attribute LC_PROBE352_TYPE : integer;
  attribute LC_PROBE352_TYPE of U0 : label is 1;
  attribute LC_PROBE352_WIDTH : integer;
  attribute LC_PROBE352_WIDTH of U0 : label is 1;
  attribute LC_PROBE353_IS_DATA : string;
  attribute LC_PROBE353_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE353_IS_TRIG : string;
  attribute LC_PROBE353_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE353_MU_CNT : integer;
  attribute LC_PROBE353_MU_CNT of U0 : label is 1;
  attribute LC_PROBE353_PID : string;
  attribute LC_PROBE353_PID of U0 : label is "16'b0000000101100001";
  attribute LC_PROBE353_TYPE : integer;
  attribute LC_PROBE353_TYPE of U0 : label is 1;
  attribute LC_PROBE353_WIDTH : integer;
  attribute LC_PROBE353_WIDTH of U0 : label is 1;
  attribute LC_PROBE354_IS_DATA : string;
  attribute LC_PROBE354_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE354_IS_TRIG : string;
  attribute LC_PROBE354_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE354_MU_CNT : integer;
  attribute LC_PROBE354_MU_CNT of U0 : label is 1;
  attribute LC_PROBE354_PID : string;
  attribute LC_PROBE354_PID of U0 : label is "16'b0000000101100010";
  attribute LC_PROBE354_TYPE : integer;
  attribute LC_PROBE354_TYPE of U0 : label is 1;
  attribute LC_PROBE354_WIDTH : integer;
  attribute LC_PROBE354_WIDTH of U0 : label is 1;
  attribute LC_PROBE355_IS_DATA : string;
  attribute LC_PROBE355_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE355_IS_TRIG : string;
  attribute LC_PROBE355_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE355_MU_CNT : integer;
  attribute LC_PROBE355_MU_CNT of U0 : label is 1;
  attribute LC_PROBE355_PID : string;
  attribute LC_PROBE355_PID of U0 : label is "16'b0000000101100011";
  attribute LC_PROBE355_TYPE : integer;
  attribute LC_PROBE355_TYPE of U0 : label is 1;
  attribute LC_PROBE355_WIDTH : integer;
  attribute LC_PROBE355_WIDTH of U0 : label is 1;
  attribute LC_PROBE356_IS_DATA : string;
  attribute LC_PROBE356_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE356_IS_TRIG : string;
  attribute LC_PROBE356_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE356_MU_CNT : integer;
  attribute LC_PROBE356_MU_CNT of U0 : label is 1;
  attribute LC_PROBE356_PID : string;
  attribute LC_PROBE356_PID of U0 : label is "16'b0000000101100100";
  attribute LC_PROBE356_TYPE : integer;
  attribute LC_PROBE356_TYPE of U0 : label is 1;
  attribute LC_PROBE356_WIDTH : integer;
  attribute LC_PROBE356_WIDTH of U0 : label is 1;
  attribute LC_PROBE357_IS_DATA : string;
  attribute LC_PROBE357_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE357_IS_TRIG : string;
  attribute LC_PROBE357_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE357_MU_CNT : integer;
  attribute LC_PROBE357_MU_CNT of U0 : label is 1;
  attribute LC_PROBE357_PID : string;
  attribute LC_PROBE357_PID of U0 : label is "16'b0000000101100101";
  attribute LC_PROBE357_TYPE : integer;
  attribute LC_PROBE357_TYPE of U0 : label is 1;
  attribute LC_PROBE357_WIDTH : integer;
  attribute LC_PROBE357_WIDTH of U0 : label is 1;
  attribute LC_PROBE358_IS_DATA : string;
  attribute LC_PROBE358_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE358_IS_TRIG : string;
  attribute LC_PROBE358_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE358_MU_CNT : integer;
  attribute LC_PROBE358_MU_CNT of U0 : label is 1;
  attribute LC_PROBE358_PID : string;
  attribute LC_PROBE358_PID of U0 : label is "16'b0000000101100110";
  attribute LC_PROBE358_TYPE : integer;
  attribute LC_PROBE358_TYPE of U0 : label is 1;
  attribute LC_PROBE358_WIDTH : integer;
  attribute LC_PROBE358_WIDTH of U0 : label is 1;
  attribute LC_PROBE359_IS_DATA : string;
  attribute LC_PROBE359_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE359_IS_TRIG : string;
  attribute LC_PROBE359_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE359_MU_CNT : integer;
  attribute LC_PROBE359_MU_CNT of U0 : label is 1;
  attribute LC_PROBE359_PID : string;
  attribute LC_PROBE359_PID of U0 : label is "16'b0000000101100111";
  attribute LC_PROBE359_TYPE : integer;
  attribute LC_PROBE359_TYPE of U0 : label is 1;
  attribute LC_PROBE359_WIDTH : integer;
  attribute LC_PROBE359_WIDTH of U0 : label is 1;
  attribute LC_PROBE35_IS_DATA : string;
  attribute LC_PROBE35_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE35_IS_TRIG : string;
  attribute LC_PROBE35_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE35_MU_CNT : integer;
  attribute LC_PROBE35_MU_CNT of U0 : label is 1;
  attribute LC_PROBE35_PID : string;
  attribute LC_PROBE35_PID of U0 : label is "16'b0000000000100011";
  attribute LC_PROBE35_TYPE : integer;
  attribute LC_PROBE35_TYPE of U0 : label is 1;
  attribute LC_PROBE35_WIDTH : integer;
  attribute LC_PROBE35_WIDTH of U0 : label is 1;
  attribute LC_PROBE360_IS_DATA : string;
  attribute LC_PROBE360_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE360_IS_TRIG : string;
  attribute LC_PROBE360_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE360_MU_CNT : integer;
  attribute LC_PROBE360_MU_CNT of U0 : label is 1;
  attribute LC_PROBE360_PID : string;
  attribute LC_PROBE360_PID of U0 : label is "16'b0000000101101000";
  attribute LC_PROBE360_TYPE : integer;
  attribute LC_PROBE360_TYPE of U0 : label is 1;
  attribute LC_PROBE360_WIDTH : integer;
  attribute LC_PROBE360_WIDTH of U0 : label is 1;
  attribute LC_PROBE361_IS_DATA : string;
  attribute LC_PROBE361_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE361_IS_TRIG : string;
  attribute LC_PROBE361_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE361_MU_CNT : integer;
  attribute LC_PROBE361_MU_CNT of U0 : label is 1;
  attribute LC_PROBE361_PID : string;
  attribute LC_PROBE361_PID of U0 : label is "16'b0000000101101001";
  attribute LC_PROBE361_TYPE : integer;
  attribute LC_PROBE361_TYPE of U0 : label is 1;
  attribute LC_PROBE361_WIDTH : integer;
  attribute LC_PROBE361_WIDTH of U0 : label is 1;
  attribute LC_PROBE362_IS_DATA : string;
  attribute LC_PROBE362_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE362_IS_TRIG : string;
  attribute LC_PROBE362_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE362_MU_CNT : integer;
  attribute LC_PROBE362_MU_CNT of U0 : label is 1;
  attribute LC_PROBE362_PID : string;
  attribute LC_PROBE362_PID of U0 : label is "16'b0000000101101010";
  attribute LC_PROBE362_TYPE : integer;
  attribute LC_PROBE362_TYPE of U0 : label is 1;
  attribute LC_PROBE362_WIDTH : integer;
  attribute LC_PROBE362_WIDTH of U0 : label is 1;
  attribute LC_PROBE363_IS_DATA : string;
  attribute LC_PROBE363_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE363_IS_TRIG : string;
  attribute LC_PROBE363_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE363_MU_CNT : integer;
  attribute LC_PROBE363_MU_CNT of U0 : label is 1;
  attribute LC_PROBE363_PID : string;
  attribute LC_PROBE363_PID of U0 : label is "16'b0000000101101011";
  attribute LC_PROBE363_TYPE : integer;
  attribute LC_PROBE363_TYPE of U0 : label is 1;
  attribute LC_PROBE363_WIDTH : integer;
  attribute LC_PROBE363_WIDTH of U0 : label is 1;
  attribute LC_PROBE364_IS_DATA : string;
  attribute LC_PROBE364_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE364_IS_TRIG : string;
  attribute LC_PROBE364_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE364_MU_CNT : integer;
  attribute LC_PROBE364_MU_CNT of U0 : label is 1;
  attribute LC_PROBE364_PID : string;
  attribute LC_PROBE364_PID of U0 : label is "16'b0000000101101100";
  attribute LC_PROBE364_TYPE : integer;
  attribute LC_PROBE364_TYPE of U0 : label is 1;
  attribute LC_PROBE364_WIDTH : integer;
  attribute LC_PROBE364_WIDTH of U0 : label is 1;
  attribute LC_PROBE365_IS_DATA : string;
  attribute LC_PROBE365_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE365_IS_TRIG : string;
  attribute LC_PROBE365_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE365_MU_CNT : integer;
  attribute LC_PROBE365_MU_CNT of U0 : label is 1;
  attribute LC_PROBE365_PID : string;
  attribute LC_PROBE365_PID of U0 : label is "16'b0000000101101101";
  attribute LC_PROBE365_TYPE : integer;
  attribute LC_PROBE365_TYPE of U0 : label is 1;
  attribute LC_PROBE365_WIDTH : integer;
  attribute LC_PROBE365_WIDTH of U0 : label is 1;
  attribute LC_PROBE366_IS_DATA : string;
  attribute LC_PROBE366_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE366_IS_TRIG : string;
  attribute LC_PROBE366_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE366_MU_CNT : integer;
  attribute LC_PROBE366_MU_CNT of U0 : label is 1;
  attribute LC_PROBE366_PID : string;
  attribute LC_PROBE366_PID of U0 : label is "16'b0000000101101110";
  attribute LC_PROBE366_TYPE : integer;
  attribute LC_PROBE366_TYPE of U0 : label is 1;
  attribute LC_PROBE366_WIDTH : integer;
  attribute LC_PROBE366_WIDTH of U0 : label is 1;
  attribute LC_PROBE367_IS_DATA : string;
  attribute LC_PROBE367_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE367_IS_TRIG : string;
  attribute LC_PROBE367_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE367_MU_CNT : integer;
  attribute LC_PROBE367_MU_CNT of U0 : label is 1;
  attribute LC_PROBE367_PID : string;
  attribute LC_PROBE367_PID of U0 : label is "16'b0000000101101111";
  attribute LC_PROBE367_TYPE : integer;
  attribute LC_PROBE367_TYPE of U0 : label is 1;
  attribute LC_PROBE367_WIDTH : integer;
  attribute LC_PROBE367_WIDTH of U0 : label is 1;
  attribute LC_PROBE368_IS_DATA : string;
  attribute LC_PROBE368_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE368_IS_TRIG : string;
  attribute LC_PROBE368_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE368_MU_CNT : integer;
  attribute LC_PROBE368_MU_CNT of U0 : label is 1;
  attribute LC_PROBE368_PID : string;
  attribute LC_PROBE368_PID of U0 : label is "16'b0000000101110000";
  attribute LC_PROBE368_TYPE : integer;
  attribute LC_PROBE368_TYPE of U0 : label is 1;
  attribute LC_PROBE368_WIDTH : integer;
  attribute LC_PROBE368_WIDTH of U0 : label is 1;
  attribute LC_PROBE369_IS_DATA : string;
  attribute LC_PROBE369_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE369_IS_TRIG : string;
  attribute LC_PROBE369_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE369_MU_CNT : integer;
  attribute LC_PROBE369_MU_CNT of U0 : label is 1;
  attribute LC_PROBE369_PID : string;
  attribute LC_PROBE369_PID of U0 : label is "16'b0000000101110001";
  attribute LC_PROBE369_TYPE : integer;
  attribute LC_PROBE369_TYPE of U0 : label is 1;
  attribute LC_PROBE369_WIDTH : integer;
  attribute LC_PROBE369_WIDTH of U0 : label is 1;
  attribute LC_PROBE36_IS_DATA : string;
  attribute LC_PROBE36_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE36_IS_TRIG : string;
  attribute LC_PROBE36_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE36_MU_CNT : integer;
  attribute LC_PROBE36_MU_CNT of U0 : label is 1;
  attribute LC_PROBE36_PID : string;
  attribute LC_PROBE36_PID of U0 : label is "16'b0000000000100100";
  attribute LC_PROBE36_TYPE : integer;
  attribute LC_PROBE36_TYPE of U0 : label is 1;
  attribute LC_PROBE36_WIDTH : integer;
  attribute LC_PROBE36_WIDTH of U0 : label is 1;
  attribute LC_PROBE370_IS_DATA : string;
  attribute LC_PROBE370_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE370_IS_TRIG : string;
  attribute LC_PROBE370_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE370_MU_CNT : integer;
  attribute LC_PROBE370_MU_CNT of U0 : label is 1;
  attribute LC_PROBE370_PID : string;
  attribute LC_PROBE370_PID of U0 : label is "16'b0000000101110010";
  attribute LC_PROBE370_TYPE : integer;
  attribute LC_PROBE370_TYPE of U0 : label is 1;
  attribute LC_PROBE370_WIDTH : integer;
  attribute LC_PROBE370_WIDTH of U0 : label is 1;
  attribute LC_PROBE371_IS_DATA : string;
  attribute LC_PROBE371_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE371_IS_TRIG : string;
  attribute LC_PROBE371_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE371_MU_CNT : integer;
  attribute LC_PROBE371_MU_CNT of U0 : label is 1;
  attribute LC_PROBE371_PID : string;
  attribute LC_PROBE371_PID of U0 : label is "16'b0000000101110011";
  attribute LC_PROBE371_TYPE : integer;
  attribute LC_PROBE371_TYPE of U0 : label is 1;
  attribute LC_PROBE371_WIDTH : integer;
  attribute LC_PROBE371_WIDTH of U0 : label is 1;
  attribute LC_PROBE372_IS_DATA : string;
  attribute LC_PROBE372_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE372_IS_TRIG : string;
  attribute LC_PROBE372_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE372_MU_CNT : integer;
  attribute LC_PROBE372_MU_CNT of U0 : label is 1;
  attribute LC_PROBE372_PID : string;
  attribute LC_PROBE372_PID of U0 : label is "16'b0000000101110100";
  attribute LC_PROBE372_TYPE : integer;
  attribute LC_PROBE372_TYPE of U0 : label is 1;
  attribute LC_PROBE372_WIDTH : integer;
  attribute LC_PROBE372_WIDTH of U0 : label is 1;
  attribute LC_PROBE373_IS_DATA : string;
  attribute LC_PROBE373_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE373_IS_TRIG : string;
  attribute LC_PROBE373_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE373_MU_CNT : integer;
  attribute LC_PROBE373_MU_CNT of U0 : label is 1;
  attribute LC_PROBE373_PID : string;
  attribute LC_PROBE373_PID of U0 : label is "16'b0000000101110101";
  attribute LC_PROBE373_TYPE : integer;
  attribute LC_PROBE373_TYPE of U0 : label is 1;
  attribute LC_PROBE373_WIDTH : integer;
  attribute LC_PROBE373_WIDTH of U0 : label is 1;
  attribute LC_PROBE374_IS_DATA : string;
  attribute LC_PROBE374_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE374_IS_TRIG : string;
  attribute LC_PROBE374_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE374_MU_CNT : integer;
  attribute LC_PROBE374_MU_CNT of U0 : label is 1;
  attribute LC_PROBE374_PID : string;
  attribute LC_PROBE374_PID of U0 : label is "16'b0000000101110110";
  attribute LC_PROBE374_TYPE : integer;
  attribute LC_PROBE374_TYPE of U0 : label is 1;
  attribute LC_PROBE374_WIDTH : integer;
  attribute LC_PROBE374_WIDTH of U0 : label is 1;
  attribute LC_PROBE375_IS_DATA : string;
  attribute LC_PROBE375_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE375_IS_TRIG : string;
  attribute LC_PROBE375_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE375_MU_CNT : integer;
  attribute LC_PROBE375_MU_CNT of U0 : label is 1;
  attribute LC_PROBE375_PID : string;
  attribute LC_PROBE375_PID of U0 : label is "16'b0000000101110111";
  attribute LC_PROBE375_TYPE : integer;
  attribute LC_PROBE375_TYPE of U0 : label is 1;
  attribute LC_PROBE375_WIDTH : integer;
  attribute LC_PROBE375_WIDTH of U0 : label is 1;
  attribute LC_PROBE376_IS_DATA : string;
  attribute LC_PROBE376_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE376_IS_TRIG : string;
  attribute LC_PROBE376_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE376_MU_CNT : integer;
  attribute LC_PROBE376_MU_CNT of U0 : label is 1;
  attribute LC_PROBE376_PID : string;
  attribute LC_PROBE376_PID of U0 : label is "16'b0000000101111000";
  attribute LC_PROBE376_TYPE : integer;
  attribute LC_PROBE376_TYPE of U0 : label is 1;
  attribute LC_PROBE376_WIDTH : integer;
  attribute LC_PROBE376_WIDTH of U0 : label is 1;
  attribute LC_PROBE377_IS_DATA : string;
  attribute LC_PROBE377_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE377_IS_TRIG : string;
  attribute LC_PROBE377_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE377_MU_CNT : integer;
  attribute LC_PROBE377_MU_CNT of U0 : label is 1;
  attribute LC_PROBE377_PID : string;
  attribute LC_PROBE377_PID of U0 : label is "16'b0000000101111001";
  attribute LC_PROBE377_TYPE : integer;
  attribute LC_PROBE377_TYPE of U0 : label is 1;
  attribute LC_PROBE377_WIDTH : integer;
  attribute LC_PROBE377_WIDTH of U0 : label is 1;
  attribute LC_PROBE378_IS_DATA : string;
  attribute LC_PROBE378_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE378_IS_TRIG : string;
  attribute LC_PROBE378_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE378_MU_CNT : integer;
  attribute LC_PROBE378_MU_CNT of U0 : label is 1;
  attribute LC_PROBE378_PID : string;
  attribute LC_PROBE378_PID of U0 : label is "16'b0000000101111010";
  attribute LC_PROBE378_TYPE : integer;
  attribute LC_PROBE378_TYPE of U0 : label is 1;
  attribute LC_PROBE378_WIDTH : integer;
  attribute LC_PROBE378_WIDTH of U0 : label is 1;
  attribute LC_PROBE379_IS_DATA : string;
  attribute LC_PROBE379_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE379_IS_TRIG : string;
  attribute LC_PROBE379_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE379_MU_CNT : integer;
  attribute LC_PROBE379_MU_CNT of U0 : label is 1;
  attribute LC_PROBE379_PID : string;
  attribute LC_PROBE379_PID of U0 : label is "16'b0000000101111011";
  attribute LC_PROBE379_TYPE : integer;
  attribute LC_PROBE379_TYPE of U0 : label is 1;
  attribute LC_PROBE379_WIDTH : integer;
  attribute LC_PROBE379_WIDTH of U0 : label is 1;
  attribute LC_PROBE37_IS_DATA : string;
  attribute LC_PROBE37_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE37_IS_TRIG : string;
  attribute LC_PROBE37_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE37_MU_CNT : integer;
  attribute LC_PROBE37_MU_CNT of U0 : label is 1;
  attribute LC_PROBE37_PID : string;
  attribute LC_PROBE37_PID of U0 : label is "16'b0000000000100101";
  attribute LC_PROBE37_TYPE : integer;
  attribute LC_PROBE37_TYPE of U0 : label is 1;
  attribute LC_PROBE37_WIDTH : integer;
  attribute LC_PROBE37_WIDTH of U0 : label is 1;
  attribute LC_PROBE380_IS_DATA : string;
  attribute LC_PROBE380_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE380_IS_TRIG : string;
  attribute LC_PROBE380_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE380_MU_CNT : integer;
  attribute LC_PROBE380_MU_CNT of U0 : label is 1;
  attribute LC_PROBE380_PID : string;
  attribute LC_PROBE380_PID of U0 : label is "16'b0000000101111100";
  attribute LC_PROBE380_TYPE : integer;
  attribute LC_PROBE380_TYPE of U0 : label is 1;
  attribute LC_PROBE380_WIDTH : integer;
  attribute LC_PROBE380_WIDTH of U0 : label is 1;
  attribute LC_PROBE381_IS_DATA : string;
  attribute LC_PROBE381_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE381_IS_TRIG : string;
  attribute LC_PROBE381_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE381_MU_CNT : integer;
  attribute LC_PROBE381_MU_CNT of U0 : label is 1;
  attribute LC_PROBE381_PID : string;
  attribute LC_PROBE381_PID of U0 : label is "16'b0000000101111101";
  attribute LC_PROBE381_TYPE : integer;
  attribute LC_PROBE381_TYPE of U0 : label is 1;
  attribute LC_PROBE381_WIDTH : integer;
  attribute LC_PROBE381_WIDTH of U0 : label is 1;
  attribute LC_PROBE382_IS_DATA : string;
  attribute LC_PROBE382_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE382_IS_TRIG : string;
  attribute LC_PROBE382_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE382_MU_CNT : integer;
  attribute LC_PROBE382_MU_CNT of U0 : label is 1;
  attribute LC_PROBE382_PID : string;
  attribute LC_PROBE382_PID of U0 : label is "16'b0000000101111110";
  attribute LC_PROBE382_TYPE : integer;
  attribute LC_PROBE382_TYPE of U0 : label is 1;
  attribute LC_PROBE382_WIDTH : integer;
  attribute LC_PROBE382_WIDTH of U0 : label is 1;
  attribute LC_PROBE383_IS_DATA : string;
  attribute LC_PROBE383_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE383_IS_TRIG : string;
  attribute LC_PROBE383_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE383_MU_CNT : integer;
  attribute LC_PROBE383_MU_CNT of U0 : label is 1;
  attribute LC_PROBE383_PID : string;
  attribute LC_PROBE383_PID of U0 : label is "16'b0000000101111111";
  attribute LC_PROBE383_TYPE : integer;
  attribute LC_PROBE383_TYPE of U0 : label is 1;
  attribute LC_PROBE383_WIDTH : integer;
  attribute LC_PROBE383_WIDTH of U0 : label is 1;
  attribute LC_PROBE384_IS_DATA : string;
  attribute LC_PROBE384_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE384_IS_TRIG : string;
  attribute LC_PROBE384_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE384_MU_CNT : integer;
  attribute LC_PROBE384_MU_CNT of U0 : label is 1;
  attribute LC_PROBE384_PID : string;
  attribute LC_PROBE384_PID of U0 : label is "16'b0000000110000000";
  attribute LC_PROBE384_TYPE : integer;
  attribute LC_PROBE384_TYPE of U0 : label is 1;
  attribute LC_PROBE384_WIDTH : integer;
  attribute LC_PROBE384_WIDTH of U0 : label is 1;
  attribute LC_PROBE385_IS_DATA : string;
  attribute LC_PROBE385_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE385_IS_TRIG : string;
  attribute LC_PROBE385_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE385_MU_CNT : integer;
  attribute LC_PROBE385_MU_CNT of U0 : label is 1;
  attribute LC_PROBE385_PID : string;
  attribute LC_PROBE385_PID of U0 : label is "16'b0000000110000001";
  attribute LC_PROBE385_TYPE : integer;
  attribute LC_PROBE385_TYPE of U0 : label is 1;
  attribute LC_PROBE385_WIDTH : integer;
  attribute LC_PROBE385_WIDTH of U0 : label is 1;
  attribute LC_PROBE386_IS_DATA : string;
  attribute LC_PROBE386_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE386_IS_TRIG : string;
  attribute LC_PROBE386_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE386_MU_CNT : integer;
  attribute LC_PROBE386_MU_CNT of U0 : label is 1;
  attribute LC_PROBE386_PID : string;
  attribute LC_PROBE386_PID of U0 : label is "16'b0000000110000010";
  attribute LC_PROBE386_TYPE : integer;
  attribute LC_PROBE386_TYPE of U0 : label is 1;
  attribute LC_PROBE386_WIDTH : integer;
  attribute LC_PROBE386_WIDTH of U0 : label is 1;
  attribute LC_PROBE387_IS_DATA : string;
  attribute LC_PROBE387_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE387_IS_TRIG : string;
  attribute LC_PROBE387_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE387_MU_CNT : integer;
  attribute LC_PROBE387_MU_CNT of U0 : label is 1;
  attribute LC_PROBE387_PID : string;
  attribute LC_PROBE387_PID of U0 : label is "16'b0000000110000011";
  attribute LC_PROBE387_TYPE : integer;
  attribute LC_PROBE387_TYPE of U0 : label is 1;
  attribute LC_PROBE387_WIDTH : integer;
  attribute LC_PROBE387_WIDTH of U0 : label is 1;
  attribute LC_PROBE388_IS_DATA : string;
  attribute LC_PROBE388_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE388_IS_TRIG : string;
  attribute LC_PROBE388_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE388_MU_CNT : integer;
  attribute LC_PROBE388_MU_CNT of U0 : label is 1;
  attribute LC_PROBE388_PID : string;
  attribute LC_PROBE388_PID of U0 : label is "16'b0000000110000100";
  attribute LC_PROBE388_TYPE : integer;
  attribute LC_PROBE388_TYPE of U0 : label is 1;
  attribute LC_PROBE388_WIDTH : integer;
  attribute LC_PROBE388_WIDTH of U0 : label is 1;
  attribute LC_PROBE389_IS_DATA : string;
  attribute LC_PROBE389_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE389_IS_TRIG : string;
  attribute LC_PROBE389_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE389_MU_CNT : integer;
  attribute LC_PROBE389_MU_CNT of U0 : label is 1;
  attribute LC_PROBE389_PID : string;
  attribute LC_PROBE389_PID of U0 : label is "16'b0000000110000101";
  attribute LC_PROBE389_TYPE : integer;
  attribute LC_PROBE389_TYPE of U0 : label is 1;
  attribute LC_PROBE389_WIDTH : integer;
  attribute LC_PROBE389_WIDTH of U0 : label is 1;
  attribute LC_PROBE38_IS_DATA : string;
  attribute LC_PROBE38_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE38_IS_TRIG : string;
  attribute LC_PROBE38_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE38_MU_CNT : integer;
  attribute LC_PROBE38_MU_CNT of U0 : label is 1;
  attribute LC_PROBE38_PID : string;
  attribute LC_PROBE38_PID of U0 : label is "16'b0000000000100110";
  attribute LC_PROBE38_TYPE : integer;
  attribute LC_PROBE38_TYPE of U0 : label is 1;
  attribute LC_PROBE38_WIDTH : integer;
  attribute LC_PROBE38_WIDTH of U0 : label is 1;
  attribute LC_PROBE390_IS_DATA : string;
  attribute LC_PROBE390_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE390_IS_TRIG : string;
  attribute LC_PROBE390_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE390_MU_CNT : integer;
  attribute LC_PROBE390_MU_CNT of U0 : label is 1;
  attribute LC_PROBE390_PID : string;
  attribute LC_PROBE390_PID of U0 : label is "16'b0000000110000110";
  attribute LC_PROBE390_TYPE : integer;
  attribute LC_PROBE390_TYPE of U0 : label is 1;
  attribute LC_PROBE390_WIDTH : integer;
  attribute LC_PROBE390_WIDTH of U0 : label is 1;
  attribute LC_PROBE391_IS_DATA : string;
  attribute LC_PROBE391_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE391_IS_TRIG : string;
  attribute LC_PROBE391_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE391_MU_CNT : integer;
  attribute LC_PROBE391_MU_CNT of U0 : label is 1;
  attribute LC_PROBE391_PID : string;
  attribute LC_PROBE391_PID of U0 : label is "16'b0000000110000111";
  attribute LC_PROBE391_TYPE : integer;
  attribute LC_PROBE391_TYPE of U0 : label is 1;
  attribute LC_PROBE391_WIDTH : integer;
  attribute LC_PROBE391_WIDTH of U0 : label is 1;
  attribute LC_PROBE392_IS_DATA : string;
  attribute LC_PROBE392_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE392_IS_TRIG : string;
  attribute LC_PROBE392_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE392_MU_CNT : integer;
  attribute LC_PROBE392_MU_CNT of U0 : label is 1;
  attribute LC_PROBE392_PID : string;
  attribute LC_PROBE392_PID of U0 : label is "16'b0000000110001000";
  attribute LC_PROBE392_TYPE : integer;
  attribute LC_PROBE392_TYPE of U0 : label is 1;
  attribute LC_PROBE392_WIDTH : integer;
  attribute LC_PROBE392_WIDTH of U0 : label is 1;
  attribute LC_PROBE393_IS_DATA : string;
  attribute LC_PROBE393_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE393_IS_TRIG : string;
  attribute LC_PROBE393_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE393_MU_CNT : integer;
  attribute LC_PROBE393_MU_CNT of U0 : label is 1;
  attribute LC_PROBE393_PID : string;
  attribute LC_PROBE393_PID of U0 : label is "16'b0000000110001001";
  attribute LC_PROBE393_TYPE : integer;
  attribute LC_PROBE393_TYPE of U0 : label is 1;
  attribute LC_PROBE393_WIDTH : integer;
  attribute LC_PROBE393_WIDTH of U0 : label is 1;
  attribute LC_PROBE394_IS_DATA : string;
  attribute LC_PROBE394_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE394_IS_TRIG : string;
  attribute LC_PROBE394_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE394_MU_CNT : integer;
  attribute LC_PROBE394_MU_CNT of U0 : label is 1;
  attribute LC_PROBE394_PID : string;
  attribute LC_PROBE394_PID of U0 : label is "16'b0000000110001010";
  attribute LC_PROBE394_TYPE : integer;
  attribute LC_PROBE394_TYPE of U0 : label is 1;
  attribute LC_PROBE394_WIDTH : integer;
  attribute LC_PROBE394_WIDTH of U0 : label is 1;
  attribute LC_PROBE395_IS_DATA : string;
  attribute LC_PROBE395_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE395_IS_TRIG : string;
  attribute LC_PROBE395_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE395_MU_CNT : integer;
  attribute LC_PROBE395_MU_CNT of U0 : label is 1;
  attribute LC_PROBE395_PID : string;
  attribute LC_PROBE395_PID of U0 : label is "16'b0000000110001011";
  attribute LC_PROBE395_TYPE : integer;
  attribute LC_PROBE395_TYPE of U0 : label is 1;
  attribute LC_PROBE395_WIDTH : integer;
  attribute LC_PROBE395_WIDTH of U0 : label is 1;
  attribute LC_PROBE396_IS_DATA : string;
  attribute LC_PROBE396_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE396_IS_TRIG : string;
  attribute LC_PROBE396_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE396_MU_CNT : integer;
  attribute LC_PROBE396_MU_CNT of U0 : label is 1;
  attribute LC_PROBE396_PID : string;
  attribute LC_PROBE396_PID of U0 : label is "16'b0000000110001100";
  attribute LC_PROBE396_TYPE : integer;
  attribute LC_PROBE396_TYPE of U0 : label is 1;
  attribute LC_PROBE396_WIDTH : integer;
  attribute LC_PROBE396_WIDTH of U0 : label is 1;
  attribute LC_PROBE397_IS_DATA : string;
  attribute LC_PROBE397_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE397_IS_TRIG : string;
  attribute LC_PROBE397_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE397_MU_CNT : integer;
  attribute LC_PROBE397_MU_CNT of U0 : label is 1;
  attribute LC_PROBE397_PID : string;
  attribute LC_PROBE397_PID of U0 : label is "16'b0000000110001101";
  attribute LC_PROBE397_TYPE : integer;
  attribute LC_PROBE397_TYPE of U0 : label is 1;
  attribute LC_PROBE397_WIDTH : integer;
  attribute LC_PROBE397_WIDTH of U0 : label is 1;
  attribute LC_PROBE398_IS_DATA : string;
  attribute LC_PROBE398_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE398_IS_TRIG : string;
  attribute LC_PROBE398_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE398_MU_CNT : integer;
  attribute LC_PROBE398_MU_CNT of U0 : label is 1;
  attribute LC_PROBE398_PID : string;
  attribute LC_PROBE398_PID of U0 : label is "16'b0000000110001110";
  attribute LC_PROBE398_TYPE : integer;
  attribute LC_PROBE398_TYPE of U0 : label is 1;
  attribute LC_PROBE398_WIDTH : integer;
  attribute LC_PROBE398_WIDTH of U0 : label is 1;
  attribute LC_PROBE399_IS_DATA : string;
  attribute LC_PROBE399_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE399_IS_TRIG : string;
  attribute LC_PROBE399_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE399_MU_CNT : integer;
  attribute LC_PROBE399_MU_CNT of U0 : label is 1;
  attribute LC_PROBE399_PID : string;
  attribute LC_PROBE399_PID of U0 : label is "16'b0000000110001111";
  attribute LC_PROBE399_TYPE : integer;
  attribute LC_PROBE399_TYPE of U0 : label is 1;
  attribute LC_PROBE399_WIDTH : integer;
  attribute LC_PROBE399_WIDTH of U0 : label is 1;
  attribute LC_PROBE39_IS_DATA : string;
  attribute LC_PROBE39_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE39_IS_TRIG : string;
  attribute LC_PROBE39_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE39_MU_CNT : integer;
  attribute LC_PROBE39_MU_CNT of U0 : label is 1;
  attribute LC_PROBE39_PID : string;
  attribute LC_PROBE39_PID of U0 : label is "16'b0000000000100111";
  attribute LC_PROBE39_TYPE : integer;
  attribute LC_PROBE39_TYPE of U0 : label is 1;
  attribute LC_PROBE39_WIDTH : integer;
  attribute LC_PROBE39_WIDTH of U0 : label is 1;
  attribute LC_PROBE3_IS_DATA : string;
  attribute LC_PROBE3_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE3_IS_TRIG : string;
  attribute LC_PROBE3_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE3_MU_CNT : integer;
  attribute LC_PROBE3_MU_CNT of U0 : label is 1;
  attribute LC_PROBE3_PID : string;
  attribute LC_PROBE3_PID of U0 : label is "16'b0000000000000011";
  attribute LC_PROBE3_TYPE : integer;
  attribute LC_PROBE3_TYPE of U0 : label is 0;
  attribute LC_PROBE3_WIDTH : integer;
  attribute LC_PROBE3_WIDTH of U0 : label is 8;
  attribute LC_PROBE400_IS_DATA : string;
  attribute LC_PROBE400_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE400_IS_TRIG : string;
  attribute LC_PROBE400_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE400_MU_CNT : integer;
  attribute LC_PROBE400_MU_CNT of U0 : label is 1;
  attribute LC_PROBE400_PID : string;
  attribute LC_PROBE400_PID of U0 : label is "16'b0000000110010000";
  attribute LC_PROBE400_TYPE : integer;
  attribute LC_PROBE400_TYPE of U0 : label is 1;
  attribute LC_PROBE400_WIDTH : integer;
  attribute LC_PROBE400_WIDTH of U0 : label is 1;
  attribute LC_PROBE401_IS_DATA : string;
  attribute LC_PROBE401_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE401_IS_TRIG : string;
  attribute LC_PROBE401_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE401_MU_CNT : integer;
  attribute LC_PROBE401_MU_CNT of U0 : label is 1;
  attribute LC_PROBE401_PID : string;
  attribute LC_PROBE401_PID of U0 : label is "16'b0000000110010001";
  attribute LC_PROBE401_TYPE : integer;
  attribute LC_PROBE401_TYPE of U0 : label is 1;
  attribute LC_PROBE401_WIDTH : integer;
  attribute LC_PROBE401_WIDTH of U0 : label is 1;
  attribute LC_PROBE402_IS_DATA : string;
  attribute LC_PROBE402_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE402_IS_TRIG : string;
  attribute LC_PROBE402_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE402_MU_CNT : integer;
  attribute LC_PROBE402_MU_CNT of U0 : label is 1;
  attribute LC_PROBE402_PID : string;
  attribute LC_PROBE402_PID of U0 : label is "16'b0000000110010010";
  attribute LC_PROBE402_TYPE : integer;
  attribute LC_PROBE402_TYPE of U0 : label is 1;
  attribute LC_PROBE402_WIDTH : integer;
  attribute LC_PROBE402_WIDTH of U0 : label is 1;
  attribute LC_PROBE403_IS_DATA : string;
  attribute LC_PROBE403_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE403_IS_TRIG : string;
  attribute LC_PROBE403_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE403_MU_CNT : integer;
  attribute LC_PROBE403_MU_CNT of U0 : label is 1;
  attribute LC_PROBE403_PID : string;
  attribute LC_PROBE403_PID of U0 : label is "16'b0000000110010011";
  attribute LC_PROBE403_TYPE : integer;
  attribute LC_PROBE403_TYPE of U0 : label is 1;
  attribute LC_PROBE403_WIDTH : integer;
  attribute LC_PROBE403_WIDTH of U0 : label is 1;
  attribute LC_PROBE404_IS_DATA : string;
  attribute LC_PROBE404_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE404_IS_TRIG : string;
  attribute LC_PROBE404_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE404_MU_CNT : integer;
  attribute LC_PROBE404_MU_CNT of U0 : label is 1;
  attribute LC_PROBE404_PID : string;
  attribute LC_PROBE404_PID of U0 : label is "16'b0000000110010100";
  attribute LC_PROBE404_TYPE : integer;
  attribute LC_PROBE404_TYPE of U0 : label is 1;
  attribute LC_PROBE404_WIDTH : integer;
  attribute LC_PROBE404_WIDTH of U0 : label is 1;
  attribute LC_PROBE405_IS_DATA : string;
  attribute LC_PROBE405_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE405_IS_TRIG : string;
  attribute LC_PROBE405_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE405_MU_CNT : integer;
  attribute LC_PROBE405_MU_CNT of U0 : label is 1;
  attribute LC_PROBE405_PID : string;
  attribute LC_PROBE405_PID of U0 : label is "16'b0000000110010101";
  attribute LC_PROBE405_TYPE : integer;
  attribute LC_PROBE405_TYPE of U0 : label is 1;
  attribute LC_PROBE405_WIDTH : integer;
  attribute LC_PROBE405_WIDTH of U0 : label is 1;
  attribute LC_PROBE406_IS_DATA : string;
  attribute LC_PROBE406_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE406_IS_TRIG : string;
  attribute LC_PROBE406_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE406_MU_CNT : integer;
  attribute LC_PROBE406_MU_CNT of U0 : label is 1;
  attribute LC_PROBE406_PID : string;
  attribute LC_PROBE406_PID of U0 : label is "16'b0000000110010110";
  attribute LC_PROBE406_TYPE : integer;
  attribute LC_PROBE406_TYPE of U0 : label is 1;
  attribute LC_PROBE406_WIDTH : integer;
  attribute LC_PROBE406_WIDTH of U0 : label is 1;
  attribute LC_PROBE407_IS_DATA : string;
  attribute LC_PROBE407_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE407_IS_TRIG : string;
  attribute LC_PROBE407_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE407_MU_CNT : integer;
  attribute LC_PROBE407_MU_CNT of U0 : label is 1;
  attribute LC_PROBE407_PID : string;
  attribute LC_PROBE407_PID of U0 : label is "16'b0000000110010111";
  attribute LC_PROBE407_TYPE : integer;
  attribute LC_PROBE407_TYPE of U0 : label is 1;
  attribute LC_PROBE407_WIDTH : integer;
  attribute LC_PROBE407_WIDTH of U0 : label is 1;
  attribute LC_PROBE408_IS_DATA : string;
  attribute LC_PROBE408_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE408_IS_TRIG : string;
  attribute LC_PROBE408_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE408_MU_CNT : integer;
  attribute LC_PROBE408_MU_CNT of U0 : label is 1;
  attribute LC_PROBE408_PID : string;
  attribute LC_PROBE408_PID of U0 : label is "16'b0000000110011000";
  attribute LC_PROBE408_TYPE : integer;
  attribute LC_PROBE408_TYPE of U0 : label is 1;
  attribute LC_PROBE408_WIDTH : integer;
  attribute LC_PROBE408_WIDTH of U0 : label is 1;
  attribute LC_PROBE409_IS_DATA : string;
  attribute LC_PROBE409_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE409_IS_TRIG : string;
  attribute LC_PROBE409_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE409_MU_CNT : integer;
  attribute LC_PROBE409_MU_CNT of U0 : label is 1;
  attribute LC_PROBE409_PID : string;
  attribute LC_PROBE409_PID of U0 : label is "16'b0000000110011001";
  attribute LC_PROBE409_TYPE : integer;
  attribute LC_PROBE409_TYPE of U0 : label is 1;
  attribute LC_PROBE409_WIDTH : integer;
  attribute LC_PROBE409_WIDTH of U0 : label is 1;
  attribute LC_PROBE40_IS_DATA : string;
  attribute LC_PROBE40_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE40_IS_TRIG : string;
  attribute LC_PROBE40_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE40_MU_CNT : integer;
  attribute LC_PROBE40_MU_CNT of U0 : label is 1;
  attribute LC_PROBE40_PID : string;
  attribute LC_PROBE40_PID of U0 : label is "16'b0000000000101000";
  attribute LC_PROBE40_TYPE : integer;
  attribute LC_PROBE40_TYPE of U0 : label is 1;
  attribute LC_PROBE40_WIDTH : integer;
  attribute LC_PROBE40_WIDTH of U0 : label is 1;
  attribute LC_PROBE410_IS_DATA : string;
  attribute LC_PROBE410_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE410_IS_TRIG : string;
  attribute LC_PROBE410_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE410_MU_CNT : integer;
  attribute LC_PROBE410_MU_CNT of U0 : label is 1;
  attribute LC_PROBE410_PID : string;
  attribute LC_PROBE410_PID of U0 : label is "16'b0000000110011010";
  attribute LC_PROBE410_TYPE : integer;
  attribute LC_PROBE410_TYPE of U0 : label is 1;
  attribute LC_PROBE410_WIDTH : integer;
  attribute LC_PROBE410_WIDTH of U0 : label is 1;
  attribute LC_PROBE411_IS_DATA : string;
  attribute LC_PROBE411_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE411_IS_TRIG : string;
  attribute LC_PROBE411_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE411_MU_CNT : integer;
  attribute LC_PROBE411_MU_CNT of U0 : label is 1;
  attribute LC_PROBE411_PID : string;
  attribute LC_PROBE411_PID of U0 : label is "16'b0000000110011011";
  attribute LC_PROBE411_TYPE : integer;
  attribute LC_PROBE411_TYPE of U0 : label is 1;
  attribute LC_PROBE411_WIDTH : integer;
  attribute LC_PROBE411_WIDTH of U0 : label is 1;
  attribute LC_PROBE412_IS_DATA : string;
  attribute LC_PROBE412_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE412_IS_TRIG : string;
  attribute LC_PROBE412_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE412_MU_CNT : integer;
  attribute LC_PROBE412_MU_CNT of U0 : label is 1;
  attribute LC_PROBE412_PID : string;
  attribute LC_PROBE412_PID of U0 : label is "16'b0000000110011100";
  attribute LC_PROBE412_TYPE : integer;
  attribute LC_PROBE412_TYPE of U0 : label is 1;
  attribute LC_PROBE412_WIDTH : integer;
  attribute LC_PROBE412_WIDTH of U0 : label is 1;
  attribute LC_PROBE413_IS_DATA : string;
  attribute LC_PROBE413_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE413_IS_TRIG : string;
  attribute LC_PROBE413_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE413_MU_CNT : integer;
  attribute LC_PROBE413_MU_CNT of U0 : label is 1;
  attribute LC_PROBE413_PID : string;
  attribute LC_PROBE413_PID of U0 : label is "16'b0000000110011101";
  attribute LC_PROBE413_TYPE : integer;
  attribute LC_PROBE413_TYPE of U0 : label is 1;
  attribute LC_PROBE413_WIDTH : integer;
  attribute LC_PROBE413_WIDTH of U0 : label is 1;
  attribute LC_PROBE414_IS_DATA : string;
  attribute LC_PROBE414_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE414_IS_TRIG : string;
  attribute LC_PROBE414_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE414_MU_CNT : integer;
  attribute LC_PROBE414_MU_CNT of U0 : label is 1;
  attribute LC_PROBE414_PID : string;
  attribute LC_PROBE414_PID of U0 : label is "16'b0000000110011110";
  attribute LC_PROBE414_TYPE : integer;
  attribute LC_PROBE414_TYPE of U0 : label is 1;
  attribute LC_PROBE414_WIDTH : integer;
  attribute LC_PROBE414_WIDTH of U0 : label is 1;
  attribute LC_PROBE415_IS_DATA : string;
  attribute LC_PROBE415_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE415_IS_TRIG : string;
  attribute LC_PROBE415_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE415_MU_CNT : integer;
  attribute LC_PROBE415_MU_CNT of U0 : label is 1;
  attribute LC_PROBE415_PID : string;
  attribute LC_PROBE415_PID of U0 : label is "16'b0000000110011111";
  attribute LC_PROBE415_TYPE : integer;
  attribute LC_PROBE415_TYPE of U0 : label is 1;
  attribute LC_PROBE415_WIDTH : integer;
  attribute LC_PROBE415_WIDTH of U0 : label is 1;
  attribute LC_PROBE416_IS_DATA : string;
  attribute LC_PROBE416_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE416_IS_TRIG : string;
  attribute LC_PROBE416_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE416_MU_CNT : integer;
  attribute LC_PROBE416_MU_CNT of U0 : label is 1;
  attribute LC_PROBE416_PID : string;
  attribute LC_PROBE416_PID of U0 : label is "16'b0000000110100000";
  attribute LC_PROBE416_TYPE : integer;
  attribute LC_PROBE416_TYPE of U0 : label is 1;
  attribute LC_PROBE416_WIDTH : integer;
  attribute LC_PROBE416_WIDTH of U0 : label is 1;
  attribute LC_PROBE417_IS_DATA : string;
  attribute LC_PROBE417_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE417_IS_TRIG : string;
  attribute LC_PROBE417_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE417_MU_CNT : integer;
  attribute LC_PROBE417_MU_CNT of U0 : label is 1;
  attribute LC_PROBE417_PID : string;
  attribute LC_PROBE417_PID of U0 : label is "16'b0000000110100001";
  attribute LC_PROBE417_TYPE : integer;
  attribute LC_PROBE417_TYPE of U0 : label is 1;
  attribute LC_PROBE417_WIDTH : integer;
  attribute LC_PROBE417_WIDTH of U0 : label is 1;
  attribute LC_PROBE418_IS_DATA : string;
  attribute LC_PROBE418_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE418_IS_TRIG : string;
  attribute LC_PROBE418_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE418_MU_CNT : integer;
  attribute LC_PROBE418_MU_CNT of U0 : label is 1;
  attribute LC_PROBE418_PID : string;
  attribute LC_PROBE418_PID of U0 : label is "16'b0000000110100010";
  attribute LC_PROBE418_TYPE : integer;
  attribute LC_PROBE418_TYPE of U0 : label is 1;
  attribute LC_PROBE418_WIDTH : integer;
  attribute LC_PROBE418_WIDTH of U0 : label is 1;
  attribute LC_PROBE419_IS_DATA : string;
  attribute LC_PROBE419_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE419_IS_TRIG : string;
  attribute LC_PROBE419_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE419_MU_CNT : integer;
  attribute LC_PROBE419_MU_CNT of U0 : label is 1;
  attribute LC_PROBE419_PID : string;
  attribute LC_PROBE419_PID of U0 : label is "16'b0000000110100011";
  attribute LC_PROBE419_TYPE : integer;
  attribute LC_PROBE419_TYPE of U0 : label is 1;
  attribute LC_PROBE419_WIDTH : integer;
  attribute LC_PROBE419_WIDTH of U0 : label is 1;
  attribute LC_PROBE41_IS_DATA : string;
  attribute LC_PROBE41_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE41_IS_TRIG : string;
  attribute LC_PROBE41_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE41_MU_CNT : integer;
  attribute LC_PROBE41_MU_CNT of U0 : label is 1;
  attribute LC_PROBE41_PID : string;
  attribute LC_PROBE41_PID of U0 : label is "16'b0000000000101001";
  attribute LC_PROBE41_TYPE : integer;
  attribute LC_PROBE41_TYPE of U0 : label is 1;
  attribute LC_PROBE41_WIDTH : integer;
  attribute LC_PROBE41_WIDTH of U0 : label is 1;
  attribute LC_PROBE420_IS_DATA : string;
  attribute LC_PROBE420_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE420_IS_TRIG : string;
  attribute LC_PROBE420_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE420_MU_CNT : integer;
  attribute LC_PROBE420_MU_CNT of U0 : label is 1;
  attribute LC_PROBE420_PID : string;
  attribute LC_PROBE420_PID of U0 : label is "16'b0000000110100100";
  attribute LC_PROBE420_TYPE : integer;
  attribute LC_PROBE420_TYPE of U0 : label is 1;
  attribute LC_PROBE420_WIDTH : integer;
  attribute LC_PROBE420_WIDTH of U0 : label is 1;
  attribute LC_PROBE421_IS_DATA : string;
  attribute LC_PROBE421_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE421_IS_TRIG : string;
  attribute LC_PROBE421_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE421_MU_CNT : integer;
  attribute LC_PROBE421_MU_CNT of U0 : label is 1;
  attribute LC_PROBE421_PID : string;
  attribute LC_PROBE421_PID of U0 : label is "16'b0000000110100101";
  attribute LC_PROBE421_TYPE : integer;
  attribute LC_PROBE421_TYPE of U0 : label is 1;
  attribute LC_PROBE421_WIDTH : integer;
  attribute LC_PROBE421_WIDTH of U0 : label is 1;
  attribute LC_PROBE422_IS_DATA : string;
  attribute LC_PROBE422_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE422_IS_TRIG : string;
  attribute LC_PROBE422_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE422_MU_CNT : integer;
  attribute LC_PROBE422_MU_CNT of U0 : label is 1;
  attribute LC_PROBE422_PID : string;
  attribute LC_PROBE422_PID of U0 : label is "16'b0000000110100110";
  attribute LC_PROBE422_TYPE : integer;
  attribute LC_PROBE422_TYPE of U0 : label is 1;
  attribute LC_PROBE422_WIDTH : integer;
  attribute LC_PROBE422_WIDTH of U0 : label is 1;
  attribute LC_PROBE423_IS_DATA : string;
  attribute LC_PROBE423_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE423_IS_TRIG : string;
  attribute LC_PROBE423_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE423_MU_CNT : integer;
  attribute LC_PROBE423_MU_CNT of U0 : label is 1;
  attribute LC_PROBE423_PID : string;
  attribute LC_PROBE423_PID of U0 : label is "16'b0000000110100111";
  attribute LC_PROBE423_TYPE : integer;
  attribute LC_PROBE423_TYPE of U0 : label is 1;
  attribute LC_PROBE423_WIDTH : integer;
  attribute LC_PROBE423_WIDTH of U0 : label is 1;
  attribute LC_PROBE424_IS_DATA : string;
  attribute LC_PROBE424_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE424_IS_TRIG : string;
  attribute LC_PROBE424_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE424_MU_CNT : integer;
  attribute LC_PROBE424_MU_CNT of U0 : label is 1;
  attribute LC_PROBE424_PID : string;
  attribute LC_PROBE424_PID of U0 : label is "16'b0000000110101000";
  attribute LC_PROBE424_TYPE : integer;
  attribute LC_PROBE424_TYPE of U0 : label is 1;
  attribute LC_PROBE424_WIDTH : integer;
  attribute LC_PROBE424_WIDTH of U0 : label is 1;
  attribute LC_PROBE425_IS_DATA : string;
  attribute LC_PROBE425_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE425_IS_TRIG : string;
  attribute LC_PROBE425_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE425_MU_CNT : integer;
  attribute LC_PROBE425_MU_CNT of U0 : label is 1;
  attribute LC_PROBE425_PID : string;
  attribute LC_PROBE425_PID of U0 : label is "16'b0000000110101001";
  attribute LC_PROBE425_TYPE : integer;
  attribute LC_PROBE425_TYPE of U0 : label is 1;
  attribute LC_PROBE425_WIDTH : integer;
  attribute LC_PROBE425_WIDTH of U0 : label is 1;
  attribute LC_PROBE426_IS_DATA : string;
  attribute LC_PROBE426_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE426_IS_TRIG : string;
  attribute LC_PROBE426_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE426_MU_CNT : integer;
  attribute LC_PROBE426_MU_CNT of U0 : label is 1;
  attribute LC_PROBE426_PID : string;
  attribute LC_PROBE426_PID of U0 : label is "16'b0000000110101010";
  attribute LC_PROBE426_TYPE : integer;
  attribute LC_PROBE426_TYPE of U0 : label is 1;
  attribute LC_PROBE426_WIDTH : integer;
  attribute LC_PROBE426_WIDTH of U0 : label is 1;
  attribute LC_PROBE427_IS_DATA : string;
  attribute LC_PROBE427_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE427_IS_TRIG : string;
  attribute LC_PROBE427_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE427_MU_CNT : integer;
  attribute LC_PROBE427_MU_CNT of U0 : label is 1;
  attribute LC_PROBE427_PID : string;
  attribute LC_PROBE427_PID of U0 : label is "16'b0000000110101011";
  attribute LC_PROBE427_TYPE : integer;
  attribute LC_PROBE427_TYPE of U0 : label is 1;
  attribute LC_PROBE427_WIDTH : integer;
  attribute LC_PROBE427_WIDTH of U0 : label is 1;
  attribute LC_PROBE428_IS_DATA : string;
  attribute LC_PROBE428_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE428_IS_TRIG : string;
  attribute LC_PROBE428_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE428_MU_CNT : integer;
  attribute LC_PROBE428_MU_CNT of U0 : label is 1;
  attribute LC_PROBE428_PID : string;
  attribute LC_PROBE428_PID of U0 : label is "16'b0000000110101100";
  attribute LC_PROBE428_TYPE : integer;
  attribute LC_PROBE428_TYPE of U0 : label is 1;
  attribute LC_PROBE428_WIDTH : integer;
  attribute LC_PROBE428_WIDTH of U0 : label is 1;
  attribute LC_PROBE429_IS_DATA : string;
  attribute LC_PROBE429_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE429_IS_TRIG : string;
  attribute LC_PROBE429_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE429_MU_CNT : integer;
  attribute LC_PROBE429_MU_CNT of U0 : label is 1;
  attribute LC_PROBE429_PID : string;
  attribute LC_PROBE429_PID of U0 : label is "16'b0000000110101101";
  attribute LC_PROBE429_TYPE : integer;
  attribute LC_PROBE429_TYPE of U0 : label is 1;
  attribute LC_PROBE429_WIDTH : integer;
  attribute LC_PROBE429_WIDTH of U0 : label is 1;
  attribute LC_PROBE42_IS_DATA : string;
  attribute LC_PROBE42_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE42_IS_TRIG : string;
  attribute LC_PROBE42_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE42_MU_CNT : integer;
  attribute LC_PROBE42_MU_CNT of U0 : label is 1;
  attribute LC_PROBE42_PID : string;
  attribute LC_PROBE42_PID of U0 : label is "16'b0000000000101010";
  attribute LC_PROBE42_TYPE : integer;
  attribute LC_PROBE42_TYPE of U0 : label is 1;
  attribute LC_PROBE42_WIDTH : integer;
  attribute LC_PROBE42_WIDTH of U0 : label is 1;
  attribute LC_PROBE430_IS_DATA : string;
  attribute LC_PROBE430_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE430_IS_TRIG : string;
  attribute LC_PROBE430_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE430_MU_CNT : integer;
  attribute LC_PROBE430_MU_CNT of U0 : label is 1;
  attribute LC_PROBE430_PID : string;
  attribute LC_PROBE430_PID of U0 : label is "16'b0000000110101110";
  attribute LC_PROBE430_TYPE : integer;
  attribute LC_PROBE430_TYPE of U0 : label is 1;
  attribute LC_PROBE430_WIDTH : integer;
  attribute LC_PROBE430_WIDTH of U0 : label is 1;
  attribute LC_PROBE431_IS_DATA : string;
  attribute LC_PROBE431_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE431_IS_TRIG : string;
  attribute LC_PROBE431_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE431_MU_CNT : integer;
  attribute LC_PROBE431_MU_CNT of U0 : label is 1;
  attribute LC_PROBE431_PID : string;
  attribute LC_PROBE431_PID of U0 : label is "16'b0000000110101111";
  attribute LC_PROBE431_TYPE : integer;
  attribute LC_PROBE431_TYPE of U0 : label is 1;
  attribute LC_PROBE431_WIDTH : integer;
  attribute LC_PROBE431_WIDTH of U0 : label is 1;
  attribute LC_PROBE432_IS_DATA : string;
  attribute LC_PROBE432_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE432_IS_TRIG : string;
  attribute LC_PROBE432_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE432_MU_CNT : integer;
  attribute LC_PROBE432_MU_CNT of U0 : label is 1;
  attribute LC_PROBE432_PID : string;
  attribute LC_PROBE432_PID of U0 : label is "16'b0000000110110000";
  attribute LC_PROBE432_TYPE : integer;
  attribute LC_PROBE432_TYPE of U0 : label is 1;
  attribute LC_PROBE432_WIDTH : integer;
  attribute LC_PROBE432_WIDTH of U0 : label is 1;
  attribute LC_PROBE433_IS_DATA : string;
  attribute LC_PROBE433_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE433_IS_TRIG : string;
  attribute LC_PROBE433_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE433_MU_CNT : integer;
  attribute LC_PROBE433_MU_CNT of U0 : label is 1;
  attribute LC_PROBE433_PID : string;
  attribute LC_PROBE433_PID of U0 : label is "16'b0000000110110001";
  attribute LC_PROBE433_TYPE : integer;
  attribute LC_PROBE433_TYPE of U0 : label is 1;
  attribute LC_PROBE433_WIDTH : integer;
  attribute LC_PROBE433_WIDTH of U0 : label is 1;
  attribute LC_PROBE434_IS_DATA : string;
  attribute LC_PROBE434_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE434_IS_TRIG : string;
  attribute LC_PROBE434_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE434_MU_CNT : integer;
  attribute LC_PROBE434_MU_CNT of U0 : label is 1;
  attribute LC_PROBE434_PID : string;
  attribute LC_PROBE434_PID of U0 : label is "16'b0000000110110010";
  attribute LC_PROBE434_TYPE : integer;
  attribute LC_PROBE434_TYPE of U0 : label is 1;
  attribute LC_PROBE434_WIDTH : integer;
  attribute LC_PROBE434_WIDTH of U0 : label is 1;
  attribute LC_PROBE435_IS_DATA : string;
  attribute LC_PROBE435_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE435_IS_TRIG : string;
  attribute LC_PROBE435_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE435_MU_CNT : integer;
  attribute LC_PROBE435_MU_CNT of U0 : label is 1;
  attribute LC_PROBE435_PID : string;
  attribute LC_PROBE435_PID of U0 : label is "16'b0000000110110011";
  attribute LC_PROBE435_TYPE : integer;
  attribute LC_PROBE435_TYPE of U0 : label is 1;
  attribute LC_PROBE435_WIDTH : integer;
  attribute LC_PROBE435_WIDTH of U0 : label is 1;
  attribute LC_PROBE436_IS_DATA : string;
  attribute LC_PROBE436_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE436_IS_TRIG : string;
  attribute LC_PROBE436_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE436_MU_CNT : integer;
  attribute LC_PROBE436_MU_CNT of U0 : label is 1;
  attribute LC_PROBE436_PID : string;
  attribute LC_PROBE436_PID of U0 : label is "16'b0000000110110100";
  attribute LC_PROBE436_TYPE : integer;
  attribute LC_PROBE436_TYPE of U0 : label is 1;
  attribute LC_PROBE436_WIDTH : integer;
  attribute LC_PROBE436_WIDTH of U0 : label is 1;
  attribute LC_PROBE437_IS_DATA : string;
  attribute LC_PROBE437_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE437_IS_TRIG : string;
  attribute LC_PROBE437_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE437_MU_CNT : integer;
  attribute LC_PROBE437_MU_CNT of U0 : label is 1;
  attribute LC_PROBE437_PID : string;
  attribute LC_PROBE437_PID of U0 : label is "16'b0000000110110101";
  attribute LC_PROBE437_TYPE : integer;
  attribute LC_PROBE437_TYPE of U0 : label is 1;
  attribute LC_PROBE437_WIDTH : integer;
  attribute LC_PROBE437_WIDTH of U0 : label is 1;
  attribute LC_PROBE438_IS_DATA : string;
  attribute LC_PROBE438_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE438_IS_TRIG : string;
  attribute LC_PROBE438_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE438_MU_CNT : integer;
  attribute LC_PROBE438_MU_CNT of U0 : label is 1;
  attribute LC_PROBE438_PID : string;
  attribute LC_PROBE438_PID of U0 : label is "16'b0000000110110110";
  attribute LC_PROBE438_TYPE : integer;
  attribute LC_PROBE438_TYPE of U0 : label is 1;
  attribute LC_PROBE438_WIDTH : integer;
  attribute LC_PROBE438_WIDTH of U0 : label is 1;
  attribute LC_PROBE439_IS_DATA : string;
  attribute LC_PROBE439_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE439_IS_TRIG : string;
  attribute LC_PROBE439_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE439_MU_CNT : integer;
  attribute LC_PROBE439_MU_CNT of U0 : label is 1;
  attribute LC_PROBE439_PID : string;
  attribute LC_PROBE439_PID of U0 : label is "16'b0000000110110111";
  attribute LC_PROBE439_TYPE : integer;
  attribute LC_PROBE439_TYPE of U0 : label is 1;
  attribute LC_PROBE439_WIDTH : integer;
  attribute LC_PROBE439_WIDTH of U0 : label is 1;
  attribute LC_PROBE43_IS_DATA : string;
  attribute LC_PROBE43_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE43_IS_TRIG : string;
  attribute LC_PROBE43_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE43_MU_CNT : integer;
  attribute LC_PROBE43_MU_CNT of U0 : label is 1;
  attribute LC_PROBE43_PID : string;
  attribute LC_PROBE43_PID of U0 : label is "16'b0000000000101011";
  attribute LC_PROBE43_TYPE : integer;
  attribute LC_PROBE43_TYPE of U0 : label is 1;
  attribute LC_PROBE43_WIDTH : integer;
  attribute LC_PROBE43_WIDTH of U0 : label is 1;
  attribute LC_PROBE440_IS_DATA : string;
  attribute LC_PROBE440_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE440_IS_TRIG : string;
  attribute LC_PROBE440_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE440_MU_CNT : integer;
  attribute LC_PROBE440_MU_CNT of U0 : label is 1;
  attribute LC_PROBE440_PID : string;
  attribute LC_PROBE440_PID of U0 : label is "16'b0000000110111000";
  attribute LC_PROBE440_TYPE : integer;
  attribute LC_PROBE440_TYPE of U0 : label is 1;
  attribute LC_PROBE440_WIDTH : integer;
  attribute LC_PROBE440_WIDTH of U0 : label is 1;
  attribute LC_PROBE441_IS_DATA : string;
  attribute LC_PROBE441_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE441_IS_TRIG : string;
  attribute LC_PROBE441_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE441_MU_CNT : integer;
  attribute LC_PROBE441_MU_CNT of U0 : label is 1;
  attribute LC_PROBE441_PID : string;
  attribute LC_PROBE441_PID of U0 : label is "16'b0000000110111001";
  attribute LC_PROBE441_TYPE : integer;
  attribute LC_PROBE441_TYPE of U0 : label is 1;
  attribute LC_PROBE441_WIDTH : integer;
  attribute LC_PROBE441_WIDTH of U0 : label is 1;
  attribute LC_PROBE442_IS_DATA : string;
  attribute LC_PROBE442_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE442_IS_TRIG : string;
  attribute LC_PROBE442_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE442_MU_CNT : integer;
  attribute LC_PROBE442_MU_CNT of U0 : label is 1;
  attribute LC_PROBE442_PID : string;
  attribute LC_PROBE442_PID of U0 : label is "16'b0000000110111010";
  attribute LC_PROBE442_TYPE : integer;
  attribute LC_PROBE442_TYPE of U0 : label is 1;
  attribute LC_PROBE442_WIDTH : integer;
  attribute LC_PROBE442_WIDTH of U0 : label is 1;
  attribute LC_PROBE443_IS_DATA : string;
  attribute LC_PROBE443_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE443_IS_TRIG : string;
  attribute LC_PROBE443_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE443_MU_CNT : integer;
  attribute LC_PROBE443_MU_CNT of U0 : label is 1;
  attribute LC_PROBE443_PID : string;
  attribute LC_PROBE443_PID of U0 : label is "16'b0000000110111011";
  attribute LC_PROBE443_TYPE : integer;
  attribute LC_PROBE443_TYPE of U0 : label is 1;
  attribute LC_PROBE443_WIDTH : integer;
  attribute LC_PROBE443_WIDTH of U0 : label is 1;
  attribute LC_PROBE444_IS_DATA : string;
  attribute LC_PROBE444_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE444_IS_TRIG : string;
  attribute LC_PROBE444_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE444_MU_CNT : integer;
  attribute LC_PROBE444_MU_CNT of U0 : label is 1;
  attribute LC_PROBE444_PID : string;
  attribute LC_PROBE444_PID of U0 : label is "16'b0000000110111100";
  attribute LC_PROBE444_TYPE : integer;
  attribute LC_PROBE444_TYPE of U0 : label is 1;
  attribute LC_PROBE444_WIDTH : integer;
  attribute LC_PROBE444_WIDTH of U0 : label is 1;
  attribute LC_PROBE445_IS_DATA : string;
  attribute LC_PROBE445_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE445_IS_TRIG : string;
  attribute LC_PROBE445_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE445_MU_CNT : integer;
  attribute LC_PROBE445_MU_CNT of U0 : label is 1;
  attribute LC_PROBE445_PID : string;
  attribute LC_PROBE445_PID of U0 : label is "16'b0000000110111101";
  attribute LC_PROBE445_TYPE : integer;
  attribute LC_PROBE445_TYPE of U0 : label is 1;
  attribute LC_PROBE445_WIDTH : integer;
  attribute LC_PROBE445_WIDTH of U0 : label is 1;
  attribute LC_PROBE446_IS_DATA : string;
  attribute LC_PROBE446_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE446_IS_TRIG : string;
  attribute LC_PROBE446_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE446_MU_CNT : integer;
  attribute LC_PROBE446_MU_CNT of U0 : label is 1;
  attribute LC_PROBE446_PID : string;
  attribute LC_PROBE446_PID of U0 : label is "16'b0000000110111110";
  attribute LC_PROBE446_TYPE : integer;
  attribute LC_PROBE446_TYPE of U0 : label is 1;
  attribute LC_PROBE446_WIDTH : integer;
  attribute LC_PROBE446_WIDTH of U0 : label is 1;
  attribute LC_PROBE447_IS_DATA : string;
  attribute LC_PROBE447_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE447_IS_TRIG : string;
  attribute LC_PROBE447_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE447_MU_CNT : integer;
  attribute LC_PROBE447_MU_CNT of U0 : label is 1;
  attribute LC_PROBE447_PID : string;
  attribute LC_PROBE447_PID of U0 : label is "16'b0000000110111111";
  attribute LC_PROBE447_TYPE : integer;
  attribute LC_PROBE447_TYPE of U0 : label is 1;
  attribute LC_PROBE447_WIDTH : integer;
  attribute LC_PROBE447_WIDTH of U0 : label is 1;
  attribute LC_PROBE448_IS_DATA : string;
  attribute LC_PROBE448_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE448_IS_TRIG : string;
  attribute LC_PROBE448_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE448_MU_CNT : integer;
  attribute LC_PROBE448_MU_CNT of U0 : label is 1;
  attribute LC_PROBE448_PID : string;
  attribute LC_PROBE448_PID of U0 : label is "16'b0000000111000000";
  attribute LC_PROBE448_TYPE : integer;
  attribute LC_PROBE448_TYPE of U0 : label is 1;
  attribute LC_PROBE448_WIDTH : integer;
  attribute LC_PROBE448_WIDTH of U0 : label is 1;
  attribute LC_PROBE449_IS_DATA : string;
  attribute LC_PROBE449_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE449_IS_TRIG : string;
  attribute LC_PROBE449_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE449_MU_CNT : integer;
  attribute LC_PROBE449_MU_CNT of U0 : label is 1;
  attribute LC_PROBE449_PID : string;
  attribute LC_PROBE449_PID of U0 : label is "16'b0000000111000001";
  attribute LC_PROBE449_TYPE : integer;
  attribute LC_PROBE449_TYPE of U0 : label is 1;
  attribute LC_PROBE449_WIDTH : integer;
  attribute LC_PROBE449_WIDTH of U0 : label is 1;
  attribute LC_PROBE44_IS_DATA : string;
  attribute LC_PROBE44_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE44_IS_TRIG : string;
  attribute LC_PROBE44_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE44_MU_CNT : integer;
  attribute LC_PROBE44_MU_CNT of U0 : label is 1;
  attribute LC_PROBE44_PID : string;
  attribute LC_PROBE44_PID of U0 : label is "16'b0000000000101100";
  attribute LC_PROBE44_TYPE : integer;
  attribute LC_PROBE44_TYPE of U0 : label is 1;
  attribute LC_PROBE44_WIDTH : integer;
  attribute LC_PROBE44_WIDTH of U0 : label is 1;
  attribute LC_PROBE450_IS_DATA : string;
  attribute LC_PROBE450_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE450_IS_TRIG : string;
  attribute LC_PROBE450_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE450_MU_CNT : integer;
  attribute LC_PROBE450_MU_CNT of U0 : label is 1;
  attribute LC_PROBE450_PID : string;
  attribute LC_PROBE450_PID of U0 : label is "16'b0000000111000010";
  attribute LC_PROBE450_TYPE : integer;
  attribute LC_PROBE450_TYPE of U0 : label is 1;
  attribute LC_PROBE450_WIDTH : integer;
  attribute LC_PROBE450_WIDTH of U0 : label is 1;
  attribute LC_PROBE451_IS_DATA : string;
  attribute LC_PROBE451_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE451_IS_TRIG : string;
  attribute LC_PROBE451_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE451_MU_CNT : integer;
  attribute LC_PROBE451_MU_CNT of U0 : label is 1;
  attribute LC_PROBE451_PID : string;
  attribute LC_PROBE451_PID of U0 : label is "16'b0000000111000011";
  attribute LC_PROBE451_TYPE : integer;
  attribute LC_PROBE451_TYPE of U0 : label is 1;
  attribute LC_PROBE451_WIDTH : integer;
  attribute LC_PROBE451_WIDTH of U0 : label is 1;
  attribute LC_PROBE452_IS_DATA : string;
  attribute LC_PROBE452_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE452_IS_TRIG : string;
  attribute LC_PROBE452_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE452_MU_CNT : integer;
  attribute LC_PROBE452_MU_CNT of U0 : label is 1;
  attribute LC_PROBE452_PID : string;
  attribute LC_PROBE452_PID of U0 : label is "16'b0000000111000100";
  attribute LC_PROBE452_TYPE : integer;
  attribute LC_PROBE452_TYPE of U0 : label is 1;
  attribute LC_PROBE452_WIDTH : integer;
  attribute LC_PROBE452_WIDTH of U0 : label is 1;
  attribute LC_PROBE453_IS_DATA : string;
  attribute LC_PROBE453_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE453_IS_TRIG : string;
  attribute LC_PROBE453_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE453_MU_CNT : integer;
  attribute LC_PROBE453_MU_CNT of U0 : label is 1;
  attribute LC_PROBE453_PID : string;
  attribute LC_PROBE453_PID of U0 : label is "16'b0000000111000101";
  attribute LC_PROBE453_TYPE : integer;
  attribute LC_PROBE453_TYPE of U0 : label is 1;
  attribute LC_PROBE453_WIDTH : integer;
  attribute LC_PROBE453_WIDTH of U0 : label is 1;
  attribute LC_PROBE454_IS_DATA : string;
  attribute LC_PROBE454_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE454_IS_TRIG : string;
  attribute LC_PROBE454_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE454_MU_CNT : integer;
  attribute LC_PROBE454_MU_CNT of U0 : label is 1;
  attribute LC_PROBE454_PID : string;
  attribute LC_PROBE454_PID of U0 : label is "16'b0000000111000110";
  attribute LC_PROBE454_TYPE : integer;
  attribute LC_PROBE454_TYPE of U0 : label is 1;
  attribute LC_PROBE454_WIDTH : integer;
  attribute LC_PROBE454_WIDTH of U0 : label is 1;
  attribute LC_PROBE455_IS_DATA : string;
  attribute LC_PROBE455_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE455_IS_TRIG : string;
  attribute LC_PROBE455_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE455_MU_CNT : integer;
  attribute LC_PROBE455_MU_CNT of U0 : label is 1;
  attribute LC_PROBE455_PID : string;
  attribute LC_PROBE455_PID of U0 : label is "16'b0000000111000111";
  attribute LC_PROBE455_TYPE : integer;
  attribute LC_PROBE455_TYPE of U0 : label is 1;
  attribute LC_PROBE455_WIDTH : integer;
  attribute LC_PROBE455_WIDTH of U0 : label is 1;
  attribute LC_PROBE456_IS_DATA : string;
  attribute LC_PROBE456_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE456_IS_TRIG : string;
  attribute LC_PROBE456_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE456_MU_CNT : integer;
  attribute LC_PROBE456_MU_CNT of U0 : label is 1;
  attribute LC_PROBE456_PID : string;
  attribute LC_PROBE456_PID of U0 : label is "16'b0000000111001000";
  attribute LC_PROBE456_TYPE : integer;
  attribute LC_PROBE456_TYPE of U0 : label is 1;
  attribute LC_PROBE456_WIDTH : integer;
  attribute LC_PROBE456_WIDTH of U0 : label is 1;
  attribute LC_PROBE457_IS_DATA : string;
  attribute LC_PROBE457_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE457_IS_TRIG : string;
  attribute LC_PROBE457_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE457_MU_CNT : integer;
  attribute LC_PROBE457_MU_CNT of U0 : label is 1;
  attribute LC_PROBE457_PID : string;
  attribute LC_PROBE457_PID of U0 : label is "16'b0000000111001001";
  attribute LC_PROBE457_TYPE : integer;
  attribute LC_PROBE457_TYPE of U0 : label is 1;
  attribute LC_PROBE457_WIDTH : integer;
  attribute LC_PROBE457_WIDTH of U0 : label is 1;
  attribute LC_PROBE458_IS_DATA : string;
  attribute LC_PROBE458_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE458_IS_TRIG : string;
  attribute LC_PROBE458_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE458_MU_CNT : integer;
  attribute LC_PROBE458_MU_CNT of U0 : label is 1;
  attribute LC_PROBE458_PID : string;
  attribute LC_PROBE458_PID of U0 : label is "16'b0000000111001010";
  attribute LC_PROBE458_TYPE : integer;
  attribute LC_PROBE458_TYPE of U0 : label is 1;
  attribute LC_PROBE458_WIDTH : integer;
  attribute LC_PROBE458_WIDTH of U0 : label is 1;
  attribute LC_PROBE459_IS_DATA : string;
  attribute LC_PROBE459_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE459_IS_TRIG : string;
  attribute LC_PROBE459_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE459_MU_CNT : integer;
  attribute LC_PROBE459_MU_CNT of U0 : label is 1;
  attribute LC_PROBE459_PID : string;
  attribute LC_PROBE459_PID of U0 : label is "16'b0000000111001011";
  attribute LC_PROBE459_TYPE : integer;
  attribute LC_PROBE459_TYPE of U0 : label is 1;
  attribute LC_PROBE459_WIDTH : integer;
  attribute LC_PROBE459_WIDTH of U0 : label is 1;
  attribute LC_PROBE45_IS_DATA : string;
  attribute LC_PROBE45_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE45_IS_TRIG : string;
  attribute LC_PROBE45_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE45_MU_CNT : integer;
  attribute LC_PROBE45_MU_CNT of U0 : label is 1;
  attribute LC_PROBE45_PID : string;
  attribute LC_PROBE45_PID of U0 : label is "16'b0000000000101101";
  attribute LC_PROBE45_TYPE : integer;
  attribute LC_PROBE45_TYPE of U0 : label is 1;
  attribute LC_PROBE45_WIDTH : integer;
  attribute LC_PROBE45_WIDTH of U0 : label is 1;
  attribute LC_PROBE460_IS_DATA : string;
  attribute LC_PROBE460_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE460_IS_TRIG : string;
  attribute LC_PROBE460_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE460_MU_CNT : integer;
  attribute LC_PROBE460_MU_CNT of U0 : label is 1;
  attribute LC_PROBE460_PID : string;
  attribute LC_PROBE460_PID of U0 : label is "16'b0000000111001100";
  attribute LC_PROBE460_TYPE : integer;
  attribute LC_PROBE460_TYPE of U0 : label is 1;
  attribute LC_PROBE460_WIDTH : integer;
  attribute LC_PROBE460_WIDTH of U0 : label is 1;
  attribute LC_PROBE461_IS_DATA : string;
  attribute LC_PROBE461_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE461_IS_TRIG : string;
  attribute LC_PROBE461_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE461_MU_CNT : integer;
  attribute LC_PROBE461_MU_CNT of U0 : label is 1;
  attribute LC_PROBE461_PID : string;
  attribute LC_PROBE461_PID of U0 : label is "16'b0000000111001101";
  attribute LC_PROBE461_TYPE : integer;
  attribute LC_PROBE461_TYPE of U0 : label is 1;
  attribute LC_PROBE461_WIDTH : integer;
  attribute LC_PROBE461_WIDTH of U0 : label is 1;
  attribute LC_PROBE462_IS_DATA : string;
  attribute LC_PROBE462_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE462_IS_TRIG : string;
  attribute LC_PROBE462_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE462_MU_CNT : integer;
  attribute LC_PROBE462_MU_CNT of U0 : label is 1;
  attribute LC_PROBE462_PID : string;
  attribute LC_PROBE462_PID of U0 : label is "16'b0000000111001110";
  attribute LC_PROBE462_TYPE : integer;
  attribute LC_PROBE462_TYPE of U0 : label is 1;
  attribute LC_PROBE462_WIDTH : integer;
  attribute LC_PROBE462_WIDTH of U0 : label is 1;
  attribute LC_PROBE463_IS_DATA : string;
  attribute LC_PROBE463_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE463_IS_TRIG : string;
  attribute LC_PROBE463_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE463_MU_CNT : integer;
  attribute LC_PROBE463_MU_CNT of U0 : label is 1;
  attribute LC_PROBE463_PID : string;
  attribute LC_PROBE463_PID of U0 : label is "16'b0000000111001111";
  attribute LC_PROBE463_TYPE : integer;
  attribute LC_PROBE463_TYPE of U0 : label is 1;
  attribute LC_PROBE463_WIDTH : integer;
  attribute LC_PROBE463_WIDTH of U0 : label is 1;
  attribute LC_PROBE464_IS_DATA : string;
  attribute LC_PROBE464_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE464_IS_TRIG : string;
  attribute LC_PROBE464_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE464_MU_CNT : integer;
  attribute LC_PROBE464_MU_CNT of U0 : label is 1;
  attribute LC_PROBE464_PID : string;
  attribute LC_PROBE464_PID of U0 : label is "16'b0000000111010000";
  attribute LC_PROBE464_TYPE : integer;
  attribute LC_PROBE464_TYPE of U0 : label is 1;
  attribute LC_PROBE464_WIDTH : integer;
  attribute LC_PROBE464_WIDTH of U0 : label is 1;
  attribute LC_PROBE465_IS_DATA : string;
  attribute LC_PROBE465_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE465_IS_TRIG : string;
  attribute LC_PROBE465_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE465_MU_CNT : integer;
  attribute LC_PROBE465_MU_CNT of U0 : label is 1;
  attribute LC_PROBE465_PID : string;
  attribute LC_PROBE465_PID of U0 : label is "16'b0000000111010001";
  attribute LC_PROBE465_TYPE : integer;
  attribute LC_PROBE465_TYPE of U0 : label is 1;
  attribute LC_PROBE465_WIDTH : integer;
  attribute LC_PROBE465_WIDTH of U0 : label is 1;
  attribute LC_PROBE466_IS_DATA : string;
  attribute LC_PROBE466_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE466_IS_TRIG : string;
  attribute LC_PROBE466_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE466_MU_CNT : integer;
  attribute LC_PROBE466_MU_CNT of U0 : label is 1;
  attribute LC_PROBE466_PID : string;
  attribute LC_PROBE466_PID of U0 : label is "16'b0000000111010010";
  attribute LC_PROBE466_TYPE : integer;
  attribute LC_PROBE466_TYPE of U0 : label is 1;
  attribute LC_PROBE466_WIDTH : integer;
  attribute LC_PROBE466_WIDTH of U0 : label is 1;
  attribute LC_PROBE467_IS_DATA : string;
  attribute LC_PROBE467_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE467_IS_TRIG : string;
  attribute LC_PROBE467_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE467_MU_CNT : integer;
  attribute LC_PROBE467_MU_CNT of U0 : label is 1;
  attribute LC_PROBE467_PID : string;
  attribute LC_PROBE467_PID of U0 : label is "16'b0000000111010011";
  attribute LC_PROBE467_TYPE : integer;
  attribute LC_PROBE467_TYPE of U0 : label is 1;
  attribute LC_PROBE467_WIDTH : integer;
  attribute LC_PROBE467_WIDTH of U0 : label is 1;
  attribute LC_PROBE468_IS_DATA : string;
  attribute LC_PROBE468_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE468_IS_TRIG : string;
  attribute LC_PROBE468_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE468_MU_CNT : integer;
  attribute LC_PROBE468_MU_CNT of U0 : label is 1;
  attribute LC_PROBE468_PID : string;
  attribute LC_PROBE468_PID of U0 : label is "16'b0000000111010100";
  attribute LC_PROBE468_TYPE : integer;
  attribute LC_PROBE468_TYPE of U0 : label is 1;
  attribute LC_PROBE468_WIDTH : integer;
  attribute LC_PROBE468_WIDTH of U0 : label is 1;
  attribute LC_PROBE469_IS_DATA : string;
  attribute LC_PROBE469_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE469_IS_TRIG : string;
  attribute LC_PROBE469_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE469_MU_CNT : integer;
  attribute LC_PROBE469_MU_CNT of U0 : label is 1;
  attribute LC_PROBE469_PID : string;
  attribute LC_PROBE469_PID of U0 : label is "16'b0000000111010101";
  attribute LC_PROBE469_TYPE : integer;
  attribute LC_PROBE469_TYPE of U0 : label is 1;
  attribute LC_PROBE469_WIDTH : integer;
  attribute LC_PROBE469_WIDTH of U0 : label is 1;
  attribute LC_PROBE46_IS_DATA : string;
  attribute LC_PROBE46_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE46_IS_TRIG : string;
  attribute LC_PROBE46_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE46_MU_CNT : integer;
  attribute LC_PROBE46_MU_CNT of U0 : label is 1;
  attribute LC_PROBE46_PID : string;
  attribute LC_PROBE46_PID of U0 : label is "16'b0000000000101110";
  attribute LC_PROBE46_TYPE : integer;
  attribute LC_PROBE46_TYPE of U0 : label is 1;
  attribute LC_PROBE46_WIDTH : integer;
  attribute LC_PROBE46_WIDTH of U0 : label is 1;
  attribute LC_PROBE470_IS_DATA : string;
  attribute LC_PROBE470_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE470_IS_TRIG : string;
  attribute LC_PROBE470_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE470_MU_CNT : integer;
  attribute LC_PROBE470_MU_CNT of U0 : label is 1;
  attribute LC_PROBE470_PID : string;
  attribute LC_PROBE470_PID of U0 : label is "16'b0000000111010110";
  attribute LC_PROBE470_TYPE : integer;
  attribute LC_PROBE470_TYPE of U0 : label is 1;
  attribute LC_PROBE470_WIDTH : integer;
  attribute LC_PROBE470_WIDTH of U0 : label is 1;
  attribute LC_PROBE471_IS_DATA : string;
  attribute LC_PROBE471_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE471_IS_TRIG : string;
  attribute LC_PROBE471_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE471_MU_CNT : integer;
  attribute LC_PROBE471_MU_CNT of U0 : label is 1;
  attribute LC_PROBE471_PID : string;
  attribute LC_PROBE471_PID of U0 : label is "16'b0000000111010111";
  attribute LC_PROBE471_TYPE : integer;
  attribute LC_PROBE471_TYPE of U0 : label is 1;
  attribute LC_PROBE471_WIDTH : integer;
  attribute LC_PROBE471_WIDTH of U0 : label is 1;
  attribute LC_PROBE472_IS_DATA : string;
  attribute LC_PROBE472_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE472_IS_TRIG : string;
  attribute LC_PROBE472_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE472_MU_CNT : integer;
  attribute LC_PROBE472_MU_CNT of U0 : label is 1;
  attribute LC_PROBE472_PID : string;
  attribute LC_PROBE472_PID of U0 : label is "16'b0000000111011000";
  attribute LC_PROBE472_TYPE : integer;
  attribute LC_PROBE472_TYPE of U0 : label is 1;
  attribute LC_PROBE472_WIDTH : integer;
  attribute LC_PROBE472_WIDTH of U0 : label is 1;
  attribute LC_PROBE473_IS_DATA : string;
  attribute LC_PROBE473_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE473_IS_TRIG : string;
  attribute LC_PROBE473_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE473_MU_CNT : integer;
  attribute LC_PROBE473_MU_CNT of U0 : label is 1;
  attribute LC_PROBE473_PID : string;
  attribute LC_PROBE473_PID of U0 : label is "16'b0000000111011001";
  attribute LC_PROBE473_TYPE : integer;
  attribute LC_PROBE473_TYPE of U0 : label is 1;
  attribute LC_PROBE473_WIDTH : integer;
  attribute LC_PROBE473_WIDTH of U0 : label is 1;
  attribute LC_PROBE474_IS_DATA : string;
  attribute LC_PROBE474_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE474_IS_TRIG : string;
  attribute LC_PROBE474_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE474_MU_CNT : integer;
  attribute LC_PROBE474_MU_CNT of U0 : label is 1;
  attribute LC_PROBE474_PID : string;
  attribute LC_PROBE474_PID of U0 : label is "16'b0000000111011010";
  attribute LC_PROBE474_TYPE : integer;
  attribute LC_PROBE474_TYPE of U0 : label is 1;
  attribute LC_PROBE474_WIDTH : integer;
  attribute LC_PROBE474_WIDTH of U0 : label is 1;
  attribute LC_PROBE475_IS_DATA : string;
  attribute LC_PROBE475_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE475_IS_TRIG : string;
  attribute LC_PROBE475_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE475_MU_CNT : integer;
  attribute LC_PROBE475_MU_CNT of U0 : label is 1;
  attribute LC_PROBE475_PID : string;
  attribute LC_PROBE475_PID of U0 : label is "16'b0000000111011011";
  attribute LC_PROBE475_TYPE : integer;
  attribute LC_PROBE475_TYPE of U0 : label is 1;
  attribute LC_PROBE475_WIDTH : integer;
  attribute LC_PROBE475_WIDTH of U0 : label is 1;
  attribute LC_PROBE476_IS_DATA : string;
  attribute LC_PROBE476_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE476_IS_TRIG : string;
  attribute LC_PROBE476_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE476_MU_CNT : integer;
  attribute LC_PROBE476_MU_CNT of U0 : label is 1;
  attribute LC_PROBE476_PID : string;
  attribute LC_PROBE476_PID of U0 : label is "16'b0000000111011100";
  attribute LC_PROBE476_TYPE : integer;
  attribute LC_PROBE476_TYPE of U0 : label is 1;
  attribute LC_PROBE476_WIDTH : integer;
  attribute LC_PROBE476_WIDTH of U0 : label is 1;
  attribute LC_PROBE477_IS_DATA : string;
  attribute LC_PROBE477_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE477_IS_TRIG : string;
  attribute LC_PROBE477_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE477_MU_CNT : integer;
  attribute LC_PROBE477_MU_CNT of U0 : label is 1;
  attribute LC_PROBE477_PID : string;
  attribute LC_PROBE477_PID of U0 : label is "16'b0000000111011101";
  attribute LC_PROBE477_TYPE : integer;
  attribute LC_PROBE477_TYPE of U0 : label is 1;
  attribute LC_PROBE477_WIDTH : integer;
  attribute LC_PROBE477_WIDTH of U0 : label is 1;
  attribute LC_PROBE478_IS_DATA : string;
  attribute LC_PROBE478_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE478_IS_TRIG : string;
  attribute LC_PROBE478_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE478_MU_CNT : integer;
  attribute LC_PROBE478_MU_CNT of U0 : label is 1;
  attribute LC_PROBE478_PID : string;
  attribute LC_PROBE478_PID of U0 : label is "16'b0000000111011110";
  attribute LC_PROBE478_TYPE : integer;
  attribute LC_PROBE478_TYPE of U0 : label is 1;
  attribute LC_PROBE478_WIDTH : integer;
  attribute LC_PROBE478_WIDTH of U0 : label is 1;
  attribute LC_PROBE479_IS_DATA : string;
  attribute LC_PROBE479_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE479_IS_TRIG : string;
  attribute LC_PROBE479_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE479_MU_CNT : integer;
  attribute LC_PROBE479_MU_CNT of U0 : label is 1;
  attribute LC_PROBE479_PID : string;
  attribute LC_PROBE479_PID of U0 : label is "16'b0000000111011111";
  attribute LC_PROBE479_TYPE : integer;
  attribute LC_PROBE479_TYPE of U0 : label is 1;
  attribute LC_PROBE479_WIDTH : integer;
  attribute LC_PROBE479_WIDTH of U0 : label is 1;
  attribute LC_PROBE47_IS_DATA : string;
  attribute LC_PROBE47_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE47_IS_TRIG : string;
  attribute LC_PROBE47_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE47_MU_CNT : integer;
  attribute LC_PROBE47_MU_CNT of U0 : label is 1;
  attribute LC_PROBE47_PID : string;
  attribute LC_PROBE47_PID of U0 : label is "16'b0000000000101111";
  attribute LC_PROBE47_TYPE : integer;
  attribute LC_PROBE47_TYPE of U0 : label is 1;
  attribute LC_PROBE47_WIDTH : integer;
  attribute LC_PROBE47_WIDTH of U0 : label is 1;
  attribute LC_PROBE480_IS_DATA : string;
  attribute LC_PROBE480_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE480_IS_TRIG : string;
  attribute LC_PROBE480_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE480_MU_CNT : integer;
  attribute LC_PROBE480_MU_CNT of U0 : label is 1;
  attribute LC_PROBE480_PID : string;
  attribute LC_PROBE480_PID of U0 : label is "16'b0000000111100000";
  attribute LC_PROBE480_TYPE : integer;
  attribute LC_PROBE480_TYPE of U0 : label is 1;
  attribute LC_PROBE480_WIDTH : integer;
  attribute LC_PROBE480_WIDTH of U0 : label is 1;
  attribute LC_PROBE481_IS_DATA : string;
  attribute LC_PROBE481_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE481_IS_TRIG : string;
  attribute LC_PROBE481_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE481_MU_CNT : integer;
  attribute LC_PROBE481_MU_CNT of U0 : label is 1;
  attribute LC_PROBE481_PID : string;
  attribute LC_PROBE481_PID of U0 : label is "16'b0000000111100001";
  attribute LC_PROBE481_TYPE : integer;
  attribute LC_PROBE481_TYPE of U0 : label is 1;
  attribute LC_PROBE481_WIDTH : integer;
  attribute LC_PROBE481_WIDTH of U0 : label is 1;
  attribute LC_PROBE482_IS_DATA : string;
  attribute LC_PROBE482_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE482_IS_TRIG : string;
  attribute LC_PROBE482_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE482_MU_CNT : integer;
  attribute LC_PROBE482_MU_CNT of U0 : label is 1;
  attribute LC_PROBE482_PID : string;
  attribute LC_PROBE482_PID of U0 : label is "16'b0000000111100010";
  attribute LC_PROBE482_TYPE : integer;
  attribute LC_PROBE482_TYPE of U0 : label is 1;
  attribute LC_PROBE482_WIDTH : integer;
  attribute LC_PROBE482_WIDTH of U0 : label is 1;
  attribute LC_PROBE483_IS_DATA : string;
  attribute LC_PROBE483_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE483_IS_TRIG : string;
  attribute LC_PROBE483_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE483_MU_CNT : integer;
  attribute LC_PROBE483_MU_CNT of U0 : label is 1;
  attribute LC_PROBE483_PID : string;
  attribute LC_PROBE483_PID of U0 : label is "16'b0000000111100011";
  attribute LC_PROBE483_TYPE : integer;
  attribute LC_PROBE483_TYPE of U0 : label is 1;
  attribute LC_PROBE483_WIDTH : integer;
  attribute LC_PROBE483_WIDTH of U0 : label is 1;
  attribute LC_PROBE484_IS_DATA : string;
  attribute LC_PROBE484_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE484_IS_TRIG : string;
  attribute LC_PROBE484_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE484_MU_CNT : integer;
  attribute LC_PROBE484_MU_CNT of U0 : label is 1;
  attribute LC_PROBE484_PID : string;
  attribute LC_PROBE484_PID of U0 : label is "16'b0000000111100100";
  attribute LC_PROBE484_TYPE : integer;
  attribute LC_PROBE484_TYPE of U0 : label is 1;
  attribute LC_PROBE484_WIDTH : integer;
  attribute LC_PROBE484_WIDTH of U0 : label is 1;
  attribute LC_PROBE485_IS_DATA : string;
  attribute LC_PROBE485_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE485_IS_TRIG : string;
  attribute LC_PROBE485_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE485_MU_CNT : integer;
  attribute LC_PROBE485_MU_CNT of U0 : label is 1;
  attribute LC_PROBE485_PID : string;
  attribute LC_PROBE485_PID of U0 : label is "16'b0000000111100101";
  attribute LC_PROBE485_TYPE : integer;
  attribute LC_PROBE485_TYPE of U0 : label is 1;
  attribute LC_PROBE485_WIDTH : integer;
  attribute LC_PROBE485_WIDTH of U0 : label is 1;
  attribute LC_PROBE486_IS_DATA : string;
  attribute LC_PROBE486_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE486_IS_TRIG : string;
  attribute LC_PROBE486_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE486_MU_CNT : integer;
  attribute LC_PROBE486_MU_CNT of U0 : label is 1;
  attribute LC_PROBE486_PID : string;
  attribute LC_PROBE486_PID of U0 : label is "16'b0000000111100110";
  attribute LC_PROBE486_TYPE : integer;
  attribute LC_PROBE486_TYPE of U0 : label is 1;
  attribute LC_PROBE486_WIDTH : integer;
  attribute LC_PROBE486_WIDTH of U0 : label is 1;
  attribute LC_PROBE487_IS_DATA : string;
  attribute LC_PROBE487_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE487_IS_TRIG : string;
  attribute LC_PROBE487_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE487_MU_CNT : integer;
  attribute LC_PROBE487_MU_CNT of U0 : label is 1;
  attribute LC_PROBE487_PID : string;
  attribute LC_PROBE487_PID of U0 : label is "16'b0000000111100111";
  attribute LC_PROBE487_TYPE : integer;
  attribute LC_PROBE487_TYPE of U0 : label is 1;
  attribute LC_PROBE487_WIDTH : integer;
  attribute LC_PROBE487_WIDTH of U0 : label is 1;
  attribute LC_PROBE488_IS_DATA : string;
  attribute LC_PROBE488_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE488_IS_TRIG : string;
  attribute LC_PROBE488_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE488_MU_CNT : integer;
  attribute LC_PROBE488_MU_CNT of U0 : label is 1;
  attribute LC_PROBE488_PID : string;
  attribute LC_PROBE488_PID of U0 : label is "16'b0000000111101000";
  attribute LC_PROBE488_TYPE : integer;
  attribute LC_PROBE488_TYPE of U0 : label is 1;
  attribute LC_PROBE488_WIDTH : integer;
  attribute LC_PROBE488_WIDTH of U0 : label is 1;
  attribute LC_PROBE489_IS_DATA : string;
  attribute LC_PROBE489_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE489_IS_TRIG : string;
  attribute LC_PROBE489_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE489_MU_CNT : integer;
  attribute LC_PROBE489_MU_CNT of U0 : label is 1;
  attribute LC_PROBE489_PID : string;
  attribute LC_PROBE489_PID of U0 : label is "16'b0000000111101001";
  attribute LC_PROBE489_TYPE : integer;
  attribute LC_PROBE489_TYPE of U0 : label is 1;
  attribute LC_PROBE489_WIDTH : integer;
  attribute LC_PROBE489_WIDTH of U0 : label is 1;
  attribute LC_PROBE48_IS_DATA : string;
  attribute LC_PROBE48_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE48_IS_TRIG : string;
  attribute LC_PROBE48_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE48_MU_CNT : integer;
  attribute LC_PROBE48_MU_CNT of U0 : label is 1;
  attribute LC_PROBE48_PID : string;
  attribute LC_PROBE48_PID of U0 : label is "16'b0000000000110000";
  attribute LC_PROBE48_TYPE : integer;
  attribute LC_PROBE48_TYPE of U0 : label is 1;
  attribute LC_PROBE48_WIDTH : integer;
  attribute LC_PROBE48_WIDTH of U0 : label is 1;
  attribute LC_PROBE490_IS_DATA : string;
  attribute LC_PROBE490_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE490_IS_TRIG : string;
  attribute LC_PROBE490_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE490_MU_CNT : integer;
  attribute LC_PROBE490_MU_CNT of U0 : label is 1;
  attribute LC_PROBE490_PID : string;
  attribute LC_PROBE490_PID of U0 : label is "16'b0000000111101010";
  attribute LC_PROBE490_TYPE : integer;
  attribute LC_PROBE490_TYPE of U0 : label is 1;
  attribute LC_PROBE490_WIDTH : integer;
  attribute LC_PROBE490_WIDTH of U0 : label is 1;
  attribute LC_PROBE491_IS_DATA : string;
  attribute LC_PROBE491_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE491_IS_TRIG : string;
  attribute LC_PROBE491_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE491_MU_CNT : integer;
  attribute LC_PROBE491_MU_CNT of U0 : label is 1;
  attribute LC_PROBE491_PID : string;
  attribute LC_PROBE491_PID of U0 : label is "16'b0000000111101011";
  attribute LC_PROBE491_TYPE : integer;
  attribute LC_PROBE491_TYPE of U0 : label is 1;
  attribute LC_PROBE491_WIDTH : integer;
  attribute LC_PROBE491_WIDTH of U0 : label is 1;
  attribute LC_PROBE492_IS_DATA : string;
  attribute LC_PROBE492_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE492_IS_TRIG : string;
  attribute LC_PROBE492_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE492_MU_CNT : integer;
  attribute LC_PROBE492_MU_CNT of U0 : label is 1;
  attribute LC_PROBE492_PID : string;
  attribute LC_PROBE492_PID of U0 : label is "16'b0000000111101100";
  attribute LC_PROBE492_TYPE : integer;
  attribute LC_PROBE492_TYPE of U0 : label is 1;
  attribute LC_PROBE492_WIDTH : integer;
  attribute LC_PROBE492_WIDTH of U0 : label is 1;
  attribute LC_PROBE493_IS_DATA : string;
  attribute LC_PROBE493_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE493_IS_TRIG : string;
  attribute LC_PROBE493_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE493_MU_CNT : integer;
  attribute LC_PROBE493_MU_CNT of U0 : label is 1;
  attribute LC_PROBE493_PID : string;
  attribute LC_PROBE493_PID of U0 : label is "16'b0000000111101101";
  attribute LC_PROBE493_TYPE : integer;
  attribute LC_PROBE493_TYPE of U0 : label is 1;
  attribute LC_PROBE493_WIDTH : integer;
  attribute LC_PROBE493_WIDTH of U0 : label is 1;
  attribute LC_PROBE494_IS_DATA : string;
  attribute LC_PROBE494_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE494_IS_TRIG : string;
  attribute LC_PROBE494_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE494_MU_CNT : integer;
  attribute LC_PROBE494_MU_CNT of U0 : label is 1;
  attribute LC_PROBE494_PID : string;
  attribute LC_PROBE494_PID of U0 : label is "16'b0000000111101110";
  attribute LC_PROBE494_TYPE : integer;
  attribute LC_PROBE494_TYPE of U0 : label is 1;
  attribute LC_PROBE494_WIDTH : integer;
  attribute LC_PROBE494_WIDTH of U0 : label is 1;
  attribute LC_PROBE495_IS_DATA : string;
  attribute LC_PROBE495_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE495_IS_TRIG : string;
  attribute LC_PROBE495_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE495_MU_CNT : integer;
  attribute LC_PROBE495_MU_CNT of U0 : label is 1;
  attribute LC_PROBE495_PID : string;
  attribute LC_PROBE495_PID of U0 : label is "16'b0000000111101111";
  attribute LC_PROBE495_TYPE : integer;
  attribute LC_PROBE495_TYPE of U0 : label is 1;
  attribute LC_PROBE495_WIDTH : integer;
  attribute LC_PROBE495_WIDTH of U0 : label is 1;
  attribute LC_PROBE496_IS_DATA : string;
  attribute LC_PROBE496_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE496_IS_TRIG : string;
  attribute LC_PROBE496_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE496_MU_CNT : integer;
  attribute LC_PROBE496_MU_CNT of U0 : label is 1;
  attribute LC_PROBE496_PID : string;
  attribute LC_PROBE496_PID of U0 : label is "16'b0000000111110000";
  attribute LC_PROBE496_TYPE : integer;
  attribute LC_PROBE496_TYPE of U0 : label is 1;
  attribute LC_PROBE496_WIDTH : integer;
  attribute LC_PROBE496_WIDTH of U0 : label is 1;
  attribute LC_PROBE497_IS_DATA : string;
  attribute LC_PROBE497_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE497_IS_TRIG : string;
  attribute LC_PROBE497_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE497_MU_CNT : integer;
  attribute LC_PROBE497_MU_CNT of U0 : label is 1;
  attribute LC_PROBE497_PID : string;
  attribute LC_PROBE497_PID of U0 : label is "16'b0000000111110001";
  attribute LC_PROBE497_TYPE : integer;
  attribute LC_PROBE497_TYPE of U0 : label is 1;
  attribute LC_PROBE497_WIDTH : integer;
  attribute LC_PROBE497_WIDTH of U0 : label is 1;
  attribute LC_PROBE498_IS_DATA : string;
  attribute LC_PROBE498_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE498_IS_TRIG : string;
  attribute LC_PROBE498_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE498_MU_CNT : integer;
  attribute LC_PROBE498_MU_CNT of U0 : label is 1;
  attribute LC_PROBE498_PID : string;
  attribute LC_PROBE498_PID of U0 : label is "16'b0000000111110010";
  attribute LC_PROBE498_TYPE : integer;
  attribute LC_PROBE498_TYPE of U0 : label is 1;
  attribute LC_PROBE498_WIDTH : integer;
  attribute LC_PROBE498_WIDTH of U0 : label is 1;
  attribute LC_PROBE499_IS_DATA : string;
  attribute LC_PROBE499_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE499_IS_TRIG : string;
  attribute LC_PROBE499_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE499_MU_CNT : integer;
  attribute LC_PROBE499_MU_CNT of U0 : label is 1;
  attribute LC_PROBE499_PID : string;
  attribute LC_PROBE499_PID of U0 : label is "16'b0000000111110011";
  attribute LC_PROBE499_TYPE : integer;
  attribute LC_PROBE499_TYPE of U0 : label is 1;
  attribute LC_PROBE499_WIDTH : integer;
  attribute LC_PROBE499_WIDTH of U0 : label is 1;
  attribute LC_PROBE49_IS_DATA : string;
  attribute LC_PROBE49_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE49_IS_TRIG : string;
  attribute LC_PROBE49_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE49_MU_CNT : integer;
  attribute LC_PROBE49_MU_CNT of U0 : label is 1;
  attribute LC_PROBE49_PID : string;
  attribute LC_PROBE49_PID of U0 : label is "16'b0000000000110001";
  attribute LC_PROBE49_TYPE : integer;
  attribute LC_PROBE49_TYPE of U0 : label is 1;
  attribute LC_PROBE49_WIDTH : integer;
  attribute LC_PROBE49_WIDTH of U0 : label is 1;
  attribute LC_PROBE4_IS_DATA : string;
  attribute LC_PROBE4_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE4_IS_TRIG : string;
  attribute LC_PROBE4_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE4_MU_CNT : integer;
  attribute LC_PROBE4_MU_CNT of U0 : label is 1;
  attribute LC_PROBE4_PID : string;
  attribute LC_PROBE4_PID of U0 : label is "16'b0000000000000100";
  attribute LC_PROBE4_TYPE : integer;
  attribute LC_PROBE4_TYPE of U0 : label is 0;
  attribute LC_PROBE4_WIDTH : integer;
  attribute LC_PROBE4_WIDTH of U0 : label is 32;
  attribute LC_PROBE500_IS_DATA : string;
  attribute LC_PROBE500_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE500_IS_TRIG : string;
  attribute LC_PROBE500_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE500_MU_CNT : integer;
  attribute LC_PROBE500_MU_CNT of U0 : label is 1;
  attribute LC_PROBE500_PID : string;
  attribute LC_PROBE500_PID of U0 : label is "16'b0000000111110100";
  attribute LC_PROBE500_TYPE : integer;
  attribute LC_PROBE500_TYPE of U0 : label is 1;
  attribute LC_PROBE500_WIDTH : integer;
  attribute LC_PROBE500_WIDTH of U0 : label is 1;
  attribute LC_PROBE501_IS_DATA : string;
  attribute LC_PROBE501_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE501_IS_TRIG : string;
  attribute LC_PROBE501_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE501_MU_CNT : integer;
  attribute LC_PROBE501_MU_CNT of U0 : label is 1;
  attribute LC_PROBE501_PID : string;
  attribute LC_PROBE501_PID of U0 : label is "16'b0000000111110101";
  attribute LC_PROBE501_TYPE : integer;
  attribute LC_PROBE501_TYPE of U0 : label is 1;
  attribute LC_PROBE501_WIDTH : integer;
  attribute LC_PROBE501_WIDTH of U0 : label is 1;
  attribute LC_PROBE502_IS_DATA : string;
  attribute LC_PROBE502_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE502_IS_TRIG : string;
  attribute LC_PROBE502_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE502_MU_CNT : integer;
  attribute LC_PROBE502_MU_CNT of U0 : label is 1;
  attribute LC_PROBE502_PID : string;
  attribute LC_PROBE502_PID of U0 : label is "16'b0000000111110110";
  attribute LC_PROBE502_TYPE : integer;
  attribute LC_PROBE502_TYPE of U0 : label is 1;
  attribute LC_PROBE502_WIDTH : integer;
  attribute LC_PROBE502_WIDTH of U0 : label is 1;
  attribute LC_PROBE503_IS_DATA : string;
  attribute LC_PROBE503_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE503_IS_TRIG : string;
  attribute LC_PROBE503_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE503_MU_CNT : integer;
  attribute LC_PROBE503_MU_CNT of U0 : label is 1;
  attribute LC_PROBE503_PID : string;
  attribute LC_PROBE503_PID of U0 : label is "16'b0000000111110111";
  attribute LC_PROBE503_TYPE : integer;
  attribute LC_PROBE503_TYPE of U0 : label is 1;
  attribute LC_PROBE503_WIDTH : integer;
  attribute LC_PROBE503_WIDTH of U0 : label is 1;
  attribute LC_PROBE504_IS_DATA : string;
  attribute LC_PROBE504_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE504_IS_TRIG : string;
  attribute LC_PROBE504_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE504_MU_CNT : integer;
  attribute LC_PROBE504_MU_CNT of U0 : label is 1;
  attribute LC_PROBE504_PID : string;
  attribute LC_PROBE504_PID of U0 : label is "16'b0000000111111000";
  attribute LC_PROBE504_TYPE : integer;
  attribute LC_PROBE504_TYPE of U0 : label is 1;
  attribute LC_PROBE504_WIDTH : integer;
  attribute LC_PROBE504_WIDTH of U0 : label is 1;
  attribute LC_PROBE505_IS_DATA : string;
  attribute LC_PROBE505_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE505_IS_TRIG : string;
  attribute LC_PROBE505_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE505_MU_CNT : integer;
  attribute LC_PROBE505_MU_CNT of U0 : label is 1;
  attribute LC_PROBE505_PID : string;
  attribute LC_PROBE505_PID of U0 : label is "16'b0000000111111001";
  attribute LC_PROBE505_TYPE : integer;
  attribute LC_PROBE505_TYPE of U0 : label is 1;
  attribute LC_PROBE505_WIDTH : integer;
  attribute LC_PROBE505_WIDTH of U0 : label is 1;
  attribute LC_PROBE506_IS_DATA : string;
  attribute LC_PROBE506_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE506_IS_TRIG : string;
  attribute LC_PROBE506_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE506_MU_CNT : integer;
  attribute LC_PROBE506_MU_CNT of U0 : label is 1;
  attribute LC_PROBE506_PID : string;
  attribute LC_PROBE506_PID of U0 : label is "16'b0000000111111010";
  attribute LC_PROBE506_TYPE : integer;
  attribute LC_PROBE506_TYPE of U0 : label is 1;
  attribute LC_PROBE506_WIDTH : integer;
  attribute LC_PROBE506_WIDTH of U0 : label is 1;
  attribute LC_PROBE507_IS_DATA : string;
  attribute LC_PROBE507_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE507_IS_TRIG : string;
  attribute LC_PROBE507_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE507_MU_CNT : integer;
  attribute LC_PROBE507_MU_CNT of U0 : label is 1;
  attribute LC_PROBE507_PID : string;
  attribute LC_PROBE507_PID of U0 : label is "16'b0000000111111011";
  attribute LC_PROBE507_TYPE : integer;
  attribute LC_PROBE507_TYPE of U0 : label is 1;
  attribute LC_PROBE507_WIDTH : integer;
  attribute LC_PROBE507_WIDTH of U0 : label is 1;
  attribute LC_PROBE508_IS_DATA : string;
  attribute LC_PROBE508_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE508_IS_TRIG : string;
  attribute LC_PROBE508_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE508_MU_CNT : integer;
  attribute LC_PROBE508_MU_CNT of U0 : label is 1;
  attribute LC_PROBE508_PID : string;
  attribute LC_PROBE508_PID of U0 : label is "16'b0000000111111100";
  attribute LC_PROBE508_TYPE : integer;
  attribute LC_PROBE508_TYPE of U0 : label is 1;
  attribute LC_PROBE508_WIDTH : integer;
  attribute LC_PROBE508_WIDTH of U0 : label is 1;
  attribute LC_PROBE509_IS_DATA : string;
  attribute LC_PROBE509_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE509_IS_TRIG : string;
  attribute LC_PROBE509_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE509_MU_CNT : integer;
  attribute LC_PROBE509_MU_CNT of U0 : label is 1;
  attribute LC_PROBE509_PID : string;
  attribute LC_PROBE509_PID of U0 : label is "16'b0000000111111101";
  attribute LC_PROBE509_TYPE : integer;
  attribute LC_PROBE509_TYPE of U0 : label is 1;
  attribute LC_PROBE509_WIDTH : integer;
  attribute LC_PROBE509_WIDTH of U0 : label is 1;
  attribute LC_PROBE50_IS_DATA : string;
  attribute LC_PROBE50_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE50_IS_TRIG : string;
  attribute LC_PROBE50_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE50_MU_CNT : integer;
  attribute LC_PROBE50_MU_CNT of U0 : label is 1;
  attribute LC_PROBE50_PID : string;
  attribute LC_PROBE50_PID of U0 : label is "16'b0000000000110010";
  attribute LC_PROBE50_TYPE : integer;
  attribute LC_PROBE50_TYPE of U0 : label is 1;
  attribute LC_PROBE50_WIDTH : integer;
  attribute LC_PROBE50_WIDTH of U0 : label is 1;
  attribute LC_PROBE510_IS_DATA : string;
  attribute LC_PROBE510_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE510_IS_TRIG : string;
  attribute LC_PROBE510_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE510_MU_CNT : integer;
  attribute LC_PROBE510_MU_CNT of U0 : label is 1;
  attribute LC_PROBE510_PID : string;
  attribute LC_PROBE510_PID of U0 : label is "16'b0000000111111110";
  attribute LC_PROBE510_TYPE : integer;
  attribute LC_PROBE510_TYPE of U0 : label is 1;
  attribute LC_PROBE510_WIDTH : integer;
  attribute LC_PROBE510_WIDTH of U0 : label is 1;
  attribute LC_PROBE511_IS_DATA : string;
  attribute LC_PROBE511_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE511_IS_TRIG : string;
  attribute LC_PROBE511_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE511_MU_CNT : integer;
  attribute LC_PROBE511_MU_CNT of U0 : label is 1;
  attribute LC_PROBE511_PID : string;
  attribute LC_PROBE511_PID of U0 : label is "16'b0000000111111111";
  attribute LC_PROBE511_TYPE : integer;
  attribute LC_PROBE511_TYPE of U0 : label is 1;
  attribute LC_PROBE511_WIDTH : integer;
  attribute LC_PROBE511_WIDTH of U0 : label is 1;
  attribute LC_PROBE512_IS_DATA : string;
  attribute LC_PROBE512_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE512_IS_TRIG : string;
  attribute LC_PROBE512_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE512_MU_CNT : integer;
  attribute LC_PROBE512_MU_CNT of U0 : label is 1;
  attribute LC_PROBE512_PID : string;
  attribute LC_PROBE512_PID of U0 : label is "16'b0000001000000000";
  attribute LC_PROBE512_TYPE : integer;
  attribute LC_PROBE512_TYPE of U0 : label is 1;
  attribute LC_PROBE512_WIDTH : integer;
  attribute LC_PROBE512_WIDTH of U0 : label is 1;
  attribute LC_PROBE513_IS_DATA : string;
  attribute LC_PROBE513_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE513_IS_TRIG : string;
  attribute LC_PROBE513_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE513_MU_CNT : integer;
  attribute LC_PROBE513_MU_CNT of U0 : label is 1;
  attribute LC_PROBE513_PID : string;
  attribute LC_PROBE513_PID of U0 : label is "16'b0000001000000001";
  attribute LC_PROBE513_TYPE : integer;
  attribute LC_PROBE513_TYPE of U0 : label is 1;
  attribute LC_PROBE513_WIDTH : integer;
  attribute LC_PROBE513_WIDTH of U0 : label is 1;
  attribute LC_PROBE514_IS_DATA : string;
  attribute LC_PROBE514_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE514_IS_TRIG : string;
  attribute LC_PROBE514_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE514_MU_CNT : integer;
  attribute LC_PROBE514_MU_CNT of U0 : label is 1;
  attribute LC_PROBE514_PID : string;
  attribute LC_PROBE514_PID of U0 : label is "16'b0000001000000010";
  attribute LC_PROBE514_TYPE : integer;
  attribute LC_PROBE514_TYPE of U0 : label is 1;
  attribute LC_PROBE514_WIDTH : integer;
  attribute LC_PROBE514_WIDTH of U0 : label is 1;
  attribute LC_PROBE515_IS_DATA : string;
  attribute LC_PROBE515_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE515_IS_TRIG : string;
  attribute LC_PROBE515_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE515_MU_CNT : integer;
  attribute LC_PROBE515_MU_CNT of U0 : label is 1;
  attribute LC_PROBE515_PID : string;
  attribute LC_PROBE515_PID of U0 : label is "16'b0000001000000011";
  attribute LC_PROBE515_TYPE : integer;
  attribute LC_PROBE515_TYPE of U0 : label is 1;
  attribute LC_PROBE515_WIDTH : integer;
  attribute LC_PROBE515_WIDTH of U0 : label is 1;
  attribute LC_PROBE516_IS_DATA : string;
  attribute LC_PROBE516_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE516_IS_TRIG : string;
  attribute LC_PROBE516_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE516_MU_CNT : integer;
  attribute LC_PROBE516_MU_CNT of U0 : label is 1;
  attribute LC_PROBE516_PID : string;
  attribute LC_PROBE516_PID of U0 : label is "16'b0000001000000100";
  attribute LC_PROBE516_TYPE : integer;
  attribute LC_PROBE516_TYPE of U0 : label is 1;
  attribute LC_PROBE516_WIDTH : integer;
  attribute LC_PROBE516_WIDTH of U0 : label is 1;
  attribute LC_PROBE517_IS_DATA : string;
  attribute LC_PROBE517_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE517_IS_TRIG : string;
  attribute LC_PROBE517_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE517_MU_CNT : integer;
  attribute LC_PROBE517_MU_CNT of U0 : label is 1;
  attribute LC_PROBE517_PID : string;
  attribute LC_PROBE517_PID of U0 : label is "16'b0000001000000101";
  attribute LC_PROBE517_TYPE : integer;
  attribute LC_PROBE517_TYPE of U0 : label is 1;
  attribute LC_PROBE517_WIDTH : integer;
  attribute LC_PROBE517_WIDTH of U0 : label is 1;
  attribute LC_PROBE518_IS_DATA : string;
  attribute LC_PROBE518_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE518_IS_TRIG : string;
  attribute LC_PROBE518_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE518_MU_CNT : integer;
  attribute LC_PROBE518_MU_CNT of U0 : label is 1;
  attribute LC_PROBE518_PID : string;
  attribute LC_PROBE518_PID of U0 : label is "16'b0000001000000110";
  attribute LC_PROBE518_TYPE : integer;
  attribute LC_PROBE518_TYPE of U0 : label is 1;
  attribute LC_PROBE518_WIDTH : integer;
  attribute LC_PROBE518_WIDTH of U0 : label is 1;
  attribute LC_PROBE519_IS_DATA : string;
  attribute LC_PROBE519_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE519_IS_TRIG : string;
  attribute LC_PROBE519_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE519_MU_CNT : integer;
  attribute LC_PROBE519_MU_CNT of U0 : label is 1;
  attribute LC_PROBE519_PID : string;
  attribute LC_PROBE519_PID of U0 : label is "16'b0000001000000111";
  attribute LC_PROBE519_TYPE : integer;
  attribute LC_PROBE519_TYPE of U0 : label is 1;
  attribute LC_PROBE519_WIDTH : integer;
  attribute LC_PROBE519_WIDTH of U0 : label is 1;
  attribute LC_PROBE51_IS_DATA : string;
  attribute LC_PROBE51_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE51_IS_TRIG : string;
  attribute LC_PROBE51_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE51_MU_CNT : integer;
  attribute LC_PROBE51_MU_CNT of U0 : label is 1;
  attribute LC_PROBE51_PID : string;
  attribute LC_PROBE51_PID of U0 : label is "16'b0000000000110011";
  attribute LC_PROBE51_TYPE : integer;
  attribute LC_PROBE51_TYPE of U0 : label is 1;
  attribute LC_PROBE51_WIDTH : integer;
  attribute LC_PROBE51_WIDTH of U0 : label is 1;
  attribute LC_PROBE520_IS_DATA : string;
  attribute LC_PROBE520_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE520_IS_TRIG : string;
  attribute LC_PROBE520_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE520_MU_CNT : integer;
  attribute LC_PROBE520_MU_CNT of U0 : label is 1;
  attribute LC_PROBE520_PID : string;
  attribute LC_PROBE520_PID of U0 : label is "16'b0000001000001000";
  attribute LC_PROBE520_TYPE : integer;
  attribute LC_PROBE520_TYPE of U0 : label is 1;
  attribute LC_PROBE520_WIDTH : integer;
  attribute LC_PROBE520_WIDTH of U0 : label is 1;
  attribute LC_PROBE521_IS_DATA : string;
  attribute LC_PROBE521_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE521_IS_TRIG : string;
  attribute LC_PROBE521_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE521_MU_CNT : integer;
  attribute LC_PROBE521_MU_CNT of U0 : label is 1;
  attribute LC_PROBE521_PID : string;
  attribute LC_PROBE521_PID of U0 : label is "16'b0000001000001001";
  attribute LC_PROBE521_TYPE : integer;
  attribute LC_PROBE521_TYPE of U0 : label is 1;
  attribute LC_PROBE521_WIDTH : integer;
  attribute LC_PROBE521_WIDTH of U0 : label is 1;
  attribute LC_PROBE522_IS_DATA : string;
  attribute LC_PROBE522_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE522_IS_TRIG : string;
  attribute LC_PROBE522_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE522_MU_CNT : integer;
  attribute LC_PROBE522_MU_CNT of U0 : label is 1;
  attribute LC_PROBE522_PID : string;
  attribute LC_PROBE522_PID of U0 : label is "16'b0000001000001010";
  attribute LC_PROBE522_TYPE : integer;
  attribute LC_PROBE522_TYPE of U0 : label is 1;
  attribute LC_PROBE522_WIDTH : integer;
  attribute LC_PROBE522_WIDTH of U0 : label is 1;
  attribute LC_PROBE523_IS_DATA : string;
  attribute LC_PROBE523_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE523_IS_TRIG : string;
  attribute LC_PROBE523_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE523_MU_CNT : integer;
  attribute LC_PROBE523_MU_CNT of U0 : label is 1;
  attribute LC_PROBE523_PID : string;
  attribute LC_PROBE523_PID of U0 : label is "16'b0000001000001011";
  attribute LC_PROBE523_TYPE : integer;
  attribute LC_PROBE523_TYPE of U0 : label is 1;
  attribute LC_PROBE523_WIDTH : integer;
  attribute LC_PROBE523_WIDTH of U0 : label is 1;
  attribute LC_PROBE524_IS_DATA : string;
  attribute LC_PROBE524_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE524_IS_TRIG : string;
  attribute LC_PROBE524_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE524_MU_CNT : integer;
  attribute LC_PROBE524_MU_CNT of U0 : label is 1;
  attribute LC_PROBE524_PID : string;
  attribute LC_PROBE524_PID of U0 : label is "16'b0000001000001100";
  attribute LC_PROBE524_TYPE : integer;
  attribute LC_PROBE524_TYPE of U0 : label is 1;
  attribute LC_PROBE524_WIDTH : integer;
  attribute LC_PROBE524_WIDTH of U0 : label is 1;
  attribute LC_PROBE525_IS_DATA : string;
  attribute LC_PROBE525_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE525_IS_TRIG : string;
  attribute LC_PROBE525_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE525_MU_CNT : integer;
  attribute LC_PROBE525_MU_CNT of U0 : label is 1;
  attribute LC_PROBE525_PID : string;
  attribute LC_PROBE525_PID of U0 : label is "16'b0000001000001101";
  attribute LC_PROBE525_TYPE : integer;
  attribute LC_PROBE525_TYPE of U0 : label is 1;
  attribute LC_PROBE525_WIDTH : integer;
  attribute LC_PROBE525_WIDTH of U0 : label is 1;
  attribute LC_PROBE526_IS_DATA : string;
  attribute LC_PROBE526_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE526_IS_TRIG : string;
  attribute LC_PROBE526_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE526_MU_CNT : integer;
  attribute LC_PROBE526_MU_CNT of U0 : label is 1;
  attribute LC_PROBE526_PID : string;
  attribute LC_PROBE526_PID of U0 : label is "16'b0000001000001110";
  attribute LC_PROBE526_TYPE : integer;
  attribute LC_PROBE526_TYPE of U0 : label is 1;
  attribute LC_PROBE526_WIDTH : integer;
  attribute LC_PROBE526_WIDTH of U0 : label is 1;
  attribute LC_PROBE527_IS_DATA : string;
  attribute LC_PROBE527_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE527_IS_TRIG : string;
  attribute LC_PROBE527_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE527_MU_CNT : integer;
  attribute LC_PROBE527_MU_CNT of U0 : label is 1;
  attribute LC_PROBE527_PID : string;
  attribute LC_PROBE527_PID of U0 : label is "16'b0000001000001111";
  attribute LC_PROBE527_TYPE : integer;
  attribute LC_PROBE527_TYPE of U0 : label is 1;
  attribute LC_PROBE527_WIDTH : integer;
  attribute LC_PROBE527_WIDTH of U0 : label is 1;
  attribute LC_PROBE528_IS_DATA : string;
  attribute LC_PROBE528_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE528_IS_TRIG : string;
  attribute LC_PROBE528_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE528_MU_CNT : integer;
  attribute LC_PROBE528_MU_CNT of U0 : label is 1;
  attribute LC_PROBE528_PID : string;
  attribute LC_PROBE528_PID of U0 : label is "16'b0000001000010000";
  attribute LC_PROBE528_TYPE : integer;
  attribute LC_PROBE528_TYPE of U0 : label is 1;
  attribute LC_PROBE528_WIDTH : integer;
  attribute LC_PROBE528_WIDTH of U0 : label is 1;
  attribute LC_PROBE529_IS_DATA : string;
  attribute LC_PROBE529_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE529_IS_TRIG : string;
  attribute LC_PROBE529_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE529_MU_CNT : integer;
  attribute LC_PROBE529_MU_CNT of U0 : label is 1;
  attribute LC_PROBE529_PID : string;
  attribute LC_PROBE529_PID of U0 : label is "16'b0000001000010001";
  attribute LC_PROBE529_TYPE : integer;
  attribute LC_PROBE529_TYPE of U0 : label is 1;
  attribute LC_PROBE529_WIDTH : integer;
  attribute LC_PROBE529_WIDTH of U0 : label is 1;
  attribute LC_PROBE52_IS_DATA : string;
  attribute LC_PROBE52_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE52_IS_TRIG : string;
  attribute LC_PROBE52_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE52_MU_CNT : integer;
  attribute LC_PROBE52_MU_CNT of U0 : label is 1;
  attribute LC_PROBE52_PID : string;
  attribute LC_PROBE52_PID of U0 : label is "16'b0000000000110100";
  attribute LC_PROBE52_TYPE : integer;
  attribute LC_PROBE52_TYPE of U0 : label is 1;
  attribute LC_PROBE52_WIDTH : integer;
  attribute LC_PROBE52_WIDTH of U0 : label is 1;
  attribute LC_PROBE530_IS_DATA : string;
  attribute LC_PROBE530_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE530_IS_TRIG : string;
  attribute LC_PROBE530_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE530_MU_CNT : integer;
  attribute LC_PROBE530_MU_CNT of U0 : label is 1;
  attribute LC_PROBE530_PID : string;
  attribute LC_PROBE530_PID of U0 : label is "16'b0000001000010010";
  attribute LC_PROBE530_TYPE : integer;
  attribute LC_PROBE530_TYPE of U0 : label is 1;
  attribute LC_PROBE530_WIDTH : integer;
  attribute LC_PROBE530_WIDTH of U0 : label is 1;
  attribute LC_PROBE531_IS_DATA : string;
  attribute LC_PROBE531_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE531_IS_TRIG : string;
  attribute LC_PROBE531_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE531_MU_CNT : integer;
  attribute LC_PROBE531_MU_CNT of U0 : label is 1;
  attribute LC_PROBE531_PID : string;
  attribute LC_PROBE531_PID of U0 : label is "16'b0000001000010011";
  attribute LC_PROBE531_TYPE : integer;
  attribute LC_PROBE531_TYPE of U0 : label is 1;
  attribute LC_PROBE531_WIDTH : integer;
  attribute LC_PROBE531_WIDTH of U0 : label is 1;
  attribute LC_PROBE532_IS_DATA : string;
  attribute LC_PROBE532_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE532_IS_TRIG : string;
  attribute LC_PROBE532_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE532_MU_CNT : integer;
  attribute LC_PROBE532_MU_CNT of U0 : label is 1;
  attribute LC_PROBE532_PID : string;
  attribute LC_PROBE532_PID of U0 : label is "16'b0000001000010100";
  attribute LC_PROBE532_TYPE : integer;
  attribute LC_PROBE532_TYPE of U0 : label is 1;
  attribute LC_PROBE532_WIDTH : integer;
  attribute LC_PROBE532_WIDTH of U0 : label is 1;
  attribute LC_PROBE533_IS_DATA : string;
  attribute LC_PROBE533_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE533_IS_TRIG : string;
  attribute LC_PROBE533_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE533_MU_CNT : integer;
  attribute LC_PROBE533_MU_CNT of U0 : label is 1;
  attribute LC_PROBE533_PID : string;
  attribute LC_PROBE533_PID of U0 : label is "16'b0000001000010101";
  attribute LC_PROBE533_TYPE : integer;
  attribute LC_PROBE533_TYPE of U0 : label is 1;
  attribute LC_PROBE533_WIDTH : integer;
  attribute LC_PROBE533_WIDTH of U0 : label is 1;
  attribute LC_PROBE534_IS_DATA : string;
  attribute LC_PROBE534_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE534_IS_TRIG : string;
  attribute LC_PROBE534_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE534_MU_CNT : integer;
  attribute LC_PROBE534_MU_CNT of U0 : label is 1;
  attribute LC_PROBE534_PID : string;
  attribute LC_PROBE534_PID of U0 : label is "16'b0000001000010110";
  attribute LC_PROBE534_TYPE : integer;
  attribute LC_PROBE534_TYPE of U0 : label is 1;
  attribute LC_PROBE534_WIDTH : integer;
  attribute LC_PROBE534_WIDTH of U0 : label is 1;
  attribute LC_PROBE535_IS_DATA : string;
  attribute LC_PROBE535_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE535_IS_TRIG : string;
  attribute LC_PROBE535_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE535_MU_CNT : integer;
  attribute LC_PROBE535_MU_CNT of U0 : label is 1;
  attribute LC_PROBE535_PID : string;
  attribute LC_PROBE535_PID of U0 : label is "16'b0000001000010111";
  attribute LC_PROBE535_TYPE : integer;
  attribute LC_PROBE535_TYPE of U0 : label is 1;
  attribute LC_PROBE535_WIDTH : integer;
  attribute LC_PROBE535_WIDTH of U0 : label is 1;
  attribute LC_PROBE536_IS_DATA : string;
  attribute LC_PROBE536_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE536_IS_TRIG : string;
  attribute LC_PROBE536_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE536_MU_CNT : integer;
  attribute LC_PROBE536_MU_CNT of U0 : label is 1;
  attribute LC_PROBE536_PID : string;
  attribute LC_PROBE536_PID of U0 : label is "16'b0000001000011000";
  attribute LC_PROBE536_TYPE : integer;
  attribute LC_PROBE536_TYPE of U0 : label is 1;
  attribute LC_PROBE536_WIDTH : integer;
  attribute LC_PROBE536_WIDTH of U0 : label is 1;
  attribute LC_PROBE537_IS_DATA : string;
  attribute LC_PROBE537_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE537_IS_TRIG : string;
  attribute LC_PROBE537_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE537_MU_CNT : integer;
  attribute LC_PROBE537_MU_CNT of U0 : label is 1;
  attribute LC_PROBE537_PID : string;
  attribute LC_PROBE537_PID of U0 : label is "16'b0000001000011001";
  attribute LC_PROBE537_TYPE : integer;
  attribute LC_PROBE537_TYPE of U0 : label is 1;
  attribute LC_PROBE537_WIDTH : integer;
  attribute LC_PROBE537_WIDTH of U0 : label is 1;
  attribute LC_PROBE538_IS_DATA : string;
  attribute LC_PROBE538_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE538_IS_TRIG : string;
  attribute LC_PROBE538_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE538_MU_CNT : integer;
  attribute LC_PROBE538_MU_CNT of U0 : label is 1;
  attribute LC_PROBE538_PID : string;
  attribute LC_PROBE538_PID of U0 : label is "16'b0000001000011010";
  attribute LC_PROBE538_TYPE : integer;
  attribute LC_PROBE538_TYPE of U0 : label is 1;
  attribute LC_PROBE538_WIDTH : integer;
  attribute LC_PROBE538_WIDTH of U0 : label is 1;
  attribute LC_PROBE539_IS_DATA : string;
  attribute LC_PROBE539_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE539_IS_TRIG : string;
  attribute LC_PROBE539_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE539_MU_CNT : integer;
  attribute LC_PROBE539_MU_CNT of U0 : label is 1;
  attribute LC_PROBE539_PID : string;
  attribute LC_PROBE539_PID of U0 : label is "16'b0000001000011011";
  attribute LC_PROBE539_TYPE : integer;
  attribute LC_PROBE539_TYPE of U0 : label is 1;
  attribute LC_PROBE539_WIDTH : integer;
  attribute LC_PROBE539_WIDTH of U0 : label is 1;
  attribute LC_PROBE53_IS_DATA : string;
  attribute LC_PROBE53_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE53_IS_TRIG : string;
  attribute LC_PROBE53_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE53_MU_CNT : integer;
  attribute LC_PROBE53_MU_CNT of U0 : label is 1;
  attribute LC_PROBE53_PID : string;
  attribute LC_PROBE53_PID of U0 : label is "16'b0000000000110101";
  attribute LC_PROBE53_TYPE : integer;
  attribute LC_PROBE53_TYPE of U0 : label is 1;
  attribute LC_PROBE53_WIDTH : integer;
  attribute LC_PROBE53_WIDTH of U0 : label is 1;
  attribute LC_PROBE540_IS_DATA : string;
  attribute LC_PROBE540_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE540_IS_TRIG : string;
  attribute LC_PROBE540_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE540_MU_CNT : integer;
  attribute LC_PROBE540_MU_CNT of U0 : label is 1;
  attribute LC_PROBE540_PID : string;
  attribute LC_PROBE540_PID of U0 : label is "16'b0000001000011100";
  attribute LC_PROBE540_TYPE : integer;
  attribute LC_PROBE540_TYPE of U0 : label is 1;
  attribute LC_PROBE540_WIDTH : integer;
  attribute LC_PROBE540_WIDTH of U0 : label is 1;
  attribute LC_PROBE541_IS_DATA : string;
  attribute LC_PROBE541_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE541_IS_TRIG : string;
  attribute LC_PROBE541_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE541_MU_CNT : integer;
  attribute LC_PROBE541_MU_CNT of U0 : label is 1;
  attribute LC_PROBE541_PID : string;
  attribute LC_PROBE541_PID of U0 : label is "16'b0000001000011101";
  attribute LC_PROBE541_TYPE : integer;
  attribute LC_PROBE541_TYPE of U0 : label is 1;
  attribute LC_PROBE541_WIDTH : integer;
  attribute LC_PROBE541_WIDTH of U0 : label is 1;
  attribute LC_PROBE542_IS_DATA : string;
  attribute LC_PROBE542_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE542_IS_TRIG : string;
  attribute LC_PROBE542_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE542_MU_CNT : integer;
  attribute LC_PROBE542_MU_CNT of U0 : label is 1;
  attribute LC_PROBE542_PID : string;
  attribute LC_PROBE542_PID of U0 : label is "16'b0000001000011110";
  attribute LC_PROBE542_TYPE : integer;
  attribute LC_PROBE542_TYPE of U0 : label is 1;
  attribute LC_PROBE542_WIDTH : integer;
  attribute LC_PROBE542_WIDTH of U0 : label is 1;
  attribute LC_PROBE543_IS_DATA : string;
  attribute LC_PROBE543_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE543_IS_TRIG : string;
  attribute LC_PROBE543_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE543_MU_CNT : integer;
  attribute LC_PROBE543_MU_CNT of U0 : label is 1;
  attribute LC_PROBE543_PID : string;
  attribute LC_PROBE543_PID of U0 : label is "16'b0000001000011111";
  attribute LC_PROBE543_TYPE : integer;
  attribute LC_PROBE543_TYPE of U0 : label is 1;
  attribute LC_PROBE543_WIDTH : integer;
  attribute LC_PROBE543_WIDTH of U0 : label is 1;
  attribute LC_PROBE544_IS_DATA : string;
  attribute LC_PROBE544_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE544_IS_TRIG : string;
  attribute LC_PROBE544_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE544_MU_CNT : integer;
  attribute LC_PROBE544_MU_CNT of U0 : label is 1;
  attribute LC_PROBE544_PID : string;
  attribute LC_PROBE544_PID of U0 : label is "16'b0000001000100000";
  attribute LC_PROBE544_TYPE : integer;
  attribute LC_PROBE544_TYPE of U0 : label is 1;
  attribute LC_PROBE544_WIDTH : integer;
  attribute LC_PROBE544_WIDTH of U0 : label is 1;
  attribute LC_PROBE545_IS_DATA : string;
  attribute LC_PROBE545_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE545_IS_TRIG : string;
  attribute LC_PROBE545_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE545_MU_CNT : integer;
  attribute LC_PROBE545_MU_CNT of U0 : label is 1;
  attribute LC_PROBE545_PID : string;
  attribute LC_PROBE545_PID of U0 : label is "16'b0000001000100001";
  attribute LC_PROBE545_TYPE : integer;
  attribute LC_PROBE545_TYPE of U0 : label is 1;
  attribute LC_PROBE545_WIDTH : integer;
  attribute LC_PROBE545_WIDTH of U0 : label is 1;
  attribute LC_PROBE546_IS_DATA : string;
  attribute LC_PROBE546_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE546_IS_TRIG : string;
  attribute LC_PROBE546_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE546_MU_CNT : integer;
  attribute LC_PROBE546_MU_CNT of U0 : label is 1;
  attribute LC_PROBE546_PID : string;
  attribute LC_PROBE546_PID of U0 : label is "16'b0000001000100010";
  attribute LC_PROBE546_TYPE : integer;
  attribute LC_PROBE546_TYPE of U0 : label is 1;
  attribute LC_PROBE546_WIDTH : integer;
  attribute LC_PROBE546_WIDTH of U0 : label is 1;
  attribute LC_PROBE547_IS_DATA : string;
  attribute LC_PROBE547_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE547_IS_TRIG : string;
  attribute LC_PROBE547_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE547_MU_CNT : integer;
  attribute LC_PROBE547_MU_CNT of U0 : label is 1;
  attribute LC_PROBE547_PID : string;
  attribute LC_PROBE547_PID of U0 : label is "16'b0000001000100011";
  attribute LC_PROBE547_TYPE : integer;
  attribute LC_PROBE547_TYPE of U0 : label is 1;
  attribute LC_PROBE547_WIDTH : integer;
  attribute LC_PROBE547_WIDTH of U0 : label is 1;
  attribute LC_PROBE548_IS_DATA : string;
  attribute LC_PROBE548_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE548_IS_TRIG : string;
  attribute LC_PROBE548_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE548_MU_CNT : integer;
  attribute LC_PROBE548_MU_CNT of U0 : label is 1;
  attribute LC_PROBE548_PID : string;
  attribute LC_PROBE548_PID of U0 : label is "16'b0000001000100100";
  attribute LC_PROBE548_TYPE : integer;
  attribute LC_PROBE548_TYPE of U0 : label is 1;
  attribute LC_PROBE548_WIDTH : integer;
  attribute LC_PROBE548_WIDTH of U0 : label is 1;
  attribute LC_PROBE549_IS_DATA : string;
  attribute LC_PROBE549_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE549_IS_TRIG : string;
  attribute LC_PROBE549_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE549_MU_CNT : integer;
  attribute LC_PROBE549_MU_CNT of U0 : label is 1;
  attribute LC_PROBE549_PID : string;
  attribute LC_PROBE549_PID of U0 : label is "16'b0000001000100101";
  attribute LC_PROBE549_TYPE : integer;
  attribute LC_PROBE549_TYPE of U0 : label is 1;
  attribute LC_PROBE549_WIDTH : integer;
  attribute LC_PROBE549_WIDTH of U0 : label is 1;
  attribute LC_PROBE54_IS_DATA : string;
  attribute LC_PROBE54_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE54_IS_TRIG : string;
  attribute LC_PROBE54_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE54_MU_CNT : integer;
  attribute LC_PROBE54_MU_CNT of U0 : label is 1;
  attribute LC_PROBE54_PID : string;
  attribute LC_PROBE54_PID of U0 : label is "16'b0000000000110110";
  attribute LC_PROBE54_TYPE : integer;
  attribute LC_PROBE54_TYPE of U0 : label is 1;
  attribute LC_PROBE54_WIDTH : integer;
  attribute LC_PROBE54_WIDTH of U0 : label is 1;
  attribute LC_PROBE550_IS_DATA : string;
  attribute LC_PROBE550_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE550_IS_TRIG : string;
  attribute LC_PROBE550_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE550_MU_CNT : integer;
  attribute LC_PROBE550_MU_CNT of U0 : label is 1;
  attribute LC_PROBE550_PID : string;
  attribute LC_PROBE550_PID of U0 : label is "16'b0000001000100110";
  attribute LC_PROBE550_TYPE : integer;
  attribute LC_PROBE550_TYPE of U0 : label is 1;
  attribute LC_PROBE550_WIDTH : integer;
  attribute LC_PROBE550_WIDTH of U0 : label is 1;
  attribute LC_PROBE551_IS_DATA : string;
  attribute LC_PROBE551_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE551_IS_TRIG : string;
  attribute LC_PROBE551_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE551_MU_CNT : integer;
  attribute LC_PROBE551_MU_CNT of U0 : label is 1;
  attribute LC_PROBE551_PID : string;
  attribute LC_PROBE551_PID of U0 : label is "16'b0000001000100111";
  attribute LC_PROBE551_TYPE : integer;
  attribute LC_PROBE551_TYPE of U0 : label is 1;
  attribute LC_PROBE551_WIDTH : integer;
  attribute LC_PROBE551_WIDTH of U0 : label is 1;
  attribute LC_PROBE552_IS_DATA : string;
  attribute LC_PROBE552_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE552_IS_TRIG : string;
  attribute LC_PROBE552_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE552_MU_CNT : integer;
  attribute LC_PROBE552_MU_CNT of U0 : label is 1;
  attribute LC_PROBE552_PID : string;
  attribute LC_PROBE552_PID of U0 : label is "16'b0000001000101000";
  attribute LC_PROBE552_TYPE : integer;
  attribute LC_PROBE552_TYPE of U0 : label is 1;
  attribute LC_PROBE552_WIDTH : integer;
  attribute LC_PROBE552_WIDTH of U0 : label is 1;
  attribute LC_PROBE553_IS_DATA : string;
  attribute LC_PROBE553_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE553_IS_TRIG : string;
  attribute LC_PROBE553_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE553_MU_CNT : integer;
  attribute LC_PROBE553_MU_CNT of U0 : label is 1;
  attribute LC_PROBE553_PID : string;
  attribute LC_PROBE553_PID of U0 : label is "16'b0000001000101001";
  attribute LC_PROBE553_TYPE : integer;
  attribute LC_PROBE553_TYPE of U0 : label is 1;
  attribute LC_PROBE553_WIDTH : integer;
  attribute LC_PROBE553_WIDTH of U0 : label is 1;
  attribute LC_PROBE554_IS_DATA : string;
  attribute LC_PROBE554_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE554_IS_TRIG : string;
  attribute LC_PROBE554_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE554_MU_CNT : integer;
  attribute LC_PROBE554_MU_CNT of U0 : label is 1;
  attribute LC_PROBE554_PID : string;
  attribute LC_PROBE554_PID of U0 : label is "16'b0000001000101010";
  attribute LC_PROBE554_TYPE : integer;
  attribute LC_PROBE554_TYPE of U0 : label is 1;
  attribute LC_PROBE554_WIDTH : integer;
  attribute LC_PROBE554_WIDTH of U0 : label is 1;
  attribute LC_PROBE555_IS_DATA : string;
  attribute LC_PROBE555_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE555_IS_TRIG : string;
  attribute LC_PROBE555_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE555_MU_CNT : integer;
  attribute LC_PROBE555_MU_CNT of U0 : label is 1;
  attribute LC_PROBE555_PID : string;
  attribute LC_PROBE555_PID of U0 : label is "16'b0000001000101011";
  attribute LC_PROBE555_TYPE : integer;
  attribute LC_PROBE555_TYPE of U0 : label is 1;
  attribute LC_PROBE555_WIDTH : integer;
  attribute LC_PROBE555_WIDTH of U0 : label is 1;
  attribute LC_PROBE556_IS_DATA : string;
  attribute LC_PROBE556_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE556_IS_TRIG : string;
  attribute LC_PROBE556_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE556_MU_CNT : integer;
  attribute LC_PROBE556_MU_CNT of U0 : label is 1;
  attribute LC_PROBE556_PID : string;
  attribute LC_PROBE556_PID of U0 : label is "16'b0000001000101100";
  attribute LC_PROBE556_TYPE : integer;
  attribute LC_PROBE556_TYPE of U0 : label is 1;
  attribute LC_PROBE556_WIDTH : integer;
  attribute LC_PROBE556_WIDTH of U0 : label is 1;
  attribute LC_PROBE557_IS_DATA : string;
  attribute LC_PROBE557_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE557_IS_TRIG : string;
  attribute LC_PROBE557_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE557_MU_CNT : integer;
  attribute LC_PROBE557_MU_CNT of U0 : label is 1;
  attribute LC_PROBE557_PID : string;
  attribute LC_PROBE557_PID of U0 : label is "16'b0000001000101101";
  attribute LC_PROBE557_TYPE : integer;
  attribute LC_PROBE557_TYPE of U0 : label is 1;
  attribute LC_PROBE557_WIDTH : integer;
  attribute LC_PROBE557_WIDTH of U0 : label is 1;
  attribute LC_PROBE558_IS_DATA : string;
  attribute LC_PROBE558_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE558_IS_TRIG : string;
  attribute LC_PROBE558_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE558_MU_CNT : integer;
  attribute LC_PROBE558_MU_CNT of U0 : label is 1;
  attribute LC_PROBE558_PID : string;
  attribute LC_PROBE558_PID of U0 : label is "16'b0000001000101110";
  attribute LC_PROBE558_TYPE : integer;
  attribute LC_PROBE558_TYPE of U0 : label is 1;
  attribute LC_PROBE558_WIDTH : integer;
  attribute LC_PROBE558_WIDTH of U0 : label is 1;
  attribute LC_PROBE559_IS_DATA : string;
  attribute LC_PROBE559_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE559_IS_TRIG : string;
  attribute LC_PROBE559_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE559_MU_CNT : integer;
  attribute LC_PROBE559_MU_CNT of U0 : label is 1;
  attribute LC_PROBE559_PID : string;
  attribute LC_PROBE559_PID of U0 : label is "16'b0000001000101111";
  attribute LC_PROBE559_TYPE : integer;
  attribute LC_PROBE559_TYPE of U0 : label is 1;
  attribute LC_PROBE559_WIDTH : integer;
  attribute LC_PROBE559_WIDTH of U0 : label is 1;
  attribute LC_PROBE55_IS_DATA : string;
  attribute LC_PROBE55_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE55_IS_TRIG : string;
  attribute LC_PROBE55_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE55_MU_CNT : integer;
  attribute LC_PROBE55_MU_CNT of U0 : label is 1;
  attribute LC_PROBE55_PID : string;
  attribute LC_PROBE55_PID of U0 : label is "16'b0000000000110111";
  attribute LC_PROBE55_TYPE : integer;
  attribute LC_PROBE55_TYPE of U0 : label is 1;
  attribute LC_PROBE55_WIDTH : integer;
  attribute LC_PROBE55_WIDTH of U0 : label is 1;
  attribute LC_PROBE560_IS_DATA : string;
  attribute LC_PROBE560_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE560_IS_TRIG : string;
  attribute LC_PROBE560_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE560_MU_CNT : integer;
  attribute LC_PROBE560_MU_CNT of U0 : label is 1;
  attribute LC_PROBE560_PID : string;
  attribute LC_PROBE560_PID of U0 : label is "16'b0000001000110000";
  attribute LC_PROBE560_TYPE : integer;
  attribute LC_PROBE560_TYPE of U0 : label is 1;
  attribute LC_PROBE560_WIDTH : integer;
  attribute LC_PROBE560_WIDTH of U0 : label is 1;
  attribute LC_PROBE561_IS_DATA : string;
  attribute LC_PROBE561_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE561_IS_TRIG : string;
  attribute LC_PROBE561_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE561_MU_CNT : integer;
  attribute LC_PROBE561_MU_CNT of U0 : label is 1;
  attribute LC_PROBE561_PID : string;
  attribute LC_PROBE561_PID of U0 : label is "16'b0000001000110001";
  attribute LC_PROBE561_TYPE : integer;
  attribute LC_PROBE561_TYPE of U0 : label is 1;
  attribute LC_PROBE561_WIDTH : integer;
  attribute LC_PROBE561_WIDTH of U0 : label is 1;
  attribute LC_PROBE562_IS_DATA : string;
  attribute LC_PROBE562_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE562_IS_TRIG : string;
  attribute LC_PROBE562_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE562_MU_CNT : integer;
  attribute LC_PROBE562_MU_CNT of U0 : label is 1;
  attribute LC_PROBE562_PID : string;
  attribute LC_PROBE562_PID of U0 : label is "16'b0000001000110010";
  attribute LC_PROBE562_TYPE : integer;
  attribute LC_PROBE562_TYPE of U0 : label is 1;
  attribute LC_PROBE562_WIDTH : integer;
  attribute LC_PROBE562_WIDTH of U0 : label is 1;
  attribute LC_PROBE563_IS_DATA : string;
  attribute LC_PROBE563_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE563_IS_TRIG : string;
  attribute LC_PROBE563_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE563_MU_CNT : integer;
  attribute LC_PROBE563_MU_CNT of U0 : label is 1;
  attribute LC_PROBE563_PID : string;
  attribute LC_PROBE563_PID of U0 : label is "16'b0000001000110011";
  attribute LC_PROBE563_TYPE : integer;
  attribute LC_PROBE563_TYPE of U0 : label is 1;
  attribute LC_PROBE563_WIDTH : integer;
  attribute LC_PROBE563_WIDTH of U0 : label is 1;
  attribute LC_PROBE564_IS_DATA : string;
  attribute LC_PROBE564_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE564_IS_TRIG : string;
  attribute LC_PROBE564_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE564_MU_CNT : integer;
  attribute LC_PROBE564_MU_CNT of U0 : label is 1;
  attribute LC_PROBE564_PID : string;
  attribute LC_PROBE564_PID of U0 : label is "16'b0000001000110100";
  attribute LC_PROBE564_TYPE : integer;
  attribute LC_PROBE564_TYPE of U0 : label is 1;
  attribute LC_PROBE564_WIDTH : integer;
  attribute LC_PROBE564_WIDTH of U0 : label is 1;
  attribute LC_PROBE565_IS_DATA : string;
  attribute LC_PROBE565_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE565_IS_TRIG : string;
  attribute LC_PROBE565_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE565_MU_CNT : integer;
  attribute LC_PROBE565_MU_CNT of U0 : label is 1;
  attribute LC_PROBE565_PID : string;
  attribute LC_PROBE565_PID of U0 : label is "16'b0000001000110101";
  attribute LC_PROBE565_TYPE : integer;
  attribute LC_PROBE565_TYPE of U0 : label is 1;
  attribute LC_PROBE565_WIDTH : integer;
  attribute LC_PROBE565_WIDTH of U0 : label is 1;
  attribute LC_PROBE566_IS_DATA : string;
  attribute LC_PROBE566_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE566_IS_TRIG : string;
  attribute LC_PROBE566_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE566_MU_CNT : integer;
  attribute LC_PROBE566_MU_CNT of U0 : label is 1;
  attribute LC_PROBE566_PID : string;
  attribute LC_PROBE566_PID of U0 : label is "16'b0000001000110110";
  attribute LC_PROBE566_TYPE : integer;
  attribute LC_PROBE566_TYPE of U0 : label is 1;
  attribute LC_PROBE566_WIDTH : integer;
  attribute LC_PROBE566_WIDTH of U0 : label is 1;
  attribute LC_PROBE567_IS_DATA : string;
  attribute LC_PROBE567_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE567_IS_TRIG : string;
  attribute LC_PROBE567_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE567_MU_CNT : integer;
  attribute LC_PROBE567_MU_CNT of U0 : label is 1;
  attribute LC_PROBE567_PID : string;
  attribute LC_PROBE567_PID of U0 : label is "16'b0000001000110111";
  attribute LC_PROBE567_TYPE : integer;
  attribute LC_PROBE567_TYPE of U0 : label is 1;
  attribute LC_PROBE567_WIDTH : integer;
  attribute LC_PROBE567_WIDTH of U0 : label is 1;
  attribute LC_PROBE568_IS_DATA : string;
  attribute LC_PROBE568_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE568_IS_TRIG : string;
  attribute LC_PROBE568_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE568_MU_CNT : integer;
  attribute LC_PROBE568_MU_CNT of U0 : label is 1;
  attribute LC_PROBE568_PID : string;
  attribute LC_PROBE568_PID of U0 : label is "16'b0000001000111000";
  attribute LC_PROBE568_TYPE : integer;
  attribute LC_PROBE568_TYPE of U0 : label is 1;
  attribute LC_PROBE568_WIDTH : integer;
  attribute LC_PROBE568_WIDTH of U0 : label is 1;
  attribute LC_PROBE569_IS_DATA : string;
  attribute LC_PROBE569_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE569_IS_TRIG : string;
  attribute LC_PROBE569_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE569_MU_CNT : integer;
  attribute LC_PROBE569_MU_CNT of U0 : label is 1;
  attribute LC_PROBE569_PID : string;
  attribute LC_PROBE569_PID of U0 : label is "16'b0000001000111001";
  attribute LC_PROBE569_TYPE : integer;
  attribute LC_PROBE569_TYPE of U0 : label is 1;
  attribute LC_PROBE569_WIDTH : integer;
  attribute LC_PROBE569_WIDTH of U0 : label is 1;
  attribute LC_PROBE56_IS_DATA : string;
  attribute LC_PROBE56_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE56_IS_TRIG : string;
  attribute LC_PROBE56_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE56_MU_CNT : integer;
  attribute LC_PROBE56_MU_CNT of U0 : label is 1;
  attribute LC_PROBE56_PID : string;
  attribute LC_PROBE56_PID of U0 : label is "16'b0000000000111000";
  attribute LC_PROBE56_TYPE : integer;
  attribute LC_PROBE56_TYPE of U0 : label is 1;
  attribute LC_PROBE56_WIDTH : integer;
  attribute LC_PROBE56_WIDTH of U0 : label is 1;
  attribute LC_PROBE570_IS_DATA : string;
  attribute LC_PROBE570_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE570_IS_TRIG : string;
  attribute LC_PROBE570_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE570_MU_CNT : integer;
  attribute LC_PROBE570_MU_CNT of U0 : label is 1;
  attribute LC_PROBE570_PID : string;
  attribute LC_PROBE570_PID of U0 : label is "16'b0000001000111010";
  attribute LC_PROBE570_TYPE : integer;
  attribute LC_PROBE570_TYPE of U0 : label is 1;
  attribute LC_PROBE570_WIDTH : integer;
  attribute LC_PROBE570_WIDTH of U0 : label is 1;
  attribute LC_PROBE571_IS_DATA : string;
  attribute LC_PROBE571_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE571_IS_TRIG : string;
  attribute LC_PROBE571_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE571_MU_CNT : integer;
  attribute LC_PROBE571_MU_CNT of U0 : label is 1;
  attribute LC_PROBE571_PID : string;
  attribute LC_PROBE571_PID of U0 : label is "16'b0000001000111011";
  attribute LC_PROBE571_TYPE : integer;
  attribute LC_PROBE571_TYPE of U0 : label is 1;
  attribute LC_PROBE571_WIDTH : integer;
  attribute LC_PROBE571_WIDTH of U0 : label is 1;
  attribute LC_PROBE572_IS_DATA : string;
  attribute LC_PROBE572_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE572_IS_TRIG : string;
  attribute LC_PROBE572_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE572_MU_CNT : integer;
  attribute LC_PROBE572_MU_CNT of U0 : label is 1;
  attribute LC_PROBE572_PID : string;
  attribute LC_PROBE572_PID of U0 : label is "16'b0000001000111100";
  attribute LC_PROBE572_TYPE : integer;
  attribute LC_PROBE572_TYPE of U0 : label is 1;
  attribute LC_PROBE572_WIDTH : integer;
  attribute LC_PROBE572_WIDTH of U0 : label is 1;
  attribute LC_PROBE573_IS_DATA : string;
  attribute LC_PROBE573_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE573_IS_TRIG : string;
  attribute LC_PROBE573_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE573_MU_CNT : integer;
  attribute LC_PROBE573_MU_CNT of U0 : label is 1;
  attribute LC_PROBE573_PID : string;
  attribute LC_PROBE573_PID of U0 : label is "16'b0000001000111101";
  attribute LC_PROBE573_TYPE : integer;
  attribute LC_PROBE573_TYPE of U0 : label is 1;
  attribute LC_PROBE573_WIDTH : integer;
  attribute LC_PROBE573_WIDTH of U0 : label is 1;
  attribute LC_PROBE574_IS_DATA : string;
  attribute LC_PROBE574_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE574_IS_TRIG : string;
  attribute LC_PROBE574_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE574_MU_CNT : integer;
  attribute LC_PROBE574_MU_CNT of U0 : label is 1;
  attribute LC_PROBE574_PID : string;
  attribute LC_PROBE574_PID of U0 : label is "16'b0000001000111110";
  attribute LC_PROBE574_TYPE : integer;
  attribute LC_PROBE574_TYPE of U0 : label is 1;
  attribute LC_PROBE574_WIDTH : integer;
  attribute LC_PROBE574_WIDTH of U0 : label is 1;
  attribute LC_PROBE575_IS_DATA : string;
  attribute LC_PROBE575_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE575_IS_TRIG : string;
  attribute LC_PROBE575_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE575_MU_CNT : integer;
  attribute LC_PROBE575_MU_CNT of U0 : label is 1;
  attribute LC_PROBE575_PID : string;
  attribute LC_PROBE575_PID of U0 : label is "16'b0000001000111111";
  attribute LC_PROBE575_TYPE : integer;
  attribute LC_PROBE575_TYPE of U0 : label is 1;
  attribute LC_PROBE575_WIDTH : integer;
  attribute LC_PROBE575_WIDTH of U0 : label is 1;
  attribute LC_PROBE576_IS_DATA : string;
  attribute LC_PROBE576_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE576_IS_TRIG : string;
  attribute LC_PROBE576_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE576_MU_CNT : integer;
  attribute LC_PROBE576_MU_CNT of U0 : label is 1;
  attribute LC_PROBE576_PID : string;
  attribute LC_PROBE576_PID of U0 : label is "16'b0000001001000000";
  attribute LC_PROBE576_TYPE : integer;
  attribute LC_PROBE576_TYPE of U0 : label is 1;
  attribute LC_PROBE576_WIDTH : integer;
  attribute LC_PROBE576_WIDTH of U0 : label is 1;
  attribute LC_PROBE577_IS_DATA : string;
  attribute LC_PROBE577_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE577_IS_TRIG : string;
  attribute LC_PROBE577_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE577_MU_CNT : integer;
  attribute LC_PROBE577_MU_CNT of U0 : label is 1;
  attribute LC_PROBE577_PID : string;
  attribute LC_PROBE577_PID of U0 : label is "16'b0000001001000001";
  attribute LC_PROBE577_TYPE : integer;
  attribute LC_PROBE577_TYPE of U0 : label is 1;
  attribute LC_PROBE577_WIDTH : integer;
  attribute LC_PROBE577_WIDTH of U0 : label is 1;
  attribute LC_PROBE578_IS_DATA : string;
  attribute LC_PROBE578_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE578_IS_TRIG : string;
  attribute LC_PROBE578_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE578_MU_CNT : integer;
  attribute LC_PROBE578_MU_CNT of U0 : label is 1;
  attribute LC_PROBE578_PID : string;
  attribute LC_PROBE578_PID of U0 : label is "16'b0000001001000010";
  attribute LC_PROBE578_TYPE : integer;
  attribute LC_PROBE578_TYPE of U0 : label is 1;
  attribute LC_PROBE578_WIDTH : integer;
  attribute LC_PROBE578_WIDTH of U0 : label is 1;
  attribute LC_PROBE579_IS_DATA : string;
  attribute LC_PROBE579_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE579_IS_TRIG : string;
  attribute LC_PROBE579_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE579_MU_CNT : integer;
  attribute LC_PROBE579_MU_CNT of U0 : label is 1;
  attribute LC_PROBE579_PID : string;
  attribute LC_PROBE579_PID of U0 : label is "16'b0000001001000011";
  attribute LC_PROBE579_TYPE : integer;
  attribute LC_PROBE579_TYPE of U0 : label is 1;
  attribute LC_PROBE579_WIDTH : integer;
  attribute LC_PROBE579_WIDTH of U0 : label is 1;
  attribute LC_PROBE57_IS_DATA : string;
  attribute LC_PROBE57_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE57_IS_TRIG : string;
  attribute LC_PROBE57_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE57_MU_CNT : integer;
  attribute LC_PROBE57_MU_CNT of U0 : label is 1;
  attribute LC_PROBE57_PID : string;
  attribute LC_PROBE57_PID of U0 : label is "16'b0000000000111001";
  attribute LC_PROBE57_TYPE : integer;
  attribute LC_PROBE57_TYPE of U0 : label is 1;
  attribute LC_PROBE57_WIDTH : integer;
  attribute LC_PROBE57_WIDTH of U0 : label is 1;
  attribute LC_PROBE580_IS_DATA : string;
  attribute LC_PROBE580_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE580_IS_TRIG : string;
  attribute LC_PROBE580_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE580_MU_CNT : integer;
  attribute LC_PROBE580_MU_CNT of U0 : label is 1;
  attribute LC_PROBE580_PID : string;
  attribute LC_PROBE580_PID of U0 : label is "16'b0000001001000100";
  attribute LC_PROBE580_TYPE : integer;
  attribute LC_PROBE580_TYPE of U0 : label is 1;
  attribute LC_PROBE580_WIDTH : integer;
  attribute LC_PROBE580_WIDTH of U0 : label is 1;
  attribute LC_PROBE581_IS_DATA : string;
  attribute LC_PROBE581_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE581_IS_TRIG : string;
  attribute LC_PROBE581_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE581_MU_CNT : integer;
  attribute LC_PROBE581_MU_CNT of U0 : label is 1;
  attribute LC_PROBE581_PID : string;
  attribute LC_PROBE581_PID of U0 : label is "16'b0000001001000101";
  attribute LC_PROBE581_TYPE : integer;
  attribute LC_PROBE581_TYPE of U0 : label is 1;
  attribute LC_PROBE581_WIDTH : integer;
  attribute LC_PROBE581_WIDTH of U0 : label is 1;
  attribute LC_PROBE582_IS_DATA : string;
  attribute LC_PROBE582_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE582_IS_TRIG : string;
  attribute LC_PROBE582_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE582_MU_CNT : integer;
  attribute LC_PROBE582_MU_CNT of U0 : label is 1;
  attribute LC_PROBE582_PID : string;
  attribute LC_PROBE582_PID of U0 : label is "16'b0000001001000110";
  attribute LC_PROBE582_TYPE : integer;
  attribute LC_PROBE582_TYPE of U0 : label is 1;
  attribute LC_PROBE582_WIDTH : integer;
  attribute LC_PROBE582_WIDTH of U0 : label is 1;
  attribute LC_PROBE583_IS_DATA : string;
  attribute LC_PROBE583_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE583_IS_TRIG : string;
  attribute LC_PROBE583_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE583_MU_CNT : integer;
  attribute LC_PROBE583_MU_CNT of U0 : label is 1;
  attribute LC_PROBE583_PID : string;
  attribute LC_PROBE583_PID of U0 : label is "16'b0000001001000111";
  attribute LC_PROBE583_TYPE : integer;
  attribute LC_PROBE583_TYPE of U0 : label is 1;
  attribute LC_PROBE583_WIDTH : integer;
  attribute LC_PROBE583_WIDTH of U0 : label is 1;
  attribute LC_PROBE584_IS_DATA : string;
  attribute LC_PROBE584_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE584_IS_TRIG : string;
  attribute LC_PROBE584_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE584_MU_CNT : integer;
  attribute LC_PROBE584_MU_CNT of U0 : label is 1;
  attribute LC_PROBE584_PID : string;
  attribute LC_PROBE584_PID of U0 : label is "16'b0000001001001000";
  attribute LC_PROBE584_TYPE : integer;
  attribute LC_PROBE584_TYPE of U0 : label is 1;
  attribute LC_PROBE584_WIDTH : integer;
  attribute LC_PROBE584_WIDTH of U0 : label is 1;
  attribute LC_PROBE585_IS_DATA : string;
  attribute LC_PROBE585_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE585_IS_TRIG : string;
  attribute LC_PROBE585_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE585_MU_CNT : integer;
  attribute LC_PROBE585_MU_CNT of U0 : label is 1;
  attribute LC_PROBE585_PID : string;
  attribute LC_PROBE585_PID of U0 : label is "16'b0000001001001001";
  attribute LC_PROBE585_TYPE : integer;
  attribute LC_PROBE585_TYPE of U0 : label is 1;
  attribute LC_PROBE585_WIDTH : integer;
  attribute LC_PROBE585_WIDTH of U0 : label is 1;
  attribute LC_PROBE586_IS_DATA : string;
  attribute LC_PROBE586_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE586_IS_TRIG : string;
  attribute LC_PROBE586_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE586_MU_CNT : integer;
  attribute LC_PROBE586_MU_CNT of U0 : label is 1;
  attribute LC_PROBE586_PID : string;
  attribute LC_PROBE586_PID of U0 : label is "16'b0000001001001010";
  attribute LC_PROBE586_TYPE : integer;
  attribute LC_PROBE586_TYPE of U0 : label is 1;
  attribute LC_PROBE586_WIDTH : integer;
  attribute LC_PROBE586_WIDTH of U0 : label is 1;
  attribute LC_PROBE587_IS_DATA : string;
  attribute LC_PROBE587_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE587_IS_TRIG : string;
  attribute LC_PROBE587_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE587_MU_CNT : integer;
  attribute LC_PROBE587_MU_CNT of U0 : label is 1;
  attribute LC_PROBE587_PID : string;
  attribute LC_PROBE587_PID of U0 : label is "16'b0000001001001011";
  attribute LC_PROBE587_TYPE : integer;
  attribute LC_PROBE587_TYPE of U0 : label is 1;
  attribute LC_PROBE587_WIDTH : integer;
  attribute LC_PROBE587_WIDTH of U0 : label is 1;
  attribute LC_PROBE588_IS_DATA : string;
  attribute LC_PROBE588_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE588_IS_TRIG : string;
  attribute LC_PROBE588_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE588_MU_CNT : integer;
  attribute LC_PROBE588_MU_CNT of U0 : label is 1;
  attribute LC_PROBE588_PID : string;
  attribute LC_PROBE588_PID of U0 : label is "16'b0000001001001100";
  attribute LC_PROBE588_TYPE : integer;
  attribute LC_PROBE588_TYPE of U0 : label is 1;
  attribute LC_PROBE588_WIDTH : integer;
  attribute LC_PROBE588_WIDTH of U0 : label is 1;
  attribute LC_PROBE589_IS_DATA : string;
  attribute LC_PROBE589_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE589_IS_TRIG : string;
  attribute LC_PROBE589_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE589_MU_CNT : integer;
  attribute LC_PROBE589_MU_CNT of U0 : label is 1;
  attribute LC_PROBE589_PID : string;
  attribute LC_PROBE589_PID of U0 : label is "16'b0000001001001101";
  attribute LC_PROBE589_TYPE : integer;
  attribute LC_PROBE589_TYPE of U0 : label is 1;
  attribute LC_PROBE589_WIDTH : integer;
  attribute LC_PROBE589_WIDTH of U0 : label is 1;
  attribute LC_PROBE58_IS_DATA : string;
  attribute LC_PROBE58_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE58_IS_TRIG : string;
  attribute LC_PROBE58_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE58_MU_CNT : integer;
  attribute LC_PROBE58_MU_CNT of U0 : label is 1;
  attribute LC_PROBE58_PID : string;
  attribute LC_PROBE58_PID of U0 : label is "16'b0000000000111010";
  attribute LC_PROBE58_TYPE : integer;
  attribute LC_PROBE58_TYPE of U0 : label is 1;
  attribute LC_PROBE58_WIDTH : integer;
  attribute LC_PROBE58_WIDTH of U0 : label is 1;
  attribute LC_PROBE590_IS_DATA : string;
  attribute LC_PROBE590_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE590_IS_TRIG : string;
  attribute LC_PROBE590_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE590_MU_CNT : integer;
  attribute LC_PROBE590_MU_CNT of U0 : label is 1;
  attribute LC_PROBE590_PID : string;
  attribute LC_PROBE590_PID of U0 : label is "16'b0000001001001110";
  attribute LC_PROBE590_TYPE : integer;
  attribute LC_PROBE590_TYPE of U0 : label is 1;
  attribute LC_PROBE590_WIDTH : integer;
  attribute LC_PROBE590_WIDTH of U0 : label is 1;
  attribute LC_PROBE591_IS_DATA : string;
  attribute LC_PROBE591_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE591_IS_TRIG : string;
  attribute LC_PROBE591_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE591_MU_CNT : integer;
  attribute LC_PROBE591_MU_CNT of U0 : label is 1;
  attribute LC_PROBE591_PID : string;
  attribute LC_PROBE591_PID of U0 : label is "16'b0000001001001111";
  attribute LC_PROBE591_TYPE : integer;
  attribute LC_PROBE591_TYPE of U0 : label is 1;
  attribute LC_PROBE591_WIDTH : integer;
  attribute LC_PROBE591_WIDTH of U0 : label is 1;
  attribute LC_PROBE592_IS_DATA : string;
  attribute LC_PROBE592_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE592_IS_TRIG : string;
  attribute LC_PROBE592_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE592_MU_CNT : integer;
  attribute LC_PROBE592_MU_CNT of U0 : label is 1;
  attribute LC_PROBE592_PID : string;
  attribute LC_PROBE592_PID of U0 : label is "16'b0000001001010000";
  attribute LC_PROBE592_TYPE : integer;
  attribute LC_PROBE592_TYPE of U0 : label is 1;
  attribute LC_PROBE592_WIDTH : integer;
  attribute LC_PROBE592_WIDTH of U0 : label is 1;
  attribute LC_PROBE593_IS_DATA : string;
  attribute LC_PROBE593_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE593_IS_TRIG : string;
  attribute LC_PROBE593_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE593_MU_CNT : integer;
  attribute LC_PROBE593_MU_CNT of U0 : label is 1;
  attribute LC_PROBE593_PID : string;
  attribute LC_PROBE593_PID of U0 : label is "16'b0000001001010001";
  attribute LC_PROBE593_TYPE : integer;
  attribute LC_PROBE593_TYPE of U0 : label is 1;
  attribute LC_PROBE593_WIDTH : integer;
  attribute LC_PROBE593_WIDTH of U0 : label is 1;
  attribute LC_PROBE594_IS_DATA : string;
  attribute LC_PROBE594_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE594_IS_TRIG : string;
  attribute LC_PROBE594_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE594_MU_CNT : integer;
  attribute LC_PROBE594_MU_CNT of U0 : label is 1;
  attribute LC_PROBE594_PID : string;
  attribute LC_PROBE594_PID of U0 : label is "16'b0000001001010010";
  attribute LC_PROBE594_TYPE : integer;
  attribute LC_PROBE594_TYPE of U0 : label is 1;
  attribute LC_PROBE594_WIDTH : integer;
  attribute LC_PROBE594_WIDTH of U0 : label is 1;
  attribute LC_PROBE595_IS_DATA : string;
  attribute LC_PROBE595_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE595_IS_TRIG : string;
  attribute LC_PROBE595_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE595_MU_CNT : integer;
  attribute LC_PROBE595_MU_CNT of U0 : label is 1;
  attribute LC_PROBE595_PID : string;
  attribute LC_PROBE595_PID of U0 : label is "16'b0000001001010011";
  attribute LC_PROBE595_TYPE : integer;
  attribute LC_PROBE595_TYPE of U0 : label is 1;
  attribute LC_PROBE595_WIDTH : integer;
  attribute LC_PROBE595_WIDTH of U0 : label is 1;
  attribute LC_PROBE596_IS_DATA : string;
  attribute LC_PROBE596_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE596_IS_TRIG : string;
  attribute LC_PROBE596_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE596_MU_CNT : integer;
  attribute LC_PROBE596_MU_CNT of U0 : label is 1;
  attribute LC_PROBE596_PID : string;
  attribute LC_PROBE596_PID of U0 : label is "16'b0000001001010100";
  attribute LC_PROBE596_TYPE : integer;
  attribute LC_PROBE596_TYPE of U0 : label is 1;
  attribute LC_PROBE596_WIDTH : integer;
  attribute LC_PROBE596_WIDTH of U0 : label is 1;
  attribute LC_PROBE597_IS_DATA : string;
  attribute LC_PROBE597_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE597_IS_TRIG : string;
  attribute LC_PROBE597_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE597_MU_CNT : integer;
  attribute LC_PROBE597_MU_CNT of U0 : label is 1;
  attribute LC_PROBE597_PID : string;
  attribute LC_PROBE597_PID of U0 : label is "16'b0000001001010101";
  attribute LC_PROBE597_TYPE : integer;
  attribute LC_PROBE597_TYPE of U0 : label is 1;
  attribute LC_PROBE597_WIDTH : integer;
  attribute LC_PROBE597_WIDTH of U0 : label is 1;
  attribute LC_PROBE598_IS_DATA : string;
  attribute LC_PROBE598_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE598_IS_TRIG : string;
  attribute LC_PROBE598_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE598_MU_CNT : integer;
  attribute LC_PROBE598_MU_CNT of U0 : label is 1;
  attribute LC_PROBE598_PID : string;
  attribute LC_PROBE598_PID of U0 : label is "16'b0000001001010110";
  attribute LC_PROBE598_TYPE : integer;
  attribute LC_PROBE598_TYPE of U0 : label is 1;
  attribute LC_PROBE598_WIDTH : integer;
  attribute LC_PROBE598_WIDTH of U0 : label is 1;
  attribute LC_PROBE599_IS_DATA : string;
  attribute LC_PROBE599_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE599_IS_TRIG : string;
  attribute LC_PROBE599_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE599_MU_CNT : integer;
  attribute LC_PROBE599_MU_CNT of U0 : label is 1;
  attribute LC_PROBE599_PID : string;
  attribute LC_PROBE599_PID of U0 : label is "16'b0000001001010111";
  attribute LC_PROBE599_TYPE : integer;
  attribute LC_PROBE599_TYPE of U0 : label is 1;
  attribute LC_PROBE599_WIDTH : integer;
  attribute LC_PROBE599_WIDTH of U0 : label is 1;
  attribute LC_PROBE59_IS_DATA : string;
  attribute LC_PROBE59_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE59_IS_TRIG : string;
  attribute LC_PROBE59_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE59_MU_CNT : integer;
  attribute LC_PROBE59_MU_CNT of U0 : label is 1;
  attribute LC_PROBE59_PID : string;
  attribute LC_PROBE59_PID of U0 : label is "16'b0000000000111011";
  attribute LC_PROBE59_TYPE : integer;
  attribute LC_PROBE59_TYPE of U0 : label is 1;
  attribute LC_PROBE59_WIDTH : integer;
  attribute LC_PROBE59_WIDTH of U0 : label is 1;
  attribute LC_PROBE5_IS_DATA : string;
  attribute LC_PROBE5_IS_DATA of U0 : label is "1'b1";
  attribute LC_PROBE5_IS_TRIG : string;
  attribute LC_PROBE5_IS_TRIG of U0 : label is "1'b1";
  attribute LC_PROBE5_MU_CNT : integer;
  attribute LC_PROBE5_MU_CNT of U0 : label is 1;
  attribute LC_PROBE5_PID : string;
  attribute LC_PROBE5_PID of U0 : label is "16'b0000000000000101";
  attribute LC_PROBE5_TYPE : integer;
  attribute LC_PROBE5_TYPE of U0 : label is 0;
  attribute LC_PROBE5_WIDTH : integer;
  attribute LC_PROBE5_WIDTH of U0 : label is 32;
  attribute LC_PROBE600_IS_DATA : string;
  attribute LC_PROBE600_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE600_IS_TRIG : string;
  attribute LC_PROBE600_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE600_MU_CNT : integer;
  attribute LC_PROBE600_MU_CNT of U0 : label is 1;
  attribute LC_PROBE600_PID : string;
  attribute LC_PROBE600_PID of U0 : label is "16'b0000001001011000";
  attribute LC_PROBE600_TYPE : integer;
  attribute LC_PROBE600_TYPE of U0 : label is 1;
  attribute LC_PROBE600_WIDTH : integer;
  attribute LC_PROBE600_WIDTH of U0 : label is 1;
  attribute LC_PROBE601_IS_DATA : string;
  attribute LC_PROBE601_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE601_IS_TRIG : string;
  attribute LC_PROBE601_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE601_MU_CNT : integer;
  attribute LC_PROBE601_MU_CNT of U0 : label is 1;
  attribute LC_PROBE601_PID : string;
  attribute LC_PROBE601_PID of U0 : label is "16'b0000001001011001";
  attribute LC_PROBE601_TYPE : integer;
  attribute LC_PROBE601_TYPE of U0 : label is 1;
  attribute LC_PROBE601_WIDTH : integer;
  attribute LC_PROBE601_WIDTH of U0 : label is 1;
  attribute LC_PROBE602_IS_DATA : string;
  attribute LC_PROBE602_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE602_IS_TRIG : string;
  attribute LC_PROBE602_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE602_MU_CNT : integer;
  attribute LC_PROBE602_MU_CNT of U0 : label is 1;
  attribute LC_PROBE602_PID : string;
  attribute LC_PROBE602_PID of U0 : label is "16'b0000001001011010";
  attribute LC_PROBE602_TYPE : integer;
  attribute LC_PROBE602_TYPE of U0 : label is 1;
  attribute LC_PROBE602_WIDTH : integer;
  attribute LC_PROBE602_WIDTH of U0 : label is 1;
  attribute LC_PROBE603_IS_DATA : string;
  attribute LC_PROBE603_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE603_IS_TRIG : string;
  attribute LC_PROBE603_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE603_MU_CNT : integer;
  attribute LC_PROBE603_MU_CNT of U0 : label is 1;
  attribute LC_PROBE603_PID : string;
  attribute LC_PROBE603_PID of U0 : label is "16'b0000001001011011";
  attribute LC_PROBE603_TYPE : integer;
  attribute LC_PROBE603_TYPE of U0 : label is 1;
  attribute LC_PROBE603_WIDTH : integer;
  attribute LC_PROBE603_WIDTH of U0 : label is 1;
  attribute LC_PROBE604_IS_DATA : string;
  attribute LC_PROBE604_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE604_IS_TRIG : string;
  attribute LC_PROBE604_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE604_MU_CNT : integer;
  attribute LC_PROBE604_MU_CNT of U0 : label is 1;
  attribute LC_PROBE604_PID : string;
  attribute LC_PROBE604_PID of U0 : label is "16'b0000001001011100";
  attribute LC_PROBE604_TYPE : integer;
  attribute LC_PROBE604_TYPE of U0 : label is 1;
  attribute LC_PROBE604_WIDTH : integer;
  attribute LC_PROBE604_WIDTH of U0 : label is 1;
  attribute LC_PROBE605_IS_DATA : string;
  attribute LC_PROBE605_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE605_IS_TRIG : string;
  attribute LC_PROBE605_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE605_MU_CNT : integer;
  attribute LC_PROBE605_MU_CNT of U0 : label is 1;
  attribute LC_PROBE605_PID : string;
  attribute LC_PROBE605_PID of U0 : label is "16'b0000001001011101";
  attribute LC_PROBE605_TYPE : integer;
  attribute LC_PROBE605_TYPE of U0 : label is 1;
  attribute LC_PROBE605_WIDTH : integer;
  attribute LC_PROBE605_WIDTH of U0 : label is 1;
  attribute LC_PROBE606_IS_DATA : string;
  attribute LC_PROBE606_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE606_IS_TRIG : string;
  attribute LC_PROBE606_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE606_MU_CNT : integer;
  attribute LC_PROBE606_MU_CNT of U0 : label is 1;
  attribute LC_PROBE606_PID : string;
  attribute LC_PROBE606_PID of U0 : label is "16'b0000001001011110";
  attribute LC_PROBE606_TYPE : integer;
  attribute LC_PROBE606_TYPE of U0 : label is 1;
  attribute LC_PROBE606_WIDTH : integer;
  attribute LC_PROBE606_WIDTH of U0 : label is 1;
  attribute LC_PROBE607_IS_DATA : string;
  attribute LC_PROBE607_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE607_IS_TRIG : string;
  attribute LC_PROBE607_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE607_MU_CNT : integer;
  attribute LC_PROBE607_MU_CNT of U0 : label is 1;
  attribute LC_PROBE607_PID : string;
  attribute LC_PROBE607_PID of U0 : label is "16'b0000001001011111";
  attribute LC_PROBE607_TYPE : integer;
  attribute LC_PROBE607_TYPE of U0 : label is 1;
  attribute LC_PROBE607_WIDTH : integer;
  attribute LC_PROBE607_WIDTH of U0 : label is 1;
  attribute LC_PROBE608_IS_DATA : string;
  attribute LC_PROBE608_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE608_IS_TRIG : string;
  attribute LC_PROBE608_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE608_MU_CNT : integer;
  attribute LC_PROBE608_MU_CNT of U0 : label is 1;
  attribute LC_PROBE608_PID : string;
  attribute LC_PROBE608_PID of U0 : label is "16'b0000001001100000";
  attribute LC_PROBE608_TYPE : integer;
  attribute LC_PROBE608_TYPE of U0 : label is 1;
  attribute LC_PROBE608_WIDTH : integer;
  attribute LC_PROBE608_WIDTH of U0 : label is 1;
  attribute LC_PROBE609_IS_DATA : string;
  attribute LC_PROBE609_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE609_IS_TRIG : string;
  attribute LC_PROBE609_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE609_MU_CNT : integer;
  attribute LC_PROBE609_MU_CNT of U0 : label is 1;
  attribute LC_PROBE609_PID : string;
  attribute LC_PROBE609_PID of U0 : label is "16'b0000001001100001";
  attribute LC_PROBE609_TYPE : integer;
  attribute LC_PROBE609_TYPE of U0 : label is 1;
  attribute LC_PROBE609_WIDTH : integer;
  attribute LC_PROBE609_WIDTH of U0 : label is 1;
  attribute LC_PROBE60_IS_DATA : string;
  attribute LC_PROBE60_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE60_IS_TRIG : string;
  attribute LC_PROBE60_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE60_MU_CNT : integer;
  attribute LC_PROBE60_MU_CNT of U0 : label is 1;
  attribute LC_PROBE60_PID : string;
  attribute LC_PROBE60_PID of U0 : label is "16'b0000000000111100";
  attribute LC_PROBE60_TYPE : integer;
  attribute LC_PROBE60_TYPE of U0 : label is 1;
  attribute LC_PROBE60_WIDTH : integer;
  attribute LC_PROBE60_WIDTH of U0 : label is 1;
  attribute LC_PROBE610_IS_DATA : string;
  attribute LC_PROBE610_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE610_IS_TRIG : string;
  attribute LC_PROBE610_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE610_MU_CNT : integer;
  attribute LC_PROBE610_MU_CNT of U0 : label is 1;
  attribute LC_PROBE610_PID : string;
  attribute LC_PROBE610_PID of U0 : label is "16'b0000001001100010";
  attribute LC_PROBE610_TYPE : integer;
  attribute LC_PROBE610_TYPE of U0 : label is 1;
  attribute LC_PROBE610_WIDTH : integer;
  attribute LC_PROBE610_WIDTH of U0 : label is 1;
  attribute LC_PROBE611_IS_DATA : string;
  attribute LC_PROBE611_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE611_IS_TRIG : string;
  attribute LC_PROBE611_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE611_MU_CNT : integer;
  attribute LC_PROBE611_MU_CNT of U0 : label is 1;
  attribute LC_PROBE611_PID : string;
  attribute LC_PROBE611_PID of U0 : label is "16'b0000001001100011";
  attribute LC_PROBE611_TYPE : integer;
  attribute LC_PROBE611_TYPE of U0 : label is 1;
  attribute LC_PROBE611_WIDTH : integer;
  attribute LC_PROBE611_WIDTH of U0 : label is 1;
  attribute LC_PROBE612_IS_DATA : string;
  attribute LC_PROBE612_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE612_IS_TRIG : string;
  attribute LC_PROBE612_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE612_MU_CNT : integer;
  attribute LC_PROBE612_MU_CNT of U0 : label is 1;
  attribute LC_PROBE612_PID : string;
  attribute LC_PROBE612_PID of U0 : label is "16'b0000001001100100";
  attribute LC_PROBE612_TYPE : integer;
  attribute LC_PROBE612_TYPE of U0 : label is 1;
  attribute LC_PROBE612_WIDTH : integer;
  attribute LC_PROBE612_WIDTH of U0 : label is 1;
  attribute LC_PROBE613_IS_DATA : string;
  attribute LC_PROBE613_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE613_IS_TRIG : string;
  attribute LC_PROBE613_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE613_MU_CNT : integer;
  attribute LC_PROBE613_MU_CNT of U0 : label is 1;
  attribute LC_PROBE613_PID : string;
  attribute LC_PROBE613_PID of U0 : label is "16'b0000001001100101";
  attribute LC_PROBE613_TYPE : integer;
  attribute LC_PROBE613_TYPE of U0 : label is 1;
  attribute LC_PROBE613_WIDTH : integer;
  attribute LC_PROBE613_WIDTH of U0 : label is 1;
  attribute LC_PROBE614_IS_DATA : string;
  attribute LC_PROBE614_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE614_IS_TRIG : string;
  attribute LC_PROBE614_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE614_MU_CNT : integer;
  attribute LC_PROBE614_MU_CNT of U0 : label is 1;
  attribute LC_PROBE614_PID : string;
  attribute LC_PROBE614_PID of U0 : label is "16'b0000001001100110";
  attribute LC_PROBE614_TYPE : integer;
  attribute LC_PROBE614_TYPE of U0 : label is 1;
  attribute LC_PROBE614_WIDTH : integer;
  attribute LC_PROBE614_WIDTH of U0 : label is 1;
  attribute LC_PROBE615_IS_DATA : string;
  attribute LC_PROBE615_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE615_IS_TRIG : string;
  attribute LC_PROBE615_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE615_MU_CNT : integer;
  attribute LC_PROBE615_MU_CNT of U0 : label is 1;
  attribute LC_PROBE615_PID : string;
  attribute LC_PROBE615_PID of U0 : label is "16'b0000001001100111";
  attribute LC_PROBE615_TYPE : integer;
  attribute LC_PROBE615_TYPE of U0 : label is 1;
  attribute LC_PROBE615_WIDTH : integer;
  attribute LC_PROBE615_WIDTH of U0 : label is 1;
  attribute LC_PROBE616_IS_DATA : string;
  attribute LC_PROBE616_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE616_IS_TRIG : string;
  attribute LC_PROBE616_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE616_MU_CNT : integer;
  attribute LC_PROBE616_MU_CNT of U0 : label is 1;
  attribute LC_PROBE616_PID : string;
  attribute LC_PROBE616_PID of U0 : label is "16'b0000001001101000";
  attribute LC_PROBE616_TYPE : integer;
  attribute LC_PROBE616_TYPE of U0 : label is 1;
  attribute LC_PROBE616_WIDTH : integer;
  attribute LC_PROBE616_WIDTH of U0 : label is 1;
  attribute LC_PROBE617_IS_DATA : string;
  attribute LC_PROBE617_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE617_IS_TRIG : string;
  attribute LC_PROBE617_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE617_MU_CNT : integer;
  attribute LC_PROBE617_MU_CNT of U0 : label is 1;
  attribute LC_PROBE617_PID : string;
  attribute LC_PROBE617_PID of U0 : label is "16'b0000001001101001";
  attribute LC_PROBE617_TYPE : integer;
  attribute LC_PROBE617_TYPE of U0 : label is 1;
  attribute LC_PROBE617_WIDTH : integer;
  attribute LC_PROBE617_WIDTH of U0 : label is 1;
  attribute LC_PROBE618_IS_DATA : string;
  attribute LC_PROBE618_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE618_IS_TRIG : string;
  attribute LC_PROBE618_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE618_MU_CNT : integer;
  attribute LC_PROBE618_MU_CNT of U0 : label is 1;
  attribute LC_PROBE618_PID : string;
  attribute LC_PROBE618_PID of U0 : label is "16'b0000001001101010";
  attribute LC_PROBE618_TYPE : integer;
  attribute LC_PROBE618_TYPE of U0 : label is 1;
  attribute LC_PROBE618_WIDTH : integer;
  attribute LC_PROBE618_WIDTH of U0 : label is 1;
  attribute LC_PROBE619_IS_DATA : string;
  attribute LC_PROBE619_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE619_IS_TRIG : string;
  attribute LC_PROBE619_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE619_MU_CNT : integer;
  attribute LC_PROBE619_MU_CNT of U0 : label is 1;
  attribute LC_PROBE619_PID : string;
  attribute LC_PROBE619_PID of U0 : label is "16'b0000001001101011";
  attribute LC_PROBE619_TYPE : integer;
  attribute LC_PROBE619_TYPE of U0 : label is 1;
  attribute LC_PROBE619_WIDTH : integer;
  attribute LC_PROBE619_WIDTH of U0 : label is 1;
  attribute LC_PROBE61_IS_DATA : string;
  attribute LC_PROBE61_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE61_IS_TRIG : string;
  attribute LC_PROBE61_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE61_MU_CNT : integer;
  attribute LC_PROBE61_MU_CNT of U0 : label is 1;
  attribute LC_PROBE61_PID : string;
  attribute LC_PROBE61_PID of U0 : label is "16'b0000000000111101";
  attribute LC_PROBE61_TYPE : integer;
  attribute LC_PROBE61_TYPE of U0 : label is 1;
  attribute LC_PROBE61_WIDTH : integer;
  attribute LC_PROBE61_WIDTH of U0 : label is 1;
  attribute LC_PROBE620_IS_DATA : string;
  attribute LC_PROBE620_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE620_IS_TRIG : string;
  attribute LC_PROBE620_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE620_MU_CNT : integer;
  attribute LC_PROBE620_MU_CNT of U0 : label is 1;
  attribute LC_PROBE620_PID : string;
  attribute LC_PROBE620_PID of U0 : label is "16'b0000001001101100";
  attribute LC_PROBE620_TYPE : integer;
  attribute LC_PROBE620_TYPE of U0 : label is 1;
  attribute LC_PROBE620_WIDTH : integer;
  attribute LC_PROBE620_WIDTH of U0 : label is 1;
  attribute LC_PROBE621_IS_DATA : string;
  attribute LC_PROBE621_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE621_IS_TRIG : string;
  attribute LC_PROBE621_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE621_MU_CNT : integer;
  attribute LC_PROBE621_MU_CNT of U0 : label is 1;
  attribute LC_PROBE621_PID : string;
  attribute LC_PROBE621_PID of U0 : label is "16'b0000001001101101";
  attribute LC_PROBE621_TYPE : integer;
  attribute LC_PROBE621_TYPE of U0 : label is 1;
  attribute LC_PROBE621_WIDTH : integer;
  attribute LC_PROBE621_WIDTH of U0 : label is 1;
  attribute LC_PROBE622_IS_DATA : string;
  attribute LC_PROBE622_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE622_IS_TRIG : string;
  attribute LC_PROBE622_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE622_MU_CNT : integer;
  attribute LC_PROBE622_MU_CNT of U0 : label is 1;
  attribute LC_PROBE622_PID : string;
  attribute LC_PROBE622_PID of U0 : label is "16'b0000001001101110";
  attribute LC_PROBE622_TYPE : integer;
  attribute LC_PROBE622_TYPE of U0 : label is 1;
  attribute LC_PROBE622_WIDTH : integer;
  attribute LC_PROBE622_WIDTH of U0 : label is 1;
  attribute LC_PROBE623_IS_DATA : string;
  attribute LC_PROBE623_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE623_IS_TRIG : string;
  attribute LC_PROBE623_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE623_MU_CNT : integer;
  attribute LC_PROBE623_MU_CNT of U0 : label is 1;
  attribute LC_PROBE623_PID : string;
  attribute LC_PROBE623_PID of U0 : label is "16'b0000001001101111";
  attribute LC_PROBE623_TYPE : integer;
  attribute LC_PROBE623_TYPE of U0 : label is 1;
  attribute LC_PROBE623_WIDTH : integer;
  attribute LC_PROBE623_WIDTH of U0 : label is 1;
  attribute LC_PROBE624_IS_DATA : string;
  attribute LC_PROBE624_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE624_IS_TRIG : string;
  attribute LC_PROBE624_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE624_MU_CNT : integer;
  attribute LC_PROBE624_MU_CNT of U0 : label is 1;
  attribute LC_PROBE624_PID : string;
  attribute LC_PROBE624_PID of U0 : label is "16'b0000001001110000";
  attribute LC_PROBE624_TYPE : integer;
  attribute LC_PROBE624_TYPE of U0 : label is 1;
  attribute LC_PROBE624_WIDTH : integer;
  attribute LC_PROBE624_WIDTH of U0 : label is 1;
  attribute LC_PROBE625_IS_DATA : string;
  attribute LC_PROBE625_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE625_IS_TRIG : string;
  attribute LC_PROBE625_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE625_MU_CNT : integer;
  attribute LC_PROBE625_MU_CNT of U0 : label is 1;
  attribute LC_PROBE625_PID : string;
  attribute LC_PROBE625_PID of U0 : label is "16'b0000001001110001";
  attribute LC_PROBE625_TYPE : integer;
  attribute LC_PROBE625_TYPE of U0 : label is 1;
  attribute LC_PROBE625_WIDTH : integer;
  attribute LC_PROBE625_WIDTH of U0 : label is 1;
  attribute LC_PROBE626_IS_DATA : string;
  attribute LC_PROBE626_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE626_IS_TRIG : string;
  attribute LC_PROBE626_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE626_MU_CNT : integer;
  attribute LC_PROBE626_MU_CNT of U0 : label is 1;
  attribute LC_PROBE626_PID : string;
  attribute LC_PROBE626_PID of U0 : label is "16'b0000001001110010";
  attribute LC_PROBE626_TYPE : integer;
  attribute LC_PROBE626_TYPE of U0 : label is 1;
  attribute LC_PROBE626_WIDTH : integer;
  attribute LC_PROBE626_WIDTH of U0 : label is 1;
  attribute LC_PROBE627_IS_DATA : string;
  attribute LC_PROBE627_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE627_IS_TRIG : string;
  attribute LC_PROBE627_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE627_MU_CNT : integer;
  attribute LC_PROBE627_MU_CNT of U0 : label is 1;
  attribute LC_PROBE627_PID : string;
  attribute LC_PROBE627_PID of U0 : label is "16'b0000001001110011";
  attribute LC_PROBE627_TYPE : integer;
  attribute LC_PROBE627_TYPE of U0 : label is 1;
  attribute LC_PROBE627_WIDTH : integer;
  attribute LC_PROBE627_WIDTH of U0 : label is 1;
  attribute LC_PROBE628_IS_DATA : string;
  attribute LC_PROBE628_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE628_IS_TRIG : string;
  attribute LC_PROBE628_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE628_MU_CNT : integer;
  attribute LC_PROBE628_MU_CNT of U0 : label is 1;
  attribute LC_PROBE628_PID : string;
  attribute LC_PROBE628_PID of U0 : label is "16'b0000001001110100";
  attribute LC_PROBE628_TYPE : integer;
  attribute LC_PROBE628_TYPE of U0 : label is 1;
  attribute LC_PROBE628_WIDTH : integer;
  attribute LC_PROBE628_WIDTH of U0 : label is 1;
  attribute LC_PROBE629_IS_DATA : string;
  attribute LC_PROBE629_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE629_IS_TRIG : string;
  attribute LC_PROBE629_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE629_MU_CNT : integer;
  attribute LC_PROBE629_MU_CNT of U0 : label is 1;
  attribute LC_PROBE629_PID : string;
  attribute LC_PROBE629_PID of U0 : label is "16'b0000001001110101";
  attribute LC_PROBE629_TYPE : integer;
  attribute LC_PROBE629_TYPE of U0 : label is 1;
  attribute LC_PROBE629_WIDTH : integer;
  attribute LC_PROBE629_WIDTH of U0 : label is 1;
  attribute LC_PROBE62_IS_DATA : string;
  attribute LC_PROBE62_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE62_IS_TRIG : string;
  attribute LC_PROBE62_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE62_MU_CNT : integer;
  attribute LC_PROBE62_MU_CNT of U0 : label is 1;
  attribute LC_PROBE62_PID : string;
  attribute LC_PROBE62_PID of U0 : label is "16'b0000000000111110";
  attribute LC_PROBE62_TYPE : integer;
  attribute LC_PROBE62_TYPE of U0 : label is 1;
  attribute LC_PROBE62_WIDTH : integer;
  attribute LC_PROBE62_WIDTH of U0 : label is 1;
  attribute LC_PROBE630_IS_DATA : string;
  attribute LC_PROBE630_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE630_IS_TRIG : string;
  attribute LC_PROBE630_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE630_MU_CNT : integer;
  attribute LC_PROBE630_MU_CNT of U0 : label is 1;
  attribute LC_PROBE630_PID : string;
  attribute LC_PROBE630_PID of U0 : label is "16'b0000001001110110";
  attribute LC_PROBE630_TYPE : integer;
  attribute LC_PROBE630_TYPE of U0 : label is 1;
  attribute LC_PROBE630_WIDTH : integer;
  attribute LC_PROBE630_WIDTH of U0 : label is 1;
  attribute LC_PROBE631_IS_DATA : string;
  attribute LC_PROBE631_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE631_IS_TRIG : string;
  attribute LC_PROBE631_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE631_MU_CNT : integer;
  attribute LC_PROBE631_MU_CNT of U0 : label is 1;
  attribute LC_PROBE631_PID : string;
  attribute LC_PROBE631_PID of U0 : label is "16'b0000001001110111";
  attribute LC_PROBE631_TYPE : integer;
  attribute LC_PROBE631_TYPE of U0 : label is 1;
  attribute LC_PROBE631_WIDTH : integer;
  attribute LC_PROBE631_WIDTH of U0 : label is 1;
  attribute LC_PROBE632_IS_DATA : string;
  attribute LC_PROBE632_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE632_IS_TRIG : string;
  attribute LC_PROBE632_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE632_MU_CNT : integer;
  attribute LC_PROBE632_MU_CNT of U0 : label is 1;
  attribute LC_PROBE632_PID : string;
  attribute LC_PROBE632_PID of U0 : label is "16'b0000001001111000";
  attribute LC_PROBE632_TYPE : integer;
  attribute LC_PROBE632_TYPE of U0 : label is 1;
  attribute LC_PROBE632_WIDTH : integer;
  attribute LC_PROBE632_WIDTH of U0 : label is 1;
  attribute LC_PROBE633_IS_DATA : string;
  attribute LC_PROBE633_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE633_IS_TRIG : string;
  attribute LC_PROBE633_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE633_MU_CNT : integer;
  attribute LC_PROBE633_MU_CNT of U0 : label is 1;
  attribute LC_PROBE633_PID : string;
  attribute LC_PROBE633_PID of U0 : label is "16'b0000001001111001";
  attribute LC_PROBE633_TYPE : integer;
  attribute LC_PROBE633_TYPE of U0 : label is 1;
  attribute LC_PROBE633_WIDTH : integer;
  attribute LC_PROBE633_WIDTH of U0 : label is 1;
  attribute LC_PROBE634_IS_DATA : string;
  attribute LC_PROBE634_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE634_IS_TRIG : string;
  attribute LC_PROBE634_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE634_MU_CNT : integer;
  attribute LC_PROBE634_MU_CNT of U0 : label is 1;
  attribute LC_PROBE634_PID : string;
  attribute LC_PROBE634_PID of U0 : label is "16'b0000001001111010";
  attribute LC_PROBE634_TYPE : integer;
  attribute LC_PROBE634_TYPE of U0 : label is 1;
  attribute LC_PROBE634_WIDTH : integer;
  attribute LC_PROBE634_WIDTH of U0 : label is 1;
  attribute LC_PROBE635_IS_DATA : string;
  attribute LC_PROBE635_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE635_IS_TRIG : string;
  attribute LC_PROBE635_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE635_MU_CNT : integer;
  attribute LC_PROBE635_MU_CNT of U0 : label is 1;
  attribute LC_PROBE635_PID : string;
  attribute LC_PROBE635_PID of U0 : label is "16'b0000001001111011";
  attribute LC_PROBE635_TYPE : integer;
  attribute LC_PROBE635_TYPE of U0 : label is 1;
  attribute LC_PROBE635_WIDTH : integer;
  attribute LC_PROBE635_WIDTH of U0 : label is 1;
  attribute LC_PROBE636_IS_DATA : string;
  attribute LC_PROBE636_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE636_IS_TRIG : string;
  attribute LC_PROBE636_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE636_MU_CNT : integer;
  attribute LC_PROBE636_MU_CNT of U0 : label is 1;
  attribute LC_PROBE636_PID : string;
  attribute LC_PROBE636_PID of U0 : label is "16'b0000001001111100";
  attribute LC_PROBE636_TYPE : integer;
  attribute LC_PROBE636_TYPE of U0 : label is 1;
  attribute LC_PROBE636_WIDTH : integer;
  attribute LC_PROBE636_WIDTH of U0 : label is 1;
  attribute LC_PROBE637_IS_DATA : string;
  attribute LC_PROBE637_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE637_IS_TRIG : string;
  attribute LC_PROBE637_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE637_MU_CNT : integer;
  attribute LC_PROBE637_MU_CNT of U0 : label is 1;
  attribute LC_PROBE637_PID : string;
  attribute LC_PROBE637_PID of U0 : label is "16'b0000001001111101";
  attribute LC_PROBE637_TYPE : integer;
  attribute LC_PROBE637_TYPE of U0 : label is 1;
  attribute LC_PROBE637_WIDTH : integer;
  attribute LC_PROBE637_WIDTH of U0 : label is 1;
  attribute LC_PROBE638_IS_DATA : string;
  attribute LC_PROBE638_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE638_IS_TRIG : string;
  attribute LC_PROBE638_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE638_MU_CNT : integer;
  attribute LC_PROBE638_MU_CNT of U0 : label is 1;
  attribute LC_PROBE638_PID : string;
  attribute LC_PROBE638_PID of U0 : label is "16'b0000001001111110";
  attribute LC_PROBE638_TYPE : integer;
  attribute LC_PROBE638_TYPE of U0 : label is 1;
  attribute LC_PROBE638_WIDTH : integer;
  attribute LC_PROBE638_WIDTH of U0 : label is 1;
  attribute LC_PROBE639_IS_DATA : string;
  attribute LC_PROBE639_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE639_IS_TRIG : string;
  attribute LC_PROBE639_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE639_MU_CNT : integer;
  attribute LC_PROBE639_MU_CNT of U0 : label is 1;
  attribute LC_PROBE639_PID : string;
  attribute LC_PROBE639_PID of U0 : label is "16'b0000001001111111";
  attribute LC_PROBE639_TYPE : integer;
  attribute LC_PROBE639_TYPE of U0 : label is 1;
  attribute LC_PROBE639_WIDTH : integer;
  attribute LC_PROBE639_WIDTH of U0 : label is 1;
  attribute LC_PROBE63_IS_DATA : string;
  attribute LC_PROBE63_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE63_IS_TRIG : string;
  attribute LC_PROBE63_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE63_MU_CNT : integer;
  attribute LC_PROBE63_MU_CNT of U0 : label is 1;
  attribute LC_PROBE63_PID : string;
  attribute LC_PROBE63_PID of U0 : label is "16'b0000000000111111";
  attribute LC_PROBE63_TYPE : integer;
  attribute LC_PROBE63_TYPE of U0 : label is 1;
  attribute LC_PROBE63_WIDTH : integer;
  attribute LC_PROBE63_WIDTH of U0 : label is 1;
  attribute LC_PROBE640_IS_DATA : string;
  attribute LC_PROBE640_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE640_IS_TRIG : string;
  attribute LC_PROBE640_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE640_MU_CNT : integer;
  attribute LC_PROBE640_MU_CNT of U0 : label is 1;
  attribute LC_PROBE640_PID : string;
  attribute LC_PROBE640_PID of U0 : label is "16'b0000001010000000";
  attribute LC_PROBE640_TYPE : integer;
  attribute LC_PROBE640_TYPE of U0 : label is 1;
  attribute LC_PROBE640_WIDTH : integer;
  attribute LC_PROBE640_WIDTH of U0 : label is 1;
  attribute LC_PROBE641_IS_DATA : string;
  attribute LC_PROBE641_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE641_IS_TRIG : string;
  attribute LC_PROBE641_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE641_MU_CNT : integer;
  attribute LC_PROBE641_MU_CNT of U0 : label is 1;
  attribute LC_PROBE641_PID : string;
  attribute LC_PROBE641_PID of U0 : label is "16'b0000001010000001";
  attribute LC_PROBE641_TYPE : integer;
  attribute LC_PROBE641_TYPE of U0 : label is 1;
  attribute LC_PROBE641_WIDTH : integer;
  attribute LC_PROBE641_WIDTH of U0 : label is 1;
  attribute LC_PROBE642_IS_DATA : string;
  attribute LC_PROBE642_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE642_IS_TRIG : string;
  attribute LC_PROBE642_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE642_MU_CNT : integer;
  attribute LC_PROBE642_MU_CNT of U0 : label is 1;
  attribute LC_PROBE642_PID : string;
  attribute LC_PROBE642_PID of U0 : label is "16'b0000001010000010";
  attribute LC_PROBE642_TYPE : integer;
  attribute LC_PROBE642_TYPE of U0 : label is 1;
  attribute LC_PROBE642_WIDTH : integer;
  attribute LC_PROBE642_WIDTH of U0 : label is 1;
  attribute LC_PROBE643_IS_DATA : string;
  attribute LC_PROBE643_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE643_IS_TRIG : string;
  attribute LC_PROBE643_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE643_MU_CNT : integer;
  attribute LC_PROBE643_MU_CNT of U0 : label is 1;
  attribute LC_PROBE643_PID : string;
  attribute LC_PROBE643_PID of U0 : label is "16'b0000001010000011";
  attribute LC_PROBE643_TYPE : integer;
  attribute LC_PROBE643_TYPE of U0 : label is 1;
  attribute LC_PROBE643_WIDTH : integer;
  attribute LC_PROBE643_WIDTH of U0 : label is 1;
  attribute LC_PROBE644_IS_DATA : string;
  attribute LC_PROBE644_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE644_IS_TRIG : string;
  attribute LC_PROBE644_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE644_MU_CNT : integer;
  attribute LC_PROBE644_MU_CNT of U0 : label is 1;
  attribute LC_PROBE644_PID : string;
  attribute LC_PROBE644_PID of U0 : label is "16'b0000001010000100";
  attribute LC_PROBE644_TYPE : integer;
  attribute LC_PROBE644_TYPE of U0 : label is 1;
  attribute LC_PROBE644_WIDTH : integer;
  attribute LC_PROBE644_WIDTH of U0 : label is 1;
  attribute LC_PROBE645_IS_DATA : string;
  attribute LC_PROBE645_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE645_IS_TRIG : string;
  attribute LC_PROBE645_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE645_MU_CNT : integer;
  attribute LC_PROBE645_MU_CNT of U0 : label is 1;
  attribute LC_PROBE645_PID : string;
  attribute LC_PROBE645_PID of U0 : label is "16'b0000001010000101";
  attribute LC_PROBE645_TYPE : integer;
  attribute LC_PROBE645_TYPE of U0 : label is 1;
  attribute LC_PROBE645_WIDTH : integer;
  attribute LC_PROBE645_WIDTH of U0 : label is 1;
  attribute LC_PROBE646_IS_DATA : string;
  attribute LC_PROBE646_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE646_IS_TRIG : string;
  attribute LC_PROBE646_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE646_MU_CNT : integer;
  attribute LC_PROBE646_MU_CNT of U0 : label is 1;
  attribute LC_PROBE646_PID : string;
  attribute LC_PROBE646_PID of U0 : label is "16'b0000001010000110";
  attribute LC_PROBE646_TYPE : integer;
  attribute LC_PROBE646_TYPE of U0 : label is 1;
  attribute LC_PROBE646_WIDTH : integer;
  attribute LC_PROBE646_WIDTH of U0 : label is 1;
  attribute LC_PROBE647_IS_DATA : string;
  attribute LC_PROBE647_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE647_IS_TRIG : string;
  attribute LC_PROBE647_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE647_MU_CNT : integer;
  attribute LC_PROBE647_MU_CNT of U0 : label is 1;
  attribute LC_PROBE647_PID : string;
  attribute LC_PROBE647_PID of U0 : label is "16'b0000001010000111";
  attribute LC_PROBE647_TYPE : integer;
  attribute LC_PROBE647_TYPE of U0 : label is 1;
  attribute LC_PROBE647_WIDTH : integer;
  attribute LC_PROBE647_WIDTH of U0 : label is 1;
  attribute LC_PROBE648_IS_DATA : string;
  attribute LC_PROBE648_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE648_IS_TRIG : string;
  attribute LC_PROBE648_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE648_MU_CNT : integer;
  attribute LC_PROBE648_MU_CNT of U0 : label is 1;
  attribute LC_PROBE648_PID : string;
  attribute LC_PROBE648_PID of U0 : label is "16'b0000001010001000";
  attribute LC_PROBE648_TYPE : integer;
  attribute LC_PROBE648_TYPE of U0 : label is 1;
  attribute LC_PROBE648_WIDTH : integer;
  attribute LC_PROBE648_WIDTH of U0 : label is 1;
  attribute LC_PROBE649_IS_DATA : string;
  attribute LC_PROBE649_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE649_IS_TRIG : string;
  attribute LC_PROBE649_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE649_MU_CNT : integer;
  attribute LC_PROBE649_MU_CNT of U0 : label is 1;
  attribute LC_PROBE649_PID : string;
  attribute LC_PROBE649_PID of U0 : label is "16'b0000001010001001";
  attribute LC_PROBE649_TYPE : integer;
  attribute LC_PROBE649_TYPE of U0 : label is 1;
  attribute LC_PROBE649_WIDTH : integer;
  attribute LC_PROBE649_WIDTH of U0 : label is 1;
  attribute LC_PROBE64_IS_DATA : string;
  attribute LC_PROBE64_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE64_IS_TRIG : string;
  attribute LC_PROBE64_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE64_MU_CNT : integer;
  attribute LC_PROBE64_MU_CNT of U0 : label is 1;
  attribute LC_PROBE64_PID : string;
  attribute LC_PROBE64_PID of U0 : label is "16'b0000000001000000";
  attribute LC_PROBE64_TYPE : integer;
  attribute LC_PROBE64_TYPE of U0 : label is 1;
  attribute LC_PROBE64_WIDTH : integer;
  attribute LC_PROBE64_WIDTH of U0 : label is 1;
  attribute LC_PROBE650_IS_DATA : string;
  attribute LC_PROBE650_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE650_IS_TRIG : string;
  attribute LC_PROBE650_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE650_MU_CNT : integer;
  attribute LC_PROBE650_MU_CNT of U0 : label is 1;
  attribute LC_PROBE650_PID : string;
  attribute LC_PROBE650_PID of U0 : label is "16'b0000001010001010";
  attribute LC_PROBE650_TYPE : integer;
  attribute LC_PROBE650_TYPE of U0 : label is 1;
  attribute LC_PROBE650_WIDTH : integer;
  attribute LC_PROBE650_WIDTH of U0 : label is 1;
  attribute LC_PROBE651_IS_DATA : string;
  attribute LC_PROBE651_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE651_IS_TRIG : string;
  attribute LC_PROBE651_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE651_MU_CNT : integer;
  attribute LC_PROBE651_MU_CNT of U0 : label is 1;
  attribute LC_PROBE651_PID : string;
  attribute LC_PROBE651_PID of U0 : label is "16'b0000001010001011";
  attribute LC_PROBE651_TYPE : integer;
  attribute LC_PROBE651_TYPE of U0 : label is 1;
  attribute LC_PROBE651_WIDTH : integer;
  attribute LC_PROBE651_WIDTH of U0 : label is 1;
  attribute LC_PROBE652_IS_DATA : string;
  attribute LC_PROBE652_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE652_IS_TRIG : string;
  attribute LC_PROBE652_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE652_MU_CNT : integer;
  attribute LC_PROBE652_MU_CNT of U0 : label is 1;
  attribute LC_PROBE652_PID : string;
  attribute LC_PROBE652_PID of U0 : label is "16'b0000001010001100";
  attribute LC_PROBE652_TYPE : integer;
  attribute LC_PROBE652_TYPE of U0 : label is 1;
  attribute LC_PROBE652_WIDTH : integer;
  attribute LC_PROBE652_WIDTH of U0 : label is 1;
  attribute LC_PROBE653_IS_DATA : string;
  attribute LC_PROBE653_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE653_IS_TRIG : string;
  attribute LC_PROBE653_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE653_MU_CNT : integer;
  attribute LC_PROBE653_MU_CNT of U0 : label is 1;
  attribute LC_PROBE653_PID : string;
  attribute LC_PROBE653_PID of U0 : label is "16'b0000001010001101";
  attribute LC_PROBE653_TYPE : integer;
  attribute LC_PROBE653_TYPE of U0 : label is 1;
  attribute LC_PROBE653_WIDTH : integer;
  attribute LC_PROBE653_WIDTH of U0 : label is 1;
  attribute LC_PROBE654_IS_DATA : string;
  attribute LC_PROBE654_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE654_IS_TRIG : string;
  attribute LC_PROBE654_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE654_MU_CNT : integer;
  attribute LC_PROBE654_MU_CNT of U0 : label is 1;
  attribute LC_PROBE654_PID : string;
  attribute LC_PROBE654_PID of U0 : label is "16'b0000001010001110";
  attribute LC_PROBE654_TYPE : integer;
  attribute LC_PROBE654_TYPE of U0 : label is 1;
  attribute LC_PROBE654_WIDTH : integer;
  attribute LC_PROBE654_WIDTH of U0 : label is 1;
  attribute LC_PROBE655_IS_DATA : string;
  attribute LC_PROBE655_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE655_IS_TRIG : string;
  attribute LC_PROBE655_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE655_MU_CNT : integer;
  attribute LC_PROBE655_MU_CNT of U0 : label is 1;
  attribute LC_PROBE655_PID : string;
  attribute LC_PROBE655_PID of U0 : label is "16'b0000001010001111";
  attribute LC_PROBE655_TYPE : integer;
  attribute LC_PROBE655_TYPE of U0 : label is 1;
  attribute LC_PROBE655_WIDTH : integer;
  attribute LC_PROBE655_WIDTH of U0 : label is 1;
  attribute LC_PROBE656_IS_DATA : string;
  attribute LC_PROBE656_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE656_IS_TRIG : string;
  attribute LC_PROBE656_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE656_MU_CNT : integer;
  attribute LC_PROBE656_MU_CNT of U0 : label is 1;
  attribute LC_PROBE656_PID : string;
  attribute LC_PROBE656_PID of U0 : label is "16'b0000001010010000";
  attribute LC_PROBE656_TYPE : integer;
  attribute LC_PROBE656_TYPE of U0 : label is 1;
  attribute LC_PROBE656_WIDTH : integer;
  attribute LC_PROBE656_WIDTH of U0 : label is 1;
  attribute LC_PROBE657_IS_DATA : string;
  attribute LC_PROBE657_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE657_IS_TRIG : string;
  attribute LC_PROBE657_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE657_MU_CNT : integer;
  attribute LC_PROBE657_MU_CNT of U0 : label is 1;
  attribute LC_PROBE657_PID : string;
  attribute LC_PROBE657_PID of U0 : label is "16'b0000001010010001";
  attribute LC_PROBE657_TYPE : integer;
  attribute LC_PROBE657_TYPE of U0 : label is 1;
  attribute LC_PROBE657_WIDTH : integer;
  attribute LC_PROBE657_WIDTH of U0 : label is 1;
  attribute LC_PROBE658_IS_DATA : string;
  attribute LC_PROBE658_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE658_IS_TRIG : string;
  attribute LC_PROBE658_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE658_MU_CNT : integer;
  attribute LC_PROBE658_MU_CNT of U0 : label is 1;
  attribute LC_PROBE658_PID : string;
  attribute LC_PROBE658_PID of U0 : label is "16'b0000001010010010";
  attribute LC_PROBE658_TYPE : integer;
  attribute LC_PROBE658_TYPE of U0 : label is 1;
  attribute LC_PROBE658_WIDTH : integer;
  attribute LC_PROBE658_WIDTH of U0 : label is 1;
  attribute LC_PROBE659_IS_DATA : string;
  attribute LC_PROBE659_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE659_IS_TRIG : string;
  attribute LC_PROBE659_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE659_MU_CNT : integer;
  attribute LC_PROBE659_MU_CNT of U0 : label is 1;
  attribute LC_PROBE659_PID : string;
  attribute LC_PROBE659_PID of U0 : label is "16'b0000001010010011";
  attribute LC_PROBE659_TYPE : integer;
  attribute LC_PROBE659_TYPE of U0 : label is 1;
  attribute LC_PROBE659_WIDTH : integer;
  attribute LC_PROBE659_WIDTH of U0 : label is 1;
  attribute LC_PROBE65_IS_DATA : string;
  attribute LC_PROBE65_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE65_IS_TRIG : string;
  attribute LC_PROBE65_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE65_MU_CNT : integer;
  attribute LC_PROBE65_MU_CNT of U0 : label is 1;
  attribute LC_PROBE65_PID : string;
  attribute LC_PROBE65_PID of U0 : label is "16'b0000000001000001";
  attribute LC_PROBE65_TYPE : integer;
  attribute LC_PROBE65_TYPE of U0 : label is 1;
  attribute LC_PROBE65_WIDTH : integer;
  attribute LC_PROBE65_WIDTH of U0 : label is 1;
  attribute LC_PROBE660_IS_DATA : string;
  attribute LC_PROBE660_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE660_IS_TRIG : string;
  attribute LC_PROBE660_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE660_MU_CNT : integer;
  attribute LC_PROBE660_MU_CNT of U0 : label is 1;
  attribute LC_PROBE660_PID : string;
  attribute LC_PROBE660_PID of U0 : label is "16'b0000001010010100";
  attribute LC_PROBE660_TYPE : integer;
  attribute LC_PROBE660_TYPE of U0 : label is 1;
  attribute LC_PROBE660_WIDTH : integer;
  attribute LC_PROBE660_WIDTH of U0 : label is 1;
  attribute LC_PROBE661_IS_DATA : string;
  attribute LC_PROBE661_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE661_IS_TRIG : string;
  attribute LC_PROBE661_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE661_MU_CNT : integer;
  attribute LC_PROBE661_MU_CNT of U0 : label is 1;
  attribute LC_PROBE661_PID : string;
  attribute LC_PROBE661_PID of U0 : label is "16'b0000001010010101";
  attribute LC_PROBE661_TYPE : integer;
  attribute LC_PROBE661_TYPE of U0 : label is 1;
  attribute LC_PROBE661_WIDTH : integer;
  attribute LC_PROBE661_WIDTH of U0 : label is 1;
  attribute LC_PROBE662_IS_DATA : string;
  attribute LC_PROBE662_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE662_IS_TRIG : string;
  attribute LC_PROBE662_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE662_MU_CNT : integer;
  attribute LC_PROBE662_MU_CNT of U0 : label is 1;
  attribute LC_PROBE662_PID : string;
  attribute LC_PROBE662_PID of U0 : label is "16'b0000001010010110";
  attribute LC_PROBE662_TYPE : integer;
  attribute LC_PROBE662_TYPE of U0 : label is 1;
  attribute LC_PROBE662_WIDTH : integer;
  attribute LC_PROBE662_WIDTH of U0 : label is 1;
  attribute LC_PROBE663_IS_DATA : string;
  attribute LC_PROBE663_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE663_IS_TRIG : string;
  attribute LC_PROBE663_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE663_MU_CNT : integer;
  attribute LC_PROBE663_MU_CNT of U0 : label is 1;
  attribute LC_PROBE663_PID : string;
  attribute LC_PROBE663_PID of U0 : label is "16'b0000001010010111";
  attribute LC_PROBE663_TYPE : integer;
  attribute LC_PROBE663_TYPE of U0 : label is 1;
  attribute LC_PROBE663_WIDTH : integer;
  attribute LC_PROBE663_WIDTH of U0 : label is 1;
  attribute LC_PROBE664_IS_DATA : string;
  attribute LC_PROBE664_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE664_IS_TRIG : string;
  attribute LC_PROBE664_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE664_MU_CNT : integer;
  attribute LC_PROBE664_MU_CNT of U0 : label is 1;
  attribute LC_PROBE664_PID : string;
  attribute LC_PROBE664_PID of U0 : label is "16'b0000001010011000";
  attribute LC_PROBE664_TYPE : integer;
  attribute LC_PROBE664_TYPE of U0 : label is 1;
  attribute LC_PROBE664_WIDTH : integer;
  attribute LC_PROBE664_WIDTH of U0 : label is 1;
  attribute LC_PROBE665_IS_DATA : string;
  attribute LC_PROBE665_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE665_IS_TRIG : string;
  attribute LC_PROBE665_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE665_MU_CNT : integer;
  attribute LC_PROBE665_MU_CNT of U0 : label is 1;
  attribute LC_PROBE665_PID : string;
  attribute LC_PROBE665_PID of U0 : label is "16'b0000001010011001";
  attribute LC_PROBE665_TYPE : integer;
  attribute LC_PROBE665_TYPE of U0 : label is 1;
  attribute LC_PROBE665_WIDTH : integer;
  attribute LC_PROBE665_WIDTH of U0 : label is 1;
  attribute LC_PROBE666_IS_DATA : string;
  attribute LC_PROBE666_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE666_IS_TRIG : string;
  attribute LC_PROBE666_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE666_MU_CNT : integer;
  attribute LC_PROBE666_MU_CNT of U0 : label is 1;
  attribute LC_PROBE666_PID : string;
  attribute LC_PROBE666_PID of U0 : label is "16'b0000001010011010";
  attribute LC_PROBE666_TYPE : integer;
  attribute LC_PROBE666_TYPE of U0 : label is 1;
  attribute LC_PROBE666_WIDTH : integer;
  attribute LC_PROBE666_WIDTH of U0 : label is 1;
  attribute LC_PROBE667_IS_DATA : string;
  attribute LC_PROBE667_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE667_IS_TRIG : string;
  attribute LC_PROBE667_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE667_MU_CNT : integer;
  attribute LC_PROBE667_MU_CNT of U0 : label is 1;
  attribute LC_PROBE667_PID : string;
  attribute LC_PROBE667_PID of U0 : label is "16'b0000001010011011";
  attribute LC_PROBE667_TYPE : integer;
  attribute LC_PROBE667_TYPE of U0 : label is 1;
  attribute LC_PROBE667_WIDTH : integer;
  attribute LC_PROBE667_WIDTH of U0 : label is 1;
  attribute LC_PROBE668_IS_DATA : string;
  attribute LC_PROBE668_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE668_IS_TRIG : string;
  attribute LC_PROBE668_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE668_MU_CNT : integer;
  attribute LC_PROBE668_MU_CNT of U0 : label is 1;
  attribute LC_PROBE668_PID : string;
  attribute LC_PROBE668_PID of U0 : label is "16'b0000001010011100";
  attribute LC_PROBE668_TYPE : integer;
  attribute LC_PROBE668_TYPE of U0 : label is 1;
  attribute LC_PROBE668_WIDTH : integer;
  attribute LC_PROBE668_WIDTH of U0 : label is 1;
  attribute LC_PROBE669_IS_DATA : string;
  attribute LC_PROBE669_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE669_IS_TRIG : string;
  attribute LC_PROBE669_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE669_MU_CNT : integer;
  attribute LC_PROBE669_MU_CNT of U0 : label is 1;
  attribute LC_PROBE669_PID : string;
  attribute LC_PROBE669_PID of U0 : label is "16'b0000001010011101";
  attribute LC_PROBE669_TYPE : integer;
  attribute LC_PROBE669_TYPE of U0 : label is 1;
  attribute LC_PROBE669_WIDTH : integer;
  attribute LC_PROBE669_WIDTH of U0 : label is 1;
  attribute LC_PROBE66_IS_DATA : string;
  attribute LC_PROBE66_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE66_IS_TRIG : string;
  attribute LC_PROBE66_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE66_MU_CNT : integer;
  attribute LC_PROBE66_MU_CNT of U0 : label is 1;
  attribute LC_PROBE66_PID : string;
  attribute LC_PROBE66_PID of U0 : label is "16'b0000000001000010";
  attribute LC_PROBE66_TYPE : integer;
  attribute LC_PROBE66_TYPE of U0 : label is 1;
  attribute LC_PROBE66_WIDTH : integer;
  attribute LC_PROBE66_WIDTH of U0 : label is 1;
  attribute LC_PROBE670_IS_DATA : string;
  attribute LC_PROBE670_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE670_IS_TRIG : string;
  attribute LC_PROBE670_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE670_MU_CNT : integer;
  attribute LC_PROBE670_MU_CNT of U0 : label is 1;
  attribute LC_PROBE670_PID : string;
  attribute LC_PROBE670_PID of U0 : label is "16'b0000001010011110";
  attribute LC_PROBE670_TYPE : integer;
  attribute LC_PROBE670_TYPE of U0 : label is 1;
  attribute LC_PROBE670_WIDTH : integer;
  attribute LC_PROBE670_WIDTH of U0 : label is 1;
  attribute LC_PROBE671_IS_DATA : string;
  attribute LC_PROBE671_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE671_IS_TRIG : string;
  attribute LC_PROBE671_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE671_MU_CNT : integer;
  attribute LC_PROBE671_MU_CNT of U0 : label is 1;
  attribute LC_PROBE671_PID : string;
  attribute LC_PROBE671_PID of U0 : label is "16'b0000001010011111";
  attribute LC_PROBE671_TYPE : integer;
  attribute LC_PROBE671_TYPE of U0 : label is 1;
  attribute LC_PROBE671_WIDTH : integer;
  attribute LC_PROBE671_WIDTH of U0 : label is 1;
  attribute LC_PROBE672_IS_DATA : string;
  attribute LC_PROBE672_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE672_IS_TRIG : string;
  attribute LC_PROBE672_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE672_MU_CNT : integer;
  attribute LC_PROBE672_MU_CNT of U0 : label is 1;
  attribute LC_PROBE672_PID : string;
  attribute LC_PROBE672_PID of U0 : label is "16'b0000001010100000";
  attribute LC_PROBE672_TYPE : integer;
  attribute LC_PROBE672_TYPE of U0 : label is 1;
  attribute LC_PROBE672_WIDTH : integer;
  attribute LC_PROBE672_WIDTH of U0 : label is 1;
  attribute LC_PROBE673_IS_DATA : string;
  attribute LC_PROBE673_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE673_IS_TRIG : string;
  attribute LC_PROBE673_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE673_MU_CNT : integer;
  attribute LC_PROBE673_MU_CNT of U0 : label is 1;
  attribute LC_PROBE673_PID : string;
  attribute LC_PROBE673_PID of U0 : label is "16'b0000001010100001";
  attribute LC_PROBE673_TYPE : integer;
  attribute LC_PROBE673_TYPE of U0 : label is 1;
  attribute LC_PROBE673_WIDTH : integer;
  attribute LC_PROBE673_WIDTH of U0 : label is 1;
  attribute LC_PROBE674_IS_DATA : string;
  attribute LC_PROBE674_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE674_IS_TRIG : string;
  attribute LC_PROBE674_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE674_MU_CNT : integer;
  attribute LC_PROBE674_MU_CNT of U0 : label is 1;
  attribute LC_PROBE674_PID : string;
  attribute LC_PROBE674_PID of U0 : label is "16'b0000001010100010";
  attribute LC_PROBE674_TYPE : integer;
  attribute LC_PROBE674_TYPE of U0 : label is 1;
  attribute LC_PROBE674_WIDTH : integer;
  attribute LC_PROBE674_WIDTH of U0 : label is 1;
  attribute LC_PROBE675_IS_DATA : string;
  attribute LC_PROBE675_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE675_IS_TRIG : string;
  attribute LC_PROBE675_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE675_MU_CNT : integer;
  attribute LC_PROBE675_MU_CNT of U0 : label is 1;
  attribute LC_PROBE675_PID : string;
  attribute LC_PROBE675_PID of U0 : label is "16'b0000001010100011";
  attribute LC_PROBE675_TYPE : integer;
  attribute LC_PROBE675_TYPE of U0 : label is 1;
  attribute LC_PROBE675_WIDTH : integer;
  attribute LC_PROBE675_WIDTH of U0 : label is 1;
  attribute LC_PROBE676_IS_DATA : string;
  attribute LC_PROBE676_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE676_IS_TRIG : string;
  attribute LC_PROBE676_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE676_MU_CNT : integer;
  attribute LC_PROBE676_MU_CNT of U0 : label is 1;
  attribute LC_PROBE676_PID : string;
  attribute LC_PROBE676_PID of U0 : label is "16'b0000001010100100";
  attribute LC_PROBE676_TYPE : integer;
  attribute LC_PROBE676_TYPE of U0 : label is 1;
  attribute LC_PROBE676_WIDTH : integer;
  attribute LC_PROBE676_WIDTH of U0 : label is 1;
  attribute LC_PROBE677_IS_DATA : string;
  attribute LC_PROBE677_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE677_IS_TRIG : string;
  attribute LC_PROBE677_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE677_MU_CNT : integer;
  attribute LC_PROBE677_MU_CNT of U0 : label is 1;
  attribute LC_PROBE677_PID : string;
  attribute LC_PROBE677_PID of U0 : label is "16'b0000001010100101";
  attribute LC_PROBE677_TYPE : integer;
  attribute LC_PROBE677_TYPE of U0 : label is 1;
  attribute LC_PROBE677_WIDTH : integer;
  attribute LC_PROBE677_WIDTH of U0 : label is 1;
  attribute LC_PROBE678_IS_DATA : string;
  attribute LC_PROBE678_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE678_IS_TRIG : string;
  attribute LC_PROBE678_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE678_MU_CNT : integer;
  attribute LC_PROBE678_MU_CNT of U0 : label is 1;
  attribute LC_PROBE678_PID : string;
  attribute LC_PROBE678_PID of U0 : label is "16'b0000001010100110";
  attribute LC_PROBE678_TYPE : integer;
  attribute LC_PROBE678_TYPE of U0 : label is 1;
  attribute LC_PROBE678_WIDTH : integer;
  attribute LC_PROBE678_WIDTH of U0 : label is 1;
  attribute LC_PROBE679_IS_DATA : string;
  attribute LC_PROBE679_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE679_IS_TRIG : string;
  attribute LC_PROBE679_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE679_MU_CNT : integer;
  attribute LC_PROBE679_MU_CNT of U0 : label is 1;
  attribute LC_PROBE679_PID : string;
  attribute LC_PROBE679_PID of U0 : label is "16'b0000001010100111";
  attribute LC_PROBE679_TYPE : integer;
  attribute LC_PROBE679_TYPE of U0 : label is 1;
  attribute LC_PROBE679_WIDTH : integer;
  attribute LC_PROBE679_WIDTH of U0 : label is 1;
  attribute LC_PROBE67_IS_DATA : string;
  attribute LC_PROBE67_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE67_IS_TRIG : string;
  attribute LC_PROBE67_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE67_MU_CNT : integer;
  attribute LC_PROBE67_MU_CNT of U0 : label is 1;
  attribute LC_PROBE67_PID : string;
  attribute LC_PROBE67_PID of U0 : label is "16'b0000000001000011";
  attribute LC_PROBE67_TYPE : integer;
  attribute LC_PROBE67_TYPE of U0 : label is 1;
  attribute LC_PROBE67_WIDTH : integer;
  attribute LC_PROBE67_WIDTH of U0 : label is 1;
  attribute LC_PROBE680_IS_DATA : string;
  attribute LC_PROBE680_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE680_IS_TRIG : string;
  attribute LC_PROBE680_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE680_MU_CNT : integer;
  attribute LC_PROBE680_MU_CNT of U0 : label is 1;
  attribute LC_PROBE680_PID : string;
  attribute LC_PROBE680_PID of U0 : label is "16'b0000001010101000";
  attribute LC_PROBE680_TYPE : integer;
  attribute LC_PROBE680_TYPE of U0 : label is 1;
  attribute LC_PROBE680_WIDTH : integer;
  attribute LC_PROBE680_WIDTH of U0 : label is 1;
  attribute LC_PROBE681_IS_DATA : string;
  attribute LC_PROBE681_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE681_IS_TRIG : string;
  attribute LC_PROBE681_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE681_MU_CNT : integer;
  attribute LC_PROBE681_MU_CNT of U0 : label is 1;
  attribute LC_PROBE681_PID : string;
  attribute LC_PROBE681_PID of U0 : label is "16'b0000001010101001";
  attribute LC_PROBE681_TYPE : integer;
  attribute LC_PROBE681_TYPE of U0 : label is 1;
  attribute LC_PROBE681_WIDTH : integer;
  attribute LC_PROBE681_WIDTH of U0 : label is 1;
  attribute LC_PROBE682_IS_DATA : string;
  attribute LC_PROBE682_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE682_IS_TRIG : string;
  attribute LC_PROBE682_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE682_MU_CNT : integer;
  attribute LC_PROBE682_MU_CNT of U0 : label is 1;
  attribute LC_PROBE682_PID : string;
  attribute LC_PROBE682_PID of U0 : label is "16'b0000001010101010";
  attribute LC_PROBE682_TYPE : integer;
  attribute LC_PROBE682_TYPE of U0 : label is 1;
  attribute LC_PROBE682_WIDTH : integer;
  attribute LC_PROBE682_WIDTH of U0 : label is 1;
  attribute LC_PROBE683_IS_DATA : string;
  attribute LC_PROBE683_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE683_IS_TRIG : string;
  attribute LC_PROBE683_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE683_MU_CNT : integer;
  attribute LC_PROBE683_MU_CNT of U0 : label is 1;
  attribute LC_PROBE683_PID : string;
  attribute LC_PROBE683_PID of U0 : label is "16'b0000001010101011";
  attribute LC_PROBE683_TYPE : integer;
  attribute LC_PROBE683_TYPE of U0 : label is 1;
  attribute LC_PROBE683_WIDTH : integer;
  attribute LC_PROBE683_WIDTH of U0 : label is 1;
  attribute LC_PROBE684_IS_DATA : string;
  attribute LC_PROBE684_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE684_IS_TRIG : string;
  attribute LC_PROBE684_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE684_MU_CNT : integer;
  attribute LC_PROBE684_MU_CNT of U0 : label is 1;
  attribute LC_PROBE684_PID : string;
  attribute LC_PROBE684_PID of U0 : label is "16'b0000001010101100";
  attribute LC_PROBE684_TYPE : integer;
  attribute LC_PROBE684_TYPE of U0 : label is 1;
  attribute LC_PROBE684_WIDTH : integer;
  attribute LC_PROBE684_WIDTH of U0 : label is 1;
  attribute LC_PROBE685_IS_DATA : string;
  attribute LC_PROBE685_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE685_IS_TRIG : string;
  attribute LC_PROBE685_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE685_MU_CNT : integer;
  attribute LC_PROBE685_MU_CNT of U0 : label is 1;
  attribute LC_PROBE685_PID : string;
  attribute LC_PROBE685_PID of U0 : label is "16'b0000001010101101";
  attribute LC_PROBE685_TYPE : integer;
  attribute LC_PROBE685_TYPE of U0 : label is 1;
  attribute LC_PROBE685_WIDTH : integer;
  attribute LC_PROBE685_WIDTH of U0 : label is 1;
  attribute LC_PROBE686_IS_DATA : string;
  attribute LC_PROBE686_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE686_IS_TRIG : string;
  attribute LC_PROBE686_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE686_MU_CNT : integer;
  attribute LC_PROBE686_MU_CNT of U0 : label is 1;
  attribute LC_PROBE686_PID : string;
  attribute LC_PROBE686_PID of U0 : label is "16'b0000001010101110";
  attribute LC_PROBE686_TYPE : integer;
  attribute LC_PROBE686_TYPE of U0 : label is 1;
  attribute LC_PROBE686_WIDTH : integer;
  attribute LC_PROBE686_WIDTH of U0 : label is 1;
  attribute LC_PROBE687_IS_DATA : string;
  attribute LC_PROBE687_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE687_IS_TRIG : string;
  attribute LC_PROBE687_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE687_MU_CNT : integer;
  attribute LC_PROBE687_MU_CNT of U0 : label is 1;
  attribute LC_PROBE687_PID : string;
  attribute LC_PROBE687_PID of U0 : label is "16'b0000001010101111";
  attribute LC_PROBE687_TYPE : integer;
  attribute LC_PROBE687_TYPE of U0 : label is 1;
  attribute LC_PROBE687_WIDTH : integer;
  attribute LC_PROBE687_WIDTH of U0 : label is 1;
  attribute LC_PROBE688_IS_DATA : string;
  attribute LC_PROBE688_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE688_IS_TRIG : string;
  attribute LC_PROBE688_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE688_MU_CNT : integer;
  attribute LC_PROBE688_MU_CNT of U0 : label is 1;
  attribute LC_PROBE688_PID : string;
  attribute LC_PROBE688_PID of U0 : label is "16'b0000001010110000";
  attribute LC_PROBE688_TYPE : integer;
  attribute LC_PROBE688_TYPE of U0 : label is 1;
  attribute LC_PROBE688_WIDTH : integer;
  attribute LC_PROBE688_WIDTH of U0 : label is 1;
  attribute LC_PROBE689_IS_DATA : string;
  attribute LC_PROBE689_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE689_IS_TRIG : string;
  attribute LC_PROBE689_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE689_MU_CNT : integer;
  attribute LC_PROBE689_MU_CNT of U0 : label is 1;
  attribute LC_PROBE689_PID : string;
  attribute LC_PROBE689_PID of U0 : label is "16'b0000001010110001";
  attribute LC_PROBE689_TYPE : integer;
  attribute LC_PROBE689_TYPE of U0 : label is 1;
  attribute LC_PROBE689_WIDTH : integer;
  attribute LC_PROBE689_WIDTH of U0 : label is 1;
  attribute LC_PROBE68_IS_DATA : string;
  attribute LC_PROBE68_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE68_IS_TRIG : string;
  attribute LC_PROBE68_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE68_MU_CNT : integer;
  attribute LC_PROBE68_MU_CNT of U0 : label is 1;
  attribute LC_PROBE68_PID : string;
  attribute LC_PROBE68_PID of U0 : label is "16'b0000000001000100";
  attribute LC_PROBE68_TYPE : integer;
  attribute LC_PROBE68_TYPE of U0 : label is 1;
  attribute LC_PROBE68_WIDTH : integer;
  attribute LC_PROBE68_WIDTH of U0 : label is 1;
  attribute LC_PROBE690_IS_DATA : string;
  attribute LC_PROBE690_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE690_IS_TRIG : string;
  attribute LC_PROBE690_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE690_MU_CNT : integer;
  attribute LC_PROBE690_MU_CNT of U0 : label is 1;
  attribute LC_PROBE690_PID : string;
  attribute LC_PROBE690_PID of U0 : label is "16'b0000001010110010";
  attribute LC_PROBE690_TYPE : integer;
  attribute LC_PROBE690_TYPE of U0 : label is 1;
  attribute LC_PROBE690_WIDTH : integer;
  attribute LC_PROBE690_WIDTH of U0 : label is 1;
  attribute LC_PROBE691_IS_DATA : string;
  attribute LC_PROBE691_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE691_IS_TRIG : string;
  attribute LC_PROBE691_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE691_MU_CNT : integer;
  attribute LC_PROBE691_MU_CNT of U0 : label is 1;
  attribute LC_PROBE691_PID : string;
  attribute LC_PROBE691_PID of U0 : label is "16'b0000001010110011";
  attribute LC_PROBE691_TYPE : integer;
  attribute LC_PROBE691_TYPE of U0 : label is 1;
  attribute LC_PROBE691_WIDTH : integer;
  attribute LC_PROBE691_WIDTH of U0 : label is 1;
  attribute LC_PROBE692_IS_DATA : string;
  attribute LC_PROBE692_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE692_IS_TRIG : string;
  attribute LC_PROBE692_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE692_MU_CNT : integer;
  attribute LC_PROBE692_MU_CNT of U0 : label is 1;
  attribute LC_PROBE692_PID : string;
  attribute LC_PROBE692_PID of U0 : label is "16'b0000001010110100";
  attribute LC_PROBE692_TYPE : integer;
  attribute LC_PROBE692_TYPE of U0 : label is 1;
  attribute LC_PROBE692_WIDTH : integer;
  attribute LC_PROBE692_WIDTH of U0 : label is 1;
  attribute LC_PROBE693_IS_DATA : string;
  attribute LC_PROBE693_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE693_IS_TRIG : string;
  attribute LC_PROBE693_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE693_MU_CNT : integer;
  attribute LC_PROBE693_MU_CNT of U0 : label is 1;
  attribute LC_PROBE693_PID : string;
  attribute LC_PROBE693_PID of U0 : label is "16'b0000001010110101";
  attribute LC_PROBE693_TYPE : integer;
  attribute LC_PROBE693_TYPE of U0 : label is 1;
  attribute LC_PROBE693_WIDTH : integer;
  attribute LC_PROBE693_WIDTH of U0 : label is 1;
  attribute LC_PROBE694_IS_DATA : string;
  attribute LC_PROBE694_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE694_IS_TRIG : string;
  attribute LC_PROBE694_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE694_MU_CNT : integer;
  attribute LC_PROBE694_MU_CNT of U0 : label is 1;
  attribute LC_PROBE694_PID : string;
  attribute LC_PROBE694_PID of U0 : label is "16'b0000001010110110";
  attribute LC_PROBE694_TYPE : integer;
  attribute LC_PROBE694_TYPE of U0 : label is 1;
  attribute LC_PROBE694_WIDTH : integer;
  attribute LC_PROBE694_WIDTH of U0 : label is 1;
  attribute LC_PROBE695_IS_DATA : string;
  attribute LC_PROBE695_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE695_IS_TRIG : string;
  attribute LC_PROBE695_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE695_MU_CNT : integer;
  attribute LC_PROBE695_MU_CNT of U0 : label is 1;
  attribute LC_PROBE695_PID : string;
  attribute LC_PROBE695_PID of U0 : label is "16'b0000001010110111";
  attribute LC_PROBE695_TYPE : integer;
  attribute LC_PROBE695_TYPE of U0 : label is 1;
  attribute LC_PROBE695_WIDTH : integer;
  attribute LC_PROBE695_WIDTH of U0 : label is 1;
  attribute LC_PROBE696_IS_DATA : string;
  attribute LC_PROBE696_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE696_IS_TRIG : string;
  attribute LC_PROBE696_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE696_MU_CNT : integer;
  attribute LC_PROBE696_MU_CNT of U0 : label is 1;
  attribute LC_PROBE696_PID : string;
  attribute LC_PROBE696_PID of U0 : label is "16'b0000001010111000";
  attribute LC_PROBE696_TYPE : integer;
  attribute LC_PROBE696_TYPE of U0 : label is 1;
  attribute LC_PROBE696_WIDTH : integer;
  attribute LC_PROBE696_WIDTH of U0 : label is 1;
  attribute LC_PROBE697_IS_DATA : string;
  attribute LC_PROBE697_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE697_IS_TRIG : string;
  attribute LC_PROBE697_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE697_MU_CNT : integer;
  attribute LC_PROBE697_MU_CNT of U0 : label is 1;
  attribute LC_PROBE697_PID : string;
  attribute LC_PROBE697_PID of U0 : label is "16'b0000001010111001";
  attribute LC_PROBE697_TYPE : integer;
  attribute LC_PROBE697_TYPE of U0 : label is 1;
  attribute LC_PROBE697_WIDTH : integer;
  attribute LC_PROBE697_WIDTH of U0 : label is 1;
  attribute LC_PROBE698_IS_DATA : string;
  attribute LC_PROBE698_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE698_IS_TRIG : string;
  attribute LC_PROBE698_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE698_MU_CNT : integer;
  attribute LC_PROBE698_MU_CNT of U0 : label is 1;
  attribute LC_PROBE698_PID : string;
  attribute LC_PROBE698_PID of U0 : label is "16'b0000001010111010";
  attribute LC_PROBE698_TYPE : integer;
  attribute LC_PROBE698_TYPE of U0 : label is 1;
  attribute LC_PROBE698_WIDTH : integer;
  attribute LC_PROBE698_WIDTH of U0 : label is 1;
  attribute LC_PROBE699_IS_DATA : string;
  attribute LC_PROBE699_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE699_IS_TRIG : string;
  attribute LC_PROBE699_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE699_MU_CNT : integer;
  attribute LC_PROBE699_MU_CNT of U0 : label is 1;
  attribute LC_PROBE699_PID : string;
  attribute LC_PROBE699_PID of U0 : label is "16'b0000001010111011";
  attribute LC_PROBE699_TYPE : integer;
  attribute LC_PROBE699_TYPE of U0 : label is 1;
  attribute LC_PROBE699_WIDTH : integer;
  attribute LC_PROBE699_WIDTH of U0 : label is 1;
  attribute LC_PROBE69_IS_DATA : string;
  attribute LC_PROBE69_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE69_IS_TRIG : string;
  attribute LC_PROBE69_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE69_MU_CNT : integer;
  attribute LC_PROBE69_MU_CNT of U0 : label is 1;
  attribute LC_PROBE69_PID : string;
  attribute LC_PROBE69_PID of U0 : label is "16'b0000000001000101";
  attribute LC_PROBE69_TYPE : integer;
  attribute LC_PROBE69_TYPE of U0 : label is 1;
  attribute LC_PROBE69_WIDTH : integer;
  attribute LC_PROBE69_WIDTH of U0 : label is 1;
  attribute LC_PROBE6_IS_DATA : string;
  attribute LC_PROBE6_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE6_IS_TRIG : string;
  attribute LC_PROBE6_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE6_MU_CNT : integer;
  attribute LC_PROBE6_MU_CNT of U0 : label is 1;
  attribute LC_PROBE6_PID : string;
  attribute LC_PROBE6_PID of U0 : label is "16'b0000000000000110";
  attribute LC_PROBE6_TYPE : integer;
  attribute LC_PROBE6_TYPE of U0 : label is 1;
  attribute LC_PROBE6_WIDTH : integer;
  attribute LC_PROBE6_WIDTH of U0 : label is 1;
  attribute LC_PROBE700_IS_DATA : string;
  attribute LC_PROBE700_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE700_IS_TRIG : string;
  attribute LC_PROBE700_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE700_MU_CNT : integer;
  attribute LC_PROBE700_MU_CNT of U0 : label is 1;
  attribute LC_PROBE700_PID : string;
  attribute LC_PROBE700_PID of U0 : label is "16'b0000001010111100";
  attribute LC_PROBE700_TYPE : integer;
  attribute LC_PROBE700_TYPE of U0 : label is 1;
  attribute LC_PROBE700_WIDTH : integer;
  attribute LC_PROBE700_WIDTH of U0 : label is 1;
  attribute LC_PROBE701_IS_DATA : string;
  attribute LC_PROBE701_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE701_IS_TRIG : string;
  attribute LC_PROBE701_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE701_MU_CNT : integer;
  attribute LC_PROBE701_MU_CNT of U0 : label is 1;
  attribute LC_PROBE701_PID : string;
  attribute LC_PROBE701_PID of U0 : label is "16'b0000001010111101";
  attribute LC_PROBE701_TYPE : integer;
  attribute LC_PROBE701_TYPE of U0 : label is 1;
  attribute LC_PROBE701_WIDTH : integer;
  attribute LC_PROBE701_WIDTH of U0 : label is 1;
  attribute LC_PROBE702_IS_DATA : string;
  attribute LC_PROBE702_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE702_IS_TRIG : string;
  attribute LC_PROBE702_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE702_MU_CNT : integer;
  attribute LC_PROBE702_MU_CNT of U0 : label is 1;
  attribute LC_PROBE702_PID : string;
  attribute LC_PROBE702_PID of U0 : label is "16'b0000001010111110";
  attribute LC_PROBE702_TYPE : integer;
  attribute LC_PROBE702_TYPE of U0 : label is 1;
  attribute LC_PROBE702_WIDTH : integer;
  attribute LC_PROBE702_WIDTH of U0 : label is 1;
  attribute LC_PROBE703_IS_DATA : string;
  attribute LC_PROBE703_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE703_IS_TRIG : string;
  attribute LC_PROBE703_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE703_MU_CNT : integer;
  attribute LC_PROBE703_MU_CNT of U0 : label is 1;
  attribute LC_PROBE703_PID : string;
  attribute LC_PROBE703_PID of U0 : label is "16'b0000001010111111";
  attribute LC_PROBE703_TYPE : integer;
  attribute LC_PROBE703_TYPE of U0 : label is 1;
  attribute LC_PROBE703_WIDTH : integer;
  attribute LC_PROBE703_WIDTH of U0 : label is 1;
  attribute LC_PROBE704_IS_DATA : string;
  attribute LC_PROBE704_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE704_IS_TRIG : string;
  attribute LC_PROBE704_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE704_MU_CNT : integer;
  attribute LC_PROBE704_MU_CNT of U0 : label is 1;
  attribute LC_PROBE704_PID : string;
  attribute LC_PROBE704_PID of U0 : label is "16'b0000001011000000";
  attribute LC_PROBE704_TYPE : integer;
  attribute LC_PROBE704_TYPE of U0 : label is 1;
  attribute LC_PROBE704_WIDTH : integer;
  attribute LC_PROBE704_WIDTH of U0 : label is 1;
  attribute LC_PROBE705_IS_DATA : string;
  attribute LC_PROBE705_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE705_IS_TRIG : string;
  attribute LC_PROBE705_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE705_MU_CNT : integer;
  attribute LC_PROBE705_MU_CNT of U0 : label is 1;
  attribute LC_PROBE705_PID : string;
  attribute LC_PROBE705_PID of U0 : label is "16'b0000001011000001";
  attribute LC_PROBE705_TYPE : integer;
  attribute LC_PROBE705_TYPE of U0 : label is 1;
  attribute LC_PROBE705_WIDTH : integer;
  attribute LC_PROBE705_WIDTH of U0 : label is 1;
  attribute LC_PROBE706_IS_DATA : string;
  attribute LC_PROBE706_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE706_IS_TRIG : string;
  attribute LC_PROBE706_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE706_MU_CNT : integer;
  attribute LC_PROBE706_MU_CNT of U0 : label is 1;
  attribute LC_PROBE706_PID : string;
  attribute LC_PROBE706_PID of U0 : label is "16'b0000001011000010";
  attribute LC_PROBE706_TYPE : integer;
  attribute LC_PROBE706_TYPE of U0 : label is 1;
  attribute LC_PROBE706_WIDTH : integer;
  attribute LC_PROBE706_WIDTH of U0 : label is 1;
  attribute LC_PROBE707_IS_DATA : string;
  attribute LC_PROBE707_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE707_IS_TRIG : string;
  attribute LC_PROBE707_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE707_MU_CNT : integer;
  attribute LC_PROBE707_MU_CNT of U0 : label is 1;
  attribute LC_PROBE707_PID : string;
  attribute LC_PROBE707_PID of U0 : label is "16'b0000001011000011";
  attribute LC_PROBE707_TYPE : integer;
  attribute LC_PROBE707_TYPE of U0 : label is 1;
  attribute LC_PROBE707_WIDTH : integer;
  attribute LC_PROBE707_WIDTH of U0 : label is 1;
  attribute LC_PROBE708_IS_DATA : string;
  attribute LC_PROBE708_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE708_IS_TRIG : string;
  attribute LC_PROBE708_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE708_MU_CNT : integer;
  attribute LC_PROBE708_MU_CNT of U0 : label is 1;
  attribute LC_PROBE708_PID : string;
  attribute LC_PROBE708_PID of U0 : label is "16'b0000001011000100";
  attribute LC_PROBE708_TYPE : integer;
  attribute LC_PROBE708_TYPE of U0 : label is 1;
  attribute LC_PROBE708_WIDTH : integer;
  attribute LC_PROBE708_WIDTH of U0 : label is 1;
  attribute LC_PROBE709_IS_DATA : string;
  attribute LC_PROBE709_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE709_IS_TRIG : string;
  attribute LC_PROBE709_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE709_MU_CNT : integer;
  attribute LC_PROBE709_MU_CNT of U0 : label is 1;
  attribute LC_PROBE709_PID : string;
  attribute LC_PROBE709_PID of U0 : label is "16'b0000001011000101";
  attribute LC_PROBE709_TYPE : integer;
  attribute LC_PROBE709_TYPE of U0 : label is 1;
  attribute LC_PROBE709_WIDTH : integer;
  attribute LC_PROBE709_WIDTH of U0 : label is 1;
  attribute LC_PROBE70_IS_DATA : string;
  attribute LC_PROBE70_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE70_IS_TRIG : string;
  attribute LC_PROBE70_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE70_MU_CNT : integer;
  attribute LC_PROBE70_MU_CNT of U0 : label is 1;
  attribute LC_PROBE70_PID : string;
  attribute LC_PROBE70_PID of U0 : label is "16'b0000000001000110";
  attribute LC_PROBE70_TYPE : integer;
  attribute LC_PROBE70_TYPE of U0 : label is 1;
  attribute LC_PROBE70_WIDTH : integer;
  attribute LC_PROBE70_WIDTH of U0 : label is 1;
  attribute LC_PROBE710_IS_DATA : string;
  attribute LC_PROBE710_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE710_IS_TRIG : string;
  attribute LC_PROBE710_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE710_MU_CNT : integer;
  attribute LC_PROBE710_MU_CNT of U0 : label is 1;
  attribute LC_PROBE710_PID : string;
  attribute LC_PROBE710_PID of U0 : label is "16'b0000001011000110";
  attribute LC_PROBE710_TYPE : integer;
  attribute LC_PROBE710_TYPE of U0 : label is 1;
  attribute LC_PROBE710_WIDTH : integer;
  attribute LC_PROBE710_WIDTH of U0 : label is 1;
  attribute LC_PROBE711_IS_DATA : string;
  attribute LC_PROBE711_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE711_IS_TRIG : string;
  attribute LC_PROBE711_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE711_MU_CNT : integer;
  attribute LC_PROBE711_MU_CNT of U0 : label is 1;
  attribute LC_PROBE711_PID : string;
  attribute LC_PROBE711_PID of U0 : label is "16'b0000001011000111";
  attribute LC_PROBE711_TYPE : integer;
  attribute LC_PROBE711_TYPE of U0 : label is 1;
  attribute LC_PROBE711_WIDTH : integer;
  attribute LC_PROBE711_WIDTH of U0 : label is 1;
  attribute LC_PROBE712_IS_DATA : string;
  attribute LC_PROBE712_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE712_IS_TRIG : string;
  attribute LC_PROBE712_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE712_MU_CNT : integer;
  attribute LC_PROBE712_MU_CNT of U0 : label is 1;
  attribute LC_PROBE712_PID : string;
  attribute LC_PROBE712_PID of U0 : label is "16'b0000001011001000";
  attribute LC_PROBE712_TYPE : integer;
  attribute LC_PROBE712_TYPE of U0 : label is 1;
  attribute LC_PROBE712_WIDTH : integer;
  attribute LC_PROBE712_WIDTH of U0 : label is 1;
  attribute LC_PROBE713_IS_DATA : string;
  attribute LC_PROBE713_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE713_IS_TRIG : string;
  attribute LC_PROBE713_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE713_MU_CNT : integer;
  attribute LC_PROBE713_MU_CNT of U0 : label is 1;
  attribute LC_PROBE713_PID : string;
  attribute LC_PROBE713_PID of U0 : label is "16'b0000001011001001";
  attribute LC_PROBE713_TYPE : integer;
  attribute LC_PROBE713_TYPE of U0 : label is 1;
  attribute LC_PROBE713_WIDTH : integer;
  attribute LC_PROBE713_WIDTH of U0 : label is 1;
  attribute LC_PROBE714_IS_DATA : string;
  attribute LC_PROBE714_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE714_IS_TRIG : string;
  attribute LC_PROBE714_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE714_MU_CNT : integer;
  attribute LC_PROBE714_MU_CNT of U0 : label is 1;
  attribute LC_PROBE714_PID : string;
  attribute LC_PROBE714_PID of U0 : label is "16'b0000001011001010";
  attribute LC_PROBE714_TYPE : integer;
  attribute LC_PROBE714_TYPE of U0 : label is 1;
  attribute LC_PROBE714_WIDTH : integer;
  attribute LC_PROBE714_WIDTH of U0 : label is 1;
  attribute LC_PROBE715_IS_DATA : string;
  attribute LC_PROBE715_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE715_IS_TRIG : string;
  attribute LC_PROBE715_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE715_MU_CNT : integer;
  attribute LC_PROBE715_MU_CNT of U0 : label is 1;
  attribute LC_PROBE715_PID : string;
  attribute LC_PROBE715_PID of U0 : label is "16'b0000001011001011";
  attribute LC_PROBE715_TYPE : integer;
  attribute LC_PROBE715_TYPE of U0 : label is 1;
  attribute LC_PROBE715_WIDTH : integer;
  attribute LC_PROBE715_WIDTH of U0 : label is 1;
  attribute LC_PROBE716_IS_DATA : string;
  attribute LC_PROBE716_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE716_IS_TRIG : string;
  attribute LC_PROBE716_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE716_MU_CNT : integer;
  attribute LC_PROBE716_MU_CNT of U0 : label is 1;
  attribute LC_PROBE716_PID : string;
  attribute LC_PROBE716_PID of U0 : label is "16'b0000001011001100";
  attribute LC_PROBE716_TYPE : integer;
  attribute LC_PROBE716_TYPE of U0 : label is 1;
  attribute LC_PROBE716_WIDTH : integer;
  attribute LC_PROBE716_WIDTH of U0 : label is 1;
  attribute LC_PROBE717_IS_DATA : string;
  attribute LC_PROBE717_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE717_IS_TRIG : string;
  attribute LC_PROBE717_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE717_MU_CNT : integer;
  attribute LC_PROBE717_MU_CNT of U0 : label is 1;
  attribute LC_PROBE717_PID : string;
  attribute LC_PROBE717_PID of U0 : label is "16'b0000001011001101";
  attribute LC_PROBE717_TYPE : integer;
  attribute LC_PROBE717_TYPE of U0 : label is 1;
  attribute LC_PROBE717_WIDTH : integer;
  attribute LC_PROBE717_WIDTH of U0 : label is 1;
  attribute LC_PROBE718_IS_DATA : string;
  attribute LC_PROBE718_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE718_IS_TRIG : string;
  attribute LC_PROBE718_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE718_MU_CNT : integer;
  attribute LC_PROBE718_MU_CNT of U0 : label is 1;
  attribute LC_PROBE718_PID : string;
  attribute LC_PROBE718_PID of U0 : label is "16'b0000001011001110";
  attribute LC_PROBE718_TYPE : integer;
  attribute LC_PROBE718_TYPE of U0 : label is 1;
  attribute LC_PROBE718_WIDTH : integer;
  attribute LC_PROBE718_WIDTH of U0 : label is 1;
  attribute LC_PROBE719_IS_DATA : string;
  attribute LC_PROBE719_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE719_IS_TRIG : string;
  attribute LC_PROBE719_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE719_MU_CNT : integer;
  attribute LC_PROBE719_MU_CNT of U0 : label is 1;
  attribute LC_PROBE719_PID : string;
  attribute LC_PROBE719_PID of U0 : label is "16'b0000001011001111";
  attribute LC_PROBE719_TYPE : integer;
  attribute LC_PROBE719_TYPE of U0 : label is 1;
  attribute LC_PROBE719_WIDTH : integer;
  attribute LC_PROBE719_WIDTH of U0 : label is 1;
  attribute LC_PROBE71_IS_DATA : string;
  attribute LC_PROBE71_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE71_IS_TRIG : string;
  attribute LC_PROBE71_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE71_MU_CNT : integer;
  attribute LC_PROBE71_MU_CNT of U0 : label is 1;
  attribute LC_PROBE71_PID : string;
  attribute LC_PROBE71_PID of U0 : label is "16'b0000000001000111";
  attribute LC_PROBE71_TYPE : integer;
  attribute LC_PROBE71_TYPE of U0 : label is 1;
  attribute LC_PROBE71_WIDTH : integer;
  attribute LC_PROBE71_WIDTH of U0 : label is 1;
  attribute LC_PROBE720_IS_DATA : string;
  attribute LC_PROBE720_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE720_IS_TRIG : string;
  attribute LC_PROBE720_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE720_MU_CNT : integer;
  attribute LC_PROBE720_MU_CNT of U0 : label is 1;
  attribute LC_PROBE720_PID : string;
  attribute LC_PROBE720_PID of U0 : label is "16'b0000001011010000";
  attribute LC_PROBE720_TYPE : integer;
  attribute LC_PROBE720_TYPE of U0 : label is 1;
  attribute LC_PROBE720_WIDTH : integer;
  attribute LC_PROBE720_WIDTH of U0 : label is 1;
  attribute LC_PROBE721_IS_DATA : string;
  attribute LC_PROBE721_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE721_IS_TRIG : string;
  attribute LC_PROBE721_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE721_MU_CNT : integer;
  attribute LC_PROBE721_MU_CNT of U0 : label is 1;
  attribute LC_PROBE721_PID : string;
  attribute LC_PROBE721_PID of U0 : label is "16'b0000001011010001";
  attribute LC_PROBE721_TYPE : integer;
  attribute LC_PROBE721_TYPE of U0 : label is 1;
  attribute LC_PROBE721_WIDTH : integer;
  attribute LC_PROBE721_WIDTH of U0 : label is 1;
  attribute LC_PROBE722_IS_DATA : string;
  attribute LC_PROBE722_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE722_IS_TRIG : string;
  attribute LC_PROBE722_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE722_MU_CNT : integer;
  attribute LC_PROBE722_MU_CNT of U0 : label is 1;
  attribute LC_PROBE722_PID : string;
  attribute LC_PROBE722_PID of U0 : label is "16'b0000001011010010";
  attribute LC_PROBE722_TYPE : integer;
  attribute LC_PROBE722_TYPE of U0 : label is 1;
  attribute LC_PROBE722_WIDTH : integer;
  attribute LC_PROBE722_WIDTH of U0 : label is 1;
  attribute LC_PROBE723_IS_DATA : string;
  attribute LC_PROBE723_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE723_IS_TRIG : string;
  attribute LC_PROBE723_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE723_MU_CNT : integer;
  attribute LC_PROBE723_MU_CNT of U0 : label is 1;
  attribute LC_PROBE723_PID : string;
  attribute LC_PROBE723_PID of U0 : label is "16'b0000001011010011";
  attribute LC_PROBE723_TYPE : integer;
  attribute LC_PROBE723_TYPE of U0 : label is 1;
  attribute LC_PROBE723_WIDTH : integer;
  attribute LC_PROBE723_WIDTH of U0 : label is 1;
  attribute LC_PROBE724_IS_DATA : string;
  attribute LC_PROBE724_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE724_IS_TRIG : string;
  attribute LC_PROBE724_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE724_MU_CNT : integer;
  attribute LC_PROBE724_MU_CNT of U0 : label is 1;
  attribute LC_PROBE724_PID : string;
  attribute LC_PROBE724_PID of U0 : label is "16'b0000001011010100";
  attribute LC_PROBE724_TYPE : integer;
  attribute LC_PROBE724_TYPE of U0 : label is 1;
  attribute LC_PROBE724_WIDTH : integer;
  attribute LC_PROBE724_WIDTH of U0 : label is 1;
  attribute LC_PROBE725_IS_DATA : string;
  attribute LC_PROBE725_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE725_IS_TRIG : string;
  attribute LC_PROBE725_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE725_MU_CNT : integer;
  attribute LC_PROBE725_MU_CNT of U0 : label is 1;
  attribute LC_PROBE725_PID : string;
  attribute LC_PROBE725_PID of U0 : label is "16'b0000001011010101";
  attribute LC_PROBE725_TYPE : integer;
  attribute LC_PROBE725_TYPE of U0 : label is 1;
  attribute LC_PROBE725_WIDTH : integer;
  attribute LC_PROBE725_WIDTH of U0 : label is 1;
  attribute LC_PROBE726_IS_DATA : string;
  attribute LC_PROBE726_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE726_IS_TRIG : string;
  attribute LC_PROBE726_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE726_MU_CNT : integer;
  attribute LC_PROBE726_MU_CNT of U0 : label is 1;
  attribute LC_PROBE726_PID : string;
  attribute LC_PROBE726_PID of U0 : label is "16'b0000001011010110";
  attribute LC_PROBE726_TYPE : integer;
  attribute LC_PROBE726_TYPE of U0 : label is 1;
  attribute LC_PROBE726_WIDTH : integer;
  attribute LC_PROBE726_WIDTH of U0 : label is 1;
  attribute LC_PROBE727_IS_DATA : string;
  attribute LC_PROBE727_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE727_IS_TRIG : string;
  attribute LC_PROBE727_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE727_MU_CNT : integer;
  attribute LC_PROBE727_MU_CNT of U0 : label is 1;
  attribute LC_PROBE727_PID : string;
  attribute LC_PROBE727_PID of U0 : label is "16'b0000001011010111";
  attribute LC_PROBE727_TYPE : integer;
  attribute LC_PROBE727_TYPE of U0 : label is 1;
  attribute LC_PROBE727_WIDTH : integer;
  attribute LC_PROBE727_WIDTH of U0 : label is 1;
  attribute LC_PROBE728_IS_DATA : string;
  attribute LC_PROBE728_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE728_IS_TRIG : string;
  attribute LC_PROBE728_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE728_MU_CNT : integer;
  attribute LC_PROBE728_MU_CNT of U0 : label is 1;
  attribute LC_PROBE728_PID : string;
  attribute LC_PROBE728_PID of U0 : label is "16'b0000001011011000";
  attribute LC_PROBE728_TYPE : integer;
  attribute LC_PROBE728_TYPE of U0 : label is 1;
  attribute LC_PROBE728_WIDTH : integer;
  attribute LC_PROBE728_WIDTH of U0 : label is 1;
  attribute LC_PROBE729_IS_DATA : string;
  attribute LC_PROBE729_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE729_IS_TRIG : string;
  attribute LC_PROBE729_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE729_MU_CNT : integer;
  attribute LC_PROBE729_MU_CNT of U0 : label is 1;
  attribute LC_PROBE729_PID : string;
  attribute LC_PROBE729_PID of U0 : label is "16'b0000001011011001";
  attribute LC_PROBE729_TYPE : integer;
  attribute LC_PROBE729_TYPE of U0 : label is 1;
  attribute LC_PROBE729_WIDTH : integer;
  attribute LC_PROBE729_WIDTH of U0 : label is 1;
  attribute LC_PROBE72_IS_DATA : string;
  attribute LC_PROBE72_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE72_IS_TRIG : string;
  attribute LC_PROBE72_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE72_MU_CNT : integer;
  attribute LC_PROBE72_MU_CNT of U0 : label is 1;
  attribute LC_PROBE72_PID : string;
  attribute LC_PROBE72_PID of U0 : label is "16'b0000000001001000";
  attribute LC_PROBE72_TYPE : integer;
  attribute LC_PROBE72_TYPE of U0 : label is 1;
  attribute LC_PROBE72_WIDTH : integer;
  attribute LC_PROBE72_WIDTH of U0 : label is 1;
  attribute LC_PROBE730_IS_DATA : string;
  attribute LC_PROBE730_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE730_IS_TRIG : string;
  attribute LC_PROBE730_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE730_MU_CNT : integer;
  attribute LC_PROBE730_MU_CNT of U0 : label is 1;
  attribute LC_PROBE730_PID : string;
  attribute LC_PROBE730_PID of U0 : label is "16'b0000001011011010";
  attribute LC_PROBE730_TYPE : integer;
  attribute LC_PROBE730_TYPE of U0 : label is 1;
  attribute LC_PROBE730_WIDTH : integer;
  attribute LC_PROBE730_WIDTH of U0 : label is 1;
  attribute LC_PROBE731_IS_DATA : string;
  attribute LC_PROBE731_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE731_IS_TRIG : string;
  attribute LC_PROBE731_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE731_MU_CNT : integer;
  attribute LC_PROBE731_MU_CNT of U0 : label is 1;
  attribute LC_PROBE731_PID : string;
  attribute LC_PROBE731_PID of U0 : label is "16'b0000001011011011";
  attribute LC_PROBE731_TYPE : integer;
  attribute LC_PROBE731_TYPE of U0 : label is 1;
  attribute LC_PROBE731_WIDTH : integer;
  attribute LC_PROBE731_WIDTH of U0 : label is 1;
  attribute LC_PROBE732_IS_DATA : string;
  attribute LC_PROBE732_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE732_IS_TRIG : string;
  attribute LC_PROBE732_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE732_MU_CNT : integer;
  attribute LC_PROBE732_MU_CNT of U0 : label is 1;
  attribute LC_PROBE732_PID : string;
  attribute LC_PROBE732_PID of U0 : label is "16'b0000001011011100";
  attribute LC_PROBE732_TYPE : integer;
  attribute LC_PROBE732_TYPE of U0 : label is 1;
  attribute LC_PROBE732_WIDTH : integer;
  attribute LC_PROBE732_WIDTH of U0 : label is 1;
  attribute LC_PROBE733_IS_DATA : string;
  attribute LC_PROBE733_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE733_IS_TRIG : string;
  attribute LC_PROBE733_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE733_MU_CNT : integer;
  attribute LC_PROBE733_MU_CNT of U0 : label is 1;
  attribute LC_PROBE733_PID : string;
  attribute LC_PROBE733_PID of U0 : label is "16'b0000001011011101";
  attribute LC_PROBE733_TYPE : integer;
  attribute LC_PROBE733_TYPE of U0 : label is 1;
  attribute LC_PROBE733_WIDTH : integer;
  attribute LC_PROBE733_WIDTH of U0 : label is 1;
  attribute LC_PROBE734_IS_DATA : string;
  attribute LC_PROBE734_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE734_IS_TRIG : string;
  attribute LC_PROBE734_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE734_MU_CNT : integer;
  attribute LC_PROBE734_MU_CNT of U0 : label is 1;
  attribute LC_PROBE734_PID : string;
  attribute LC_PROBE734_PID of U0 : label is "16'b0000001011011110";
  attribute LC_PROBE734_TYPE : integer;
  attribute LC_PROBE734_TYPE of U0 : label is 1;
  attribute LC_PROBE734_WIDTH : integer;
  attribute LC_PROBE734_WIDTH of U0 : label is 1;
  attribute LC_PROBE735_IS_DATA : string;
  attribute LC_PROBE735_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE735_IS_TRIG : string;
  attribute LC_PROBE735_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE735_MU_CNT : integer;
  attribute LC_PROBE735_MU_CNT of U0 : label is 1;
  attribute LC_PROBE735_PID : string;
  attribute LC_PROBE735_PID of U0 : label is "16'b0000001011011111";
  attribute LC_PROBE735_TYPE : integer;
  attribute LC_PROBE735_TYPE of U0 : label is 1;
  attribute LC_PROBE735_WIDTH : integer;
  attribute LC_PROBE735_WIDTH of U0 : label is 1;
  attribute LC_PROBE736_IS_DATA : string;
  attribute LC_PROBE736_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE736_IS_TRIG : string;
  attribute LC_PROBE736_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE736_MU_CNT : integer;
  attribute LC_PROBE736_MU_CNT of U0 : label is 1;
  attribute LC_PROBE736_PID : string;
  attribute LC_PROBE736_PID of U0 : label is "16'b0000001011100000";
  attribute LC_PROBE736_TYPE : integer;
  attribute LC_PROBE736_TYPE of U0 : label is 1;
  attribute LC_PROBE736_WIDTH : integer;
  attribute LC_PROBE736_WIDTH of U0 : label is 1;
  attribute LC_PROBE737_IS_DATA : string;
  attribute LC_PROBE737_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE737_IS_TRIG : string;
  attribute LC_PROBE737_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE737_MU_CNT : integer;
  attribute LC_PROBE737_MU_CNT of U0 : label is 1;
  attribute LC_PROBE737_PID : string;
  attribute LC_PROBE737_PID of U0 : label is "16'b0000001011100001";
  attribute LC_PROBE737_TYPE : integer;
  attribute LC_PROBE737_TYPE of U0 : label is 1;
  attribute LC_PROBE737_WIDTH : integer;
  attribute LC_PROBE737_WIDTH of U0 : label is 1;
  attribute LC_PROBE738_IS_DATA : string;
  attribute LC_PROBE738_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE738_IS_TRIG : string;
  attribute LC_PROBE738_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE738_MU_CNT : integer;
  attribute LC_PROBE738_MU_CNT of U0 : label is 1;
  attribute LC_PROBE738_PID : string;
  attribute LC_PROBE738_PID of U0 : label is "16'b0000001011100010";
  attribute LC_PROBE738_TYPE : integer;
  attribute LC_PROBE738_TYPE of U0 : label is 1;
  attribute LC_PROBE738_WIDTH : integer;
  attribute LC_PROBE738_WIDTH of U0 : label is 1;
  attribute LC_PROBE739_IS_DATA : string;
  attribute LC_PROBE739_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE739_IS_TRIG : string;
  attribute LC_PROBE739_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE739_MU_CNT : integer;
  attribute LC_PROBE739_MU_CNT of U0 : label is 1;
  attribute LC_PROBE739_PID : string;
  attribute LC_PROBE739_PID of U0 : label is "16'b0000001011100011";
  attribute LC_PROBE739_TYPE : integer;
  attribute LC_PROBE739_TYPE of U0 : label is 1;
  attribute LC_PROBE739_WIDTH : integer;
  attribute LC_PROBE739_WIDTH of U0 : label is 1;
  attribute LC_PROBE73_IS_DATA : string;
  attribute LC_PROBE73_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE73_IS_TRIG : string;
  attribute LC_PROBE73_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE73_MU_CNT : integer;
  attribute LC_PROBE73_MU_CNT of U0 : label is 1;
  attribute LC_PROBE73_PID : string;
  attribute LC_PROBE73_PID of U0 : label is "16'b0000000001001001";
  attribute LC_PROBE73_TYPE : integer;
  attribute LC_PROBE73_TYPE of U0 : label is 1;
  attribute LC_PROBE73_WIDTH : integer;
  attribute LC_PROBE73_WIDTH of U0 : label is 1;
  attribute LC_PROBE740_IS_DATA : string;
  attribute LC_PROBE740_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE740_IS_TRIG : string;
  attribute LC_PROBE740_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE740_MU_CNT : integer;
  attribute LC_PROBE740_MU_CNT of U0 : label is 1;
  attribute LC_PROBE740_PID : string;
  attribute LC_PROBE740_PID of U0 : label is "16'b0000001011100100";
  attribute LC_PROBE740_TYPE : integer;
  attribute LC_PROBE740_TYPE of U0 : label is 1;
  attribute LC_PROBE740_WIDTH : integer;
  attribute LC_PROBE740_WIDTH of U0 : label is 1;
  attribute LC_PROBE741_IS_DATA : string;
  attribute LC_PROBE741_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE741_IS_TRIG : string;
  attribute LC_PROBE741_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE741_MU_CNT : integer;
  attribute LC_PROBE741_MU_CNT of U0 : label is 1;
  attribute LC_PROBE741_PID : string;
  attribute LC_PROBE741_PID of U0 : label is "16'b0000001011100101";
  attribute LC_PROBE741_TYPE : integer;
  attribute LC_PROBE741_TYPE of U0 : label is 1;
  attribute LC_PROBE741_WIDTH : integer;
  attribute LC_PROBE741_WIDTH of U0 : label is 1;
  attribute LC_PROBE742_IS_DATA : string;
  attribute LC_PROBE742_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE742_IS_TRIG : string;
  attribute LC_PROBE742_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE742_MU_CNT : integer;
  attribute LC_PROBE742_MU_CNT of U0 : label is 1;
  attribute LC_PROBE742_PID : string;
  attribute LC_PROBE742_PID of U0 : label is "16'b0000001011100110";
  attribute LC_PROBE742_TYPE : integer;
  attribute LC_PROBE742_TYPE of U0 : label is 1;
  attribute LC_PROBE742_WIDTH : integer;
  attribute LC_PROBE742_WIDTH of U0 : label is 1;
  attribute LC_PROBE743_IS_DATA : string;
  attribute LC_PROBE743_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE743_IS_TRIG : string;
  attribute LC_PROBE743_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE743_MU_CNT : integer;
  attribute LC_PROBE743_MU_CNT of U0 : label is 1;
  attribute LC_PROBE743_PID : string;
  attribute LC_PROBE743_PID of U0 : label is "16'b0000001011100111";
  attribute LC_PROBE743_TYPE : integer;
  attribute LC_PROBE743_TYPE of U0 : label is 1;
  attribute LC_PROBE743_WIDTH : integer;
  attribute LC_PROBE743_WIDTH of U0 : label is 1;
  attribute LC_PROBE744_IS_DATA : string;
  attribute LC_PROBE744_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE744_IS_TRIG : string;
  attribute LC_PROBE744_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE744_MU_CNT : integer;
  attribute LC_PROBE744_MU_CNT of U0 : label is 1;
  attribute LC_PROBE744_PID : string;
  attribute LC_PROBE744_PID of U0 : label is "16'b0000001011101000";
  attribute LC_PROBE744_TYPE : integer;
  attribute LC_PROBE744_TYPE of U0 : label is 1;
  attribute LC_PROBE744_WIDTH : integer;
  attribute LC_PROBE744_WIDTH of U0 : label is 1;
  attribute LC_PROBE745_IS_DATA : string;
  attribute LC_PROBE745_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE745_IS_TRIG : string;
  attribute LC_PROBE745_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE745_MU_CNT : integer;
  attribute LC_PROBE745_MU_CNT of U0 : label is 1;
  attribute LC_PROBE745_PID : string;
  attribute LC_PROBE745_PID of U0 : label is "16'b0000001011101001";
  attribute LC_PROBE745_TYPE : integer;
  attribute LC_PROBE745_TYPE of U0 : label is 1;
  attribute LC_PROBE745_WIDTH : integer;
  attribute LC_PROBE745_WIDTH of U0 : label is 1;
  attribute LC_PROBE746_IS_DATA : string;
  attribute LC_PROBE746_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE746_IS_TRIG : string;
  attribute LC_PROBE746_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE746_MU_CNT : integer;
  attribute LC_PROBE746_MU_CNT of U0 : label is 1;
  attribute LC_PROBE746_PID : string;
  attribute LC_PROBE746_PID of U0 : label is "16'b0000001011101010";
  attribute LC_PROBE746_TYPE : integer;
  attribute LC_PROBE746_TYPE of U0 : label is 1;
  attribute LC_PROBE746_WIDTH : integer;
  attribute LC_PROBE746_WIDTH of U0 : label is 1;
  attribute LC_PROBE747_IS_DATA : string;
  attribute LC_PROBE747_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE747_IS_TRIG : string;
  attribute LC_PROBE747_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE747_MU_CNT : integer;
  attribute LC_PROBE747_MU_CNT of U0 : label is 1;
  attribute LC_PROBE747_PID : string;
  attribute LC_PROBE747_PID of U0 : label is "16'b0000001011101011";
  attribute LC_PROBE747_TYPE : integer;
  attribute LC_PROBE747_TYPE of U0 : label is 1;
  attribute LC_PROBE747_WIDTH : integer;
  attribute LC_PROBE747_WIDTH of U0 : label is 1;
  attribute LC_PROBE748_IS_DATA : string;
  attribute LC_PROBE748_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE748_IS_TRIG : string;
  attribute LC_PROBE748_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE748_MU_CNT : integer;
  attribute LC_PROBE748_MU_CNT of U0 : label is 1;
  attribute LC_PROBE748_PID : string;
  attribute LC_PROBE748_PID of U0 : label is "16'b0000001011101100";
  attribute LC_PROBE748_TYPE : integer;
  attribute LC_PROBE748_TYPE of U0 : label is 1;
  attribute LC_PROBE748_WIDTH : integer;
  attribute LC_PROBE748_WIDTH of U0 : label is 1;
  attribute LC_PROBE749_IS_DATA : string;
  attribute LC_PROBE749_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE749_IS_TRIG : string;
  attribute LC_PROBE749_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE749_MU_CNT : integer;
  attribute LC_PROBE749_MU_CNT of U0 : label is 1;
  attribute LC_PROBE749_PID : string;
  attribute LC_PROBE749_PID of U0 : label is "16'b0000001011101101";
  attribute LC_PROBE749_TYPE : integer;
  attribute LC_PROBE749_TYPE of U0 : label is 1;
  attribute LC_PROBE749_WIDTH : integer;
  attribute LC_PROBE749_WIDTH of U0 : label is 1;
  attribute LC_PROBE74_IS_DATA : string;
  attribute LC_PROBE74_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE74_IS_TRIG : string;
  attribute LC_PROBE74_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE74_MU_CNT : integer;
  attribute LC_PROBE74_MU_CNT of U0 : label is 1;
  attribute LC_PROBE74_PID : string;
  attribute LC_PROBE74_PID of U0 : label is "16'b0000000001001010";
  attribute LC_PROBE74_TYPE : integer;
  attribute LC_PROBE74_TYPE of U0 : label is 1;
  attribute LC_PROBE74_WIDTH : integer;
  attribute LC_PROBE74_WIDTH of U0 : label is 1;
  attribute LC_PROBE750_IS_DATA : string;
  attribute LC_PROBE750_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE750_IS_TRIG : string;
  attribute LC_PROBE750_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE750_MU_CNT : integer;
  attribute LC_PROBE750_MU_CNT of U0 : label is 1;
  attribute LC_PROBE750_PID : string;
  attribute LC_PROBE750_PID of U0 : label is "16'b0000001011101110";
  attribute LC_PROBE750_TYPE : integer;
  attribute LC_PROBE750_TYPE of U0 : label is 1;
  attribute LC_PROBE750_WIDTH : integer;
  attribute LC_PROBE750_WIDTH of U0 : label is 1;
  attribute LC_PROBE751_IS_DATA : string;
  attribute LC_PROBE751_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE751_IS_TRIG : string;
  attribute LC_PROBE751_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE751_MU_CNT : integer;
  attribute LC_PROBE751_MU_CNT of U0 : label is 1;
  attribute LC_PROBE751_PID : string;
  attribute LC_PROBE751_PID of U0 : label is "16'b0000001011101111";
  attribute LC_PROBE751_TYPE : integer;
  attribute LC_PROBE751_TYPE of U0 : label is 1;
  attribute LC_PROBE751_WIDTH : integer;
  attribute LC_PROBE751_WIDTH of U0 : label is 1;
  attribute LC_PROBE752_IS_DATA : string;
  attribute LC_PROBE752_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE752_IS_TRIG : string;
  attribute LC_PROBE752_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE752_MU_CNT : integer;
  attribute LC_PROBE752_MU_CNT of U0 : label is 1;
  attribute LC_PROBE752_PID : string;
  attribute LC_PROBE752_PID of U0 : label is "16'b0000001011110000";
  attribute LC_PROBE752_TYPE : integer;
  attribute LC_PROBE752_TYPE of U0 : label is 1;
  attribute LC_PROBE752_WIDTH : integer;
  attribute LC_PROBE752_WIDTH of U0 : label is 1;
  attribute LC_PROBE753_IS_DATA : string;
  attribute LC_PROBE753_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE753_IS_TRIG : string;
  attribute LC_PROBE753_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE753_MU_CNT : integer;
  attribute LC_PROBE753_MU_CNT of U0 : label is 1;
  attribute LC_PROBE753_PID : string;
  attribute LC_PROBE753_PID of U0 : label is "16'b0000001011110001";
  attribute LC_PROBE753_TYPE : integer;
  attribute LC_PROBE753_TYPE of U0 : label is 1;
  attribute LC_PROBE753_WIDTH : integer;
  attribute LC_PROBE753_WIDTH of U0 : label is 1;
  attribute LC_PROBE754_IS_DATA : string;
  attribute LC_PROBE754_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE754_IS_TRIG : string;
  attribute LC_PROBE754_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE754_MU_CNT : integer;
  attribute LC_PROBE754_MU_CNT of U0 : label is 1;
  attribute LC_PROBE754_PID : string;
  attribute LC_PROBE754_PID of U0 : label is "16'b0000001011110010";
  attribute LC_PROBE754_TYPE : integer;
  attribute LC_PROBE754_TYPE of U0 : label is 1;
  attribute LC_PROBE754_WIDTH : integer;
  attribute LC_PROBE754_WIDTH of U0 : label is 1;
  attribute LC_PROBE755_IS_DATA : string;
  attribute LC_PROBE755_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE755_IS_TRIG : string;
  attribute LC_PROBE755_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE755_MU_CNT : integer;
  attribute LC_PROBE755_MU_CNT of U0 : label is 1;
  attribute LC_PROBE755_PID : string;
  attribute LC_PROBE755_PID of U0 : label is "16'b0000001011110011";
  attribute LC_PROBE755_TYPE : integer;
  attribute LC_PROBE755_TYPE of U0 : label is 1;
  attribute LC_PROBE755_WIDTH : integer;
  attribute LC_PROBE755_WIDTH of U0 : label is 1;
  attribute LC_PROBE756_IS_DATA : string;
  attribute LC_PROBE756_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE756_IS_TRIG : string;
  attribute LC_PROBE756_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE756_MU_CNT : integer;
  attribute LC_PROBE756_MU_CNT of U0 : label is 1;
  attribute LC_PROBE756_PID : string;
  attribute LC_PROBE756_PID of U0 : label is "16'b0000001011110100";
  attribute LC_PROBE756_TYPE : integer;
  attribute LC_PROBE756_TYPE of U0 : label is 1;
  attribute LC_PROBE756_WIDTH : integer;
  attribute LC_PROBE756_WIDTH of U0 : label is 1;
  attribute LC_PROBE757_IS_DATA : string;
  attribute LC_PROBE757_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE757_IS_TRIG : string;
  attribute LC_PROBE757_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE757_MU_CNT : integer;
  attribute LC_PROBE757_MU_CNT of U0 : label is 1;
  attribute LC_PROBE757_PID : string;
  attribute LC_PROBE757_PID of U0 : label is "16'b0000001011110101";
  attribute LC_PROBE757_TYPE : integer;
  attribute LC_PROBE757_TYPE of U0 : label is 1;
  attribute LC_PROBE757_WIDTH : integer;
  attribute LC_PROBE757_WIDTH of U0 : label is 1;
  attribute LC_PROBE758_IS_DATA : string;
  attribute LC_PROBE758_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE758_IS_TRIG : string;
  attribute LC_PROBE758_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE758_MU_CNT : integer;
  attribute LC_PROBE758_MU_CNT of U0 : label is 1;
  attribute LC_PROBE758_PID : string;
  attribute LC_PROBE758_PID of U0 : label is "16'b0000001011110110";
  attribute LC_PROBE758_TYPE : integer;
  attribute LC_PROBE758_TYPE of U0 : label is 1;
  attribute LC_PROBE758_WIDTH : integer;
  attribute LC_PROBE758_WIDTH of U0 : label is 1;
  attribute LC_PROBE759_IS_DATA : string;
  attribute LC_PROBE759_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE759_IS_TRIG : string;
  attribute LC_PROBE759_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE759_MU_CNT : integer;
  attribute LC_PROBE759_MU_CNT of U0 : label is 1;
  attribute LC_PROBE759_PID : string;
  attribute LC_PROBE759_PID of U0 : label is "16'b0000001011110111";
  attribute LC_PROBE759_TYPE : integer;
  attribute LC_PROBE759_TYPE of U0 : label is 1;
  attribute LC_PROBE759_WIDTH : integer;
  attribute LC_PROBE759_WIDTH of U0 : label is 1;
  attribute LC_PROBE75_IS_DATA : string;
  attribute LC_PROBE75_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE75_IS_TRIG : string;
  attribute LC_PROBE75_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE75_MU_CNT : integer;
  attribute LC_PROBE75_MU_CNT of U0 : label is 1;
  attribute LC_PROBE75_PID : string;
  attribute LC_PROBE75_PID of U0 : label is "16'b0000000001001011";
  attribute LC_PROBE75_TYPE : integer;
  attribute LC_PROBE75_TYPE of U0 : label is 1;
  attribute LC_PROBE75_WIDTH : integer;
  attribute LC_PROBE75_WIDTH of U0 : label is 1;
  attribute LC_PROBE760_IS_DATA : string;
  attribute LC_PROBE760_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE760_IS_TRIG : string;
  attribute LC_PROBE760_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE760_MU_CNT : integer;
  attribute LC_PROBE760_MU_CNT of U0 : label is 1;
  attribute LC_PROBE760_PID : string;
  attribute LC_PROBE760_PID of U0 : label is "16'b0000001011111000";
  attribute LC_PROBE760_TYPE : integer;
  attribute LC_PROBE760_TYPE of U0 : label is 1;
  attribute LC_PROBE760_WIDTH : integer;
  attribute LC_PROBE760_WIDTH of U0 : label is 1;
  attribute LC_PROBE761_IS_DATA : string;
  attribute LC_PROBE761_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE761_IS_TRIG : string;
  attribute LC_PROBE761_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE761_MU_CNT : integer;
  attribute LC_PROBE761_MU_CNT of U0 : label is 1;
  attribute LC_PROBE761_PID : string;
  attribute LC_PROBE761_PID of U0 : label is "16'b0000001011111001";
  attribute LC_PROBE761_TYPE : integer;
  attribute LC_PROBE761_TYPE of U0 : label is 1;
  attribute LC_PROBE761_WIDTH : integer;
  attribute LC_PROBE761_WIDTH of U0 : label is 1;
  attribute LC_PROBE762_IS_DATA : string;
  attribute LC_PROBE762_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE762_IS_TRIG : string;
  attribute LC_PROBE762_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE762_MU_CNT : integer;
  attribute LC_PROBE762_MU_CNT of U0 : label is 1;
  attribute LC_PROBE762_PID : string;
  attribute LC_PROBE762_PID of U0 : label is "16'b0000001011111010";
  attribute LC_PROBE762_TYPE : integer;
  attribute LC_PROBE762_TYPE of U0 : label is 1;
  attribute LC_PROBE762_WIDTH : integer;
  attribute LC_PROBE762_WIDTH of U0 : label is 1;
  attribute LC_PROBE763_IS_DATA : string;
  attribute LC_PROBE763_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE763_IS_TRIG : string;
  attribute LC_PROBE763_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE763_MU_CNT : integer;
  attribute LC_PROBE763_MU_CNT of U0 : label is 1;
  attribute LC_PROBE763_PID : string;
  attribute LC_PROBE763_PID of U0 : label is "16'b0000001011111011";
  attribute LC_PROBE763_TYPE : integer;
  attribute LC_PROBE763_TYPE of U0 : label is 1;
  attribute LC_PROBE763_WIDTH : integer;
  attribute LC_PROBE763_WIDTH of U0 : label is 1;
  attribute LC_PROBE764_IS_DATA : string;
  attribute LC_PROBE764_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE764_IS_TRIG : string;
  attribute LC_PROBE764_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE764_MU_CNT : integer;
  attribute LC_PROBE764_MU_CNT of U0 : label is 1;
  attribute LC_PROBE764_PID : string;
  attribute LC_PROBE764_PID of U0 : label is "16'b0000001011111100";
  attribute LC_PROBE764_TYPE : integer;
  attribute LC_PROBE764_TYPE of U0 : label is 1;
  attribute LC_PROBE764_WIDTH : integer;
  attribute LC_PROBE764_WIDTH of U0 : label is 1;
  attribute LC_PROBE765_IS_DATA : string;
  attribute LC_PROBE765_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE765_IS_TRIG : string;
  attribute LC_PROBE765_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE765_MU_CNT : integer;
  attribute LC_PROBE765_MU_CNT of U0 : label is 1;
  attribute LC_PROBE765_PID : string;
  attribute LC_PROBE765_PID of U0 : label is "16'b0000001011111101";
  attribute LC_PROBE765_TYPE : integer;
  attribute LC_PROBE765_TYPE of U0 : label is 1;
  attribute LC_PROBE765_WIDTH : integer;
  attribute LC_PROBE765_WIDTH of U0 : label is 1;
  attribute LC_PROBE766_IS_DATA : string;
  attribute LC_PROBE766_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE766_IS_TRIG : string;
  attribute LC_PROBE766_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE766_MU_CNT : integer;
  attribute LC_PROBE766_MU_CNT of U0 : label is 1;
  attribute LC_PROBE766_PID : string;
  attribute LC_PROBE766_PID of U0 : label is "16'b0000001011111110";
  attribute LC_PROBE766_TYPE : integer;
  attribute LC_PROBE766_TYPE of U0 : label is 1;
  attribute LC_PROBE766_WIDTH : integer;
  attribute LC_PROBE766_WIDTH of U0 : label is 1;
  attribute LC_PROBE767_IS_DATA : string;
  attribute LC_PROBE767_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE767_IS_TRIG : string;
  attribute LC_PROBE767_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE767_MU_CNT : integer;
  attribute LC_PROBE767_MU_CNT of U0 : label is 1;
  attribute LC_PROBE767_PID : string;
  attribute LC_PROBE767_PID of U0 : label is "16'b0000001011111111";
  attribute LC_PROBE767_TYPE : integer;
  attribute LC_PROBE767_TYPE of U0 : label is 1;
  attribute LC_PROBE767_WIDTH : integer;
  attribute LC_PROBE767_WIDTH of U0 : label is 1;
  attribute LC_PROBE768_IS_DATA : string;
  attribute LC_PROBE768_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE768_IS_TRIG : string;
  attribute LC_PROBE768_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE768_MU_CNT : integer;
  attribute LC_PROBE768_MU_CNT of U0 : label is 1;
  attribute LC_PROBE768_PID : string;
  attribute LC_PROBE768_PID of U0 : label is "16'b0000001100000000";
  attribute LC_PROBE768_TYPE : integer;
  attribute LC_PROBE768_TYPE of U0 : label is 1;
  attribute LC_PROBE768_WIDTH : integer;
  attribute LC_PROBE768_WIDTH of U0 : label is 1;
  attribute LC_PROBE769_IS_DATA : string;
  attribute LC_PROBE769_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE769_IS_TRIG : string;
  attribute LC_PROBE769_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE769_MU_CNT : integer;
  attribute LC_PROBE769_MU_CNT of U0 : label is 1;
  attribute LC_PROBE769_PID : string;
  attribute LC_PROBE769_PID of U0 : label is "16'b0000001100000001";
  attribute LC_PROBE769_TYPE : integer;
  attribute LC_PROBE769_TYPE of U0 : label is 1;
  attribute LC_PROBE769_WIDTH : integer;
  attribute LC_PROBE769_WIDTH of U0 : label is 1;
  attribute LC_PROBE76_IS_DATA : string;
  attribute LC_PROBE76_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE76_IS_TRIG : string;
  attribute LC_PROBE76_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE76_MU_CNT : integer;
  attribute LC_PROBE76_MU_CNT of U0 : label is 1;
  attribute LC_PROBE76_PID : string;
  attribute LC_PROBE76_PID of U0 : label is "16'b0000000001001100";
  attribute LC_PROBE76_TYPE : integer;
  attribute LC_PROBE76_TYPE of U0 : label is 1;
  attribute LC_PROBE76_WIDTH : integer;
  attribute LC_PROBE76_WIDTH of U0 : label is 1;
  attribute LC_PROBE770_IS_DATA : string;
  attribute LC_PROBE770_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE770_IS_TRIG : string;
  attribute LC_PROBE770_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE770_MU_CNT : integer;
  attribute LC_PROBE770_MU_CNT of U0 : label is 1;
  attribute LC_PROBE770_PID : string;
  attribute LC_PROBE770_PID of U0 : label is "16'b0000001100000010";
  attribute LC_PROBE770_TYPE : integer;
  attribute LC_PROBE770_TYPE of U0 : label is 1;
  attribute LC_PROBE770_WIDTH : integer;
  attribute LC_PROBE770_WIDTH of U0 : label is 1;
  attribute LC_PROBE771_IS_DATA : string;
  attribute LC_PROBE771_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE771_IS_TRIG : string;
  attribute LC_PROBE771_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE771_MU_CNT : integer;
  attribute LC_PROBE771_MU_CNT of U0 : label is 1;
  attribute LC_PROBE771_PID : string;
  attribute LC_PROBE771_PID of U0 : label is "16'b0000001100000011";
  attribute LC_PROBE771_TYPE : integer;
  attribute LC_PROBE771_TYPE of U0 : label is 1;
  attribute LC_PROBE771_WIDTH : integer;
  attribute LC_PROBE771_WIDTH of U0 : label is 1;
  attribute LC_PROBE772_IS_DATA : string;
  attribute LC_PROBE772_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE772_IS_TRIG : string;
  attribute LC_PROBE772_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE772_MU_CNT : integer;
  attribute LC_PROBE772_MU_CNT of U0 : label is 1;
  attribute LC_PROBE772_PID : string;
  attribute LC_PROBE772_PID of U0 : label is "16'b0000001100000100";
  attribute LC_PROBE772_TYPE : integer;
  attribute LC_PROBE772_TYPE of U0 : label is 1;
  attribute LC_PROBE772_WIDTH : integer;
  attribute LC_PROBE772_WIDTH of U0 : label is 1;
  attribute LC_PROBE773_IS_DATA : string;
  attribute LC_PROBE773_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE773_IS_TRIG : string;
  attribute LC_PROBE773_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE773_MU_CNT : integer;
  attribute LC_PROBE773_MU_CNT of U0 : label is 1;
  attribute LC_PROBE773_PID : string;
  attribute LC_PROBE773_PID of U0 : label is "16'b0000001100000101";
  attribute LC_PROBE773_TYPE : integer;
  attribute LC_PROBE773_TYPE of U0 : label is 1;
  attribute LC_PROBE773_WIDTH : integer;
  attribute LC_PROBE773_WIDTH of U0 : label is 1;
  attribute LC_PROBE774_IS_DATA : string;
  attribute LC_PROBE774_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE774_IS_TRIG : string;
  attribute LC_PROBE774_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE774_MU_CNT : integer;
  attribute LC_PROBE774_MU_CNT of U0 : label is 1;
  attribute LC_PROBE774_PID : string;
  attribute LC_PROBE774_PID of U0 : label is "16'b0000001100000110";
  attribute LC_PROBE774_TYPE : integer;
  attribute LC_PROBE774_TYPE of U0 : label is 1;
  attribute LC_PROBE774_WIDTH : integer;
  attribute LC_PROBE774_WIDTH of U0 : label is 1;
  attribute LC_PROBE775_IS_DATA : string;
  attribute LC_PROBE775_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE775_IS_TRIG : string;
  attribute LC_PROBE775_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE775_MU_CNT : integer;
  attribute LC_PROBE775_MU_CNT of U0 : label is 1;
  attribute LC_PROBE775_PID : string;
  attribute LC_PROBE775_PID of U0 : label is "16'b0000001100000111";
  attribute LC_PROBE775_TYPE : integer;
  attribute LC_PROBE775_TYPE of U0 : label is 1;
  attribute LC_PROBE775_WIDTH : integer;
  attribute LC_PROBE775_WIDTH of U0 : label is 1;
  attribute LC_PROBE776_IS_DATA : string;
  attribute LC_PROBE776_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE776_IS_TRIG : string;
  attribute LC_PROBE776_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE776_MU_CNT : integer;
  attribute LC_PROBE776_MU_CNT of U0 : label is 1;
  attribute LC_PROBE776_PID : string;
  attribute LC_PROBE776_PID of U0 : label is "16'b0000001100001000";
  attribute LC_PROBE776_TYPE : integer;
  attribute LC_PROBE776_TYPE of U0 : label is 1;
  attribute LC_PROBE776_WIDTH : integer;
  attribute LC_PROBE776_WIDTH of U0 : label is 1;
  attribute LC_PROBE777_IS_DATA : string;
  attribute LC_PROBE777_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE777_IS_TRIG : string;
  attribute LC_PROBE777_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE777_MU_CNT : integer;
  attribute LC_PROBE777_MU_CNT of U0 : label is 1;
  attribute LC_PROBE777_PID : string;
  attribute LC_PROBE777_PID of U0 : label is "16'b0000001100001001";
  attribute LC_PROBE777_TYPE : integer;
  attribute LC_PROBE777_TYPE of U0 : label is 1;
  attribute LC_PROBE777_WIDTH : integer;
  attribute LC_PROBE777_WIDTH of U0 : label is 1;
  attribute LC_PROBE778_IS_DATA : string;
  attribute LC_PROBE778_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE778_IS_TRIG : string;
  attribute LC_PROBE778_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE778_MU_CNT : integer;
  attribute LC_PROBE778_MU_CNT of U0 : label is 1;
  attribute LC_PROBE778_PID : string;
  attribute LC_PROBE778_PID of U0 : label is "16'b0000001100001010";
  attribute LC_PROBE778_TYPE : integer;
  attribute LC_PROBE778_TYPE of U0 : label is 1;
  attribute LC_PROBE778_WIDTH : integer;
  attribute LC_PROBE778_WIDTH of U0 : label is 1;
  attribute LC_PROBE779_IS_DATA : string;
  attribute LC_PROBE779_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE779_IS_TRIG : string;
  attribute LC_PROBE779_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE779_MU_CNT : integer;
  attribute LC_PROBE779_MU_CNT of U0 : label is 1;
  attribute LC_PROBE779_PID : string;
  attribute LC_PROBE779_PID of U0 : label is "16'b0000001100001011";
  attribute LC_PROBE779_TYPE : integer;
  attribute LC_PROBE779_TYPE of U0 : label is 1;
  attribute LC_PROBE779_WIDTH : integer;
  attribute LC_PROBE779_WIDTH of U0 : label is 1;
  attribute LC_PROBE77_IS_DATA : string;
  attribute LC_PROBE77_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE77_IS_TRIG : string;
  attribute LC_PROBE77_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE77_MU_CNT : integer;
  attribute LC_PROBE77_MU_CNT of U0 : label is 1;
  attribute LC_PROBE77_PID : string;
  attribute LC_PROBE77_PID of U0 : label is "16'b0000000001001101";
  attribute LC_PROBE77_TYPE : integer;
  attribute LC_PROBE77_TYPE of U0 : label is 1;
  attribute LC_PROBE77_WIDTH : integer;
  attribute LC_PROBE77_WIDTH of U0 : label is 1;
  attribute LC_PROBE780_IS_DATA : string;
  attribute LC_PROBE780_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE780_IS_TRIG : string;
  attribute LC_PROBE780_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE780_MU_CNT : integer;
  attribute LC_PROBE780_MU_CNT of U0 : label is 1;
  attribute LC_PROBE780_PID : string;
  attribute LC_PROBE780_PID of U0 : label is "16'b0000001100001100";
  attribute LC_PROBE780_TYPE : integer;
  attribute LC_PROBE780_TYPE of U0 : label is 1;
  attribute LC_PROBE780_WIDTH : integer;
  attribute LC_PROBE780_WIDTH of U0 : label is 1;
  attribute LC_PROBE781_IS_DATA : string;
  attribute LC_PROBE781_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE781_IS_TRIG : string;
  attribute LC_PROBE781_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE781_MU_CNT : integer;
  attribute LC_PROBE781_MU_CNT of U0 : label is 1;
  attribute LC_PROBE781_PID : string;
  attribute LC_PROBE781_PID of U0 : label is "16'b0000001100001101";
  attribute LC_PROBE781_TYPE : integer;
  attribute LC_PROBE781_TYPE of U0 : label is 1;
  attribute LC_PROBE781_WIDTH : integer;
  attribute LC_PROBE781_WIDTH of U0 : label is 1;
  attribute LC_PROBE782_IS_DATA : string;
  attribute LC_PROBE782_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE782_IS_TRIG : string;
  attribute LC_PROBE782_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE782_MU_CNT : integer;
  attribute LC_PROBE782_MU_CNT of U0 : label is 1;
  attribute LC_PROBE782_PID : string;
  attribute LC_PROBE782_PID of U0 : label is "16'b0000001100001110";
  attribute LC_PROBE782_TYPE : integer;
  attribute LC_PROBE782_TYPE of U0 : label is 1;
  attribute LC_PROBE782_WIDTH : integer;
  attribute LC_PROBE782_WIDTH of U0 : label is 1;
  attribute LC_PROBE783_IS_DATA : string;
  attribute LC_PROBE783_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE783_IS_TRIG : string;
  attribute LC_PROBE783_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE783_MU_CNT : integer;
  attribute LC_PROBE783_MU_CNT of U0 : label is 1;
  attribute LC_PROBE783_PID : string;
  attribute LC_PROBE783_PID of U0 : label is "16'b0000001100001111";
  attribute LC_PROBE783_TYPE : integer;
  attribute LC_PROBE783_TYPE of U0 : label is 1;
  attribute LC_PROBE783_WIDTH : integer;
  attribute LC_PROBE783_WIDTH of U0 : label is 1;
  attribute LC_PROBE784_IS_DATA : string;
  attribute LC_PROBE784_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE784_IS_TRIG : string;
  attribute LC_PROBE784_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE784_MU_CNT : integer;
  attribute LC_PROBE784_MU_CNT of U0 : label is 1;
  attribute LC_PROBE784_PID : string;
  attribute LC_PROBE784_PID of U0 : label is "16'b0000001100010000";
  attribute LC_PROBE784_TYPE : integer;
  attribute LC_PROBE784_TYPE of U0 : label is 1;
  attribute LC_PROBE784_WIDTH : integer;
  attribute LC_PROBE784_WIDTH of U0 : label is 1;
  attribute LC_PROBE785_IS_DATA : string;
  attribute LC_PROBE785_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE785_IS_TRIG : string;
  attribute LC_PROBE785_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE785_MU_CNT : integer;
  attribute LC_PROBE785_MU_CNT of U0 : label is 1;
  attribute LC_PROBE785_PID : string;
  attribute LC_PROBE785_PID of U0 : label is "16'b0000001100010001";
  attribute LC_PROBE785_TYPE : integer;
  attribute LC_PROBE785_TYPE of U0 : label is 1;
  attribute LC_PROBE785_WIDTH : integer;
  attribute LC_PROBE785_WIDTH of U0 : label is 1;
  attribute LC_PROBE786_IS_DATA : string;
  attribute LC_PROBE786_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE786_IS_TRIG : string;
  attribute LC_PROBE786_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE786_MU_CNT : integer;
  attribute LC_PROBE786_MU_CNT of U0 : label is 1;
  attribute LC_PROBE786_PID : string;
  attribute LC_PROBE786_PID of U0 : label is "16'b0000001100010010";
  attribute LC_PROBE786_TYPE : integer;
  attribute LC_PROBE786_TYPE of U0 : label is 1;
  attribute LC_PROBE786_WIDTH : integer;
  attribute LC_PROBE786_WIDTH of U0 : label is 1;
  attribute LC_PROBE787_IS_DATA : string;
  attribute LC_PROBE787_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE787_IS_TRIG : string;
  attribute LC_PROBE787_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE787_MU_CNT : integer;
  attribute LC_PROBE787_MU_CNT of U0 : label is 1;
  attribute LC_PROBE787_PID : string;
  attribute LC_PROBE787_PID of U0 : label is "16'b0000001100010011";
  attribute LC_PROBE787_TYPE : integer;
  attribute LC_PROBE787_TYPE of U0 : label is 1;
  attribute LC_PROBE787_WIDTH : integer;
  attribute LC_PROBE787_WIDTH of U0 : label is 1;
  attribute LC_PROBE788_IS_DATA : string;
  attribute LC_PROBE788_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE788_IS_TRIG : string;
  attribute LC_PROBE788_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE788_MU_CNT : integer;
  attribute LC_PROBE788_MU_CNT of U0 : label is 1;
  attribute LC_PROBE788_PID : string;
  attribute LC_PROBE788_PID of U0 : label is "16'b0000001100010100";
  attribute LC_PROBE788_TYPE : integer;
  attribute LC_PROBE788_TYPE of U0 : label is 1;
  attribute LC_PROBE788_WIDTH : integer;
  attribute LC_PROBE788_WIDTH of U0 : label is 1;
  attribute LC_PROBE789_IS_DATA : string;
  attribute LC_PROBE789_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE789_IS_TRIG : string;
  attribute LC_PROBE789_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE789_MU_CNT : integer;
  attribute LC_PROBE789_MU_CNT of U0 : label is 1;
  attribute LC_PROBE789_PID : string;
  attribute LC_PROBE789_PID of U0 : label is "16'b0000001100010101";
  attribute LC_PROBE789_TYPE : integer;
  attribute LC_PROBE789_TYPE of U0 : label is 1;
  attribute LC_PROBE789_WIDTH : integer;
  attribute LC_PROBE789_WIDTH of U0 : label is 1;
  attribute LC_PROBE78_IS_DATA : string;
  attribute LC_PROBE78_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE78_IS_TRIG : string;
  attribute LC_PROBE78_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE78_MU_CNT : integer;
  attribute LC_PROBE78_MU_CNT of U0 : label is 1;
  attribute LC_PROBE78_PID : string;
  attribute LC_PROBE78_PID of U0 : label is "16'b0000000001001110";
  attribute LC_PROBE78_TYPE : integer;
  attribute LC_PROBE78_TYPE of U0 : label is 1;
  attribute LC_PROBE78_WIDTH : integer;
  attribute LC_PROBE78_WIDTH of U0 : label is 1;
  attribute LC_PROBE790_IS_DATA : string;
  attribute LC_PROBE790_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE790_IS_TRIG : string;
  attribute LC_PROBE790_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE790_MU_CNT : integer;
  attribute LC_PROBE790_MU_CNT of U0 : label is 1;
  attribute LC_PROBE790_PID : string;
  attribute LC_PROBE790_PID of U0 : label is "16'b0000001100010110";
  attribute LC_PROBE790_TYPE : integer;
  attribute LC_PROBE790_TYPE of U0 : label is 1;
  attribute LC_PROBE790_WIDTH : integer;
  attribute LC_PROBE790_WIDTH of U0 : label is 1;
  attribute LC_PROBE791_IS_DATA : string;
  attribute LC_PROBE791_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE791_IS_TRIG : string;
  attribute LC_PROBE791_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE791_MU_CNT : integer;
  attribute LC_PROBE791_MU_CNT of U0 : label is 1;
  attribute LC_PROBE791_PID : string;
  attribute LC_PROBE791_PID of U0 : label is "16'b0000001100010111";
  attribute LC_PROBE791_TYPE : integer;
  attribute LC_PROBE791_TYPE of U0 : label is 1;
  attribute LC_PROBE791_WIDTH : integer;
  attribute LC_PROBE791_WIDTH of U0 : label is 1;
  attribute LC_PROBE792_IS_DATA : string;
  attribute LC_PROBE792_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE792_IS_TRIG : string;
  attribute LC_PROBE792_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE792_MU_CNT : integer;
  attribute LC_PROBE792_MU_CNT of U0 : label is 1;
  attribute LC_PROBE792_PID : string;
  attribute LC_PROBE792_PID of U0 : label is "16'b0000001100011000";
  attribute LC_PROBE792_TYPE : integer;
  attribute LC_PROBE792_TYPE of U0 : label is 1;
  attribute LC_PROBE792_WIDTH : integer;
  attribute LC_PROBE792_WIDTH of U0 : label is 1;
  attribute LC_PROBE793_IS_DATA : string;
  attribute LC_PROBE793_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE793_IS_TRIG : string;
  attribute LC_PROBE793_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE793_MU_CNT : integer;
  attribute LC_PROBE793_MU_CNT of U0 : label is 1;
  attribute LC_PROBE793_PID : string;
  attribute LC_PROBE793_PID of U0 : label is "16'b0000001100011001";
  attribute LC_PROBE793_TYPE : integer;
  attribute LC_PROBE793_TYPE of U0 : label is 1;
  attribute LC_PROBE793_WIDTH : integer;
  attribute LC_PROBE793_WIDTH of U0 : label is 1;
  attribute LC_PROBE794_IS_DATA : string;
  attribute LC_PROBE794_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE794_IS_TRIG : string;
  attribute LC_PROBE794_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE794_MU_CNT : integer;
  attribute LC_PROBE794_MU_CNT of U0 : label is 1;
  attribute LC_PROBE794_PID : string;
  attribute LC_PROBE794_PID of U0 : label is "16'b0000001100011010";
  attribute LC_PROBE794_TYPE : integer;
  attribute LC_PROBE794_TYPE of U0 : label is 1;
  attribute LC_PROBE794_WIDTH : integer;
  attribute LC_PROBE794_WIDTH of U0 : label is 1;
  attribute LC_PROBE795_IS_DATA : string;
  attribute LC_PROBE795_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE795_IS_TRIG : string;
  attribute LC_PROBE795_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE795_MU_CNT : integer;
  attribute LC_PROBE795_MU_CNT of U0 : label is 1;
  attribute LC_PROBE795_PID : string;
  attribute LC_PROBE795_PID of U0 : label is "16'b0000001100011011";
  attribute LC_PROBE795_TYPE : integer;
  attribute LC_PROBE795_TYPE of U0 : label is 1;
  attribute LC_PROBE795_WIDTH : integer;
  attribute LC_PROBE795_WIDTH of U0 : label is 1;
  attribute LC_PROBE796_IS_DATA : string;
  attribute LC_PROBE796_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE796_IS_TRIG : string;
  attribute LC_PROBE796_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE796_MU_CNT : integer;
  attribute LC_PROBE796_MU_CNT of U0 : label is 1;
  attribute LC_PROBE796_PID : string;
  attribute LC_PROBE796_PID of U0 : label is "16'b0000001100011100";
  attribute LC_PROBE796_TYPE : integer;
  attribute LC_PROBE796_TYPE of U0 : label is 1;
  attribute LC_PROBE796_WIDTH : integer;
  attribute LC_PROBE796_WIDTH of U0 : label is 1;
  attribute LC_PROBE797_IS_DATA : string;
  attribute LC_PROBE797_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE797_IS_TRIG : string;
  attribute LC_PROBE797_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE797_MU_CNT : integer;
  attribute LC_PROBE797_MU_CNT of U0 : label is 1;
  attribute LC_PROBE797_PID : string;
  attribute LC_PROBE797_PID of U0 : label is "16'b0000001100011101";
  attribute LC_PROBE797_TYPE : integer;
  attribute LC_PROBE797_TYPE of U0 : label is 1;
  attribute LC_PROBE797_WIDTH : integer;
  attribute LC_PROBE797_WIDTH of U0 : label is 1;
  attribute LC_PROBE798_IS_DATA : string;
  attribute LC_PROBE798_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE798_IS_TRIG : string;
  attribute LC_PROBE798_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE798_MU_CNT : integer;
  attribute LC_PROBE798_MU_CNT of U0 : label is 1;
  attribute LC_PROBE798_PID : string;
  attribute LC_PROBE798_PID of U0 : label is "16'b0000001100011110";
  attribute LC_PROBE798_TYPE : integer;
  attribute LC_PROBE798_TYPE of U0 : label is 1;
  attribute LC_PROBE798_WIDTH : integer;
  attribute LC_PROBE798_WIDTH of U0 : label is 1;
  attribute LC_PROBE799_IS_DATA : string;
  attribute LC_PROBE799_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE799_IS_TRIG : string;
  attribute LC_PROBE799_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE799_MU_CNT : integer;
  attribute LC_PROBE799_MU_CNT of U0 : label is 1;
  attribute LC_PROBE799_PID : string;
  attribute LC_PROBE799_PID of U0 : label is "16'b0000001100011111";
  attribute LC_PROBE799_TYPE : integer;
  attribute LC_PROBE799_TYPE of U0 : label is 1;
  attribute LC_PROBE799_WIDTH : integer;
  attribute LC_PROBE799_WIDTH of U0 : label is 1;
  attribute LC_PROBE79_IS_DATA : string;
  attribute LC_PROBE79_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE79_IS_TRIG : string;
  attribute LC_PROBE79_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE79_MU_CNT : integer;
  attribute LC_PROBE79_MU_CNT of U0 : label is 1;
  attribute LC_PROBE79_PID : string;
  attribute LC_PROBE79_PID of U0 : label is "16'b0000000001001111";
  attribute LC_PROBE79_TYPE : integer;
  attribute LC_PROBE79_TYPE of U0 : label is 1;
  attribute LC_PROBE79_WIDTH : integer;
  attribute LC_PROBE79_WIDTH of U0 : label is 1;
  attribute LC_PROBE7_IS_DATA : string;
  attribute LC_PROBE7_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE7_IS_TRIG : string;
  attribute LC_PROBE7_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE7_MU_CNT : integer;
  attribute LC_PROBE7_MU_CNT of U0 : label is 1;
  attribute LC_PROBE7_PID : string;
  attribute LC_PROBE7_PID of U0 : label is "16'b0000000000000111";
  attribute LC_PROBE7_TYPE : integer;
  attribute LC_PROBE7_TYPE of U0 : label is 1;
  attribute LC_PROBE7_WIDTH : integer;
  attribute LC_PROBE7_WIDTH of U0 : label is 1;
  attribute LC_PROBE800_IS_DATA : string;
  attribute LC_PROBE800_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE800_IS_TRIG : string;
  attribute LC_PROBE800_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE800_MU_CNT : integer;
  attribute LC_PROBE800_MU_CNT of U0 : label is 1;
  attribute LC_PROBE800_PID : string;
  attribute LC_PROBE800_PID of U0 : label is "16'b0000001100100000";
  attribute LC_PROBE800_TYPE : integer;
  attribute LC_PROBE800_TYPE of U0 : label is 1;
  attribute LC_PROBE800_WIDTH : integer;
  attribute LC_PROBE800_WIDTH of U0 : label is 1;
  attribute LC_PROBE801_IS_DATA : string;
  attribute LC_PROBE801_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE801_IS_TRIG : string;
  attribute LC_PROBE801_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE801_MU_CNT : integer;
  attribute LC_PROBE801_MU_CNT of U0 : label is 1;
  attribute LC_PROBE801_PID : string;
  attribute LC_PROBE801_PID of U0 : label is "16'b0000001100100001";
  attribute LC_PROBE801_TYPE : integer;
  attribute LC_PROBE801_TYPE of U0 : label is 1;
  attribute LC_PROBE801_WIDTH : integer;
  attribute LC_PROBE801_WIDTH of U0 : label is 1;
  attribute LC_PROBE802_IS_DATA : string;
  attribute LC_PROBE802_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE802_IS_TRIG : string;
  attribute LC_PROBE802_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE802_MU_CNT : integer;
  attribute LC_PROBE802_MU_CNT of U0 : label is 1;
  attribute LC_PROBE802_PID : string;
  attribute LC_PROBE802_PID of U0 : label is "16'b0000001100100010";
  attribute LC_PROBE802_TYPE : integer;
  attribute LC_PROBE802_TYPE of U0 : label is 1;
  attribute LC_PROBE802_WIDTH : integer;
  attribute LC_PROBE802_WIDTH of U0 : label is 1;
  attribute LC_PROBE803_IS_DATA : string;
  attribute LC_PROBE803_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE803_IS_TRIG : string;
  attribute LC_PROBE803_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE803_MU_CNT : integer;
  attribute LC_PROBE803_MU_CNT of U0 : label is 1;
  attribute LC_PROBE803_PID : string;
  attribute LC_PROBE803_PID of U0 : label is "16'b0000001100100011";
  attribute LC_PROBE803_TYPE : integer;
  attribute LC_PROBE803_TYPE of U0 : label is 1;
  attribute LC_PROBE803_WIDTH : integer;
  attribute LC_PROBE803_WIDTH of U0 : label is 1;
  attribute LC_PROBE804_IS_DATA : string;
  attribute LC_PROBE804_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE804_IS_TRIG : string;
  attribute LC_PROBE804_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE804_MU_CNT : integer;
  attribute LC_PROBE804_MU_CNT of U0 : label is 1;
  attribute LC_PROBE804_PID : string;
  attribute LC_PROBE804_PID of U0 : label is "16'b0000001100100100";
  attribute LC_PROBE804_TYPE : integer;
  attribute LC_PROBE804_TYPE of U0 : label is 1;
  attribute LC_PROBE804_WIDTH : integer;
  attribute LC_PROBE804_WIDTH of U0 : label is 1;
  attribute LC_PROBE805_IS_DATA : string;
  attribute LC_PROBE805_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE805_IS_TRIG : string;
  attribute LC_PROBE805_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE805_MU_CNT : integer;
  attribute LC_PROBE805_MU_CNT of U0 : label is 1;
  attribute LC_PROBE805_PID : string;
  attribute LC_PROBE805_PID of U0 : label is "16'b0000001100100101";
  attribute LC_PROBE805_TYPE : integer;
  attribute LC_PROBE805_TYPE of U0 : label is 1;
  attribute LC_PROBE805_WIDTH : integer;
  attribute LC_PROBE805_WIDTH of U0 : label is 1;
  attribute LC_PROBE806_IS_DATA : string;
  attribute LC_PROBE806_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE806_IS_TRIG : string;
  attribute LC_PROBE806_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE806_MU_CNT : integer;
  attribute LC_PROBE806_MU_CNT of U0 : label is 1;
  attribute LC_PROBE806_PID : string;
  attribute LC_PROBE806_PID of U0 : label is "16'b0000001100100110";
  attribute LC_PROBE806_TYPE : integer;
  attribute LC_PROBE806_TYPE of U0 : label is 1;
  attribute LC_PROBE806_WIDTH : integer;
  attribute LC_PROBE806_WIDTH of U0 : label is 1;
  attribute LC_PROBE807_IS_DATA : string;
  attribute LC_PROBE807_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE807_IS_TRIG : string;
  attribute LC_PROBE807_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE807_MU_CNT : integer;
  attribute LC_PROBE807_MU_CNT of U0 : label is 1;
  attribute LC_PROBE807_PID : string;
  attribute LC_PROBE807_PID of U0 : label is "16'b0000001100100111";
  attribute LC_PROBE807_TYPE : integer;
  attribute LC_PROBE807_TYPE of U0 : label is 1;
  attribute LC_PROBE807_WIDTH : integer;
  attribute LC_PROBE807_WIDTH of U0 : label is 1;
  attribute LC_PROBE808_IS_DATA : string;
  attribute LC_PROBE808_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE808_IS_TRIG : string;
  attribute LC_PROBE808_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE808_MU_CNT : integer;
  attribute LC_PROBE808_MU_CNT of U0 : label is 1;
  attribute LC_PROBE808_PID : string;
  attribute LC_PROBE808_PID of U0 : label is "16'b0000001100101000";
  attribute LC_PROBE808_TYPE : integer;
  attribute LC_PROBE808_TYPE of U0 : label is 1;
  attribute LC_PROBE808_WIDTH : integer;
  attribute LC_PROBE808_WIDTH of U0 : label is 1;
  attribute LC_PROBE809_IS_DATA : string;
  attribute LC_PROBE809_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE809_IS_TRIG : string;
  attribute LC_PROBE809_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE809_MU_CNT : integer;
  attribute LC_PROBE809_MU_CNT of U0 : label is 1;
  attribute LC_PROBE809_PID : string;
  attribute LC_PROBE809_PID of U0 : label is "16'b0000001100101001";
  attribute LC_PROBE809_TYPE : integer;
  attribute LC_PROBE809_TYPE of U0 : label is 1;
  attribute LC_PROBE809_WIDTH : integer;
  attribute LC_PROBE809_WIDTH of U0 : label is 1;
  attribute LC_PROBE80_IS_DATA : string;
  attribute LC_PROBE80_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE80_IS_TRIG : string;
  attribute LC_PROBE80_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE80_MU_CNT : integer;
  attribute LC_PROBE80_MU_CNT of U0 : label is 1;
  attribute LC_PROBE80_PID : string;
  attribute LC_PROBE80_PID of U0 : label is "16'b0000000001010000";
  attribute LC_PROBE80_TYPE : integer;
  attribute LC_PROBE80_TYPE of U0 : label is 1;
  attribute LC_PROBE80_WIDTH : integer;
  attribute LC_PROBE80_WIDTH of U0 : label is 1;
  attribute LC_PROBE810_IS_DATA : string;
  attribute LC_PROBE810_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE810_IS_TRIG : string;
  attribute LC_PROBE810_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE810_MU_CNT : integer;
  attribute LC_PROBE810_MU_CNT of U0 : label is 1;
  attribute LC_PROBE810_PID : string;
  attribute LC_PROBE810_PID of U0 : label is "16'b0000001100101010";
  attribute LC_PROBE810_TYPE : integer;
  attribute LC_PROBE810_TYPE of U0 : label is 1;
  attribute LC_PROBE810_WIDTH : integer;
  attribute LC_PROBE810_WIDTH of U0 : label is 1;
  attribute LC_PROBE811_IS_DATA : string;
  attribute LC_PROBE811_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE811_IS_TRIG : string;
  attribute LC_PROBE811_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE811_MU_CNT : integer;
  attribute LC_PROBE811_MU_CNT of U0 : label is 1;
  attribute LC_PROBE811_PID : string;
  attribute LC_PROBE811_PID of U0 : label is "16'b0000001100101011";
  attribute LC_PROBE811_TYPE : integer;
  attribute LC_PROBE811_TYPE of U0 : label is 1;
  attribute LC_PROBE811_WIDTH : integer;
  attribute LC_PROBE811_WIDTH of U0 : label is 1;
  attribute LC_PROBE812_IS_DATA : string;
  attribute LC_PROBE812_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE812_IS_TRIG : string;
  attribute LC_PROBE812_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE812_MU_CNT : integer;
  attribute LC_PROBE812_MU_CNT of U0 : label is 1;
  attribute LC_PROBE812_PID : string;
  attribute LC_PROBE812_PID of U0 : label is "16'b0000001100101100";
  attribute LC_PROBE812_TYPE : integer;
  attribute LC_PROBE812_TYPE of U0 : label is 1;
  attribute LC_PROBE812_WIDTH : integer;
  attribute LC_PROBE812_WIDTH of U0 : label is 1;
  attribute LC_PROBE813_IS_DATA : string;
  attribute LC_PROBE813_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE813_IS_TRIG : string;
  attribute LC_PROBE813_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE813_MU_CNT : integer;
  attribute LC_PROBE813_MU_CNT of U0 : label is 1;
  attribute LC_PROBE813_PID : string;
  attribute LC_PROBE813_PID of U0 : label is "16'b0000001100101101";
  attribute LC_PROBE813_TYPE : integer;
  attribute LC_PROBE813_TYPE of U0 : label is 1;
  attribute LC_PROBE813_WIDTH : integer;
  attribute LC_PROBE813_WIDTH of U0 : label is 1;
  attribute LC_PROBE814_IS_DATA : string;
  attribute LC_PROBE814_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE814_IS_TRIG : string;
  attribute LC_PROBE814_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE814_MU_CNT : integer;
  attribute LC_PROBE814_MU_CNT of U0 : label is 1;
  attribute LC_PROBE814_PID : string;
  attribute LC_PROBE814_PID of U0 : label is "16'b0000001100101110";
  attribute LC_PROBE814_TYPE : integer;
  attribute LC_PROBE814_TYPE of U0 : label is 1;
  attribute LC_PROBE814_WIDTH : integer;
  attribute LC_PROBE814_WIDTH of U0 : label is 1;
  attribute LC_PROBE815_IS_DATA : string;
  attribute LC_PROBE815_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE815_IS_TRIG : string;
  attribute LC_PROBE815_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE815_MU_CNT : integer;
  attribute LC_PROBE815_MU_CNT of U0 : label is 1;
  attribute LC_PROBE815_PID : string;
  attribute LC_PROBE815_PID of U0 : label is "16'b0000001100101111";
  attribute LC_PROBE815_TYPE : integer;
  attribute LC_PROBE815_TYPE of U0 : label is 1;
  attribute LC_PROBE815_WIDTH : integer;
  attribute LC_PROBE815_WIDTH of U0 : label is 1;
  attribute LC_PROBE816_IS_DATA : string;
  attribute LC_PROBE816_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE816_IS_TRIG : string;
  attribute LC_PROBE816_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE816_MU_CNT : integer;
  attribute LC_PROBE816_MU_CNT of U0 : label is 1;
  attribute LC_PROBE816_PID : string;
  attribute LC_PROBE816_PID of U0 : label is "16'b0000001100110000";
  attribute LC_PROBE816_TYPE : integer;
  attribute LC_PROBE816_TYPE of U0 : label is 1;
  attribute LC_PROBE816_WIDTH : integer;
  attribute LC_PROBE816_WIDTH of U0 : label is 1;
  attribute LC_PROBE817_IS_DATA : string;
  attribute LC_PROBE817_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE817_IS_TRIG : string;
  attribute LC_PROBE817_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE817_MU_CNT : integer;
  attribute LC_PROBE817_MU_CNT of U0 : label is 1;
  attribute LC_PROBE817_PID : string;
  attribute LC_PROBE817_PID of U0 : label is "16'b0000001100110001";
  attribute LC_PROBE817_TYPE : integer;
  attribute LC_PROBE817_TYPE of U0 : label is 1;
  attribute LC_PROBE817_WIDTH : integer;
  attribute LC_PROBE817_WIDTH of U0 : label is 1;
  attribute LC_PROBE818_IS_DATA : string;
  attribute LC_PROBE818_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE818_IS_TRIG : string;
  attribute LC_PROBE818_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE818_MU_CNT : integer;
  attribute LC_PROBE818_MU_CNT of U0 : label is 1;
  attribute LC_PROBE818_PID : string;
  attribute LC_PROBE818_PID of U0 : label is "16'b0000001100110010";
  attribute LC_PROBE818_TYPE : integer;
  attribute LC_PROBE818_TYPE of U0 : label is 1;
  attribute LC_PROBE818_WIDTH : integer;
  attribute LC_PROBE818_WIDTH of U0 : label is 1;
  attribute LC_PROBE819_IS_DATA : string;
  attribute LC_PROBE819_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE819_IS_TRIG : string;
  attribute LC_PROBE819_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE819_MU_CNT : integer;
  attribute LC_PROBE819_MU_CNT of U0 : label is 1;
  attribute LC_PROBE819_PID : string;
  attribute LC_PROBE819_PID of U0 : label is "16'b0000001100110011";
  attribute LC_PROBE819_TYPE : integer;
  attribute LC_PROBE819_TYPE of U0 : label is 1;
  attribute LC_PROBE819_WIDTH : integer;
  attribute LC_PROBE819_WIDTH of U0 : label is 1;
  attribute LC_PROBE81_IS_DATA : string;
  attribute LC_PROBE81_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE81_IS_TRIG : string;
  attribute LC_PROBE81_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE81_MU_CNT : integer;
  attribute LC_PROBE81_MU_CNT of U0 : label is 1;
  attribute LC_PROBE81_PID : string;
  attribute LC_PROBE81_PID of U0 : label is "16'b0000000001010001";
  attribute LC_PROBE81_TYPE : integer;
  attribute LC_PROBE81_TYPE of U0 : label is 1;
  attribute LC_PROBE81_WIDTH : integer;
  attribute LC_PROBE81_WIDTH of U0 : label is 1;
  attribute LC_PROBE820_IS_DATA : string;
  attribute LC_PROBE820_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE820_IS_TRIG : string;
  attribute LC_PROBE820_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE820_MU_CNT : integer;
  attribute LC_PROBE820_MU_CNT of U0 : label is 1;
  attribute LC_PROBE820_PID : string;
  attribute LC_PROBE820_PID of U0 : label is "16'b0000001100110100";
  attribute LC_PROBE820_TYPE : integer;
  attribute LC_PROBE820_TYPE of U0 : label is 1;
  attribute LC_PROBE820_WIDTH : integer;
  attribute LC_PROBE820_WIDTH of U0 : label is 1;
  attribute LC_PROBE821_IS_DATA : string;
  attribute LC_PROBE821_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE821_IS_TRIG : string;
  attribute LC_PROBE821_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE821_MU_CNT : integer;
  attribute LC_PROBE821_MU_CNT of U0 : label is 1;
  attribute LC_PROBE821_PID : string;
  attribute LC_PROBE821_PID of U0 : label is "16'b0000001100110101";
  attribute LC_PROBE821_TYPE : integer;
  attribute LC_PROBE821_TYPE of U0 : label is 1;
  attribute LC_PROBE821_WIDTH : integer;
  attribute LC_PROBE821_WIDTH of U0 : label is 1;
  attribute LC_PROBE822_IS_DATA : string;
  attribute LC_PROBE822_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE822_IS_TRIG : string;
  attribute LC_PROBE822_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE822_MU_CNT : integer;
  attribute LC_PROBE822_MU_CNT of U0 : label is 1;
  attribute LC_PROBE822_PID : string;
  attribute LC_PROBE822_PID of U0 : label is "16'b0000001100110110";
  attribute LC_PROBE822_TYPE : integer;
  attribute LC_PROBE822_TYPE of U0 : label is 1;
  attribute LC_PROBE822_WIDTH : integer;
  attribute LC_PROBE822_WIDTH of U0 : label is 1;
  attribute LC_PROBE823_IS_DATA : string;
  attribute LC_PROBE823_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE823_IS_TRIG : string;
  attribute LC_PROBE823_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE823_MU_CNT : integer;
  attribute LC_PROBE823_MU_CNT of U0 : label is 1;
  attribute LC_PROBE823_PID : string;
  attribute LC_PROBE823_PID of U0 : label is "16'b0000001100110111";
  attribute LC_PROBE823_TYPE : integer;
  attribute LC_PROBE823_TYPE of U0 : label is 1;
  attribute LC_PROBE823_WIDTH : integer;
  attribute LC_PROBE823_WIDTH of U0 : label is 1;
  attribute LC_PROBE824_IS_DATA : string;
  attribute LC_PROBE824_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE824_IS_TRIG : string;
  attribute LC_PROBE824_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE824_MU_CNT : integer;
  attribute LC_PROBE824_MU_CNT of U0 : label is 1;
  attribute LC_PROBE824_PID : string;
  attribute LC_PROBE824_PID of U0 : label is "16'b0000001100111000";
  attribute LC_PROBE824_TYPE : integer;
  attribute LC_PROBE824_TYPE of U0 : label is 1;
  attribute LC_PROBE824_WIDTH : integer;
  attribute LC_PROBE824_WIDTH of U0 : label is 1;
  attribute LC_PROBE825_IS_DATA : string;
  attribute LC_PROBE825_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE825_IS_TRIG : string;
  attribute LC_PROBE825_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE825_MU_CNT : integer;
  attribute LC_PROBE825_MU_CNT of U0 : label is 1;
  attribute LC_PROBE825_PID : string;
  attribute LC_PROBE825_PID of U0 : label is "16'b0000001100111001";
  attribute LC_PROBE825_TYPE : integer;
  attribute LC_PROBE825_TYPE of U0 : label is 1;
  attribute LC_PROBE825_WIDTH : integer;
  attribute LC_PROBE825_WIDTH of U0 : label is 1;
  attribute LC_PROBE826_IS_DATA : string;
  attribute LC_PROBE826_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE826_IS_TRIG : string;
  attribute LC_PROBE826_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE826_MU_CNT : integer;
  attribute LC_PROBE826_MU_CNT of U0 : label is 1;
  attribute LC_PROBE826_PID : string;
  attribute LC_PROBE826_PID of U0 : label is "16'b0000001100111010";
  attribute LC_PROBE826_TYPE : integer;
  attribute LC_PROBE826_TYPE of U0 : label is 1;
  attribute LC_PROBE826_WIDTH : integer;
  attribute LC_PROBE826_WIDTH of U0 : label is 1;
  attribute LC_PROBE827_IS_DATA : string;
  attribute LC_PROBE827_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE827_IS_TRIG : string;
  attribute LC_PROBE827_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE827_MU_CNT : integer;
  attribute LC_PROBE827_MU_CNT of U0 : label is 1;
  attribute LC_PROBE827_PID : string;
  attribute LC_PROBE827_PID of U0 : label is "16'b0000001100111011";
  attribute LC_PROBE827_TYPE : integer;
  attribute LC_PROBE827_TYPE of U0 : label is 1;
  attribute LC_PROBE827_WIDTH : integer;
  attribute LC_PROBE827_WIDTH of U0 : label is 1;
  attribute LC_PROBE828_IS_DATA : string;
  attribute LC_PROBE828_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE828_IS_TRIG : string;
  attribute LC_PROBE828_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE828_MU_CNT : integer;
  attribute LC_PROBE828_MU_CNT of U0 : label is 1;
  attribute LC_PROBE828_PID : string;
  attribute LC_PROBE828_PID of U0 : label is "16'b0000001100111100";
  attribute LC_PROBE828_TYPE : integer;
  attribute LC_PROBE828_TYPE of U0 : label is 1;
  attribute LC_PROBE828_WIDTH : integer;
  attribute LC_PROBE828_WIDTH of U0 : label is 1;
  attribute LC_PROBE829_IS_DATA : string;
  attribute LC_PROBE829_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE829_IS_TRIG : string;
  attribute LC_PROBE829_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE829_MU_CNT : integer;
  attribute LC_PROBE829_MU_CNT of U0 : label is 1;
  attribute LC_PROBE829_PID : string;
  attribute LC_PROBE829_PID of U0 : label is "16'b0000001100111101";
  attribute LC_PROBE829_TYPE : integer;
  attribute LC_PROBE829_TYPE of U0 : label is 1;
  attribute LC_PROBE829_WIDTH : integer;
  attribute LC_PROBE829_WIDTH of U0 : label is 1;
  attribute LC_PROBE82_IS_DATA : string;
  attribute LC_PROBE82_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE82_IS_TRIG : string;
  attribute LC_PROBE82_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE82_MU_CNT : integer;
  attribute LC_PROBE82_MU_CNT of U0 : label is 1;
  attribute LC_PROBE82_PID : string;
  attribute LC_PROBE82_PID of U0 : label is "16'b0000000001010010";
  attribute LC_PROBE82_TYPE : integer;
  attribute LC_PROBE82_TYPE of U0 : label is 1;
  attribute LC_PROBE82_WIDTH : integer;
  attribute LC_PROBE82_WIDTH of U0 : label is 1;
  attribute LC_PROBE830_IS_DATA : string;
  attribute LC_PROBE830_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE830_IS_TRIG : string;
  attribute LC_PROBE830_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE830_MU_CNT : integer;
  attribute LC_PROBE830_MU_CNT of U0 : label is 1;
  attribute LC_PROBE830_PID : string;
  attribute LC_PROBE830_PID of U0 : label is "16'b0000001100111110";
  attribute LC_PROBE830_TYPE : integer;
  attribute LC_PROBE830_TYPE of U0 : label is 1;
  attribute LC_PROBE830_WIDTH : integer;
  attribute LC_PROBE830_WIDTH of U0 : label is 1;
  attribute LC_PROBE831_IS_DATA : string;
  attribute LC_PROBE831_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE831_IS_TRIG : string;
  attribute LC_PROBE831_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE831_MU_CNT : integer;
  attribute LC_PROBE831_MU_CNT of U0 : label is 1;
  attribute LC_PROBE831_PID : string;
  attribute LC_PROBE831_PID of U0 : label is "16'b0000001100111111";
  attribute LC_PROBE831_TYPE : integer;
  attribute LC_PROBE831_TYPE of U0 : label is 1;
  attribute LC_PROBE831_WIDTH : integer;
  attribute LC_PROBE831_WIDTH of U0 : label is 1;
  attribute LC_PROBE832_IS_DATA : string;
  attribute LC_PROBE832_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE832_IS_TRIG : string;
  attribute LC_PROBE832_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE832_MU_CNT : integer;
  attribute LC_PROBE832_MU_CNT of U0 : label is 1;
  attribute LC_PROBE832_PID : string;
  attribute LC_PROBE832_PID of U0 : label is "16'b0000001101000000";
  attribute LC_PROBE832_TYPE : integer;
  attribute LC_PROBE832_TYPE of U0 : label is 1;
  attribute LC_PROBE832_WIDTH : integer;
  attribute LC_PROBE832_WIDTH of U0 : label is 1;
  attribute LC_PROBE833_IS_DATA : string;
  attribute LC_PROBE833_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE833_IS_TRIG : string;
  attribute LC_PROBE833_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE833_MU_CNT : integer;
  attribute LC_PROBE833_MU_CNT of U0 : label is 1;
  attribute LC_PROBE833_PID : string;
  attribute LC_PROBE833_PID of U0 : label is "16'b0000001101000001";
  attribute LC_PROBE833_TYPE : integer;
  attribute LC_PROBE833_TYPE of U0 : label is 1;
  attribute LC_PROBE833_WIDTH : integer;
  attribute LC_PROBE833_WIDTH of U0 : label is 1;
  attribute LC_PROBE834_IS_DATA : string;
  attribute LC_PROBE834_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE834_IS_TRIG : string;
  attribute LC_PROBE834_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE834_MU_CNT : integer;
  attribute LC_PROBE834_MU_CNT of U0 : label is 1;
  attribute LC_PROBE834_PID : string;
  attribute LC_PROBE834_PID of U0 : label is "16'b0000001101000010";
  attribute LC_PROBE834_TYPE : integer;
  attribute LC_PROBE834_TYPE of U0 : label is 1;
  attribute LC_PROBE834_WIDTH : integer;
  attribute LC_PROBE834_WIDTH of U0 : label is 1;
  attribute LC_PROBE835_IS_DATA : string;
  attribute LC_PROBE835_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE835_IS_TRIG : string;
  attribute LC_PROBE835_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE835_MU_CNT : integer;
  attribute LC_PROBE835_MU_CNT of U0 : label is 1;
  attribute LC_PROBE835_PID : string;
  attribute LC_PROBE835_PID of U0 : label is "16'b0000001101000011";
  attribute LC_PROBE835_TYPE : integer;
  attribute LC_PROBE835_TYPE of U0 : label is 1;
  attribute LC_PROBE835_WIDTH : integer;
  attribute LC_PROBE835_WIDTH of U0 : label is 1;
  attribute LC_PROBE836_IS_DATA : string;
  attribute LC_PROBE836_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE836_IS_TRIG : string;
  attribute LC_PROBE836_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE836_MU_CNT : integer;
  attribute LC_PROBE836_MU_CNT of U0 : label is 1;
  attribute LC_PROBE836_PID : string;
  attribute LC_PROBE836_PID of U0 : label is "16'b0000001101000100";
  attribute LC_PROBE836_TYPE : integer;
  attribute LC_PROBE836_TYPE of U0 : label is 1;
  attribute LC_PROBE836_WIDTH : integer;
  attribute LC_PROBE836_WIDTH of U0 : label is 1;
  attribute LC_PROBE837_IS_DATA : string;
  attribute LC_PROBE837_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE837_IS_TRIG : string;
  attribute LC_PROBE837_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE837_MU_CNT : integer;
  attribute LC_PROBE837_MU_CNT of U0 : label is 1;
  attribute LC_PROBE837_PID : string;
  attribute LC_PROBE837_PID of U0 : label is "16'b0000001101000101";
  attribute LC_PROBE837_TYPE : integer;
  attribute LC_PROBE837_TYPE of U0 : label is 1;
  attribute LC_PROBE837_WIDTH : integer;
  attribute LC_PROBE837_WIDTH of U0 : label is 1;
  attribute LC_PROBE838_IS_DATA : string;
  attribute LC_PROBE838_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE838_IS_TRIG : string;
  attribute LC_PROBE838_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE838_MU_CNT : integer;
  attribute LC_PROBE838_MU_CNT of U0 : label is 1;
  attribute LC_PROBE838_PID : string;
  attribute LC_PROBE838_PID of U0 : label is "16'b0000001101000110";
  attribute LC_PROBE838_TYPE : integer;
  attribute LC_PROBE838_TYPE of U0 : label is 1;
  attribute LC_PROBE838_WIDTH : integer;
  attribute LC_PROBE838_WIDTH of U0 : label is 1;
  attribute LC_PROBE839_IS_DATA : string;
  attribute LC_PROBE839_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE839_IS_TRIG : string;
  attribute LC_PROBE839_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE839_MU_CNT : integer;
  attribute LC_PROBE839_MU_CNT of U0 : label is 1;
  attribute LC_PROBE839_PID : string;
  attribute LC_PROBE839_PID of U0 : label is "16'b0000001101000111";
  attribute LC_PROBE839_TYPE : integer;
  attribute LC_PROBE839_TYPE of U0 : label is 1;
  attribute LC_PROBE839_WIDTH : integer;
  attribute LC_PROBE839_WIDTH of U0 : label is 1;
  attribute LC_PROBE83_IS_DATA : string;
  attribute LC_PROBE83_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE83_IS_TRIG : string;
  attribute LC_PROBE83_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE83_MU_CNT : integer;
  attribute LC_PROBE83_MU_CNT of U0 : label is 1;
  attribute LC_PROBE83_PID : string;
  attribute LC_PROBE83_PID of U0 : label is "16'b0000000001010011";
  attribute LC_PROBE83_TYPE : integer;
  attribute LC_PROBE83_TYPE of U0 : label is 1;
  attribute LC_PROBE83_WIDTH : integer;
  attribute LC_PROBE83_WIDTH of U0 : label is 1;
  attribute LC_PROBE840_IS_DATA : string;
  attribute LC_PROBE840_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE840_IS_TRIG : string;
  attribute LC_PROBE840_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE840_MU_CNT : integer;
  attribute LC_PROBE840_MU_CNT of U0 : label is 1;
  attribute LC_PROBE840_PID : string;
  attribute LC_PROBE840_PID of U0 : label is "16'b0000001101001000";
  attribute LC_PROBE840_TYPE : integer;
  attribute LC_PROBE840_TYPE of U0 : label is 1;
  attribute LC_PROBE840_WIDTH : integer;
  attribute LC_PROBE840_WIDTH of U0 : label is 1;
  attribute LC_PROBE841_IS_DATA : string;
  attribute LC_PROBE841_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE841_IS_TRIG : string;
  attribute LC_PROBE841_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE841_MU_CNT : integer;
  attribute LC_PROBE841_MU_CNT of U0 : label is 1;
  attribute LC_PROBE841_PID : string;
  attribute LC_PROBE841_PID of U0 : label is "16'b0000001101001001";
  attribute LC_PROBE841_TYPE : integer;
  attribute LC_PROBE841_TYPE of U0 : label is 1;
  attribute LC_PROBE841_WIDTH : integer;
  attribute LC_PROBE841_WIDTH of U0 : label is 1;
  attribute LC_PROBE842_IS_DATA : string;
  attribute LC_PROBE842_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE842_IS_TRIG : string;
  attribute LC_PROBE842_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE842_MU_CNT : integer;
  attribute LC_PROBE842_MU_CNT of U0 : label is 1;
  attribute LC_PROBE842_PID : string;
  attribute LC_PROBE842_PID of U0 : label is "16'b0000001101001010";
  attribute LC_PROBE842_TYPE : integer;
  attribute LC_PROBE842_TYPE of U0 : label is 1;
  attribute LC_PROBE842_WIDTH : integer;
  attribute LC_PROBE842_WIDTH of U0 : label is 1;
  attribute LC_PROBE843_IS_DATA : string;
  attribute LC_PROBE843_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE843_IS_TRIG : string;
  attribute LC_PROBE843_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE843_MU_CNT : integer;
  attribute LC_PROBE843_MU_CNT of U0 : label is 1;
  attribute LC_PROBE843_PID : string;
  attribute LC_PROBE843_PID of U0 : label is "16'b0000001101001011";
  attribute LC_PROBE843_TYPE : integer;
  attribute LC_PROBE843_TYPE of U0 : label is 1;
  attribute LC_PROBE843_WIDTH : integer;
  attribute LC_PROBE843_WIDTH of U0 : label is 1;
  attribute LC_PROBE844_IS_DATA : string;
  attribute LC_PROBE844_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE844_IS_TRIG : string;
  attribute LC_PROBE844_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE844_MU_CNT : integer;
  attribute LC_PROBE844_MU_CNT of U0 : label is 1;
  attribute LC_PROBE844_PID : string;
  attribute LC_PROBE844_PID of U0 : label is "16'b0000001101001100";
  attribute LC_PROBE844_TYPE : integer;
  attribute LC_PROBE844_TYPE of U0 : label is 1;
  attribute LC_PROBE844_WIDTH : integer;
  attribute LC_PROBE844_WIDTH of U0 : label is 1;
  attribute LC_PROBE845_IS_DATA : string;
  attribute LC_PROBE845_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE845_IS_TRIG : string;
  attribute LC_PROBE845_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE845_MU_CNT : integer;
  attribute LC_PROBE845_MU_CNT of U0 : label is 1;
  attribute LC_PROBE845_PID : string;
  attribute LC_PROBE845_PID of U0 : label is "16'b0000001101001101";
  attribute LC_PROBE845_TYPE : integer;
  attribute LC_PROBE845_TYPE of U0 : label is 1;
  attribute LC_PROBE845_WIDTH : integer;
  attribute LC_PROBE845_WIDTH of U0 : label is 1;
  attribute LC_PROBE846_IS_DATA : string;
  attribute LC_PROBE846_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE846_IS_TRIG : string;
  attribute LC_PROBE846_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE846_MU_CNT : integer;
  attribute LC_PROBE846_MU_CNT of U0 : label is 1;
  attribute LC_PROBE846_PID : string;
  attribute LC_PROBE846_PID of U0 : label is "16'b0000001101001110";
  attribute LC_PROBE846_TYPE : integer;
  attribute LC_PROBE846_TYPE of U0 : label is 1;
  attribute LC_PROBE846_WIDTH : integer;
  attribute LC_PROBE846_WIDTH of U0 : label is 1;
  attribute LC_PROBE847_IS_DATA : string;
  attribute LC_PROBE847_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE847_IS_TRIG : string;
  attribute LC_PROBE847_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE847_MU_CNT : integer;
  attribute LC_PROBE847_MU_CNT of U0 : label is 1;
  attribute LC_PROBE847_PID : string;
  attribute LC_PROBE847_PID of U0 : label is "16'b0000001101001111";
  attribute LC_PROBE847_TYPE : integer;
  attribute LC_PROBE847_TYPE of U0 : label is 1;
  attribute LC_PROBE847_WIDTH : integer;
  attribute LC_PROBE847_WIDTH of U0 : label is 1;
  attribute LC_PROBE848_IS_DATA : string;
  attribute LC_PROBE848_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE848_IS_TRIG : string;
  attribute LC_PROBE848_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE848_MU_CNT : integer;
  attribute LC_PROBE848_MU_CNT of U0 : label is 1;
  attribute LC_PROBE848_PID : string;
  attribute LC_PROBE848_PID of U0 : label is "16'b0000001101010000";
  attribute LC_PROBE848_TYPE : integer;
  attribute LC_PROBE848_TYPE of U0 : label is 1;
  attribute LC_PROBE848_WIDTH : integer;
  attribute LC_PROBE848_WIDTH of U0 : label is 1;
  attribute LC_PROBE849_IS_DATA : string;
  attribute LC_PROBE849_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE849_IS_TRIG : string;
  attribute LC_PROBE849_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE849_MU_CNT : integer;
  attribute LC_PROBE849_MU_CNT of U0 : label is 1;
  attribute LC_PROBE849_PID : string;
  attribute LC_PROBE849_PID of U0 : label is "16'b0000001101010001";
  attribute LC_PROBE849_TYPE : integer;
  attribute LC_PROBE849_TYPE of U0 : label is 1;
  attribute LC_PROBE849_WIDTH : integer;
  attribute LC_PROBE849_WIDTH of U0 : label is 1;
  attribute LC_PROBE84_IS_DATA : string;
  attribute LC_PROBE84_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE84_IS_TRIG : string;
  attribute LC_PROBE84_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE84_MU_CNT : integer;
  attribute LC_PROBE84_MU_CNT of U0 : label is 1;
  attribute LC_PROBE84_PID : string;
  attribute LC_PROBE84_PID of U0 : label is "16'b0000000001010100";
  attribute LC_PROBE84_TYPE : integer;
  attribute LC_PROBE84_TYPE of U0 : label is 1;
  attribute LC_PROBE84_WIDTH : integer;
  attribute LC_PROBE84_WIDTH of U0 : label is 1;
  attribute LC_PROBE850_IS_DATA : string;
  attribute LC_PROBE850_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE850_IS_TRIG : string;
  attribute LC_PROBE850_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE850_MU_CNT : integer;
  attribute LC_PROBE850_MU_CNT of U0 : label is 1;
  attribute LC_PROBE850_PID : string;
  attribute LC_PROBE850_PID of U0 : label is "16'b0000001101010010";
  attribute LC_PROBE850_TYPE : integer;
  attribute LC_PROBE850_TYPE of U0 : label is 1;
  attribute LC_PROBE850_WIDTH : integer;
  attribute LC_PROBE850_WIDTH of U0 : label is 1;
  attribute LC_PROBE851_IS_DATA : string;
  attribute LC_PROBE851_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE851_IS_TRIG : string;
  attribute LC_PROBE851_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE851_MU_CNT : integer;
  attribute LC_PROBE851_MU_CNT of U0 : label is 1;
  attribute LC_PROBE851_PID : string;
  attribute LC_PROBE851_PID of U0 : label is "16'b0000001101010011";
  attribute LC_PROBE851_TYPE : integer;
  attribute LC_PROBE851_TYPE of U0 : label is 1;
  attribute LC_PROBE851_WIDTH : integer;
  attribute LC_PROBE851_WIDTH of U0 : label is 1;
  attribute LC_PROBE852_IS_DATA : string;
  attribute LC_PROBE852_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE852_IS_TRIG : string;
  attribute LC_PROBE852_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE852_MU_CNT : integer;
  attribute LC_PROBE852_MU_CNT of U0 : label is 1;
  attribute LC_PROBE852_PID : string;
  attribute LC_PROBE852_PID of U0 : label is "16'b0000001101010100";
  attribute LC_PROBE852_TYPE : integer;
  attribute LC_PROBE852_TYPE of U0 : label is 1;
  attribute LC_PROBE852_WIDTH : integer;
  attribute LC_PROBE852_WIDTH of U0 : label is 1;
  attribute LC_PROBE853_IS_DATA : string;
  attribute LC_PROBE853_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE853_IS_TRIG : string;
  attribute LC_PROBE853_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE853_MU_CNT : integer;
  attribute LC_PROBE853_MU_CNT of U0 : label is 1;
  attribute LC_PROBE853_PID : string;
  attribute LC_PROBE853_PID of U0 : label is "16'b0000001101010101";
  attribute LC_PROBE853_TYPE : integer;
  attribute LC_PROBE853_TYPE of U0 : label is 1;
  attribute LC_PROBE853_WIDTH : integer;
  attribute LC_PROBE853_WIDTH of U0 : label is 1;
  attribute LC_PROBE854_IS_DATA : string;
  attribute LC_PROBE854_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE854_IS_TRIG : string;
  attribute LC_PROBE854_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE854_MU_CNT : integer;
  attribute LC_PROBE854_MU_CNT of U0 : label is 1;
  attribute LC_PROBE854_PID : string;
  attribute LC_PROBE854_PID of U0 : label is "16'b0000001101010110";
  attribute LC_PROBE854_TYPE : integer;
  attribute LC_PROBE854_TYPE of U0 : label is 1;
  attribute LC_PROBE854_WIDTH : integer;
  attribute LC_PROBE854_WIDTH of U0 : label is 1;
  attribute LC_PROBE855_IS_DATA : string;
  attribute LC_PROBE855_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE855_IS_TRIG : string;
  attribute LC_PROBE855_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE855_MU_CNT : integer;
  attribute LC_PROBE855_MU_CNT of U0 : label is 1;
  attribute LC_PROBE855_PID : string;
  attribute LC_PROBE855_PID of U0 : label is "16'b0000001101010111";
  attribute LC_PROBE855_TYPE : integer;
  attribute LC_PROBE855_TYPE of U0 : label is 1;
  attribute LC_PROBE855_WIDTH : integer;
  attribute LC_PROBE855_WIDTH of U0 : label is 1;
  attribute LC_PROBE856_IS_DATA : string;
  attribute LC_PROBE856_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE856_IS_TRIG : string;
  attribute LC_PROBE856_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE856_MU_CNT : integer;
  attribute LC_PROBE856_MU_CNT of U0 : label is 1;
  attribute LC_PROBE856_PID : string;
  attribute LC_PROBE856_PID of U0 : label is "16'b0000001101011000";
  attribute LC_PROBE856_TYPE : integer;
  attribute LC_PROBE856_TYPE of U0 : label is 1;
  attribute LC_PROBE856_WIDTH : integer;
  attribute LC_PROBE856_WIDTH of U0 : label is 1;
  attribute LC_PROBE857_IS_DATA : string;
  attribute LC_PROBE857_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE857_IS_TRIG : string;
  attribute LC_PROBE857_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE857_MU_CNT : integer;
  attribute LC_PROBE857_MU_CNT of U0 : label is 1;
  attribute LC_PROBE857_PID : string;
  attribute LC_PROBE857_PID of U0 : label is "16'b0000001101011001";
  attribute LC_PROBE857_TYPE : integer;
  attribute LC_PROBE857_TYPE of U0 : label is 1;
  attribute LC_PROBE857_WIDTH : integer;
  attribute LC_PROBE857_WIDTH of U0 : label is 1;
  attribute LC_PROBE858_IS_DATA : string;
  attribute LC_PROBE858_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE858_IS_TRIG : string;
  attribute LC_PROBE858_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE858_MU_CNT : integer;
  attribute LC_PROBE858_MU_CNT of U0 : label is 1;
  attribute LC_PROBE858_PID : string;
  attribute LC_PROBE858_PID of U0 : label is "16'b0000001101011010";
  attribute LC_PROBE858_TYPE : integer;
  attribute LC_PROBE858_TYPE of U0 : label is 1;
  attribute LC_PROBE858_WIDTH : integer;
  attribute LC_PROBE858_WIDTH of U0 : label is 1;
  attribute LC_PROBE859_IS_DATA : string;
  attribute LC_PROBE859_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE859_IS_TRIG : string;
  attribute LC_PROBE859_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE859_MU_CNT : integer;
  attribute LC_PROBE859_MU_CNT of U0 : label is 1;
  attribute LC_PROBE859_PID : string;
  attribute LC_PROBE859_PID of U0 : label is "16'b0000001101011011";
  attribute LC_PROBE859_TYPE : integer;
  attribute LC_PROBE859_TYPE of U0 : label is 1;
  attribute LC_PROBE859_WIDTH : integer;
  attribute LC_PROBE859_WIDTH of U0 : label is 1;
  attribute LC_PROBE85_IS_DATA : string;
  attribute LC_PROBE85_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE85_IS_TRIG : string;
  attribute LC_PROBE85_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE85_MU_CNT : integer;
  attribute LC_PROBE85_MU_CNT of U0 : label is 1;
  attribute LC_PROBE85_PID : string;
  attribute LC_PROBE85_PID of U0 : label is "16'b0000000001010101";
  attribute LC_PROBE85_TYPE : integer;
  attribute LC_PROBE85_TYPE of U0 : label is 1;
  attribute LC_PROBE85_WIDTH : integer;
  attribute LC_PROBE85_WIDTH of U0 : label is 1;
  attribute LC_PROBE860_IS_DATA : string;
  attribute LC_PROBE860_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE860_IS_TRIG : string;
  attribute LC_PROBE860_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE860_MU_CNT : integer;
  attribute LC_PROBE860_MU_CNT of U0 : label is 1;
  attribute LC_PROBE860_PID : string;
  attribute LC_PROBE860_PID of U0 : label is "16'b0000001101011100";
  attribute LC_PROBE860_TYPE : integer;
  attribute LC_PROBE860_TYPE of U0 : label is 1;
  attribute LC_PROBE860_WIDTH : integer;
  attribute LC_PROBE860_WIDTH of U0 : label is 1;
  attribute LC_PROBE861_IS_DATA : string;
  attribute LC_PROBE861_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE861_IS_TRIG : string;
  attribute LC_PROBE861_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE861_MU_CNT : integer;
  attribute LC_PROBE861_MU_CNT of U0 : label is 1;
  attribute LC_PROBE861_PID : string;
  attribute LC_PROBE861_PID of U0 : label is "16'b0000001101011101";
  attribute LC_PROBE861_TYPE : integer;
  attribute LC_PROBE861_TYPE of U0 : label is 1;
  attribute LC_PROBE861_WIDTH : integer;
  attribute LC_PROBE861_WIDTH of U0 : label is 1;
  attribute LC_PROBE862_IS_DATA : string;
  attribute LC_PROBE862_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE862_IS_TRIG : string;
  attribute LC_PROBE862_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE862_MU_CNT : integer;
  attribute LC_PROBE862_MU_CNT of U0 : label is 1;
  attribute LC_PROBE862_PID : string;
  attribute LC_PROBE862_PID of U0 : label is "16'b0000001101011110";
  attribute LC_PROBE862_TYPE : integer;
  attribute LC_PROBE862_TYPE of U0 : label is 1;
  attribute LC_PROBE862_WIDTH : integer;
  attribute LC_PROBE862_WIDTH of U0 : label is 1;
  attribute LC_PROBE863_IS_DATA : string;
  attribute LC_PROBE863_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE863_IS_TRIG : string;
  attribute LC_PROBE863_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE863_MU_CNT : integer;
  attribute LC_PROBE863_MU_CNT of U0 : label is 1;
  attribute LC_PROBE863_PID : string;
  attribute LC_PROBE863_PID of U0 : label is "16'b0000001101011111";
  attribute LC_PROBE863_TYPE : integer;
  attribute LC_PROBE863_TYPE of U0 : label is 1;
  attribute LC_PROBE863_WIDTH : integer;
  attribute LC_PROBE863_WIDTH of U0 : label is 1;
  attribute LC_PROBE864_IS_DATA : string;
  attribute LC_PROBE864_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE864_IS_TRIG : string;
  attribute LC_PROBE864_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE864_MU_CNT : integer;
  attribute LC_PROBE864_MU_CNT of U0 : label is 1;
  attribute LC_PROBE864_PID : string;
  attribute LC_PROBE864_PID of U0 : label is "16'b0000001101100000";
  attribute LC_PROBE864_TYPE : integer;
  attribute LC_PROBE864_TYPE of U0 : label is 1;
  attribute LC_PROBE864_WIDTH : integer;
  attribute LC_PROBE864_WIDTH of U0 : label is 1;
  attribute LC_PROBE865_IS_DATA : string;
  attribute LC_PROBE865_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE865_IS_TRIG : string;
  attribute LC_PROBE865_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE865_MU_CNT : integer;
  attribute LC_PROBE865_MU_CNT of U0 : label is 1;
  attribute LC_PROBE865_PID : string;
  attribute LC_PROBE865_PID of U0 : label is "16'b0000001101100001";
  attribute LC_PROBE865_TYPE : integer;
  attribute LC_PROBE865_TYPE of U0 : label is 1;
  attribute LC_PROBE865_WIDTH : integer;
  attribute LC_PROBE865_WIDTH of U0 : label is 1;
  attribute LC_PROBE866_IS_DATA : string;
  attribute LC_PROBE866_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE866_IS_TRIG : string;
  attribute LC_PROBE866_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE866_MU_CNT : integer;
  attribute LC_PROBE866_MU_CNT of U0 : label is 1;
  attribute LC_PROBE866_PID : string;
  attribute LC_PROBE866_PID of U0 : label is "16'b0000001101100010";
  attribute LC_PROBE866_TYPE : integer;
  attribute LC_PROBE866_TYPE of U0 : label is 1;
  attribute LC_PROBE866_WIDTH : integer;
  attribute LC_PROBE866_WIDTH of U0 : label is 1;
  attribute LC_PROBE867_IS_DATA : string;
  attribute LC_PROBE867_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE867_IS_TRIG : string;
  attribute LC_PROBE867_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE867_MU_CNT : integer;
  attribute LC_PROBE867_MU_CNT of U0 : label is 1;
  attribute LC_PROBE867_PID : string;
  attribute LC_PROBE867_PID of U0 : label is "16'b0000001101100011";
  attribute LC_PROBE867_TYPE : integer;
  attribute LC_PROBE867_TYPE of U0 : label is 1;
  attribute LC_PROBE867_WIDTH : integer;
  attribute LC_PROBE867_WIDTH of U0 : label is 1;
  attribute LC_PROBE868_IS_DATA : string;
  attribute LC_PROBE868_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE868_IS_TRIG : string;
  attribute LC_PROBE868_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE868_MU_CNT : integer;
  attribute LC_PROBE868_MU_CNT of U0 : label is 1;
  attribute LC_PROBE868_PID : string;
  attribute LC_PROBE868_PID of U0 : label is "16'b0000001101100100";
  attribute LC_PROBE868_TYPE : integer;
  attribute LC_PROBE868_TYPE of U0 : label is 1;
  attribute LC_PROBE868_WIDTH : integer;
  attribute LC_PROBE868_WIDTH of U0 : label is 1;
  attribute LC_PROBE869_IS_DATA : string;
  attribute LC_PROBE869_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE869_IS_TRIG : string;
  attribute LC_PROBE869_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE869_MU_CNT : integer;
  attribute LC_PROBE869_MU_CNT of U0 : label is 1;
  attribute LC_PROBE869_PID : string;
  attribute LC_PROBE869_PID of U0 : label is "16'b0000001101100101";
  attribute LC_PROBE869_TYPE : integer;
  attribute LC_PROBE869_TYPE of U0 : label is 1;
  attribute LC_PROBE869_WIDTH : integer;
  attribute LC_PROBE869_WIDTH of U0 : label is 1;
  attribute LC_PROBE86_IS_DATA : string;
  attribute LC_PROBE86_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE86_IS_TRIG : string;
  attribute LC_PROBE86_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE86_MU_CNT : integer;
  attribute LC_PROBE86_MU_CNT of U0 : label is 1;
  attribute LC_PROBE86_PID : string;
  attribute LC_PROBE86_PID of U0 : label is "16'b0000000001010110";
  attribute LC_PROBE86_TYPE : integer;
  attribute LC_PROBE86_TYPE of U0 : label is 1;
  attribute LC_PROBE86_WIDTH : integer;
  attribute LC_PROBE86_WIDTH of U0 : label is 1;
  attribute LC_PROBE870_IS_DATA : string;
  attribute LC_PROBE870_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE870_IS_TRIG : string;
  attribute LC_PROBE870_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE870_MU_CNT : integer;
  attribute LC_PROBE870_MU_CNT of U0 : label is 1;
  attribute LC_PROBE870_PID : string;
  attribute LC_PROBE870_PID of U0 : label is "16'b0000001101100110";
  attribute LC_PROBE870_TYPE : integer;
  attribute LC_PROBE870_TYPE of U0 : label is 1;
  attribute LC_PROBE870_WIDTH : integer;
  attribute LC_PROBE870_WIDTH of U0 : label is 1;
  attribute LC_PROBE871_IS_DATA : string;
  attribute LC_PROBE871_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE871_IS_TRIG : string;
  attribute LC_PROBE871_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE871_MU_CNT : integer;
  attribute LC_PROBE871_MU_CNT of U0 : label is 1;
  attribute LC_PROBE871_PID : string;
  attribute LC_PROBE871_PID of U0 : label is "16'b0000001101100111";
  attribute LC_PROBE871_TYPE : integer;
  attribute LC_PROBE871_TYPE of U0 : label is 1;
  attribute LC_PROBE871_WIDTH : integer;
  attribute LC_PROBE871_WIDTH of U0 : label is 1;
  attribute LC_PROBE872_IS_DATA : string;
  attribute LC_PROBE872_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE872_IS_TRIG : string;
  attribute LC_PROBE872_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE872_MU_CNT : integer;
  attribute LC_PROBE872_MU_CNT of U0 : label is 1;
  attribute LC_PROBE872_PID : string;
  attribute LC_PROBE872_PID of U0 : label is "16'b0000001101101000";
  attribute LC_PROBE872_TYPE : integer;
  attribute LC_PROBE872_TYPE of U0 : label is 1;
  attribute LC_PROBE872_WIDTH : integer;
  attribute LC_PROBE872_WIDTH of U0 : label is 1;
  attribute LC_PROBE873_IS_DATA : string;
  attribute LC_PROBE873_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE873_IS_TRIG : string;
  attribute LC_PROBE873_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE873_MU_CNT : integer;
  attribute LC_PROBE873_MU_CNT of U0 : label is 1;
  attribute LC_PROBE873_PID : string;
  attribute LC_PROBE873_PID of U0 : label is "16'b0000001101101001";
  attribute LC_PROBE873_TYPE : integer;
  attribute LC_PROBE873_TYPE of U0 : label is 1;
  attribute LC_PROBE873_WIDTH : integer;
  attribute LC_PROBE873_WIDTH of U0 : label is 1;
  attribute LC_PROBE874_IS_DATA : string;
  attribute LC_PROBE874_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE874_IS_TRIG : string;
  attribute LC_PROBE874_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE874_MU_CNT : integer;
  attribute LC_PROBE874_MU_CNT of U0 : label is 1;
  attribute LC_PROBE874_PID : string;
  attribute LC_PROBE874_PID of U0 : label is "16'b0000001101101010";
  attribute LC_PROBE874_TYPE : integer;
  attribute LC_PROBE874_TYPE of U0 : label is 1;
  attribute LC_PROBE874_WIDTH : integer;
  attribute LC_PROBE874_WIDTH of U0 : label is 1;
  attribute LC_PROBE875_IS_DATA : string;
  attribute LC_PROBE875_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE875_IS_TRIG : string;
  attribute LC_PROBE875_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE875_MU_CNT : integer;
  attribute LC_PROBE875_MU_CNT of U0 : label is 1;
  attribute LC_PROBE875_PID : string;
  attribute LC_PROBE875_PID of U0 : label is "16'b0000001101101011";
  attribute LC_PROBE875_TYPE : integer;
  attribute LC_PROBE875_TYPE of U0 : label is 1;
  attribute LC_PROBE875_WIDTH : integer;
  attribute LC_PROBE875_WIDTH of U0 : label is 1;
  attribute LC_PROBE876_IS_DATA : string;
  attribute LC_PROBE876_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE876_IS_TRIG : string;
  attribute LC_PROBE876_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE876_MU_CNT : integer;
  attribute LC_PROBE876_MU_CNT of U0 : label is 1;
  attribute LC_PROBE876_PID : string;
  attribute LC_PROBE876_PID of U0 : label is "16'b0000001101101100";
  attribute LC_PROBE876_TYPE : integer;
  attribute LC_PROBE876_TYPE of U0 : label is 1;
  attribute LC_PROBE876_WIDTH : integer;
  attribute LC_PROBE876_WIDTH of U0 : label is 1;
  attribute LC_PROBE877_IS_DATA : string;
  attribute LC_PROBE877_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE877_IS_TRIG : string;
  attribute LC_PROBE877_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE877_MU_CNT : integer;
  attribute LC_PROBE877_MU_CNT of U0 : label is 1;
  attribute LC_PROBE877_PID : string;
  attribute LC_PROBE877_PID of U0 : label is "16'b0000001101101101";
  attribute LC_PROBE877_TYPE : integer;
  attribute LC_PROBE877_TYPE of U0 : label is 1;
  attribute LC_PROBE877_WIDTH : integer;
  attribute LC_PROBE877_WIDTH of U0 : label is 1;
  attribute LC_PROBE878_IS_DATA : string;
  attribute LC_PROBE878_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE878_IS_TRIG : string;
  attribute LC_PROBE878_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE878_MU_CNT : integer;
  attribute LC_PROBE878_MU_CNT of U0 : label is 1;
  attribute LC_PROBE878_PID : string;
  attribute LC_PROBE878_PID of U0 : label is "16'b0000001101101110";
  attribute LC_PROBE878_TYPE : integer;
  attribute LC_PROBE878_TYPE of U0 : label is 1;
  attribute LC_PROBE878_WIDTH : integer;
  attribute LC_PROBE878_WIDTH of U0 : label is 1;
  attribute LC_PROBE879_IS_DATA : string;
  attribute LC_PROBE879_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE879_IS_TRIG : string;
  attribute LC_PROBE879_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE879_MU_CNT : integer;
  attribute LC_PROBE879_MU_CNT of U0 : label is 1;
  attribute LC_PROBE879_PID : string;
  attribute LC_PROBE879_PID of U0 : label is "16'b0000001101101111";
  attribute LC_PROBE879_TYPE : integer;
  attribute LC_PROBE879_TYPE of U0 : label is 1;
  attribute LC_PROBE879_WIDTH : integer;
  attribute LC_PROBE879_WIDTH of U0 : label is 1;
  attribute LC_PROBE87_IS_DATA : string;
  attribute LC_PROBE87_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE87_IS_TRIG : string;
  attribute LC_PROBE87_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE87_MU_CNT : integer;
  attribute LC_PROBE87_MU_CNT of U0 : label is 1;
  attribute LC_PROBE87_PID : string;
  attribute LC_PROBE87_PID of U0 : label is "16'b0000000001010111";
  attribute LC_PROBE87_TYPE : integer;
  attribute LC_PROBE87_TYPE of U0 : label is 1;
  attribute LC_PROBE87_WIDTH : integer;
  attribute LC_PROBE87_WIDTH of U0 : label is 1;
  attribute LC_PROBE880_IS_DATA : string;
  attribute LC_PROBE880_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE880_IS_TRIG : string;
  attribute LC_PROBE880_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE880_MU_CNT : integer;
  attribute LC_PROBE880_MU_CNT of U0 : label is 1;
  attribute LC_PROBE880_PID : string;
  attribute LC_PROBE880_PID of U0 : label is "16'b0000001101110000";
  attribute LC_PROBE880_TYPE : integer;
  attribute LC_PROBE880_TYPE of U0 : label is 1;
  attribute LC_PROBE880_WIDTH : integer;
  attribute LC_PROBE880_WIDTH of U0 : label is 1;
  attribute LC_PROBE881_IS_DATA : string;
  attribute LC_PROBE881_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE881_IS_TRIG : string;
  attribute LC_PROBE881_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE881_MU_CNT : integer;
  attribute LC_PROBE881_MU_CNT of U0 : label is 1;
  attribute LC_PROBE881_PID : string;
  attribute LC_PROBE881_PID of U0 : label is "16'b0000001101110001";
  attribute LC_PROBE881_TYPE : integer;
  attribute LC_PROBE881_TYPE of U0 : label is 1;
  attribute LC_PROBE881_WIDTH : integer;
  attribute LC_PROBE881_WIDTH of U0 : label is 1;
  attribute LC_PROBE882_IS_DATA : string;
  attribute LC_PROBE882_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE882_IS_TRIG : string;
  attribute LC_PROBE882_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE882_MU_CNT : integer;
  attribute LC_PROBE882_MU_CNT of U0 : label is 1;
  attribute LC_PROBE882_PID : string;
  attribute LC_PROBE882_PID of U0 : label is "16'b0000001101110010";
  attribute LC_PROBE882_TYPE : integer;
  attribute LC_PROBE882_TYPE of U0 : label is 1;
  attribute LC_PROBE882_WIDTH : integer;
  attribute LC_PROBE882_WIDTH of U0 : label is 1;
  attribute LC_PROBE883_IS_DATA : string;
  attribute LC_PROBE883_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE883_IS_TRIG : string;
  attribute LC_PROBE883_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE883_MU_CNT : integer;
  attribute LC_PROBE883_MU_CNT of U0 : label is 1;
  attribute LC_PROBE883_PID : string;
  attribute LC_PROBE883_PID of U0 : label is "16'b0000001101110011";
  attribute LC_PROBE883_TYPE : integer;
  attribute LC_PROBE883_TYPE of U0 : label is 1;
  attribute LC_PROBE883_WIDTH : integer;
  attribute LC_PROBE883_WIDTH of U0 : label is 1;
  attribute LC_PROBE884_IS_DATA : string;
  attribute LC_PROBE884_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE884_IS_TRIG : string;
  attribute LC_PROBE884_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE884_MU_CNT : integer;
  attribute LC_PROBE884_MU_CNT of U0 : label is 1;
  attribute LC_PROBE884_PID : string;
  attribute LC_PROBE884_PID of U0 : label is "16'b0000001101110100";
  attribute LC_PROBE884_TYPE : integer;
  attribute LC_PROBE884_TYPE of U0 : label is 1;
  attribute LC_PROBE884_WIDTH : integer;
  attribute LC_PROBE884_WIDTH of U0 : label is 1;
  attribute LC_PROBE885_IS_DATA : string;
  attribute LC_PROBE885_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE885_IS_TRIG : string;
  attribute LC_PROBE885_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE885_MU_CNT : integer;
  attribute LC_PROBE885_MU_CNT of U0 : label is 1;
  attribute LC_PROBE885_PID : string;
  attribute LC_PROBE885_PID of U0 : label is "16'b0000001101110101";
  attribute LC_PROBE885_TYPE : integer;
  attribute LC_PROBE885_TYPE of U0 : label is 1;
  attribute LC_PROBE885_WIDTH : integer;
  attribute LC_PROBE885_WIDTH of U0 : label is 1;
  attribute LC_PROBE886_IS_DATA : string;
  attribute LC_PROBE886_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE886_IS_TRIG : string;
  attribute LC_PROBE886_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE886_MU_CNT : integer;
  attribute LC_PROBE886_MU_CNT of U0 : label is 1;
  attribute LC_PROBE886_PID : string;
  attribute LC_PROBE886_PID of U0 : label is "16'b0000001101110110";
  attribute LC_PROBE886_TYPE : integer;
  attribute LC_PROBE886_TYPE of U0 : label is 1;
  attribute LC_PROBE886_WIDTH : integer;
  attribute LC_PROBE886_WIDTH of U0 : label is 1;
  attribute LC_PROBE887_IS_DATA : string;
  attribute LC_PROBE887_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE887_IS_TRIG : string;
  attribute LC_PROBE887_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE887_MU_CNT : integer;
  attribute LC_PROBE887_MU_CNT of U0 : label is 1;
  attribute LC_PROBE887_PID : string;
  attribute LC_PROBE887_PID of U0 : label is "16'b0000001101110111";
  attribute LC_PROBE887_TYPE : integer;
  attribute LC_PROBE887_TYPE of U0 : label is 1;
  attribute LC_PROBE887_WIDTH : integer;
  attribute LC_PROBE887_WIDTH of U0 : label is 1;
  attribute LC_PROBE888_IS_DATA : string;
  attribute LC_PROBE888_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE888_IS_TRIG : string;
  attribute LC_PROBE888_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE888_MU_CNT : integer;
  attribute LC_PROBE888_MU_CNT of U0 : label is 1;
  attribute LC_PROBE888_PID : string;
  attribute LC_PROBE888_PID of U0 : label is "16'b0000001101111000";
  attribute LC_PROBE888_TYPE : integer;
  attribute LC_PROBE888_TYPE of U0 : label is 1;
  attribute LC_PROBE888_WIDTH : integer;
  attribute LC_PROBE888_WIDTH of U0 : label is 1;
  attribute LC_PROBE889_IS_DATA : string;
  attribute LC_PROBE889_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE889_IS_TRIG : string;
  attribute LC_PROBE889_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE889_MU_CNT : integer;
  attribute LC_PROBE889_MU_CNT of U0 : label is 1;
  attribute LC_PROBE889_PID : string;
  attribute LC_PROBE889_PID of U0 : label is "16'b0000001101111001";
  attribute LC_PROBE889_TYPE : integer;
  attribute LC_PROBE889_TYPE of U0 : label is 1;
  attribute LC_PROBE889_WIDTH : integer;
  attribute LC_PROBE889_WIDTH of U0 : label is 1;
  attribute LC_PROBE88_IS_DATA : string;
  attribute LC_PROBE88_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE88_IS_TRIG : string;
  attribute LC_PROBE88_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE88_MU_CNT : integer;
  attribute LC_PROBE88_MU_CNT of U0 : label is 1;
  attribute LC_PROBE88_PID : string;
  attribute LC_PROBE88_PID of U0 : label is "16'b0000000001011000";
  attribute LC_PROBE88_TYPE : integer;
  attribute LC_PROBE88_TYPE of U0 : label is 1;
  attribute LC_PROBE88_WIDTH : integer;
  attribute LC_PROBE88_WIDTH of U0 : label is 1;
  attribute LC_PROBE890_IS_DATA : string;
  attribute LC_PROBE890_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE890_IS_TRIG : string;
  attribute LC_PROBE890_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE890_MU_CNT : integer;
  attribute LC_PROBE890_MU_CNT of U0 : label is 1;
  attribute LC_PROBE890_PID : string;
  attribute LC_PROBE890_PID of U0 : label is "16'b0000001101111010";
  attribute LC_PROBE890_TYPE : integer;
  attribute LC_PROBE890_TYPE of U0 : label is 1;
  attribute LC_PROBE890_WIDTH : integer;
  attribute LC_PROBE890_WIDTH of U0 : label is 1;
  attribute LC_PROBE891_IS_DATA : string;
  attribute LC_PROBE891_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE891_IS_TRIG : string;
  attribute LC_PROBE891_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE891_MU_CNT : integer;
  attribute LC_PROBE891_MU_CNT of U0 : label is 1;
  attribute LC_PROBE891_PID : string;
  attribute LC_PROBE891_PID of U0 : label is "16'b0000001101111011";
  attribute LC_PROBE891_TYPE : integer;
  attribute LC_PROBE891_TYPE of U0 : label is 1;
  attribute LC_PROBE891_WIDTH : integer;
  attribute LC_PROBE891_WIDTH of U0 : label is 1;
  attribute LC_PROBE892_IS_DATA : string;
  attribute LC_PROBE892_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE892_IS_TRIG : string;
  attribute LC_PROBE892_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE892_MU_CNT : integer;
  attribute LC_PROBE892_MU_CNT of U0 : label is 1;
  attribute LC_PROBE892_PID : string;
  attribute LC_PROBE892_PID of U0 : label is "16'b0000001101111100";
  attribute LC_PROBE892_TYPE : integer;
  attribute LC_PROBE892_TYPE of U0 : label is 1;
  attribute LC_PROBE892_WIDTH : integer;
  attribute LC_PROBE892_WIDTH of U0 : label is 1;
  attribute LC_PROBE893_IS_DATA : string;
  attribute LC_PROBE893_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE893_IS_TRIG : string;
  attribute LC_PROBE893_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE893_MU_CNT : integer;
  attribute LC_PROBE893_MU_CNT of U0 : label is 1;
  attribute LC_PROBE893_PID : string;
  attribute LC_PROBE893_PID of U0 : label is "16'b0000001101111101";
  attribute LC_PROBE893_TYPE : integer;
  attribute LC_PROBE893_TYPE of U0 : label is 1;
  attribute LC_PROBE893_WIDTH : integer;
  attribute LC_PROBE893_WIDTH of U0 : label is 1;
  attribute LC_PROBE894_IS_DATA : string;
  attribute LC_PROBE894_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE894_IS_TRIG : string;
  attribute LC_PROBE894_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE894_MU_CNT : integer;
  attribute LC_PROBE894_MU_CNT of U0 : label is 1;
  attribute LC_PROBE894_PID : string;
  attribute LC_PROBE894_PID of U0 : label is "16'b0000001101111110";
  attribute LC_PROBE894_TYPE : integer;
  attribute LC_PROBE894_TYPE of U0 : label is 1;
  attribute LC_PROBE894_WIDTH : integer;
  attribute LC_PROBE894_WIDTH of U0 : label is 1;
  attribute LC_PROBE895_IS_DATA : string;
  attribute LC_PROBE895_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE895_IS_TRIG : string;
  attribute LC_PROBE895_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE895_MU_CNT : integer;
  attribute LC_PROBE895_MU_CNT of U0 : label is 1;
  attribute LC_PROBE895_PID : string;
  attribute LC_PROBE895_PID of U0 : label is "16'b0000001101111111";
  attribute LC_PROBE895_TYPE : integer;
  attribute LC_PROBE895_TYPE of U0 : label is 1;
  attribute LC_PROBE895_WIDTH : integer;
  attribute LC_PROBE895_WIDTH of U0 : label is 1;
  attribute LC_PROBE896_IS_DATA : string;
  attribute LC_PROBE896_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE896_IS_TRIG : string;
  attribute LC_PROBE896_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE896_MU_CNT : integer;
  attribute LC_PROBE896_MU_CNT of U0 : label is 1;
  attribute LC_PROBE896_PID : string;
  attribute LC_PROBE896_PID of U0 : label is "16'b0000001110000000";
  attribute LC_PROBE896_TYPE : integer;
  attribute LC_PROBE896_TYPE of U0 : label is 1;
  attribute LC_PROBE896_WIDTH : integer;
  attribute LC_PROBE896_WIDTH of U0 : label is 1;
  attribute LC_PROBE897_IS_DATA : string;
  attribute LC_PROBE897_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE897_IS_TRIG : string;
  attribute LC_PROBE897_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE897_MU_CNT : integer;
  attribute LC_PROBE897_MU_CNT of U0 : label is 1;
  attribute LC_PROBE897_PID : string;
  attribute LC_PROBE897_PID of U0 : label is "16'b0000001110000001";
  attribute LC_PROBE897_TYPE : integer;
  attribute LC_PROBE897_TYPE of U0 : label is 1;
  attribute LC_PROBE897_WIDTH : integer;
  attribute LC_PROBE897_WIDTH of U0 : label is 1;
  attribute LC_PROBE898_IS_DATA : string;
  attribute LC_PROBE898_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE898_IS_TRIG : string;
  attribute LC_PROBE898_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE898_MU_CNT : integer;
  attribute LC_PROBE898_MU_CNT of U0 : label is 1;
  attribute LC_PROBE898_PID : string;
  attribute LC_PROBE898_PID of U0 : label is "16'b0000001110000010";
  attribute LC_PROBE898_TYPE : integer;
  attribute LC_PROBE898_TYPE of U0 : label is 1;
  attribute LC_PROBE898_WIDTH : integer;
  attribute LC_PROBE898_WIDTH of U0 : label is 1;
  attribute LC_PROBE899_IS_DATA : string;
  attribute LC_PROBE899_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE899_IS_TRIG : string;
  attribute LC_PROBE899_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE899_MU_CNT : integer;
  attribute LC_PROBE899_MU_CNT of U0 : label is 1;
  attribute LC_PROBE899_PID : string;
  attribute LC_PROBE899_PID of U0 : label is "16'b0000001110000011";
  attribute LC_PROBE899_TYPE : integer;
  attribute LC_PROBE899_TYPE of U0 : label is 1;
  attribute LC_PROBE899_WIDTH : integer;
  attribute LC_PROBE899_WIDTH of U0 : label is 1;
  attribute LC_PROBE89_IS_DATA : string;
  attribute LC_PROBE89_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE89_IS_TRIG : string;
  attribute LC_PROBE89_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE89_MU_CNT : integer;
  attribute LC_PROBE89_MU_CNT of U0 : label is 1;
  attribute LC_PROBE89_PID : string;
  attribute LC_PROBE89_PID of U0 : label is "16'b0000000001011001";
  attribute LC_PROBE89_TYPE : integer;
  attribute LC_PROBE89_TYPE of U0 : label is 1;
  attribute LC_PROBE89_WIDTH : integer;
  attribute LC_PROBE89_WIDTH of U0 : label is 1;
  attribute LC_PROBE8_IS_DATA : string;
  attribute LC_PROBE8_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE8_IS_TRIG : string;
  attribute LC_PROBE8_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE8_MU_CNT : integer;
  attribute LC_PROBE8_MU_CNT of U0 : label is 1;
  attribute LC_PROBE8_PID : string;
  attribute LC_PROBE8_PID of U0 : label is "16'b0000000000001000";
  attribute LC_PROBE8_TYPE : integer;
  attribute LC_PROBE8_TYPE of U0 : label is 1;
  attribute LC_PROBE8_WIDTH : integer;
  attribute LC_PROBE8_WIDTH of U0 : label is 1;
  attribute LC_PROBE900_IS_DATA : string;
  attribute LC_PROBE900_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE900_IS_TRIG : string;
  attribute LC_PROBE900_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE900_MU_CNT : integer;
  attribute LC_PROBE900_MU_CNT of U0 : label is 1;
  attribute LC_PROBE900_PID : string;
  attribute LC_PROBE900_PID of U0 : label is "16'b0000001110000100";
  attribute LC_PROBE900_TYPE : integer;
  attribute LC_PROBE900_TYPE of U0 : label is 1;
  attribute LC_PROBE900_WIDTH : integer;
  attribute LC_PROBE900_WIDTH of U0 : label is 1;
  attribute LC_PROBE901_IS_DATA : string;
  attribute LC_PROBE901_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE901_IS_TRIG : string;
  attribute LC_PROBE901_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE901_MU_CNT : integer;
  attribute LC_PROBE901_MU_CNT of U0 : label is 1;
  attribute LC_PROBE901_PID : string;
  attribute LC_PROBE901_PID of U0 : label is "16'b0000001110000101";
  attribute LC_PROBE901_TYPE : integer;
  attribute LC_PROBE901_TYPE of U0 : label is 1;
  attribute LC_PROBE901_WIDTH : integer;
  attribute LC_PROBE901_WIDTH of U0 : label is 1;
  attribute LC_PROBE902_IS_DATA : string;
  attribute LC_PROBE902_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE902_IS_TRIG : string;
  attribute LC_PROBE902_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE902_MU_CNT : integer;
  attribute LC_PROBE902_MU_CNT of U0 : label is 1;
  attribute LC_PROBE902_PID : string;
  attribute LC_PROBE902_PID of U0 : label is "16'b0000001110000110";
  attribute LC_PROBE902_TYPE : integer;
  attribute LC_PROBE902_TYPE of U0 : label is 1;
  attribute LC_PROBE902_WIDTH : integer;
  attribute LC_PROBE902_WIDTH of U0 : label is 1;
  attribute LC_PROBE903_IS_DATA : string;
  attribute LC_PROBE903_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE903_IS_TRIG : string;
  attribute LC_PROBE903_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE903_MU_CNT : integer;
  attribute LC_PROBE903_MU_CNT of U0 : label is 1;
  attribute LC_PROBE903_PID : string;
  attribute LC_PROBE903_PID of U0 : label is "16'b0000001110000111";
  attribute LC_PROBE903_TYPE : integer;
  attribute LC_PROBE903_TYPE of U0 : label is 1;
  attribute LC_PROBE903_WIDTH : integer;
  attribute LC_PROBE903_WIDTH of U0 : label is 1;
  attribute LC_PROBE904_IS_DATA : string;
  attribute LC_PROBE904_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE904_IS_TRIG : string;
  attribute LC_PROBE904_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE904_MU_CNT : integer;
  attribute LC_PROBE904_MU_CNT of U0 : label is 1;
  attribute LC_PROBE904_PID : string;
  attribute LC_PROBE904_PID of U0 : label is "16'b0000001110001000";
  attribute LC_PROBE904_TYPE : integer;
  attribute LC_PROBE904_TYPE of U0 : label is 1;
  attribute LC_PROBE904_WIDTH : integer;
  attribute LC_PROBE904_WIDTH of U0 : label is 1;
  attribute LC_PROBE905_IS_DATA : string;
  attribute LC_PROBE905_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE905_IS_TRIG : string;
  attribute LC_PROBE905_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE905_MU_CNT : integer;
  attribute LC_PROBE905_MU_CNT of U0 : label is 1;
  attribute LC_PROBE905_PID : string;
  attribute LC_PROBE905_PID of U0 : label is "16'b0000001110001001";
  attribute LC_PROBE905_TYPE : integer;
  attribute LC_PROBE905_TYPE of U0 : label is 1;
  attribute LC_PROBE905_WIDTH : integer;
  attribute LC_PROBE905_WIDTH of U0 : label is 1;
  attribute LC_PROBE906_IS_DATA : string;
  attribute LC_PROBE906_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE906_IS_TRIG : string;
  attribute LC_PROBE906_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE906_MU_CNT : integer;
  attribute LC_PROBE906_MU_CNT of U0 : label is 1;
  attribute LC_PROBE906_PID : string;
  attribute LC_PROBE906_PID of U0 : label is "16'b0000001110001010";
  attribute LC_PROBE906_TYPE : integer;
  attribute LC_PROBE906_TYPE of U0 : label is 1;
  attribute LC_PROBE906_WIDTH : integer;
  attribute LC_PROBE906_WIDTH of U0 : label is 1;
  attribute LC_PROBE907_IS_DATA : string;
  attribute LC_PROBE907_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE907_IS_TRIG : string;
  attribute LC_PROBE907_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE907_MU_CNT : integer;
  attribute LC_PROBE907_MU_CNT of U0 : label is 1;
  attribute LC_PROBE907_PID : string;
  attribute LC_PROBE907_PID of U0 : label is "16'b0000001110001011";
  attribute LC_PROBE907_TYPE : integer;
  attribute LC_PROBE907_TYPE of U0 : label is 1;
  attribute LC_PROBE907_WIDTH : integer;
  attribute LC_PROBE907_WIDTH of U0 : label is 1;
  attribute LC_PROBE908_IS_DATA : string;
  attribute LC_PROBE908_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE908_IS_TRIG : string;
  attribute LC_PROBE908_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE908_MU_CNT : integer;
  attribute LC_PROBE908_MU_CNT of U0 : label is 1;
  attribute LC_PROBE908_PID : string;
  attribute LC_PROBE908_PID of U0 : label is "16'b0000001110001100";
  attribute LC_PROBE908_TYPE : integer;
  attribute LC_PROBE908_TYPE of U0 : label is 1;
  attribute LC_PROBE908_WIDTH : integer;
  attribute LC_PROBE908_WIDTH of U0 : label is 1;
  attribute LC_PROBE909_IS_DATA : string;
  attribute LC_PROBE909_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE909_IS_TRIG : string;
  attribute LC_PROBE909_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE909_MU_CNT : integer;
  attribute LC_PROBE909_MU_CNT of U0 : label is 1;
  attribute LC_PROBE909_PID : string;
  attribute LC_PROBE909_PID of U0 : label is "16'b0000001110001101";
  attribute LC_PROBE909_TYPE : integer;
  attribute LC_PROBE909_TYPE of U0 : label is 1;
  attribute LC_PROBE909_WIDTH : integer;
  attribute LC_PROBE909_WIDTH of U0 : label is 1;
  attribute LC_PROBE90_IS_DATA : string;
  attribute LC_PROBE90_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE90_IS_TRIG : string;
  attribute LC_PROBE90_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE90_MU_CNT : integer;
  attribute LC_PROBE90_MU_CNT of U0 : label is 1;
  attribute LC_PROBE90_PID : string;
  attribute LC_PROBE90_PID of U0 : label is "16'b0000000001011010";
  attribute LC_PROBE90_TYPE : integer;
  attribute LC_PROBE90_TYPE of U0 : label is 1;
  attribute LC_PROBE90_WIDTH : integer;
  attribute LC_PROBE90_WIDTH of U0 : label is 1;
  attribute LC_PROBE910_IS_DATA : string;
  attribute LC_PROBE910_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE910_IS_TRIG : string;
  attribute LC_PROBE910_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE910_MU_CNT : integer;
  attribute LC_PROBE910_MU_CNT of U0 : label is 1;
  attribute LC_PROBE910_PID : string;
  attribute LC_PROBE910_PID of U0 : label is "16'b0000001110001110";
  attribute LC_PROBE910_TYPE : integer;
  attribute LC_PROBE910_TYPE of U0 : label is 1;
  attribute LC_PROBE910_WIDTH : integer;
  attribute LC_PROBE910_WIDTH of U0 : label is 1;
  attribute LC_PROBE911_IS_DATA : string;
  attribute LC_PROBE911_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE911_IS_TRIG : string;
  attribute LC_PROBE911_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE911_MU_CNT : integer;
  attribute LC_PROBE911_MU_CNT of U0 : label is 1;
  attribute LC_PROBE911_PID : string;
  attribute LC_PROBE911_PID of U0 : label is "16'b0000001110001111";
  attribute LC_PROBE911_TYPE : integer;
  attribute LC_PROBE911_TYPE of U0 : label is 1;
  attribute LC_PROBE911_WIDTH : integer;
  attribute LC_PROBE911_WIDTH of U0 : label is 1;
  attribute LC_PROBE912_IS_DATA : string;
  attribute LC_PROBE912_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE912_IS_TRIG : string;
  attribute LC_PROBE912_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE912_MU_CNT : integer;
  attribute LC_PROBE912_MU_CNT of U0 : label is 1;
  attribute LC_PROBE912_PID : string;
  attribute LC_PROBE912_PID of U0 : label is "16'b0000001110010000";
  attribute LC_PROBE912_TYPE : integer;
  attribute LC_PROBE912_TYPE of U0 : label is 1;
  attribute LC_PROBE912_WIDTH : integer;
  attribute LC_PROBE912_WIDTH of U0 : label is 1;
  attribute LC_PROBE913_IS_DATA : string;
  attribute LC_PROBE913_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE913_IS_TRIG : string;
  attribute LC_PROBE913_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE913_MU_CNT : integer;
  attribute LC_PROBE913_MU_CNT of U0 : label is 1;
  attribute LC_PROBE913_PID : string;
  attribute LC_PROBE913_PID of U0 : label is "16'b0000001110010001";
  attribute LC_PROBE913_TYPE : integer;
  attribute LC_PROBE913_TYPE of U0 : label is 1;
  attribute LC_PROBE913_WIDTH : integer;
  attribute LC_PROBE913_WIDTH of U0 : label is 1;
  attribute LC_PROBE914_IS_DATA : string;
  attribute LC_PROBE914_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE914_IS_TRIG : string;
  attribute LC_PROBE914_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE914_MU_CNT : integer;
  attribute LC_PROBE914_MU_CNT of U0 : label is 1;
  attribute LC_PROBE914_PID : string;
  attribute LC_PROBE914_PID of U0 : label is "16'b0000001110010010";
  attribute LC_PROBE914_TYPE : integer;
  attribute LC_PROBE914_TYPE of U0 : label is 1;
  attribute LC_PROBE914_WIDTH : integer;
  attribute LC_PROBE914_WIDTH of U0 : label is 1;
  attribute LC_PROBE915_IS_DATA : string;
  attribute LC_PROBE915_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE915_IS_TRIG : string;
  attribute LC_PROBE915_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE915_MU_CNT : integer;
  attribute LC_PROBE915_MU_CNT of U0 : label is 1;
  attribute LC_PROBE915_PID : string;
  attribute LC_PROBE915_PID of U0 : label is "16'b0000001110010011";
  attribute LC_PROBE915_TYPE : integer;
  attribute LC_PROBE915_TYPE of U0 : label is 1;
  attribute LC_PROBE915_WIDTH : integer;
  attribute LC_PROBE915_WIDTH of U0 : label is 1;
  attribute LC_PROBE916_IS_DATA : string;
  attribute LC_PROBE916_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE916_IS_TRIG : string;
  attribute LC_PROBE916_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE916_MU_CNT : integer;
  attribute LC_PROBE916_MU_CNT of U0 : label is 1;
  attribute LC_PROBE916_PID : string;
  attribute LC_PROBE916_PID of U0 : label is "16'b0000001110010100";
  attribute LC_PROBE916_TYPE : integer;
  attribute LC_PROBE916_TYPE of U0 : label is 1;
  attribute LC_PROBE916_WIDTH : integer;
  attribute LC_PROBE916_WIDTH of U0 : label is 1;
  attribute LC_PROBE917_IS_DATA : string;
  attribute LC_PROBE917_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE917_IS_TRIG : string;
  attribute LC_PROBE917_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE917_MU_CNT : integer;
  attribute LC_PROBE917_MU_CNT of U0 : label is 1;
  attribute LC_PROBE917_PID : string;
  attribute LC_PROBE917_PID of U0 : label is "16'b0000001110010101";
  attribute LC_PROBE917_TYPE : integer;
  attribute LC_PROBE917_TYPE of U0 : label is 1;
  attribute LC_PROBE917_WIDTH : integer;
  attribute LC_PROBE917_WIDTH of U0 : label is 1;
  attribute LC_PROBE918_IS_DATA : string;
  attribute LC_PROBE918_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE918_IS_TRIG : string;
  attribute LC_PROBE918_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE918_MU_CNT : integer;
  attribute LC_PROBE918_MU_CNT of U0 : label is 1;
  attribute LC_PROBE918_PID : string;
  attribute LC_PROBE918_PID of U0 : label is "16'b0000001110010110";
  attribute LC_PROBE918_TYPE : integer;
  attribute LC_PROBE918_TYPE of U0 : label is 1;
  attribute LC_PROBE918_WIDTH : integer;
  attribute LC_PROBE918_WIDTH of U0 : label is 1;
  attribute LC_PROBE919_IS_DATA : string;
  attribute LC_PROBE919_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE919_IS_TRIG : string;
  attribute LC_PROBE919_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE919_MU_CNT : integer;
  attribute LC_PROBE919_MU_CNT of U0 : label is 1;
  attribute LC_PROBE919_PID : string;
  attribute LC_PROBE919_PID of U0 : label is "16'b0000001110010111";
  attribute LC_PROBE919_TYPE : integer;
  attribute LC_PROBE919_TYPE of U0 : label is 1;
  attribute LC_PROBE919_WIDTH : integer;
  attribute LC_PROBE919_WIDTH of U0 : label is 1;
  attribute LC_PROBE91_IS_DATA : string;
  attribute LC_PROBE91_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE91_IS_TRIG : string;
  attribute LC_PROBE91_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE91_MU_CNT : integer;
  attribute LC_PROBE91_MU_CNT of U0 : label is 1;
  attribute LC_PROBE91_PID : string;
  attribute LC_PROBE91_PID of U0 : label is "16'b0000000001011011";
  attribute LC_PROBE91_TYPE : integer;
  attribute LC_PROBE91_TYPE of U0 : label is 1;
  attribute LC_PROBE91_WIDTH : integer;
  attribute LC_PROBE91_WIDTH of U0 : label is 1;
  attribute LC_PROBE920_IS_DATA : string;
  attribute LC_PROBE920_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE920_IS_TRIG : string;
  attribute LC_PROBE920_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE920_MU_CNT : integer;
  attribute LC_PROBE920_MU_CNT of U0 : label is 1;
  attribute LC_PROBE920_PID : string;
  attribute LC_PROBE920_PID of U0 : label is "16'b0000001110011000";
  attribute LC_PROBE920_TYPE : integer;
  attribute LC_PROBE920_TYPE of U0 : label is 1;
  attribute LC_PROBE920_WIDTH : integer;
  attribute LC_PROBE920_WIDTH of U0 : label is 1;
  attribute LC_PROBE921_IS_DATA : string;
  attribute LC_PROBE921_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE921_IS_TRIG : string;
  attribute LC_PROBE921_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE921_MU_CNT : integer;
  attribute LC_PROBE921_MU_CNT of U0 : label is 1;
  attribute LC_PROBE921_PID : string;
  attribute LC_PROBE921_PID of U0 : label is "16'b0000001110011001";
  attribute LC_PROBE921_TYPE : integer;
  attribute LC_PROBE921_TYPE of U0 : label is 1;
  attribute LC_PROBE921_WIDTH : integer;
  attribute LC_PROBE921_WIDTH of U0 : label is 1;
  attribute LC_PROBE922_IS_DATA : string;
  attribute LC_PROBE922_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE922_IS_TRIG : string;
  attribute LC_PROBE922_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE922_MU_CNT : integer;
  attribute LC_PROBE922_MU_CNT of U0 : label is 1;
  attribute LC_PROBE922_PID : string;
  attribute LC_PROBE922_PID of U0 : label is "16'b0000001110011010";
  attribute LC_PROBE922_TYPE : integer;
  attribute LC_PROBE922_TYPE of U0 : label is 1;
  attribute LC_PROBE922_WIDTH : integer;
  attribute LC_PROBE922_WIDTH of U0 : label is 1;
  attribute LC_PROBE923_IS_DATA : string;
  attribute LC_PROBE923_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE923_IS_TRIG : string;
  attribute LC_PROBE923_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE923_MU_CNT : integer;
  attribute LC_PROBE923_MU_CNT of U0 : label is 1;
  attribute LC_PROBE923_PID : string;
  attribute LC_PROBE923_PID of U0 : label is "16'b0000001110011011";
  attribute LC_PROBE923_TYPE : integer;
  attribute LC_PROBE923_TYPE of U0 : label is 1;
  attribute LC_PROBE923_WIDTH : integer;
  attribute LC_PROBE923_WIDTH of U0 : label is 1;
  attribute LC_PROBE924_IS_DATA : string;
  attribute LC_PROBE924_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE924_IS_TRIG : string;
  attribute LC_PROBE924_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE924_MU_CNT : integer;
  attribute LC_PROBE924_MU_CNT of U0 : label is 1;
  attribute LC_PROBE924_PID : string;
  attribute LC_PROBE924_PID of U0 : label is "16'b0000001110011100";
  attribute LC_PROBE924_TYPE : integer;
  attribute LC_PROBE924_TYPE of U0 : label is 1;
  attribute LC_PROBE924_WIDTH : integer;
  attribute LC_PROBE924_WIDTH of U0 : label is 1;
  attribute LC_PROBE925_IS_DATA : string;
  attribute LC_PROBE925_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE925_IS_TRIG : string;
  attribute LC_PROBE925_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE925_MU_CNT : integer;
  attribute LC_PROBE925_MU_CNT of U0 : label is 1;
  attribute LC_PROBE925_PID : string;
  attribute LC_PROBE925_PID of U0 : label is "16'b0000001110011101";
  attribute LC_PROBE925_TYPE : integer;
  attribute LC_PROBE925_TYPE of U0 : label is 1;
  attribute LC_PROBE925_WIDTH : integer;
  attribute LC_PROBE925_WIDTH of U0 : label is 1;
  attribute LC_PROBE926_IS_DATA : string;
  attribute LC_PROBE926_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE926_IS_TRIG : string;
  attribute LC_PROBE926_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE926_MU_CNT : integer;
  attribute LC_PROBE926_MU_CNT of U0 : label is 1;
  attribute LC_PROBE926_PID : string;
  attribute LC_PROBE926_PID of U0 : label is "16'b0000001110011110";
  attribute LC_PROBE926_TYPE : integer;
  attribute LC_PROBE926_TYPE of U0 : label is 1;
  attribute LC_PROBE926_WIDTH : integer;
  attribute LC_PROBE926_WIDTH of U0 : label is 1;
  attribute LC_PROBE927_IS_DATA : string;
  attribute LC_PROBE927_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE927_IS_TRIG : string;
  attribute LC_PROBE927_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE927_MU_CNT : integer;
  attribute LC_PROBE927_MU_CNT of U0 : label is 1;
  attribute LC_PROBE927_PID : string;
  attribute LC_PROBE927_PID of U0 : label is "16'b0000001110011111";
  attribute LC_PROBE927_TYPE : integer;
  attribute LC_PROBE927_TYPE of U0 : label is 1;
  attribute LC_PROBE927_WIDTH : integer;
  attribute LC_PROBE927_WIDTH of U0 : label is 1;
  attribute LC_PROBE928_IS_DATA : string;
  attribute LC_PROBE928_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE928_IS_TRIG : string;
  attribute LC_PROBE928_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE928_MU_CNT : integer;
  attribute LC_PROBE928_MU_CNT of U0 : label is 1;
  attribute LC_PROBE928_PID : string;
  attribute LC_PROBE928_PID of U0 : label is "16'b0000001110100000";
  attribute LC_PROBE928_TYPE : integer;
  attribute LC_PROBE928_TYPE of U0 : label is 1;
  attribute LC_PROBE928_WIDTH : integer;
  attribute LC_PROBE928_WIDTH of U0 : label is 1;
  attribute LC_PROBE929_IS_DATA : string;
  attribute LC_PROBE929_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE929_IS_TRIG : string;
  attribute LC_PROBE929_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE929_MU_CNT : integer;
  attribute LC_PROBE929_MU_CNT of U0 : label is 1;
  attribute LC_PROBE929_PID : string;
  attribute LC_PROBE929_PID of U0 : label is "16'b0000001110100001";
  attribute LC_PROBE929_TYPE : integer;
  attribute LC_PROBE929_TYPE of U0 : label is 1;
  attribute LC_PROBE929_WIDTH : integer;
  attribute LC_PROBE929_WIDTH of U0 : label is 1;
  attribute LC_PROBE92_IS_DATA : string;
  attribute LC_PROBE92_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE92_IS_TRIG : string;
  attribute LC_PROBE92_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE92_MU_CNT : integer;
  attribute LC_PROBE92_MU_CNT of U0 : label is 1;
  attribute LC_PROBE92_PID : string;
  attribute LC_PROBE92_PID of U0 : label is "16'b0000000001011100";
  attribute LC_PROBE92_TYPE : integer;
  attribute LC_PROBE92_TYPE of U0 : label is 1;
  attribute LC_PROBE92_WIDTH : integer;
  attribute LC_PROBE92_WIDTH of U0 : label is 1;
  attribute LC_PROBE930_IS_DATA : string;
  attribute LC_PROBE930_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE930_IS_TRIG : string;
  attribute LC_PROBE930_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE930_MU_CNT : integer;
  attribute LC_PROBE930_MU_CNT of U0 : label is 1;
  attribute LC_PROBE930_PID : string;
  attribute LC_PROBE930_PID of U0 : label is "16'b0000001110100010";
  attribute LC_PROBE930_TYPE : integer;
  attribute LC_PROBE930_TYPE of U0 : label is 1;
  attribute LC_PROBE930_WIDTH : integer;
  attribute LC_PROBE930_WIDTH of U0 : label is 1;
  attribute LC_PROBE931_IS_DATA : string;
  attribute LC_PROBE931_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE931_IS_TRIG : string;
  attribute LC_PROBE931_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE931_MU_CNT : integer;
  attribute LC_PROBE931_MU_CNT of U0 : label is 1;
  attribute LC_PROBE931_PID : string;
  attribute LC_PROBE931_PID of U0 : label is "16'b0000001110100011";
  attribute LC_PROBE931_TYPE : integer;
  attribute LC_PROBE931_TYPE of U0 : label is 1;
  attribute LC_PROBE931_WIDTH : integer;
  attribute LC_PROBE931_WIDTH of U0 : label is 1;
  attribute LC_PROBE932_IS_DATA : string;
  attribute LC_PROBE932_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE932_IS_TRIG : string;
  attribute LC_PROBE932_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE932_MU_CNT : integer;
  attribute LC_PROBE932_MU_CNT of U0 : label is 1;
  attribute LC_PROBE932_PID : string;
  attribute LC_PROBE932_PID of U0 : label is "16'b0000001110100100";
  attribute LC_PROBE932_TYPE : integer;
  attribute LC_PROBE932_TYPE of U0 : label is 1;
  attribute LC_PROBE932_WIDTH : integer;
  attribute LC_PROBE932_WIDTH of U0 : label is 1;
  attribute LC_PROBE933_IS_DATA : string;
  attribute LC_PROBE933_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE933_IS_TRIG : string;
  attribute LC_PROBE933_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE933_MU_CNT : integer;
  attribute LC_PROBE933_MU_CNT of U0 : label is 1;
  attribute LC_PROBE933_PID : string;
  attribute LC_PROBE933_PID of U0 : label is "16'b0000001110100101";
  attribute LC_PROBE933_TYPE : integer;
  attribute LC_PROBE933_TYPE of U0 : label is 1;
  attribute LC_PROBE933_WIDTH : integer;
  attribute LC_PROBE933_WIDTH of U0 : label is 1;
  attribute LC_PROBE934_IS_DATA : string;
  attribute LC_PROBE934_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE934_IS_TRIG : string;
  attribute LC_PROBE934_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE934_MU_CNT : integer;
  attribute LC_PROBE934_MU_CNT of U0 : label is 1;
  attribute LC_PROBE934_PID : string;
  attribute LC_PROBE934_PID of U0 : label is "16'b0000001110100110";
  attribute LC_PROBE934_TYPE : integer;
  attribute LC_PROBE934_TYPE of U0 : label is 1;
  attribute LC_PROBE934_WIDTH : integer;
  attribute LC_PROBE934_WIDTH of U0 : label is 1;
  attribute LC_PROBE935_IS_DATA : string;
  attribute LC_PROBE935_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE935_IS_TRIG : string;
  attribute LC_PROBE935_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE935_MU_CNT : integer;
  attribute LC_PROBE935_MU_CNT of U0 : label is 1;
  attribute LC_PROBE935_PID : string;
  attribute LC_PROBE935_PID of U0 : label is "16'b0000001110100111";
  attribute LC_PROBE935_TYPE : integer;
  attribute LC_PROBE935_TYPE of U0 : label is 1;
  attribute LC_PROBE935_WIDTH : integer;
  attribute LC_PROBE935_WIDTH of U0 : label is 1;
  attribute LC_PROBE936_IS_DATA : string;
  attribute LC_PROBE936_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE936_IS_TRIG : string;
  attribute LC_PROBE936_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE936_MU_CNT : integer;
  attribute LC_PROBE936_MU_CNT of U0 : label is 1;
  attribute LC_PROBE936_PID : string;
  attribute LC_PROBE936_PID of U0 : label is "16'b0000001110101000";
  attribute LC_PROBE936_TYPE : integer;
  attribute LC_PROBE936_TYPE of U0 : label is 1;
  attribute LC_PROBE936_WIDTH : integer;
  attribute LC_PROBE936_WIDTH of U0 : label is 1;
  attribute LC_PROBE937_IS_DATA : string;
  attribute LC_PROBE937_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE937_IS_TRIG : string;
  attribute LC_PROBE937_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE937_MU_CNT : integer;
  attribute LC_PROBE937_MU_CNT of U0 : label is 1;
  attribute LC_PROBE937_PID : string;
  attribute LC_PROBE937_PID of U0 : label is "16'b0000001110101001";
  attribute LC_PROBE937_TYPE : integer;
  attribute LC_PROBE937_TYPE of U0 : label is 1;
  attribute LC_PROBE937_WIDTH : integer;
  attribute LC_PROBE937_WIDTH of U0 : label is 1;
  attribute LC_PROBE938_IS_DATA : string;
  attribute LC_PROBE938_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE938_IS_TRIG : string;
  attribute LC_PROBE938_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE938_MU_CNT : integer;
  attribute LC_PROBE938_MU_CNT of U0 : label is 1;
  attribute LC_PROBE938_PID : string;
  attribute LC_PROBE938_PID of U0 : label is "16'b0000001110101010";
  attribute LC_PROBE938_TYPE : integer;
  attribute LC_PROBE938_TYPE of U0 : label is 1;
  attribute LC_PROBE938_WIDTH : integer;
  attribute LC_PROBE938_WIDTH of U0 : label is 1;
  attribute LC_PROBE939_IS_DATA : string;
  attribute LC_PROBE939_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE939_IS_TRIG : string;
  attribute LC_PROBE939_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE939_MU_CNT : integer;
  attribute LC_PROBE939_MU_CNT of U0 : label is 1;
  attribute LC_PROBE939_PID : string;
  attribute LC_PROBE939_PID of U0 : label is "16'b0000001110101011";
  attribute LC_PROBE939_TYPE : integer;
  attribute LC_PROBE939_TYPE of U0 : label is 1;
  attribute LC_PROBE939_WIDTH : integer;
  attribute LC_PROBE939_WIDTH of U0 : label is 1;
  attribute LC_PROBE93_IS_DATA : string;
  attribute LC_PROBE93_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE93_IS_TRIG : string;
  attribute LC_PROBE93_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE93_MU_CNT : integer;
  attribute LC_PROBE93_MU_CNT of U0 : label is 1;
  attribute LC_PROBE93_PID : string;
  attribute LC_PROBE93_PID of U0 : label is "16'b0000000001011101";
  attribute LC_PROBE93_TYPE : integer;
  attribute LC_PROBE93_TYPE of U0 : label is 1;
  attribute LC_PROBE93_WIDTH : integer;
  attribute LC_PROBE93_WIDTH of U0 : label is 1;
  attribute LC_PROBE940_IS_DATA : string;
  attribute LC_PROBE940_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE940_IS_TRIG : string;
  attribute LC_PROBE940_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE940_MU_CNT : integer;
  attribute LC_PROBE940_MU_CNT of U0 : label is 1;
  attribute LC_PROBE940_PID : string;
  attribute LC_PROBE940_PID of U0 : label is "16'b0000001110101100";
  attribute LC_PROBE940_TYPE : integer;
  attribute LC_PROBE940_TYPE of U0 : label is 1;
  attribute LC_PROBE940_WIDTH : integer;
  attribute LC_PROBE940_WIDTH of U0 : label is 1;
  attribute LC_PROBE941_IS_DATA : string;
  attribute LC_PROBE941_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE941_IS_TRIG : string;
  attribute LC_PROBE941_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE941_MU_CNT : integer;
  attribute LC_PROBE941_MU_CNT of U0 : label is 1;
  attribute LC_PROBE941_PID : string;
  attribute LC_PROBE941_PID of U0 : label is "16'b0000001110101101";
  attribute LC_PROBE941_TYPE : integer;
  attribute LC_PROBE941_TYPE of U0 : label is 1;
  attribute LC_PROBE941_WIDTH : integer;
  attribute LC_PROBE941_WIDTH of U0 : label is 1;
  attribute LC_PROBE942_IS_DATA : string;
  attribute LC_PROBE942_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE942_IS_TRIG : string;
  attribute LC_PROBE942_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE942_MU_CNT : integer;
  attribute LC_PROBE942_MU_CNT of U0 : label is 1;
  attribute LC_PROBE942_PID : string;
  attribute LC_PROBE942_PID of U0 : label is "16'b0000001110101110";
  attribute LC_PROBE942_TYPE : integer;
  attribute LC_PROBE942_TYPE of U0 : label is 1;
  attribute LC_PROBE942_WIDTH : integer;
  attribute LC_PROBE942_WIDTH of U0 : label is 1;
  attribute LC_PROBE943_IS_DATA : string;
  attribute LC_PROBE943_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE943_IS_TRIG : string;
  attribute LC_PROBE943_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE943_MU_CNT : integer;
  attribute LC_PROBE943_MU_CNT of U0 : label is 1;
  attribute LC_PROBE943_PID : string;
  attribute LC_PROBE943_PID of U0 : label is "16'b0000001110101111";
  attribute LC_PROBE943_TYPE : integer;
  attribute LC_PROBE943_TYPE of U0 : label is 1;
  attribute LC_PROBE943_WIDTH : integer;
  attribute LC_PROBE943_WIDTH of U0 : label is 1;
  attribute LC_PROBE944_IS_DATA : string;
  attribute LC_PROBE944_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE944_IS_TRIG : string;
  attribute LC_PROBE944_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE944_MU_CNT : integer;
  attribute LC_PROBE944_MU_CNT of U0 : label is 1;
  attribute LC_PROBE944_PID : string;
  attribute LC_PROBE944_PID of U0 : label is "16'b0000001110110000";
  attribute LC_PROBE944_TYPE : integer;
  attribute LC_PROBE944_TYPE of U0 : label is 1;
  attribute LC_PROBE944_WIDTH : integer;
  attribute LC_PROBE944_WIDTH of U0 : label is 1;
  attribute LC_PROBE945_IS_DATA : string;
  attribute LC_PROBE945_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE945_IS_TRIG : string;
  attribute LC_PROBE945_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE945_MU_CNT : integer;
  attribute LC_PROBE945_MU_CNT of U0 : label is 1;
  attribute LC_PROBE945_PID : string;
  attribute LC_PROBE945_PID of U0 : label is "16'b0000001110110001";
  attribute LC_PROBE945_TYPE : integer;
  attribute LC_PROBE945_TYPE of U0 : label is 1;
  attribute LC_PROBE945_WIDTH : integer;
  attribute LC_PROBE945_WIDTH of U0 : label is 1;
  attribute LC_PROBE946_IS_DATA : string;
  attribute LC_PROBE946_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE946_IS_TRIG : string;
  attribute LC_PROBE946_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE946_MU_CNT : integer;
  attribute LC_PROBE946_MU_CNT of U0 : label is 1;
  attribute LC_PROBE946_PID : string;
  attribute LC_PROBE946_PID of U0 : label is "16'b0000001110110010";
  attribute LC_PROBE946_TYPE : integer;
  attribute LC_PROBE946_TYPE of U0 : label is 1;
  attribute LC_PROBE946_WIDTH : integer;
  attribute LC_PROBE946_WIDTH of U0 : label is 1;
  attribute LC_PROBE947_IS_DATA : string;
  attribute LC_PROBE947_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE947_IS_TRIG : string;
  attribute LC_PROBE947_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE947_MU_CNT : integer;
  attribute LC_PROBE947_MU_CNT of U0 : label is 1;
  attribute LC_PROBE947_PID : string;
  attribute LC_PROBE947_PID of U0 : label is "16'b0000001110110011";
  attribute LC_PROBE947_TYPE : integer;
  attribute LC_PROBE947_TYPE of U0 : label is 1;
  attribute LC_PROBE947_WIDTH : integer;
  attribute LC_PROBE947_WIDTH of U0 : label is 1;
  attribute LC_PROBE948_IS_DATA : string;
  attribute LC_PROBE948_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE948_IS_TRIG : string;
  attribute LC_PROBE948_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE948_MU_CNT : integer;
  attribute LC_PROBE948_MU_CNT of U0 : label is 1;
  attribute LC_PROBE948_PID : string;
  attribute LC_PROBE948_PID of U0 : label is "16'b0000001110110100";
  attribute LC_PROBE948_TYPE : integer;
  attribute LC_PROBE948_TYPE of U0 : label is 1;
  attribute LC_PROBE948_WIDTH : integer;
  attribute LC_PROBE948_WIDTH of U0 : label is 1;
  attribute LC_PROBE949_IS_DATA : string;
  attribute LC_PROBE949_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE949_IS_TRIG : string;
  attribute LC_PROBE949_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE949_MU_CNT : integer;
  attribute LC_PROBE949_MU_CNT of U0 : label is 1;
  attribute LC_PROBE949_PID : string;
  attribute LC_PROBE949_PID of U0 : label is "16'b0000001110110101";
  attribute LC_PROBE949_TYPE : integer;
  attribute LC_PROBE949_TYPE of U0 : label is 1;
  attribute LC_PROBE949_WIDTH : integer;
  attribute LC_PROBE949_WIDTH of U0 : label is 1;
  attribute LC_PROBE94_IS_DATA : string;
  attribute LC_PROBE94_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE94_IS_TRIG : string;
  attribute LC_PROBE94_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE94_MU_CNT : integer;
  attribute LC_PROBE94_MU_CNT of U0 : label is 1;
  attribute LC_PROBE94_PID : string;
  attribute LC_PROBE94_PID of U0 : label is "16'b0000000001011110";
  attribute LC_PROBE94_TYPE : integer;
  attribute LC_PROBE94_TYPE of U0 : label is 1;
  attribute LC_PROBE94_WIDTH : integer;
  attribute LC_PROBE94_WIDTH of U0 : label is 1;
  attribute LC_PROBE950_IS_DATA : string;
  attribute LC_PROBE950_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE950_IS_TRIG : string;
  attribute LC_PROBE950_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE950_MU_CNT : integer;
  attribute LC_PROBE950_MU_CNT of U0 : label is 1;
  attribute LC_PROBE950_PID : string;
  attribute LC_PROBE950_PID of U0 : label is "16'b0000001110110110";
  attribute LC_PROBE950_TYPE : integer;
  attribute LC_PROBE950_TYPE of U0 : label is 1;
  attribute LC_PROBE950_WIDTH : integer;
  attribute LC_PROBE950_WIDTH of U0 : label is 1;
  attribute LC_PROBE951_IS_DATA : string;
  attribute LC_PROBE951_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE951_IS_TRIG : string;
  attribute LC_PROBE951_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE951_MU_CNT : integer;
  attribute LC_PROBE951_MU_CNT of U0 : label is 1;
  attribute LC_PROBE951_PID : string;
  attribute LC_PROBE951_PID of U0 : label is "16'b0000001110110111";
  attribute LC_PROBE951_TYPE : integer;
  attribute LC_PROBE951_TYPE of U0 : label is 1;
  attribute LC_PROBE951_WIDTH : integer;
  attribute LC_PROBE951_WIDTH of U0 : label is 1;
  attribute LC_PROBE952_IS_DATA : string;
  attribute LC_PROBE952_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE952_IS_TRIG : string;
  attribute LC_PROBE952_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE952_MU_CNT : integer;
  attribute LC_PROBE952_MU_CNT of U0 : label is 1;
  attribute LC_PROBE952_PID : string;
  attribute LC_PROBE952_PID of U0 : label is "16'b0000001110111000";
  attribute LC_PROBE952_TYPE : integer;
  attribute LC_PROBE952_TYPE of U0 : label is 1;
  attribute LC_PROBE952_WIDTH : integer;
  attribute LC_PROBE952_WIDTH of U0 : label is 1;
  attribute LC_PROBE953_IS_DATA : string;
  attribute LC_PROBE953_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE953_IS_TRIG : string;
  attribute LC_PROBE953_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE953_MU_CNT : integer;
  attribute LC_PROBE953_MU_CNT of U0 : label is 1;
  attribute LC_PROBE953_PID : string;
  attribute LC_PROBE953_PID of U0 : label is "16'b0000001110111001";
  attribute LC_PROBE953_TYPE : integer;
  attribute LC_PROBE953_TYPE of U0 : label is 1;
  attribute LC_PROBE953_WIDTH : integer;
  attribute LC_PROBE953_WIDTH of U0 : label is 1;
  attribute LC_PROBE954_IS_DATA : string;
  attribute LC_PROBE954_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE954_IS_TRIG : string;
  attribute LC_PROBE954_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE954_MU_CNT : integer;
  attribute LC_PROBE954_MU_CNT of U0 : label is 1;
  attribute LC_PROBE954_PID : string;
  attribute LC_PROBE954_PID of U0 : label is "16'b0000001110111010";
  attribute LC_PROBE954_TYPE : integer;
  attribute LC_PROBE954_TYPE of U0 : label is 1;
  attribute LC_PROBE954_WIDTH : integer;
  attribute LC_PROBE954_WIDTH of U0 : label is 1;
  attribute LC_PROBE955_IS_DATA : string;
  attribute LC_PROBE955_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE955_IS_TRIG : string;
  attribute LC_PROBE955_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE955_MU_CNT : integer;
  attribute LC_PROBE955_MU_CNT of U0 : label is 1;
  attribute LC_PROBE955_PID : string;
  attribute LC_PROBE955_PID of U0 : label is "16'b0000001110111011";
  attribute LC_PROBE955_TYPE : integer;
  attribute LC_PROBE955_TYPE of U0 : label is 1;
  attribute LC_PROBE955_WIDTH : integer;
  attribute LC_PROBE955_WIDTH of U0 : label is 1;
  attribute LC_PROBE956_IS_DATA : string;
  attribute LC_PROBE956_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE956_IS_TRIG : string;
  attribute LC_PROBE956_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE956_MU_CNT : integer;
  attribute LC_PROBE956_MU_CNT of U0 : label is 1;
  attribute LC_PROBE956_PID : string;
  attribute LC_PROBE956_PID of U0 : label is "16'b0000001110111100";
  attribute LC_PROBE956_TYPE : integer;
  attribute LC_PROBE956_TYPE of U0 : label is 1;
  attribute LC_PROBE956_WIDTH : integer;
  attribute LC_PROBE956_WIDTH of U0 : label is 1;
  attribute LC_PROBE957_IS_DATA : string;
  attribute LC_PROBE957_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE957_IS_TRIG : string;
  attribute LC_PROBE957_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE957_MU_CNT : integer;
  attribute LC_PROBE957_MU_CNT of U0 : label is 1;
  attribute LC_PROBE957_PID : string;
  attribute LC_PROBE957_PID of U0 : label is "16'b0000001110111101";
  attribute LC_PROBE957_TYPE : integer;
  attribute LC_PROBE957_TYPE of U0 : label is 1;
  attribute LC_PROBE957_WIDTH : integer;
  attribute LC_PROBE957_WIDTH of U0 : label is 1;
  attribute LC_PROBE958_IS_DATA : string;
  attribute LC_PROBE958_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE958_IS_TRIG : string;
  attribute LC_PROBE958_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE958_MU_CNT : integer;
  attribute LC_PROBE958_MU_CNT of U0 : label is 1;
  attribute LC_PROBE958_PID : string;
  attribute LC_PROBE958_PID of U0 : label is "16'b0000001110111110";
  attribute LC_PROBE958_TYPE : integer;
  attribute LC_PROBE958_TYPE of U0 : label is 1;
  attribute LC_PROBE958_WIDTH : integer;
  attribute LC_PROBE958_WIDTH of U0 : label is 1;
  attribute LC_PROBE959_IS_DATA : string;
  attribute LC_PROBE959_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE959_IS_TRIG : string;
  attribute LC_PROBE959_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE959_MU_CNT : integer;
  attribute LC_PROBE959_MU_CNT of U0 : label is 1;
  attribute LC_PROBE959_PID : string;
  attribute LC_PROBE959_PID of U0 : label is "16'b0000001110111111";
  attribute LC_PROBE959_TYPE : integer;
  attribute LC_PROBE959_TYPE of U0 : label is 1;
  attribute LC_PROBE959_WIDTH : integer;
  attribute LC_PROBE959_WIDTH of U0 : label is 1;
  attribute LC_PROBE95_IS_DATA : string;
  attribute LC_PROBE95_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE95_IS_TRIG : string;
  attribute LC_PROBE95_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE95_MU_CNT : integer;
  attribute LC_PROBE95_MU_CNT of U0 : label is 1;
  attribute LC_PROBE95_PID : string;
  attribute LC_PROBE95_PID of U0 : label is "16'b0000000001011111";
  attribute LC_PROBE95_TYPE : integer;
  attribute LC_PROBE95_TYPE of U0 : label is 1;
  attribute LC_PROBE95_WIDTH : integer;
  attribute LC_PROBE95_WIDTH of U0 : label is 1;
  attribute LC_PROBE960_IS_DATA : string;
  attribute LC_PROBE960_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE960_IS_TRIG : string;
  attribute LC_PROBE960_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE960_MU_CNT : integer;
  attribute LC_PROBE960_MU_CNT of U0 : label is 1;
  attribute LC_PROBE960_PID : string;
  attribute LC_PROBE960_PID of U0 : label is "16'b0000001111000000";
  attribute LC_PROBE960_TYPE : integer;
  attribute LC_PROBE960_TYPE of U0 : label is 1;
  attribute LC_PROBE960_WIDTH : integer;
  attribute LC_PROBE960_WIDTH of U0 : label is 1;
  attribute LC_PROBE961_IS_DATA : string;
  attribute LC_PROBE961_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE961_IS_TRIG : string;
  attribute LC_PROBE961_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE961_MU_CNT : integer;
  attribute LC_PROBE961_MU_CNT of U0 : label is 1;
  attribute LC_PROBE961_PID : string;
  attribute LC_PROBE961_PID of U0 : label is "16'b0000001111000001";
  attribute LC_PROBE961_TYPE : integer;
  attribute LC_PROBE961_TYPE of U0 : label is 1;
  attribute LC_PROBE961_WIDTH : integer;
  attribute LC_PROBE961_WIDTH of U0 : label is 1;
  attribute LC_PROBE962_IS_DATA : string;
  attribute LC_PROBE962_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE962_IS_TRIG : string;
  attribute LC_PROBE962_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE962_MU_CNT : integer;
  attribute LC_PROBE962_MU_CNT of U0 : label is 1;
  attribute LC_PROBE962_PID : string;
  attribute LC_PROBE962_PID of U0 : label is "16'b0000001111000010";
  attribute LC_PROBE962_TYPE : integer;
  attribute LC_PROBE962_TYPE of U0 : label is 1;
  attribute LC_PROBE962_WIDTH : integer;
  attribute LC_PROBE962_WIDTH of U0 : label is 1;
  attribute LC_PROBE963_IS_DATA : string;
  attribute LC_PROBE963_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE963_IS_TRIG : string;
  attribute LC_PROBE963_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE963_MU_CNT : integer;
  attribute LC_PROBE963_MU_CNT of U0 : label is 1;
  attribute LC_PROBE963_PID : string;
  attribute LC_PROBE963_PID of U0 : label is "16'b0000001111000011";
  attribute LC_PROBE963_TYPE : integer;
  attribute LC_PROBE963_TYPE of U0 : label is 1;
  attribute LC_PROBE963_WIDTH : integer;
  attribute LC_PROBE963_WIDTH of U0 : label is 1;
  attribute LC_PROBE964_IS_DATA : string;
  attribute LC_PROBE964_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE964_IS_TRIG : string;
  attribute LC_PROBE964_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE964_MU_CNT : integer;
  attribute LC_PROBE964_MU_CNT of U0 : label is 1;
  attribute LC_PROBE964_PID : string;
  attribute LC_PROBE964_PID of U0 : label is "16'b0000001111000100";
  attribute LC_PROBE964_TYPE : integer;
  attribute LC_PROBE964_TYPE of U0 : label is 1;
  attribute LC_PROBE964_WIDTH : integer;
  attribute LC_PROBE964_WIDTH of U0 : label is 1;
  attribute LC_PROBE965_IS_DATA : string;
  attribute LC_PROBE965_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE965_IS_TRIG : string;
  attribute LC_PROBE965_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE965_MU_CNT : integer;
  attribute LC_PROBE965_MU_CNT of U0 : label is 1;
  attribute LC_PROBE965_PID : string;
  attribute LC_PROBE965_PID of U0 : label is "16'b0000001111000101";
  attribute LC_PROBE965_TYPE : integer;
  attribute LC_PROBE965_TYPE of U0 : label is 1;
  attribute LC_PROBE965_WIDTH : integer;
  attribute LC_PROBE965_WIDTH of U0 : label is 1;
  attribute LC_PROBE966_IS_DATA : string;
  attribute LC_PROBE966_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE966_IS_TRIG : string;
  attribute LC_PROBE966_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE966_MU_CNT : integer;
  attribute LC_PROBE966_MU_CNT of U0 : label is 1;
  attribute LC_PROBE966_PID : string;
  attribute LC_PROBE966_PID of U0 : label is "16'b0000001111000110";
  attribute LC_PROBE966_TYPE : integer;
  attribute LC_PROBE966_TYPE of U0 : label is 1;
  attribute LC_PROBE966_WIDTH : integer;
  attribute LC_PROBE966_WIDTH of U0 : label is 1;
  attribute LC_PROBE967_IS_DATA : string;
  attribute LC_PROBE967_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE967_IS_TRIG : string;
  attribute LC_PROBE967_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE967_MU_CNT : integer;
  attribute LC_PROBE967_MU_CNT of U0 : label is 1;
  attribute LC_PROBE967_PID : string;
  attribute LC_PROBE967_PID of U0 : label is "16'b0000001111000111";
  attribute LC_PROBE967_TYPE : integer;
  attribute LC_PROBE967_TYPE of U0 : label is 1;
  attribute LC_PROBE967_WIDTH : integer;
  attribute LC_PROBE967_WIDTH of U0 : label is 1;
  attribute LC_PROBE968_IS_DATA : string;
  attribute LC_PROBE968_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE968_IS_TRIG : string;
  attribute LC_PROBE968_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE968_MU_CNT : integer;
  attribute LC_PROBE968_MU_CNT of U0 : label is 1;
  attribute LC_PROBE968_PID : string;
  attribute LC_PROBE968_PID of U0 : label is "16'b0000001111001000";
  attribute LC_PROBE968_TYPE : integer;
  attribute LC_PROBE968_TYPE of U0 : label is 1;
  attribute LC_PROBE968_WIDTH : integer;
  attribute LC_PROBE968_WIDTH of U0 : label is 1;
  attribute LC_PROBE969_IS_DATA : string;
  attribute LC_PROBE969_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE969_IS_TRIG : string;
  attribute LC_PROBE969_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE969_MU_CNT : integer;
  attribute LC_PROBE969_MU_CNT of U0 : label is 1;
  attribute LC_PROBE969_PID : string;
  attribute LC_PROBE969_PID of U0 : label is "16'b0000001111001001";
  attribute LC_PROBE969_TYPE : integer;
  attribute LC_PROBE969_TYPE of U0 : label is 1;
  attribute LC_PROBE969_WIDTH : integer;
  attribute LC_PROBE969_WIDTH of U0 : label is 1;
  attribute LC_PROBE96_IS_DATA : string;
  attribute LC_PROBE96_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE96_IS_TRIG : string;
  attribute LC_PROBE96_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE96_MU_CNT : integer;
  attribute LC_PROBE96_MU_CNT of U0 : label is 1;
  attribute LC_PROBE96_PID : string;
  attribute LC_PROBE96_PID of U0 : label is "16'b0000000001100000";
  attribute LC_PROBE96_TYPE : integer;
  attribute LC_PROBE96_TYPE of U0 : label is 1;
  attribute LC_PROBE96_WIDTH : integer;
  attribute LC_PROBE96_WIDTH of U0 : label is 1;
  attribute LC_PROBE970_IS_DATA : string;
  attribute LC_PROBE970_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE970_IS_TRIG : string;
  attribute LC_PROBE970_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE970_MU_CNT : integer;
  attribute LC_PROBE970_MU_CNT of U0 : label is 1;
  attribute LC_PROBE970_PID : string;
  attribute LC_PROBE970_PID of U0 : label is "16'b0000001111001010";
  attribute LC_PROBE970_TYPE : integer;
  attribute LC_PROBE970_TYPE of U0 : label is 1;
  attribute LC_PROBE970_WIDTH : integer;
  attribute LC_PROBE970_WIDTH of U0 : label is 1;
  attribute LC_PROBE971_IS_DATA : string;
  attribute LC_PROBE971_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE971_IS_TRIG : string;
  attribute LC_PROBE971_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE971_MU_CNT : integer;
  attribute LC_PROBE971_MU_CNT of U0 : label is 1;
  attribute LC_PROBE971_PID : string;
  attribute LC_PROBE971_PID of U0 : label is "16'b0000001111001011";
  attribute LC_PROBE971_TYPE : integer;
  attribute LC_PROBE971_TYPE of U0 : label is 1;
  attribute LC_PROBE971_WIDTH : integer;
  attribute LC_PROBE971_WIDTH of U0 : label is 1;
  attribute LC_PROBE972_IS_DATA : string;
  attribute LC_PROBE972_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE972_IS_TRIG : string;
  attribute LC_PROBE972_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE972_MU_CNT : integer;
  attribute LC_PROBE972_MU_CNT of U0 : label is 1;
  attribute LC_PROBE972_PID : string;
  attribute LC_PROBE972_PID of U0 : label is "16'b0000001111001100";
  attribute LC_PROBE972_TYPE : integer;
  attribute LC_PROBE972_TYPE of U0 : label is 1;
  attribute LC_PROBE972_WIDTH : integer;
  attribute LC_PROBE972_WIDTH of U0 : label is 1;
  attribute LC_PROBE973_IS_DATA : string;
  attribute LC_PROBE973_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE973_IS_TRIG : string;
  attribute LC_PROBE973_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE973_MU_CNT : integer;
  attribute LC_PROBE973_MU_CNT of U0 : label is 1;
  attribute LC_PROBE973_PID : string;
  attribute LC_PROBE973_PID of U0 : label is "16'b0000001111001101";
  attribute LC_PROBE973_TYPE : integer;
  attribute LC_PROBE973_TYPE of U0 : label is 1;
  attribute LC_PROBE973_WIDTH : integer;
  attribute LC_PROBE973_WIDTH of U0 : label is 1;
  attribute LC_PROBE974_IS_DATA : string;
  attribute LC_PROBE974_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE974_IS_TRIG : string;
  attribute LC_PROBE974_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE974_MU_CNT : integer;
  attribute LC_PROBE974_MU_CNT of U0 : label is 1;
  attribute LC_PROBE974_PID : string;
  attribute LC_PROBE974_PID of U0 : label is "16'b0000001111001110";
  attribute LC_PROBE974_TYPE : integer;
  attribute LC_PROBE974_TYPE of U0 : label is 1;
  attribute LC_PROBE974_WIDTH : integer;
  attribute LC_PROBE974_WIDTH of U0 : label is 1;
  attribute LC_PROBE975_IS_DATA : string;
  attribute LC_PROBE975_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE975_IS_TRIG : string;
  attribute LC_PROBE975_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE975_MU_CNT : integer;
  attribute LC_PROBE975_MU_CNT of U0 : label is 1;
  attribute LC_PROBE975_PID : string;
  attribute LC_PROBE975_PID of U0 : label is "16'b0000001111001111";
  attribute LC_PROBE975_TYPE : integer;
  attribute LC_PROBE975_TYPE of U0 : label is 1;
  attribute LC_PROBE975_WIDTH : integer;
  attribute LC_PROBE975_WIDTH of U0 : label is 1;
  attribute LC_PROBE976_IS_DATA : string;
  attribute LC_PROBE976_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE976_IS_TRIG : string;
  attribute LC_PROBE976_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE976_MU_CNT : integer;
  attribute LC_PROBE976_MU_CNT of U0 : label is 1;
  attribute LC_PROBE976_PID : string;
  attribute LC_PROBE976_PID of U0 : label is "16'b0000001111010000";
  attribute LC_PROBE976_TYPE : integer;
  attribute LC_PROBE976_TYPE of U0 : label is 1;
  attribute LC_PROBE976_WIDTH : integer;
  attribute LC_PROBE976_WIDTH of U0 : label is 1;
  attribute LC_PROBE977_IS_DATA : string;
  attribute LC_PROBE977_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE977_IS_TRIG : string;
  attribute LC_PROBE977_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE977_MU_CNT : integer;
  attribute LC_PROBE977_MU_CNT of U0 : label is 1;
  attribute LC_PROBE977_PID : string;
  attribute LC_PROBE977_PID of U0 : label is "16'b0000001111010001";
  attribute LC_PROBE977_TYPE : integer;
  attribute LC_PROBE977_TYPE of U0 : label is 1;
  attribute LC_PROBE977_WIDTH : integer;
  attribute LC_PROBE977_WIDTH of U0 : label is 1;
  attribute LC_PROBE978_IS_DATA : string;
  attribute LC_PROBE978_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE978_IS_TRIG : string;
  attribute LC_PROBE978_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE978_MU_CNT : integer;
  attribute LC_PROBE978_MU_CNT of U0 : label is 1;
  attribute LC_PROBE978_PID : string;
  attribute LC_PROBE978_PID of U0 : label is "16'b0000001111010010";
  attribute LC_PROBE978_TYPE : integer;
  attribute LC_PROBE978_TYPE of U0 : label is 1;
  attribute LC_PROBE978_WIDTH : integer;
  attribute LC_PROBE978_WIDTH of U0 : label is 1;
  attribute LC_PROBE979_IS_DATA : string;
  attribute LC_PROBE979_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE979_IS_TRIG : string;
  attribute LC_PROBE979_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE979_MU_CNT : integer;
  attribute LC_PROBE979_MU_CNT of U0 : label is 1;
  attribute LC_PROBE979_PID : string;
  attribute LC_PROBE979_PID of U0 : label is "16'b0000001111010011";
  attribute LC_PROBE979_TYPE : integer;
  attribute LC_PROBE979_TYPE of U0 : label is 1;
  attribute LC_PROBE979_WIDTH : integer;
  attribute LC_PROBE979_WIDTH of U0 : label is 1;
  attribute LC_PROBE97_IS_DATA : string;
  attribute LC_PROBE97_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE97_IS_TRIG : string;
  attribute LC_PROBE97_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE97_MU_CNT : integer;
  attribute LC_PROBE97_MU_CNT of U0 : label is 1;
  attribute LC_PROBE97_PID : string;
  attribute LC_PROBE97_PID of U0 : label is "16'b0000000001100001";
  attribute LC_PROBE97_TYPE : integer;
  attribute LC_PROBE97_TYPE of U0 : label is 1;
  attribute LC_PROBE97_WIDTH : integer;
  attribute LC_PROBE97_WIDTH of U0 : label is 1;
  attribute LC_PROBE980_IS_DATA : string;
  attribute LC_PROBE980_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE980_IS_TRIG : string;
  attribute LC_PROBE980_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE980_MU_CNT : integer;
  attribute LC_PROBE980_MU_CNT of U0 : label is 1;
  attribute LC_PROBE980_PID : string;
  attribute LC_PROBE980_PID of U0 : label is "16'b0000001111010100";
  attribute LC_PROBE980_TYPE : integer;
  attribute LC_PROBE980_TYPE of U0 : label is 1;
  attribute LC_PROBE980_WIDTH : integer;
  attribute LC_PROBE980_WIDTH of U0 : label is 1;
  attribute LC_PROBE981_IS_DATA : string;
  attribute LC_PROBE981_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE981_IS_TRIG : string;
  attribute LC_PROBE981_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE981_MU_CNT : integer;
  attribute LC_PROBE981_MU_CNT of U0 : label is 1;
  attribute LC_PROBE981_PID : string;
  attribute LC_PROBE981_PID of U0 : label is "16'b0000001111010101";
  attribute LC_PROBE981_TYPE : integer;
  attribute LC_PROBE981_TYPE of U0 : label is 1;
  attribute LC_PROBE981_WIDTH : integer;
  attribute LC_PROBE981_WIDTH of U0 : label is 1;
  attribute LC_PROBE982_IS_DATA : string;
  attribute LC_PROBE982_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE982_IS_TRIG : string;
  attribute LC_PROBE982_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE982_MU_CNT : integer;
  attribute LC_PROBE982_MU_CNT of U0 : label is 1;
  attribute LC_PROBE982_PID : string;
  attribute LC_PROBE982_PID of U0 : label is "16'b0000001111010110";
  attribute LC_PROBE982_TYPE : integer;
  attribute LC_PROBE982_TYPE of U0 : label is 1;
  attribute LC_PROBE982_WIDTH : integer;
  attribute LC_PROBE982_WIDTH of U0 : label is 1;
  attribute LC_PROBE983_IS_DATA : string;
  attribute LC_PROBE983_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE983_IS_TRIG : string;
  attribute LC_PROBE983_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE983_MU_CNT : integer;
  attribute LC_PROBE983_MU_CNT of U0 : label is 1;
  attribute LC_PROBE983_PID : string;
  attribute LC_PROBE983_PID of U0 : label is "16'b0000001111010111";
  attribute LC_PROBE983_TYPE : integer;
  attribute LC_PROBE983_TYPE of U0 : label is 1;
  attribute LC_PROBE983_WIDTH : integer;
  attribute LC_PROBE983_WIDTH of U0 : label is 1;
  attribute LC_PROBE984_IS_DATA : string;
  attribute LC_PROBE984_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE984_IS_TRIG : string;
  attribute LC_PROBE984_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE984_MU_CNT : integer;
  attribute LC_PROBE984_MU_CNT of U0 : label is 1;
  attribute LC_PROBE984_PID : string;
  attribute LC_PROBE984_PID of U0 : label is "16'b0000001111011000";
  attribute LC_PROBE984_TYPE : integer;
  attribute LC_PROBE984_TYPE of U0 : label is 1;
  attribute LC_PROBE984_WIDTH : integer;
  attribute LC_PROBE984_WIDTH of U0 : label is 1;
  attribute LC_PROBE985_IS_DATA : string;
  attribute LC_PROBE985_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE985_IS_TRIG : string;
  attribute LC_PROBE985_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE985_MU_CNT : integer;
  attribute LC_PROBE985_MU_CNT of U0 : label is 1;
  attribute LC_PROBE985_PID : string;
  attribute LC_PROBE985_PID of U0 : label is "16'b0000001111011001";
  attribute LC_PROBE985_TYPE : integer;
  attribute LC_PROBE985_TYPE of U0 : label is 1;
  attribute LC_PROBE985_WIDTH : integer;
  attribute LC_PROBE985_WIDTH of U0 : label is 1;
  attribute LC_PROBE986_IS_DATA : string;
  attribute LC_PROBE986_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE986_IS_TRIG : string;
  attribute LC_PROBE986_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE986_MU_CNT : integer;
  attribute LC_PROBE986_MU_CNT of U0 : label is 1;
  attribute LC_PROBE986_PID : string;
  attribute LC_PROBE986_PID of U0 : label is "16'b0000001111011010";
  attribute LC_PROBE986_TYPE : integer;
  attribute LC_PROBE986_TYPE of U0 : label is 1;
  attribute LC_PROBE986_WIDTH : integer;
  attribute LC_PROBE986_WIDTH of U0 : label is 1;
  attribute LC_PROBE987_IS_DATA : string;
  attribute LC_PROBE987_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE987_IS_TRIG : string;
  attribute LC_PROBE987_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE987_MU_CNT : integer;
  attribute LC_PROBE987_MU_CNT of U0 : label is 1;
  attribute LC_PROBE987_PID : string;
  attribute LC_PROBE987_PID of U0 : label is "16'b0000001111011011";
  attribute LC_PROBE987_TYPE : integer;
  attribute LC_PROBE987_TYPE of U0 : label is 1;
  attribute LC_PROBE987_WIDTH : integer;
  attribute LC_PROBE987_WIDTH of U0 : label is 1;
  attribute LC_PROBE988_IS_DATA : string;
  attribute LC_PROBE988_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE988_IS_TRIG : string;
  attribute LC_PROBE988_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE988_MU_CNT : integer;
  attribute LC_PROBE988_MU_CNT of U0 : label is 1;
  attribute LC_PROBE988_PID : string;
  attribute LC_PROBE988_PID of U0 : label is "16'b0000001111011100";
  attribute LC_PROBE988_TYPE : integer;
  attribute LC_PROBE988_TYPE of U0 : label is 1;
  attribute LC_PROBE988_WIDTH : integer;
  attribute LC_PROBE988_WIDTH of U0 : label is 1;
  attribute LC_PROBE989_IS_DATA : string;
  attribute LC_PROBE989_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE989_IS_TRIG : string;
  attribute LC_PROBE989_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE989_MU_CNT : integer;
  attribute LC_PROBE989_MU_CNT of U0 : label is 1;
  attribute LC_PROBE989_PID : string;
  attribute LC_PROBE989_PID of U0 : label is "16'b0000001111011101";
  attribute LC_PROBE989_TYPE : integer;
  attribute LC_PROBE989_TYPE of U0 : label is 1;
  attribute LC_PROBE989_WIDTH : integer;
  attribute LC_PROBE989_WIDTH of U0 : label is 1;
  attribute LC_PROBE98_IS_DATA : string;
  attribute LC_PROBE98_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE98_IS_TRIG : string;
  attribute LC_PROBE98_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE98_MU_CNT : integer;
  attribute LC_PROBE98_MU_CNT of U0 : label is 1;
  attribute LC_PROBE98_PID : string;
  attribute LC_PROBE98_PID of U0 : label is "16'b0000000001100010";
  attribute LC_PROBE98_TYPE : integer;
  attribute LC_PROBE98_TYPE of U0 : label is 1;
  attribute LC_PROBE98_WIDTH : integer;
  attribute LC_PROBE98_WIDTH of U0 : label is 1;
  attribute LC_PROBE990_IS_DATA : string;
  attribute LC_PROBE990_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE990_IS_TRIG : string;
  attribute LC_PROBE990_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE990_MU_CNT : integer;
  attribute LC_PROBE990_MU_CNT of U0 : label is 1;
  attribute LC_PROBE990_PID : string;
  attribute LC_PROBE990_PID of U0 : label is "16'b0000001111011110";
  attribute LC_PROBE990_TYPE : integer;
  attribute LC_PROBE990_TYPE of U0 : label is 1;
  attribute LC_PROBE990_WIDTH : integer;
  attribute LC_PROBE990_WIDTH of U0 : label is 1;
  attribute LC_PROBE991_IS_DATA : string;
  attribute LC_PROBE991_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE991_IS_TRIG : string;
  attribute LC_PROBE991_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE991_MU_CNT : integer;
  attribute LC_PROBE991_MU_CNT of U0 : label is 1;
  attribute LC_PROBE991_PID : string;
  attribute LC_PROBE991_PID of U0 : label is "16'b0000001111011111";
  attribute LC_PROBE991_TYPE : integer;
  attribute LC_PROBE991_TYPE of U0 : label is 1;
  attribute LC_PROBE991_WIDTH : integer;
  attribute LC_PROBE991_WIDTH of U0 : label is 1;
  attribute LC_PROBE992_IS_DATA : string;
  attribute LC_PROBE992_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE992_IS_TRIG : string;
  attribute LC_PROBE992_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE992_MU_CNT : integer;
  attribute LC_PROBE992_MU_CNT of U0 : label is 1;
  attribute LC_PROBE992_PID : string;
  attribute LC_PROBE992_PID of U0 : label is "16'b0000001111100000";
  attribute LC_PROBE992_TYPE : integer;
  attribute LC_PROBE992_TYPE of U0 : label is 1;
  attribute LC_PROBE992_WIDTH : integer;
  attribute LC_PROBE992_WIDTH of U0 : label is 1;
  attribute LC_PROBE993_IS_DATA : string;
  attribute LC_PROBE993_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE993_IS_TRIG : string;
  attribute LC_PROBE993_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE993_MU_CNT : integer;
  attribute LC_PROBE993_MU_CNT of U0 : label is 1;
  attribute LC_PROBE993_PID : string;
  attribute LC_PROBE993_PID of U0 : label is "16'b0000001111100001";
  attribute LC_PROBE993_TYPE : integer;
  attribute LC_PROBE993_TYPE of U0 : label is 1;
  attribute LC_PROBE993_WIDTH : integer;
  attribute LC_PROBE993_WIDTH of U0 : label is 1;
  attribute LC_PROBE994_IS_DATA : string;
  attribute LC_PROBE994_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE994_IS_TRIG : string;
  attribute LC_PROBE994_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE994_MU_CNT : integer;
  attribute LC_PROBE994_MU_CNT of U0 : label is 1;
  attribute LC_PROBE994_PID : string;
  attribute LC_PROBE994_PID of U0 : label is "16'b0000001111100010";
  attribute LC_PROBE994_TYPE : integer;
  attribute LC_PROBE994_TYPE of U0 : label is 1;
  attribute LC_PROBE994_WIDTH : integer;
  attribute LC_PROBE994_WIDTH of U0 : label is 1;
  attribute LC_PROBE995_IS_DATA : string;
  attribute LC_PROBE995_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE995_IS_TRIG : string;
  attribute LC_PROBE995_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE995_MU_CNT : integer;
  attribute LC_PROBE995_MU_CNT of U0 : label is 1;
  attribute LC_PROBE995_PID : string;
  attribute LC_PROBE995_PID of U0 : label is "16'b0000001111100011";
  attribute LC_PROBE995_TYPE : integer;
  attribute LC_PROBE995_TYPE of U0 : label is 1;
  attribute LC_PROBE995_WIDTH : integer;
  attribute LC_PROBE995_WIDTH of U0 : label is 1;
  attribute LC_PROBE996_IS_DATA : string;
  attribute LC_PROBE996_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE996_IS_TRIG : string;
  attribute LC_PROBE996_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE996_MU_CNT : integer;
  attribute LC_PROBE996_MU_CNT of U0 : label is 1;
  attribute LC_PROBE996_PID : string;
  attribute LC_PROBE996_PID of U0 : label is "16'b0000001111100100";
  attribute LC_PROBE996_TYPE : integer;
  attribute LC_PROBE996_TYPE of U0 : label is 1;
  attribute LC_PROBE996_WIDTH : integer;
  attribute LC_PROBE996_WIDTH of U0 : label is 1;
  attribute LC_PROBE997_IS_DATA : string;
  attribute LC_PROBE997_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE997_IS_TRIG : string;
  attribute LC_PROBE997_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE997_MU_CNT : integer;
  attribute LC_PROBE997_MU_CNT of U0 : label is 1;
  attribute LC_PROBE997_PID : string;
  attribute LC_PROBE997_PID of U0 : label is "16'b0000001111100101";
  attribute LC_PROBE997_TYPE : integer;
  attribute LC_PROBE997_TYPE of U0 : label is 1;
  attribute LC_PROBE997_WIDTH : integer;
  attribute LC_PROBE997_WIDTH of U0 : label is 1;
  attribute LC_PROBE998_IS_DATA : string;
  attribute LC_PROBE998_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE998_IS_TRIG : string;
  attribute LC_PROBE998_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE998_MU_CNT : integer;
  attribute LC_PROBE998_MU_CNT of U0 : label is 1;
  attribute LC_PROBE998_PID : string;
  attribute LC_PROBE998_PID of U0 : label is "16'b0000001111100110";
  attribute LC_PROBE998_TYPE : integer;
  attribute LC_PROBE998_TYPE of U0 : label is 1;
  attribute LC_PROBE998_WIDTH : integer;
  attribute LC_PROBE998_WIDTH of U0 : label is 1;
  attribute LC_PROBE999_IS_DATA : string;
  attribute LC_PROBE999_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE999_IS_TRIG : string;
  attribute LC_PROBE999_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE999_MU_CNT : integer;
  attribute LC_PROBE999_MU_CNT of U0 : label is 1;
  attribute LC_PROBE999_PID : string;
  attribute LC_PROBE999_PID of U0 : label is "16'b0000001111100111";
  attribute LC_PROBE999_TYPE : integer;
  attribute LC_PROBE999_TYPE of U0 : label is 1;
  attribute LC_PROBE999_WIDTH : integer;
  attribute LC_PROBE999_WIDTH of U0 : label is 1;
  attribute LC_PROBE99_IS_DATA : string;
  attribute LC_PROBE99_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE99_IS_TRIG : string;
  attribute LC_PROBE99_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE99_MU_CNT : integer;
  attribute LC_PROBE99_MU_CNT of U0 : label is 1;
  attribute LC_PROBE99_PID : string;
  attribute LC_PROBE99_PID of U0 : label is "16'b0000000001100011";
  attribute LC_PROBE99_TYPE : integer;
  attribute LC_PROBE99_TYPE of U0 : label is 1;
  attribute LC_PROBE99_WIDTH : integer;
  attribute LC_PROBE99_WIDTH of U0 : label is 1;
  attribute LC_PROBE9_IS_DATA : string;
  attribute LC_PROBE9_IS_DATA of U0 : label is "1'b0";
  attribute LC_PROBE9_IS_TRIG : string;
  attribute LC_PROBE9_IS_TRIG of U0 : label is "1'b0";
  attribute LC_PROBE9_MU_CNT : integer;
  attribute LC_PROBE9_MU_CNT of U0 : label is 1;
  attribute LC_PROBE9_PID : string;
  attribute LC_PROBE9_PID of U0 : label is "16'b0000000000001001";
  attribute LC_PROBE9_TYPE : integer;
  attribute LC_PROBE9_TYPE of U0 : label is 1;
  attribute LC_PROBE9_WIDTH : integer;
  attribute LC_PROBE9_WIDTH of U0 : label is 1;
  attribute LC_PROBES_WIDTH : integer;
  attribute LC_PROBES_WIDTH of U0 : label is 138;
  attribute LC_PROBE_IS_DATA_STRING : string;
  attribute LC_PROBE_IS_DATA_STRING of U0 : label is "1024'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111";
  attribute LC_PROBE_IS_TRIG_STRING : string;
  attribute LC_PROBE_IS_TRIG_STRING of U0 : label is "4096' ";
  attribute LC_PROBE_WIDTH_STRING : string;
  attribute LC_PROBE_WIDTH_STRING of U0 : label is "16384' ";
  attribute LC_TIME_TAG_MU_CNT : integer;
  attribute LC_TIME_TAG_MU_CNT of U0 : label is 2;
  attribute LC_TIME_TAG_TYPE : integer;
  attribute LC_TIME_TAG_TYPE of U0 : label is 0;
  attribute LC_TIME_TAG_WIDTH : integer;
  attribute LC_TIME_TAG_WIDTH of U0 : label is 1;
  attribute LC_TRIG_WIDTH : integer;
  attribute LC_TRIG_WIDTH of U0 : label is 138;
  attribute syn_noprune : string;
  attribute syn_noprune of U0 : label is "TRUE";
begin
U0: entity work.ila_full_aurora_ila_v6_2_10_ila
     port map (
      clk => clk,
      clk_nobuf => '0',
      clkdiv_out => NLW_U0_clkdiv_out_UNCONNECTED,
      probe0(63 downto 0) => probe0(63 downto 0),
      probe1(0) => probe1(0),
      probe10(0) => '0',
      probe100(0) => '0',
      probe1000(0) => '0',
      probe1001(0) => '0',
      probe1002(0) => '0',
      probe1003(0) => '0',
      probe1004(0) => '0',
      probe1005(0) => '0',
      probe1006(0) => '0',
      probe1007(0) => '0',
      probe1008(0) => '0',
      probe1009(0) => '0',
      probe101(0) => '0',
      probe1010(0) => '0',
      probe1011(0) => '0',
      probe1012(0) => '0',
      probe1013(0) => '0',
      probe1014(0) => '0',
      probe1015(0) => '0',
      probe1016(0) => '0',
      probe1017(0) => '0',
      probe1018(0) => '0',
      probe1019(0) => '0',
      probe102(0) => '0',
      probe1020(0) => '0',
      probe1021(0) => '0',
      probe1022(0) => '0',
      probe1023(0) => '0',
      probe103(0) => '0',
      probe104(0) => '0',
      probe105(0) => '0',
      probe106(0) => '0',
      probe107(0) => '0',
      probe108(0) => '0',
      probe109(0) => '0',
      probe11(0) => '0',
      probe110(0) => '0',
      probe111(0) => '0',
      probe112(0) => '0',
      probe113(0) => '0',
      probe114(0) => '0',
      probe115(0) => '0',
      probe116(0) => '0',
      probe117(0) => '0',
      probe118(0) => '0',
      probe119(0) => '0',
      probe12(0) => '0',
      probe120(0) => '0',
      probe121(0) => '0',
      probe122(0) => '0',
      probe123(0) => '0',
      probe124(0) => '0',
      probe125(0) => '0',
      probe126(0) => '0',
      probe127(0) => '0',
      probe128(0) => '0',
      probe129(0) => '0',
      probe13(0) => '0',
      probe130(0) => '0',
      probe131(0) => '0',
      probe132(0) => '0',
      probe133(0) => '0',
      probe134(0) => '0',
      probe135(0) => '0',
      probe136(0) => '0',
      probe137(0) => '0',
      probe138(0) => '0',
      probe139(0) => '0',
      probe14(0) => '0',
      probe140(0) => '0',
      probe141(0) => '0',
      probe142(0) => '0',
      probe143(0) => '0',
      probe144(0) => '0',
      probe145(0) => '0',
      probe146(0) => '0',
      probe147(0) => '0',
      probe148(0) => '0',
      probe149(0) => '0',
      probe15(0) => '0',
      probe150(0) => '0',
      probe151(0) => '0',
      probe152(0) => '0',
      probe153(0) => '0',
      probe154(0) => '0',
      probe155(0) => '0',
      probe156(0) => '0',
      probe157(0) => '0',
      probe158(0) => '0',
      probe159(0) => '0',
      probe16(0) => '0',
      probe160(0) => '0',
      probe161(0) => '0',
      probe162(0) => '0',
      probe163(0) => '0',
      probe164(0) => '0',
      probe165(0) => '0',
      probe166(0) => '0',
      probe167(0) => '0',
      probe168(0) => '0',
      probe169(0) => '0',
      probe17(0) => '0',
      probe170(0) => '0',
      probe171(0) => '0',
      probe172(0) => '0',
      probe173(0) => '0',
      probe174(0) => '0',
      probe175(0) => '0',
      probe176(0) => '0',
      probe177(0) => '0',
      probe178(0) => '0',
      probe179(0) => '0',
      probe18(0) => '0',
      probe180(0) => '0',
      probe181(0) => '0',
      probe182(0) => '0',
      probe183(0) => '0',
      probe184(0) => '0',
      probe185(0) => '0',
      probe186(0) => '0',
      probe187(0) => '0',
      probe188(0) => '0',
      probe189(0) => '0',
      probe19(0) => '0',
      probe190(0) => '0',
      probe191(0) => '0',
      probe192(0) => '0',
      probe193(0) => '0',
      probe194(0) => '0',
      probe195(0) => '0',
      probe196(0) => '0',
      probe197(0) => '0',
      probe198(0) => '0',
      probe199(0) => '0',
      probe2(0) => probe2(0),
      probe20(0) => '0',
      probe200(0) => '0',
      probe201(0) => '0',
      probe202(0) => '0',
      probe203(0) => '0',
      probe204(0) => '0',
      probe205(0) => '0',
      probe206(0) => '0',
      probe207(0) => '0',
      probe208(0) => '0',
      probe209(0) => '0',
      probe21(0) => '0',
      probe210(0) => '0',
      probe211(0) => '0',
      probe212(0) => '0',
      probe213(0) => '0',
      probe214(0) => '0',
      probe215(0) => '0',
      probe216(0) => '0',
      probe217(0) => '0',
      probe218(0) => '0',
      probe219(0) => '0',
      probe22(0) => '0',
      probe220(0) => '0',
      probe221(0) => '0',
      probe222(0) => '0',
      probe223(0) => '0',
      probe224(0) => '0',
      probe225(0) => '0',
      probe226(0) => '0',
      probe227(0) => '0',
      probe228(0) => '0',
      probe229(0) => '0',
      probe23(0) => '0',
      probe230(0) => '0',
      probe231(0) => '0',
      probe232(0) => '0',
      probe233(0) => '0',
      probe234(0) => '0',
      probe235(0) => '0',
      probe236(0) => '0',
      probe237(0) => '0',
      probe238(0) => '0',
      probe239(0) => '0',
      probe24(0) => '0',
      probe240(0) => '0',
      probe241(0) => '0',
      probe242(0) => '0',
      probe243(0) => '0',
      probe244(0) => '0',
      probe245(0) => '0',
      probe246(0) => '0',
      probe247(0) => '0',
      probe248(0) => '0',
      probe249(0) => '0',
      probe25(0) => '0',
      probe250(0) => '0',
      probe251(0) => '0',
      probe252(0) => '0',
      probe253(0) => '0',
      probe254(0) => '0',
      probe255(0) => '0',
      probe256(0) => '0',
      probe257(0) => '0',
      probe258(0) => '0',
      probe259(0) => '0',
      probe26(0) => '0',
      probe260(0) => '0',
      probe261(0) => '0',
      probe262(0) => '0',
      probe263(0) => '0',
      probe264(0) => '0',
      probe265(0) => '0',
      probe266(0) => '0',
      probe267(0) => '0',
      probe268(0) => '0',
      probe269(0) => '0',
      probe27(0) => '0',
      probe270(0) => '0',
      probe271(0) => '0',
      probe272(0) => '0',
      probe273(0) => '0',
      probe274(0) => '0',
      probe275(0) => '0',
      probe276(0) => '0',
      probe277(0) => '0',
      probe278(0) => '0',
      probe279(0) => '0',
      probe28(0) => '0',
      probe280(0) => '0',
      probe281(0) => '0',
      probe282(0) => '0',
      probe283(0) => '0',
      probe284(0) => '0',
      probe285(0) => '0',
      probe286(0) => '0',
      probe287(0) => '0',
      probe288(0) => '0',
      probe289(0) => '0',
      probe29(0) => '0',
      probe290(0) => '0',
      probe291(0) => '0',
      probe292(0) => '0',
      probe293(0) => '0',
      probe294(0) => '0',
      probe295(0) => '0',
      probe296(0) => '0',
      probe297(0) => '0',
      probe298(0) => '0',
      probe299(0) => '0',
      probe3(7 downto 0) => probe3(7 downto 0),
      probe30(0) => '0',
      probe300(0) => '0',
      probe301(0) => '0',
      probe302(0) => '0',
      probe303(0) => '0',
      probe304(0) => '0',
      probe305(0) => '0',
      probe306(0) => '0',
      probe307(0) => '0',
      probe308(0) => '0',
      probe309(0) => '0',
      probe31(0) => '0',
      probe310(0) => '0',
      probe311(0) => '0',
      probe312(0) => '0',
      probe313(0) => '0',
      probe314(0) => '0',
      probe315(0) => '0',
      probe316(0) => '0',
      probe317(0) => '0',
      probe318(0) => '0',
      probe319(0) => '0',
      probe32(0) => '0',
      probe320(0) => '0',
      probe321(0) => '0',
      probe322(0) => '0',
      probe323(0) => '0',
      probe324(0) => '0',
      probe325(0) => '0',
      probe326(0) => '0',
      probe327(0) => '0',
      probe328(0) => '0',
      probe329(0) => '0',
      probe33(0) => '0',
      probe330(0) => '0',
      probe331(0) => '0',
      probe332(0) => '0',
      probe333(0) => '0',
      probe334(0) => '0',
      probe335(0) => '0',
      probe336(0) => '0',
      probe337(0) => '0',
      probe338(0) => '0',
      probe339(0) => '0',
      probe34(0) => '0',
      probe340(0) => '0',
      probe341(0) => '0',
      probe342(0) => '0',
      probe343(0) => '0',
      probe344(0) => '0',
      probe345(0) => '0',
      probe346(0) => '0',
      probe347(0) => '0',
      probe348(0) => '0',
      probe349(0) => '0',
      probe35(0) => '0',
      probe350(0) => '0',
      probe351(0) => '0',
      probe352(0) => '0',
      probe353(0) => '0',
      probe354(0) => '0',
      probe355(0) => '0',
      probe356(0) => '0',
      probe357(0) => '0',
      probe358(0) => '0',
      probe359(0) => '0',
      probe36(0) => '0',
      probe360(0) => '0',
      probe361(0) => '0',
      probe362(0) => '0',
      probe363(0) => '0',
      probe364(0) => '0',
      probe365(0) => '0',
      probe366(0) => '0',
      probe367(0) => '0',
      probe368(0) => '0',
      probe369(0) => '0',
      probe37(0) => '0',
      probe370(0) => '0',
      probe371(0) => '0',
      probe372(0) => '0',
      probe373(0) => '0',
      probe374(0) => '0',
      probe375(0) => '0',
      probe376(0) => '0',
      probe377(0) => '0',
      probe378(0) => '0',
      probe379(0) => '0',
      probe38(0) => '0',
      probe380(0) => '0',
      probe381(0) => '0',
      probe382(0) => '0',
      probe383(0) => '0',
      probe384(0) => '0',
      probe385(0) => '0',
      probe386(0) => '0',
      probe387(0) => '0',
      probe388(0) => '0',
      probe389(0) => '0',
      probe39(0) => '0',
      probe390(0) => '0',
      probe391(0) => '0',
      probe392(0) => '0',
      probe393(0) => '0',
      probe394(0) => '0',
      probe395(0) => '0',
      probe396(0) => '0',
      probe397(0) => '0',
      probe398(0) => '0',
      probe399(0) => '0',
      probe4(31 downto 0) => probe4(31 downto 0),
      probe40(0) => '0',
      probe400(0) => '0',
      probe401(0) => '0',
      probe402(0) => '0',
      probe403(0) => '0',
      probe404(0) => '0',
      probe405(0) => '0',
      probe406(0) => '0',
      probe407(0) => '0',
      probe408(0) => '0',
      probe409(0) => '0',
      probe41(0) => '0',
      probe410(0) => '0',
      probe411(0) => '0',
      probe412(0) => '0',
      probe413(0) => '0',
      probe414(0) => '0',
      probe415(0) => '0',
      probe416(0) => '0',
      probe417(0) => '0',
      probe418(0) => '0',
      probe419(0) => '0',
      probe42(0) => '0',
      probe420(0) => '0',
      probe421(0) => '0',
      probe422(0) => '0',
      probe423(0) => '0',
      probe424(0) => '0',
      probe425(0) => '0',
      probe426(0) => '0',
      probe427(0) => '0',
      probe428(0) => '0',
      probe429(0) => '0',
      probe43(0) => '0',
      probe430(0) => '0',
      probe431(0) => '0',
      probe432(0) => '0',
      probe433(0) => '0',
      probe434(0) => '0',
      probe435(0) => '0',
      probe436(0) => '0',
      probe437(0) => '0',
      probe438(0) => '0',
      probe439(0) => '0',
      probe44(0) => '0',
      probe440(0) => '0',
      probe441(0) => '0',
      probe442(0) => '0',
      probe443(0) => '0',
      probe444(0) => '0',
      probe445(0) => '0',
      probe446(0) => '0',
      probe447(0) => '0',
      probe448(0) => '0',
      probe449(0) => '0',
      probe45(0) => '0',
      probe450(0) => '0',
      probe451(0) => '0',
      probe452(0) => '0',
      probe453(0) => '0',
      probe454(0) => '0',
      probe455(0) => '0',
      probe456(0) => '0',
      probe457(0) => '0',
      probe458(0) => '0',
      probe459(0) => '0',
      probe46(0) => '0',
      probe460(0) => '0',
      probe461(0) => '0',
      probe462(0) => '0',
      probe463(0) => '0',
      probe464(0) => '0',
      probe465(0) => '0',
      probe466(0) => '0',
      probe467(0) => '0',
      probe468(0) => '0',
      probe469(0) => '0',
      probe47(0) => '0',
      probe470(0) => '0',
      probe471(0) => '0',
      probe472(0) => '0',
      probe473(0) => '0',
      probe474(0) => '0',
      probe475(0) => '0',
      probe476(0) => '0',
      probe477(0) => '0',
      probe478(0) => '0',
      probe479(0) => '0',
      probe48(0) => '0',
      probe480(0) => '0',
      probe481(0) => '0',
      probe482(0) => '0',
      probe483(0) => '0',
      probe484(0) => '0',
      probe485(0) => '0',
      probe486(0) => '0',
      probe487(0) => '0',
      probe488(0) => '0',
      probe489(0) => '0',
      probe49(0) => '0',
      probe490(0) => '0',
      probe491(0) => '0',
      probe492(0) => '0',
      probe493(0) => '0',
      probe494(0) => '0',
      probe495(0) => '0',
      probe496(0) => '0',
      probe497(0) => '0',
      probe498(0) => '0',
      probe499(0) => '0',
      probe5(31 downto 0) => probe5(31 downto 0),
      probe50(0) => '0',
      probe500(0) => '0',
      probe501(0) => '0',
      probe502(0) => '0',
      probe503(0) => '0',
      probe504(0) => '0',
      probe505(0) => '0',
      probe506(0) => '0',
      probe507(0) => '0',
      probe508(0) => '0',
      probe509(0) => '0',
      probe51(0) => '0',
      probe510(0) => '0',
      probe511(0) => '0',
      probe512(0) => '0',
      probe513(0) => '0',
      probe514(0) => '0',
      probe515(0) => '0',
      probe516(0) => '0',
      probe517(0) => '0',
      probe518(0) => '0',
      probe519(0) => '0',
      probe52(0) => '0',
      probe520(0) => '0',
      probe521(0) => '0',
      probe522(0) => '0',
      probe523(0) => '0',
      probe524(0) => '0',
      probe525(0) => '0',
      probe526(0) => '0',
      probe527(0) => '0',
      probe528(0) => '0',
      probe529(0) => '0',
      probe53(0) => '0',
      probe530(0) => '0',
      probe531(0) => '0',
      probe532(0) => '0',
      probe533(0) => '0',
      probe534(0) => '0',
      probe535(0) => '0',
      probe536(0) => '0',
      probe537(0) => '0',
      probe538(0) => '0',
      probe539(0) => '0',
      probe54(0) => '0',
      probe540(0) => '0',
      probe541(0) => '0',
      probe542(0) => '0',
      probe543(0) => '0',
      probe544(0) => '0',
      probe545(0) => '0',
      probe546(0) => '0',
      probe547(0) => '0',
      probe548(0) => '0',
      probe549(0) => '0',
      probe55(0) => '0',
      probe550(0) => '0',
      probe551(0) => '0',
      probe552(0) => '0',
      probe553(0) => '0',
      probe554(0) => '0',
      probe555(0) => '0',
      probe556(0) => '0',
      probe557(0) => '0',
      probe558(0) => '0',
      probe559(0) => '0',
      probe56(0) => '0',
      probe560(0) => '0',
      probe561(0) => '0',
      probe562(0) => '0',
      probe563(0) => '0',
      probe564(0) => '0',
      probe565(0) => '0',
      probe566(0) => '0',
      probe567(0) => '0',
      probe568(0) => '0',
      probe569(0) => '0',
      probe57(0) => '0',
      probe570(0) => '0',
      probe571(0) => '0',
      probe572(0) => '0',
      probe573(0) => '0',
      probe574(0) => '0',
      probe575(0) => '0',
      probe576(0) => '0',
      probe577(0) => '0',
      probe578(0) => '0',
      probe579(0) => '0',
      probe58(0) => '0',
      probe580(0) => '0',
      probe581(0) => '0',
      probe582(0) => '0',
      probe583(0) => '0',
      probe584(0) => '0',
      probe585(0) => '0',
      probe586(0) => '0',
      probe587(0) => '0',
      probe588(0) => '0',
      probe589(0) => '0',
      probe59(0) => '0',
      probe590(0) => '0',
      probe591(0) => '0',
      probe592(0) => '0',
      probe593(0) => '0',
      probe594(0) => '0',
      probe595(0) => '0',
      probe596(0) => '0',
      probe597(0) => '0',
      probe598(0) => '0',
      probe599(0) => '0',
      probe6(0) => '0',
      probe60(0) => '0',
      probe600(0) => '0',
      probe601(0) => '0',
      probe602(0) => '0',
      probe603(0) => '0',
      probe604(0) => '0',
      probe605(0) => '0',
      probe606(0) => '0',
      probe607(0) => '0',
      probe608(0) => '0',
      probe609(0) => '0',
      probe61(0) => '0',
      probe610(0) => '0',
      probe611(0) => '0',
      probe612(0) => '0',
      probe613(0) => '0',
      probe614(0) => '0',
      probe615(0) => '0',
      probe616(0) => '0',
      probe617(0) => '0',
      probe618(0) => '0',
      probe619(0) => '0',
      probe62(0) => '0',
      probe620(0) => '0',
      probe621(0) => '0',
      probe622(0) => '0',
      probe623(0) => '0',
      probe624(0) => '0',
      probe625(0) => '0',
      probe626(0) => '0',
      probe627(0) => '0',
      probe628(0) => '0',
      probe629(0) => '0',
      probe63(0) => '0',
      probe630(0) => '0',
      probe631(0) => '0',
      probe632(0) => '0',
      probe633(0) => '0',
      probe634(0) => '0',
      probe635(0) => '0',
      probe636(0) => '0',
      probe637(0) => '0',
      probe638(0) => '0',
      probe639(0) => '0',
      probe64(0) => '0',
      probe640(0) => '0',
      probe641(0) => '0',
      probe642(0) => '0',
      probe643(0) => '0',
      probe644(0) => '0',
      probe645(0) => '0',
      probe646(0) => '0',
      probe647(0) => '0',
      probe648(0) => '0',
      probe649(0) => '0',
      probe65(0) => '0',
      probe650(0) => '0',
      probe651(0) => '0',
      probe652(0) => '0',
      probe653(0) => '0',
      probe654(0) => '0',
      probe655(0) => '0',
      probe656(0) => '0',
      probe657(0) => '0',
      probe658(0) => '0',
      probe659(0) => '0',
      probe66(0) => '0',
      probe660(0) => '0',
      probe661(0) => '0',
      probe662(0) => '0',
      probe663(0) => '0',
      probe664(0) => '0',
      probe665(0) => '0',
      probe666(0) => '0',
      probe667(0) => '0',
      probe668(0) => '0',
      probe669(0) => '0',
      probe67(0) => '0',
      probe670(0) => '0',
      probe671(0) => '0',
      probe672(0) => '0',
      probe673(0) => '0',
      probe674(0) => '0',
      probe675(0) => '0',
      probe676(0) => '0',
      probe677(0) => '0',
      probe678(0) => '0',
      probe679(0) => '0',
      probe68(0) => '0',
      probe680(0) => '0',
      probe681(0) => '0',
      probe682(0) => '0',
      probe683(0) => '0',
      probe684(0) => '0',
      probe685(0) => '0',
      probe686(0) => '0',
      probe687(0) => '0',
      probe688(0) => '0',
      probe689(0) => '0',
      probe69(0) => '0',
      probe690(0) => '0',
      probe691(0) => '0',
      probe692(0) => '0',
      probe693(0) => '0',
      probe694(0) => '0',
      probe695(0) => '0',
      probe696(0) => '0',
      probe697(0) => '0',
      probe698(0) => '0',
      probe699(0) => '0',
      probe7(0) => '0',
      probe70(0) => '0',
      probe700(0) => '0',
      probe701(0) => '0',
      probe702(0) => '0',
      probe703(0) => '0',
      probe704(0) => '0',
      probe705(0) => '0',
      probe706(0) => '0',
      probe707(0) => '0',
      probe708(0) => '0',
      probe709(0) => '0',
      probe71(0) => '0',
      probe710(0) => '0',
      probe711(0) => '0',
      probe712(0) => '0',
      probe713(0) => '0',
      probe714(0) => '0',
      probe715(0) => '0',
      probe716(0) => '0',
      probe717(0) => '0',
      probe718(0) => '0',
      probe719(0) => '0',
      probe72(0) => '0',
      probe720(0) => '0',
      probe721(0) => '0',
      probe722(0) => '0',
      probe723(0) => '0',
      probe724(0) => '0',
      probe725(0) => '0',
      probe726(0) => '0',
      probe727(0) => '0',
      probe728(0) => '0',
      probe729(0) => '0',
      probe73(0) => '0',
      probe730(0) => '0',
      probe731(0) => '0',
      probe732(0) => '0',
      probe733(0) => '0',
      probe734(0) => '0',
      probe735(0) => '0',
      probe736(0) => '0',
      probe737(0) => '0',
      probe738(0) => '0',
      probe739(0) => '0',
      probe74(0) => '0',
      probe740(0) => '0',
      probe741(0) => '0',
      probe742(0) => '0',
      probe743(0) => '0',
      probe744(0) => '0',
      probe745(0) => '0',
      probe746(0) => '0',
      probe747(0) => '0',
      probe748(0) => '0',
      probe749(0) => '0',
      probe75(0) => '0',
      probe750(0) => '0',
      probe751(0) => '0',
      probe752(0) => '0',
      probe753(0) => '0',
      probe754(0) => '0',
      probe755(0) => '0',
      probe756(0) => '0',
      probe757(0) => '0',
      probe758(0) => '0',
      probe759(0) => '0',
      probe76(0) => '0',
      probe760(0) => '0',
      probe761(0) => '0',
      probe762(0) => '0',
      probe763(0) => '0',
      probe764(0) => '0',
      probe765(0) => '0',
      probe766(0) => '0',
      probe767(0) => '0',
      probe768(0) => '0',
      probe769(0) => '0',
      probe77(0) => '0',
      probe770(0) => '0',
      probe771(0) => '0',
      probe772(0) => '0',
      probe773(0) => '0',
      probe774(0) => '0',
      probe775(0) => '0',
      probe776(0) => '0',
      probe777(0) => '0',
      probe778(0) => '0',
      probe779(0) => '0',
      probe78(0) => '0',
      probe780(0) => '0',
      probe781(0) => '0',
      probe782(0) => '0',
      probe783(0) => '0',
      probe784(0) => '0',
      probe785(0) => '0',
      probe786(0) => '0',
      probe787(0) => '0',
      probe788(0) => '0',
      probe789(0) => '0',
      probe79(0) => '0',
      probe790(0) => '0',
      probe791(0) => '0',
      probe792(0) => '0',
      probe793(0) => '0',
      probe794(0) => '0',
      probe795(0) => '0',
      probe796(0) => '0',
      probe797(0) => '0',
      probe798(0) => '0',
      probe799(0) => '0',
      probe8(0) => '0',
      probe80(0) => '0',
      probe800(0) => '0',
      probe801(0) => '0',
      probe802(0) => '0',
      probe803(0) => '0',
      probe804(0) => '0',
      probe805(0) => '0',
      probe806(0) => '0',
      probe807(0) => '0',
      probe808(0) => '0',
      probe809(0) => '0',
      probe81(0) => '0',
      probe810(0) => '0',
      probe811(0) => '0',
      probe812(0) => '0',
      probe813(0) => '0',
      probe814(0) => '0',
      probe815(0) => '0',
      probe816(0) => '0',
      probe817(0) => '0',
      probe818(0) => '0',
      probe819(0) => '0',
      probe82(0) => '0',
      probe820(0) => '0',
      probe821(0) => '0',
      probe822(0) => '0',
      probe823(0) => '0',
      probe824(0) => '0',
      probe825(0) => '0',
      probe826(0) => '0',
      probe827(0) => '0',
      probe828(0) => '0',
      probe829(0) => '0',
      probe83(0) => '0',
      probe830(0) => '0',
      probe831(0) => '0',
      probe832(0) => '0',
      probe833(0) => '0',
      probe834(0) => '0',
      probe835(0) => '0',
      probe836(0) => '0',
      probe837(0) => '0',
      probe838(0) => '0',
      probe839(0) => '0',
      probe84(0) => '0',
      probe840(0) => '0',
      probe841(0) => '0',
      probe842(0) => '0',
      probe843(0) => '0',
      probe844(0) => '0',
      probe845(0) => '0',
      probe846(0) => '0',
      probe847(0) => '0',
      probe848(0) => '0',
      probe849(0) => '0',
      probe85(0) => '0',
      probe850(0) => '0',
      probe851(0) => '0',
      probe852(0) => '0',
      probe853(0) => '0',
      probe854(0) => '0',
      probe855(0) => '0',
      probe856(0) => '0',
      probe857(0) => '0',
      probe858(0) => '0',
      probe859(0) => '0',
      probe86(0) => '0',
      probe860(0) => '0',
      probe861(0) => '0',
      probe862(0) => '0',
      probe863(0) => '0',
      probe864(0) => '0',
      probe865(0) => '0',
      probe866(0) => '0',
      probe867(0) => '0',
      probe868(0) => '0',
      probe869(0) => '0',
      probe87(0) => '0',
      probe870(0) => '0',
      probe871(0) => '0',
      probe872(0) => '0',
      probe873(0) => '0',
      probe874(0) => '0',
      probe875(0) => '0',
      probe876(0) => '0',
      probe877(0) => '0',
      probe878(0) => '0',
      probe879(0) => '0',
      probe88(0) => '0',
      probe880(0) => '0',
      probe881(0) => '0',
      probe882(0) => '0',
      probe883(0) => '0',
      probe884(0) => '0',
      probe885(0) => '0',
      probe886(0) => '0',
      probe887(0) => '0',
      probe888(0) => '0',
      probe889(0) => '0',
      probe89(0) => '0',
      probe890(0) => '0',
      probe891(0) => '0',
      probe892(0) => '0',
      probe893(0) => '0',
      probe894(0) => '0',
      probe895(0) => '0',
      probe896(0) => '0',
      probe897(0) => '0',
      probe898(0) => '0',
      probe899(0) => '0',
      probe9(0) => '0',
      probe90(0) => '0',
      probe900(0) => '0',
      probe901(0) => '0',
      probe902(0) => '0',
      probe903(0) => '0',
      probe904(0) => '0',
      probe905(0) => '0',
      probe906(0) => '0',
      probe907(0) => '0',
      probe908(0) => '0',
      probe909(0) => '0',
      probe91(0) => '0',
      probe910(0) => '0',
      probe911(0) => '0',
      probe912(0) => '0',
      probe913(0) => '0',
      probe914(0) => '0',
      probe915(0) => '0',
      probe916(0) => '0',
      probe917(0) => '0',
      probe918(0) => '0',
      probe919(0) => '0',
      probe92(0) => '0',
      probe920(0) => '0',
      probe921(0) => '0',
      probe922(0) => '0',
      probe923(0) => '0',
      probe924(0) => '0',
      probe925(0) => '0',
      probe926(0) => '0',
      probe927(0) => '0',
      probe928(0) => '0',
      probe929(0) => '0',
      probe93(0) => '0',
      probe930(0) => '0',
      probe931(0) => '0',
      probe932(0) => '0',
      probe933(0) => '0',
      probe934(0) => '0',
      probe935(0) => '0',
      probe936(0) => '0',
      probe937(0) => '0',
      probe938(0) => '0',
      probe939(0) => '0',
      probe94(0) => '0',
      probe940(0) => '0',
      probe941(0) => '0',
      probe942(0) => '0',
      probe943(0) => '0',
      probe944(0) => '0',
      probe945(0) => '0',
      probe946(0) => '0',
      probe947(0) => '0',
      probe948(0) => '0',
      probe949(0) => '0',
      probe95(0) => '0',
      probe950(0) => '0',
      probe951(0) => '0',
      probe952(0) => '0',
      probe953(0) => '0',
      probe954(0) => '0',
      probe955(0) => '0',
      probe956(0) => '0',
      probe957(0) => '0',
      probe958(0) => '0',
      probe959(0) => '0',
      probe96(0) => '0',
      probe960(0) => '0',
      probe961(0) => '0',
      probe962(0) => '0',
      probe963(0) => '0',
      probe964(0) => '0',
      probe965(0) => '0',
      probe966(0) => '0',
      probe967(0) => '0',
      probe968(0) => '0',
      probe969(0) => '0',
      probe97(0) => '0',
      probe970(0) => '0',
      probe971(0) => '0',
      probe972(0) => '0',
      probe973(0) => '0',
      probe974(0) => '0',
      probe975(0) => '0',
      probe976(0) => '0',
      probe977(0) => '0',
      probe978(0) => '0',
      probe979(0) => '0',
      probe98(0) => '0',
      probe980(0) => '0',
      probe981(0) => '0',
      probe982(0) => '0',
      probe983(0) => '0',
      probe984(0) => '0',
      probe985(0) => '0',
      probe986(0) => '0',
      probe987(0) => '0',
      probe988(0) => '0',
      probe989(0) => '0',
      probe99(0) => '0',
      probe990(0) => '0',
      probe991(0) => '0',
      probe992(0) => '0',
      probe993(0) => '0',
      probe994(0) => '0',
      probe995(0) => '0',
      probe996(0) => '0',
      probe997(0) => '0',
      probe998(0) => '0',
      probe999(0) => '0',
      sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
      sl_oport0(16 downto 0) => NLW_U0_sl_oport0_UNCONNECTED(16 downto 0),
      trig_in => '0',
      trig_in_ack => NLW_U0_trig_in_ack_UNCONNECTED,
      trig_out => NLW_U0_trig_out_UNCONNECTED,
      trig_out_ack => '0'
    );
end STRUCTURE;
