// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Thu Oct 27 21:09:24 2022
// Host        : hog-efex1.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/SWd4Zmoh/1/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont_stub.v
// Design      : ila_l1id_cont
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ila,Vivado 2019.2" *)
module ila_l1id_cont(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
  probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[1:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[23:0],probe9[7:0],probe10[23:0],probe11[7:0],probe12[31:0],probe13[31:0],probe14[31:0]" */;
  input clk;
  input [1:0]probe0;
  input [0:0]probe1;
  input [0:0]probe2;
  input [0:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe6;
  input [0:0]probe7;
  input [23:0]probe8;
  input [7:0]probe9;
  input [23:0]probe10;
  input [7:0]probe11;
  input [31:0]probe12;
  input [31:0]probe13;
  input [31:0]probe14;
endmodule
