xilinx.com customized_ip rod_RO_Tx 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis gtwizard_v3_6_11 xilinx_anylanguagesynthesis_view_fileset GENtimestamp Mon May 04 20:57:34 UTC 2020 outputProductCRC 9:2d4b5102 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints outputProductCRC 9:2d4b5102 xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl rod_RO_Tx xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:57:34 UTC 2020 outputProductCRC 9:2d4b5102 xilinx_implementation Implementation :vivado.xilinx.com:implementation xilinx_implementation_view_fileset GENtimestamp Mon May 04 20:57:34 UTC 2020 outputProductCRC 9:2d4b5102 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:51:33 UTC 2020 outputProductCRC 9:2d4b5102 dummy out std_logic xilinx_anylanguagesynthesis component_name rod_RO_Tx gt_type GTH gt_column left_column identical_config true identical_protocol_file Start_from_scratch example_chipscope 0 tdlock_time 1000 identical_val_tx_line_rate 6.413 identical_val_tx_reference_clock 160.325 identical_val_no_tx false identical_val_rx_line_rate 6.413 identical_val_rx_reference_clock 160.325 identical_val_no_rx true gt_val_drp false gt_val_drp_clock 60 gt0_val true gt1_val false gt2_val false gt3_val false gt4_val false gt5_val false gt6_val false gt7_val false gt8_val false gt9_val false gt10_val false gt11_val false gt12_val false gt13_val false gt14_val false gt15_val false gt16_val false gt17_val false gt18_val false gt19_val false gt20_val false gt21_val false gt22_val false gt23_val false gt24_val false gt25_val false gt26_val false gt27_val false gt28_val false gt29_val false gt30_val false gt31_val false gt32_val false gt33_val false gt34_val false gt35_val false gt_val_tx_qpll false gt_val_rx_qpll false gt0_val_tx_refclk REFCLK0_Q1 gt1_val_tx_refclk REFCLK1_Q0 gt2_val_tx_refclk REFCLK1_Q0 gt3_val_tx_refclk REFCLK1_Q0 gt4_val_tx_refclk REFCLK1_Q1 gt5_val_tx_refclk REFCLK1_Q1 gt6_val_tx_refclk REFCLK1_Q1 gt7_val_tx_refclk REFCLK1_Q1 gt8_val_tx_refclk REFCLK1_Q2 gt9_val_tx_refclk REFCLK1_Q2 gt10_val_tx_refclk REFCLK1_Q2 gt11_val_tx_refclk REFCLK1_Q2 gt12_val_tx_refclk REFCLK1_Q3 gt13_val_tx_refclk REFCLK1_Q3 gt14_val_tx_refclk REFCLK1_Q3 gt15_val_tx_refclk REFCLK1_Q3 gt16_val_tx_refclk REFCLK1_Q4 gt17_val_tx_refclk REFCLK1_Q4 gt18_val_tx_refclk REFCLK1_Q4 gt19_val_tx_refclk REFCLK1_Q4 gt20_val_tx_refclk REFCLK1_Q5 gt21_val_tx_refclk REFCLK1_Q5 gt22_val_tx_refclk REFCLK1_Q5 gt23_val_tx_refclk REFCLK1_Q5 gt24_val_tx_refclk REFCLK1_Q6 gt25_val_tx_refclk REFCLK1_Q6 gt26_val_tx_refclk REFCLK1_Q6 gt27_val_tx_refclk REFCLK1_Q6 gt28_val_tx_refclk REFCLK1_Q7 gt29_val_tx_refclk REFCLK1_Q7 gt30_val_tx_refclk REFCLK1_Q7 gt31_val_tx_refclk REFCLK1_Q7 gt32_val_tx_refclk REFCLK1_Q8 gt33_val_tx_refclk REFCLK1_Q8 gt34_val_tx_refclk REFCLK1_Q8 gt35_val_tx_refclk REFCLK1_Q8 gt0_val_rx_refclk REFCLK0_Q1 gt1_val_rx_refclk REFCLK1_Q0 gt2_val_rx_refclk REFCLK1_Q0 gt3_val_rx_refclk REFCLK1_Q0 gt4_val_rx_refclk REFCLK1_Q1 gt5_val_rx_refclk REFCLK1_Q1 gt6_val_rx_refclk REFCLK1_Q1 gt7_val_rx_refclk REFCLK1_Q1 gt8_val_rx_refclk REFCLK1_Q2 gt9_val_rx_refclk REFCLK1_Q2 gt10_val_rx_refclk REFCLK1_Q2 gt11_val_rx_refclk REFCLK1_Q2 gt12_val_rx_refclk REFCLK1_Q3 gt13_val_rx_refclk REFCLK1_Q3 gt14_val_rx_refclk REFCLK1_Q3 gt15_val_rx_refclk REFCLK1_Q3 gt16_val_rx_refclk REFCLK1_Q4 gt17_val_rx_refclk REFCLK1_Q4 gt18_val_rx_refclk REFCLK1_Q4 gt19_val_rx_refclk REFCLK1_Q4 gt20_val_rx_refclk REFCLK1_Q5 gt21_val_rx_refclk REFCLK1_Q5 gt22_val_rx_refclk REFCLK1_Q5 gt23_val_rx_refclk REFCLK1_Q5 gt24_val_rx_refclk REFCLK1_Q6 gt25_val_rx_refclk REFCLK1_Q6 gt26_val_rx_refclk REFCLK1_Q6 gt27_val_rx_refclk REFCLK1_Q6 gt28_val_rx_refclk REFCLK1_Q7 gt29_val_rx_refclk REFCLK1_Q7 gt30_val_rx_refclk REFCLK1_Q7 gt31_val_rx_refclk REFCLK1_Q7 gt32_val_rx_refclk REFCLK1_Q8 gt33_val_rx_refclk REFCLK1_Q8 gt34_val_rx_refclk REFCLK1_Q8 gt35_val_rx_refclk REFCLK1_Q8 advanced_clocking false prbs_gen_check false gt0_val_protocol_file Start_from_scratch gt0_val_no_tx false gt0_val_no_rx true gt0_val_tx_line_rate 6.413 gt0_val_tx_data_width 40 gt0_val_encoding 8B/10B gt0_val_tx_int_datawidth 40 gt0_val_tx_reference_clock 160.325 gt0_val_cpll_fbdiv_45 5 gt0_val_cpll_fbdiv 4 gt0_val_qpll_fbdiv 16 gt0_val_cpll_refclk_div 1 gt0_val_qpll_refclk_div 1 gt0_val_cpll_txout_div 1 gt0_val_rx_line_rate 6.413 gt0_val_rx_data_width 20 gt0_val_decoding None gt0_val_rx_int_datawidth 20 gt0_val_rx_reference_clock 160.325 gt0_val_cpll_rxout_div 1 gt0_val_drp true gt0_val_drp_clock 40.08 gt0_val_port_tx8b10bbypass false gt0_val_port_txchardispmode false gt0_val_port_txchardispval false gt0_val_port_txrundisp false gt0_val_port_rxchariscomma false gt0_val_port_rxcharisk false gt0_val_port_rxrundisp false gt0_val_txbuf_en true gt0_val_txusrclk TXOUTCLK gt0_val_rxbuf_en true gt0_val_rxusrclk TXOUTCLK gt0_val_port_txpcsreset false gt0_val_port_txbufstatus false gt0_val_port_txoutclk true gt0_val_port_txrate false gt0_val_port_rxpcsreset false gt0_val_port_rxbufstatus false gt0_val_port_rxbufreset false gt0_val_port_rxoutclk true gt0_val_port_rxrate false gt0_val_rxcomma_deten true gt0_val_align_mcomma_det true gt0_val_align_pcomma_det true gt0_val_dec_mcomma_detect true gt0_val_dec_pcomma_detect true gt0_val_dec_valid_comma_only false gt0_val_comma_preset User_defined gt0_val_align_pcomma_value 0101111100 gt0_val_align_mcomma_value 1010000011 gt0_val_align_comma_enable 1111111111 gt0_val_align_comma_double false gt0_val_align_comma_word Any_Byte_Boundary gt0_val_port_rxpcommaalignen false gt0_val_port_rxmcommaalignen false gt0_val_port_rxslide false gt0_val_port_rxbyteisaligned false gt0_val_port_rxbyterealign false gt0_val_port_rxcommadet false gt0_val_txdiff_emph_mode Custom gt0_val_txdiffctrl false gt0_val_txpostcursor false gt0_val_dfe_mode DFE-Auto_(no_sliding_TAP) gt0_val_agc_mode Auto gt0_val_rx_termination_voltage GND gt0_val_rx_cm_trim 100 gt0_val_port_txpolarity false gt0_val_port_txinhibit false gt0_val_port_rxpolarity false gt0_val_port_txqpibiasen false gt0_val_port_txqpisenn false gt0_val_port_txqpisenp false gt0_val_port_txqpistrongpdown false gt0_val_port_txqpiweakpup false gt0_val_port_rxqpien false gt0_val_port_rxqpisenn false gt0_val_port_rxqpisenp false gt0_val_port_rxdfereset false gt0_val_port_rxdfeagcovrden false gt0_val_port_rxlpmhfovrden false gt0_val_port_rxlpmlfklovrden false gt0_val_pcs_pcie_en false gt0_val_sata_rx_burst_val 4 gt0_val_sata_e_idle_val 4 gt0_val_pd_trans_time_to_p2 100 gt0_val_pd_trans_time_from_p2 60 gt0_val_pd_trans_time_non_p2 60 gt0_val_port_loopback false gt0_val_port_sigvalidclk false gt0_val_port_clkrsvd false gt0_val_port_tx8b10ben false gt0_val_port_txpippmen false gt0_val_port_txpippmpd false gt0_val_port_txpippmovrden false gt0_val_port_txpippmstepsize false gt0_val_port_txpippmsel false gt0_val_port_rxstatus false gt0_val_port_rxvalid false gt0_val_port_cominitdet false gt0_val_port_comsasdet false gt0_val_port_comwakedet false gt0_val_port_txcominit false gt0_val_port_txcomsas false gt0_val_port_txcomwake false gt0_val_port_txcomfinish false gt0_val_port_txdetectrx false gt0_val_port_txelecidle false gt0_val_port_phystatus false gt0_val_port_rxelecidle true gt0_val_prbs_detector false gt0_val_port_txprbssel false gt0_val_port_txprbsforceerr false gt0_val_rxprbs_err_loopback false gt0_val_cb false gt0_val_chan_bond_seq_2_use false gt0_val_chan_bond_seq_len 1 gt0_val_chan_bond_max_skew 1 gt0_val_cc false gt0_val_clk_cor_seq_2_use false gt0_val_clk_cor_seq_len 1 gt0_val_ppm_offset 100 gt0_val_cc_seq_periodicity 5000 gt0_val_chan_bond_seq_1_1 00000000 gt0_val_chan_bond_seq_1_1_k false gt0_val_chan_bond_seq_1_1_disp false gt0_val_chan_bond_seq_1_1_mask false gt0_val_chan_bond_seq_1_2 00000000 gt0_val_chan_bond_seq_1_2_k false gt0_val_chan_bond_seq_1_2_disp false gt0_val_chan_bond_seq_1_2_mask false gt0_val_chan_bond_seq_1_3 00000000 gt0_val_chan_bond_seq_1_3_k false gt0_val_chan_bond_seq_1_3_disp false gt0_val_chan_bond_seq_1_3_mask false gt0_val_chan_bond_seq_1_4 00000000 gt0_val_chan_bond_seq_1_4_k false gt0_val_chan_bond_seq_1_4_disp false gt0_val_chan_bond_seq_1_4_mask false gt0_val_chan_bond_seq_2_1 00000000 gt0_val_chan_bond_seq_2_1_k false gt0_val_chan_bond_seq_2_1_disp false gt0_val_chan_bond_seq_2_1_mask false gt0_val_chan_bond_seq_2_2 00000000 gt0_val_chan_bond_seq_2_2_k false gt0_val_chan_bond_seq_2_2_disp false gt0_val_chan_bond_seq_2_2_mask false gt0_val_chan_bond_seq_2_3 00000000 gt0_val_chan_bond_seq_2_3_k false gt0_val_chan_bond_seq_2_3_disp false gt0_val_chan_bond_seq_2_3_mask false gt0_val_chan_bond_seq_2_4 00000000 gt0_val_chan_bond_seq_2_4_k false gt0_val_chan_bond_seq_2_4_disp false gt0_val_chan_bond_seq_2_4_mask false gt0_val_clk_cor_seq_1_1 0100000000 gt0_val_clk_cor_seq_1_1_k false gt0_val_clk_cor_seq_1_1_disp false gt0_val_clk_cor_seq_1_1_mask false gt0_val_clk_cor_seq_1_2 0000000000 gt0_val_clk_cor_seq_1_2_k false gt0_val_clk_cor_seq_1_2_disp false gt0_val_clk_cor_seq_1_2_mask false gt0_val_clk_cor_seq_1_3 0000000000 gt0_val_clk_cor_seq_1_3_k false gt0_val_clk_cor_seq_1_3_disp false gt0_val_clk_cor_seq_1_3_mask false gt0_val_clk_cor_seq_1_4 0000000000 gt0_val_clk_cor_seq_1_4_k false gt0_val_clk_cor_seq_1_4_disp false gt0_val_clk_cor_seq_1_4_mask false gt0_val_clk_cor_seq_2_1 0100000000 gt0_val_clk_cor_seq_2_1_k false gt0_val_clk_cor_seq_2_1_disp false gt0_val_clk_cor_seq_2_1_mask false gt0_val_clk_cor_seq_2_2 0000000000 gt0_val_clk_cor_seq_2_2_k false gt0_val_clk_cor_seq_2_2_disp false gt0_val_clk_cor_seq_2_2_mask false gt0_val_clk_cor_seq_2_3 0000000000 gt0_val_clk_cor_seq_2_3_k false gt0_val_clk_cor_seq_2_3_disp false gt0_val_clk_cor_seq_2_3_mask false gt0_val_clk_cor_seq_2_4 0000000000 gt0_val_clk_cor_seq_2_4_k false gt0_val_clk_cor_seq_2_4_disp false gt0_val_clk_cor_seq_2_4_mask false gt0_val_rxslide_mode OFF gt0_val_max_cb_level 7 gt0_val_txoutclk_source AUTO gt0_val_rxoutclk_source AUTO num_active_gt_in_unit 1 num_active_unit 1 c_xspeedgrade -2 c_xdevice xc7vx550t gt_row bottom_row silicon_version no_silicon_version_loaded gt36_val false gt37_val false gt38_val false gt39_val false gt40_val false gt41_val false gt42_val false gt43_val false gt44_val false gt45_val false gt46_val false gt47_val false gt_val_tx_pll CPLL gt_val_rx_pll CPLL gt_val_extended_timeout false gt36_val_tx_refclk REFCLK1_Q9 gt37_val_tx_refclk REFCLK1_Q9 gt38_val_tx_refclk REFCLK1_Q9 gt39_val_tx_refclk REFCLK1_Q9 gt40_val_tx_refclk REFCLK1_Q10 gt41_val_tx_refclk REFCLK1_Q10 gt42_val_tx_refclk REFCLK1_Q10 gt43_val_tx_refclk REFCLK1_Q10 gt44_val_tx_refclk REFCLK1_Q11 gt45_val_tx_refclk REFCLK1_Q11 gt46_val_tx_refclk REFCLK1_Q11 gt47_val_tx_refclk REFCLK1_Q11 gt36_val_rx_refclk REFCLK1_Q9 gt37_val_rx_refclk REFCLK1_Q9 gt38_val_rx_refclk REFCLK1_Q9 gt39_val_rx_refclk REFCLK1_Q9 gt40_val_rx_refclk REFCLK1_Q10 gt41_val_rx_refclk REFCLK1_Q10 gt42_val_rx_refclk REFCLK1_Q10 gt43_val_rx_refclk REFCLK1_Q10 gt44_val_rx_refclk REFCLK1_Q11 gt45_val_rx_refclk REFCLK1_Q11 gt46_val_rx_refclk REFCLK1_Q11 gt47_val_rx_refclk REFCLK1_Q11 gt0_uselabtools true gt0_usesharedlogic 0 gt0_pll0_fbdiv 1 gt0_pll0_fbdiv_45 4 gt0_pll0_refclk_div 1 gt0_pll0_txout_div 1 gt0_pll0_rxout_div 1 gt0_pll1_fbdiv 1 gt0_pll1_fbdiv_45 4 gt0_pll1_refclk_div 1 gt0_pll1_txout_div 1 gt0_pll1_rxout_div 1 pcie_sync_mode false pcie_cb_en false pcie_lpm_dfe DFE pcie_cb_mode One_Hop gt0_val_port_pll0pd false gt0_val_port_pll1pd false gt0_val_port_cpllpd false gt0_val_port_qpllpd false gt0_val_port_rxstartofseq false gt0_val_tx_buffer_bypass_mode Auto gt0_val_rx_buffer_bypass_mode Auto gt0_val_port_txpmareset false gt0_val_port_txsysclksel false gt0_val_port_rxpmareset false gt0_val_port_rxsysclksel false gt0_val_port_rxcdrhold false gt0_val_txprecursor false gt0_val_txmaincursor false gt0_val_rx_equalizer false gt0_val_port_rxlpmen false gt0_val_port_txpowerdown false gt0_val_port_rxpowerdown false gt0_val_oob false octal0_val true octal1_val false octal0_val_identical_config true octal0_val_multi_channel_mode 0000 octal0_val_master_slave false use_gtz0 true use_gtz1 true use_gtz2 true use_gtz3 true use_gtz4 true use_gtz5 true use_gtz6 true use_gtz7 true octal0_val_identical_protocol_file Start_from_scratch gtz0_val_protocol_file Start_from_scratch gtz1_val_protocol_file Start_from_scratch gtz2_val_protocol_file Start_from_scratch gtz3_val_protocol_file Start_from_scratch gtz4_val_protocol_file Start_from_scratch gtz5_val_protocol_file Start_from_scratch gtz6_val_protocol_file Start_from_scratch gtz7_val_protocol_file Start_from_scratch octal0_val_identical_tx_line_rate 25.78125 gtz0_val_tx_line_rate 25.78125 gtz1_val_tx_line_rate 25.78125 gtz2_val_tx_line_rate 25.78125 gtz3_val_tx_line_rate 25.78125 gtz4_val_tx_line_rate 25.78125 gtz5_val_tx_line_rate 25.78125 gtz6_val_tx_line_rate 25.78125 gtz7_val_tx_line_rate 25.78125 octal0_val_identical_no_tx false gtz0_val_no_tx false gtz1_val_no_tx false gtz2_val_no_tx false gtz3_val_no_tx false gtz4_val_no_tx false gtz5_val_no_tx false gtz6_val_no_tx false gtz7_val_no_tx false octal0_val_identical_rx_line_rate 25.78125 gtz0_val_rx_line_rate 25.78125 gtz1_val_rx_line_rate 25.78125 gtz2_val_rx_line_rate 25.78125 gtz3_val_rx_line_rate 25.78125 gtz4_val_rx_line_rate 25.78125 gtz5_val_rx_line_rate 25.78125 gtz6_val_rx_line_rate 25.78125 gtz7_val_rx_line_rate 25.78125 octal0_val_identical_no_rx false gtz0_val_no_rx false gtz1_val_no_rx false gtz2_val_no_rx false gtz3_val_no_rx false gtz4_val_no_rx false gtz5_val_no_rx false gtz6_val_no_rx false gtz7_val_no_rx false octal0_val_identical_refclk_source REFCLK0 octal0_val_refclk0 322.266 octal0_val_refclk1 322.266 octal0_val_txoutclk0_source LANE0 octal0_val_txoutclk1_source LANE0 octal0_val_rxoutclk0_source LANE0 octal0_val_rxoutclk1_source LANE0 octal0_val_rxoutclk2_source LANE0 octal0_val_rxoutclk3_source LANE0 octal0_val_drpclk_source DRPCLK0 gtz0_val_refclk_source REFCLK0 gtz1_val_refclk_source REFCLK0 gtz2_val_refclk_source REFCLK0 gtz3_val_refclk_source REFCLK0 gtz4_val_refclk_source REFCLK0 gtz5_val_refclk_source REFCLK0 gtz6_val_refclk_source REFCLK0 gtz7_val_refclk_source REFCLK0 gtz0_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz1_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz2_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz3_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz4_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz5_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz6_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz7_val_txoutclk_source TXOUTCLKPMA_DIV4 gtz0_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz1_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz2_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz3_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz4_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz5_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz6_val_rxoutclk_source RXRECCLKPMA_DIV4 gtz7_val_rxoutclk_source RXRECCLKPMA_DIV4 octal0_val_txusrclk0_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk1_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk2_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk3_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk4_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk5_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk6_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk7_source OCTAL0_TXOUTCLK0 octal0_val_rxusrclk0_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk1_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk2_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk3_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk4_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk5_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk6_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk7_source OCTAL0_RXOUTCLK0 gtz0_val_txusrclk_source TXUSRCLK0 gtz1_val_txusrclk_source TXUSRCLK0 gtz2_val_txusrclk_source TXUSRCLK0 gtz3_val_txusrclk_source TXUSRCLK0 gtz4_val_txusrclk_source TXUSRCLK0 gtz5_val_txusrclk_source TXUSRCLK0 gtz6_val_txusrclk_source TXUSRCLK0 gtz7_val_txusrclk_source TXUSRCLK0 gtz0_val_rxusrclk_source RXUSRCLK0 gtz1_val_rxusrclk_source RXUSRCLK0 gtz2_val_rxusrclk_source RXUSRCLK0 gtz3_val_rxusrclk_source RXUSRCLK0 gtz4_val_rxusrclk_source RXUSRCLK0 gtz5_val_rxusrclk_source RXUSRCLK0 gtz6_val_rxusrclk_source RXUSRCLK0 gtz7_val_rxusrclk_source RXUSRCLK0 gtz0_val_data_width 160 gtz1_val_data_width 160 gtz2_val_data_width 160 gtz3_val_data_width 160 gtz4_val_data_width 160 gtz5_val_data_width 160 gtz6_val_data_width 160 gtz7_val_data_width 160 gtz0_val_encoding GB_100GBASE_R4 gtz1_val_encoding GB_100GBASE_R4 gtz2_val_encoding GB_100GBASE_R4 gtz3_val_encoding GB_100GBASE_R4 gtz4_val_encoding GB_100GBASE_R4 gtz5_val_encoding GB_100GBASE_R4 gtz6_val_encoding GB_100GBASE_R4 gtz7_val_encoding GB_100GBASE_R4 gtz0_val_port_txfibreset false gtz0_val_port_txfifostatus false gtz0_val_port_txratesel false gtz0_val_port_txen false gtz0_val_port_txpolarity false gtz0_val_port_txoutputen false gtz0_val_port_txeqpostctrl false gtz0_val_port_txeqprectrl false gtz0_val_port_txslewctrl false gtz0_val_port_txattnctrl false gtz0_val_port_rxfibreset false gtz0_val_port_rxfifostatus false gtz0_val_port_rxratesel false gtz0_val_port_rxpolarity false gtz0_val_port_rxen false gtz0_val_port_rxsignalok false gtz0_val_port_rxbitslip false gtz0_val_port_refsel false gtz0_val_port_corecntl false gtz0_val_port_pllrecalen false gtz0_val_port_loopback false gtz0_val_port_txprbs false gtz0_val_port_rxprbs false gtz0_val_rx_div_N1 5 gtz0_val_rx_div_N2 8 gtz0_val_rx_div_L 0.5 gtz0_val_tx_div_N1 5 gtz0_val_tx_div_N2 8 gtz0_val_tx_div_L 0.5 gtz1_val_rx_div_N1 5 gtz1_val_rx_div_N2 8 gtz1_val_rx_div_L 0.5 gtz1_val_tx_div_N1 5 gtz1_val_tx_div_N2 8 gtz1_val_tx_div_L 0.5 gtz2_val_rx_div_N1 5 gtz2_val_rx_div_N2 8 gtz2_val_rx_div_L 0.5 gtz2_val_tx_div_N1 5 gtz2_val_tx_div_N2 8 gtz2_val_tx_div_L 0.5 gtz3_val_rx_div_N1 5 gtz3_val_rx_div_N2 8 gtz3_val_rx_div_L 0.5 gtz3_val_tx_div_N1 5 gtz3_val_tx_div_N2 8 gtz3_val_tx_div_L 0.5 gtz4_val_rx_div_N1 5 gtz4_val_rx_div_N2 8 gtz4_val_rx_div_L 0.5 gtz4_val_tx_div_N1 5 gtz4_val_tx_div_N2 8 gtz4_val_tx_div_L 0.5 gtz5_val_rx_div_N1 5 gtz5_val_rx_div_N2 8 gtz5_val_rx_div_L 0.5 gtz5_val_tx_div_N1 5 gtz5_val_tx_div_N2 8 gtz5_val_tx_div_L 0.5 gtz6_val_rx_div_N1 5 gtz6_val_rx_div_N2 8 gtz6_val_rx_div_L 0.5 gtz6_val_tx_div_N1 5 gtz6_val_tx_div_N2 8 gtz6_val_tx_div_L 0.5 gtz7_val_rx_div_N1 5 gtz7_val_rx_div_N2 8 gtz7_val_rx_div_L 0.5 gtz7_val_tx_div_N1 5 gtz7_val_tx_div_N2 8 gtz7_val_tx_div_L 0.5 choice_list_00d9575a 16 32 64 choice_list_0fbde0c1 20 choice_list_11c8f0f1 TXOUTCLK RXOUTCLK choice_list_2160e282 TXUSRCLK0 TXUSRCLK1 TXUSRCLK2 TXUSRCLK3 TXUSRCLK4 TXUSRCLK5 TXUSRCLK6 TXUSRCLK7 choice_list_26882056 Auto choice_list_67df265b PCS PMA AUTO OFF choice_list_6f11e568 Auto Manual choice_list_741d7aa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 choice_list_7f4090d6 16 20 32 40 64 80 choice_list_97e83fc8 RXUSRCLK0 RXUSRCLK1 RXUSRCLK2 RXUSRCLK3 RXUSRCLK4 RXUSRCLK5 RXUSRCLK6 RXUSRCLK7 choice_list_9a0309a1 160 80 40 choice_list_a025f10b 322.266 choice_list_a0d11b39 100 200 250 300 350 400 500 550 600 700 800 850 900 950 1000 1100 choice_list_a4d68fc1 GND AVTT Floating Programmable choice_list_ae1b3e88 128.260 160.325 200.406 213.767 256.520 267.208 320.650 400.813 427.533 534.417 641.300 801.625 choice_list_afcf1f92 GTH choice_list_bd62f487 TXOUTCLK choice_list_c4fcf6a2 DFE LPM choice_list_c70dfaa0 20 40 choice_list_dede9491 CPLL QPLL choice_list_e6469819 1 2 4 choice_list_ee039839 GTZ0 GTZ1 GTZ2 GTZ3 GTZ4 GTZ5 GTZ6 GTZ7 choice_list_f82abaec DRPCLK0 DRPCLK1 choice_list_fb544742 REFCLK0 REFCLK1 choice_pairs_02337852 REFCLK0_Q10 REFCLK1_Q10 choice_pairs_0a1ce076 left_column right_column choice_pairs_0bd5755c REFCLK0_Q7 REFCLK1_Q7 REFCLK0_Q8 REFCLK1_Q8 REFCLK0_Q9 REFCLK1_Q9 choice_pairs_1578a8ac no_silicon_version_loaded Initial_ES choice_pairs_1a449a0c OCTAL0_RXOUTCLK0 OCTAL0_RXOUTCLK1 OCTAL0_RXOUTCLK2 OCTAL0_RXOUTCLK3 OCTAL1_RXOUTCLK0 OCTAL1_RXOUTCLK1 OCTAL1_RXOUTCLK2 OCTAL1_RXOUTCLK3 choice_pairs_2b285abe REFCLK0_Q2 REFCLK1_Q2 REFCLK0_Q3 REFCLK1_Q3 REFCLK0_Q4 REFCLK1_Q4 choice_pairs_2bfee281 REFCLK0_Q4 REFCLK1_Q4 REFCLK0_Q5 REFCLK1_Q5 REFCLK0_Q6 REFCLK1_Q6 choice_pairs_2d0dd098 None None_(MSB_First) 8B/10B 64B/66B_with_Ext_Seq_Ctr 64B/67B_with_Ext_Seq_Ctr choice_pairs_2d726288 OCTAL0_TXOUTCLK0 OCTAL0_TXOUTCLK1 OCTAL1_TXOUTCLK0 OCTAL1_TXOUTCLK1 choice_pairs_4803bc60 Custom PCIe_Gen1/Gen2 PCIe_Gen3 QPI choice_pairs_53749dec 1 0 choice_pairs_55bc3414 Any_Byte_Boundary Two_Byte_Boundaries Four_Byte_Boundaries choice_pairs_5d8a4689 RXOUTCLK_LANE0 RXOUTCLK_LANE1 RXOUTCLK_LANE2 RXOUTCLK_LANE3 RXOUTCLK_LANE4 RXOUTCLK_LANE5 RXOUTCLK_LANE6 RXOUTCLK_LANE7 choice_pairs_623b42a7 None None_(MSB_First) choice_pairs_6f032911 REFCLK0_Q3 REFCLK1_Q3 REFCLK0_Q4 REFCLK1_Q4 REFCLK0_Q5 REFCLK1_Q5 choice_pairs_77fb08df top_row bottom_row choice_pairs_799edca2 REFCLK0_Q0 REFCLK1_Q0 REFCLK0_Q1 REFCLK1_Q1 REFCLK0_Q2 REFCLK1_Q2 choice_pairs_8925e2f0 TXOUTCLK_LANE0 TXOUTCLK_LANE1 TXOUTCLK_LANE2 TXOUTCLK_LANE3 TXOUTCLK_LANE4 TXOUTCLK_LANE5 TXOUTCLK_LANE6 TXOUTCLK_LANE7 choice_pairs_8b716cf3 REFCLK0_Q0 REFCLK1_Q0 REFCLK0_Q1 REFCLK1_Q1 choice_pairs_8cd604e4 Start_from_scratch choice_pairs_8dd91650 REFCLK0_Q11 REFCLK1_Q11 choice_pairs_8e455686 REFCLK0_Q6 REFCLK1_Q6 REFCLK0_Q7 REFCLK1_Q7 REFCLK0_Q8 REFCLK1_Q8 choice_pairs_9312a059 Start_from_scratch 10GBASE-KR 10GBASE-R aurora_8b10b_multi_lane_2byte aurora_8b10b_multi_lane_4byte aurora_8b10b_single_lane_2byte aurora_8b10b_single_lane_4byte aurora_64b66b CAUI CEI6 CEI11 cpri display_port gigabit_ethernet_CC gigabit_ethernet_noCC hdmi interlaken JESD204 OC48 OC192 OTL_3_4 OTU4 QSGMII rxaui-Dune_Networks srio_gen2_multi_lane srio_gen2_single_lane srio_multi_lane srio_single_lane xaui xlaui choice_pairs_959dabb1 One_Hop Daisy_Chain Binary_Tree choice_pairs_9b80d527 TX_FIFO_CLK choice_pairs_9eff6d1e RX_FIFO_CLK choice_pairs_b0d08417 REFCLK0_Q1 REFCLK1_Q1 REFCLK0_Q2 REFCLK1_Q2 REFCLK0_Q3 REFCLK1_Q3 choice_pairs_bdc70e9d REFCLK0_Q8 REFCLK1_Q8 REFCLK0_Q9 REFCLK1_Q9 choice_pairs_bf7c0194 100GBASER_MODE 64B66B_MODE RAW_MODE choice_pairs_d701f812 DFE-Auto_(no_sliding_TAP) LPM-Auto choice_pairs_e2b0ba34 REFCLK0_Q5 REFCLK1_Q5 REFCLK0_Q6 REFCLK1_Q6 REFCLK0_Q7 REFCLK1_Q7 choice_pairs_e3564e73 Start_from_scratch CAUI_4 choice_pairs_f28bec3f OFF x4_channels_0to3 x4_channels_4to7 2x4_channels_0to7 x5_channels_0to4 x8_channels_0to7 choice_pairs_fb7aacb4 User_defined K28.5 K28.1 xilinx_anylanguagesynthesis_view_fileset rod_RO_Tx/example_design/rod_ro_tx_tx_startup_fsm.vhd vhdlSource rod_RO_Tx/example_design/rod_ro_tx_rx_startup_fsm.vhd vhdlSource rod_ro_tx_init.vhd vhdlSource rod_ro_tx_cpll_railing.vhd vhdlSource rod_ro_tx_gt.vhd vhdlSource rod_ro_tx_multi_gt.vhd vhdlSource rod_RO_Tx.xdc xdc rod_RO_Tx/example_design/rod_ro_tx_sync_block.vhd vhdlSource rod_RO_Tx_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis xilinx_vhdlsynthesiswrapper_view_fileset rod_ro_tx.vhd vhdlSource xilinx_implementation_view_fileset tcl/v7ht.tcl tclSource USED_IN_opt_design xilinx_externalfiles_view_fileset rod_RO_Tx.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib rod_RO_Tx_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib rod_RO_Tx_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib rod_RO_Tx_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib rod_RO_Tx_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib Use the 7 Series FPGAs Transceivers Wizard to configure one or more Virtex-7/Kintex-7/Artix-7/Zynq FPGA transceivers. Start from scratch, or use an industry standard template. The Wizard generates a custom wrapper for the tranceivers you've selected. In addition, it produces an example design, testbench, and scripts to observe the transceivers operating under simulation and in hardware. Component_Name rod_RO_Tx identical_config true identical_protocol_file Start_from_scratch gt_type GTH gt_column left_column silicon_version no_silicon_version_loaded identical_val_tx_line_rate Identical Val Tx Line Rate 6.413 identical_val_no_tx false identical_val_rx_line_rate 6.413 identical_val_no_rx true gt_val_drp false gt_val_drp_clock 60 gt0_val Gt0 Val true gt_val_tx_pll CPLL gt0_val_tx_refclk Gt0 Val Tx Refclk REFCLK0_Q1 gt_val_rx_pll CPLL gt0_val_rx_refclk Gt0 Val Rx Refclk REFCLK0_Q1 gt1_val Gt1 Val false gt1_val_tx_refclk Gt1 Val Tx Refclk REFCLK1_Q0 gt1_val_rx_refclk Gt1 Val Rx Refclk REFCLK1_Q0 gt2_val Gt2 Val false gt2_val_tx_refclk Gt2 Val Tx Refclk REFCLK1_Q0 gt2_val_rx_refclk Gt2 Val Rx Refclk REFCLK1_Q0 gt3_val Gt3 Val false gt3_val_tx_refclk Gt3 Val Tx Refclk REFCLK1_Q0 gt3_val_rx_refclk Gt3 Val Rx Refclk REFCLK1_Q0 gt4_val Gt4 Val false gt4_val_tx_refclk Gt4 Val Tx Refclk REFCLK1_Q1 gt4_val_rx_refclk Gt4 Val Rx Refclk REFCLK1_Q1 gt5_val Gt5 Val false gt5_val_tx_refclk Gt5 Val Tx Refclk REFCLK1_Q1 gt5_val_rx_refclk Gt5 Val Rx Refclk REFCLK1_Q1 gt6_val Gt6 Val false gt6_val_tx_refclk Gt6 Val Tx Refclk REFCLK1_Q1 gt6_val_rx_refclk Gt6 Val Rx Refclk REFCLK1_Q1 gt7_val Gt7 Val false gt7_val_tx_refclk Gt7 Val Tx Refclk REFCLK1_Q1 gt7_val_rx_refclk Gt7 Val Rx Refclk REFCLK1_Q1 gt8_val Gt8 Val false gt8_val_tx_refclk Gt8 Val Tx Refclk REFCLK1_Q2 gt8_val_rx_refclk Gt8 Val Rx Refclk REFCLK1_Q2 gt9_val Gt9 Val false gt9_val_tx_refclk Gt9 Val Tx Refclk REFCLK1_Q2 gt9_val_rx_refclk Gt9 Val Rx Refclk REFCLK1_Q2 gt10_val Gt10 Val false gt10_val_tx_refclk Gt10 Val Tx Refclk REFCLK1_Q2 gt10_val_rx_refclk Gt10 Val Rx Refclk REFCLK1_Q2 gt11_val Gt11 Val false gt11_val_tx_refclk Gt11 Val Tx Refclk REFCLK1_Q2 gt11_val_rx_refclk Gt11 Val Rx Refclk REFCLK1_Q2 gt12_val Gt12 Val false gt12_val_tx_refclk Gt12 Val Tx Refclk REFCLK1_Q3 gt12_val_rx_refclk Gt12 Val Rx Refclk REFCLK1_Q3 gt13_val Gt13 Val false gt13_val_tx_refclk Gt13 Val Tx Refclk REFCLK1_Q3 gt13_val_rx_refclk Gt13 Val Rx Refclk REFCLK1_Q3 gt14_val Gt14 Val false gt14_val_tx_refclk Gt14 Val Tx Refclk REFCLK1_Q3 gt14_val_rx_refclk Gt14 Val Rx Refclk REFCLK1_Q3 gt15_val Gt15 Val false gt15_val_tx_refclk Gt15 Val Tx Refclk REFCLK1_Q3 gt15_val_rx_refclk Gt15 Val Rx Refclk REFCLK1_Q3 gt16_val Gt16 Val false gt16_val_tx_refclk Gt16 Val Tx Refclk REFCLK1_Q4 gt16_val_rx_refclk Gt16 Val Rx Refclk REFCLK1_Q4 gt17_val Gt17 Val false gt17_val_tx_refclk Gt17 Val Tx Refclk REFCLK1_Q4 gt17_val_rx_refclk Gt17 Val Rx Refclk REFCLK1_Q4 gt18_val Gt18 Val false gt18_val_tx_refclk Gt18 Val Tx Refclk REFCLK1_Q4 gt18_val_rx_refclk Gt18 Val Rx Refclk REFCLK1_Q4 gt19_val Gt19 Val false gt19_val_tx_refclk Gt19 Val Tx Refclk REFCLK1_Q4 gt19_val_rx_refclk Gt19 Val Rx Refclk REFCLK1_Q4 gt20_val Gt20 Val false gt20_val_tx_refclk Gt20 Val Tx Refclk REFCLK1_Q5 gt20_val_rx_refclk Gt20 Val Rx Refclk REFCLK1_Q5 gt21_val Gt21 Val false gt21_val_tx_refclk Gt21 Val Tx Refclk REFCLK1_Q5 gt21_val_rx_refclk Gt21 Val Rx Refclk REFCLK1_Q5 gt22_val Gt22 Val false gt22_val_tx_refclk Gt22 Val Tx Refclk REFCLK1_Q5 gt22_val_rx_refclk Gt22 Val Rx Refclk REFCLK1_Q5 gt23_val Gt23 Val false gt23_val_tx_refclk Gt23 Val Tx Refclk REFCLK1_Q5 gt23_val_rx_refclk Gt23 Val Rx Refclk REFCLK1_Q5 gt24_val Gt24 Val false gt24_val_tx_refclk Gt24 Val Tx Refclk REFCLK1_Q6 gt24_val_rx_refclk Gt24 Val Rx Refclk REFCLK1_Q6 gt25_val Gt25 Val false gt25_val_tx_refclk Gt25 Val Tx Refclk REFCLK1_Q6 gt25_val_rx_refclk Gt25 Val Rx Refclk REFCLK1_Q6 gt26_val Gt26 Val false gt26_val_tx_refclk Gt26 Val Tx Refclk REFCLK1_Q6 gt26_val_rx_refclk Gt26 Val Rx Refclk REFCLK1_Q6 gt27_val Gt27 Val false gt27_val_tx_refclk Gt27 Val Tx Refclk REFCLK1_Q6 gt27_val_rx_refclk Gt27 Val Rx Refclk REFCLK1_Q6 gt28_val Gt28 Val false gt28_val_tx_refclk Gt28 Val Tx Refclk REFCLK1_Q7 gt28_val_rx_refclk Gt28 Val Rx Refclk REFCLK1_Q7 gt29_val Gt29 Val false gt29_val_tx_refclk Gt29 Val Tx Refclk REFCLK1_Q7 gt29_val_rx_refclk Gt29 Val Rx Refclk REFCLK1_Q7 gt30_val Gt30 Val false gt30_val_tx_refclk Gt30 Val Tx Refclk REFCLK1_Q7 gt30_val_rx_refclk Gt30 Val Rx Refclk REFCLK1_Q7 gt31_val Gt31 Val false gt31_val_tx_refclk Gt31 Val Tx Refclk REFCLK1_Q7 gt31_val_rx_refclk Gt31 Val Rx Refclk REFCLK1_Q7 gt32_val Gt32 Val false gt32_val_tx_refclk Gt32 Val Tx Refclk REFCLK1_Q8 gt32_val_rx_refclk Gt32 Val Rx Refclk REFCLK1_Q8 gt33_val Gt33 Val false gt33_val_tx_refclk Gt33 Val Tx Refclk REFCLK1_Q8 gt33_val_rx_refclk Gt33 Val Rx Refclk REFCLK1_Q8 gt34_val Gt34 Val false gt34_val_tx_refclk Gt34 Val Tx Refclk REFCLK1_Q8 gt34_val_rx_refclk Gt34 Val Rx Refclk REFCLK1_Q8 gt35_val Gt35 Val false gt35_val_tx_refclk Gt35 Val Tx Refclk REFCLK1_Q8 gt35_val_rx_refclk Gt35 Val Rx Refclk REFCLK1_Q8 gt36_val Gt36 Val false gt36_val_tx_refclk Gt36 Val Tx Refclk REFCLK1_Q9 gt36_val_rx_refclk Gt36 Val Rx Refclk REFCLK1_Q9 gt37_val Gt37 Val false gt37_val_tx_refclk Gt37 Val Tx Refclk REFCLK1_Q9 gt37_val_rx_refclk Gt37 Val Rx Refclk REFCLK1_Q9 gt38_val Gt38 Val false gt38_val_tx_refclk Gt38 Val Tx Refclk REFCLK1_Q9 gt38_val_rx_refclk Gt38 Val Rx Refclk REFCLK1_Q9 gt39_val Gt39 Val false gt39_val_tx_refclk Gt39 Val Tx Refclk REFCLK1_Q9 gt39_val_rx_refclk Gt39 Val Rx Refclk REFCLK1_Q9 gt40_val Gt40 Val false gt40_val_tx_refclk Gt40 Val Tx Refclk REFCLK1_Q10 gt40_val_rx_refclk Gt40 Val Rx Refclk REFCLK1_Q10 gt41_val Gt41 Val false gt41_val_tx_refclk Gt41 Val Tx Refclk REFCLK1_Q10 gt41_val_rx_refclk Gt41 Val Rx Refclk REFCLK1_Q10 gt42_val Gt42 Val false gt42_val_tx_refclk Gt42 Val Tx Refclk REFCLK1_Q10 gt42_val_rx_refclk Gt42 Val Rx Refclk REFCLK1_Q10 gt43_val Gt43 Val false gt43_val_tx_refclk Gt43 Val Tx Refclk REFCLK1_Q10 gt43_val_rx_refclk Gt43 Val Rx Refclk REFCLK1_Q10 gt44_val Gt44 Val false gt44_val_tx_refclk Gt44 Val Tx Refclk REFCLK1_Q11 gt44_val_rx_refclk Gt44 Val Rx Refclk REFCLK1_Q11 gt45_val Gt45 Val false gt45_val_tx_refclk Gt45 Val Tx Refclk REFCLK1_Q11 gt45_val_rx_refclk Gt45 Val Rx Refclk REFCLK1_Q11 gt46_val Gt46 Val false gt46_val_tx_refclk Gt46 Val Tx Refclk REFCLK1_Q11 gt46_val_rx_refclk Gt46 Val Rx Refclk REFCLK1_Q11 gt47_val Gt47 Val false gt47_val_tx_refclk Gt47 Val Tx Refclk REFCLK1_Q11 gt47_val_rx_refclk Gt47 Val Rx Refclk REFCLK1_Q11 advanced_clocking false identical_val_tx_reference_clock Identical Val Tx Reference Clock 160.325 identical_val_rx_reference_clock Identical Val Rx Reference Clock 160.325 gt0_val_protocol_file Start_from_scratch gt0_val_no_tx false gt0_val_no_rx true gt0_val_tx_line_rate Gt0 Val Tx Line Rate 6.413 gt0_val_tx_data_width Gt0 Val Tx Data Width 32 gt0_val_encoding Gt0 Val Encoding 8B/10B gt0_val_tx_int_datawidth Gt0 Val Tx Int Datawidth 40 gt0_val_tx_reference_clock Gt0 Val Tx Reference Clock 160.325 gt0_val_rx_line_rate Gt0 Val Rx Line Rate 6.413 gt0_val_rx_data_width Gt0 Val Rx Data Width 20 gt0_val_decoding Gt0 Val Decoding None gt0_val_rx_int_datawidth Gt0 Val Rx Int Datawidth 20 gt0_val_rx_reference_clock Gt0 Val Rx Reference Clock 160.325 gt0_val_cpll_fbdiv_45 5 gt0_val_cpll_fbdiv 4 gt0_val_cpll_refclk_div 1 gt0_val_qpll_refclk_div 1 gt0_val_qpll_fbdiv 16 gt0_val_cpll_rxout_div 1 gt0_val_cpll_txout_div 1 gt0_val_drp true gt0_val_drp_clock 40.08 gt0_val_port_tx8b10bbypass false gt0_val_port_txchardispmode false gt0_val_port_txchardispval false gt0_val_port_rxchariscomma false gt0_val_port_rxcharisk false gt0_val_port_rxstartofseq false gt0_val_txbuf_en true gt0_val_tx_buffer_bypass_mode Auto gt0_val_txusrclk Gt0 Val Txusrclk TXOUTCLK gt0_val_txoutclk_source false gt0_val_rxbuf_en true gt0_val_rx_buffer_bypass_mode Auto gt0_val_rxusrclk Gt0 Val Rxusrclk TXOUTCLK gt0_val_rxoutclk_source false gt0_val_port_txpcsreset false gt0_val_port_txbufstatus false gt0_val_port_txrate false gt0_val_port_rxpcsreset false gt0_val_port_rxbufstatus false gt0_val_port_rxbufreset false gt0_val_port_rxrate false gt0_val_port_txpmareset false gt0_val_port_txsysclksel false gt0_val_port_rxpmareset false gt0_val_port_rxsysclksel false gt0_val_port_rxcdrhold false gt0_val_port_cpllpd false gt0_val_port_qpllpd false pcie_sync_mode false pcie_cb_en false pcie_cb_mode Pcie Cb Mode One_Hop pcie_lpm_dfe Pcie Lpm Dfe DFE gt0_val_rxcomma_deten true gt0_val_align_mcomma_det true gt0_val_align_pcomma_det true gt0_val_dec_mcomma_detect true gt0_val_dec_pcomma_detect true gt0_val_dec_valid_comma_only false gt0_val_comma_preset Gt0 Val Comma Preset User_defined gt0_val_align_pcomma_value 0101111100 gt0_val_align_mcomma_value 1010000011 gt0_val_align_comma_enable 1111111111 gt0_val_align_comma_double false gt0_val_align_comma_word Gt0 Val Align Comma Word Any_Byte_Boundary gt0_val_port_rxpcommaalignen false gt0_val_port_rxmcommaalignen false gt0_val_port_rxslide false gt0_val_port_rxbyteisaligned false gt0_val_port_rxbyterealign false gt0_val_port_rxcommadet false gt0_val_txdiff_emph_mode Gt0 Val Txdiff Emph Mode Custom gt0_val_txdiffctrl false gt0_val_txpostcursor false gt0_val_txprecursor false gt0_val_txmaincursor false gt0_val_dfe_mode Gt0 Val Dfe Mode DFE-Auto_(no_sliding_TAP) gt0_val_agc_mode Gt0 Val Agc Mode Auto gt0_val_rx_termination_voltage GND gt0_val_rx_cm_trim 100 gt0_val_rx_equalizer false gt0_val_port_txpolarity false gt0_val_port_txinhibit false gt0_val_port_rxpolarity false gt0_val_port_txqpibiasen false gt0_val_port_txqpisenn false gt0_val_port_txqpisenp false gt0_val_port_rxqpien false gt0_val_port_rxqpisenn false gt0_val_port_rxqpisenp false gt0_val_port_txqpistrongpdown false gt0_val_port_txqpiweakpup false gt0_val_port_rxdfereset false gt0_val_port_rxdfeagcovrden false gt0_val_port_rxlpmhfovrden false gt0_val_port_rxlpmlfklovrden false gt0_val_port_rxlpmen false gt0_val_pcs_pcie_en false gt0_val_sata_rx_burst_val Gt0 Val Sata Rx Burst Val 4 gt0_val_sata_e_idle_val 4 gt0_val_pd_trans_time_to_p2 Gt0 Val Pd Trans Time To P2 100 gt0_val_pd_trans_time_from_p2 Gt0 Val Pd Trans Time From P2 60 gt0_val_pd_trans_time_non_p2 Gt0 Val Pd Trans Time Non P2 60 gt0_val_port_loopback false gt0_val_port_rxstatus false gt0_val_port_rxvalid false gt0_val_port_cominitdet false gt0_val_port_comsasdet false gt0_val_port_comwakedet false gt0_val_port_txcominit false gt0_val_port_txcomsas false gt0_val_port_txcomwake false gt0_val_port_txcomfinish false gt0_val_port_txdetectrx false gt0_val_port_txelecidle false gt0_val_port_phystatus false gt0_val_port_txpowerdown false gt0_val_port_rxpowerdown false gt0_val_oob false gt0_val_port_rxelecidle true gt0_val_prbs_detector false gt0_val_port_txprbssel false gt0_val_port_txprbsforceerr false gt0_val_rxprbs_err_loopback false gt0_val_cb false gt0_val_chan_bond_seq_2_use false gt0_val_chan_bond_seq_len 1 gt0_val_chan_bond_max_skew 1 gt0_val_cc false gt0_val_ppm_offset 100 gt0_val_cc_seq_periodicity 5000 gt0_val_clk_cor_seq_2_use false gt0_val_clk_cor_seq_len 1 gt0_val_chan_bond_seq_1_1 00000000 gt0_val_chan_bond_seq_1_1_k false gt0_val_chan_bond_seq_1_1_disp false gt0_val_chan_bond_seq_1_1_mask false gt0_val_chan_bond_seq_1_2 00000000 gt0_val_chan_bond_seq_1_2_k false gt0_val_chan_bond_seq_1_2_disp false gt0_val_chan_bond_seq_1_2_mask false gt0_val_chan_bond_seq_1_3 00000000 gt0_val_chan_bond_seq_1_3_k false gt0_val_chan_bond_seq_1_3_disp false gt0_val_chan_bond_seq_1_3_mask false gt0_val_chan_bond_seq_1_4 00000000 gt0_val_chan_bond_seq_1_4_k false gt0_val_chan_bond_seq_1_4_disp false gt0_val_chan_bond_seq_1_4_mask false gt0_val_chan_bond_seq_2_1 00000000 gt0_val_chan_bond_seq_2_1_k false gt0_val_chan_bond_seq_2_1_disp false gt0_val_chan_bond_seq_2_1_mask false gt0_val_chan_bond_seq_2_2 00000000 gt0_val_chan_bond_seq_2_2_k false gt0_val_chan_bond_seq_2_2_disp false gt0_val_chan_bond_seq_2_2_mask false gt0_val_chan_bond_seq_2_3 00000000 gt0_val_chan_bond_seq_2_3_k false gt0_val_chan_bond_seq_2_3_disp false gt0_val_chan_bond_seq_2_3_mask false gt0_val_chan_bond_seq_2_4 00000000 gt0_val_chan_bond_seq_2_4_k false gt0_val_chan_bond_seq_2_4_disp false gt0_val_chan_bond_seq_2_4_mask false gt0_val_clk_cor_seq_1_1_mask false gt0_val_clk_cor_seq_1_1 0100000000 gt0_val_clk_cor_seq_1_1_k false gt0_val_clk_cor_seq_1_1_disp false gt0_val_clk_cor_seq_1_2_mask false gt0_val_clk_cor_seq_1_2 0000000000 gt0_val_clk_cor_seq_1_2_k false gt0_val_clk_cor_seq_1_2_disp false gt0_val_clk_cor_seq_1_3_mask false gt0_val_clk_cor_seq_1_3 0000000000 gt0_val_clk_cor_seq_1_3_k false gt0_val_clk_cor_seq_1_3_disp false gt0_val_clk_cor_seq_1_4_mask false gt0_val_clk_cor_seq_1_4 0000000000 gt0_val_clk_cor_seq_1_4_k false gt0_val_clk_cor_seq_1_4_disp false gt0_val_clk_cor_seq_2_1_mask false gt0_val_clk_cor_seq_2_1 0100000000 gt0_val_clk_cor_seq_2_1_k false gt0_val_clk_cor_seq_2_1_disp false gt0_val_clk_cor_seq_2_2_mask false gt0_val_clk_cor_seq_2_2 0000000000 gt0_val_clk_cor_seq_2_2_k false gt0_val_clk_cor_seq_2_2_disp false gt0_val_clk_cor_seq_2_3_mask false gt0_val_clk_cor_seq_2_3 0000000000 gt0_val_clk_cor_seq_2_3_k false gt0_val_clk_cor_seq_2_3_disp false gt0_val_clk_cor_seq_2_4_mask false gt0_val_clk_cor_seq_2_4 0000000000 gt0_val_clk_cor_seq_2_4_k false gt0_val_clk_cor_seq_2_4_disp false gt0_val_rxslide_mode Gt0 Val Rxslide Mode OFF gt0_val_max_cb_level 7 gt0_val_port_txoutclk true gt0_val_port_rxoutclk true gt0_pll0_fbdiv 1 gt0_pll0_fbdiv_45 4 gt0_pll0_refclk_div 1 gt0_pll0_txout_div 1 gt0_pll0_rxout_div 1 gt0_pll1_fbdiv 1 gt0_pll1_fbdiv_45 4 gt0_pll1_refclk_div 1 gt0_pll1_txout_div 1 gt0_pll1_rxout_div 1 gt_row bottom_row gt0_val_port_pll0pd false gt0_val_port_pll1pd false gtz_selection GTZ0 octal0_val true octal1_val false octal0_val_identical_config true octal0_val_multi_channel_mode OFF octal0_val_master_slave false use_gtz0 true use_gtz1 true use_gtz2 true use_gtz3 true use_gtz4 true use_gtz5 true use_gtz6 true use_gtz7 true octal0_val_identical_protocol_file Start_from_scratch gtz0_val_protocol_file Start_from_scratch gtz1_val_protocol_file Start_from_scratch gtz2_val_protocol_file Start_from_scratch gtz3_val_protocol_file Start_from_scratch gtz4_val_protocol_file Start_from_scratch gtz5_val_protocol_file Start_from_scratch gtz6_val_protocol_file Start_from_scratch gtz7_val_protocol_file Start_from_scratch octal0_val_identical_tx_line_rate 25.78125 gtz0_val_tx_line_rate 25.78125 gtz1_val_tx_line_rate 25.78125 gtz2_val_tx_line_rate 25.78125 gtz3_val_tx_line_rate 25.78125 gtz4_val_tx_line_rate 25.78125 gtz5_val_tx_line_rate 25.78125 gtz6_val_tx_line_rate 25.78125 gtz7_val_tx_line_rate 25.78125 octal0_val_identical_no_tx false gtz0_val_no_tx false gtz1_val_no_tx false gtz2_val_no_tx false gtz3_val_no_tx false gtz4_val_no_tx false gtz5_val_no_tx false gtz6_val_no_tx false gtz7_val_no_tx false octal0_val_identical_rx_line_rate 25.78125 gtz0_val_rx_line_rate 25.78125 gtz1_val_rx_line_rate 25.78125 gtz2_val_rx_line_rate 25.78125 gtz3_val_rx_line_rate 25.78125 gtz4_val_rx_line_rate 25.78125 gtz5_val_rx_line_rate 25.78125 gtz6_val_rx_line_rate 25.78125 gtz7_val_rx_line_rate 25.78125 octal0_val_identical_no_rx false gtz0_val_no_rx false gtz1_val_no_rx false gtz2_val_no_rx false gtz3_val_no_rx false gtz4_val_no_rx false gtz5_val_no_rx false gtz6_val_no_rx false gtz7_val_no_rx false octal0_val_identical_refclk_source REFCLK0 gtz0_val_refclk_source REFCLK0 gtz1_val_refclk_source REFCLK0 gtz2_val_refclk_source REFCLK0 gtz3_val_refclk_source REFCLK0 gtz4_val_refclk_source REFCLK0 gtz5_val_refclk_source REFCLK0 gtz6_val_refclk_source REFCLK0 gtz7_val_refclk_source REFCLK0 octal0_val_refclk0 322.266 octal0_val_refclk1 322.266 octal0_val_txoutclk0_source TXOUTCLK_LANE0 octal0_val_txoutclk1_source TXOUTCLK_LANE0 octal0_val_rxoutclk0_source RXOUTCLK_LANE0 octal0_val_rxoutclk1_source RXOUTCLK_LANE0 octal0_val_rxoutclk2_source RXOUTCLK_LANE0 octal0_val_rxoutclk3_source RXOUTCLK_LANE0 octal0_val_drpclk_source DRPCLK0 gtz0_val_txoutclk_source TX_FIFO_CLK gtz1_val_txoutclk_source TX_FIFO_CLK gtz2_val_txoutclk_source TX_FIFO_CLK gtz3_val_txoutclk_source TX_FIFO_CLK gtz4_val_txoutclk_source TX_FIFO_CLK gtz5_val_txoutclk_source TX_FIFO_CLK gtz6_val_txoutclk_source TX_FIFO_CLK gtz7_val_txoutclk_source TX_FIFO_CLK gtz0_val_rxoutclk_source RX_FIFO_CLK gtz1_val_rxoutclk_source RX_FIFO_CLK gtz2_val_rxoutclk_source RX_FIFO_CLK gtz3_val_rxoutclk_source RX_FIFO_CLK gtz4_val_rxoutclk_source RX_FIFO_CLK gtz5_val_rxoutclk_source RX_FIFO_CLK gtz6_val_rxoutclk_source RX_FIFO_CLK gtz7_val_rxoutclk_source RX_FIFO_CLK octal0_val_txusrclk0_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk1_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk2_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk3_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk4_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk5_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk6_source OCTAL0_TXOUTCLK0 octal0_val_txusrclk7_source OCTAL0_TXOUTCLK0 octal0_val_rxusrclk0_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk1_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk2_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk3_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk4_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk5_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk6_source OCTAL0_RXOUTCLK0 octal0_val_rxusrclk7_source OCTAL0_RXOUTCLK0 gtz0_val_txusrclk_source TXUSRCLK0 gtz1_val_txusrclk_source TXUSRCLK0 gtz2_val_txusrclk_source TXUSRCLK0 gtz3_val_txusrclk_source TXUSRCLK0 gtz4_val_txusrclk_source TXUSRCLK0 gtz5_val_txusrclk_source TXUSRCLK0 gtz6_val_txusrclk_source TXUSRCLK0 gtz7_val_txusrclk_source TXUSRCLK0 gtz0_val_rxusrclk_source RXUSRCLK0 gtz1_val_rxusrclk_source RXUSRCLK0 gtz2_val_rxusrclk_source RXUSRCLK0 gtz3_val_rxusrclk_source RXUSRCLK0 gtz4_val_rxusrclk_source RXUSRCLK0 gtz5_val_rxusrclk_source RXUSRCLK0 gtz6_val_rxusrclk_source RXUSRCLK0 gtz7_val_rxusrclk_source RXUSRCLK0 gtz0_val_data_width 160 gtz1_val_data_width 160 gtz2_val_data_width 160 gtz3_val_data_width 160 gtz4_val_data_width 160 gtz5_val_data_width 160 gtz6_val_data_width 160 gtz7_val_data_width 160 gtz0_val_encoding 100GBASER_MODE gtz1_val_encoding 100GBASER_MODE gtz2_val_encoding 100GBASER_MODE gtz3_val_encoding 100GBASER_MODE gtz4_val_encoding 100GBASER_MODE gtz5_val_encoding 100GBASER_MODE gtz6_val_encoding 100GBASER_MODE gtz7_val_encoding 100GBASER_MODE gtz0_val_port_txfibreset false gtz0_val_port_txfifostatus false gtz0_val_port_txratesel false gtz0_val_port_txen false gtz0_val_port_txpolarity false gtz0_val_port_txoutputen false gtz0_val_port_txeqpostctrl false gtz0_val_port_txeqprectrl false gtz0_val_port_txslewctrl false gtz0_val_port_txattnctrl false gtz0_val_port_rxfibreset false gtz0_val_port_rxfifostatus false gtz0_val_port_rxratesel false gtz0_val_port_rxpolarity false gtz0_val_port_rxen false gtz0_val_port_rxsignalok false gtz0_val_port_rxbitslip false gtz0_val_port_refsel false gtz0_val_port_corecntl false gtz0_val_port_pllrecalen false gtz0_val_port_loopback false gtz0_val_port_txprbs false gtz0_val_port_rxprbs false gt0_uselabtools true gt0_usesharedlogic 0 gt0_val_port_clkrsvd false gt0_val_port_tx8b10ben false gt0_val_port_sigvalidclk false gt0_val_port_txpippmen false gt0_val_port_txpippmpd false gt0_val_port_txpippmovrden false gt0_val_port_txpippmsel false gt0_val_port_txpippmstepsize false prbs_gen_check false example_chipscope 0 tdlock_time 1000 gt_val_extended_timeout false true 7 Series FPGAs Transceivers Wizard 11 2019.2