xilinx.com customized_ip ttc_header_fifo 1.0 M_AXIS TDATA m_axis_tdata TDEST m_axis_tdest TID m_axis_tid TKEEP m_axis_tkeep TLAST m_axis_tlast TREADY m_axis_tready TSTRB m_axis_tstrb TUSER m_axis_tuser TVALID m_axis_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false S_AXIS TDATA s_axis_tdata TDEST s_axis_tdest TID s_axis_tid TKEEP s_axis_tkeep TLAST s_axis_tlast TREADY s_axis_tready TSTRB s_axis_tstrb TUSER s_axis_tuser TVALID s_axis_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false S_AXI ARADDR s_axi_araddr ARBURST s_axi_arburst ARCACHE s_axi_arcache ARID s_axi_arid ARLEN s_axi_arlen ARLOCK s_axi_arlock ARPROT s_axi_arprot ARQOS s_axi_arqos ARREADY s_axi_arready ARREGION s_axi_arregion ARSIZE s_axi_arsize ARUSER s_axi_aruser ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWBURST s_axi_awburst AWCACHE s_axi_awcache AWID s_axi_awid AWLEN s_axi_awlen AWLOCK s_axi_awlock AWPROT s_axi_awprot AWQOS s_axi_awqos AWREADY s_axi_awready AWREGION s_axi_awregion AWSIZE s_axi_awsize AWUSER s_axi_awuser AWVALID s_axi_awvalid BID s_axi_bid BREADY s_axi_bready BRESP s_axi_bresp BUSER s_axi_buser BVALID s_axi_bvalid RDATA s_axi_rdata RID s_axi_rid RLAST s_axi_rlast RREADY s_axi_rready RRESP s_axi_rresp RUSER s_axi_ruser RVALID s_axi_rvalid WDATA s_axi_wdata WID s_axi_wid WLAST s_axi_wlast WREADY s_axi_wready WSTRB s_axi_wstrb WUSER s_axi_wuser WVALID s_axi_wvalid BD_ATTRIBUTE.TYPE INTERIOR DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false M_AXI ARADDR m_axi_araddr ARBURST m_axi_arburst ARCACHE m_axi_arcache ARID m_axi_arid ARLEN m_axi_arlen ARLOCK m_axi_arlock ARPROT m_axi_arprot ARQOS m_axi_arqos ARREADY m_axi_arready ARREGION m_axi_arregion ARSIZE m_axi_arsize ARUSER m_axi_aruser ARVALID m_axi_arvalid AWADDR m_axi_awaddr AWBURST m_axi_awburst AWCACHE m_axi_awcache AWID m_axi_awid AWLEN m_axi_awlen AWLOCK m_axi_awlock AWPROT m_axi_awprot AWQOS m_axi_awqos AWREADY m_axi_awready AWREGION m_axi_awregion AWSIZE m_axi_awsize AWUSER m_axi_awuser AWVALID m_axi_awvalid BID m_axi_bid BREADY m_axi_bready BRESP m_axi_bresp BUSER m_axi_buser BVALID m_axi_bvalid RDATA m_axi_rdata RID m_axi_rid RLAST m_axi_rlast RREADY m_axi_rready RRESP m_axi_rresp RUSER m_axi_ruser RVALID m_axi_rvalid WDATA m_axi_wdata WID m_axi_wid WLAST m_axi_wlast WREADY m_axi_wready WSTRB m_axi_wstrb WUSER m_axi_wuser WVALID m_axi_wvalid DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false core_clk CLK clk FREQ_HZ clock frequency specify frequency of the clock connected to port clk 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false master_aclk CLK m_aclk ASSOCIATED_BUSIF M_AXIS:M_AXI FREQ_HZ m_aclk frequency specify frequency of the clock connected to port m_aclk 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false slave_aclk CLK s_aclk ASSOCIATED_BUSIF S_AXIS:S_AXI ASSOCIATED_RESET s_aresetn FREQ_HZ s_aclk frequency specify frequency of the clock connected to port m_aclk 100000000 PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl false write_clk CLK wr_clk FREQ_HZ write clock frequency specify frequency of the clock connected to port wr_clk 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true read_clk CLK rd_clk FREQ_HZ read clock frequency specify frequency of the clock connected to port rd_clk 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true slave_aresetn RST s_aresetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl false FIFO_WRITE FIFO_WRITE ALMOST_FULL almost_full FULL full WR_DATA din WR_EN wr_en true FIFO_READ FIFO_READ ALMOST_EMPTY almost_empty EMPTY empty RD_DATA dout RD_EN rd_en true xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl fifo_generator_v13_2_5 xilinx_vhdlsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset xilinx_vhdlsynthesis_view_fileset GENtimestamp Mon May 04 20:57:28 UTC 2020 outputProductCRC 9:5d892ae7 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints xilinx_synthesisconstraints_view_fileset GENtimestamp Mon May 04 20:57:28 UTC 2020 outputProductCRC 9:5d892ae7 xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl ttc_header_fifo xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:57:28 UTC 2020 outputProductCRC 9:5d892ae7 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:57:03 UTC 2020 outputProductCRC 9:5d892ae7 backup in std_logic xilinx_vhdlsynthesis 0 false backup_marker in std_logic xilinx_vhdlsynthesis 0 false clk in std_logic xilinx_vhdlsynthesis 0 false rst in std_logic xilinx_vhdlsynthesis 0 true srst in std_logic xilinx_vhdlsynthesis 0 false wr_clk in std_logic xilinx_vhdlsynthesis 0 true wr_rst in std_logic xilinx_vhdlsynthesis 0 false rd_clk in std_logic xilinx_vhdlsynthesis 0 true rd_rst in std_logic xilinx_vhdlsynthesis 0 false din in 63 0 std_logic_vector xilinx_vhdlsynthesis 0 true wr_en in std_logic xilinx_vhdlsynthesis 0 true rd_en in std_logic xilinx_vhdlsynthesis 0 true prog_empty_thresh in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_empty_thresh_assert in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_empty_thresh_negate in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_full_thresh in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_full_thresh_assert in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_full_thresh_negate in 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false int_clk in std_logic xilinx_vhdlsynthesis 0 false injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false sleep in std_logic xilinx_vhdlsynthesis 0 false dout out 63 0 std_logic_vector xilinx_vhdlsynthesis 0 true full out std_logic xilinx_vhdlsynthesis 0x0 true almost_full out std_logic xilinx_vhdlsynthesis 0x0 true wr_ack out std_logic xilinx_vhdlsynthesis 0x0 false overflow out std_logic xilinx_vhdlsynthesis 0x0 false empty out std_logic xilinx_vhdlsynthesis 0x1 true almost_empty out std_logic xilinx_vhdlsynthesis 0x1 false valid out std_logic xilinx_vhdlsynthesis 0x0 true underflow out std_logic xilinx_vhdlsynthesis 0x0 true data_count out 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false rd_data_count out 8 0 std_logic_vector xilinx_vhdlsynthesis 0 true wr_data_count out 8 0 std_logic_vector xilinx_vhdlsynthesis 0 false prog_full out std_logic xilinx_vhdlsynthesis 0x0 false prog_empty out std_logic xilinx_vhdlsynthesis 0x1 false sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false wr_rst_busy out std_logic xilinx_vhdlsynthesis 0 false rd_rst_busy out std_logic xilinx_vhdlsynthesis 0 false m_aclk in std_logic xilinx_vhdlsynthesis 0 false s_aclk in std_logic xilinx_vhdlsynthesis 0 false s_aresetn in std_logic xilinx_vhdlsynthesis 0 false m_aclk_en in std_logic xilinx_vhdlsynthesis 0 false s_aclk_en in std_logic xilinx_vhdlsynthesis 0 false s_axi_awid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awaddr in 31 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awlen in 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awsize in 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awburst in 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awlock in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awcache in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awprot in 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awqos in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awregion in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awuser in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_awvalid in std_logic xilinx_vhdlsynthesis 0 false s_axi_awready out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_wid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_wdata in 63 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_wstrb in 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_wlast in std_logic xilinx_vhdlsynthesis 0 false s_axi_wuser in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_wvalid in std_logic xilinx_vhdlsynthesis 0 false s_axi_wready out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_bid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_bresp out 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_buser out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_bvalid out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_bready in std_logic xilinx_vhdlsynthesis 0 false m_axi_awid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awaddr out 31 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awlen out 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awsize out 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awburst out 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awlock out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awcache out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awprot out 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awqos out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awregion out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awuser out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_awvalid out std_logic xilinx_vhdlsynthesis 0x0 false m_axi_awready in std_logic xilinx_vhdlsynthesis 0 false m_axi_wid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_wdata out 63 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_wstrb out 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_wlast out std_logic xilinx_vhdlsynthesis 0x0 false m_axi_wuser out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_wvalid out std_logic xilinx_vhdlsynthesis 0x0 false m_axi_wready in std_logic xilinx_vhdlsynthesis 0 false m_axi_bid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_bresp in 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_buser in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_bvalid in std_logic xilinx_vhdlsynthesis 0 false m_axi_bready out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_arid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_araddr in 31 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arlen in 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arsize in 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arburst in 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arlock in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arcache in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arprot in 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arqos in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arregion in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_aruser in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_arvalid in std_logic xilinx_vhdlsynthesis 0 false s_axi_arready out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_rid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_rdata out 63 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_rresp out 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_rlast out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_ruser out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axi_rvalid out std_logic xilinx_vhdlsynthesis 0x0 false s_axi_rready in std_logic xilinx_vhdlsynthesis 0 false m_axi_arid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_araddr out 31 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arlen out 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arsize out 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arburst out 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arlock out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arcache out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arprot out 2 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arqos out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arregion out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_aruser out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_arvalid out std_logic xilinx_vhdlsynthesis 0x0 false m_axi_arready in std_logic xilinx_vhdlsynthesis 0 false m_axi_rid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_rdata in 63 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_rresp in 1 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_rlast in std_logic xilinx_vhdlsynthesis 0 false m_axi_ruser in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axi_rvalid in std_logic xilinx_vhdlsynthesis 0 false m_axi_rready out std_logic xilinx_vhdlsynthesis 0x0 false s_axis_tvalid in std_logic xilinx_vhdlsynthesis 0 false s_axis_tready out std_logic xilinx_vhdlsynthesis 0x0 false s_axis_tdata in 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axis_tstrb in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axis_tkeep in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axis_tlast in std_logic xilinx_vhdlsynthesis 0 false s_axis_tid in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axis_tdest in 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false s_axis_tuser in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tvalid out std_logic xilinx_vhdlsynthesis 0x0 false m_axis_tready in std_logic xilinx_vhdlsynthesis 0 false m_axis_tdata out 7 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tstrb out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tkeep out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tlast out std_logic xilinx_vhdlsynthesis 0x0 false m_axis_tid out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tdest out 0 0 std_logic_vector xilinx_vhdlsynthesis 0 false m_axis_tuser out 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_aw_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_aw_prog_full_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_prog_empty_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_wr_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_rd_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_aw_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_aw_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_aw_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_aw_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_aw_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axi_aw_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false axi_w_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_w_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_w_prog_full_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_w_prog_empty_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_w_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_w_wr_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_w_rd_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_w_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_w_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_w_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_w_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_w_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axi_w_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false axi_b_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_b_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_b_prog_full_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_b_prog_empty_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_b_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_b_wr_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_b_rd_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_b_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_b_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_b_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_b_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_b_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axi_b_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false axi_ar_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_ar_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_ar_prog_full_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_ar_prog_empty_thresh in 3 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_ar_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_ar_wr_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_ar_rd_data_count out 4 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_ar_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_ar_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_ar_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_ar_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_ar_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axi_ar_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false axi_r_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_r_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axi_r_prog_full_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_r_prog_empty_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_r_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_r_wr_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_r_rd_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axi_r_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_r_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axi_r_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_r_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axi_r_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axi_r_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false axis_injectsbiterr in std_logic xilinx_vhdlsynthesis 0 false axis_injectdbiterr in std_logic xilinx_vhdlsynthesis 0 false axis_prog_full_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axis_prog_empty_thresh in 9 0 std_logic_vector xilinx_vhdlsynthesis 0 false axis_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axis_wr_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axis_rd_data_count out 10 0 std_logic_vector xilinx_vhdlsynthesis 0 false axis_sbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axis_dbiterr out std_logic xilinx_vhdlsynthesis 0x0 false axis_overflow out std_logic xilinx_vhdlsynthesis 0x0 false axis_underflow out std_logic xilinx_vhdlsynthesis 0x0 false axis_prog_full out STD_LOGIC xilinx_vhdlsynthesis 0 false axis_prog_empty out STD_LOGIC xilinx_vhdlsynthesis 1 false C_COMMON_CLOCK 0 C_SELECT_XPM 0 C_COUNT_TYPE 0 C_DATA_COUNT_WIDTH 9 C_DEFAULT_VALUE BlankString C_DIN_WIDTH 64 C_DOUT_RST_VAL 0 C_DOUT_WIDTH 64 C_ENABLE_RLOCS 0 C_FAMILY virtex7 C_FULL_FLAGS_RST_VAL 1 C_HAS_ALMOST_EMPTY 0 C_HAS_ALMOST_FULL 1 C_HAS_BACKUP 0 C_HAS_DATA_COUNT 0 C_HAS_INT_CLK 0 C_HAS_MEMINIT_FILE 0 C_HAS_OVERFLOW 0 C_HAS_RD_DATA_COUNT 1 C_HAS_RD_RST 0 C_HAS_RST 1 C_HAS_SRST 0 C_HAS_UNDERFLOW 1 C_HAS_VALID 1 C_HAS_WR_ACK 0 C_HAS_WR_DATA_COUNT 0 C_HAS_WR_RST 0 C_IMPLEMENTATION_TYPE 2 C_INIT_WR_PNTR_VAL 0 C_MEMORY_TYPE 2 C_MIF_FILE_NAME BlankString C_OPTIMIZATION_MODE 0 C_OVERFLOW_LOW 0 C_PRELOAD_LATENCY 0 C_PRELOAD_REGS 1 C_PRIM_FIFO_TYPE 512x72 C_PROG_EMPTY_THRESH_ASSERT_VAL 4 C_PROG_EMPTY_THRESH_NEGATE_VAL 5 C_PROG_EMPTY_TYPE 0 C_PROG_FULL_THRESH_ASSERT_VAL 511 C_PROG_FULL_THRESH_NEGATE_VAL 510 C_PROG_FULL_TYPE 0 C_RD_DATA_COUNT_WIDTH 9 C_RD_DEPTH 512 C_RD_FREQ 1 C_RD_PNTR_WIDTH 9 C_UNDERFLOW_LOW 0 C_USE_DOUT_RST 1 C_USE_ECC 0 C_USE_EMBEDDED_REG 0 C_USE_PIPELINE_REG 0 C_POWER_SAVING_MODE 0 C_USE_FIFO16_FLAGS 0 C_USE_FWFT_DATA_COUNT 0 C_VALID_LOW 0 C_WR_ACK_LOW 0 C_WR_DATA_COUNT_WIDTH 9 C_WR_DEPTH 512 C_WR_FREQ 1 C_WR_PNTR_WIDTH 9 C_WR_RESPONSE_LATENCY 1 C_MSGON_VAL 1 C_ENABLE_RST_SYNC 1 C_EN_SAFETY_CKT 0 C_ERROR_INJECTION_TYPE 0 C_SYNCHRONIZER_STAGE 2 C_INTERFACE_TYPE 0 C_AXI_TYPE 1 C_HAS_AXI_WR_CHANNEL 1 C_HAS_AXI_RD_CHANNEL 1 C_HAS_SLAVE_CE 0 C_HAS_MASTER_CE 0 C_ADD_NGC_CONSTRAINT 0 C_USE_COMMON_OVERFLOW 0 C_USE_COMMON_UNDERFLOW 0 C_USE_DEFAULT_SETTINGS 0 C_AXI_ID_WIDTH 1 C_AXI_ADDR_WIDTH 32 C_AXI_DATA_WIDTH 64 C_AXI_LEN_WIDTH 8 C_AXI_LOCK_WIDTH 1 C_HAS_AXI_ID 0 C_HAS_AXI_AWUSER 0 C_HAS_AXI_WUSER 0 C_HAS_AXI_BUSER 0 C_HAS_AXI_ARUSER 0 C_HAS_AXI_RUSER 0 C_AXI_ARUSER_WIDTH 1 C_AXI_AWUSER_WIDTH 1 C_AXI_WUSER_WIDTH 1 C_AXI_BUSER_WIDTH 1 C_AXI_RUSER_WIDTH 1 C_HAS_AXIS_TDATA 1 C_HAS_AXIS_TID 0 C_HAS_AXIS_TDEST 0 C_HAS_AXIS_TUSER 1 C_HAS_AXIS_TREADY 1 C_HAS_AXIS_TLAST 0 C_HAS_AXIS_TSTRB 0 C_HAS_AXIS_TKEEP 0 C_AXIS_TDATA_WIDTH 8 C_AXIS_TID_WIDTH 1 C_AXIS_TDEST_WIDTH 1 C_AXIS_TUSER_WIDTH 4 C_AXIS_TSTRB_WIDTH 1 C_AXIS_TKEEP_WIDTH 1 C_WACH_TYPE 0 C_WDCH_TYPE 0 C_WRCH_TYPE 0 C_RACH_TYPE 0 C_RDCH_TYPE 0 C_AXIS_TYPE 0 C_IMPLEMENTATION_TYPE_WACH 1 C_IMPLEMENTATION_TYPE_WDCH 1 C_IMPLEMENTATION_TYPE_WRCH 1 C_IMPLEMENTATION_TYPE_RACH 1 C_IMPLEMENTATION_TYPE_RDCH 1 C_IMPLEMENTATION_TYPE_AXIS 1 C_APPLICATION_TYPE_WACH 0 C_APPLICATION_TYPE_WDCH 0 C_APPLICATION_TYPE_WRCH 0 C_APPLICATION_TYPE_RACH 0 C_APPLICATION_TYPE_RDCH 0 C_APPLICATION_TYPE_AXIS 0 C_PRIM_FIFO_TYPE_WACH 512x36 C_PRIM_FIFO_TYPE_WDCH 1kx36 C_PRIM_FIFO_TYPE_WRCH 512x36 C_PRIM_FIFO_TYPE_RACH 512x36 C_PRIM_FIFO_TYPE_RDCH 1kx36 C_PRIM_FIFO_TYPE_AXIS 1kx18 C_USE_ECC_WACH 0 C_USE_ECC_WDCH 0 C_USE_ECC_WRCH 0 C_USE_ECC_RACH 0 C_USE_ECC_RDCH 0 C_USE_ECC_AXIS 0 C_ERROR_INJECTION_TYPE_WACH 0 C_ERROR_INJECTION_TYPE_WDCH 0 C_ERROR_INJECTION_TYPE_WRCH 0 C_ERROR_INJECTION_TYPE_RACH 0 C_ERROR_INJECTION_TYPE_RDCH 0 C_ERROR_INJECTION_TYPE_AXIS 0 C_DIN_WIDTH_WACH 1 C_DIN_WIDTH_WDCH 64 C_DIN_WIDTH_WRCH 2 C_DIN_WIDTH_RACH 32 C_DIN_WIDTH_RDCH 64 C_DIN_WIDTH_AXIS 1 C_WR_DEPTH_WACH 16 C_WR_DEPTH_WDCH 1024 C_WR_DEPTH_WRCH 16 C_WR_DEPTH_RACH 16 C_WR_DEPTH_RDCH 1024 C_WR_DEPTH_AXIS 1024 C_WR_PNTR_WIDTH_WACH 4 C_WR_PNTR_WIDTH_WDCH 10 C_WR_PNTR_WIDTH_WRCH 4 C_WR_PNTR_WIDTH_RACH 4 C_WR_PNTR_WIDTH_RDCH 10 C_WR_PNTR_WIDTH_AXIS 10 C_HAS_DATA_COUNTS_WACH 0 C_HAS_DATA_COUNTS_WDCH 0 C_HAS_DATA_COUNTS_WRCH 0 C_HAS_DATA_COUNTS_RACH 0 C_HAS_DATA_COUNTS_RDCH 0 C_HAS_DATA_COUNTS_AXIS 0 C_HAS_PROG_FLAGS_WACH 0 C_HAS_PROG_FLAGS_WDCH 0 C_HAS_PROG_FLAGS_WRCH 0 C_HAS_PROG_FLAGS_RACH 0 C_HAS_PROG_FLAGS_RDCH 0 C_HAS_PROG_FLAGS_AXIS 0 C_PROG_FULL_TYPE_WACH 0 C_PROG_FULL_TYPE_WDCH 0 C_PROG_FULL_TYPE_WRCH 0 C_PROG_FULL_TYPE_RACH 0 C_PROG_FULL_TYPE_RDCH 0 C_PROG_FULL_TYPE_AXIS 0 C_PROG_FULL_THRESH_ASSERT_VAL_WACH 1023 C_PROG_FULL_THRESH_ASSERT_VAL_WDCH 1023 C_PROG_FULL_THRESH_ASSERT_VAL_WRCH 1023 C_PROG_FULL_THRESH_ASSERT_VAL_RACH 1023 C_PROG_FULL_THRESH_ASSERT_VAL_RDCH 1023 C_PROG_FULL_THRESH_ASSERT_VAL_AXIS 1023 C_PROG_EMPTY_TYPE_WACH 0 C_PROG_EMPTY_TYPE_WDCH 0 C_PROG_EMPTY_TYPE_WRCH 0 C_PROG_EMPTY_TYPE_RACH 0 C_PROG_EMPTY_TYPE_RDCH 0 C_PROG_EMPTY_TYPE_AXIS 0 C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH 1022 C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH 1022 C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH 1022 C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH 1022 C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH 1022 C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS 1022 C_REG_SLICE_MODE_WACH 0 C_REG_SLICE_MODE_WDCH 0 C_REG_SLICE_MODE_WRCH 0 C_REG_SLICE_MODE_RACH 0 C_REG_SLICE_MODE_RDCH 0 C_REG_SLICE_MODE_AXIS 0 choice_list_087d29fa 0 1 2 4 8 16 32 64 128 256 512 choice_list_165ed04b 64 choice_list_6727dfa6 1 0 choice_list_89b1ac3c 64 8 16 32 64 128 256 512 choice_list_8af5a703 0 1 choice_list_bf1143fa 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 choice_pairs_0721dec1 No_Programmable_Empty_Threshold Single_Programmable_Empty_Threshold_Constant Multiple_Programmable_Empty_Threshold_Constants Single_Programmable_Empty_Threshold_Input_Port Multiple_Programmable_Empty_Threshold_Input_Ports choice_pairs_08e28d5f Active_High Active_Low choice_pairs_26bda4ef Asynchronous_Reset choice_pairs_2d5d8925 Common_Clock_Block_RAM Common_Clock_Distributed_RAM Common_Clock_Shift_Register Common_Clock_Builtin_FIFO Independent_Clocks_Block_RAM Independent_Clocks_Distributed_RAM Independent_Clocks_Builtin_FIFO choice_pairs_3c123ec0 Common_Clock_Block_RAM Common_Clock_Distributed_RAM choice_pairs_53eba4dc Native AXI_MEMORY_MAPPED AXI_STREAM choice_pairs_541ed8d9 Embedded_Reg Fabric_Reg Both choice_pairs_5548b404 Common_Clock Independent_Clock choice_pairs_5f1451ad Standard_FIFO First_Word_Fall_Through choice_pairs_619f3529 AXI4 AXI3 AXI4_Lite choice_pairs_8334cf20 Data_FIFO Packet_FIFO Low_Latency_Data_FIFO choice_pairs_88535724 No_Programmable_Full_Threshold Single_Programmable_Full_Threshold_Constant Multiple_Programmable_Full_Threshold_Constants Single_Programmable_Full_Threshold_Input_Port Multiple_Programmable_Full_Threshold_Input_Ports choice_pairs_9b232fe1 Slave_Interface_Clock_Enable Master_Interface_Clock_Enable choice_pairs_a8c5818a Fully_Registered Light_Weight choice_pairs_b3e9d19b FIFO Register_Slice Pass_Through_Wire choice_pairs_bec132cf FIFO Register_Slice choice_pairs_c94a1851 Hard_ECC Soft_ECC choice_pairs_ccb14e2b READ_WRITE READ_ONLY WRITE_ONLY choice_pairs_eb98f74b No_Programmable_Empty_Threshold Single_Programmable_Empty_Threshold_Constant Single_Programmable_Empty_Threshold_Input_Port choice_pairs_ec2b452f No_Programmable_Full_Threshold Single_Programmable_Full_Threshold_Constant Single_Programmable_Full_Threshold_Input_Port xilinx_vhdlsynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd vhdlSource blk_mem_gen_v8_4_4 xilinx_vhdlsynthesis_view_fileset ttc_header_fifo.xdc xdc ttc_header_fifo_clocks.xdc xdc processing_order late hdl/fifo_generator_v13_2_vhsyn_rfs.vhd vhdlSource fifo_generator_v13_2_5 xilinx_synthesisconstraints_view_fileset ttc_header_fifo_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis xilinx_vhdlsynthesiswrapper_view_fileset synth/ttc_header_fifo.vhd vhdlSource xil_defaultlib xilinx_externalfiles_view_fileset ttc_header_fifo.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib ttc_header_fifo_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib ttc_header_fifo_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib ttc_header_fifo_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib ttc_header_fifo_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. Component_Name ttc_header_fifo true Fifo_Implementation Independent_Clocks_Distributed_RAM true synchronization_stages 2 true synchronization_stages_axi 2 true INTERFACE_TYPE Native true Performance_Options First_Word_Fall_Through true asymmetric_port_width false false Input_Data_Width 64 true Input_Depth 512 true Output_Data_Width 64 false Output_Depth 512 false Enable_ECC false false Use_Embedded_Registers false false Reset_Pin true true Enable_Reset_Synchronization true true Reset_Type Asynchronous_Reset false Full_Flags_Reset_Value 1 true Use_Dout_Reset true true Dout_Reset_Value 0 true dynamic_power_saving false false Almost_Full_Flag true true Almost_Empty_Flag false true Valid_Flag true true Valid_Sense Active_High true Underflow_Flag true true Underflow_Sense Active_High true Write_Acknowledge_Flag false true Write_Acknowledge_Sense Active_High false Overflow_Flag false true Overflow_Sense Active_High false Inject_Sbit_Error false false Inject_Dbit_Error false false ecc_pipeline_reg false false Use_Extra_Logic false true Data_Count false false Data_Count_Width 9 false Write_Data_Count false true Write_Data_Count_Width 9 false Read_Data_Count true true Read_Data_Count_Width 9 true Disable_Timing_Violations false true Read_Clock_Frequency 1 false Write_Clock_Frequency 1 false Programmable_Full_Type No_Programmable_Full_Threshold true Full_Threshold_Assert_Value 511 false Full_Threshold_Negate_Value 510 false Programmable_Empty_Type No_Programmable_Empty_Threshold true Empty_Threshold_Assert_Value 4 false Empty_Threshold_Negate_Value 5 false PROTOCOL AXI4 false Clock_Type_AXI Common_Clock true HAS_ACLKEN false false Clock_Enable_Type Slave_Interface_Clock_Enable false READ_WRITE_MODE READ_WRITE true ID_WIDTH 0 false ADDRESS_WIDTH 32 false DATA_WIDTH 64 false AWUSER_Width 0 false WUSER_Width 0 false BUSER_Width 0 false ARUSER_Width 0 false RUSER_Width 0 false TDATA_NUM_BYTES 1 true TID_WIDTH 0 false TDEST_WIDTH 0 false TUSER_WIDTH 4 false Enable_TREADY true false Enable_TLAST false true HAS_TSTRB false false TSTRB_WIDTH 1 false HAS_TKEEP false false TKEEP_WIDTH 1 false wach_type Configuration Options FIFO true FIFO_Implementation_wach Common_Clock_Block_RAM true FIFO_Application_Type_wach FIFO Application Type Data_FIFO false Enable_ECC_wach false false Inject_Sbit_Error_wach Single Bit Error Injection false false Inject_Dbit_Error_wach false false Input_Depth_wach 16 true Enable_Data_Counts_wach false false Programmable_Full_Type_wach Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_wach Full Threshold Assert Value 1023 false Programmable_Empty_Type_wach Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_wach Empty Threshold Assert Value 1022 false wdch_type Configuration Options FIFO true FIFO_Implementation_wdch FIFO Implementation Type Common_Clock_Block_RAM true FIFO_Application_Type_wdch FIFO Application Type Data_FIFO false Enable_ECC_wdch false false Inject_Sbit_Error_wdch Single Bit Error Injection false false Inject_Dbit_Error_wdch false false Input_Depth_wdch 1024 true Enable_Data_Counts_wdch false false Programmable_Full_Type_wdch Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_wdch Full Threshold Assert Value 1023 false Programmable_Empty_Type_wdch Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_wdch Empty Threshold Assert Value 1022 false wrch_type Configuration Options FIFO true FIFO_Implementation_wrch FIFO Implementation Type Common_Clock_Block_RAM true FIFO_Application_Type_wrch FIFO Application Type Data_FIFO false Enable_ECC_wrch false false Inject_Sbit_Error_wrch Single Bit Error Injection false false Inject_Dbit_Error_wrch false false Input_Depth_wrch 16 true Enable_Data_Counts_wrch false false Programmable_Full_Type_wrch Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_wrch Full Threshold Assert Value 1023 false Programmable_Empty_Type_wrch Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_wrch Empty Threshold Assert Value 1022 false rach_type Configuration Options FIFO true FIFO_Implementation_rach FIFO Implementation Type Common_Clock_Block_RAM true FIFO_Application_Type_rach FIFO Application Type Data_FIFO false Enable_ECC_rach false false Inject_Sbit_Error_rach Single Bit Error Injection false false Inject_Dbit_Error_rach false false Input_Depth_rach 16 true Enable_Data_Counts_rach false false Programmable_Full_Type_rach Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_rach Full Threshold Assert Value 1023 false Programmable_Empty_Type_rach Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_rach Empty Threshold Assert Value 1022 false rdch_type Configuration Options FIFO true FIFO_Implementation_rdch FIFO Implementation Type Common_Clock_Block_RAM true FIFO_Application_Type_rdch FIFO Application Type Data_FIFO false Enable_ECC_rdch false false Inject_Sbit_Error_rdch Single Bit Error Injection false false Inject_Dbit_Error_rdch false false Input_Depth_rdch 1024 true Enable_Data_Counts_rdch false false Programmable_Full_Type_rdch Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_rdch Full Threshold Assert Value 1023 false Programmable_Empty_Type_rdch Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_rdch Empty Threshold Assert Value 1022 false axis_type Configuration Options FIFO true FIFO_Implementation_axis FIFO Implementation Type Common_Clock_Block_RAM true FIFO_Application_Type_axis FIFO Application Type Data_FIFO false Enable_ECC_axis false false Inject_Sbit_Error_axis Single Bit Error Injection false false Inject_Dbit_Error_axis Double Bit Error Injection false false Input_Depth_axis 1024 true Enable_Data_Counts_axis false false Programmable_Full_Type_axis Deassert READY When No_Programmable_Full_Threshold false Full_Threshold_Assert_Value_axis Full Threshold Assert Value 1023 false Programmable_Empty_Type_axis Deassert VALID When No_Programmable_Empty_Threshold false Empty_Threshold_Assert_Value_axis Empty Threshold Assert Value 1022 false Register_Slice_Mode_wach Register Slice Options Fully_Registered true Register_Slice_Mode_wdch Register Slice Options Fully_Registered true Register_Slice_Mode_wrch Register Slice Options Fully_Registered true Register_Slice_Mode_rach Register Slice Options Fully_Registered true Register_Slice_Mode_rdch Register Slice Options Fully_Registered true Register_Slice_Mode_axis Register Slice Options Fully_Registered true Underflow_Flag_AXI Underflow Flag false true Underflow_Sense_AXI Underflow (Read Error) Active_High true Overflow_Flag_AXI Overflow Flag false true Overflow_Sense_AXI Overflow (Write Error) Active_High true Disable_Timing_Violations_AXI false true Add_NGC_Constraint_AXI false true Enable_Common_Underflow false true Enable_Common_Overflow false true enable_read_pointer_increment_by2 false true Use_Embedded_Registers_axis false false enable_low_latency false false use_dout_register false false Master_interface_Clock_enable_memory_mapped false false Slave_interface_Clock_enable_memory_mapped false false Output_Register_Type Embedded_Reg false Enable_Safety_Circuit false false Enable_ECC_Type Hard_ECC false C_SELECT_XPM 0 FIFO Generator XPM_MEMORY XPM_CDC 5 2019.2