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------------------------------------------------------------------------------/
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_misc.all;
     use IEEE.numeric_std.all;
     use ieee.std_logic_arith.all;
     use ieee.std_logic_unsigned.all;

entity  tx_aurora_1ln_rx is
 port (
    -- AXI TX Interface
    s_axi_tx_tdata         : in  std_logic_vector(31 downto 0);
 
    s_axi_tx_tvalid        : in  std_logic;
    s_axi_tx_tready        : out std_logic;
    s_axi_tx_tkeep         : in std_logic_vector(3 downto 0);
 
    s_axi_tx_tlast         : in  std_logic;



    -- User Flow Control TX Interface
    s_axi_ufc_tx_tvalid    : in std_logic;
    s_axi_ufc_tx_tdata     : in std_logic_vector(2 downto 0);
    s_axi_ufc_tx_tready    : out std_logic;




    txp                    : out std_logic_vector(0 downto 0);
    txn                    : out std_logic_vector(0 downto 0);

    -- GT Reference Clock Interface
    gt_refclk1_p             : in  std_logic;
    gt_refclk1_n             : in  std_logic;
    gt_refclk1_out           : out std_logic;

    -- Error Detection Interface
    tx_hard_err            : out std_logic;
    -- Status
    tx_lane_up             : out std_logic_vector(0 downto 0);
    tx_channel_up          : out std_logic;




    -- System Interface
    user_clk_out           : out std_logic;
    sync_clk_out           : out std_logic;
 
    tx_system_reset        : in  std_logic;

    power_down             : in  std_logic;
    loopback               : in  std_logic_vector(2 downto 0);
    gt_reset               : in  std_logic;
    tx_lock                : out std_logic;
    sys_reset_out          : out std_logic;
    gt_reset_out           : out std_logic;
 
    init_clk_p             : in  std_logic;
    init_clk_n             : in  std_logic;
    init_clk_out           : out std_logic;
    tx_resetdone_out       : out std_logic;

    --DRP Ports
 
    drpclk_in                         : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;

--__________COMMON PORTS _______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_out       :  out  std_logic;
      gt0_qpllrefclklost_out :  out  std_logic;
  gt_qpllclk_quad10_out     : out  std_logic;  
  gt_qpllrefclk_quad10_out  : out  std_logic;  
--____________________________COMMON PORTS _______________________________}
    pll_not_locked_out     : out std_logic

 );

end tx_aurora_1ln_rx;


architecture STRUCTURE of tx_aurora_1ln_rx is
  attribute core_generation_info           : string;
  attribute core_generation_info of STRUCTURE : architecture is "tx_aurora_1ln_rx,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTHQ9,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=1,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=64128,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160320,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";

    component tx_aurora_1ln_rx_support
 port (
    -- AXI TX Interface
    s_axi_tx_tdata         : in  std_logic_vector(31 downto 0);
    s_axi_tx_tkeep         : in std_logic_vector(3 downto 0);
    s_axi_tx_tvalid        : in  std_logic;
    s_axi_tx_tready        : out std_logic;
    s_axi_tx_tlast         : in  std_logic;



    -- User Flow Control TX Interface
    s_axi_ufc_tx_req       : in std_logic;
    s_axi_ufc_tx_ms        : in std_logic_vector(2 downto 0);
    s_axi_ufc_tx_ack       : out std_logic;




    txp                    : out std_logic_vector(0 downto 0);
    txn                    : out std_logic_vector(0 downto 0);

    -- GT Reference Clock Interface
    gt_refclk1_p             : in  std_logic;
    gt_refclk1_n             : in  std_logic;
    gt_refclk1_out           : out  std_logic;

    -- Error Detection Interface
    tx_hard_err            : out std_logic;
    -- Status
    tx_lane_up             : out std_logic_vector(0 downto 0);
    tx_channel_up          : out std_logic;




    -- System Interface
    user_clk_out           : out std_logic;
    sync_clk_out           : out std_logic;
 
    tx_system_reset        : in  std_logic;
    sys_reset_out          : out std_logic;
    gt_reset_out           : out std_logic;
    power_down             : in  std_logic;
    loopback               : in  std_logic_vector(2 downto 0);
    gt_reset               : in  std_logic;
    init_clk_p             : in  std_logic;
    init_clk_n             : in  std_logic;
    init_clk_out           : out  std_logic;
    pll_not_locked_out     : out std_logic;
    tx_resetdone_out       : out std_logic;


    --DRP Ports
    drpclk_in                          : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;
--__________COMMON PORTS _______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_out       :  out  std_logic;
      gt0_qpllrefclklost_out :  out  std_logic;
  gt_qpllclk_quad10_out     : out  std_logic;  
  gt_qpllrefclk_quad10_out  : out  std_logic;  
--____________________________COMMON PORTS _______________________________}

    tx_lock                : out std_logic

 );

    end component;

begin

 --*********************************Main Body of Code**********************************

     U0 : tx_aurora_1ln_rx_support
     port map (
        -- AXI TX Interface
        S_AXI_TX_TDATA               => s_axi_tx_tdata,
        S_AXI_TX_TKEEP               => s_axi_tx_tkeep,
        S_AXI_TX_TVALID              => s_axi_tx_tvalid,
        S_AXI_TX_TLAST               => s_axi_tx_tlast,
        S_AXI_TX_TREADY              => s_axi_tx_tready,


        -- User Flow Control TX Interface
        S_AXI_UFC_TX_REQ             => s_axi_ufc_tx_tvalid,
        S_AXI_UFC_TX_MS              => s_axi_ufc_tx_tdata,
        S_AXI_UFC_TX_ACK             => s_axi_ufc_tx_tready,


        -- GT Serial I/O
        TXP                          => txp,
        TXN                          => txn,

        -- GT Reference Clock Interface
        gt_refclk1_p                   => gt_refclk1_p,
        gt_refclk1_n                   => gt_refclk1_n,
        gt_refclk1_out                 => gt_refclk1_out,
        -- Error Detection Interface

        -- Error Detection Interface
        TX_HARD_ERR                  => tx_hard_err,

        -- Status
        TX_CHANNEL_UP                => tx_channel_up,
        TX_LANE_UP                   => tx_lane_up,




        -- System Interface
        USER_CLK_OUT                 => user_clk_out,
        sync_clk_out                 => sync_clk_out,
        TX_SYSTEM_RESET              => tx_system_reset,
        sys_reset_out                => sys_reset_out,
        gt_reset_out                 => gt_reset_out,
        POWER_DOWN                   => power_down,
        LOOPBACK                     => loopback,
        GT_RESET                     => gt_reset,
        INIT_CLK_P                   => init_clk_p,
        INIT_CLK_N                   => init_clk_n,
        init_clk_out                 => init_clk_out,
        PLL_NOT_LOCKED_OUT           => pll_not_locked_out,
	TX_RESETDONE_OUT             => tx_resetdone_out,
        drpclk_in                           => drpclk_in,
        DRPADDR_IN                   => drpaddr_in,
        DRPEN_IN                     => drpen_in,
        DRPDI_IN                     => drpdi_in,
        DRPRDY_OUT                   => drprdy_out, 
        DRPDO_OUT                    => drpdo_out,
        DRPWE_IN                     => drpwe_in,
--____________________________COMMON PORTS _______________________________
--    ------------------------- Common Block - QPLL Ports ------------------------
  gt0_qplllock_out        =>  gt0_qplllock_out,
  gt0_qpllrefclklost_out  =>  gt0_qpllrefclklost_out,
  gt_qpllclk_quad10_out =>  gt_qpllclk_quad10_out ,
  gt_qpllrefclk_quad10_out =>  gt_qpllrefclk_quad10_out ,
        TX_LOCK                      => tx_lock

     );

 end STRUCTURE;
