------------------------------------------------------------------------------/
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------------------------------------------------------------------------------/
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_misc.all;
     use IEEE.numeric_std.all;
     use ieee.std_logic_arith.all;
     use ieee.std_logic_unsigned.all;

-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on

entity  tx_aurora_1ln_rx_support is
port (
    -- AXI TX Interface
    s_axi_tx_tdata         : in  std_logic_vector(31 downto 0);
    s_axi_tx_tkeep         : in std_logic_vector(3 downto 0);
    s_axi_tx_tvalid        : in  std_logic;
    s_axi_tx_tready        : out std_logic;
    s_axi_tx_tlast         : in  std_logic;



    -- User Flow Control TX Interface
    s_axi_ufc_tx_req       : in std_logic;
    s_axi_ufc_tx_ms        : in std_logic_vector(2 downto 0);
    s_axi_ufc_tx_ack       : out std_logic;




    txp                    : out std_logic_vector(0 downto 0);
    txn                    : out std_logic_vector(0 downto 0);

    -- GT Reference Clock Interface
    gt_refclk1_p             : in  std_logic;
    gt_refclk1_n             : in  std_logic;
    gt_refclk1_out           : out  std_logic;

    -- Error Detection Interface
    tx_hard_err            : out std_logic;
    -- Status
    tx_lane_up             : out std_logic_vector(0 downto 0);
    tx_channel_up          : out std_logic;




    -- System Interface
    user_clk_out           : out std_logic;
    sync_clk_out           : out std_logic;
 
    tx_system_reset        : in  std_logic;
    gt_reset               : in  std_logic;
    sys_reset_out          : out std_logic;
    gt_reset_out           : out  std_logic;  

    power_down             : in  std_logic;
    loopback               : in  std_logic_vector(2 downto 0);
    tx_lock                : out std_logic;
    init_clk_p             : in  std_logic;
    init_clk_n             : in  std_logic;
    init_clk_out           : out std_logic;
    tx_resetdone_out       : out std_logic;


    --DRP Ports
    drpclk_in                         : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;
   
--__________COMMON PORTS _______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_out       :  out  std_logic;
      gt0_qpllrefclklost_out :  out  std_logic;
  gt_qpllclk_quad10_out     : out  std_logic;  
  gt_qpllrefclk_quad10_out  : out  std_logic;  
--____________________________COMMON PORTS _______________________________}

    pll_not_locked_out      : out  std_logic

 );

end tx_aurora_1ln_rx_support;


architecture STRUCTURE of tx_aurora_1ln_rx_support is
  attribute core_generation_info           : string;
  attribute core_generation_info of STRUCTURE : architecture is "tx_aurora_1ln_rx,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTHQ9,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=1,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=64128,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160320,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";

    component tx_aurora_1ln_rx_core
        port   (
         -- TX Stream Interface
         S_AXI_TX_TDATA         : in  std_logic_vector(31 downto 0);
         S_AXI_TX_TKEEP         : in std_logic_vector(3 downto 0);
         S_AXI_TX_TVALID        : in  std_logic;
         S_AXI_TX_TREADY        : out std_logic;
         S_AXI_TX_TLAST         : in  std_logic;

         -- User Flow Control TX Interface

         S_AXI_UFC_TX_REQ       : in std_logic;
         S_AXI_UFC_TX_MS        : in std_logic_vector(2 downto 0);
         S_AXI_UFC_TX_ACK       : out std_logic;


    TXP                    : out std_logic;
    TXN                    : out std_logic;

         -- GT Reference Clock Interface
         gt_refclk1           : in std_logic;

         -- Error Detection Interface
         TX_HARD_ERR            : out std_logic;

         -- Status
         TX_CHANNEL_UP          : out std_logic;
         TX_LANE_UP             : out std_logic;

               




         -- System Interface

         USER_CLK         : in std_logic;
         SYNC_CLK         : in std_logic;
         GT_RESET         : in std_logic;
         TX_SYSTEM_RESET  : in std_logic;
         sys_reset_out    : out std_logic;
         POWER_DOWN       : in std_logic;
         LOOPBACK         : in std_logic_vector(2 downto 0);
         TX_OUT_CLK       : out std_logic;
         INIT_CLK_IN         : in  std_logic; 
         PLL_NOT_LOCKED      : in  std_logic;
         TX_RESETDONE_OUT    : out std_logic;

         drpclk_in                                             : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;
   	
--------------------{
--__________COMMON PORTS _______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
  gt_qpllclk_quad10_in     : in  std_logic;  
  gt_qpllrefclk_quad10_in  : in  std_logic;  
--____________________________COMMON PORTS _______________________________}
         TX_LOCK          : out std_logic
    );

    end component;


component tx_aurora_1ln_rx_gt_common_wrapper
port
(
--____________________________COMMON PORTS ,_______________________________{
   gt_qpllclk_quad10_i    : out std_logic;
   gt_qpllrefclk_quad10_i : out std_logic;
--____________________________COMMON PORTS ,_______________________________}
    ---------------------- Common Block  - Ref Clock Ports ---------------------
    gt0_gtrefclk0_common_in    :  in  std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
    gt0_qplllock_out           : out std_logic;
    gt0_qplllockdetclk_in      : in  std_logic;
    gt0_qpllrefclklost_out     : out std_logic;
    gt0_qpllreset_in           : in  std_logic  

);
end component;


  component IBUFDS_GTE2
  port (
     O : out std_ulogic;
     ODIV2 : out std_ulogic;
     CEB : in std_ulogic;
     I : in std_ulogic;
     IB : in std_ulogic
       );
  end component;

    component BUFG

        port (

                O : out std_ulogic;
                I : in  std_ulogic

             );

    end component;

    component tx_aurora_1ln_rx_CLOCK_MODULE
        port (
                INIT_CLK_P              : in std_logic;
                INIT_CLK_N              : in std_logic;
                INIT_CLK_O              : out std_logic; 
                GT_CLK                  : in std_logic;
                GT_CLK_LOCKED           : in std_logic;
                USER_CLK                : out std_logic;
                SYNC_CLK                : out std_logic;
                PLL_NOT_LOCKED          : out std_logic
             );
    end component;

    component tx_aurora_1ln_rx_SUPPORT_RESET_LOGIC
        port (
                RESET                  : in std_logic;
                USER_CLK               : in std_logic;
                INIT_CLK_IN            : in std_logic;
                GT_RESET_IN            : in std_logic;
                SYSTEM_RESET           : out std_logic;
                GT_RESET_OUT           : out std_logic
             );
    end component;

  component  tx_aurora_1ln_rx_cdc_sync is
    generic (
        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
                                    -- 0 is pulse synch
                                    -- 1 is level synch
                                    -- 2 is ack based level sync
        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
                                    -- 0 is reset not needed 
                                    -- 1 is reset needed 
        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
                                    -- 0 is bus input
                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 32 := 32               ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
            -- Vector Data witdth
    );

    port (
        prmry_aclk                  : in  std_logic                             ;               --
        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                                --
        scndry_aclk                 : in  std_logic                             ;               --
        scndry_resetn               : in  std_logic                             ;               --
                                                                                                --
        -- Primary to Secondary Clock Crossing                                                  --
        scndry_out                  : out std_logic                             ;               --
                                                                                                --
        scndry_vect_out             : out std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );
  end component;

------------  Wire declarations
--------------------{
    ------------------------- Common Block - QPLL Ports ------------------------
signal gt0_qplllock_i         : std_logic;
signal gt0_qpllrefclklost_i   : std_logic;
signal gt0_qpllreset_i        : std_logic;
signal                      gt_qpllclk_quad10_i  :  std_logic;
signal                      gt_qpllrefclk_quad10_i  :  std_logic;
--------------------}
signal               gt_refclk1    :   std_logic;

signal               tx_out_clk_i            :  std_logic;
signal               user_clk_i              :  std_logic;
signal               sync_clk_i              :  std_logic;
signal               pll_not_locked_i        :  std_logic;
signal               tx_lock_i               :  std_logic;

signal               init_clk_i              :  std_logic;
signal               tx_resetdone_i          :  std_logic;
signal               system_reset_i          :  std_logic;
signal               gt_reset_i              :  std_logic;
signal               drpclk_i                :  std_logic;
signal               reset_sync_user_clk     : std_logic;
signal               gt_reset_sync_init_clk  : std_logic;
begin

 --*********************************Main Body of Code**********************************

      IBUFDS_GTE2_CLK1 :  IBUFDS_GTE2
      port map (
           I     => gt_refclk1_p,
           IB    => gt_refclk1_n,
           CEB   => '0',
           O     => gt_refclk1,
           ODIV2 => OPEN);


  drpclk_i <= drpclk_in;

    -- Instantiate a clock module for clock division

    clock_module_i : tx_aurora_1ln_rx_CLOCK_MODULE
        port map (
                    INIT_CLK_P          => init_clk_p,
                    INIT_CLK_N          => init_clk_n,
                    INIT_CLK_O          => init_clk_i,
                    GT_CLK              => tx_out_clk_i,
                    GT_CLK_LOCKED       => tx_lock_i,
                    USER_CLK            => user_clk_i,
                    SYNC_CLK            => sync_clk_i,
                    PLL_NOT_LOCKED      => pll_not_locked_i
                 );

  --  outputs
  gt_reset_out          <=  gt_reset_i;
  gt_refclk1_out        <=  gt_refclk1;
  sync_clk_out          <=  sync_clk_i;
  init_clk_out          <=  init_clk_i;
  user_clk_out          <=  user_clk_i;
  pll_not_locked_out    <=  pll_not_locked_i;
  tx_lock               <=  tx_lock_i;
  tx_resetdone_out      <=  tx_resetdone_i;

--____________________________COMMON PORTS _______________________________
--    ------------------------- Common Block - QPLL Ports ------------------------
  gt0_qplllock_out         <= gt0_qplllock_i;
  gt0_qpllrefclklost_out   <= gt0_qpllrefclklost_i;
  gt_qpllclk_quad10_out  <= gt_qpllclk_quad10_i ;
  gt_qpllrefclk_quad10_out  <= gt_qpllrefclk_quad10_i ;

 reset_sync_user_clk_cdc_sync : tx_aurora_1ln_rx_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                ,
       prmry_resetn      => '1'                ,
       prmry_in          => tx_system_reset    ,
       prmry_vect_in     => "00"               ,
       scndry_aclk       => user_clk_i         ,
       scndry_resetn     => '1'                ,
       prmry_ack         => open               ,
       scndry_out        => reset_sync_user_clk,
       scndry_vect_out   => open           
     );

 gt_reset_cdc_sync : tx_aurora_1ln_rx_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                   ,
       prmry_resetn      => '1'                   ,
       prmry_in          => gt_reset              ,
       prmry_vect_in     => "00"                  ,
       scndry_aclk       => init_clk_i            ,
       scndry_resetn     => '1'                   ,
       prmry_ack         => open                  ,
       scndry_out        => gt_reset_sync_init_clk,
       scndry_vect_out   => open           
     );

    support_reset_logic_i : tx_aurora_1ln_rx_SUPPORT_RESET_LOGIC
        port map (
                   RESET               =>  reset_sync_user_clk,
                   USER_CLK            =>  user_clk_i,
                   INIT_CLK_IN         =>  init_clk_i,
                   GT_RESET_IN         =>  gt_reset_sync_init_clk,
                   SYSTEM_RESET        =>  system_reset_i,
                   GT_RESET_OUT        =>  gt_reset_i
                 );

-------- instance of _gt_common_wrapper ---{
gt_common_support : tx_aurora_1ln_rx_gt_common_wrapper

port map
(
--____________________________COMMON PORTS ,_______________________________{
  gt_qpllclk_quad10_i     => gt_qpllclk_quad10_i ,
  gt_qpllrefclk_quad10_i  => gt_qpllrefclk_quad10_i ,
    ---------------------- Common Block  - Ref Clock Ports ---------------------
      gt0_gtrefclk0_common_in  =>  gt_refclk1,

    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_out        => gt0_qplllock_i,
      gt0_qplllockdetclk_in   => init_clk_i,
      gt0_qpllrefclklost_out  => gt0_qpllrefclklost_i ,
      gt0_qpllreset_in  =>  gt0_qpllreset_i 
--____________________________COMMON PORTS ,_______________________________}
);


-------- instance of _gt_common_wrapper ---}

     tx_aurora_1ln_rx_core_i : tx_aurora_1ln_rx_core
     port map (
        -- AXI TX Interface
        s_axi_tx_tdata               => s_axi_tx_tdata,
        s_axi_tx_tkeep               => s_axi_tx_tkeep,
        s_axi_tx_tvalid              => s_axi_tx_tvalid,
        s_axi_tx_tlast               => s_axi_tx_tlast,
        s_axi_tx_tready              => s_axi_tx_tready,


        -- User Flow Control TX Interface
        s_axi_ufc_tx_req             => s_axi_ufc_tx_req,
        s_axi_ufc_tx_ms              => s_axi_ufc_tx_ms,
        s_axi_ufc_tx_ack             => s_axi_ufc_tx_ack,


        -- GT Serial I/O
        txp                          => txp(0),
        txn                          => txn(0),

        -- GT Reference Clock Interface
        gt_refclk1                   => gt_refclk1,
        -- Error Detection Interface

        -- Error Detection Interface
        tx_hard_err                  => tx_hard_err,

        -- Status
        tx_channel_up                => tx_channel_up,
        tx_lane_up                   => tx_lane_up(0),




        -- System Interface
        user_clk                     => user_clk_i,
        sync_clk                     => sync_clk_i,
        tx_system_reset              => system_reset_i,
        sys_reset_out                => sys_reset_out,
        power_down                   => power_down,
        loopback                     => loopback,
        gt_reset                     => gt_reset_i,
        tx_lock                      => tx_lock_i,
        init_clk_in                  => init_clk_i,
        pll_not_locked               => pll_not_locked_i,
	tx_resetdone_out             => tx_resetdone_i,


        drpclk_in                            => drpclk_i,
        drpaddr_in                   => drpaddr_in,
        drpen_in                     => drpen_in,
        drpdi_in                     => drpdi_in,
        drprdy_out                   => drprdy_out, 
        drpdo_out                    => drpdo_out,
        drpwe_in                     => drpwe_in,
--------------------{
--__________COMMON PORTS _______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in        =>  gt0_qplllock_i,
      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_i,
      gt0_qpllreset_out      =>  gt0_qpllreset_i,
  gt_qpllclk_quad10_in     => gt_qpllclk_quad10_i ,
  gt_qpllrefclk_quad10_in  => gt_qpllrefclk_quad10_i ,
--____________________________COMMON PORTS ,_______________________________}
--------------------}
        tx_out_clk                   => tx_out_clk_i

     );

 end STRUCTURE; 
