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--
--  TX_ERR_DETECT_SIMPLEX
--
--
--
--  Description : The TX_ERR_DETECT_SIMPLEX module monitors the V5 to detect hard
--                errors.  All errors are reported to the Global Logic Interface.
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA_PKG.all;

entity tx_aurora_1ln_rx_TX_ERR_DETECT_SIMPLEX is

    port (

    -- Lane Init SM Interface

            ENABLE_ERR_DETECT : in std_logic;
            HARD_ERR_RESET    : out std_logic;

    -- Global Logic Interface

            HARD_ERR          : out std_logic;

    -- V5 Interface

            TX_K_ERR            : in std_logic_vector(1 downto 0);
            TX_BUF_ERR          : in std_logic;

    -- System Interface

            USER_CLK            : in std_logic

         );

end tx_aurora_1ln_rx_TX_ERR_DETECT_SIMPLEX;

architecture RTL of tx_aurora_1ln_rx_TX_ERR_DETECT_SIMPLEX is

-- Parameter Declarations --

    constant DLY : time := 1 ns;

-- External Register Declarations --

    signal HARD_ERR_RESET_Buffer : std_logic;
    signal HARD_ERR_Buffer       : std_logic;

-- Internal Register Declarations --

    signal hard_err_flop_r : std_logic;  -- Traveling flop for timing.

begin

    HARD_ERR_RESET <= HARD_ERR_RESET_Buffer;
    HARD_ERR       <= HARD_ERR_Buffer;

-- Main Body of Code --

    -- Detect Hard Errors

    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            if (ENABLE_ERR_DETECT = '1') then

                hard_err_flop_r <= std_bool(TX_K_ERR /= "00") or
                                     TX_BUF_ERR after DLY;
                HARD_ERR_Buffer <= hard_err_flop_r after DLY;

            else

                hard_err_flop_r <= '0' after DLY;
                HARD_ERR_Buffer <= '0' after DLY;

            end if;

        end if;

    end process;


    -- Assert hard error reset when there is a hard error.  This assignment
    -- just renames the two fanout branches of the hard error signal.

    HARD_ERR_RESET_Buffer <= hard_err_flop_r;

end RTL;
