Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date             : Tue Dec  1 20:08:44 2020
| Host             : hog-efex3.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command          : report_power -file top_rod_efex_power_routed.rpt -pb top_rod_efex_power_summary_routed.pb -rpx top_rod_efex_power_routed.rpx
| Design           : top_rod_efex
| Device           : xc7vx550tffg1927-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------------------

Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 18.061       |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 17.359       |
| Device Static (W)        | 0.701        |
| Effective TJA (C/W)      | 0.8          |
| Max Ambient (C)          | 69.7         |
| Junction Temperature (C) | 40.3         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     1.292 |       75 |       --- |             --- |
| Slice Logic              |     0.182 |   363053 |       --- |             --- |
|   LUT as Logic           |     0.136 |   104762 |    346400 |           30.24 |
|   Register               |     0.019 |   191034 |    692800 |           27.57 |
|   LUT as Shift Register  |     0.010 |    12582 |    174200 |            7.22 |
|   CARRY4                 |     0.008 |     6782 |    108300 |            6.26 |
|   Others                 |     0.006 |    20340 |       --- |             --- |
|   LUT as Distributed RAM |     0.002 |     1813 |    174200 |            1.04 |
|   F7/F8 Muxes            |    <0.001 |     2752 |    433200 |            0.64 |
|   BUFG                   |    <0.001 |        2 |        32 |            6.25 |
| Signals                  |     0.293 |   275336 |       --- |             --- |
| Block RAM                |     0.250 |      262 |      1180 |           22.20 |
| MMCM                     |     0.463 |        4 |        20 |           20.00 |
| I/O                      |     0.065 |      103 |       600 |           17.17 |
| GTH                      |    14.814 |       54 |       --- |             --- |
| XADC                     |    <0.001 |        1 |       --- |             --- |
| Static Power             |     0.701 |          |           |                 |
| Total                    |    18.061 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     4.763 |       4.397 |      0.366 |
| Vccaux    |       1.800 |     0.334 |       0.274 |      0.059 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.019 |       0.018 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.040 |       0.020 |      0.021 |
| MGTAVcc   |       1.000 |     7.738 |       7.607 |      0.130 |
| MGTAVtt   |       1.200 |     4.010 |       3.976 |      0.033 |
| MGTVccaux |       1.800 |     0.021 |       0.020 |      0.000 |
| MGTZVccl  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZAVcc  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZVcch  |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 0.8                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 1.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                                                                 | Domain                                                                                                                                          | Constraint (ns) |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| CLK_125_pin                                                                                                                                           | CLK_125_pin                                                                                                                                     |             8.0 |
| CLK_40_pin                                                                                                                                            | CLK_40                                                                                                                                          |            25.0 |
| CLK_40_pin                                                                                                                                            | CLK_40_pin_P                                                                                                                                    |            25.0 |
| FM_TXOUTCLK                                                                                                                                           | fm_interface_1/u0/I                                                                                                                             |             4.2 |
| FM_TXOUTCLK_2                                                                                                                                         | fm_interface_2/u0/I                                                                                                                             |             4.2 |
| GT_REFCLK112                                                                                                                                          | GTCLK_q112_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK115                                                                                                                                          | GTCLK_q115_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK118                                                                                                                                          | GTCLK_q118_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK211                                                                                                                                          | GTCLK_q211_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK214                                                                                                                                          | GTCLK_q214_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK217                                                                                                                                          | GTCLK_q217_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK219                                                                                                                                          | GTCLK_q219_c0p                                                                                                                                  |             6.2 |
| GT_REFCLK_C1_218                                                                                                                                      | GTCLK_q218_c1p                                                                                                                                  |             4.2 |
| backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK  | backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK  |             3.1 |
| backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK             |             3.1 |
| backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK | backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK |             3.1 |
| backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK             |             3.1 |
| backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK | backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK |             3.1 |
| backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK              | backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK              |             3.1 |
| backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK  | backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK  |             3.1 |
| backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK              | backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK              |             3.1 |
| backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK  | backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK  |             3.1 |
| backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK              | backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK              |             3.1 |
| backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK  | backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/TX_OUT_CLK  |             3.1 |
| backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK              | backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/TX_OUT_CLK              |             3.1 |
| backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gthe2_i/RXOUTCLK                        | backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gt0_rxoutclk_out                  |             6.2 |
| backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/TXOUTCLK                                           | backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gt0_txoutclk_out                                     |             6.2 |
| clk240_clk_wiz_240                                                                                                                                    | fm_interface_1/clk_blk/inst/clk240_clk_wiz_240                                                                                                  |             4.2 |
| clk240_clk_wiz_240_1                                                                                                                                  | fm_interface_2/clk_blk/inst/clk240_clk_wiz_240                                                                                                  |             4.2 |
| clk40                                                                                                                                                 | fm_interface_1/clk_blk/inst/clk40_clk_wiz_240                                                                                                   |            10.0 |
| clk40_2                                                                                                                                               | fm_interface_2/clk_blk/inst/clk40_clk_wiz_240                                                                                                   |            10.0 |
| clkfbout                                                                                                                                              | ipbus_blk/ipbus/example_clocks/clock_generator/clkfbout                                                                                         |             8.0 |
| clkfbout_clk_wiz_240                                                                                                                                  | fm_interface_1/clk_blk/inst/clkfbout_clk_wiz_240                                                                                                |            25.0 |
| clkfbout_clk_wiz_240_1                                                                                                                                | fm_interface_2/clk_blk/inst/clkfbout_clk_wiz_240                                                                                                |            25.0 |
| clkfbout_packet_processor_clock                                                                                                                       | proc_clock_gen/inst/clkfbout_packet_processor_clock                                                                                             |            25.0 |
| clkout0                                                                                                                                               | ipbus_blk/ipbus/example_clocks/clock_generator/clkout0                                                                                          |             8.0 |
| clkout1                                                                                                                                               | ipbus_blk/ipbus/example_clocks/clock_generator/clkout1                                                                                          |            10.0 |
| clkout2                                                                                                                                               | ipbus_blk/ipbus/example_clocks/clock_generator/clkout2                                                                                          |             5.0 |
| clkout3                                                                                                                                               | ipbus_blk/ipbus/example_clocks/clock_generator/clkout3                                                                                          |            32.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK                                                            | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/tck_bs                                                                            |            33.0 |
| pp_clock_packet_processor_clock                                                                                                                       | proc_clock_gen/inst/pp_clock_packet_processor_clock                                                                                             |             6.2 |
| rgmii_rxc                                                                                                                                             | rgmii_rxc                                                                                                                                       |             8.0 |
| user_clk_out_10                                                                                                                                       | backplane/aurora_10/aurora_module_i/clock_module_i/CLK                                                                                          |             3.2 |
| user_clk_out_11                                                                                                                                       | backplane/aurora_11/aurora_module_i/clock_module_i/CLK                                                                                          |             3.2 |
| user_clk_out_12                                                                                                                                       | backplane/aurora_12/aurora_module_i/clock_module_i/CLK                                                                                          |             3.2 |
| user_clk_out_13                                                                                                                                       | backplane/aurora_13/aurora_module_i/clock_module_i/CLK                                                                                          |             3.2 |
| user_clk_out_14                                                                                                                                       | backplane/aurora_14/aurora_module_i/clock_module_i/CLK                                                                                          |             3.2 |
| user_clk_out_3                                                                                                                                        | backplane/aurora_3/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_4                                                                                                                                        | backplane/aurora_4/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_5                                                                                                                                        | backplane/aurora_5/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_6                                                                                                                                        | backplane/aurora_6/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_7                                                                                                                                        | backplane/aurora_7/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_8                                                                                                                                        | backplane/aurora_8/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
| user_clk_out_9                                                                                                                                        | backplane/aurora_9/aurora_module_i/clock_module_i/CLK                                                                                           |             3.2 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------------------------------+-----------+
| Name                               | Power (W) |
+------------------------------------+-----------+
| top_rod_efex                       |    17.359 |
|   Bulk_0_64_32                     |     0.039 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.002 |
|       inst                         |     0.002 |
|     main_fifo                      |     0.010 |
|       inst                         |     0.010 |
|   Bulk_1_64_32                     |     0.033 |
|     ILA_packet_fifo                |     0.023 |
|       U0                           |     0.023 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.009 |
|       inst                         |     0.009 |
|   Bulk_2_64_32                     |     0.039 |
|     ILA_packet_fifo                |     0.027 |
|       U0                           |     0.027 |
|     data_width_conv                |     0.002 |
|       inst                         |     0.002 |
|     main_fifo                      |     0.010 |
|       inst                         |     0.010 |
|   ILA_axi_slot4                    |     0.014 |
|     U0                             |     0.014 |
|       ila_core_inst                |     0.014 |
|   ILA_axi_slot5                    |     0.013 |
|     U0                             |     0.013 |
|       ila_core_inst                |     0.013 |
|   backplane                        |    14.651 |
|     aurora_10                      |     1.182 |
|       aurora_module_i              |     1.182 |
|     aurora_11                      |     1.177 |
|       aurora_module_i              |     1.177 |
|     aurora_12                      |     1.180 |
|       aurora_module_i              |     1.180 |
|     aurora_13                      |     1.179 |
|       aurora_module_i              |     1.178 |
|     aurora_14                      |     1.189 |
|       aurora_module_i              |     1.189 |
|     aurora_3                       |     1.179 |
|       aurora_module_i              |     1.179 |
|     aurora_4                       |     1.179 |
|       aurora_module_i              |     1.179 |
|     aurora_5                       |     1.177 |
|       aurora_module_i              |     1.177 |
|     aurora_6                       |     1.180 |
|       aurora_module_i              |     1.180 |
|     aurora_7                       |     1.180 |
|       aurora_module_i              |     1.180 |
|     aurora_8                       |     1.195 |
|       aurora_module_i              |     1.195 |
|     aurora_9                       |     1.177 |
|       aurora_module_i              |     1.177 |
|     clock_tester                   |     0.007 |
|       clock_test_ila_block         |     0.006 |
|     combined_ttc                   |     0.266 |
|       gt0_frame_check              |     0.003 |
|       ila_rx2_inst                 |     0.022 |
|       inst_regs                    |     0.004 |
|       sume_RO_Rx_support_i         |     0.237 |
|     readout_ctrl                   |     0.203 |
|       ila_tx0_inst                 |     0.005 |
|       rod_RO_Tx_support_i          |     0.196 |
|   bkpln_control_ila                |     0.008 |
|     U0                             |     0.008 |
|       ila_core_inst                |     0.008 |
|   dbg_hub                          |     0.006 |
|     inst                           |     0.006 |
|       BSCANID.u_xsdbm_id           |     0.006 |
|   event_builder                    |     0.962 |
|     bulk_0                         |     0.027 |
|       bulkl_proc_probe             |     0.012 |
|       gen_reg.status_regs          |     0.006 |
|       input_mux                    |     0.007 |
|     bulk_1                         |     0.019 |
|       bulkl_proc_probe             |     0.011 |
|       gen_reg.status_regs          |     0.006 |
|     bulk_2                         |     0.018 |
|       bulkl_proc_probe             |     0.011 |
|       gen_reg.status_regs          |     0.006 |
|     fifo_layer                     |     0.759 |
|       ch0                          |     0.089 |
|       ch1                          |     0.086 |
|       ch10                         |     0.036 |
|       ch11                         |     0.043 |
|       ch2                          |     0.082 |
|       ch3                          |     0.074 |
|       ch4                          |     0.073 |
|       ch5                          |     0.047 |
|       ch6                          |     0.071 |
|       ch7                          |     0.076 |
|       ch8                          |     0.035 |
|       ch9                          |     0.037 |
|       gen_reg.channel_map_ila      |     0.005 |
|       gen_reg.registers            |     0.001 |
|       gen_reg.ttc_regs             |     0.005 |
|     readout_controller             |     0.040 |
|       readout_ctrl_ila2            |     0.024 |
|       ro_crc                       |     0.006 |
|     tob_processor_0                |     0.058 |
|       event_builder_0              |     0.037 |
|       gen_reg.status_regs          |     0.006 |
|       input_mux                    |     0.007 |
|       input_mux_ila                |     0.008 |
|     ttc_input                      |     0.040 |
|       bulk_ttc_fifo                |     0.008 |
|       ila_bulk_ttc_fifo            |     0.007 |
|       ila_ttc_fifo_in              |     0.008 |
|       ila_ttc_fifo_out             |     0.008 |
|       ttc_fifo                     |     0.008 |
|   fm_interface_1                   |     0.534 |
|     chan_0                         |     0.039 |
|       L1ID_fifo                    |     0.002 |
|       ctl0                         |     0.001 |
|       ila_fm                       |     0.010 |
|       ram0                         |     0.005 |
|       u5                           |     0.011 |
|       u7                           |     0.008 |
|     chan_1                         |     0.033 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.010 |
|       ram0                         |     0.005 |
|       u5                           |     0.009 |
|       u7                           |     0.005 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     u0                             |     0.344 |
|       g_gt_channel[0].rxresetfsm_i |     0.002 |
|       g_gt_channel[1].rxresetfsm_i |     0.002 |
|       ila_resetfsm                 |     0.005 |
|       txresetfsm_i                 |     0.002 |
|   fm_interface_2                   |     0.591 |
|     chan_0                         |     0.066 |
|       L1ID_fifo                    |     0.002 |
|       axi_trace_dbg.fm_axi_trace   |     0.015 |
|       ila_ed_dbg.ila_ed            |     0.018 |
|       ila_fm                       |     0.009 |
|       ram0                         |     0.005 |
|       u5                           |     0.007 |
|       u7                           |     0.008 |
|     chan_1                         |     0.061 |
|       L1ID_fifo                    |     0.002 |
|       axi_trace_dbg.fm_axi_trace   |     0.015 |
|       ila_ed_dbg.ila_ed            |     0.016 |
|       ila_fm                       |     0.008 |
|       ram0                         |     0.005 |
|       u5                           |     0.007 |
|       u7                           |     0.005 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     u0                             |     0.346 |
|       g_gt_channel[0].rxresetfsm_i |     0.002 |
|       g_gt_channel[1].rxresetfsm_i |     0.002 |
|       ila_resetfsm                 |     0.005 |
|       txresetfsm_i                 |     0.002 |
|   ipbus_blk                        |     0.301 |
|     axi4_subsys                    |     0.025 |
|       axi4_subsys_i                |     0.025 |
|     ipbus                          |     0.273 |
|       clocks                       |     0.003 |
|       example_clocks               |     0.109 |
|       ipbus                        |     0.069 |
|       trimac_fifo_block            |     0.092 |
|   pp_out_fifo_6432                 |     0.033 |
|     ILA_packet_fifo                |     0.023 |
|       U0                           |     0.023 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.009 |
|       inst                         |     0.009 |
|   proc_clock_gen                   |     0.123 |
|     inst                           |     0.123 |
+------------------------------------+-----------+