diff --git a/BD/axi4_subsys.bd b/BD/axi4_subsys.bd index d18ef54..22dfcb3 100644 --- a/BD/axi4_subsys.bd +++ b/BD/axi4_subsys.bd @@ -618,17 +618,17 @@ } }, "interface_nets": { - "s00_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_s00_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -814,17 +814,17 @@ } }, "interface_nets": { - "auto_pc_to_m01_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m01_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m01_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -902,17 +902,17 @@ } }, "interface_nets": { - "auto_pc_to_m02_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m02_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m02_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -1284,16 +1284,22 @@ } }, "interface_nets": { - "axi_interconnect_0_to_s00_couplers": { + "xbar_to_m03_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "xbar/M03_AXI", + "m03_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "m00_couplers_to_axi_interconnect_0": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "m06_couplers_to_axi_interconnect_0": { + "interface_ports": [ + "M06_AXI", + "m06_couplers/M_AXI" ] }, "axi_interconnect_0_to_s01_couplers": { @@ -1302,46 +1308,46 @@ "s01_couplers/S_AXI" ] }, - "s01_couplers_to_xbar": { + "xbar_to_m06_couplers": { "interface_ports": [ - "s01_couplers/M_AXI", - "xbar/S01_AXI" + "xbar/M06_AXI", + "m06_couplers/S_AXI" ] }, - "m00_couplers_to_axi_interconnect_0": { + "xbar_to_m02_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M02_AXI", + "m02_couplers/S_AXI" ] }, - "m01_couplers_to_axi_interconnect_0": { + "xbar_to_m01_couplers": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "xbar/M01_AXI", + "m01_couplers/S_AXI" ] }, - "xbar_to_m00_couplers": { + "m04_couplers_to_axi_interconnect_0": { "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" + "M04_AXI", + "m04_couplers/M_AXI" ] }, - "xbar_to_m01_couplers": { + "m01_couplers_to_axi_interconnect_0": { "interface_ports": [ - "xbar/M01_AXI", - "m01_couplers/S_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, - "m02_couplers_to_axi_interconnect_0": { + "s01_couplers_to_xbar": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "s01_couplers/M_AXI", + "xbar/S01_AXI" ] }, - "xbar_to_m02_couplers": { + "m05_couplers_to_axi_interconnect_0": { "interface_ports": [ - "xbar/M02_AXI", - "m02_couplers/S_AXI" + "M05_AXI", + "m05_couplers/M_AXI" ] }, "m03_couplers_to_axi_interconnect_0": { @@ -1350,16 +1356,16 @@ "m03_couplers/M_AXI" ] }, - "xbar_to_m03_couplers": { + "xbar_to_m05_couplers": { "interface_ports": [ - "xbar/M03_AXI", - "m03_couplers/S_AXI" + "xbar/M05_AXI", + "m05_couplers/S_AXI" ] }, - "m04_couplers_to_axi_interconnect_0": { + "axi_interconnect_0_to_s00_couplers": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, "xbar_to_m04_couplers": { @@ -1368,28 +1374,22 @@ "m04_couplers/S_AXI" ] }, - "m05_couplers_to_axi_interconnect_0": { - "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" - ] - }, - "xbar_to_m05_couplers": { + "m02_couplers_to_axi_interconnect_0": { "interface_ports": [ - "xbar/M05_AXI", - "m05_couplers/S_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, - "m06_couplers_to_axi_interconnect_0": { + "xbar_to_m00_couplers": { "interface_ports": [ - "M06_AXI", - "m06_couplers/M_AXI" + "xbar/M00_AXI", + "m00_couplers/S_AXI" ] }, - "xbar_to_m06_couplers": { + "s00_couplers_to_xbar": { "interface_ports": [ - "xbar/M06_AXI", - "m06_couplers/S_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] } }, @@ -1513,34 +1513,22 @@ } }, "interface_nets": { - "axi_interconnect_0_M02_AXI": { - "interface_ports": [ - "axi_iic_0/S_AXI", - "axi_interconnect_0/M02_AXI" - ] - }, - "axi_interconnect_0_M06_AXI": { - "interface_ports": [ - "axi_interconnect_0/M06_AXI", - "xadc_wiz_0/s_axi_lite" - ] - }, - "axi_interconnect_0_M04_AXI": { + "axi_interconnect_0_M01_AXI": { "interface_ports": [ - "axi_interconnect_0/M04_AXI", - "axi_quad_spi_0/AXI_LITE" + "axi_gpio_0/S_AXI", + "axi_interconnect_0/M01_AXI" ] }, - "axi_gpio_0_GPIO2": { + "axi_interconnect_0_M02_AXI": { "interface_ports": [ - "GPIO2", - "axi_gpio_0/GPIO2" + "axi_iic_0/S_AXI", + "axi_interconnect_0/M02_AXI" ] }, - "Vp_Vn_1": { + "axi_interconnect_0_M03_AXI": { "interface_ports": [ - "Vp_Vn", - "xadc_wiz_0/Vp_Vn" + "axi_iic_1/S_AXI", + "axi_interconnect_0/M03_AXI" ] }, "jtag_axi_0_M_AXI": { @@ -1549,22 +1537,28 @@ "jtag_axi_0/M_AXI" ] }, + "axi_gpio_0_GPIO": { + "interface_ports": [ + "GPIO", + "axi_gpio_0/GPIO" + ] + }, "axi_quad_spi_0_SPI_0": { "interface_ports": [ "SPI_0", "axi_quad_spi_0/SPI_0" ] }, - "axi_iic_0_IIC": { + "Vp_Vn_1": { "interface_ports": [ - "IIC", - "axi_iic_0/IIC" + "Vp_Vn", + "xadc_wiz_0/Vp_Vn" ] }, - "axi_iic_1_IIC": { + "axi_interconnect_0_M06_AXI": { "interface_ports": [ - "IIC_1", - "axi_iic_1/IIC" + "axi_interconnect_0/M06_AXI", + "xadc_wiz_0/s_axi_lite" ] }, "axi_interconnect_0_M00_AXI": { @@ -1579,28 +1573,34 @@ "axi_interconnect_0/M05_AXI" ] }, - "axi_interconnect_0_M01_AXI": { - "interface_ports": [ - "axi_gpio_0/S_AXI", - "axi_interconnect_0/M01_AXI" - ] - }, "S00_AXI_1": { "interface_ports": [ "S00_AXI", "axi_interconnect_0/S00_AXI" ] }, - "axi_interconnect_0_M03_AXI": { + "axi_interconnect_0_M04_AXI": { "interface_ports": [ - "axi_iic_1/S_AXI", - "axi_interconnect_0/M03_AXI" + "axi_interconnect_0/M04_AXI", + "axi_quad_spi_0/AXI_LITE" ] }, - "axi_gpio_0_GPIO": { + "axi_iic_1_IIC": { "interface_ports": [ - "GPIO", - "axi_gpio_0/GPIO" + "IIC_1", + "axi_iic_1/IIC" + ] + }, + "axi_gpio_0_GPIO2": { + "interface_ports": [ + "GPIO2", + "axi_gpio_0/GPIO2" + ] + }, + "axi_iic_0_IIC": { + "interface_ports": [ + "IIC", + "axi_iic_0/IIC" ] } },