*** Running vivado with args -log axis_input_fifo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axis_input_fifo.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source axis_input_fifo.tcl -notrace Command: synth_design -top axis_input_fifo -part xc7vx550tffg1927-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10588 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2230.719 ; gain = 201.684 ; free physical = 146 ; free virtual = 14009 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'axis_input_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/synth/axis_input_fifo.v:58] INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_v2_0_2_top' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_data_fifo_v2_0_vl_rfs.v:54] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer Parameter C_AXIS_SIGNAL_SET bound to: 32'b00000000000000000000000010010011 Parameter C_FIFO_DEPTH bound to: 2048 - type: integer Parameter C_FIFO_MODE bound to: 2 - type: integer Parameter C_IS_ACLK_ASYNC bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_ACLKEN_CONV_MODE bound to: 0 - type: integer Parameter C_ECC_MODE bound to: 0 - type: integer Parameter C_FIFO_MEMORY_TYPE bound to: auto - type: string Parameter C_USE_ADV_FEATURES bound to: 826486851 - type: integer Parameter C_PROG_EMPTY_THRESH bound to: 5 - type: integer Parameter C_PROG_FULL_THRESH bound to: 11 - type: integer Parameter G_INDX_SS_TREADY bound to: 0 - type: integer Parameter G_INDX_SS_TDATA bound to: 1 - type: integer Parameter G_INDX_SS_TSTRB bound to: 2 - type: integer Parameter G_INDX_SS_TKEEP bound to: 3 - type: integer Parameter G_INDX_SS_TLAST bound to: 4 - type: integer Parameter G_INDX_SS_TID bound to: 5 - type: integer Parameter G_INDX_SS_TDEST bound to: 6 - type: integer Parameter G_INDX_SS_TUSER bound to: 7 - type: integer Parameter G_MASK_SS_TREADY bound to: 1 - type: integer Parameter G_MASK_SS_TDATA bound to: 2 - type: integer Parameter G_MASK_SS_TSTRB bound to: 4 - type: integer Parameter G_MASK_SS_TKEEP bound to: 8 - type: integer Parameter G_MASK_SS_TLAST bound to: 16 - type: integer Parameter G_MASK_SS_TID bound to: 32 - type: integer Parameter G_MASK_SS_TDEST bound to: 64 - type: integer Parameter G_MASK_SS_TUSER bound to: 128 - type: integer Parameter G_TASK_SEVERITY_ERR bound to: 2 - type: integer Parameter G_TASK_SEVERITY_WARNING bound to: 1 - type: integer Parameter G_TASK_SEVERITY_INFO bound to: 0 - type: integer Parameter LP_CDC_SYNC_STAGES bound to: 3 - type: integer Parameter LP_CLOCKING_MODE bound to: independent_clock - type: string Parameter LP_ECC_MODE bound to: no_ecc - type: string Parameter LP_FIFO_DEPTH bound to: 2048 - type: integer Parameter LP_FIFO_MEMORY_TYPE bound to: auto - type: string Parameter LP_PACKET_FIFO bound to: true - type: string Parameter LP_PROG_EMPTY_THRESH bound to: 5 - type: integer Parameter LP_PROG_FULL_THRESH bound to: 11 - type: integer Parameter LP_RD_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter LP_RELATED_CLOCKS bound to: 0 - type: integer Parameter LP_TDATA_WIDTH bound to: 64 - type: integer Parameter LP_TDEST_WIDTH bound to: 1 - type: integer Parameter LP_TID_WIDTH bound to: 1 - type: integer Parameter LP_TUSER_WIDTH bound to: 4 - type: integer Parameter LP_USE_ADV_FEATURES bound to: 826486851 - type: integer Parameter LP_WR_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter LP_S_ACLKEN_CAN_TOGGLE bound to: 0 - type: integer Parameter LP_M_ACLKEN_CAN_TOGGLE bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:600] Parameter C_TDATA_WIDTH bound to: 64 - type: integer Parameter C_TID_WIDTH bound to: 1 - type: integer Parameter C_TDEST_WIDTH bound to: 1 - type: integer Parameter C_TUSER_WIDTH bound to: 4 - type: integer Parameter C_SIGNAL_SET bound to: 255 - type: integer Parameter C_S_ACLKEN_CAN_TOGGLE bound to: 0 - type: integer Parameter C_M_ACLKEN_CAN_TOGGLE bound to: 0 - type: integer Parameter G_INDX_SS_TREADY bound to: 0 - type: integer Parameter G_INDX_SS_TDATA bound to: 1 - type: integer Parameter G_INDX_SS_TSTRB bound to: 2 - type: integer Parameter G_INDX_SS_TKEEP bound to: 3 - type: integer Parameter G_INDX_SS_TLAST bound to: 4 - type: integer Parameter G_INDX_SS_TID bound to: 5 - type: integer Parameter G_INDX_SS_TDEST bound to: 6 - type: integer Parameter G_INDX_SS_TUSER bound to: 7 - type: integer Parameter G_MASK_SS_TREADY bound to: 1 - type: integer Parameter G_MASK_SS_TDATA bound to: 2 - type: integer Parameter G_MASK_SS_TSTRB bound to: 4 - type: integer Parameter G_MASK_SS_TKEEP bound to: 8 - type: integer Parameter G_MASK_SS_TLAST bound to: 16 - type: integer Parameter G_MASK_SS_TID bound to: 32 - type: integer Parameter G_MASK_SS_TDEST bound to: 64 - type: integer Parameter G_MASK_SS_TUSER bound to: 128 - type: integer Parameter G_TASK_SEVERITY_ERR bound to: 2 - type: integer Parameter G_TASK_SEVERITY_WARNING bound to: 1 - type: integer Parameter G_TASK_SEVERITY_INFO bound to: 0 - type: integer Parameter P_TPAYLOAD_WIDTH bound to: 87 - type: integer INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:810] Parameter C_TDATA_WIDTH bound to: 64 - type: integer Parameter C_TID_WIDTH bound to: 1 - type: integer Parameter C_TDEST_WIDTH bound to: 1 - type: integer Parameter C_TUSER_WIDTH bound to: 4 - type: integer Parameter C_TPAYLOAD_WIDTH bound to: 87 - type: integer Parameter C_SIGNAL_SET bound to: 255 - type: integer Parameter G_INDX_SS_TREADY bound to: 0 - type: integer Parameter G_INDX_SS_TDATA bound to: 1 - type: integer Parameter G_INDX_SS_TSTRB bound to: 2 - type: integer Parameter G_INDX_SS_TKEEP bound to: 3 - type: integer Parameter G_INDX_SS_TLAST bound to: 4 - type: integer Parameter G_INDX_SS_TID bound to: 5 - type: integer Parameter G_INDX_SS_TDEST bound to: 6 - type: integer Parameter G_INDX_SS_TUSER bound to: 7 - type: integer Parameter G_MASK_SS_TREADY bound to: 1 - type: integer Parameter G_MASK_SS_TDATA bound to: 2 - type: integer Parameter G_MASK_SS_TSTRB bound to: 4 - type: integer Parameter G_MASK_SS_TKEEP bound to: 8 - type: integer Parameter G_MASK_SS_TLAST bound to: 16 - type: integer Parameter G_MASK_SS_TID bound to: 32 - type: integer Parameter G_MASK_SS_TDEST bound to: 64 - type: integer Parameter G_MASK_SS_TUSER bound to: 128 - type: integer Parameter G_TASK_SEVERITY_ERR bound to: 2 - type: integer Parameter G_TASK_SEVERITY_WARNING bound to: 1 - type: integer Parameter G_TASK_SEVERITY_INFO bound to: 0 - type: integer Parameter P_TDATA_INDX bound to: 0 - type: integer Parameter P_TSTRB_INDX bound to: 64 - type: integer Parameter P_TKEEP_INDX bound to: 72 - type: integer Parameter P_TLAST_INDX bound to: 80 - type: integer Parameter P_TID_INDX bound to: 81 - type: integer Parameter P_TDEST_INDX bound to: 82 - type: integer Parameter P_TUSER_INDX bound to: 83 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (1#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:810] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:992] Parameter C_TDATA_WIDTH bound to: 64 - type: integer Parameter C_TID_WIDTH bound to: 1 - type: integer Parameter C_TDEST_WIDTH bound to: 1 - type: integer Parameter C_TUSER_WIDTH bound to: 4 - type: integer Parameter C_TPAYLOAD_WIDTH bound to: 87 - type: integer Parameter C_SIGNAL_SET bound to: 255 - type: integer Parameter G_INDX_SS_TREADY bound to: 0 - type: integer Parameter G_INDX_SS_TDATA bound to: 1 - type: integer Parameter G_INDX_SS_TSTRB bound to: 2 - type: integer Parameter G_INDX_SS_TKEEP bound to: 3 - type: integer Parameter G_INDX_SS_TLAST bound to: 4 - type: integer Parameter G_INDX_SS_TID bound to: 5 - type: integer Parameter G_INDX_SS_TDEST bound to: 6 - type: integer Parameter G_INDX_SS_TUSER bound to: 7 - type: integer Parameter G_MASK_SS_TREADY bound to: 1 - type: integer Parameter G_MASK_SS_TDATA bound to: 2 - type: integer Parameter G_MASK_SS_TSTRB bound to: 4 - type: integer Parameter G_MASK_SS_TKEEP bound to: 8 - type: integer Parameter G_MASK_SS_TLAST bound to: 16 - type: integer Parameter G_MASK_SS_TID bound to: 32 - type: integer Parameter G_MASK_SS_TDEST bound to: 64 - type: integer Parameter G_MASK_SS_TUSER bound to: 128 - type: integer Parameter G_TASK_SEVERITY_ERR bound to: 2 - type: integer Parameter G_TASK_SEVERITY_WARNING bound to: 1 - type: integer Parameter G_TASK_SEVERITY_INFO bound to: 0 - type: integer Parameter P_TDATA_INDX bound to: 0 - type: integer Parameter P_TSTRB_INDX bound to: 64 - type: integer Parameter P_TKEEP_INDX bound to: 72 - type: integer Parameter P_TLAST_INDX bound to: 80 - type: integer Parameter P_TID_INDX bound to: 81 - type: integer Parameter P_TDEST_INDX bound to: 82 - type: integer Parameter P_TUSER_INDX bound to: 83 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (2#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:992] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_aclken_converter_wrapper' (3#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_infrastructure_v1_1_vl_rfs.v:600] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_axis' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2225] Parameter CLOCKING_MODE bound to: independent_clock - type: string Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter PACKET_FIFO bound to: true - type: string Parameter FIFO_DEPTH bound to: 2048 - type: integer Parameter TDATA_WIDTH bound to: 64 - type: integer Parameter TID_WIDTH bound to: 1 - type: integer Parameter TDEST_WIDTH bound to: 1 - type: integer Parameter TUSER_WIDTH bound to: 4 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 826486851 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter PROG_FULL_THRESH bound to: 11 - type: integer Parameter PROG_EMPTY_THRESH bound to: 5 - type: integer Parameter CDC_SYNC_STAGES bound to: 3 - type: integer Parameter EN_ADV_FEATURE_AXIS bound to: 16'b0001110000001100 Parameter EN_ALMOST_FULL_INT bound to: 1'b1 Parameter EN_ALMOST_EMPTY_INT bound to: 1'b1 Parameter EN_DATA_VALID_INT bound to: 1'b1 Parameter EN_ADV_FEATURE_AXIS_INT bound to: 16'b0001110000001100 Parameter USE_ADV_FEATURES_INT bound to: 826486851 - type: integer Parameter PKT_SIZE_LT8 bound to: 1'b0 Parameter LOG_DEPTH_AXIS bound to: 11 - type: integer Parameter TDATA_OFFSET bound to: 64 - type: integer Parameter TSTRB_OFFSET bound to: 72 - type: integer Parameter TKEEP_OFFSET bound to: 80 - type: integer Parameter TID_OFFSET bound to: 81 - type: integer Parameter TDEST_OFFSET bound to: 82 - type: integer Parameter TUSER_OFFSET bound to: 86 - type: integer Parameter AXIS_DATA_WIDTH bound to: 87 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_PKT_MODE bound to: 1 - type: integer Parameter AXIS_FINAL_DATA_WIDTH bound to: 87 - type: integer Parameter TUSER_MAX_WIDTH bound to: 4013 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1111] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (4#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 11 - type: integer INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (5#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SRC_INPUT_REG bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (6#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 2048 - type: integer Parameter WRITE_DATA_WIDTH bound to: 87 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter PROG_FULL_THRESH bound to: 11 - type: integer Parameter USE_ADV_FEATURES bound to: 826486851 - type: integer Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 87 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 12 - type: integer Parameter PROG_EMPTY_THRESH bound to: 5 - type: integer Parameter DOUT_RESET_VALUE bound to: (null) - type: string Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 0 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 2048 - type: integer Parameter FIFO_SIZE bound to: 178176 - type: integer Parameter WR_WIDTH_LOG bound to: 7 - type: integer Parameter WR_DEPTH_LOG bound to: 11 - type: integer Parameter WR_PNTR_WIDTH bound to: 11 - type: integer Parameter RD_PNTR_WIDTH bound to: 11 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 9 - type: integer Parameter PE_THRESH_ADJ bound to: 3 - type: integer Parameter PF_THRESH_MIN bound to: 8 - type: integer Parameter PF_THRESH_MAX bound to: 2043 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 2043 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 12 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 12 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001110000001100 Parameter EN_OF bound to: 1'b0 Parameter EN_PF bound to: 1'b0 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b0 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b0 Parameter EN_PE bound to: 1'b0 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 11 - type: integer Parameter RESET_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (7#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 11 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (7#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 178176 - type: integer Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 87 - type: integer Parameter READ_DATA_WIDTH_A bound to: 87 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 87 - type: integer Parameter ADDR_WIDTH_A bound to: 11 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 87 - type: integer Parameter READ_DATA_WIDTH_B bound to: 87 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 87 - type: integer Parameter ADDR_WIDTH_B bound to: 11 - type: integer Parameter READ_RESET_VALUE_B bound to: (null) - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 87 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 87 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 87 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 87 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 2048 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 87 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 87 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 11 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 11 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 11 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 11 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 88 - type: integer Parameter rstb_loop_iter bound to: 88 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 87 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:484] WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:2882] INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (8#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 11 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (8#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] Parameter REG_WIDTH bound to: 11 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (9#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 5 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 12 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (9#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] Parameter REG_WIDTH bound to: 12 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (9#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized2' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 3 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 12 - type: integer WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized2' (9#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790] Parameter RST_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (10#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 2 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (10#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 3 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1574] INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1580] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (11#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 12 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (11#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 11 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (11#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:524] WARNING: [Synth 8-6014] Unused sequential element gen_pf_ic_rc.gae_ic_std.ram_aempty_i_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:744] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-4471] merging register 'gen_fwft.empty_fwft_fb_reg' into 'gen_fwft.empty_fwft_i_reg' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1294] WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1294] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (12#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_axis' (13#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2225] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_v2_0_2_top' (14#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/hdl/axis_data_fifo_v2_0_vl_rfs.v:54] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'axis_input_fifo' (15#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/synth/axis_input_fifo.v:58] WARNING: [Synth 8-3331] design axis_infrastructure_v1_1_0_util_aclken_converter_wrapper has unconnected port ACLK WARNING: [Synth 8-3331] design axis_infrastructure_v1_1_0_util_aclken_converter_wrapper has unconnected port ARESETN WARNING: [Synth 8-3331] design axis_infrastructure_v1_1_0_util_aclken_converter_wrapper has unconnected port S_ACLKEN WARNING: [Synth 8-3331] design axis_infrastructure_v1_1_0_util_aclken_converter_wrapper has unconnected port M_ACLKEN WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port sleep WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port rsta WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port regcea WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port injectsbiterra WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port injectdbiterra WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[86] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[85] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[84] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[83] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[82] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[81] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[80] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[79] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[78] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[77] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[76] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[75] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[74] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[73] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[72] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[71] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[70] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[69] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[68] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[67] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[66] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[65] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[64] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[63] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[62] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[61] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[60] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[59] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[58] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[57] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[56] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[55] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[54] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[53] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[52] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[51] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[50] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[49] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[48] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[47] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[46] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[45] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[44] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[43] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[42] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[41] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[40] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[39] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[38] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[37] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[36] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[35] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[34] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[33] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[32] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[31] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[30] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[29] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[28] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[27] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[26] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[25] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[24] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[23] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[22] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[21] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[20] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[19] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[18] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[17] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[16] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[15] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[14] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[13] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[12] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[11] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[10] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[9] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[8] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[7] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[6] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[5] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[4] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[3] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[2] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[1] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port dinb[0] WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port injectsbiterrb WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port injectdbiterrb WARNING: [Synth 8-3331] design xpm_cdc_single has unconnected port src_clk --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2296.441 ; gain = 267.406 ; free physical = 336 ; free virtual = 13447 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2302.375 ; gain = 273.340 ; free physical = 249 ; free virtual = 13359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2302.375 ; gain = 273.340 ; free physical = 249 ; free virtual = 13359 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2302.375 ; gain = 0.000 ; free physical = 222 ; free virtual = 13340 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo_ooc.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc] Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_ic.wpkt_cnt_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_ic.wpkt_cnt_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_ic.af_axis_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_ic.af_axis_cdc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'inst/gen_fifo.xpm_fifo_axis_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/axis_input_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/axis_input_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2477.062 ; gain = 0.000 ; free physical = 222 ; free virtual = 13087 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2481.031 ; gain = 3.969 ; free physical = 217 ; free virtual = 13083 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:41 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 374 ; free virtual = 13161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:41 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 373 ; free virtual = 13161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_pkt_fifo_ic.wpkt_cnt_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_pkt_fifo_ic.af_axis_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /\gaxis_rst_sync.xpm_cdc_sync_rst_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_fifo.xpm_fifo_axis_inst . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:41 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 371 ; free virtual = 13159 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 00 | 00 RRST_IN | 01 | 10 RRST_OUT | 10 | 11 RRST_EXIT | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:42 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 351 ; free virtual = 13149 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 4 Input 12 Bit Adders := 3 3 Input 12 Bit Adders := 2 2 Input 12 Bit Adders := 1 4 Input 11 Bit Adders := 5 2 Input 11 Bit Adders := 2 4 Input 2 Bit Adders := 1 +---XORs : 2 Input 12 Bit XORs := 2 2 Input 11 Bit XORs := 3 2 Input 1 Bit XORs := 52 +---Registers : 87 Bit Registers := 2 12 Bit Registers := 17 11 Bit Registers := 22 3 Bit Registers := 4 2 Bit Registers := 2 1 Bit Registers := 17 +---RAMs : 174K Bit RAMs := 1 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 33 4 Input 2 Bit Muxes := 7 2 Input 1 Bit Muxes := 7 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module xpm_cdc_sync_rst Detailed RTL Component Info : +---Registers : 3 Bit Registers := 1 Module xpm_cdc_gray Detailed RTL Component Info : +---XORs : 2 Input 11 Bit XORs := 1 2 Input 1 Bit XORs := 10 +---Registers : 11 Bit Registers := 5 Module xpm_cdc_single Detailed RTL Component Info : +---Registers : 3 Bit Registers := 1 Module xpm_counter_updn Detailed RTL Component Info : +---Adders : 4 Input 11 Bit Adders := 1 +---Registers : 11 Bit Registers := 1 Module xpm_counter_updn__parameterized0 Detailed RTL Component Info : +---Adders : 4 Input 11 Bit Adders := 1 +---Registers : 11 Bit Registers := 1 Module xpm_memory_base Detailed RTL Component Info : +---Registers : 87 Bit Registers := 2 +---RAMs : 174K Bit RAMs := 1 Module xpm_cdc_gray__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 11 Bit XORs := 1 2 Input 1 Bit XORs := 10 +---Registers : 11 Bit Registers := 4 Module xpm_fifo_reg_vec Detailed RTL Component Info : +---Registers : 11 Bit Registers := 1 Module xpm_cdc_gray__parameterized1 Detailed RTL Component Info : +---XORs : 2 Input 12 Bit XORs := 1 2 Input 1 Bit XORs := 11 +---Registers : 12 Bit Registers := 6 Module xpm_fifo_reg_vec__parameterized0 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 Module xpm_cdc_gray__parameterized2 Detailed RTL Component Info : +---XORs : 2 Input 12 Bit XORs := 1 2 Input 1 Bit XORs := 11 +---Registers : 12 Bit Registers := 4 Module xpm_fifo_reg_bit Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized1 Detailed RTL Component Info : +---Adders : 4 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 Module xpm_fifo_rst Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module xpm_counter_updn__parameterized2 Detailed RTL Component Info : +---Adders : 4 Input 12 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 Module xpm_counter_updn__parameterized3 Detailed RTL Component Info : +---Adders : 4 Input 11 Bit Adders := 1 +---Registers : 11 Bit Registers := 1 Module xpm_fifo_base Detailed RTL Component Info : +---Adders : 3 Input 12 Bit Adders := 2 4 Input 12 Bit Adders := 1 +---Registers : 12 Bit Registers := 2 1 Bit Registers := 7 +---Muxes : 2 Input 2 Bit Muxes := 31 4 Input 2 Bit Muxes := 7 4 Input 1 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 1 Module xpm_fifo_axis Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 11 Bit Adders := 2 +---Registers : 12 Bit Registers := 1 11 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3331] design xpm_memory_base has unconnected port rsta INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5784] Optimized 18 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 87 bits, new ram width 69 bits. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM gen_wr_a.gen_word_narrow.mem_reg to conserve power INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][64]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][65]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][66]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][67]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][68]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][69]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][70]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][71]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][72]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][73]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][74]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][75]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][76]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][77]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][78]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][79]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3886] merging instance 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][80]' (FDRE) to 'inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/i_2/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /i_2/\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][81] ) --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 1262 ; free virtual = 14086 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 2 K x 87(NO_CHANGE) | W | | 2 K x 87(WRITE_FIRST) | | R | Port A and B | 0 | 4 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 884 ; free virtual = 13719 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:01:01 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 870 ; free virtual = 13705 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |inst/\gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 2 K x 87(NO_CHANGE) | W | | 2 K x 87(WRITE_FIRST) | | R | Port A and B | 0 | 4 | +----------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:01:02 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 849 ; free virtual = 13684 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 745 ; free virtual = 13582 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 745 ; free virtual = 13582 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 743 ; free virtual = 13581 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 743 ; free virtual = 13581 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 743 ; free virtual = 13580 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 743 ; free virtual = 13580 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |CARRY4 | 35| |2 |LUT1 | 14| |3 |LUT2 | 106| |4 |LUT3 | 25| |5 |LUT4 | 39| |6 |LUT5 | 32| |7 |LUT6 | 41| |8 |RAMB36E1_1 | 4| |9 |FDRE | 462| |10 |FDSE | 10| +------+-----------+------+ Report Instance Areas: +------+---------------------------------------------+-----------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------------+-----------------------------------+------+ |1 |top | | 768| |2 | inst |axis_data_fifo_v2_0_2_top | 768| |3 | \gen_fifo.xpm_fifo_axis_inst |xpm_fifo_axis | 768| |4 | \gaxis_rst_sync.xpm_cdc_sync_rst_inst |xpm_cdc_sync_rst__3 | 3| |5 | \gaxis_pkt_fifo_ic.wpkt_cnt_cdc_inst |xpm_cdc_gray | 75| |6 | \gaxis_pkt_fifo_ic.af_axis_cdc_inst |xpm_cdc_single | 3| |7 | xpm_fifo_base_inst |xpm_fifo_base | 605| |8 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base | 4| |9 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized0__2 | 64| |10 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized1 | 94| |11 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized0 | 64| |12 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized2 | 70| |13 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn | 14| |14 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec | 29| |15 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized0 | 12| |16 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec_0 | 22| |17 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized0_1 | 24| |18 | \gen_fwft.rdpp1_inst |xpm_counter_updn__parameterized1 | 8| |19 | rdp_inst |xpm_counter_updn__parameterized2 | 42| |20 | rdpp1_inst |xpm_counter_updn__parameterized3 | 15| |21 | rst_d1_inst |xpm_fifo_reg_bit | 6| |22 | wrp_inst |xpm_counter_updn__parameterized2_2 | 30| |23 | wrpp1_inst |xpm_counter_updn__parameterized3_3 | 14| |24 | wrpp2_inst |xpm_counter_updn__parameterized0 | 14| |25 | xpm_fifo_rst_inst |xpm_fifo_rst | 40| |26 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__4 | 3| |27 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst | 3| +------+---------------------------------------------+-----------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 743 ; free virtual = 13580 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 114 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:00:58 . Memory (MB): peak = 2481.031 ; gain = 273.340 ; free physical = 795 ; free virtual = 13632 Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:01:06 . Memory (MB): peak = 2481.031 ; gain = 451.996 ; free physical = 795 ; free virtual = 13632 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2481.031 ; gain = 0.000 ; free physical = 858 ; free virtual = 13696 INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2481.031 ; gain = 0.000 ; free physical = 851 ; free virtual = 13690 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 110 Infos, 107 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:06 ; elapsed = 00:02:04 . Memory (MB): peak = 2481.031 ; gain = 859.961 ; free physical = 972 ; free virtual = 13812 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2481.031 ; gain = 0.000 ; free physical = 972 ; free virtual = 13812 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/axis_input_fifo.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP axis_input_fifo, cache-ID = 8437d0deae3abfd4 INFO: [Coretcl 2-1174] Renamed 26 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2505.047 ; gain = 0.000 ; free physical = 1017 ; free virtual = 13858 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/axis_input_fifo_synth_1/axis_input_fifo.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file axis_input_fifo_utilization_synth.rpt -pb axis_input_fifo_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu May 6 00:07:18 2021...