*** Running vivado
with args -log top_rod_efex.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_rod_efex.tcl
****** Vivado v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
**** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source top_rod_efex.tcl -notrace
source /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-synthesis.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.18.0
INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it...
INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd...
INFO: [Hog:ResetRepoFiles-0] Found modified *.bd files: BD/axi4_subsys.bd, will restore them...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Hog clean.
CRITICAL WARNING: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex not clean, commit hash, and version will be set to 0.
INFO: [Hog:GetVerFromSHA-0] No tag contains 3AD286A, will use most recent tag v0.1.10. As this is an official tag, patch will be incremented to 11.
INFO: [Hog:GetVerFromSHA-0] No tag contains FD3654A, will use most recent tag v0.1.10. As this is an official tag, patch will be incremented to 11.
INFO: [Hog:Msg-0] Git describe for 0000000 is: v0.1.10-10-geb12298-dirty
CRITICAL WARNING: [Hog:Msg-0] Repository is not clean, will use current SHA (eb12298) and create a dirty bitfile...
INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml and replacing placeholders with xml version 0001000B...
INFO: [Hog:CopyXMLsFromListFile-0] 19 lines read from ./Top/rod_efex/list/xml.lst
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod_common_IdVersion.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplane.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplaneRegisters.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBulkProc.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodChannel.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlash.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashChip.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashSectors.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodGpio.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodHwicap.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodI2C.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodInfrastructure.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodPktCaptureRegisters.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodProcessor.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTobProc.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTTCRegisters.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadc.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadcMeasurements.xml to /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] 19 file/s copied
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRod.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRod.vhd match.
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRod_common_IdVersion.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRod_common_IdVersion.vhd match.
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBackplane.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBackplane.vhd match.
CRITICAL WARNING: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBackplaneRegisters.vhd does not correspond to its XML /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBackplaneRegisters.xml, 6 line/s differ:
> constant N_SLV_CLOCK_STATUS: integer := 10;
< constant N_SLV_CLOCK_STAT: integer := 10;
> sel := ipbus_sel_t(to_unsigned(N_SLV_CLOCK_STATUS, IPBUS_SEL_WIDTH)); -- Clock_Status / base 0x0000000b / mask 0x0000000f
< sel := ipbus_sel_t(to_unsigned(N_SLV_CLOCK_STAT, IPBUS_SEL_WIDTH)); --manual hack
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBulkProc.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBulkProc.vhd match.
CRITICAL WARNING: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodChannel.vhd does not correspond to its XML /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodChannel.xml, 6 line/s differ:
> constant N_SLV_AURORA_AUTORESET_DISABLE: integer := 13;
< constant N_SLV_AURORA_CHANNEL_DISABLE: integer := 13;
> constant N_SLV_AURORA_AUTO_RESET_COUNT: integer := 25;
< constant N_SLV_AURORA_AUTO_RESET_COUNT: integer := 25;
> sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_AUTORESET_DISABLE, IPBUS_SEL_WIDTH)); -- Aurora_autoreset_disable / base 0x0000000d / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_CHANNEL_DISABLE, IPBUS_SEL_WIDTH)); -- Aurora_channel_disable / base 0x0000000d / mask 0x0000001f
> sel := ipbus_sel_t(to_unsigned(N_SLV_UFC_PARITY_ERROR_COUNT, IPBUS_SEL_WIDTH)); -- UFC_parity_error_count / base 0x00000019 / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_UFC_PARITY_ERROR_COUNT, IPBUS_SEL_WIDTH)); -- UFC_CRC_error_count / base 0x00000019 / mask 0x0000001f
> sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_AUTO_RESET_COUNT, IPBUS_SEL_WIDTH)); -- Aurora_auto_reset_count / base 0x0000001a / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_AUTO_RESET_COUNT, IPBUS_SEL_WIDTH)); -- AURORA_AUTO_RESET_COUNT / base 0x0000001A / mask 0x0000001f
> sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_CHAN_UP_TIME, IPBUS_SEL_WIDTH)); -- AURORA_CHAN_UP_TIME / base 0x0000001b / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_AURORA_CHAN_UP_TIME, IPBUS_SEL_WIDTH)); -- AURORA_AUTO_RESET_COUNT / base 0x0000001B / mask 0x0000001f
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlash.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlashChip.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlashSectors.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodGpio.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodHwicap.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodI2C.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodInfrastructure.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodPktCaptureRegisters.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodPktCaptureRegisters.vhd match.
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodProcessor.xml and /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodProcessor.vhd match.
CRITICAL WARNING: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodTobProc.vhd does not correspond to its XML /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodTobProc.xml, 6 line/s differ:
> constant N_SLV_TOB_TIMEOUT_VALUES: integer := 16;
< constant N_SLV_TOB_TIMEOUT: integer := 16;
> constant N_SLV_TOB_ERROR_COUNT: integer := 17;
< constant N_SLV_TOB_error_count: integer := 17;
> constant N_SLV_TOB_ERROR_RESET: integer := 18;
< constant N_SLV_PKT_CAPTURE_REGS: integer := 18;
> constant N_SLV_PKT_CAPTURE_REGS: integer := 19;
< constant N_SLV_tob_proc_reset: integer := 19;
> sel := ipbus_sel_t(to_unsigned(N_SLV_TOB_TIMEOUT_VALUES, IPBUS_SEL_WIDTH)); -- Tob_timeout_values / base 0x00000010 / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_TOB_TIMEOUT, IPBUS_SEL_WIDTH));
> sel := ipbus_sel_t(to_unsigned(N_SLV_TOB_ERROR_COUNT, IPBUS_SEL_WIDTH)); -- Tob_error_count / base 0x00000012 / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_TOB_error_count, IPBUS_SEL_WIDTH));
> sel := ipbus_sel_t(to_unsigned(N_SLV_TOB_ERROR_RESET, IPBUS_SEL_WIDTH)); -- Tob_error_reset / base 0x00000013 / mask 0x0000001f
< sel := ipbus_sel_t(to_unsigned(N_SLV_tob_proc_reset, IPBUS_SEL_WIDTH));
> sel := ipbus_sel_t(to_unsigned(N_SLV_PKT_CAPTURE_REGS, IPBUS_SEL_WIDTH)); -- pkt_capture_regs / base 0x00000018 / mask 0x00000018
< sel := ipbus_sel_t(to_unsigned(N_SLV_PKT_CAPTURE_REGS, IPBUS_SEL_WIDTH)); -- pkt_capture_regs / base 0x00000010 / mask 0x00000018
CRITICAL WARNING: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodTTCRegisters.vhd does not correspond to its XML /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodTTCRegisters.xml, 6 line/s differ:
> sel := ipbus_sel_t(to_unsigned(N_SLV_TOTAL_EVENT_COUNT_MSB, IPBUS_SEL_WIDTH)); -- total_event_count_msb / base 0x0000000e / mask 0x0000000f
< sel := ipbus_sel_t(to_unsigned(N_SLV_TOTAL_EVENT_COUNT_MSB, IPBUS_SEL_WIDTH)); -- total_event_count / base 0x0000000d / mask 0x0000000f
> sel := ipbus_sel_t(to_unsigned(N_SLV_ORBIT, IPBUS_SEL_WIDTH)); -- orbit / base 0x0000000f / mask 0x0000000f
< sel := ipbus_sel_t(to_unsigned(N_SLV_ORBIT, IPBUS_SEL_WIDTH)); -- orbit / base 0x0000000e / mask 0x0000000f
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodXadc.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodXadcMeasurements.xml as no VHDL file was specified.
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:GitVersion-0] Found Git version: git version 2.18.0
INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/versions.txt...
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.1.10-10-geb12298-dirty...
INFO: [Hog:Msg-0] Evaluating non committed changes...
WARNING: [Hog:Msg-0] Found non committed changes:...
diff --git a/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci b/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci
index bde36d4..beefd54 100644
--- a/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci
+++ b/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci
@@ -78,7 +78,7 @@
1
14
AXI4
- 32
+ 1
0
0
virtex7
diff --git a/IP/packet_processor/ila_self_reset/ila_self_reset.xci b/IP/packet_processor/ila_self_reset/ila_self_reset.xci
index 43bfa08..8a7a848 100644
--- a/IP/packet_processor/ila_self_reset/ila_self_reset.xci
+++ b/IP/packet_processor/ila_self_reset/ila_self_reset.xci
@@ -78,7 +78,7 @@
1
6
AXI4
- 32
+ 1
0
0
virtex7
diff --git a/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci b/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci
index a78ef20..df8317b 100644
--- a/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci
+++ b/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci
@@ -78,7 +78,7 @@
1
6
AXI4
- 32
+ 1
0
0
virtex7
------------------------- PRE SYNTHESIS -------------------------
06/05/2021 at 00:09:23
Firmware date and time: '05052021', '00225518'
Global SHA: eb12298, VER: 0.0.0
Constraints SHA: 43AD2A3, VER: 0.1.5
IPbus XML SHA: FD3654A, VER: 0.1.11
Top SHA: ABC60DD, VER: 0.0.6
Hog SHA: 48C98B7, VER: 3.8.0
--- Libraries ---
rod_efex SHA: 3AD286A, VER: 0.1.11
--- External Libraries ---
-----------------------------------------------------------------
INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml
INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2021.1 in .gitlab-ci.yml.
INFO: [Hog:GitVersion-0] Found Git version: git version 2.18.0
INFO: [Hog:Msg-0] Opening project rod_efex...
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
open_project: Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1837.523 ; gain = 236.262 ; free physical = 5723 ; free virtual = 18727
INFO: [Hog:Msg-0] Checking rod_efex list files...
CRITICAL WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/coe/DPram_32b_ed.coe not found in project source files! Was it removed from the project?
CRITICAL WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/test_bench_fifo/test_bench_fifo.xci not found in project IPs! Was it removed from the project?
CRITICAL WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/test_bench_fifo/test_bench_fifo.xci not found in project IPs! Was it removed from the project?
CRITICAL WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/test_bench_fifo/test_bench_fifo.xci not found in project IPs! Was it removed from the project?
CRITICAL WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/test_bench_fifo/test_bench_fifo.xci not found in project IPs! Was it removed from the project?
CRITICAL WARNING: [Hog:Msg-0] Number of errors: 5
INFO: [Hog:Msg-0] All done.
Command: synth_design -top top_rod_efex -part xc7vx550tffg1927-2 -fanout_limit 400 -directive PerformanceOptimized -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Device 21-403] Loading part xc7vx550tffg1927-2
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 13870
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Starting RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:56 . Memory (MB): peak = 2464.883 ; gain = 8.160 ; free physical = 6317 ; free virtual = 19358
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WARNING: [Synth 8-2048] function gpo_bit_used does not always return a value [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1139]
WARNING: [Synth 8-1090] 'jtag_axi_v1_2_10_jtag_axi' is not compiled in library jtag_axi [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:57]
WARNING: [Synth 8-2488] overwriting existing primary unit crc [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:25]
INFO: [Synth 8-638] synthesizing module 'top_rod_efex' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:328]
Parameter Module_ID bound to: 32'b01000000000000000000000011101101
Parameter GLOBAL_DATE bound to: 32'b00000101000001010010000000100001
Parameter GLOBAL_TIME bound to: 32'b00000000001000100101010100011000
Parameter GLOBAL_VER bound to: 32'b00000000000000000000000000000000
Parameter GLOBAL_SHA bound to: 32'b00001110101100010010001010011000
Parameter TOP_VER bound to: 32'b00000000000000000000000000000110
Parameter TOP_SHA bound to: 32'b00001010101111000110000011011101
Parameter CON_VER bound to: 32'b00000000000000010000000000000101
Parameter CON_SHA bound to: 32'b00000100001110101101001010100011
Parameter HOG_VER bound to: 32'b00000011000010000000000000000000
Parameter HOG_SHA bound to: 32'b00000100100011001001100010110111
Parameter XML_SHA bound to: 32'b00001111110100110110010101001010
Parameter XML_VER bound to: 32'b00000000000000010000000000001011
Parameter ROD_EFEX_SHA bound to: 32'b00000011101011010010100001101010
Parameter ROD_EFEX_VER bound to: 32'b00000000000000010000000000001011
Parameter jfex_rod bound to: 0 - type: integer
Parameter efex_rod bound to: 1 - type: integer
Parameter golden_rod bound to: 0 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter max_count bound to: 32'b00000000000000001111111111111111
INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:8' bound to instance 'reset_top' of component 'system_top_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1807]
INFO: [Synth 8-638] synthesizing module 'system_top_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21]
Parameter max_count bound to: 65535 - type: integer
INFO: [Synth 8-256] done synthesizing module 'system_top_reset' (1#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21]
Parameter max_count bound to: 32'b00000010011000100101101000000000
INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:8' bound to instance 'phy_reset' of component 'system_top_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1826]
INFO: [Synth 8-638] synthesizing module 'system_top_reset__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21]
Parameter max_count bound to: 40000000 - type: integer
INFO: [Synth 8-256] done synthesizing module 'system_top_reset__parameterized1' (1#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21]
INFO: [Synth 8-3491] module 'packet_processor_clock' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/packet_processor_clock_stub.vhdl:5' bound to instance 'proc_clock_gen' of component 'packet_processor_clock' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1845]
INFO: [Synth 8-638] synthesizing module 'packet_processor_clock' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/packet_processor_clock_stub.vhdl:15]
INFO: [Synth 8-3491] module 'vio_top' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_top_stub.vhdl:5' bound to instance 'top_vio' of component 'vio_top' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1857]
INFO: [Synth 8-638] synthesizing module 'vio_top' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_top_stub.vhdl:26]
WARNING: [Synth 8-5640] Port 'pkt_clk' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:352]
WARNING: [Synth 8-5640] Port 'pkt_aresetn' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:352]
WARNING: [Synth 8-5640] Port 'rod_gp_led' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:352]
WARNING: [Synth 8-5640] Port 'fp_gp_led_b' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:352]
Parameter GLOBAL_DATE bound to: 84221985 - type: integer
Parameter GLOBAL_TIME bound to: 2250008 - type: integer
Parameter GLOBAL_VER bound to: 0 - type: integer
Parameter GLOBAL_SHA bound to: 246489752 - type: integer
Parameter TOP_VER bound to: 6 - type: integer
Parameter TOP_SHA bound to: 180117725 - type: integer
Parameter CON_VER bound to: 65541 - type: integer
Parameter CON_SHA bound to: 70963875 - type: integer
Parameter HOG_VER bound to: 50855936 - type: integer
Parameter HOG_SHA bound to: 76322999 - type: integer
Parameter XML_SHA bound to: 265512266 - type: integer
Parameter XML_VER bound to: 65547 - type: integer
Parameter ROD_EFEX_SHA bound to: 61679722 - type: integer
Parameter ROD_EFEX_VER bound to: 65547 - type: integer
Parameter jfex_rod bound to: 0 - type: integer
Parameter efex_rod bound to: 1 - type: integer
Parameter golden_rod bound to: 0 - type: integer
Parameter Module_ID bound to: 1073742061 - type: integer
Parameter BuildTimeAndDate bound to: 84221985 - type: integer
Parameter FirmwareVersion bound to: 246489752 - type: integer
INFO: [Synth 8-3491] module 'ROD_system' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:40' bound to instance 'ipbus_blk' of component 'ROD_system' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1880]
INFO: [Synth 8-638] synthesizing module 'ROD_system' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:207]
Parameter GLOBAL_DATE bound to: 84221985 - type: integer
Parameter GLOBAL_TIME bound to: 2250008 - type: integer
Parameter GLOBAL_VER bound to: 0 - type: integer
Parameter GLOBAL_SHA bound to: 246489752 - type: integer
Parameter TOP_VER bound to: 6 - type: integer
Parameter TOP_SHA bound to: 180117725 - type: integer
Parameter CON_VER bound to: 65541 - type: integer
Parameter CON_SHA bound to: 70963875 - type: integer
Parameter HOG_VER bound to: 50855936 - type: integer
Parameter HOG_SHA bound to: 76322999 - type: integer
Parameter XML_SHA bound to: 265512266 - type: integer
Parameter XML_VER bound to: 65547 - type: integer
Parameter ROD_EFEX_SHA bound to: 61679722 - type: integer
Parameter ROD_EFEX_VER bound to: 65547 - type: integer
Parameter jfex_rod bound to: 0 - type: integer
Parameter efex_rod bound to: 1 - type: integer
Parameter golden_rod bound to: 0 - type: integer
Parameter Module_ID bound to: 1073742061 - type: integer
Parameter BuildTimeAndDate bound to: 84221985 - type: integer
Parameter FirmwareVersion bound to: 246489752 - type: integer
INFO: [Synth 8-3491] module 'addr_sel_rom' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:59' bound to instance 'address_sel' of component 'addr_sel_rom' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:541]
INFO: [Synth 8-638] synthesizing module 'addr_sel_rom' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:69]
INFO: [Synth 8-256] done synthesizing module 'addr_sel_rom' (2#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:69]
Parameter GLOBAL_DATE bound to: 84221985 - type: integer
Parameter GLOBAL_TIME bound to: 2250008 - type: integer
Parameter GLOBAL_VER bound to: 0 - type: integer
Parameter GLOBAL_SHA bound to: 246489752 - type: integer
Parameter TOP_VER bound to: 6 - type: integer
Parameter TOP_SHA bound to: 180117725 - type: integer
Parameter CON_VER bound to: 65541 - type: integer
Parameter CON_SHA bound to: 70963875 - type: integer
Parameter HOG_VER bound to: 50855936 - type: integer
Parameter HOG_SHA bound to: 76322999 - type: integer
Parameter XML_SHA bound to: 265512266 - type: integer
Parameter XML_VER bound to: 65547 - type: integer
Parameter ROD_EFEX_SHA bound to: 61679722 - type: integer
Parameter ROD_EFEX_VER bound to: 65547 - type: integer
Parameter jfex_rod bound to: 0 - type: integer
Parameter efex_rod bound to: 1 - type: integer
Parameter golden_rod bound to: 0 - type: integer
Parameter Module_ID bound to: 1073742061 - type: integer
Parameter BuildTimeAndDate bound to: 84221985 - type: integer
Parameter FirmwareVersion bound to: 246489752 - type: integer
INFO: [Synth 8-3491] module 'common_IdVersion_regs' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:37' bound to instance 'common_regs' of component 'common_IdVersion_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:555]
INFO: [Synth 8-638] synthesizing module 'common_IdVersion_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:82]
Parameter GLOBAL_DATE bound to: 84221985 - type: integer
Parameter GLOBAL_TIME bound to: 2250008 - type: integer
Parameter GLOBAL_VER bound to: 0 - type: integer
Parameter GLOBAL_SHA bound to: 246489752 - type: integer
Parameter TOP_VER bound to: 6 - type: integer
Parameter TOP_SHA bound to: 180117725 - type: integer
Parameter CON_VER bound to: 65541 - type: integer
Parameter CON_SHA bound to: 70963875 - type: integer
Parameter HOG_VER bound to: 50855936 - type: integer
Parameter HOG_SHA bound to: 76322999 - type: integer
Parameter XML_SHA bound to: 265512266 - type: integer
Parameter XML_VER bound to: 65547 - type: integer
Parameter ROD_EFEX_SHA bound to: 61679722 - type: integer
Parameter ROD_EFEX_VER bound to: 65547 - type: integer
Parameter ROD_JFEX_SHA bound to: 32'b00000000000000000000000000001100
Parameter ROD_JFEX_VER bound to: 32'b00000000000000000000000000001101
Parameter jfex_rod bound to: 0 - type: integer
Parameter efex_rod bound to: 1 - type: integer
Parameter golden bound to: 0 - type: integer
Parameter Module_ID bound to: 1073742061 - type: integer
Parameter BuildTimeAndDate bound to: 84221985 - type: integer
Parameter FirmwareVersion bound to: 246489752 - type: integer
WARNING: [Synth 8-3819] Generic 'golden_rod' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:555]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 5 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 3 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (3#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74]
Parameter N_CTRL bound to: 0 - type: integer
Parameter N_STAT bound to: 1 - type: integer
Parameter SWAP_ORDER bound to: 0 - type: bool
WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66]
WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67]
WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68]
WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82]
INFO: [Synth 8-638] synthesizing module 'syncreg_r' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58]
Parameter SIZE bound to: 32 - type: integer
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'syncreg_r' (4#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58]
INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v' (5#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:133]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:134]
INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74]
Parameter N_CTRL bound to: 0 - type: integer
Parameter N_STAT bound to: 2 - type: integer
Parameter SWAP_ORDER bound to: 0 - type: bool
WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66]
WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67]
WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68]
WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82]
INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v__parameterized0' (5#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:203]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:205]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:223]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:225]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68]
Parameter N_CTRL bound to: 0 - type: integer
Parameter N_STAT bound to: 2 - type: integer
Parameter SWAP_ORDER bound to: 0 - type: bool
WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:60]
WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:61]
WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:62]
WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:63]
WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:73]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (6#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:237]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:239]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:266]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:268]
INFO: [Synth 8-3491] module 'dna_reader' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:30' bound to instance 'fpga_dna' of component 'dna_reader' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:270]
INFO: [Synth 8-638] synthesizing module 'dna_reader' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38]
Parameter SIM_DNA_VALUE bound to: 60'b000100100011010001010110011110001001101010111100110111100010
INFO: [Synth 8-113] binding component instance 'DNA_PORT_inst' to cell 'DNA_PORT' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:67]
WARNING: [Synth 8-614] signal 'reset_reg' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:84]
INFO: [Synth 8-256] done synthesizing module 'dna_reader' (7#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'common_IdVersion_regs' (8#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:82]
INFO: [Synth 8-3491] module 'ipbus_rod' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:139' bound to instance 'ipbus' of component 'ipbus_rod' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:601]
INFO: [Synth 8-638] synthesizing module 'ipbus_rod' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:214]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_clocks' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:60' bound to instance 'example_clocks' of component 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:679]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79]
Parameter CE_TYPE bound to: SYNC - type: string
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_I_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
Parameter STARTUP_SYNC bound to: FALSE - type: string
INFO: [Synth 8-113] binding component instance 'bufg_clkin1' to cell 'BUFGCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:154]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'lock_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:157]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84]
Parameter INITIALISE bound to: 1'b0
Parameter DEPTH bound to: 5 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'data_sync_reg0' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:113]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:126]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:138]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:150]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:162]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_sync_block' (9#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'mmcm_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:178]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87]
Parameter INITIALISE bound to: 1'b1
Parameter DEPTH bound to: 5 - type: integer
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'reset_sync0' to cell 'FDPE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:109]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'reset_sync1' to cell 'FDPE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:121]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'reset_sync2' to cell 'FDPE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:133]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'reset_sync3' to cell 'FDPE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:145]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_PRE_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'reset_sync4' to cell 'FDPE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:157]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_reset_sync' (10#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_clk_wiz' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:71' bound to instance 'clock_generator' of component 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:190]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT1_DIVIDE bound to: 10 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT3_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT4_CASCADE bound to: 0 - type: bool
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool
Parameter COMPENSATION bound to: ZHOLD - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
Parameter IS_PSEN_INVERTED bound to: 1'b0
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
Parameter IS_RST_INVERTED bound to: 1'b0
Parameter REF_JITTER1 bound to: 0.010000 - type: double
Parameter REF_JITTER2 bound to: 0.000000 - type: double
Parameter SS_EN bound to: FALSE - type: string
Parameter SS_MODE bound to: CENTER_HIGH - type: string
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
Parameter STARTUP_WAIT bound to: 0 - type: bool
INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:122]
Parameter CE_TYPE bound to: SYNC - type: string
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_I_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
Parameter STARTUP_SYNC bound to: FALSE - type: string
INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:201]
Parameter CE_TYPE bound to: SYNC - type: string
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_I_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
Parameter STARTUP_SYNC bound to: FALSE - type: string
INFO: [Synth 8-113] binding component instance 'clkout2_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:207]
Parameter CE_TYPE bound to: SYNC - type: string
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_I_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
Parameter STARTUP_SYNC bound to: FALSE - type: string
INFO: [Synth 8-113] binding component instance 'clkout3_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:213]
INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:219]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_clk_wiz' (11#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_clocks' (12#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_resets' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:57' bound to instance 'example_resets' of component 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:711]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'dcm_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:131]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'glbl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:145]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'axi_lite_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:159]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'gtx_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:187]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'chk_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:219]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_resets' (13#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84]
INFO: [Synth 8-3491] module 'eth_7s_rgmii' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:94' bound to instance 'trimac_fifo_block' of component 'eth_7s_rgmii' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:903]
INFO: [Synth 8-638] synthesizing module 'eth_7s_rgmii' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212]
WARNING: [Synth 8-5640] Port 'rx_statistics_vector' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220]
WARNING: [Synth 8-5640] Port 'rx_statistics_valid' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220]
WARNING: [Synth 8-5640] Port 'tx_statistics_vector' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220]
WARNING: [Synth 8-5640] Port 'tx_statistics_valid' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:68' bound to instance 'trimac_sup_block' of component 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:528]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support_resets' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:62' bound to instance 'tri_mode_ethernet_mac_support_resets_i' of component 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:284]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'idelayctrl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:108]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support_resets' (14#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72]
Parameter SIM_DEVICE bound to: 7SERIES - type: string
INFO: [Synth 8-113] binding component instance 'tri_mode_ethernet_mac_idelayctrl_common_i' to cell 'IDELAYCTRL' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:295]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:5' bound to instance 'tri_mode_ethernet_mac_i' of component 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:309]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:67]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support' (15#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164]
INFO: [Synth 8-3491] module 'rgmii_rx_fifo_2' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:5' bound to instance 'trimac_read_fifo_2' of component 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:642]
INFO: [Synth 8-638] synthesizing module 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:26]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'rx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:684]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'tx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:692]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_axi_lite_sm' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:69' bound to instance 'axi_lite_controller' of component 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:761]
INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105]
INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'update_speed_sync_inst' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:278]
INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' (16#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105]
WARNING: [Synth 8-3848] Net tx_axis_fifo_tready in module/entity eth_7s_rgmii does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:138]
WARNING: [Synth 8-3848] Net rx_fifo_overflow in module/entity eth_7s_rgmii does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:206]
INFO: [Synth 8-256] done synthesizing module 'eth_7s_rgmii' (17#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212]
INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50]
INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24]
Parameter INIT bound to: 16'b0000000000000000
INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:30]
INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (18#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24]
INFO: [Synth 8-638] synthesizing module 'led_stretcher' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25]
Parameter WIDTH bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'led_stretcher' (19#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25]
WARNING: [Synth 8-6014] Unused sequential element rctr_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:133]
INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (20#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:67]
Parameter MAC_CFG bound to: 1'b0
Parameter IP_CFG bound to: 1'b0
Parameter BUFWIDTH bound to: 4 - type: integer
Parameter INTERNALWIDTH bound to: 1 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
Parameter IPBUSPORT bound to: 16'b1100001101010001
Parameter SECONDARYPORT bound to: 1'b0
Parameter N_OOB bound to: 0 - type: integer
WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:61]
WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:62]
INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_if_flat.vhd:65]
Parameter BUFWIDTH bound to: 4 - type: integer
Parameter INTERNALWIDTH bound to: 1 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
Parameter IPBUSPORT bound to: 16'b1100001101010001
Parameter SECONDARYPORT bound to: 1'b0
INFO: [Synth 8-638] synthesizing module 'udp_rarp_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:24]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:55]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:56]
WARNING: [Synth 8-6014] Unused sequential element pkt_data_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:112]
WARNING: [Synth 8-6014] Unused sequential element addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:145]
WARNING: [Synth 8-6014] Unused sequential element tick_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:164]
WARNING: [Synth 8-6014] Unused sequential element t_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:195]
WARNING: [Synth 8-6014] Unused sequential element rarp_req_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:220]
INFO: [Synth 8-256] done synthesizing module 'udp_rarp_block' (21#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:24]
INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:28]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:45]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:47]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:81]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:82]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:225]
INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (22#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:28]
INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:31]
WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:54]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:114]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element ping_we_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:179]
WARNING: [Synth 8-6014] Unused sequential element clr_sum_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:251]
WARNING: [Synth 8-6014] Unused sequential element int_valid_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:252]
WARNING: [Synth 8-6014] Unused sequential element int_data_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:253]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:351]
INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (23#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:31]
INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd:30]
INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_block' (24#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd:30]
INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:33]
WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:60]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:63]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element next_low_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:409]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:486]
INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (25#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:33]
INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_resend.vhd:23]
INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (26#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_resend.vhd:23]
INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:28]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:43]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:97]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:98]
WARNING: [Synth 8-6014] Unused sequential element request_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:183]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:247]
INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (27#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:28]
INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:49]
Parameter BUFWIDTH bound to: 4 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
WARNING: [Synth 8-6014] Unused sequential element bufsize_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:101]
WARNING: [Synth 8-6014] Unused sequential element nbuf_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:102]
WARNING: [Synth 8-6014] Unused sequential element new_event_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:149]
WARNING: [Synth 8-6014] Unused sequential element async_ready_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:150]
WARNING: [Synth 8-6014] Unused sequential element rarp_arp_ping_ipbus_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:156]
WARNING: [Synth 8-6014] Unused sequential element payload_status_resend_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:158]
WARNING: [Synth 8-6014] Unused sequential element got_event_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:239]
WARNING: [Synth 8-6014] Unused sequential element event_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:240]
INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (28#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:49]
INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_byte_sum.vhd:25]
INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (29#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_byte_sum.vhd:25]
INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_do_rx_reset.vhd:20]
INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (30#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_do_rx_reset.vhd:20]
INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_packet_parser.vhd:37]
Parameter IPBUSPORT bound to: 16'b1100001101010001
Parameter SECONDARYPORT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (31#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_packet_parser.vhd:37]
INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:56]
WARNING: [Synth 8-6014] Unused sequential element rxram_dropped_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:74]
WARNING: [Synth 8-6014] Unused sequential element rxram_end_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:97]
WARNING: [Synth 8-6014] Unused sequential element rxram_send_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:98]
WARNING: [Synth 8-6014] Unused sequential element dia_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:154]
WARNING: [Synth 8-6014] Unused sequential element addra_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:155]
WARNING: [Synth 8-6014] Unused sequential element wea_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:156]
INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (32#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:56]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram.vhd:22]
Parameter BUFWIDTH bound to: 1 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (33#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
Parameter BUFWIDTH bound to: 1 - type: integer
WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (34#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_shim.vhd:30]
Parameter BUFWIDTH bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (35#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_shim.vhd:30]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:22]
Parameter BUFWIDTH bound to: 4 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:36]
WARNING: [Synth 8-6014] Unused sequential element byte4_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:56]
WARNING: [Synth 8-6014] Unused sequential element byte3_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:57]
WARNING: [Synth 8-6014] Unused sequential element byte2_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:58]
WARNING: [Synth 8-6014] Unused sequential element byte1_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:59]
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (36#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
Parameter BUFWIDTH bound to: 4 - type: integer
WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (36#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:23]
WARNING: [Synth 8-6014] Unused sequential element rxpayload_dropped_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:35]
WARNING: [Synth 8-6014] Unused sequential element pkt_rcvd_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:36]
INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (37#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:23]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:22]
Parameter BUFWIDTH bound to: 4 - type: integer
Parameter ADDRWIDTH bound to: 11 - type: integer
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (38#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
Parameter BUFWIDTH bound to: 4 - type: integer
WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (38#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:52]
Parameter INTERNAL_ONLY bound to: 1'b0
WARNING: [Synth 8-6014] Unused sequential element low_addr_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:139]
WARNING: [Synth 8-6014] Unused sequential element next_mac_tx_buf_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:171]
WARNING: [Synth 8-6014] Unused sequential element default_mode.ipbus_out_valid_int_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:675]
INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (39#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:52]
INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:35]
Parameter BUFWIDTH bound to: 4 - type: integer
WARNING: [Synth 8-6014] Unused sequential element req_resend_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:64]
WARNING: [Synth 8-6014] Unused sequential element req_not_found_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:65]
WARNING: [Synth 8-6014] Unused sequential element resend_buf_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (40#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:35]
INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:43]
Parameter BUFWIDTH bound to: 4 - type: integer
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:48]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:49]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (41#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'UDP_if' (42#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_if_flat.vhd:65]
INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor.vhd:34]
INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_if.vhd:31]
INFO: [Synth 8-256] done synthesizing module 'transactor_if' (43#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_if.vhd:31]
INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_sm.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (44#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_sm.vhd:39]
INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_cfg.vhd:27]
INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (45#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_cfg.vhd:27]
INFO: [Synth 8-256] done synthesizing module 'transactor' (46#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor.vhd:34]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (47#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:67]
INFO: [Synth 8-638] synthesizing module 'ipbus_example' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 4 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 3 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (47#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
INFO: [Synth 8-638] synthesizing module 'ipbus_axi4_bridge' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'ipbus_axi4_bridge' (48#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66]
WARNING: [Synth 8-3848] Net nuke in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:33]
WARNING: [Synth 8-3848] Net soft_rst in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:34]
WARNING: [Synth 8-3848] Net userled in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:35]
INFO: [Synth 8-256] done synthesizing module 'ipbus_example' (49#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60]
WARNING: [Synth 8-3848] Net tx_axis_fifo_tvalid in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:537]
WARNING: [Synth 8-3848] Net tx_axis_fifo_tdata in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:535]
WARNING: [Synth 8-3848] Net tx_axis_fifo_tlast in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:538]
WARNING: [Synth 8-3848] Net pause_val in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:565]
INFO: [Synth 8-256] done synthesizing module 'ipbus_rod' (50#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:214]
INFO: [Synth 8-3491] module 'axi4_subsys_wrapper' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:14' bound to instance 'axi4_subsys' of component 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:672]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80]
INFO: [Synth 8-3491] module 'axi4_subsys' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4596' bound to instance 'axi4_subsys_i' of component 'axi4_subsys' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:231]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4667]
INFO: [Synth 8-3491] module 'axi4_subsys_axi_emc_0_0' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:59' bound to instance 'axi_emc_0' of component 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:5341]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_INSTANCE bound to: axi_emc_inst - type: string
Parameter C_AXI_CLK_PERIOD_PS bound to: 30769 - type: integer
Parameter C_LFLASH_PERIOD_PS bound to: 30769 - type: integer
Parameter C_LINEAR_FLASH_SYNC_BURST bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_PORT_DIFF bound to: 0 - type: integer
Parameter C_S_AXI_REG_ADDR_WIDTH bound to: 5 - type: integer
Parameter C_S_AXI_REG_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_EN_REG bound to: 0 - type: integer
Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer
Parameter C_S_AXI_MEM0_BASEADDR bound to: 32'b01100000000000000000000000000000
Parameter C_S_AXI_MEM0_HIGHADDR bound to: 32'b01111111111111111111111111111111
Parameter C_S_AXI_MEM1_BASEADDR bound to: 32'b10110000000000000000000000000000
Parameter C_S_AXI_MEM1_HIGHADDR bound to: 32'b10111111111111111111111111111111
Parameter C_S_AXI_MEM2_BASEADDR bound to: 32'b11000000000000000000000000000000
Parameter C_S_AXI_MEM2_HIGHADDR bound to: 32'b11001111111111111111111111111111
Parameter C_S_AXI_MEM3_BASEADDR bound to: 32'b11010000000000000000000000000000
Parameter C_S_AXI_MEM3_HIGHADDR bound to: 32'b11011111111111111111111111111111
Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_MEM0_TYPE bound to: 1 - type: integer
Parameter C_MEM1_TYPE bound to: 0 - type: integer
Parameter C_MEM2_TYPE bound to: 0 - type: integer
Parameter C_MEM3_TYPE bound to: 0 - type: integer
Parameter C_MEM0_WIDTH bound to: 32 - type: integer
Parameter C_MEM1_WIDTH bound to: 16 - type: integer
Parameter C_MEM2_WIDTH bound to: 16 - type: integer
Parameter C_MEM3_WIDTH bound to: 16 - type: integer
Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer
Parameter C_PAGE_SIZE bound to: 16 - type: integer
Parameter C_MEM_A_MSB bound to: 31 - type: integer
Parameter C_MEM_A_LSB bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_0 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_1 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_2 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_3 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer
INFO: [Synth 8-3491] module 'axi_emc' declared at '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3428' bound to instance 'U0' of component 'axi_emc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:373]
INFO: [Synth 8-638] synthesizing module 'axi_emc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3738]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_INSTANCE bound to: axi_emc_inst - type: string
Parameter C_AXI_CLK_PERIOD_PS bound to: 30769 - type: integer
Parameter C_LFLASH_PERIOD_PS bound to: 30769 - type: integer
Parameter C_LINEAR_FLASH_SYNC_BURST bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_PORT_DIFF bound to: 0 - type: integer
Parameter C_S_AXI_REG_ADDR_WIDTH bound to: 5 - type: integer
Parameter C_S_AXI_REG_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_EN_REG bound to: 0 - type: integer
Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer
Parameter C_S_AXI_MEM0_BASEADDR bound to: 1610612736 - type: integer
Parameter C_S_AXI_MEM0_HIGHADDR bound to: 2147483647 - type: integer
Parameter C_S_AXI_MEM1_BASEADDR bound to: -1342177280 - type: integer
Parameter C_S_AXI_MEM1_HIGHADDR bound to: -1073741825 - type: integer
Parameter C_S_AXI_MEM2_BASEADDR bound to: -1073741824 - type: integer
Parameter C_S_AXI_MEM2_HIGHADDR bound to: -805306369 - type: integer
Parameter C_S_AXI_MEM3_BASEADDR bound to: -805306368 - type: integer
Parameter C_S_AXI_MEM3_HIGHADDR bound to: -536870913 - type: integer
Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_MEM0_TYPE bound to: 1 - type: integer
Parameter C_MEM1_TYPE bound to: 0 - type: integer
Parameter C_MEM2_TYPE bound to: 0 - type: integer
Parameter C_MEM3_TYPE bound to: 0 - type: integer
Parameter C_MEM0_WIDTH bound to: 32 - type: integer
Parameter C_MEM1_WIDTH bound to: 16 - type: integer
Parameter C_MEM2_WIDTH bound to: 16 - type: integer
Parameter C_MEM3_WIDTH bound to: 16 - type: integer
Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer
Parameter C_PAGE_SIZE bound to: 16 - type: integer
Parameter C_MEM_A_MSB bound to: 31 - type: integer
Parameter C_MEM_A_LSB bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_0 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_1 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_2 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_MEM_3 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer
Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4175]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4214]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4215]
INFO: [Synth 8-638] synthesizing module 'axi_emc_native_interface' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1827]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer
Parameter C_S_AXI_MEM0_BASEADDR bound to: 1610612736 - type: integer
Parameter C_S_AXI_MEM0_HIGHADDR bound to: 2147483647 - type: integer
Parameter C_S_AXI_MEM1_BASEADDR bound to: -1342177280 - type: integer
Parameter C_S_AXI_MEM1_HIGHADDR bound to: -1073741825 - type: integer
Parameter C_S_AXI_MEM2_BASEADDR bound to: -1073741824 - type: integer
Parameter C_S_AXI_MEM2_HIGHADDR bound to: -805306369 - type: integer
Parameter C_S_AXI_MEM3_BASEADDR bound to: -805306368 - type: integer
Parameter C_S_AXI_MEM3_HIGHADDR bound to: -536870913 - type: integer
Parameter AXI_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111
Parameter AXI_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000001
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_emc_addr_gen' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:614]
Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_emc_addr_gen' (51#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:614]
INFO: [Synth 8-638] synthesizing module 'axi_emc_address_decode' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1250]
Parameter C_S_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_ADDR_DECODE_BITS bound to: 32 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000001
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_emc_address_decode' (52#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1250]
INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
Parameter C_DWIDTH bound to: 33 - type: integer
Parameter C_DEPTH bound to: 256 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
Parameter C_SIZE bound to: 9 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (53#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
Parameter C_DEPTH bound to: 256 - type: integer
Parameter C_DWIDTH bound to: 33 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (54#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (55#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
INFO: [Synth 8-638] synthesizing module 'axi_emc_v3_0_20_counter_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:241]
Parameter C_NUM_BITS bound to: 8 - type: integer
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_emc_v3_0_20_counter_f' (56#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:241]
WARNING: [Synth 8-6014] Unused sequential element last_rd_data_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:2434]
WARNING: [Synth 8-6014] Unused sequential element single_transfer_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:2452]
INFO: [Synth 8-256] done synthesizing module 'axi_emc_native_interface' (57#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1827]
INFO: [Synth 8-638] synthesizing module 'EMC' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:8233]
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
Parameter C_IPIF_AWIDTH bound to: 32 - type: integer
Parameter C_PAGE_SIZE bound to: 16 - type: integer
Parameter C_MEM0_BASEADDR bound to: 1610612736 - type: integer
Parameter C_MEM0_HIGHADDR bound to: 2147483647 - type: integer
Parameter C_MEM1_BASEADDR bound to: -1342177280 - type: integer
Parameter C_MEM1_HIGHADDR bound to: -1073741825 - type: integer
Parameter C_MEM2_BASEADDR bound to: -1073741824 - type: integer
Parameter C_MEM2_HIGHADDR bound to: -805306369 - type: integer
Parameter C_MEM3_BASEADDR bound to: -805306368 - type: integer
Parameter C_MEM3_HIGHADDR bound to: -536870913 - type: integer
Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_0 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_1 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_2 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_3 bound to: 0 - type: integer
Parameter C_MEM0_WIDTH bound to: 32 - type: integer
Parameter C_MEM1_WIDTH bound to: 16 - type: integer
Parameter C_MEM2_WIDTH bound to: 16 - type: integer
Parameter C_MEM3_WIDTH bound to: 16 - type: integer
Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer
Parameter C_MEM0_TYPE bound to: 1 - type: integer
Parameter C_MEM1_TYPE bound to: 0 - type: integer
Parameter C_MEM2_TYPE bound to: 0 - type: integer
Parameter C_MEM3_TYPE bound to: 0 - type: integer
Parameter C_PARITY_TYPE_0 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_1 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_2 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_3 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer
Parameter C_BUS_CLOCK_PERIOD_PS bound to: 30769 - type: integer
Parameter C_SYNCH_MEM_0 bound to: 0 - type: integer
Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer
Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer
Parameter C_SYNCH_MEM_1 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer
Parameter C_SYNCH_MEM_2 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer
Parameter C_SYNCH_MEM_3 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer
Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer
Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer
Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer
Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer
Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer
Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer
INFO: [Synth 8-638] synthesizing module 'emc_common_v3_0_5_ipic_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:580]
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
INFO: [Synth 8-638] synthesizing module 'ld_arith_reg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
Parameter C_ADD_SUB_NOT bound to: 0 - type: bool
Parameter C_REG_WIDTH bound to: 8 - type: integer
Parameter C_RESET_VALUE bound to: 8'b00000000
Parameter C_LD_WIDTH bound to: 8 - type: integer
Parameter C_LD_OFFSET bound to: 0 - type: integer
Parameter C_AD_WIDTH bound to: 1 - type: integer
Parameter C_AD_OFFSET bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-6157] synthesizing module 'MULT_AND' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867]
INFO: [Synth 8-6155] done synthesizing module 'MULT_AND' (58#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-6157] synthesizing module 'MUXCY' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878]
INFO: [Synth 8-6155] done synthesizing module 'MUXCY' (59#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-6157] synthesizing module 'XORCY' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303]
INFO: [Synth 8-6155] done synthesizing module 'XORCY' (60#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-6157] synthesizing module 'FDRE' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-6155] done synthesizing module 'FDRE' (61#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg' (62#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
WARNING: [Synth 8-6014] Unused sequential element bus2ip_mem_cs_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:668]
WARNING: [Synth 8-6014] Unused sequential element pr_state_wait_temp_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:669]
INFO: [Synth 8-256] done synthesizing module 'emc_common_v3_0_5_ipic_if' (63#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:580]
INFO: [Synth 8-638] synthesizing module 'mem_state_machine' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2190]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114]
WARNING: [Synth 8-6014] Unused sequential element mem_cen_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3179]
WARNING: [Synth 8-6014] Unused sequential element mem_oen_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3180]
WARNING: [Synth 8-6014] Unused sequential element mem_wen_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3181]
WARNING: [Synth 8-6014] Unused sequential element addr_cnt_ce_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3208]
WARNING: [Synth 8-6014] Unused sequential element addr_cnt_rst_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3209]
WARNING: [Synth 8-6014] Unused sequential element Bus2IP_RdReq_d2_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3258]
WARNING: [Synth 8-6014] Unused sequential element last_addr1_d1_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3304]
WARNING: [Synth 8-6014] Unused sequential element last_addr1_d2_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3305]
WARNING: [Synth 8-6014] Unused sequential element last_addr1_d3_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3306]
WARNING: [Synth 8-3848] Net addressData_strobe_cmb in module/entity mem_state_machine does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2238]
INFO: [Synth 8-256] done synthesizing module 'mem_state_machine' (64#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2190]
INFO: [Synth 8-638] synthesizing module 'addr_counter_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4461]
Parameter C_ADDR_CNTR_WIDTH bound to: 2 - type: integer
Parameter C_IPIF_AWIDTH bound to: 32 - type: integer
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
Parameter C_ADDR_OFFSET bound to: 2 - type: integer
Parameter PARITY_TYPE_MEMORY bound to: 0 - type: integer
Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573]
WARNING: [Synth 8-3848] Net Addr_align in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4436]
WARNING: [Synth 8-3848] Net par_error_addr in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4444]
INFO: [Synth 8-256] done synthesizing module 'addr_counter_mux' (65#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4461]
INFO: [Synth 8-638] synthesizing module 'counters' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1669]
INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
Parameter C_ADD_SUB_NOT bound to: 0 - type: bool
Parameter C_REG_WIDTH bound to: 5 - type: integer
Parameter C_RESET_VALUE bound to: 5'b11111
Parameter C_LD_WIDTH bound to: 5 - type: integer
Parameter C_LD_OFFSET bound to: 0 - type: integer
Parameter C_AD_WIDTH bound to: 1 - type: integer
Parameter C_AD_OFFSET bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328]
INFO: [Synth 8-6157] synthesizing module 'FDSE' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
INFO: [Synth 8-6155] done synthesizing module 'FDSE' (66#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328]
INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized0' (66#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
Parameter C_ADD_SUB_NOT bound to: 0 - type: bool
Parameter C_REG_WIDTH bound to: 5 - type: integer
Parameter C_RESET_VALUE bound to: 5'b00000
Parameter C_LD_WIDTH bound to: 5 - type: integer
Parameter C_LD_OFFSET bound to: 0 - type: integer
Parameter C_AD_WIDTH bound to: 1 - type: integer
Parameter C_AD_OFFSET bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318]
INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281]
INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291]
INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302]
INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized1' (66#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
Parameter C_ADD_SUB_NOT bound to: 0 - type: bool
Parameter C_REG_WIDTH bound to: 16 - type: integer
Parameter C_RESET_VALUE bound to: 16'b1111111111111111
Parameter C_LD_WIDTH bound to: 16 - type: integer
Parameter C_LD_OFFSET bound to: 0 - type: integer
Parameter C_AD_WIDTH bound to: 1 - type: integer
Parameter C_AD_OFFSET bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized2' (66#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161]
INFO: [Synth 8-256] done synthesizing module 'counters' (67#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1669]
INFO: [Synth 8-638] synthesizing module 'select_param' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3633]
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_PAGE_SIZE bound to: 16 - type: integer
Parameter C_GLOBAL_SYNC_MEM bound to: 0 - type: integer
Parameter C_SYNCH_MEM_0 bound to: 0 - type: integer
Parameter C_SYNCH_MEM_1 bound to: 1 - type: integer
Parameter C_SYNCH_MEM_2 bound to: 1 - type: integer
Parameter C_SYNCH_MEM_3 bound to: 1 - type: integer
Parameter C_MEM0_WIDTH bound to: 32 - type: integer
Parameter C_MEM1_WIDTH bound to: 16 - type: integer
Parameter C_MEM2_WIDTH bound to: 16 - type: integer
Parameter C_MEM3_WIDTH bound to: 16 - type: integer
Parameter C_PAGEMODE_FLASH bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_0 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_1 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_2 bound to: 0 - type: integer
Parameter C_PAGEMODE_FLASH_3 bound to: 0 - type: integer
Parameter PARITY_TYPE_MEMORY bound to: 0 - type: integer
Parameter C_PARITY_TYPE_0 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_1 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_2 bound to: 0 - type: integer
Parameter C_PARITY_TYPE_3 bound to: 0 - type: integer
Parameter C_IPIF_AWIDTH bound to: 32 - type: integer
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer
Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer
Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer
Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer
Parameter TRDCNT_0 bound to: 5'b00100
Parameter TRDCNT_1 bound to: 5'b00001
Parameter TRDCNT_2 bound to: 5'b00001
Parameter TRDCNT_3 bound to: 5'b00001
Parameter THZCNT_0 bound to: 5'b00001
Parameter THZCNT_1 bound to: 5'b00001
Parameter THZCNT_2 bound to: 5'b00001
Parameter THZCNT_3 bound to: 5'b00001
Parameter TWRCNT_0 bound to: 5'b00000
Parameter TWRCNT_1 bound to: 5'b00000
Parameter TWRCNT_2 bound to: 5'b00000
Parameter TWRCNT_3 bound to: 5'b00000
Parameter TWPHCNT_0 bound to: 5'b00001
Parameter TWPHCNT_1 bound to: 5'b00001
Parameter TWPHCNT_2 bound to: 5'b00001
Parameter TWPHCNT_3 bound to: 5'b00001
Parameter TPACC_0 bound to: 5'b00001
Parameter TPACC_1 bound to: 5'b00001
Parameter TPACC_2 bound to: 5'b00001
Parameter TPACC_3 bound to: 5'b00001
Parameter TLZCNT_0 bound to: 5'b00001
Parameter TLZCNT_1 bound to: 5'b00001
Parameter TLZCNT_2 bound to: 5'b00001
Parameter TLZCNT_3 bound to: 5'b00001
Parameter TP_WR_REC_CNT_0 bound to: 16'b0000000000000001
Parameter TP_WR_REC_CNT_1 bound to: 16'b0000000000000001
Parameter TP_WR_REC_CNT_2 bound to: 16'b0000000000000001
Parameter TP_WR_REC_CNT_3 bound to: 16'b0000000000000001
INFO: [Synth 8-256] done synthesizing module 'select_param' (68#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3633]
INFO: [Synth 8-638] synthesizing module 'mem_steer' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5345]
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer
Parameter C_MIN_MEM_WIDTH bound to: 8 - type: integer
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
Parameter C_IPIF_AWIDTH bound to: 32 - type: integer
Parameter C_PARITY_TYPE_MEMORY bound to: 0 - type: integer
Parameter C_ADDR_CNTR_WIDTH bound to: 2 - type: integer
Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer
Parameter C_GLOBAL_SYNC_MEM bound to: 0 - type: integer
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6024]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6024]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6087]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6087]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:7120]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:7120]
INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
WARNING: [Synth 8-6014] Unused sequential element mem_dqt_parity_t_d_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6961]
WARNING: [Synth 8-3848] Net write_data_parity_cmb in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5368]
WARNING: [Synth 8-3848] Net MemSteer_Mem_DQ_prty_T in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5305]
INFO: [Synth 8-256] done synthesizing module 'mem_steer' (69#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5345]
INFO: [Synth 8-638] synthesizing module 'io_registers' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1226]
Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer
Parameter C_IPIF_AWIDTH bound to: 32 - type: integer
Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer
Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex6 - type: string
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1245]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1248]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1249]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1249]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1250]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1251]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1252]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1253]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1254]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1255]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1256]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1257]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1265]
INFO: [Synth 8-256] done synthesizing module 'io_registers' (70#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1226]
INFO: [Synth 8-256] done synthesizing module 'EMC' (71#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:8233]
WARNING: [Synth 8-6014] Unused sequential element mem_wait_io_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4262]
WARNING: [Synth 8-6014] Unused sequential element or_reduced_rdce_d1_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:6329]
WARNING: [Synth 8-6014] Unused sequential element bus2ip_wrreq_reg_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:6330]
WARNING: [Synth 8-3848] Net mem_cre_int in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4214]
WARNING: [Synth 8-3848] Net cfgclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3668]
WARNING: [Synth 8-3848] Net cfgmclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3669]
WARNING: [Synth 8-3848] Net eos in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3670]
INFO: [Synth 8-256] done synthesizing module 'axi_emc' (72#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3738]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_emc_0_0' (73#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_gpio_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_GPIO_WIDTH bound to: 16 - type: integer
Parameter C_GPIO2_WIDTH bound to: 24 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000001111111100000000
Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111
INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_GPIO_WIDTH bound to: 16 - type: integer
Parameter C_GPIO2_WIDTH bound to: 24 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 65280 - type: integer
Parameter C_TRI_DEFAULT bound to: -1 - type: integer
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer
Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
Parameter C_BUS_AWIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b00
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' (74#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b01
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' (74#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b10
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' (74#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 2 - type: integer
Parameter C_BAR bound to: 2'b11
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' (74#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (75#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (76#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (77#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
Parameter C_DW bound to: 32 - type: integer
Parameter C_AW bound to: 9 - type: integer
Parameter C_GPIO_WIDTH bound to: 16 - type: integer
Parameter C_GPIO2_WIDTH bound to: 24 - type: integer
Parameter C_MAX_GPIO_WIDTH bound to: 24 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 65280 - type: integer
Parameter C_TRI_DEFAULT bound to: -1 - type: integer
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer
Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:835]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 0 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 16 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (78#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 0 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 24 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (78#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (79#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (80#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_gpio_0_0' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_hwicap_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_ICAP_EXTERNAL bound to: 1 - type: integer
Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer
Parameter C_ENABLE_ASYNC bound to: 0 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer
Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer
Parameter C_ICAP_WIDTH_S bound to: X32 - type: string
Parameter C_DEVICE_ID bound to: 32'b00000100001000100100000010010011
Parameter C_MODE bound to: 0 - type: integer
Parameter C_NOREAD bound to: 0 - type: integer
Parameter C_SIMULATION bound to: 2 - type: integer
Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_OPERATION bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_hwicap' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4084]
Parameter C_ENABLE_ASYNC bound to: 0 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer
Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer
Parameter C_ICAP_WIDTH_S bound to: X32 - type: string
Parameter C_DEVICE_ID bound to: 69353619 - type: integer
Parameter C_MODE bound to: 0 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_OPERATION bound to: 0 - type: integer
Parameter C_NOREAD bound to: 0 - type: integer
Parameter C_SIMULATION bound to: 2 - type: integer
Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer
Parameter C_ICAP_EXTERNAL bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 16 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111
Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111
Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000
Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 16 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
Parameter C_BUS_AWIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111
Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 9 - type: integer
Parameter C_BAR bound to: 9'b000000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 9 - type: integer
Parameter C_BAR bound to: 9'b100000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized0' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized0' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized0' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'hwicap_shared' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3444]
Parameter ICAP_DWIDTH bound to: 32 - type: integer
Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer
Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer
Parameter C_SAXI_DWIDTH bound to: 32 - type: integer
Parameter C_SIMULATION bound to: 2 - type: integer
Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer
Parameter C_ICAP_WIDTH bound to: X32 - type: string
Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_MODE bound to: 0 - type: integer
Parameter C_ICAP_EXTERNAL bound to: 0 - type: integer
Parameter C_OPERATION bound to: 0 - type: integer
Parameter C_NOREAD bound to: 0 - type: integer
Parameter C_ENABLE_ASYNC bound to: 0 - type: integer
Parameter C_DEVICE_ID bound to: 69353619 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'axi_hwicap_v3_0_24_ipic_if' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:216]
Parameter C_ENABLE_ASYNC bound to: 0 - type: integer
Parameter C_MODE bound to: 0 - type: integer
Parameter C_NOREAD bound to: 0 - type: integer
Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer
Parameter C_SAXI_DWIDTH bound to: 32 - type: integer
Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer
Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter ICAP_DWIDTH bound to: 32 - type: integer
Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 0 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 12 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized1' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 0 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized2' (81#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'async_fifo_fg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 64 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer
Parameter C_HAS_RD_ACK bound to: 1 - type: integer
Parameter C_HAS_RD_COUNT bound to: 1 - type: integer
Parameter C_HAS_RD_ERR bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 1 - type: integer
Parameter C_HAS_WR_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_ERR bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer
Parameter C_RD_ACK_LOW bound to: 0 - type: integer
Parameter C_RD_COUNT_WIDTH bound to: 7 - type: integer
Parameter C_RD_ERR_LOW bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer
Parameter C_USE_BLOCKMEM bound to: 1 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_COUNT_WIDTH bound to: 7 - type: integer
Parameter C_WR_ERR_LOW bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 4 - type: integer
Parameter C_XPM_FIFO bound to: 1 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: block - type: string
Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter READ_MODE bound to: std - type: string
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter CDC_SYNC_STAGES bound to: 4 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029]
Parameter FIFO_MEMORY_TYPE bound to: block - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: std - type: string
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_SYNC_STAGES bound to: 4 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
Parameter P_ECC_MODE bound to: 0 - type: integer
Parameter P_READ_MODE bound to: 0 - type: integer
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: 0 - type: integer
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter invalid bound to: 0 - type: integer
Parameter stage1_valid bound to: 2 - type: integer
Parameter stage2_valid bound to: 1 - type: integer
Parameter both_stages_valid bound to: 3 - type: integer
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
Parameter RD_MODE bound to: 0 - type: integer
Parameter ENABLE_ECC bound to: 0 - type: integer
Parameter FIFO_READ_DEPTH bound to: 64 - type: integer
Parameter FIFO_SIZE bound to: 2048 - type: integer
Parameter WR_WIDTH_LOG bound to: 5 - type: integer
Parameter WR_DEPTH_LOG bound to: 6 - type: integer
Parameter WR_PNTR_WIDTH bound to: 6 - type: integer
Parameter RD_PNTR_WIDTH bound to: 6 - type: integer
Parameter FULL_RST_VAL bound to: 1'b1
Parameter WR_RD_RATIO bound to: 0 - type: integer
Parameter PF_THRESH_ADJ bound to: 10 - type: integer
Parameter PE_THRESH_ADJ bound to: 10 - type: integer
Parameter PF_THRESH_MIN bound to: 7 - type: integer
Parameter PF_THRESH_MAX bound to: 61 - type: integer
Parameter PE_THRESH_MIN bound to: 3 - type: integer
Parameter PE_THRESH_MAX bound to: 61 - type: integer
Parameter WR_DC_WIDTH_EXT bound to: 7 - type: integer
Parameter RD_DC_WIDTH_EXT bound to: 7 - type: integer
Parameter RD_LATENCY bound to: 1 - type: integer
Parameter WIDTH_RATIO bound to: 1 - type: integer
Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111
Parameter EN_OF bound to: 1'b1
Parameter EN_PF bound to: 1'b1
Parameter EN_WDC bound to: 1'b1
Parameter EN_AF bound to: 1'b1
Parameter EN_WACK bound to: 1'b1
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
Parameter EN_UF bound to: 1'b1
Parameter EN_PE bound to: 1'b1
Parameter EN_RDC bound to: 1'b1
Parameter EN_AE bound to: 1'b1
Parameter EN_DVLD bound to: 1'b1
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 6 - type: integer
Parameter RESET_VALUE bound to: 3 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (82#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 6 - type: integer
Parameter RESET_VALUE bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (82#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
Parameter MEMORY_TYPE bound to: 1 - type: integer
Parameter MEMORY_SIZE bound to: 2048 - type: integer
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
Parameter CLOCKING_MODE bound to: 1 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter MEMORY_INIT_FILE bound to: none - type: string
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
Parameter USE_MEM_INIT bound to: 0 - type: integer
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
Parameter ADDR_WIDTH_A bound to: 6 - type: integer
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
Parameter READ_LATENCY_A bound to: 2 - type: integer
Parameter WRITE_MODE_A bound to: 2 - type: integer
Parameter RST_MODE_A bound to: SYNC - type: string
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
Parameter ADDR_WIDTH_B bound to: 6 - type: integer
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
Parameter READ_LATENCY_B bound to: 1 - type: integer
Parameter WRITE_MODE_B bound to: 2 - type: integer
Parameter RST_MODE_B bound to: SYNC - type: string
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
Parameter P_MAX_DEPTH_DATA bound to: 64 - type: integer
Parameter P_ECC_MODE bound to: no_ecc - type: string
Parameter P_MEMORY_OPT bound to: yes - type: string
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
Parameter P_WIDTH_ADDR_WRITE_A bound to: 6 - type: integer
Parameter P_WIDTH_ADDR_WRITE_B bound to: 6 - type: integer
Parameter P_WIDTH_ADDR_READ_A bound to: 6 - type: integer
Parameter P_WIDTH_ADDR_READ_B bound to: 6 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
Parameter P_SDP_WRITE_MODE bound to: no - type: string
Parameter rsta_loop_iter bound to: 32 - type: integer
Parameter rstb_loop_iter bound to: 32 - type: integer
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (83#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
Parameter DEST_SYNC_FF bound to: 4 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 6 - type: integer
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (84#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
Parameter REG_WIDTH bound to: 6 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (85#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
Parameter DEST_SYNC_FF bound to: 4 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 7 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (85#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
Parameter REG_WIDTH bound to: 7 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (85#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506]
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1574]
INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1580]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059]
Parameter DEST_SYNC_FF bound to: 4 - type: integer
Parameter INIT bound to: 32'sb00000000000000000000000000000000
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter DEF_VAL bound to: 1'b0
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1111]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (86#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (87#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790]
Parameter RST_VALUE bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (88#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 7 - type: integer
Parameter RESET_VALUE bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (88#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 6 - type: integer
Parameter RESET_VALUE bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (88#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (89#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (90#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg' (91#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized3' (91#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 128 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer
Parameter C_HAS_RD_ACK bound to: 1 - type: integer
Parameter C_HAS_RD_COUNT bound to: 1 - type: integer
Parameter C_HAS_RD_ERR bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 1 - type: integer
Parameter C_HAS_WR_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_ERR bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer
Parameter C_RD_ACK_LOW bound to: 0 - type: integer
Parameter C_RD_COUNT_WIDTH bound to: 8 - type: integer
Parameter C_RD_ERR_LOW bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer
Parameter C_USE_BLOCKMEM bound to: 1 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_COUNT_WIDTH bound to: 8 - type: integer
Parameter C_WR_ERR_LOW bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 4 - type: integer
Parameter C_XPM_FIFO bound to: 1 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: block - type: string
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter READ_MODE bound to: std - type: string
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter CDC_SYNC_STAGES bound to: 4 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029]
Parameter FIFO_MEMORY_TYPE bound to: block - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: std - type: string
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_SYNC_STAGES bound to: 4 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111
Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
Parameter P_ECC_MODE bound to: 0 - type: integer
Parameter P_READ_MODE bound to: 0 - type: integer
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: 0 - type: integer
Parameter FIFO_READ_LATENCY bound to: 1 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter invalid bound to: 0 - type: integer
Parameter stage1_valid bound to: 2 - type: integer
Parameter stage2_valid bound to: 1 - type: integer
Parameter both_stages_valid bound to: 3 - type: integer
Parameter FIFO_MEM_TYPE bound to: 2 - type: integer
Parameter RD_MODE bound to: 0 - type: integer
Parameter ENABLE_ECC bound to: 0 - type: integer
Parameter FIFO_READ_DEPTH bound to: 128 - type: integer
Parameter FIFO_SIZE bound to: 4096 - type: integer
Parameter WR_WIDTH_LOG bound to: 5 - type: integer
Parameter WR_DEPTH_LOG bound to: 7 - type: integer
Parameter WR_PNTR_WIDTH bound to: 7 - type: integer
Parameter RD_PNTR_WIDTH bound to: 7 - type: integer
Parameter FULL_RST_VAL bound to: 1'b1
Parameter WR_RD_RATIO bound to: 0 - type: integer
Parameter PF_THRESH_ADJ bound to: 10 - type: integer
Parameter PE_THRESH_ADJ bound to: 10 - type: integer
Parameter PF_THRESH_MIN bound to: 7 - type: integer
Parameter PF_THRESH_MAX bound to: 125 - type: integer
Parameter PE_THRESH_MIN bound to: 3 - type: integer
Parameter PE_THRESH_MAX bound to: 125 - type: integer
Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer
Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer
Parameter RD_LATENCY bound to: 1 - type: integer
Parameter WIDTH_RATIO bound to: 1 - type: integer
Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111
Parameter EN_OF bound to: 1'b1
Parameter EN_PF bound to: 1'b1
Parameter EN_WDC bound to: 1'b1
Parameter EN_AF bound to: 1'b1
Parameter EN_WACK bound to: 1'b1
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
Parameter EN_UF bound to: 1'b1
Parameter EN_PE bound to: 1'b1
Parameter EN_RDC bound to: 1'b1
Parameter EN_AE bound to: 1'b1
Parameter EN_DVLD bound to: 1'b1
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 7 - type: integer
Parameter RESET_VALUE bound to: 3 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 7 - type: integer
Parameter RESET_VALUE bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
Parameter MEMORY_TYPE bound to: 1 - type: integer
Parameter MEMORY_SIZE bound to: 4096 - type: integer
Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer
Parameter CLOCKING_MODE bound to: 1 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter MEMORY_INIT_FILE bound to: none - type: string
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
Parameter USE_MEM_INIT bound to: 0 - type: integer
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
Parameter ADDR_WIDTH_A bound to: 7 - type: integer
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
Parameter READ_LATENCY_A bound to: 2 - type: integer
Parameter WRITE_MODE_A bound to: 2 - type: integer
Parameter RST_MODE_A bound to: SYNC - type: string
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
Parameter ADDR_WIDTH_B bound to: 7 - type: integer
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
Parameter READ_LATENCY_B bound to: 1 - type: integer
Parameter WRITE_MODE_B bound to: 2 - type: integer
Parameter RST_MODE_B bound to: SYNC - type: string
Parameter P_MEMORY_PRIMITIVE bound to: block - type: string
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer
Parameter P_ECC_MODE bound to: no_ecc - type: string
Parameter P_MEMORY_OPT bound to: yes - type: string
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer
Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer
Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer
Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
Parameter P_SDP_WRITE_MODE bound to: no - type: string
Parameter rsta_loop_iter bound to: 32 - type: integer
Parameter rstb_loop_iter bound to: 32 - type: integer
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
Parameter DEST_SYNC_FF bound to: 4 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
Parameter REG_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter RESET_VALUE bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized6' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
Parameter COUNTER_WIDTH bound to: 7 - type: integer
Parameter RESET_VALUE bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized6' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized0' (91#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
Parameter C_MTBF_STAGES bound to: 3 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized4' (91#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 12 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized5' (91#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter PROG_USR bound to: FALSE - type: string
Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
WARNING: [Synth 8-3848] Net Status_read in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:186]
WARNING: [Synth 8-3848] Net CFGCLK in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:197]
WARNING: [Synth 8-3848] Net CFGMCLK in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:198]
WARNING: [Synth 8-3848] Net PREQ in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:199]
INFO: [Synth 8-256] done synthesizing module 'axi_hwicap_v3_0_24_ipic_if' (92#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:216]
INFO: [Synth 8-638] synthesizing module 'icap_statemachine_shared' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2160]
Parameter ICAP_DWIDTH bound to: 32 - type: integer
Parameter C_MODE bound to: 0 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2119]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2124]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2132]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2133]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2139]
INFO: [Synth 8-256] done synthesizing module 'icap_statemachine_shared' (93#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2160]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'hwicap_shared' (94#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3444]
INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
Parameter C_NUM_CE bound to: 16 - type: integer
Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer
Parameter C_IP_INTR_MODE_ARRAY bound to: 128'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool
Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (95#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'axi_hwicap' (96#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4084]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_hwicap_0_0' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_GPO_WIDTH bound to: 1 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_LEVEL bound to: 1 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: 8'b00000000
INFO: [Synth 8-638] synthesizing module 'axi_iic' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6870]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_GPO_WIDTH bound to: 1 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_LEVEL bound to: 1 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: 8'b00000000
INFO: [Synth 8-638] synthesizing module 'iic' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6187]
Parameter C_NUM_IIC_REGS bound to: 18 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_GPO_WIDTH bound to: 1 - type: integer
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_LEVEL bound to: 1 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool
Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DEFAULT_VALUE bound to: 8'b00000000
INFO: [Synth 8-638] synthesizing module 'axi_ipif_ssp1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5661]
Parameter C_NUM_IIC_REGS bound to: 18 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010
Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_USE_WSTRB bound to: 0 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
Parameter C_BUS_AWIDTH bound to: 9 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 7 - type: integer
Parameter C_AW bound to: 9 - type: integer
Parameter C_BAR bound to: 9'b001000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 1 - type: integer
Parameter C_AW bound to: 9 - type: integer
Parameter C_BAR bound to: 9'b100000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized52' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized52' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized53' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized53' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized54' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b00111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized54' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized55' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized55' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized56' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized56' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized57' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized57' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized58' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized58' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized59' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized59' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized60' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized60' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized61' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized61' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized62' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b01111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized62' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized63' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b10000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized63' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized64' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 5 - type: integer
Parameter C_BAR bound to: 5'b10001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized64' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized1' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized1' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized1' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
Parameter C_NUM_CE bound to: 16 - type: integer
Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer
Parameter C_IP_INTR_MODE_ARRAY bound to: 256'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool
Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized0' (97#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
INFO: [Synth 8-638] synthesizing module 'axi_iic_v2_0_23_soft_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:141]
Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer
Parameter C_RESET_WIDTH bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'axi_iic_v2_0_23_soft_reset' (98#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:141]
INFO: [Synth 8-256] done synthesizing module 'axi_ipif_ssp1' (99#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5661]
INFO: [Synth 8-638] synthesizing module 'reg_interface' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1677]
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool
Parameter C_TX_FIFO_BITS bound to: 4 - type: integer
Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool
Parameter C_RC_FIFO_BITS bound to: 4 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_GPO_WIDTH bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_SIZE bound to: 10 - type: integer
Parameter C_NUM_IIC_REGS bound to: 18 - type: integer
Parameter C_DEFAULT_VALUE bound to: 8'b00000000
INFO: [Synth 8-256] done synthesizing module 'reg_interface' (100#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1677]
INFO: [Synth 8-638] synthesizing module 'filter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:4985]
Parameter SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter SDA_INERTIAL_DELAY bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'debounce' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1307]
Parameter C_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_DEFAULT bound to: 1'b1
INFO: [Synth 8-256] done synthesizing module 'debounce' (101#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1307]
INFO: [Synth 8-256] done synthesizing module 'filter' (102#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:4985]
INFO: [Synth 8-638] synthesizing module 'iic_control' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:2908]
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_SIZE bound to: 10 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_SDA_LEVEL bound to: 1 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
Parameter C_SIZE bound to: 10 - type: integer
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (103#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
INFO: [Synth 8-638] synthesizing module 'shift8' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:897]
INFO: [Synth 8-256] done synthesizing module 'shift8' (104#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:897]
INFO: [Synth 8-638] synthesizing module 'upcnt_n__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
Parameter C_SIZE bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'upcnt_n__parameterized0' (104#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740]
INFO: [Synth 8-256] done synthesizing module 'iic_control' (105#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:2908]
INFO: [Synth 8-638] synthesizing module 'SRL_FIFO' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_DEPTH bound to: 4 - type: integer
Parameter C_XON bound to: 0 - type: bool
INFO: [Synth 8-6157] synthesizing module 'FDR' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13695]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-6155] done synthesizing module 'FDR' (106#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13695]
INFO: [Synth 8-6157] synthesizing module 'MUXCY_L' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42903]
INFO: [Synth 8-6155] done synthesizing module 'MUXCY_L' (107#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42903]
INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77965]
Parameter INIT bound to: 16'b0000000000000000
Parameter IS_CLK_INVERTED bound to: 1'b0
INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (108#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77965]
INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO' (109#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
Parameter C_DATA_BITS bound to: 8 - type: integer
Parameter C_DEPTH bound to: 4 - type: integer
Parameter C_XON bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized0' (109#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
INFO: [Synth 8-638] synthesizing module 'dynamic_master' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5204]
INFO: [Synth 8-256] done synthesizing module 'dynamic_master' (110#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5204]
INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
Parameter C_DATA_BITS bound to: 2 - type: integer
Parameter C_DEPTH bound to: 4 - type: integer
Parameter C_XON bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized1' (110#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449]
INFO: [Synth 8-256] done synthesizing module 'iic' (111#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6187]
INFO: [Synth 8-256] done synthesizing module 'axi_iic' (112#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6870]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_0_0' (113#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_1_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_IIC_FREQ bound to: 32000 - type: integer
Parameter C_TEN_BIT_ADR bound to: 0 - type: integer
Parameter C_GPO_WIDTH bound to: 1 - type: integer
Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer
Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer
Parameter C_SDA_LEVEL bound to: 1 - type: integer
Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: 8'b00000000
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_1_0' (114#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_interconnect_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2823]
INFO: [Synth 8-638] synthesizing module 'm00_couplers_imp_1AOY6T4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:93]
INFO: [Synth 8-256] done synthesizing module 'm00_couplers_imp_1AOY6T4' (115#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:93]
INFO: [Synth 8-638] synthesizing module 'm01_couplers_imp_FF3AZQ' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:270]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:58]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_M_AXI_PROTOCOL bound to: 2 - type: integer
Parameter C_S_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_IGNORE_ID bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_TRANSLATION_MODE bound to: 2 - type: integer
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_AXILITE_SIZE bound to: 3'b010
Parameter P_INCR bound to: 2'b01
Parameter P_DECERR bound to: 2'b11
Parameter P_SLVERR bound to: 2'b10
Parameter P_PROTECTION bound to: 1 - type: integer
Parameter P_CONVERSION bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226]
Parameter C_S_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_aw_channel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971]
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_cmd_translator' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464]
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter P_AXBURST_FIXED bound to: 2'b00
Parameter P_AXBURST_INCR bound to: 2'b01
Parameter P_AXBURST_WRAP bound to: 2'b10
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_incr_cmd' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092]
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_incr_cmd' (116#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wrap_cmd' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902]
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wrap_cmd' (117#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_cmd_translator' (118#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224]
Parameter SM_IDLE bound to: 2'b00
Parameter SM_CMD_EN bound to: 2'b01
Parameter SM_CMD_ACCEPTED bound to: 2'b10
Parameter SM_DONE_WAIT bound to: 2'b11
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3277]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm' (119#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_aw_channel' (120#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_b_channel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606]
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter LP_RESP_OKAY bound to: 2'b00
Parameter LP_RESP_EXOKAY bound to: 2'b01
Parameter LP_RESP_SLVERROR bound to: 2'b10
Parameter LP_RESP_DECERR bound to: 2'b11
Parameter P_WIDTH bound to: 10 - type: integer
Parameter P_DEPTH bound to: 4 - type: integer
Parameter P_AWIDTH bound to: 2 - type: integer
Parameter P_RWIDTH bound to: 2 - type: integer
Parameter P_RDEPTH bound to: 4 - type: integer
Parameter P_RAWIDTH bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
Parameter C_WIDTH bound to: 10 - type: integer
Parameter C_AWIDTH bound to: 2 - type: integer
Parameter C_DEPTH bound to: 4 - type: integer
Parameter C_EMPTY bound to: 2'b11
Parameter C_EMPTY_PRE bound to: 2'b00
Parameter C_FULL bound to: 2'b10
Parameter C_FULL_PRE bound to: 2'b01
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo' (121#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
Parameter C_WIDTH bound to: 2 - type: integer
Parameter C_AWIDTH bound to: 2 - type: integer
Parameter C_DEPTH bound to: 4 - type: integer
Parameter C_EMPTY bound to: 2'b11
Parameter C_EMPTY_PRE bound to: 2'b00
Parameter C_FULL bound to: 2'b10
Parameter C_FULL_PRE bound to: 2'b01
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0' (121#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_b_channel' (122#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_ar_channel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082]
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334]
Parameter SM_IDLE bound to: 2'b00
Parameter SM_CMD_EN bound to: 2'b01
Parameter SM_CMD_ACCEPTED bound to: 2'b10
Parameter SM_DONE bound to: 2'b11
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3395]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' (123#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_ar_channel' (124#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_r_channel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811]
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter P_WIDTH bound to: 3 - type: integer
Parameter P_DEPTH bound to: 32 - type: integer
Parameter P_AWIDTH bound to: 5 - type: integer
Parameter P_D_WIDTH bound to: 34 - type: integer
Parameter P_D_DEPTH bound to: 32 - type: integer
Parameter P_D_AWIDTH bound to: 5 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
Parameter C_WIDTH bound to: 34 - type: integer
Parameter C_AWIDTH bound to: 5 - type: integer
Parameter C_DEPTH bound to: 32 - type: integer
Parameter C_EMPTY bound to: 5'b11111
Parameter C_EMPTY_PRE bound to: 5'b00000
Parameter C_FULL bound to: 5'b11110
Parameter C_FULL_PRE bound to: 5'b11010
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1' (124#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
Parameter C_WIDTH bound to: 3 - type: integer
Parameter C_AWIDTH bound to: 5 - type: integer
Parameter C_DEPTH bound to: 32 - type: integer
Parameter C_EMPTY bound to: 5'b11111
Parameter C_EMPTY_PRE bound to: 5'b00000
Parameter C_FULL bound to: 5'b11110
Parameter C_FULL_PRE bound to: 5'b11010
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2' (124#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_r_channel' (125#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_REG_CONFIG_AW bound to: 1 - type: integer
Parameter C_REG_CONFIG_W bound to: 0 - type: integer
Parameter C_REG_CONFIG_B bound to: 1 - type: integer
Parameter C_REG_CONFIG_AR bound to: 1 - type: integer
Parameter C_REG_CONFIG_R bound to: 1 - type: integer
Parameter C_RESERVE_MODE bound to: 0 - type: integer
Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter P_FORWARD bound to: 0 - type: integer
Parameter P_RESPONSE bound to: 1 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (126#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (127#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 63 - type: integer
Parameter C_REG_CONFIG bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice' (128#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 37 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized0' (128#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 4 - type: integer
Parameter C_REG_CONFIG bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized1' (128#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 37 - type: integer
Parameter C_REG_CONFIG bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized2' (128#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704]
WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_AXI_PROTOCOL bound to: 2 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_REG_CONFIG_AW bound to: 0 - type: integer
Parameter C_REG_CONFIG_W bound to: 0 - type: integer
Parameter C_REG_CONFIG_B bound to: 0 - type: integer
Parameter C_REG_CONFIG_AR bound to: 0 - type: integer
Parameter C_REG_CONFIG_R bound to: 0 - type: integer
Parameter C_RESERVE_MODE bound to: 0 - type: integer
Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer
Parameter P_FORWARD bound to: 0 - type: integer
Parameter P_RESPONSE bound to: 1 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WID_INDEX bound to: 36 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RID_INDEX bound to: 34 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
Parameter C_AXI_PROTOCOL bound to: 2 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WID_INDEX bound to: 36 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RID_INDEX bound to: 34 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
Parameter C_AXI_PROTOCOL bound to: 2 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WID_INDEX bound to: 36 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RID_INDEX bound to: 34 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 35 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized3' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 36 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized4' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 2 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized5' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex6 - type: string
Parameter C_DATA_WIDTH bound to: 34 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized6' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized0' (129#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704]
WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s' (130#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter' (131#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_0' (132#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:58]
INFO: [Synth 8-256] done synthesizing module 'm01_couplers_imp_FF3AZQ' (133#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:270]
INFO: [Synth 8-638] synthesizing module 'm02_couplers_imp_L8N2BP' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:587]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:58]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_1' (134#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:58]
INFO: [Synth 8-256] done synthesizing module 'm02_couplers_imp_L8N2BP' (135#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:587]
INFO: [Synth 8-638] synthesizing module 'm03_couplers_imp_1MMZOD7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:904]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:58]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_2' (136#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:58]
INFO: [Synth 8-256] done synthesizing module 'm03_couplers_imp_1MMZOD7' (137#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:904]
INFO: [Synth 8-638] synthesizing module 'm04_couplers_imp_1FSUCEB' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1221]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:58]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_3' (138#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:58]
INFO: [Synth 8-256] done synthesizing module 'm04_couplers_imp_1FSUCEB' (139#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1221]
INFO: [Synth 8-638] synthesizing module 'm05_couplers_imp_ADRT99' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1538]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:58]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_4' (140#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:58]
INFO: [Synth 8-256] done synthesizing module 'm05_couplers_imp_ADRT99' (141#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1538]
INFO: [Synth 8-638] synthesizing module 'm06_couplers_imp_Q7JFB2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1855]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:58]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_5' (142#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:58]
INFO: [Synth 8-256] done synthesizing module 'm06_couplers_imp_Q7JFB2' (143#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1855]
INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_IY3DNS' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2168]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:58]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_M_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_S_AXI_PROTOCOL bound to: 2 - type: integer
Parameter C_IGNORE_ID bound to: 1 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_TRANSLATION_MODE bound to: 2 - type: integer
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_AXILITE_SIZE bound to: 3'b010
Parameter P_INCR bound to: 2'b01
Parameter P_DECERR bound to: 2'b11
Parameter P_SLVERR bound to: 2'b10
Parameter P_PROTECTION bound to: 1 - type: integer
Parameter P_CONVERSION bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter__parameterized0' (143#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808]
INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_6' (144#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:58]
INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_IY3DNS' (145#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2168]
INFO: [Synth 8-638] synthesizing module 's01_couplers_imp_1OXAPVA' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2487]
INFO: [Synth 8-256] done synthesizing module 's01_couplers_imp_1OXAPVA' (146#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2487]
INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_xbar_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xbar_0/synth/axi4_subsys_xbar_0.v:59]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_axi_crossbar' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4884]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer
Parameter C_NUM_MASTER_SLOTS bound to: 7 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_M_AXI_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_M_AXI_ADDR_WIDTH bound to: 224'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000011101
Parameter C_S_AXI_BASE_ID bound to: 64'b0000000000000000000000000000001000000000000000000000000000000000
Parameter C_S_AXI_THREAD_ID_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000000
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_M_AXI_WRITE_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_M_AXI_READ_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_R_REGISTER bound to: 0 - type: integer
Parameter C_S_AXI_SINGLE_THREAD bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
Parameter C_S_AXI_WRITE_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010
Parameter C_S_AXI_READ_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010
Parameter C_M_AXI_WRITE_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter C_M_AXI_READ_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter C_S_AXI_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_CONNECTIVITY_MODE bound to: 1 - type: integer
Parameter P_ONES bound to: 65'b11111111111111111111111111111111111111111111111111111111111111111
Parameter P_S_AXI_BASE_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000
Parameter P_S_AXI_HIGH_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_AXILITE_SIZE bound to: 3'b010
Parameter P_INCR bound to: 2'b01
Parameter P_M_AXI_SUPPORTS_WRITE bound to: 7'b1111111
Parameter P_M_AXI_SUPPORTS_READ bound to: 7'b1111111
Parameter P_S_AXI_SUPPORTS_WRITE bound to: 2'b11
Parameter P_S_AXI_SUPPORTS_READ bound to: 2'b11
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_RANGE_CHECK bound to: 1 - type: integer
Parameter P_ADDR_DECODE bound to: 1 - type: integer
Parameter P_M_AXI_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter P_LEN bound to: 8 - type: integer
Parameter P_LOCK bound to: 1 - type: integer
Parameter P_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_crossbar' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:2239]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer
Parameter C_NUM_MASTER_SLOTS bound to: 7 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_M_AXI_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_M_AXI_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_S_AXI_BASE_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000
Parameter C_S_AXI_HIGH_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000
Parameter C_S_AXI_THREAD_ID_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000000
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_S_AXI_SUPPORTS_WRITE bound to: 2'b11
Parameter C_S_AXI_SUPPORTS_READ bound to: 2'b11
Parameter C_M_AXI_SUPPORTS_WRITE bound to: 7'b1111111
Parameter C_M_AXI_SUPPORTS_READ bound to: 7'b1111111
Parameter C_M_AXI_WRITE_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_M_AXI_READ_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_S_AXI_SINGLE_THREAD bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
Parameter C_S_AXI_WRITE_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010
Parameter C_S_AXI_READ_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010
Parameter C_M_AXI_WRITE_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter C_M_AXI_READ_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter C_S_AXI_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_M_AXI_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_RANGE_CHECK bound to: 1 - type: integer
Parameter C_ADDR_DECODE bound to: 1 - type: integer
Parameter C_W_ISSUE_WIDTH bound to: 256'b0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001
Parameter C_R_ISSUE_WIDTH bound to: 256'b0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001
Parameter C_W_ACCEPT_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000001
Parameter C_R_ACCEPT_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000001
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_WRITE bound to: 0 - type: integer
Parameter P_READ bound to: 1 - type: integer
Parameter P_NUM_MASTER_SLOTS_LOG bound to: 3 - type: integer
Parameter P_NUM_SLAVE_SLOTS_LOG bound to: 1 - type: integer
Parameter P_AXI_WID_WIDTH bound to: 1 - type: integer
Parameter P_ST_AWMESG_WIDTH bound to: 11 - type: integer
Parameter P_AA_AWMESG_WIDTH bound to: 65 - type: integer
Parameter P_ST_ARMESG_WIDTH bound to: 11 - type: integer
Parameter P_AA_ARMESG_WIDTH bound to: 65 - type: integer
Parameter P_ST_BMESG_WIDTH bound to: 3 - type: integer
Parameter P_ST_RMESG_WIDTH bound to: 35 - type: integer
Parameter P_WR_WMESG_WIDTH bound to: 38 - type: integer
Parameter P_BYPASS bound to: 0 - type: integer
Parameter P_FWD_REV bound to: 1 - type: integer
Parameter P_SIMPLE bound to: 7 - type: integer
Parameter P_M_AXI_SUPPORTS_READ bound to: 8'b11111111
Parameter P_M_AXI_SUPPORTS_WRITE bound to: 8'b11111111
Parameter P_M_AXI_WRITE_CONNECTIVITY bound to: 256'b1111111111111111111111111111111100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter P_M_AXI_READ_CONNECTIVITY bound to: 256'b1111111111111111111111111111111100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter P_S_AXI_WRITE_CONNECTIVITY bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111
Parameter P_S_AXI_READ_CONNECTIVITY bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111
Parameter P_M_AXI_READ_ISSUING bound to: 256'b0000000000000000000000000000000100000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter P_M_AXI_WRITE_ISSUING bound to: 256'b0000000000000000000000000000000100000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010
Parameter P_DECERR bound to: 2'b11
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SI bound to: 0 - type: integer
Parameter C_DIR bound to: 1 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_NUM_M bound to: 7 - type: integer
Parameter C_NUM_M_LOG bound to: 3 - type: integer
Parameter C_ACCEPTANCE bound to: 2 - type: integer
Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_THREAD_ID_WIDTH bound to: 0 - type: integer
Parameter C_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AMESG_WIDTH bound to: 11 - type: integer
Parameter C_RMESG_WIDTH bound to: 35 - type: integer
Parameter C_BASE_ID bound to: 2'b00
Parameter C_HIGH_ID bound to: 2'b00
Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_SINGLE_THREAD bound to: 0 - type: integer
Parameter C_TARGET_QUAL bound to: 7'b1111111
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_RANGE_CHECK bound to: 1 - type: integer
Parameter C_ADDR_DECODE bound to: 1 - type: integer
Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_WRITE bound to: 0 - type: integer
Parameter P_READ bound to: 1 - type: integer
Parameter P_RMUX_MESG_WIDTH bound to: 38 - type: integer
Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer
Parameter P_NONSECURE_BIT bound to: 1 - type: integer
Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer
Parameter P_M_AXILITE bound to: 7'b0000000
Parameter P_FIXED bound to: 2'b00
Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer
Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer
Parameter P_NUM_ID_VAL bound to: 1 - type: integer
Parameter P_NUM_THREADS bound to: 1 - type: integer
Parameter P_M_SECURE_MASK bound to: 7'b0000000
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_addr_decoder' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_TARGETS bound to: 7 - type: integer
Parameter C_NUM_TARGETS_LOG bound to: 3 - type: integer
Parameter C_NUM_RANGES bound to: 1 - type: integer
Parameter C_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_TARGET_ENC bound to: 1 - type: integer
Parameter C_TARGET_HOT bound to: 1 - type: integer
Parameter C_REGION_ENC bound to: 1 - type: integer
Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_TARGET_QUAL bound to: 8'b01111111
Parameter C_RESOLUTION bound to: 2 - type: integer
Parameter C_COMPARATOR_THRESHOLD bound to: 6 - type: integer
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b011000000000000000000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_carry_and' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62]
Parameter C_FAMILY bound to: rtl - type: string
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_carry_and' (147#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62]
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010000000000000000000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010000001000000000000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010000001000000100000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010001001010000000000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010000000010000000000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_VALUE bound to: 30'b010001001010000100000000000000
Parameter C_DATA_WIDTH bound to: 30 - type: integer
Parameter C_BITS_PER_LUT bound to: 6 - type: integer
Parameter C_NUM_LUT bound to: 5 - type: integer
Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' (148#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_addr_decoder' (149#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 8 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter C_USE_FULL bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_ndeep_srl' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:1135]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_A_WIDTH bound to: 2 - type: integer
Parameter P_SRLASIZE bound to: 5 - type: integer
Parameter P_SRLDEPTH bound to: 32 - type: integer
Parameter P_NUMSRLS bound to: 1 - type: integer
Parameter P_SHIFT_DEPTH bound to: 4 - type: integer
INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78115]
Parameter INIT bound to: 32'b00000000000000000000000000000000
Parameter IS_CLK_INVERTED bound to: 1'b0
INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (150#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78115]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_ndeep_srl' (151#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:1135]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo' (152#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_RATIO bound to: 8 - type: integer
Parameter C_SEL_WIDTH bound to: 3 - type: integer
Parameter C_DATA_WIDTH bound to: 38 - type: integer
INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42989]
INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (153#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42989]
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' (154#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor' (155#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SI bound to: 0 - type: integer
Parameter C_DIR bound to: 0 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_NUM_M bound to: 7 - type: integer
Parameter C_NUM_M_LOG bound to: 3 - type: integer
Parameter C_ACCEPTANCE bound to: 2 - type: integer
Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_THREAD_ID_WIDTH bound to: 0 - type: integer
Parameter C_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AMESG_WIDTH bound to: 11 - type: integer
Parameter C_RMESG_WIDTH bound to: 3 - type: integer
Parameter C_BASE_ID bound to: 2'b00
Parameter C_HIGH_ID bound to: 2'b00
Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_SINGLE_THREAD bound to: 0 - type: integer
Parameter C_TARGET_QUAL bound to: 7'b1111111
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_RANGE_CHECK bound to: 1 - type: integer
Parameter C_ADDR_DECODE bound to: 1 - type: integer
Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_WRITE bound to: 0 - type: integer
Parameter P_READ bound to: 1 - type: integer
Parameter P_RMUX_MESG_WIDTH bound to: 6 - type: integer
Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer
Parameter P_NONSECURE_BIT bound to: 1 - type: integer
Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer
Parameter P_M_AXILITE bound to: 7'b0000000
Parameter P_FIXED bound to: 2'b00
Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer
Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer
Parameter P_NUM_ID_VAL bound to: 1 - type: integer
Parameter P_NUM_THREADS bound to: 1 - type: integer
Parameter P_M_SECURE_MASK bound to: 7'b0000000
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_RATIO bound to: 8 - type: integer
Parameter C_SEL_WIDTH bound to: 3 - type: integer
Parameter C_DATA_WIDTH bound to: 6 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' (155#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized0' (155#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_splitter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
Parameter C_NUM_M bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_splitter' (156#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4461]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_wdata_router' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4736]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_WMESG_WIDTH bound to: 38 - type: integer
Parameter C_NUM_MASTER_SLOTS bound to: 8 - type: integer
Parameter C_SELECT_WIDTH bound to: 4 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 4 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer
Parameter C_USE_FULL bound to: 1 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
Parameter ZERO bound to: 2'b10
Parameter ONE bound to: 2'b11
Parameter TWO bound to: 2'b01
INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' (157#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_wdata_router' (158#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4736]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SI bound to: 1 - type: integer
Parameter C_DIR bound to: 1 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_NUM_M bound to: 7 - type: integer
Parameter C_NUM_M_LOG bound to: 3 - type: integer
Parameter C_ACCEPTANCE bound to: 2 - type: integer
Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_THREAD_ID_WIDTH bound to: 1 - type: integer
Parameter C_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AMESG_WIDTH bound to: 11 - type: integer
Parameter C_RMESG_WIDTH bound to: 35 - type: integer
Parameter C_BASE_ID bound to: 2'b10
Parameter C_HIGH_ID bound to: 2'b11
Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_SINGLE_THREAD bound to: 0 - type: integer
Parameter C_TARGET_QUAL bound to: 7'b1111111
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_RANGE_CHECK bound to: 1 - type: integer
Parameter C_ADDR_DECODE bound to: 1 - type: integer
Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_WRITE bound to: 0 - type: integer
Parameter P_READ bound to: 1 - type: integer
Parameter P_RMUX_MESG_WIDTH bound to: 38 - type: integer
Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer
Parameter P_NONSECURE_BIT bound to: 1 - type: integer
Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer
Parameter P_M_AXILITE bound to: 7'b0000000
Parameter P_FIXED bound to: 2'b00
Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer
Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer
Parameter P_NUM_ID_VAL bound to: 2 - type: integer
Parameter P_NUM_THREADS bound to: 2 - type: integer
Parameter P_M_SECURE_MASK bound to: 7'b0000000
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_arbiter_resp' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:1025]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_S bound to: 8 - type: integer
Parameter C_NUM_S_LOG bound to: 3 - type: integer
Parameter C_GRANT_ENC bound to: 1 - type: integer
Parameter C_GRANT_HOT bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_arbiter_resp' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:1025]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized1' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SI bound to: 1 - type: integer
Parameter C_DIR bound to: 0 - type: integer
Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer
Parameter C_NUM_M bound to: 7 - type: integer
Parameter C_NUM_M_LOG bound to: 3 - type: integer
Parameter C_ACCEPTANCE bound to: 2 - type: integer
Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer
Parameter C_ID_WIDTH bound to: 2 - type: integer
Parameter C_THREAD_ID_WIDTH bound to: 1 - type: integer
Parameter C_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AMESG_WIDTH bound to: 11 - type: integer
Parameter C_RMESG_WIDTH bound to: 3 - type: integer
Parameter C_BASE_ID bound to: 2'b10
Parameter C_HIGH_ID bound to: 2'b11
Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111
Parameter C_SINGLE_THREAD bound to: 0 - type: integer
Parameter C_TARGET_QUAL bound to: 7'b1111111
Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_RANGE_CHECK bound to: 1 - type: integer
Parameter C_ADDR_DECODE bound to: 1 - type: integer
Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter C_DEBUG bound to: 1 - type: integer
Parameter P_WRITE bound to: 0 - type: integer
Parameter P_READ bound to: 1 - type: integer
Parameter P_RMUX_MESG_WIDTH bound to: 6 - type: integer
Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer
Parameter P_NONSECURE_BIT bound to: 1 - type: integer
Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer
Parameter P_M_AXILITE bound to: 7'b0000000
Parameter P_FIXED bound to: 2'b00
Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer
Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer
Parameter P_NUM_ID_VAL bound to: 2 - type: integer
Parameter P_NUM_THREADS bound to: 2 - type: integer
Parameter P_M_SECURE_MASK bound to: 7'b0000000
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized2' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_addr_decoder__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_TARGETS bound to: 2 - type: integer
Parameter C_NUM_TARGETS_LOG bound to: 1 - type: integer
Parameter C_NUM_RANGES bound to: 1 - type: integer
Parameter C_ADDR_WIDTH bound to: 2 - type: integer
Parameter C_TARGET_ENC bound to: 1 - type: integer
Parameter C_TARGET_HOT bound to: 1 - type: integer
Parameter C_REGION_ENC bound to: 0 - type: integer
Parameter C_BASE_ADDR bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000
Parameter C_HIGH_ADDR bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000
Parameter C_TARGET_QUAL bound to: 3'b011
Parameter C_RESOLUTION bound to: 0 - type: integer
Parameter C_COMPARATOR_THRESHOLD bound to: 6 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_addr_decoder__parameterized0' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 8 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer
Parameter C_USE_FULL bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698]
INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_wdata_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4561]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_WMESG_WIDTH bound to: 38 - type: integer
Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer
Parameter C_SELECT_WIDTH bound to: 1 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 1 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer
Parameter C_USE_FULL bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
Parameter ZERO bound to: 2'b10
Parameter ONE bound to: 2'b11
Parameter TWO bound to: 2'b01
INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_RATIO bound to: 2 - type: integer
Parameter C_SEL_WIDTH bound to: 1 - type: integer
Parameter C_DATA_WIDTH bound to: 38 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' (159#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452]
INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_wdata_mux' (160#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4561]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704]
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_REG_CONFIG_AW bound to: 0 - type: integer
Parameter C_REG_CONFIG_W bound to: 0 - type: integer
Parameter C_REG_CONFIG_B bound to: 7 - type: integer
Parameter C_REG_CONFIG_AR bound to: 0 - type: integer
Parameter C_REG_CONFIG_R bound to: 1 - type: integer
Parameter C_RESERVE_MODE bound to: 0 - type: integer
Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer
Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter P_FORWARD bound to: 0 - type: integer
Parameter P_RESPONSE bound to: 1 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized1' (160#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AWPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter C_ARPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer
Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer
Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer
Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer
Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer
Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer
Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer
Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer
Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer
Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer
Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer
Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer
Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer
Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer
Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer
Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer
Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer
Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer
Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer
Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_WID_INDEX bound to: 37 - type: integer
Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer
Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer
Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BID_INDEX bound to: 2 - type: integer
Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer
Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer
Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer
Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer
Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer
Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer
Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer
Parameter G_AXI_RID_INDEX bound to: 35 - type: integer
Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer
Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer
Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer
Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized1' (160#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized7' (160#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 37 - type: integer
Parameter C_REG_CONFIG bound to: 0 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized8' (160#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476]
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 4 - type: integer
Parameter C_REG_CONFIG bound to: 7 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 37 - type: integer
Parameter C_REG_CONFIG bound to: 1 - type: integer
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 8 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer
Parameter C_USE_FULL bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_WMESG_WIDTH bound to: 38 - type: integer
Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer
Parameter C_SELECT_WIDTH bound to: 1 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 0 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_WIDTH bound to: 1 - type: integer
Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer
Parameter C_USE_FULL bound to: 0 - type: integer
Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer
Parameter P_EMPTY bound to: 2'b11
Parameter P_ALMOSTEMPTY bound to: 2'b00
Parameter P_ALMOSTFULL_TEMP bound to: 3'b110
Parameter P_ALMOSTFULL bound to: 2'b10
Parameter P_NUM_REPS bound to: 1 - type: integer
Parameter ZERO bound to: 2'b10
Parameter ONE bound to: 2'b11
Parameter TWO bound to: 2'b01
INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986]
WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122]
Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_RESP bound to: 3 - type: integer
Parameter P_WRITE_IDLE bound to: 2'b00
Parameter P_WRITE_DATA bound to: 2'b01
Parameter P_WRITE_RESP bound to: 2'b10
Parameter P_READ_IDLE bound to: 1'b0
Parameter P_READ_DATA bound to: 1'b1
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3633]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_NUM_S bound to: 2 - type: integer
Parameter C_NUM_S_LOG bound to: 1 - type: integer
Parameter C_NUM_M bound to: 8 - type: integer
Parameter C_MESG_WIDTH bound to: 65 - type: integer
Parameter C_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
Parameter P_PRIO_MASK bound to: 2'b00
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_RATIO bound to: 2 - type: integer
Parameter C_SEL_WIDTH bound to: 1 - type: integer
Parameter C_DATA_WIDTH bound to: 65 - type: integer
Parameter C_FAMILY bound to: rtl - type: string
Parameter C_RATIO bound to: 2 - type: integer
Parameter C_SEL_WIDTH bound to: 1 - type: integer
Parameter C_DATA_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_interconnect_0_0' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2823]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_quad_spi_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97]
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SELECT_XPM bound to: 1 - type: integer
Parameter C_SUB_FAMILY bound to: virtex7 - type: string
Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string
Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer
Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer
Parameter C_XIP_MODE bound to: 0 - type: integer
Parameter C_UC_FAMILY bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_SCK_RATIO bound to: 16 - type: integer
Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_NEW_SEQ_EN bound to: 1 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer
Parameter C_SPI_MEMORY bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer
Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_S_AXI4_BASEADDR bound to: 32'b11111111111111111111111111111111
Parameter C_S_AXI4_HIGHADDR bound to: 32'b00000000000000000000000000000000
Parameter C_LSB_STUP bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36696]
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SELECT_XPM bound to: 1 - type: integer
Parameter C_SUB_FAMILY bound to: virtex7 - type: string
Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string
Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer
Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer
Parameter C_XIP_MODE bound to: 0 - type: integer
Parameter C_UC_FAMILY bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_SCK_RATIO bound to: 16 - type: integer
Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_NEW_SEQ_EN bound to: 1 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer
Parameter C_SPI_MEMORY bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer
Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer
Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer
Parameter C_LSB_STUP bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_top' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34957]
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SELECT_XPM bound to: 1 - type: integer
Parameter C_SUB_FAMILY bound to: virtex7 - type: string
Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string
Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer
Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer
Parameter C_XIP_MODE bound to: 0 - type: integer
Parameter C_UC_FAMILY bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_SCK_RATIO bound to: 16 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_SPI_MEMORY bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer
Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer
Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer
Parameter C_LSB_STUP bound to: 0 - type: integer
Parameter C_DUAL_MODE bound to: 0 - type: integer
Parameter C_NEW_SEQ_EN bound to: 1 - type: integer
Parameter C_STARTUP_EXT bound to: 0 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000001111100
Parameter C_USE_WSTRB bound to: 1 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 20 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000
Parameter C_IPIF_ABUS_WIDTH bound to: 7 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 124 - type: integer
Parameter C_USE_WSTRB bound to: 1 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 20 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
Parameter C_BUS_AWIDTH bound to: 7 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 124 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized65' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 1 - type: integer
Parameter C_AW bound to: 7 - type: integer
Parameter C_BAR bound to: 7'b0000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized65' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized66' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 7 - type: integer
Parameter C_BAR bound to: 7'b1000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized66' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized67' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
Parameter C_AB bound to: 2 - type: integer
Parameter C_AW bound to: 7 - type: integer
Parameter C_BAR bound to: 7'b1100000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized67' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized2' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized2' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized2' (166#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'qspi_core_interface' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19201]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_SUB_FAMILY bound to: virtex7 - type: string
Parameter C_SELECT_XPM bound to: 1 - type: integer
Parameter C_UC_FAMILY bound to: 0 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_NUM_CE_SIGNALS bound to: 32 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_SCK_RATIO bound to: 16 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_SPI_MEMORY bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer
Parameter C_FIFO_EXIST bound to: 1 - type: integer
Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer
Parameter C_OCCUPANCY_NUM_BITS bound to: 4 - type: integer
Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer
Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer
Parameter C_LSB_STUP bound to: 0 - type: integer
Parameter C_DUAL_MODE bound to: 0 - type: integer
Parameter C_NEW_SEQ_EN bound to: 1 - type: integer
Parameter C_STARTUP_EXT bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'reset_sync_module' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2426]
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'reset_sync_module' (167#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2426]
INFO: [Synth 8-638] synthesizing module 'cross_clk_sync_fifo_1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:14937]
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cross_clk_sync_fifo_1' (168#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:14937]
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter READ_MODE bound to: fwft - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter USE_ADV_FEATURES bound to: 1f1f - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
Parameter USE_ADV_FEATURES bound to: 1f1f - type: string
Parameter READ_MODE bound to: fwft - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111
Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
Parameter P_ECC_MODE bound to: 0 - type: integer
Parameter P_READ_MODE bound to: 1 - type: integer
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter USE_ADV_FEATURES bound to: 1f1f - type: string
Parameter READ_MODE bound to: 1 - type: integer
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter invalid bound to: 0 - type: integer
Parameter stage1_valid bound to: 2 - type: integer
Parameter stage2_valid bound to: 1 - type: integer
Parameter both_stages_valid bound to: 3 - type: integer
Parameter FIFO_MEM_TYPE bound to: 0 - type: integer
Parameter RD_MODE bound to: 1 - type: integer
Parameter ENABLE_ECC bound to: 0 - type: integer
Parameter FIFO_READ_DEPTH bound to: 16 - type: integer
Parameter FIFO_SIZE bound to: 512 - type: integer
Parameter WR_WIDTH_LOG bound to: 5 - type: integer
Parameter WR_DEPTH_LOG bound to: 4 - type: integer
Parameter WR_PNTR_WIDTH bound to: 4 - type: integer
Parameter RD_PNTR_WIDTH bound to: 4 - type: integer
Parameter FULL_RST_VAL bound to: 1'b0
Parameter WR_RD_RATIO bound to: 0 - type: integer
Parameter PF_THRESH_ADJ bound to: 8 - type: integer
Parameter PE_THRESH_ADJ bound to: 8 - type: integer
Parameter PF_THRESH_MIN bound to: 7 - type: integer
Parameter PF_THRESH_MAX bound to: 11 - type: integer
Parameter PE_THRESH_MIN bound to: 5 - type: integer
Parameter PE_THRESH_MAX bound to: 11 - type: integer
Parameter WR_DC_WIDTH_EXT bound to: 5 - type: integer
Parameter RD_DC_WIDTH_EXT bound to: 5 - type: integer
Parameter RD_LATENCY bound to: 2 - type: integer
Parameter WIDTH_RATIO bound to: 1 - type: integer
Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111
Parameter EN_OF bound to: 1'b1
Parameter EN_PF bound to: 1'b1
Parameter EN_WDC bound to: 1'b1
Parameter EN_AF bound to: 1'b1
Parameter EN_WACK bound to: 1'b1
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
Parameter EN_UF bound to: 1'b1
Parameter EN_PE bound to: 1'b1
Parameter EN_RDC bound to: 1'b1
Parameter EN_AE bound to: 1'b1
Parameter EN_DVLD bound to: 1'b1
Parameter COUNTER_WIDTH bound to: 4 - type: integer
Parameter RESET_VALUE bound to: 3 - type: integer
Parameter COUNTER_WIDTH bound to: 4 - type: integer
Parameter RESET_VALUE bound to: 2 - type: integer
Parameter MEMORY_TYPE bound to: 1 - type: integer
Parameter MEMORY_SIZE bound to: 512 - type: integer
Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer
Parameter CLOCKING_MODE bound to: 1 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter MEMORY_INIT_FILE bound to: none - type: string
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
Parameter USE_MEM_INIT bound to: 0 - type: integer
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer
Parameter MESSAGE_CONTROL bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer
Parameter ADDR_WIDTH_A bound to: 4 - type: integer
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
Parameter READ_LATENCY_A bound to: 2 - type: integer
Parameter WRITE_MODE_A bound to: 2 - type: integer
Parameter RST_MODE_A bound to: SYNC - type: string
Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer
Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer
Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer
Parameter ADDR_WIDTH_B bound to: 4 - type: integer
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
Parameter READ_LATENCY_B bound to: 2 - type: integer
Parameter WRITE_MODE_B bound to: 2 - type: integer
Parameter RST_MODE_B bound to: SYNC - type: string
Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string
Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer
Parameter P_MAX_DEPTH_DATA bound to: 16 - type: integer
Parameter P_ECC_MODE bound to: no_ecc - type: string
Parameter P_MEMORY_OPT bound to: yes - type: string
Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer
Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer
Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer
Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer
Parameter P_WIDTH_ADDR_WRITE_A bound to: 4 - type: integer
Parameter P_WIDTH_ADDR_WRITE_B bound to: 4 - type: integer
Parameter P_WIDTH_ADDR_READ_A bound to: 4 - type: integer
Parameter P_WIDTH_ADDR_READ_B bound to: 4 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer
Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer
Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer
Parameter P_SDP_WRITE_MODE bound to: yes - type: string
Parameter rsta_loop_iter bound to: 32 - type: integer
Parameter rstb_loop_iter bound to: 32 - type: integer
Parameter NUM_CHAR_LOC bound to: 0 - type: integer
Parameter MAX_NUM_CHAR bound to: 0 - type: integer
Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer
Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:484]
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
Parameter DEST_SYNC_FF bound to: 2 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 4 - type: integer
Parameter REG_WIDTH bound to: 4 - type: integer
Parameter DEST_SYNC_FF bound to: 4 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 5 - type: integer
Parameter REG_WIDTH bound to: 5 - type: integer
Parameter DEST_SYNC_FF bound to: 2 - type: integer
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter REG_OUTPUT bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter WIDTH bound to: 5 - type: integer
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246]
Parameter COUNTER_WIDTH bound to: 2 - type: integer
Parameter RESET_VALUE bound to: 0 - type: integer
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter DEST_SYNC_FF bound to: 2 - type: integer
Parameter INIT bound to: 32'sb00000000000000000000000000000000
Parameter INIT_SYNC_FF bound to: 1 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter DEF_VAL bound to: 1'b0
Parameter COUNTER_WIDTH bound to: 5 - type: integer
Parameter RESET_VALUE bound to: 0 - type: integer
Parameter COUNTER_WIDTH bound to: 4 - type: integer
Parameter RESET_VALUE bound to: 1 - type: integer
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 1 - type: integer
Parameter C_MTBF_STAGES bound to: 2 - type: integer
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized6' (168#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_19_counter_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:669]
Parameter C_NUM_BITS bound to: 4 - type: integer
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_19_counter_f' (169#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:669]
INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_DATA_WIDTH bound to: 32 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 16 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer
Parameter C_HAS_RD_ACK bound to: 1 - type: integer
Parameter C_HAS_RD_COUNT bound to: 1 - type: integer
Parameter C_HAS_RD_ERR bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 1 - type: integer
Parameter C_HAS_WR_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_ERR bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_RD_ACK_LOW bound to: 0 - type: integer
Parameter C_RD_COUNT_WIDTH bound to: 5 - type: integer
Parameter C_RD_ERR_LOW bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_USE_BLOCKMEM bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_COUNT_WIDTH bound to: 5 - type: integer
Parameter C_WR_ERR_LOW bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer
Parameter C_XPM_FIFO bound to: 1 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter READ_MODE bound to: fwft - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: fwft - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111
Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer
Parameter P_COMMON_CLOCK bound to: 0 - type: integer
Parameter P_ECC_MODE bound to: 0 - type: integer
Parameter P_READ_MODE bound to: 1 - type: integer
Parameter P_WAKEUP_TIME bound to: 2 - type: integer
Parameter COMMON_CLOCK bound to: 0 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer
Parameter ECC_MODE bound to: 0 - type: integer
Parameter SIM_ASSERT_CHK bound to: 0 - type: integer
Parameter CASCADE_HEIGHT bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_MODE bound to: 1 - type: integer
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter READ_DATA_WIDTH bound to: 32 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter VERSION bound to: 0 - type: integer
Parameter invalid bound to: 0 - type: integer
Parameter stage1_valid bound to: 2 - type: integer
Parameter stage2_valid bound to: 1 - type: integer
Parameter both_stages_valid bound to: 3 - type: integer
Parameter FIFO_MEM_TYPE bound to: 0 - type: integer
Parameter RD_MODE bound to: 1 - type: integer
Parameter ENABLE_ECC bound to: 0 - type: integer
Parameter FIFO_READ_DEPTH bound to: 16 - type: integer
Parameter FIFO_SIZE bound to: 512 - type: integer
Parameter WR_WIDTH_LOG bound to: 5 - type: integer
Parameter WR_DEPTH_LOG bound to: 4 - type: integer
Parameter WR_PNTR_WIDTH bound to: 4 - type: integer
Parameter RD_PNTR_WIDTH bound to: 4 - type: integer
Parameter FULL_RST_VAL bound to: 1'b1
Parameter WR_RD_RATIO bound to: 0 - type: integer
Parameter PF_THRESH_ADJ bound to: 8 - type: integer
Parameter PE_THRESH_ADJ bound to: 8 - type: integer
Parameter PF_THRESH_MIN bound to: 7 - type: integer
Parameter PF_THRESH_MAX bound to: 11 - type: integer
Parameter PE_THRESH_MIN bound to: 5 - type: integer
Parameter PE_THRESH_MAX bound to: 11 - type: integer
Parameter WR_DC_WIDTH_EXT bound to: 5 - type: integer
Parameter RD_DC_WIDTH_EXT bound to: 5 - type: integer
Parameter RD_LATENCY bound to: 2 - type: integer
Parameter WIDTH_RATIO bound to: 1 - type: integer
Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111
Parameter EN_OF bound to: 1'b1
Parameter EN_PF bound to: 1'b1
Parameter EN_WDC bound to: 1'b1
Parameter EN_AF bound to: 1'b1
Parameter EN_WACK bound to: 1'b1
Parameter FG_EQ_ASYM_DOUT bound to: 1'b0
Parameter EN_UF bound to: 1'b1
Parameter EN_PE bound to: 1'b1
Parameter EN_RDC bound to: 1'b1
Parameter EN_AE bound to: 1'b1
Parameter EN_DVLD bound to: 1'b1
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235]
INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized1' (169#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255]
INFO: [Synth 8-638] synthesizing module 'qspi_fifo_ifmodule' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13461]
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'qspi_fifo_ifmodule' (170#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13461]
INFO: [Synth 8-638] synthesizing module 'qspi_occupancy_reg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:3647]
Parameter C_OCCUPANCY_NUM_BITS bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'qspi_occupancy_reg' (171#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:3647]
INFO: [Synth 8-638] synthesizing module 'qspi_mode_0_module' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:8775]
Parameter C_SCK_RATIO bound to: 16 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer
Parameter C_SUB_FAMILY bound to: virtex7 - type: string
Parameter C_FIFO_EXIST bound to: 1 - type: integer
Parameter C_DUAL_MODE bound to: 0 - type: integer
Parameter C_STARTUP_EXT bound to: 0 - type: integer
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b1
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'qspi_mode_0_module' (172#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:8775]
INFO: [Synth 8-638] synthesizing module 'qspi_cntrl_reg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13816]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer
Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'qspi_cntrl_reg' (173#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13816]
INFO: [Synth 8-638] synthesizing module 'qspi_status_slave_sel_reg' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2658]
Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer
INFO: [Synth 8-256] done synthesizing module 'qspi_status_slave_sel_reg' (174#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2658]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_19_soft_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:874]
Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer
Parameter C_RESET_WIDTH bound to: 16 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_19_soft_reset' (175#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:874]
INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
Parameter C_NUM_CE bound to: 16 - type: integer
Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer
Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011
Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool
Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized1' (175#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
WARNING: [Synth 8-3848] Net cfgclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19178]
WARNING: [Synth 8-3848] Net cfgmclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19179]
WARNING: [Synth 8-3848] Net eos in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19180]
WARNING: [Synth 8-3848] Net preq in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19181]
WARNING: [Synth 8-3848] Net di in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19182]
INFO: [Synth 8-256] done synthesizing module 'qspi_core_interface' (176#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19201]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
WARNING: [Synth 8-3848] Net s_axi4_awready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34848]
WARNING: [Synth 8-3848] Net s_axi4_wready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34856]
WARNING: [Synth 8-3848] Net s_axi4_bid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34860]
WARNING: [Synth 8-3848] Net s_axi4_bresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34861]
WARNING: [Synth 8-3848] Net s_axi4_bvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34862]
WARNING: [Synth 8-3848] Net s_axi4_arready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34876]
WARNING: [Synth 8-3848] Net s_axi4_rid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34880]
WARNING: [Synth 8-3848] Net s_axi4_rdata in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34881]
WARNING: [Synth 8-3848] Net s_axi4_rresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34882]
WARNING: [Synth 8-3848] Net s_axi4_rlast in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34883]
WARNING: [Synth 8-3848] Net s_axi4_rvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34884]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_top' (177#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34957]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
WARNING: [Synth 8-3848] Net io0_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36639]
WARNING: [Synth 8-3848] Net io0_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36640]
WARNING: [Synth 8-3848] Net io1_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36643]
WARNING: [Synth 8-3848] Net io1_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36644]
WARNING: [Synth 8-3848] Net io2_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36649]
WARNING: [Synth 8-3848] Net io2_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36650]
WARNING: [Synth 8-3848] Net io3_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36653]
WARNING: [Synth 8-3848] Net io3_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36654]
WARNING: [Synth 8-3848] Net ss_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36669]
WARNING: [Synth 8-3848] Net ss_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36670]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi' (178#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36696]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_quad_spi_0_0' (179#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_jtag_axi_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103]
Parameter RD_TXN_QUEUE_LENGTH bound to: 1 - type: integer
Parameter WR_TXN_QUEUE_LENGTH bound to: 1 - type: integer
Parameter M_AXI_ID_WIDTH bound to: 1 - type: integer
Parameter M_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter FAMILY bound to: virtex7 - type: string
Parameter M_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter M_HAS_BURST bound to: 1 - type: integer
Parameter PROTOCOL bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_jtag_axi_0_0' (217#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100]
Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_INCLUDE_INTR bound to: 1 - type: integer
Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235]
Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_INCLUDE_INTR bound to: 1 - type: integer
Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111
Parameter C_USE_WSTRB bound to: 1 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227]
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001
Parameter C_IPIF_ABUS_WIDTH bound to: 11 - type: integer
Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer
Parameter C_USE_WSTRB bound to: 1 - type: integer
Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176]
Parameter C_BUS_AWIDTH bound to: 10 - type: integer
Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer
Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111
Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 5 - type: integer
Parameter C_AW bound to: 10 - type: integer
Parameter C_BAR bound to: 10'b0000000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 3 - type: integer
Parameter C_AW bound to: 3 - type: integer
Parameter C_BAR bound to: 3'b111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 10 - type: integer
Parameter C_BAR bound to: 10'b0001000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b0111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1001
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1010
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1011
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1100
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1101
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1110
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 4 - type: integer
Parameter C_AW bound to: 4 - type: integer
Parameter C_BAR bound to: 4'b1111
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
Parameter C_AB bound to: 1 - type: integer
Parameter C_AW bound to: 10 - type: integer
Parameter C_BAR bound to: 10'b1000000000
Parameter C_FAMILY bound to: nofamily - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' (218#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' (219#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:381]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' (220#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' (221#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241]
Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter CE_NUMBERS bound to: 9 - type: integer
Parameter IP_INTR_NUM bound to: 17 - type: integer
Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string
Parameter MUX_ADDR_NO bound to: 5 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186]
Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_FAMILY bound to: virtex7 - type: string
Parameter CE_NUMBERS bound to: 9 - type: integer
Parameter IP_INTR_NUM bound to: 17 - type: integer
Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string
Parameter MUX_ADDR_NO bound to: 5 - type: integer
Parameter INIT_40 bound to: 16'b0000000000000000
Parameter INIT_41 bound to: 16'b0010000110100000
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0111111100000001
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' (222#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142]
Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer
Parameter C_RESET_WIDTH bound to: 16 - type: integer
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter IS_CE_INVERTED bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
Parameter IS_S_INVERTED bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' (223#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142]
INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240]
Parameter C_NUM_CE bound to: 16 - type: integer
Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer
Parameter C_IP_INTR_MODE_ARRAY bound to: 544'b0000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101
Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool
Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool
Parameter C_IPIF_DWIDTH bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' (224#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' (225#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235]
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0' (226#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys' (227#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4667]
Parameter DEVICE_ID bound to: 28'b0011011001010001000010010011
Parameter ICAP_WIDTH bound to: X32 - type: string
Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_wrapper' (229#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: 1 - type: bool
Parameter IOSTANDARD bound to: DEFAULT - type: string
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
WARNING: [Synth 8-3848] Net ipb_clk_i in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:524]
WARNING: [Synth 8-3848] Net rod_gp_led in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:148]
WARNING: [Synth 8-3848] Net FP_GP_LED_B in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:149]
INFO: [Synth 8-256] done synthesizing module 'ROD_system' (230#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:207]
INFO: [Synth 8-638] synthesizing module 'aurora_64b_rx_12ch' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:339]
Parameter CLKCM_CFG bound to: TRUE - type: string
Parameter CLKRCV_TRST bound to: TRUE - type: string
Parameter CLKSWING_CFG bound to: 2'b11
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_exdes' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:100]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:119]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:120]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:121]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:122]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:123]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:138]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:155]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:156]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:157]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:164]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:165]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:170]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:171]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:178]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:179]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:180]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:182]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:213]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:222]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:223]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:224]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:225]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:226]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:155]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_CLOCK_MODULE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_CLOCK_MODULE' (233#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:94]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 1 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 3 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_cdc_sync_exdes' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 1 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 3 - type: integer
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:300]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:302]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:303]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:304]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:305]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:306]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:307]
WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:135]
WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:143]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_cdc_sync_exdes' (234#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' (235#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_gt_common_wrapper' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84]
Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string
Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000
Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111
Parameter QPLL_CLKOUT_CFG bound to: 4'b1111
Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000
Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0
Parameter QPLL_CP bound to: 10'b0000011111
Parameter QPLL_CP_MONITOR_EN bound to: 1'b0
Parameter QPLL_DMONITOR_SEL bound to: 1'b0
Parameter QPLL_FBDIV bound to: 10'b0010000000
Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0
Parameter QPLL_FBDIV_RATIO bound to: 1'b1
Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110
Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000
Parameter QPLL_LPF bound to: 4'b1111
Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter QPLL_RP_COMP bound to: 1'b0
Parameter QPLL_VTRL_RESET bound to: 2'b00
Parameter RCAL_CFG bound to: 2'b00
Parameter RSVD_ATTR0 bound to: 16'b0000000000000000
Parameter RSVD_ATTR1 bound to: 16'b0000000000000000
Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001
Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_gt_common_wrapper' (236#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/aurora_rx_1q_stub.vhdl:70]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_support' (237#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:155]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:735]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_exdes' (238#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:100]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:125]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:126]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:127]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:128]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:129]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:144]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:161]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:162]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:163]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:170]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:171]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:176]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:178]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:184]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:185]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:186]
INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:188]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:219]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:228]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:229]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:230]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:231]
INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:232]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' (240#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:94]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 1 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 3 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 1 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 3 - type: integer
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:300]
INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:135]
WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:143]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' (241#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' (242#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93]
Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string
Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000
Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111
Parameter QPLL_CLKOUT_CFG bound to: 4'b1111
Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000
Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0
Parameter QPLL_CP bound to: 10'b0000011111
Parameter QPLL_CP_MONITOR_EN bound to: 1'b0
Parameter QPLL_DMONITOR_SEL bound to: 1'b0
Parameter QPLL_FBDIV bound to: 10'b0010000000
Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0
Parameter QPLL_FBDIV_RATIO bound to: 1'b1
Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110
Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000
Parameter QPLL_LPF bound to: 4'b1111
Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter QPLL_RP_COMP bound to: 1'b0
Parameter QPLL_VTRL_RESET bound to: 2'b00
Parameter RCAL_CFG bound to: 2'b00
Parameter RSVD_ATTR0 bound to: 16'b0000000000000000
Parameter RSVD_ATTR1 bound to: 16'b0000000000000000
Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001
Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000
Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111
Parameter QPLL_CLKOUT_CFG bound to: 4'b1111
Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000
Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0
Parameter QPLL_CP bound to: 10'b0000011111
Parameter QPLL_CP_MONITOR_EN bound to: 1'b0
Parameter QPLL_DMONITOR_SEL bound to: 1'b0
Parameter QPLL_FBDIV bound to: 10'b0010000000
Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0
Parameter QPLL_FBDIV_RATIO bound to: 1'b1
Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110
Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000
Parameter QPLL_LPF bound to: 4'b1111
Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter QPLL_RP_COMP bound to: 1'b0
Parameter QPLL_VTRL_RESET bound to: 2'b00
Parameter RCAL_CFG bound to: 2'b00
Parameter RSVD_ATTR0 bound to: 16'b0000000000000000
Parameter RSVD_ATTR1 bound to: 16'b0000000000000000
Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001
Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' (243#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93]
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/aurora_rx_4l_64b_stub.vhdl:75]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support' (244#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:745]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes' (245#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 0 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107]
Parameter USE_COMMON_BLOCK bound to: 0 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154]
Parameter USE_COMMON_BLOCK bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support__parameterized1' (245#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:745]
INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' (245#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107]
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
Parameter USE_COMMON_BLOCK bound to: 1 - type: integer
Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer
Parameter USE_CHIPSCOPE bound to: 0 - type: bool
WARNING: [Synth 8-5640] Port 'ck_pwr_dnb' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'ref_ck_sel' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'ck_syncb' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'gttx_reset_in' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'gtrx_reset_in' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'cpll_reset_in' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
WARNING: [Synth 8-5640] Port 'qpll_reset_in' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521]
INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_exdes' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158]
Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer
Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer
Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:147]
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87]
INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' (246#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87]
INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/rod_RO_Tx_stub.vhdl:51]
INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_support' (247#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:147]
INFO: [Synth 8-638] synthesizing module 'vio_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_0_stub.vhdl:14]
INFO: [Synth 8-638] synthesizing module 'ila_1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_1_stub.vhdl:14]
WARNING: [Synth 8-5640] Port 'probe_out1' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:357]
INFO: [Synth 8-638] synthesizing module 'vio_RO_CTL_test' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_RO_CTL_test_stub.vhdl:20]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rod_RO_Tx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:613]
INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_exdes' (249#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158]
Parameter COUNTER_WIDTH bound to: 6 - type: integer
INFO: [Synth 8-638] synthesizing module 'pulse_stretch' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
Parameter COUNTER_WIDTH bound to: 6 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pulse_stretch' (250#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
INFO: [Synth 8-638] synthesizing module 'combined_ttc_rx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:91]
Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer
Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer
Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_support' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:156]
Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer
INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87]
INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' (251#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87]
WARNING: [Synth 8-5640] Port 'gt0_rxoutclkfabric_out' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:163]
INFO: [Synth 8-638] synthesizing module 'MGT_combined_ttc_rx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/MGT_combined_ttc_rx_stub.vhdl:53]
WARNING: [Synth 8-3848] Net GT0_DRPDO_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:143]
WARNING: [Synth 8-3848] Net GT0_DRPRDY_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:145]
WARNING: [Synth 8-3848] Net gt0_qplloutclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:371]
WARNING: [Synth 8-3848] Net gt0_qplloutrefclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:372]
INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_support' (252#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:156]
Parameter RX_DATA_WIDTH bound to: 32 - type: integer
Parameter RXCTRL_WIDTH bound to: 4 - type: integer
Parameter WORDS_IN_BRAM bound to: 512 - type: integer
Parameter CHANBOND_SEQ_LEN bound to: 1 - type: integer
Parameter COMMA_DOUBLE bound to: 16'b0000010010111100
Parameter START_OF_PACKET_CHAR bound to: 32'b10100101000011110000010110111100
INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124]
Parameter RX_DATA_WIDTH bound to: 32 - type: integer
Parameter RXCTRL_WIDTH bound to: 4 - type: integer
Parameter WORDS_IN_BRAM bound to: 512 - type: integer
Parameter CHANBOND_SEQ_LEN bound to: 1 - type: integer
Parameter COMMA_DOUBLE bound to: 16'b0000010010111100
Parameter START_OF_PACKET_CHAR bound to: -1525742148 - type: integer
Parameter INIT bound to: 1'b0
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:712]
WARNING: [Synth 8-3848] Net slip_assert_r in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:171]
WARNING: [Synth 8-3848] Net input_to_chanbond_reg_i in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:189]
INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' (253#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124]
INFO: [Synth 8-638] synthesizing module 'vio_ttc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_ttc_stub.vhdl:14]
INFO: [Synth 8-638] synthesizing module 'ila_2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_2_stub.vhdl:24]
INFO: [Synth 8-638] synthesizing module 'rx_registers' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'rx_registers' (254#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:48]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gt0_frame_check'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:744]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'inst_regs'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:893]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'sume_RO_Rx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:599]
WARNING: [Synth 8-3848] Net gt0_cpllrefclklost_i in module/entity combined_ttc_rx does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:358]
INFO: [Synth 8-256] done synthesizing module 'combined_ttc_rx' (255#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:91]
INFO: [Synth 8-638] synthesizing module 'aurora_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'aurora_reset' (256#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46]
INFO: [Synth 8-638] synthesizing module 'pwr_on_timer' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45]
Parameter max_count bound to: 32'b00000000000000111111111111111111
INFO: [Synth 8-256] done synthesizing module 'pwr_on_timer' (257#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'aurora_64b_rx_12ch' (258#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:339]
INFO: [Synth 8-638] synthesizing module 'axi_ch0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/axi_ch0_stub.vhdl:17]
INFO: [Synth 8-638] synthesizing module 'pp_ctrl_vio' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/pp_ctrl_vio_stub.vhdl:18]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_user_clock_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_stat_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'aurora_chan_control_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 'bp_data_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tvalid_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tlast_23' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_12' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_13' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_14' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_15' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_16' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_17' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_18' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_19' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_20' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_21' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
WARNING: [Synth 8-5640] Port 's_axis_tready_22' is missing in component declaration [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:858]
INFO: [Common 17-14] Message 'Synth 8-5640' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter jfex bound to: 0 - type: integer
Parameter sim bound to: 0 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter bp_width bound to: 64 - type: integer
INFO: [Synth 8-638] synthesizing module 'packet_processor' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:504]
Parameter SIM bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter header_width bound to: 64 - type: integer
Parameter event_width bound to: 64 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
Parameter COUNTER_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized1' (258#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
Parameter sim bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'input_fifos' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1062]
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter efex bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 26 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 5 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (258#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
INFO: [Synth 8-638] synthesizing module 'backplane_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:72]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 11 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 4 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (258#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:178]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:179]
INFO: [Synth 8-638] synthesizing module 'ipbus_reg_v' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55]
Parameter N_REG bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'ipbus_reg_v' (259#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:292]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:293]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:327]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:328]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:347]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:348]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:369]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:370]
WARNING: [Synth 8-614] signal 'chan_dis' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:384]
WARNING: [Synth 8-614] signal 'backplane_control' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:411]
INFO: [Synth 8-638] synthesizing module 'priority_encoder' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'priority_encoder' (260#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43]
Parameter COUNTER_WIDTH_40 bound to: 8 - type: integer
Parameter reset_count bound to: 16'b0000001111111111
Parameter count_40_term bound to: 8'b01000101
Parameter count_160_term bound to: 8'b01000101
INFO: [Synth 8-638] synthesizing module 'clock_test_ipbus' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81]
Parameter COUNTER_WIDTH_40 bound to: 8 - type: integer
Parameter reset_count bound to: 16'b0000001111111111
Parameter count_40_term bound to: 8'b01000101
Parameter count_160_term bound to: 8'b01000101
INFO: [Synth 8-256] done synthesizing module 'clock_test_ipbus' (261#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81]
WARNING: [Synth 8-3848] Net proc_soft_reset in module/entity backplane_regs does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:53]
WARNING: [Synth 8-3848] Net backplane_ttc_control in module/entity backplane_regs does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:68]
INFO: [Synth 8-256] done synthesizing module 'backplane_regs' (262#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:72]
INFO: [Synth 8-638] synthesizing module 'chan_map_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/chan_map_ila_stub.vhdl:15]
INFO: [Synth 8-638] synthesizing module 'ttc_chan_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:72]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 15 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 4 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (262#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:193]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:194]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:216]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:217]
INFO: [Synth 8-638] synthesizing module 'watermark' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49]
Parameter watermark_width bound to: 16 - type: integer
INFO: [Synth 8-256] done synthesizing module 'watermark' (263#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:254]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:255]
INFO: [Synth 8-638] synthesizing module 'threshold_counter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'threshold_counter' (264#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:289]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:290]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:306]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:307]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:326]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:327]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:375]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:376]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:392]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:393]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:410]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:411]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:431]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:432]
WARNING: [Synth 8-614] signal 'run_event_count_reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:443]
INFO: [Synth 8-638] synthesizing module 'error_counter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52]
Parameter cwidth bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'error_counter' (265#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52]
INFO: [Synth 8-256] done synthesizing module 'ttc_chan_regs' (266#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:72]
Parameter channel_num bound to: 12'b000000000000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
INFO: [Synth 8-638] synthesizing module 'CRC' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
INFO: [Synth 8-256] done synthesizing module 'CRC' (267#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized3' (267#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe' (268#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
INFO: [Synth 8-638] synthesizing module 'axis_input_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/axis_input_fifo_stub.vhdl:26]
INFO: [Synth 8-638] synthesizing module 'aurora_fifo_in_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/aurora_fifo_in_ila_stub.vhdl:25]
INFO: [Synth 8-638] synthesizing module 'aurora_fifo_out_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/aurora_fifo_out_ila_stub.vhdl:22]
INFO: [Synth 8-638] synthesizing module 'data_fifo_vio' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/data_fifo_vio_stub.vhdl:14]
INFO: [Synth 8-638] synthesizing module 'ufc_rx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:68]
INFO: [Synth 8-256] done synthesizing module 'ufc_rx' (269#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:68]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'fex_chan_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:124]
Parameter COUNTER_WIDTH bound to: 5 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 27 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 5 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (269#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:344]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:345]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:373]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:374]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:410]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:411]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:437]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:438]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:498]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:499]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:522]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:523]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:561]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:562]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:589]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:590]
Parameter COUNTER_WIDTH bound to: 5 - type: integer
INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
Parameter COUNTER_WIDTH bound to: 5 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized5' (269#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:671]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:672]
INFO: [Synth 8-638] synthesizing module 'error_counter__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52]
Parameter cwidth bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'error_counter__parameterized0' (269#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52]
WARNING: [Synth 8-614] signal 'master_reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:721]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_init' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56]
Parameter jfex bound to: 0 - type: integer
Parameter COUNTER_WIDTH bound to: 5 - type: integer
Parameter GAP_WIDTH bound to: 20 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'self_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66]
Parameter GAP_WIDTH bound to: 20 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'self_reset' (270#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'channel_init' (271#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56]
Parameter cwidth bound to: 4 - type: integer
INFO: [Synth 8-638] synthesizing module 'edge_error_counter' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53]
Parameter cwidth bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'edge_error_counter' (272#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:840]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:841]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:861]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:862]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:894]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:895]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:926]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:927]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:959]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:960]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:992]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:993]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1025]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1026]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1060]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1061]
WARNING: [Synth 8-614] signal 'pp_clock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1068]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1093]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1094]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1110]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1111]
INFO: [Synth 8-256] done synthesizing module 'fex_chan_regs' (273#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:124]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:926]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'pulse_stretcher'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:493]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ufc_receiver'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:905]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized1' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized1' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 1 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized3' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized3' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized5' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
INFO: [Synth 8-638] synthesizing module 'clock_cross_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/clock_cross_fifo_stub.vhdl:26]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized5' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000100
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000100
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000100
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000100
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized7' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized7' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000101
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000101
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000101
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000101
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized9' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized9' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000110
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized11' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000110
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000110
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized11' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000110
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized11' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized11' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000111
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized13' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000000111
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000000111
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized13' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000000111
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized13' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508]
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized13' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized15' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000001000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized15' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000001000
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized15' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized15' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized17' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000001001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized17' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000001001
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized17' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized17' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized19' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000001010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized19' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000001010
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
WARNING: [Synth 8-614] signal 'aurora_user_clk' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:488]
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized19' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized19' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized21' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
Parameter channel_num bound to: 12'b000000001011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 0 - type: integer
Parameter axi_fifo bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter length_lsb bound to: 20 - type: integer
Parameter length_msb bound to: 31 - type: integer
Parameter COUNTER_WIDTH bound to: 8 - type: integer
Parameter channel_num bound to: 12'b000000001011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized21' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter channel_num bound to: 12'b000000001011
Parameter lmem bound to: 4'b0000
Parameter max_packet_length bound to: 16'b0000001010100000
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:163]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:191]
WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:216]
INFO: [Common 17-14] Message 'Synth 8-614' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
Parameter COUNTER_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized21' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized21' (274#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.registers'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1273]
WARNING: [Synth 8-3848] Net aurora_chan_control_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:577]
WARNING: [Synth 8-3848] Net tob_s_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:580]
WARNING: [Synth 8-3848] Net tob_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:585]
WARNING: [Synth 8-3848] Net tob_m_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:586]
WARNING: [Synth 8-3848] Net tob_m_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:588]
WARNING: [Synth 8-3848] Net tob_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:589]
WARNING: [Synth 8-3848] Net tob_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:590]
WARNING: [Synth 8-3848] Net hdr_crc_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:591]
WARNING: [Synth 8-3848] Net comb_error_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:592]
WARNING: [Synth 8-3848] Net calo_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:595]
WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:596]
WARNING: [Synth 8-3848] Net calo_s_axis_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:598]
WARNING: [Synth 8-3848] Net calo_m_axis_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:599]
WARNING: [Synth 8-3848] Net calo_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:600]
WARNING: [Synth 8-3848] Net calo_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:601]
WARNING: [Synth 8-3848] Net aurora_chan_control_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:617]
WARNING: [Synth 8-3848] Net tob_s_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:620]
WARNING: [Synth 8-3848] Net tob_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:625]
WARNING: [Synth 8-3848] Net tob_m_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:626]
WARNING: [Synth 8-3848] Net tob_m_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:628]
WARNING: [Synth 8-3848] Net tob_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:629]
WARNING: [Synth 8-3848] Net tob_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:630]
WARNING: [Synth 8-3848] Net hdr_crc_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:631]
WARNING: [Synth 8-3848] Net comb_error_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:632]
WARNING: [Synth 8-3848] Net calo_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:635]
WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:636]
WARNING: [Synth 8-3848] Net calo_s_axis_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:638]
WARNING: [Synth 8-3848] Net calo_m_axis_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:639]
WARNING: [Synth 8-3848] Net calo_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:640]
WARNING: [Synth 8-3848] Net calo_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:641]
WARNING: [Synth 8-3848] Net aurora_chan_control_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:658]
WARNING: [Synth 8-3848] Net tob_s_tready_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:661]
WARNING: [Synth 8-3848] Net tob_m_tvalid_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:666]
WARNING: [Synth 8-3848] Net tob_m_tlast_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:667]
WARNING: [Synth 8-3848] Net tob_m_tdata_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:669]
WARNING: [Synth 8-3848] Net tob_header_marker_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:670]
INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'input_fifos' (275#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1062]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4196]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4201]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4206]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4211]
Parameter sim bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'tob_processor' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:354]
Parameter sim bound to: 0 - type: integer
Parameter jfex bound to: 0 - type: integer
Parameter timeout_1_default bound to: 16'b0000010000000000
Parameter timeout_n_default bound to: 16'b0000000000110000
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter header_width bound to: 64 - type: integer
Parameter event_width bound to: 64 - type: integer
INFO: [Synth 8-638] synthesizing module 'channel_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:329]
Parameter bp_width bound to: 64 - type: integer
Parameter n bound to: 5 - type: integer
Parameter m bound to: 32 - type: integer
INFO: [Synth 8-638] synthesizing module 'onehot_dec' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47]
Parameter n bound to: 5 - type: integer
Parameter m bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'onehot_dec' (276#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'channel_mux' (277#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:329]
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter event_width bound to: 64 - type: integer
Parameter header_width bound to: 64 - type: integer
INFO: [Synth 8-638] synthesizing module 'ev_builder' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:171]
Parameter jfex bound to: 0 - type: integer
Parameter bp_width bound to: 64 - type: integer
Parameter event_width bound to: 64 - type: integer
Parameter header_width bound to: 64 - type: integer
Parameter n bound to: 6 - type: integer
INFO: [Synth 8-638] synthesizing module 'vDFF' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64]
Parameter n bound to: 6 - type: integer
INFO: [Synth 8-256] done synthesizing module 'vDFF' (278#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64]
INFO: [Synth 8-638] synthesizing module 'event_builder_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/event_builder_fifo_stub.vhdl:25]
INFO: [Synth 8-638] synthesizing module 'event_fifo_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/event_fifo_ila_stub.vhdl:26]
INFO: [Synth 8-638] synthesizing module 'tob_timeout' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'tob_timeout' (279#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:54]
INFO: [Synth 8-638] synthesizing module 'hdr_in_crc9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50]
INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (280#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'hdr_in_crc9' (281#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50]
INFO: [Synth 8-638] synthesizing module 'event_hdr_crc9' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'event_hdr_crc9' (282#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b11000001101011001111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-638] synthesizing module 'event_trailer_CRC20' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:58]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b11000001101011001111
Parameter G_InitVal bound to: 20'b11111111111111111111
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b10000011010010011111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-638] synthesizing module 'flx_CRC' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b10000011010010011111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-256] done synthesizing module 'flx_CRC' (283#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34]
INFO: [Synth 8-256] done synthesizing module 'event_trailer_CRC20' (284#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:58]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b11000001101011001111
Parameter G_InitVal bound to: 20'b11111111111111111111
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'trailer_map' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:58]
Parameter jfex bound to: 0 - type: integer
Parameter n bound to: 4 - type: integer
Parameter m bound to: 16 - type: integer
INFO: [Synth 8-638] synthesizing module 'onehot_dec__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47]
Parameter n bound to: 4 - type: integer
Parameter m bound to: 16 - type: integer
INFO: [Synth 8-256] done synthesizing module 'onehot_dec__parameterized1' (284#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47]
WARNING: [Synth 8-3936] Found unconnected internal register 'current_chan_del_reg' and it is trimmed from '5' to '4' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:105]
INFO: [Synth 8-256] done synthesizing module 'trailer_map' (285#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:58]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1876]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b11000001101011001111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-638] synthesizing module 'CRC__parameterized3' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b11000001101011001111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized3' (285#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
Parameter jfex bound to: 0 - type: integer
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1975]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1979]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1984]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1989]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1994]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_trailer_crc'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1617]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'state_reg'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:523]
INFO: [Synth 8-256] done synthesizing module 'ev_builder' (286#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:171]
Parameter timeout_1_default bound to: 16'b0000010000000000
Parameter timeout_n_default bound to: 16'b0000000000110000
INFO: [Synth 8-638] synthesizing module 'tob_proc_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:78]
Parameter timeout_1_default bound to: 16'b0000010000000000
Parameter timeout_n_default bound to: 16'b0000000000110000
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 20 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 5 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (286#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:217]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:218]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:253]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:254]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:288]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:289]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:323]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:324]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:342]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:343]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:377]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:378]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:429]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:430]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:495]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:496]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:519]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:520]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:549]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:550]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68]
Parameter N_CTRL bound to: 1 - type: integer
Parameter N_STAT bound to: 1 - type: integer
Parameter SWAP_ORDER bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (286#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:616]
WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:617]
INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39]
Parameter packet_version bound to: 3'b001
Parameter sim bound to: 0 - type: integer
Parameter debug bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized6' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 8 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 4 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized6' (286#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs' (287#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'tob_proc_regs' (288#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:78]
INFO: [Synth 8-638] synthesizing module 'dummy_chan_in' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'dummy_chan_in' (289#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47]
INFO: [Synth 8-638] synthesizing module 'ppmux_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ppmux_ila_stub.vhdl:22]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_mux'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:860]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_in_gen'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:1276]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:1232]
INFO: [Synth 8-256] done synthesizing module 'tob_processor' (290#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:354]
INFO: [Synth 8-638] synthesizing module 'ttc_info' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:93]
INFO: [Synth 8-638] synthesizing module 'ttc_header_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ttc_header_fifo_stub.vhdl:24]
INFO: [Synth 8-638] synthesizing module 'ila_bulk_ttc' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_bulk_ttc_stub.vhdl:26]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:489]
INFO: [Synth 8-638] synthesizing module 'ila_ttc_in' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_ttc_in_stub.vhdl:19]
INFO: [Synth 8-638] synthesizing module 'ila_ttc_out' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_ttc_out_stub.vhdl:19]
INFO: [Synth 8-256] done synthesizing module 'ttc_info' (291#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:93]
Parameter sim bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_processor' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:165]
Parameter sim bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/bulk_ila_stub.vhdl:21]
INFO: [Synth 8-638] synthesizing module 'bulk_data_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/bulk_data_fifo_stub.vhdl:25]
Parameter COUNTER_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_controller' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:76]
Parameter n bound to: 4 - type: integer
INFO: [Synth 8-638] synthesizing module 'vDFF__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64]
Parameter n bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'vDFF__parameterized1' (291#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64]
INFO: [Synth 8-256] done synthesizing module 'bulk_controller' (292#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:76]
Parameter bp_width bound to: 64 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_channel_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:310]
Parameter bp_width bound to: 64 - type: integer
Parameter n bound to: 5 - type: integer
Parameter m bound to: 32 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_onehot' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46]
Parameter n bound to: 5 - type: integer
Parameter m bound to: 32 - type: integer
INFO: [Synth 8-256] done synthesizing module 'bulk_onehot' (293#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'bulk_channel_mux' (294#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:310]
Parameter SIM bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'bulk_proc_regs' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:79]
Parameter SIM bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized7' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter NSLV bound to: 16 - type: integer
Parameter STROBE_GAP bound to: 0 - type: bool
Parameter SEL_WIDTH bound to: 5 - type: integer
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized7' (294#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55]
Parameter sim bound to: 1 - type: integer
Parameter debug bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs__parameterized1' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39]
Parameter packet_version bound to: 3'b001
Parameter sim bound to: 1 - type: integer
Parameter debug bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs__parameterized1' (294#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'bulk_proc_regs' (295#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:79]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'controller'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:737]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:1105]
INFO: [Synth 8-256] done synthesizing module 'bulk_processor' (296#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:165]
Parameter sim bound to: 0 - type: integer
Parameter sim bound to: 0 - type: integer
INFO: [Synth 8-638] synthesizing module 'ro_controller' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:50]
Parameter Nbits bound to: 64 - type: integer
Parameter CRC_Width bound to: 9 - type: integer
Parameter G_Poly bound to: 9'b011111011
Parameter G_InitVal bound to: 9'b111111111
INFO: [Synth 8-638] synthesizing module 'rod_ROctrl_mux_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/rod_ROctrl_mux_ila_stub.vhdl:19]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ro_crc'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:179]
INFO: [Synth 8-256] done synthesizing module 'ro_controller' (297#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:50]
INFO: [Synth 8-256] done synthesizing module 'packet_processor' (298#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:504]
Parameter DEBUG bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'Full_Mode_Tx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:120]
Parameter DEBUG bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'clk_wiz_240' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/clk_wiz_240_stub.vhdl:16]
Parameter debug bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'FM_channel' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:120]
Parameter debug bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'FMchannelTXctrl' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35]
INFO: [Synth 8-638] synthesizing module 'pulse_pdxx_pwxx' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25]
Parameter pd bound to: 0 - type: integer
Parameter pw bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'pulse_pdxx_pwxx' (299#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25]
INFO: [Synth 8-638] synthesizing module 'CRC__parameterized4' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
Parameter Nbits bound to: 32 - type: integer
Parameter CRC_Width bound to: 20 - type: integer
Parameter G_Poly bound to: 20'b10000011010110011111
Parameter G_InitVal bound to: 20'b11111111111111111111
INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized4' (299#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/crc.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'FMchannelTXctrl' (300#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35]
INFO: [Synth 8-638] synthesizing module 'FIFO34to34b' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29]
INFO: [Synth 8-638] synthesizing module 'fifo1KB_34bit' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/fifo1KB_34bit_stub.vhdl:22]
INFO: [Synth 8-256] done synthesizing module 'FIFO34to34b' (301#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29]
INFO: [Synth 8-638] synthesizing module 'vio_fullmode_reset' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/vio_fullmode_reset_stub.vhdl:23]
INFO: [Synth 8-638] synthesizing module 'rst_tmr' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'rst_tmr' (302#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47]
INFO: [Synth 8-638] synthesizing module 'tx_data_mux' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:57]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:62]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:67]
INFO: [Synth 8-256] done synthesizing module 'tx_data_mux' (303#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53]
INFO: [Synth 8-638] synthesizing module 'fm_axi' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51]
INFO: [Synth 8-256] done synthesizing module 'fm_axi' (304#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51]
INFO: [Synth 8-638] synthesizing module 'FM_example_emuram' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22]
INFO: [Synth 8-638] synthesizing module 'DPram_32b' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/DPram_32b_stub.vhdl:21]
INFO: [Synth 8-256] done synthesizing module 'FM_example_emuram' (305#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22]
INFO: [Synth 8-638] synthesizing module 'FM_example_FIFOctrl' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'FM_example_FIFOctrl' (306#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26]
INFO: [Synth 8-638] synthesizing module 'fm_status_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/fm_status_fifo_stub.vhdl:21]
INFO: [Synth 8-638] synthesizing module 'ila_fullmode' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_fullmode_stub.vhdl:14]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_timer'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:700]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ctl0'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:857]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ram0'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:801]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u7'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:563]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u5'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:550]
INFO: [Synth 8-256] done synthesizing module 'FM_channel' (307#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:120]
Parameter debug bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter USE_GREFCLK bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49]
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter USE_GREFCLK bound to: 0 - type: bool
Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000
Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111
Parameter QPLL_CLKOUT_CFG bound to: 4'b1111
Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000
Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0
Parameter QPLL_CP bound to: 10'b0000011111
Parameter QPLL_CP_MONITOR_EN bound to: 1'b0
Parameter QPLL_DMONITOR_SEL bound to: 1'b0
Parameter QPLL_FBDIV bound to: 10'b0010000000
Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0
Parameter QPLL_FBDIV_RATIO bound to: 1'b1
Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110
Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000
Parameter QPLL_LPF bound to: 4'b1111
Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter QPLL_RP_COMP bound to: 1'b0
Parameter QPLL_VTRL_RESET bound to: 2'b00
Parameter RCAL_CFG bound to: 2'b00
Parameter RSVD_ATTR0 bound to: 16'b0000000000000000
Parameter RSVD_ATTR1 bound to: 16'b0000000000000000
Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001
Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:462]
Parameter ACJTAG_DEBUG_MODE bound to: 1'b0
Parameter ACJTAG_MODE bound to: 1'b0
Parameter ACJTAG_RESET bound to: 1'b0
Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000
Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string
Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111
Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer
Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string
Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011
Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string
Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100
Parameter A_RXOSCALRESET bound to: 1'b0
Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string
Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000
Parameter CFOK_CFG2 bound to: 8'b00100000
Parameter CFOK_CFG3 bound to: 8'b00100000
Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string
Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer
Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111
Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111
Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string
Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer
Parameter CLK_CORRECT_USE bound to: FALSE - type: string
Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string
Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer
Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer
Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string
Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer
Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000
Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111
Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000
Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111
Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string
Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer
Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100
Parameter CPLL_FBDIV bound to: 2 - type: integer
Parameter CPLL_FBDIV_45 bound to: 5 - type: integer
Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110
Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000
Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string
Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string
Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string
Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000
Parameter ES_CLK_PHASE_SEL bound to: 1'b0
Parameter ES_CONTROL bound to: 6'b000000
Parameter ES_ERRDET_EN bound to: FALSE - type: string
Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string
Parameter ES_HORZ_OFFSET bound to: 12'b000000000000
Parameter ES_PMA_CFG bound to: 10'b0000000000
Parameter ES_PRESCALE bound to: 5'b00000
Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_VERT_OFFSET bound to: 9'b000000000
Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111
Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111
Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string
Parameter GEARBOX_MODE bound to: 3'b000
Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0
Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0
Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0
Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0
Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0
Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0
Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0
Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0
Parameter LOOPBACK_CFG bound to: 1'b0
Parameter OUTREFCLK_SEL_INV bound to: 2'b11
Parameter PCS_PCIE_EN bound to: FALSE - type: string
Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000
Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100
Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100
Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100
Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000
Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010
Parameter PMA_RSV3 bound to: 2'b00
Parameter PMA_RSV4 bound to: 16'b0000000000001000
Parameter PMA_RSV5 bound to: 4'b0000
Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0
Parameter RXBUFRESET_TIME bound to: 5'b00001
Parameter RXBUF_ADDR_MODE bound to: FAST - type: string
Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000
Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000
Parameter RXBUF_EN bound to: TRUE - type: string
Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string
Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string
Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string
Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer
Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string
Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer
Parameter RXCDRFREQRESET_TIME bound to: 5'b00001
Parameter RXCDRPHRESET_TIME bound to: 5'b00001
Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000
Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0
Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0
Parameter RXCDR_LOCK_CFG bound to: 6'b010101
Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0
Parameter RXDFELPMRESET_TIME bound to: 7'b0001111
Parameter RXDLY_CFG bound to: 16'b0000000000011111
Parameter RXDLY_LCFG bound to: 12'b000000110000
Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000
Parameter RXGEARBOX_EN bound to: FALSE - type: string
Parameter RXISCANRESET_TIME bound to: 5'b00001
Parameter RXLPM_HF_CFG bound to: 14'b00001000000000
Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000
Parameter RXOOB_CFG bound to: 7'b0000110
Parameter RXOOB_CLK_CFG bound to: PMA - type: string
Parameter RXOSCALRESET_TIME bound to: 5'b00011
Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000
Parameter RXOUT_DIV bound to: 1 - type: integer
Parameter RXPCSRESET_TIME bound to: 5'b00001
Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000
Parameter RXPH_CFG bound to: 24'b110000000000000000000010
Parameter RXPH_MONITOR_SEL bound to: 5'b00000
Parameter RXPI_CFG0 bound to: 2'b00
Parameter RXPI_CFG1 bound to: 2'b00
Parameter RXPI_CFG2 bound to: 2'b00
Parameter RXPI_CFG3 bound to: 2'b11
Parameter RXPI_CFG4 bound to: 1'b1
Parameter RXPI_CFG5 bound to: 1'b1
Parameter RXPI_CFG6 bound to: 3'b001
Parameter RXPMARESET_TIME bound to: 5'b00011
Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0
Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer
Parameter RXSLIDE_MODE bound to: OFF - type: string
Parameter RXSYNC_MULTILANE bound to: 1'b0
Parameter RXSYNC_OVRD bound to: 1'b0
Parameter RXSYNC_SKIP_DA bound to: 1'b0
Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000
Parameter RX_BUFFER_CFG bound to: 6'b000000
Parameter RX_CLK25_DIV bound to: 10 - type: integer
Parameter RX_CLKMUX_PD bound to: 1'b1
Parameter RX_CM_SEL bound to: 2'b01
Parameter RX_CM_TRIM bound to: 4'b0000
Parameter RX_DATA_WIDTH bound to: 20 - type: integer
Parameter RX_DDI_SEL bound to: 6'b000000
Parameter RX_DEBUG_CFG bound to: 14'b00000000000000
Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string
Parameter RX_DFELPM_CFG0 bound to: 4'b0110
Parameter RX_DFELPM_CFG1 bound to: 1'b0
Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1
Parameter RX_DFE_AGC_CFG0 bound to: 2'b00
Parameter RX_DFE_AGC_CFG1 bound to: 3'b010
Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000
Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1
Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000
Parameter RX_DFE_H2_CFG bound to: 12'b000000000000
Parameter RX_DFE_H3_CFG bound to: 12'b000001000000
Parameter RX_DFE_H4_CFG bound to: 11'b00011100000
Parameter RX_DFE_H5_CFG bound to: 11'b00011100000
Parameter RX_DFE_H6_CFG bound to: 12'b000000100000
Parameter RX_DFE_H7_CFG bound to: 12'b000000100000
Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000
Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01
Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010
Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010
Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1
Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01
Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010
Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010
Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1
Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000
Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0
Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111
Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000
Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011
Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string
Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer
Parameter RX_OS_CFG bound to: 13'b0000010000000
Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer
Parameter RX_XCLK_SEL bound to: RXREC - type: string
Parameter SAS_MAX_COM bound to: 64 - type: integer
Parameter SAS_MIN_COM bound to: 36 - type: integer
Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101
Parameter SATA_BURST_VAL bound to: 3'b100
Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string
Parameter SATA_EIDLE_VAL bound to: 3'b100
Parameter SATA_MAX_BURST bound to: 8 - type: integer
Parameter SATA_MAX_INIT bound to: 21 - type: integer
Parameter SATA_MAX_WAKE bound to: 7 - type: integer
Parameter SATA_MIN_BURST bound to: 4 - type: integer
Parameter SATA_MIN_INIT bound to: 12 - type: integer
Parameter SATA_MIN_WAKE bound to: 4 - type: integer
Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string
Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111
Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string
Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string
Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
Parameter TERM_RCAL_CFG bound to: 15'b100001000010000
Parameter TERM_RCAL_OVRD bound to: 3'b000
Parameter TRANS_TIME_RATE bound to: 8'b00001110
Parameter TST_RSV bound to: 32'b00000000000000000000000000000000
Parameter TXBUF_EN bound to: TRUE - type: string
Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
Parameter TXDLY_CFG bound to: 16'b0000000000011111
Parameter TXDLY_LCFG bound to: 12'b000000110000
Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000
Parameter TXGEARBOX_EN bound to: FALSE - type: string
Parameter TXOOB_CFG bound to: 1'b0
Parameter TXOUT_DIV bound to: 1 - type: integer
Parameter TXPCSRESET_TIME bound to: 5'b00001
Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000
Parameter TXPH_CFG bound to: 16'b0000011110000000
Parameter TXPH_MONITOR_SEL bound to: 5'b00000
Parameter TXPI_CFG0 bound to: 2'b00
Parameter TXPI_CFG1 bound to: 2'b00
Parameter TXPI_CFG2 bound to: 2'b00
Parameter TXPI_CFG3 bound to: 1'b0
Parameter TXPI_CFG4 bound to: 1'b0
Parameter TXPI_CFG5 bound to: 3'b100
Parameter TXPI_GREY_SEL bound to: 1'b0
Parameter TXPI_INVSTROBE_SEL bound to: 1'b0
Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string
Parameter TXPI_PPM_CFG bound to: 8'b00000000
Parameter TXPI_SYNFREQ_PPM bound to: 3'b001
Parameter TXPMARESET_TIME bound to: 5'b00001
Parameter TXSYNC_MULTILANE bound to: 1'b0
Parameter TXSYNC_OVRD bound to: 1'b0
Parameter TXSYNC_SKIP_DA bound to: 1'b0
Parameter TX_CLK25_DIV bound to: 10 - type: integer
Parameter TX_CLKMUX_PD bound to: 1'b1
Parameter TX_DATA_WIDTH bound to: 40 - type: integer
Parameter TX_DEEMPH0 bound to: 6'b000000
Parameter TX_DEEMPH1 bound to: 6'b000000
Parameter TX_DRIVE_MODE bound to: DIRECT - type: string
Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110
Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100
Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer
Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string
Parameter TX_MAINCURSOR_SEL bound to: 1'b0
Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110
Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001
Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101
Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010
Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000
Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110
Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100
Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010
Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000
Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000
Parameter TX_QPI_STATUS_EN bound to: 1'b0
Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010
Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100
Parameter TX_RXDETECT_REF bound to: 3'b100
Parameter TX_XCLK_SEL bound to: TXOUT - type: string
Parameter UCODEER_CLR bound to: 1'b0
Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
Parameter EQ_MODE bound to: LPM - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer
Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer
Parameter TX_QPLL_USED bound to: 1 - type: bool
Parameter RX_QPLL_USED bound to: 0 - type: bool
Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623]
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
Parameter EQ_MODE bound to: LPM - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer
Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer
Parameter TX_QPLL_USED bound to: 1 - type: bool
Parameter RX_QPLL_USED bound to: 0 - type: bool
Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INITIALISE bound to: 6'b000000
INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_sync_block' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386]
Parameter INITIALISE bound to: 6'b000000
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
Parameter INIT bound to: 1'b0
INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_sync_block' (308#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386]
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' (309#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623]
Parameter ACJTAG_DEBUG_MODE bound to: 1'b0
Parameter ACJTAG_MODE bound to: 1'b0
Parameter ACJTAG_RESET bound to: 1'b0
Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000
Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string
Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111
Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer
Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string
Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011
Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string
Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100
Parameter A_RXOSCALRESET bound to: 1'b0
Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string
Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000
Parameter CFOK_CFG2 bound to: 8'b00100000
Parameter CFOK_CFG3 bound to: 8'b00100000
Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string
Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer
Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111
Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000
Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111
Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string
Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer
Parameter CLK_CORRECT_USE bound to: FALSE - type: string
Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string
Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer
Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer
Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string
Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer
Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000
Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111
Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000
Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000
Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111
Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string
Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer
Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100
Parameter CPLL_FBDIV bound to: 2 - type: integer
Parameter CPLL_FBDIV_45 bound to: 5 - type: integer
Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110
Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000
Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer
Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string
Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string
Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string
Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000
Parameter ES_CLK_PHASE_SEL bound to: 1'b0
Parameter ES_CONTROL bound to: 6'b000000
Parameter ES_ERRDET_EN bound to: FALSE - type: string
Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string
Parameter ES_HORZ_OFFSET bound to: 12'b000000000000
Parameter ES_PMA_CFG bound to: 10'b0000000000
Parameter ES_PRESCALE bound to: 5'b00000
Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter ES_VERT_OFFSET bound to: 9'b000000000
Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111
Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111
Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string
Parameter GEARBOX_MODE bound to: 3'b000
Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0
Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0
Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0
Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0
Parameter IS_DRPCLK_INVERTED bound to: 1'b0
Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0
Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0
Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0
Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0
Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0
Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0
Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0
Parameter LOOPBACK_CFG bound to: 1'b0
Parameter OUTREFCLK_SEL_INV bound to: 2'b11
Parameter PCS_PCIE_EN bound to: FALSE - type: string
Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000
Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100
Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100
Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100
Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000
Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010
Parameter PMA_RSV3 bound to: 2'b00
Parameter PMA_RSV4 bound to: 16'b0000000000001000
Parameter PMA_RSV5 bound to: 4'b0000
Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0
Parameter RXBUFRESET_TIME bound to: 5'b00001
Parameter RXBUF_ADDR_MODE bound to: FAST - type: string
Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000
Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000
Parameter RXBUF_EN bound to: TRUE - type: string
Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string
Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string
Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string
Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer
Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string
Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer
Parameter RXCDRFREQRESET_TIME bound to: 5'b00001
Parameter RXCDRPHRESET_TIME bound to: 5'b00001
Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000
Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0
Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0
Parameter RXCDR_LOCK_CFG bound to: 6'b010101
Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0
Parameter RXDFELPMRESET_TIME bound to: 7'b0001111
Parameter RXDLY_CFG bound to: 16'b0000000000011111
Parameter RXDLY_LCFG bound to: 12'b000000110000
Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000
Parameter RXGEARBOX_EN bound to: FALSE - type: string
Parameter RXISCANRESET_TIME bound to: 5'b00001
Parameter RXLPM_HF_CFG bound to: 14'b00001000000000
Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000
Parameter RXOOB_CFG bound to: 7'b0000110
Parameter RXOOB_CLK_CFG bound to: PMA - type: string
Parameter RXOSCALRESET_TIME bound to: 5'b00011
Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000
Parameter RXOUT_DIV bound to: 1 - type: integer
Parameter RXPCSRESET_TIME bound to: 5'b00001
Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000
Parameter RXPH_CFG bound to: 24'b110000000000000000000010
Parameter RXPH_MONITOR_SEL bound to: 5'b00000
Parameter RXPI_CFG0 bound to: 2'b00
Parameter RXPI_CFG1 bound to: 2'b00
Parameter RXPI_CFG2 bound to: 2'b00
Parameter RXPI_CFG3 bound to: 2'b11
Parameter RXPI_CFG4 bound to: 1'b1
Parameter RXPI_CFG5 bound to: 1'b1
Parameter RXPI_CFG6 bound to: 3'b001
Parameter RXPMARESET_TIME bound to: 5'b00011
Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0
Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer
Parameter RXSLIDE_MODE bound to: OFF - type: string
Parameter RXSYNC_MULTILANE bound to: 1'b0
Parameter RXSYNC_OVRD bound to: 1'b0
Parameter RXSYNC_SKIP_DA bound to: 1'b0
Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000
Parameter RX_BUFFER_CFG bound to: 6'b000000
Parameter RX_CLK25_DIV bound to: 10 - type: integer
Parameter RX_CLKMUX_PD bound to: 1'b1
Parameter RX_CM_SEL bound to: 2'b01
Parameter RX_CM_TRIM bound to: 4'b0000
Parameter RX_DATA_WIDTH bound to: 20 - type: integer
Parameter RX_DDI_SEL bound to: 6'b000000
Parameter RX_DEBUG_CFG bound to: 14'b00000000000000
Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string
Parameter RX_DFELPM_CFG0 bound to: 4'b0110
Parameter RX_DFELPM_CFG1 bound to: 1'b0
Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1
Parameter RX_DFE_AGC_CFG0 bound to: 2'b00
Parameter RX_DFE_AGC_CFG1 bound to: 3'b010
Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000
Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1
Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000
Parameter RX_DFE_H2_CFG bound to: 12'b000000000000
Parameter RX_DFE_H3_CFG bound to: 12'b000001000000
Parameter RX_DFE_H4_CFG bound to: 11'b00011100000
Parameter RX_DFE_H5_CFG bound to: 11'b00011100000
Parameter RX_DFE_H6_CFG bound to: 12'b000000100000
Parameter RX_DFE_H7_CFG bound to: 12'b000000100000
Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000
Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01
Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010
Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010
Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1
Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01
Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010
Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010
Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1
Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000
Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0
Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111
Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000
Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011
Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string
Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer
Parameter RX_OS_CFG bound to: 13'b0000010000000
Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer
Parameter RX_XCLK_SEL bound to: RXREC - type: string
Parameter SAS_MAX_COM bound to: 64 - type: integer
Parameter SAS_MIN_COM bound to: 36 - type: integer
Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101
Parameter SATA_BURST_VAL bound to: 3'b100
Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string
Parameter SATA_EIDLE_VAL bound to: 3'b100
Parameter SATA_MAX_BURST bound to: 8 - type: integer
Parameter SATA_MAX_INIT bound to: 21 - type: integer
Parameter SATA_MAX_WAKE bound to: 7 - type: integer
Parameter SATA_MIN_BURST bound to: 4 - type: integer
Parameter SATA_MIN_INIT bound to: 12 - type: integer
Parameter SATA_MIN_WAKE bound to: 4 - type: integer
Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string
Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111
Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string
Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string
Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string
Parameter SIM_VERSION bound to: 2.0 - type: string
Parameter TERM_RCAL_CFG bound to: 15'b100001000010000
Parameter TERM_RCAL_OVRD bound to: 3'b000
Parameter TRANS_TIME_RATE bound to: 8'b00001110
Parameter TST_RSV bound to: 32'b00000000000000000000000000000000
Parameter TXBUF_EN bound to: TRUE - type: string
Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string
Parameter TXDLY_CFG bound to: 16'b0000000000011111
Parameter TXDLY_LCFG bound to: 12'b000000110000
Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000
Parameter TXGEARBOX_EN bound to: FALSE - type: string
Parameter TXOOB_CFG bound to: 1'b0
Parameter TXOUT_DIV bound to: 1 - type: integer
Parameter TXPCSRESET_TIME bound to: 5'b00001
Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000
Parameter TXPH_CFG bound to: 16'b0000011110000000
Parameter TXPH_MONITOR_SEL bound to: 5'b00000
Parameter TXPI_CFG0 bound to: 2'b00
Parameter TXPI_CFG1 bound to: 2'b00
Parameter TXPI_CFG2 bound to: 2'b00
Parameter TXPI_CFG3 bound to: 1'b0
Parameter TXPI_CFG4 bound to: 1'b0
Parameter TXPI_CFG5 bound to: 3'b100
Parameter TXPI_GREY_SEL bound to: 1'b0
Parameter TXPI_INVSTROBE_SEL bound to: 1'b0
Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string
Parameter TXPI_PPM_CFG bound to: 8'b00000000
Parameter TXPI_SYNFREQ_PPM bound to: 3'b001
Parameter TXPMARESET_TIME bound to: 5'b00001
Parameter TXSYNC_MULTILANE bound to: 1'b0
Parameter TXSYNC_OVRD bound to: 1'b0
Parameter TXSYNC_SKIP_DA bound to: 1'b0
Parameter TX_CLK25_DIV bound to: 10 - type: integer
Parameter TX_CLKMUX_PD bound to: 1'b1
Parameter TX_DATA_WIDTH bound to: 40 - type: integer
Parameter TX_DEEMPH0 bound to: 6'b000000
Parameter TX_DEEMPH1 bound to: 6'b000000
Parameter TX_DRIVE_MODE bound to: DIRECT - type: string
Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110
Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100
Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer
Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string
Parameter TX_MAINCURSOR_SEL bound to: 1'b0
Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110
Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001
Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101
Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010
Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000
Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110
Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100
Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010
Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000
Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000
Parameter TX_QPI_STATUS_EN bound to: 1'b0
Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010
Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100
Parameter TX_RXDETECT_REF bound to: 3'b100
Parameter TX_XCLK_SEL bound to: TXOUT - type: string
Parameter UCODEER_CLR bound to: 1'b0
Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
Parameter EQ_MODE bound to: LPM - type: string
Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer
Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer
Parameter TX_QPLL_USED bound to: 1 - type: bool
Parameter RX_QPLL_USED bound to: 0 - type: bool
Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer
Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer
Parameter TX_QPLL_USED bound to: 1 - type: bool
Parameter RX_QPLL_USED bound to: 0 - type: bool
Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51]
Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer
Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer
Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer
Parameter TX_QPLL_USED bound to: 1 - type: bool
Parameter RX_QPLL_USED bound to: 0 - type: bool
Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
Parameter INITIALISE bound to: 6'b000000
INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' (310#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51]
INFO: [Synth 8-638] synthesizing module 'ila_mgtfsm' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_mgtfsm_stub.vhdl:20]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'txresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1902]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[1].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1819]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[0].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1819]
INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver' (311#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'Full_Mode_Tx' (312#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:120]
Parameter DEBUG bound to: 0 - type: integer
Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool
Parameter NUM_LINKS bound to: 2 - type: integer
Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'packet_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:60]
INFO: [Synth 8-638] synthesizing module 'axis_dwidth_64_32' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/axis_dwidth_64_32_stub.vhdl:21]
INFO: [Synth 8-638] synthesizing module 'axis_data_fifo_0' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/axis_data_fifo_0_stub.vhdl:25]
INFO: [Synth 8-638] synthesizing module 'ila_fifo' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/ila_fifo_stub.vhdl:25]
INFO: [Synth 8-256] done synthesizing module 'packet_fifo' (313#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:60]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DIFF_TERM bound to: 0 - type: bool
Parameter DQS_BIAS bound to: FALSE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: 1 - type: bool
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter COUNTER_WIDTH bound to: 5 - type: integer
INFO: [Synth 8-638] synthesizing module 'reset_count' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48]
Parameter COUNTER_WIDTH bound to: 5 - type: integer
INFO: [Synth 8-256] done synthesizing module 'reset_count' (315#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
Parameter CLKCM_CFG bound to: 1 - type: bool
Parameter CLKRCV_TRST bound to: 1 - type: bool
Parameter CLKSWING_CFG bound to: 2'b11
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-638] synthesizing module 'backplane_control_ila' [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-12698-hog-efex3.cern.ch/realtime/backplane_control_ila_stub.vhdl:13]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'backplane'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2059]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_interface_2'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2861]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_interface_1'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2812]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_builder'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2491]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_top'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1807]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'phy_reset'. This will prevent further optimization [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1826]
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg
INFO: [Synth 8-256] done synthesizing module 'top_rod_efex' (316#1) [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:328]
WARNING: [Synth 8-3331] design FullModeTransceiver_TX_STARTUP_FSM has unconnected port CPLLREFCLKLOST
WARNING: [Synth 8-3331] design FullModeTransceiver_RX_STARTUP_FSM has unconnected port QPLLREFCLKLOST
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][19]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][18]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][17]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][16]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][15]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][14]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][13]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][12]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][11]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][10]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][9]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][8]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][7]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][6]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][5]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][4]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][3]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][2]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][1]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][0]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][19]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][18]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][17]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][16]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][15]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][14]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][13]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][12]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][11]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][10]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][9]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][8]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][7]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][6]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][5]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][4]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][3]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][2]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][1]
WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][0]
WARNING: [Synth 8-3331] design FM_channel has unconnected port app_clk_in
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[31]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[30]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[29]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[28]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[27]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[26]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[25]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[24]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[15]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[14]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[13]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[12]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[11]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[10]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[9]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[8]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[7]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[6]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[5]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[4]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[3]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[2]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[31]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[30]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[29]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[28]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[27]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[26]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[25]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[24]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[15]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[14]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[13]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[12]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[11]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[10]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[9]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[8]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[7]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[6]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[5]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[4]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[3]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[2]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[31]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[30]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[29]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[28]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[27]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[26]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[25]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[24]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[23]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[22]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[21]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[20]
WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[19]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:02:01 ; elapsed = 00:03:17 . Memory (MB): peak = 3008.434 ; gain = 551.711 ; free physical = 6514 ; free virtual = 19609
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:08 ; elapsed = 00:03:25 . Memory (MB): peak = 3008.434 ; gain = 551.711 ; free physical = 6400 ; free virtual = 19495
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:08 ; elapsed = 00:03:25 . Memory (MB): peak = 3008.434 ; gain = 551.711 ; free physical = 6400 ; free virtual = 19495
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3008.434 ; gain = 0.000 ; free physical = 6163 ; free virtual = 19257
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
INFO: [Netlist 29-17] Analyzing 1510 Unisim elements for replacement
WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/backplane_control_ila/backplane_control_ila_in_context.xdc] for cell 'bkpln_control_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/backplane_control_ila/backplane_control_ila_in_context.xdc] for cell 'bkpln_control_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_2/u0/ila_resetfsm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_2/u0/ila_resetfsm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_0/ila_fm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_0/ila_fm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_fm'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_fm'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_2/clk_blk'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_2/clk_blk'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila/ppmux_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila/ppmux_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila/event_fifo_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila/event_fifo_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.channel_fifo_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.channel_fifo_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.calo_fifo_out_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.calo_fifo_out_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_in_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_in_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/chan_map_ila/chan_map_ila_in_context.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/chan_map_ila/chan_map_ila_in_context.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio/pp_ctrl_vio_in_context.xdc] for cell 'vio_pp_ctrl'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio/pp_ctrl_vio_in_context.xdc] for cell 'vio_pp_ctrl'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/data_fifo_vio_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/data_fifo_vio_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test/vio_RO_CTL_test_in_context.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test/vio_RO_CTL_test_in_context.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0/data_fifo_vio_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0/data_fifo_vio_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot4'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot4'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot5'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot5'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_0/ram0/RAM_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_0/ram0/RAM_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_1/ram0/RAM_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_1/ram0/RAM_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/axi_type_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/axi_type_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/axi_type_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/axi_type_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/axi_type_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/axi_type_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/axi_type_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/axi_type_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/axi_type_fifo.clk_cross_tob_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/axi_type_fifo.clk_cross_tob_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/axi_type_fifo.calo_fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/axis_input_fifo/axis_input_fifo/axis_input_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/axi_type_fifo.calo_fifo'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_5/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_6/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_7/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_8/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_9/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/GEN_BUS2ICAP_RESET/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/FIFO_RST_CDC_PROCESS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2PLB_SYNCH1/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2PLB_SYNCH2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
WARNING: [Vivado 12-508] No pins matched 'fm_interface_1/clk_blk/inst/mmcm_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:62]
WARNING: [Vivado 12-508] No pins matched 'fm_interface_2/clk_blk/inst/mmcm_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:72]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_rod_efex_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3274.988 ; gain = 0.000 ; free physical = 5451 ; free virtual = 18552
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 1267 instances were transformed.
BUFGCE => BUFGCTRL: 4 instances
FD => FDRE: 336 instances
FDP => FDPE: 8 instances
FDR => FDRE: 762 instances
FDRSE => FDRSE (FDRE, LUT4, VCC): 44 instances
IBUFG => IBUF: 1 instance
IOBUF => IOBUF (IBUF, OBUFT): 24 instances
MULT_AND => LUT2: 62 instances
MUXCY_L => MUXCY: 24 instances
SRL16 => SRL16E: 2 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3274.992 ; gain = 0.004 ; free physical = 5447 ; free virtual = 18549
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_slot4' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_slot5' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'bkpln_control_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'vio_pp_ctrl' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/combined_ttc/ila_rx2_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/readout_ctrl/ila_tx0_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/readout_ctrl/vio_RO_ctrl_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_0/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_0/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_1/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_1/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_2/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_2/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/gen_reg.channel_map_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/axi_type_fifo.calo_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/axi_type_fifo.clk_cross_tob_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/axi_type_fifo.calo_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/axi_type_fifo.clk_cross_tob_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/axi_type_fifo.calo_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/axi_type_fifo.clk_cross_tob_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/readout_controller/readout_ctrl_ila2' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/input_mux_ila' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/debug_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/event_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/bulk_ttc_fifo' at clock pin 'rd_clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_bulk_ttc_fifo' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_ttc_fifo_in' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_ttc_fifo_out' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ttc_fifo' at clock pin 'rd_clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'fm_interface_1/clk_blk' at clock pin 'clk_in1' is different from the actual clock period '24.970', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/u0/ila_resetfsm' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'fm_interface_2/clk_blk' at clock pin 'clk_in1' is different from the actual clock period '24.970', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '6.250', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results.
INFO: [Common 17-14] Message 'Timing 38-316' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:03:12 ; elapsed = 00:04:38 . Memory (MB): peak = 3274.992 ; gain = 818.270 ; free physical = 5808 ; free virtual = 18925
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INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 1 processes.
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/s00_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m01_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m02_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m03_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m04_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m05_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/m06_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for top_vio. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ILA_axi_slot4. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ILA_axi_slot5. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/ttc_input/ila_bulk_ttc_fifo. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for proc_clock_gen. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for fm_interface_1/chan_0/ram0/RAM_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for fm_interface_1/chan_1/ram0/RAM_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for fm_interface_2/chan_0/ram0/RAM_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for fm_interface_2/chan_1/ram0/RAM_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch0/\axi_type_fifo.calo_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch1/\axi_type_fifo.calo_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch2/\axi_type_fifo.calo_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch0/\axi_type_fifo.clk_cross_tob_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch1/\axi_type_fifo.clk_cross_tob_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for event_builder/fifo_layer/ch2/\axi_type_fifo.clk_cross_tob_fifo . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II . (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:03:14 ; elapsed = 00:04:40 . Memory (MB): peak = 3278.910 ; gain = 822.188 ; free physical = 5761 ; free virtual = 18878
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'idelay_reset_cnt_reg' in module 'ethernet_mac_rgmii_support_resets'
INFO: [Synth 8-5544] ROM "idelayctrl_reset" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "idelay_reset_cnt" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'axi_state_reg' in module 'ethernet_mac_rgmii_axi_lite_sm'
INFO: [Synth 8-802] inferred FSM for state register 'mdio_access_sm_reg' in module 'ethernet_mac_rgmii_axi_lite_sm'
INFO: [Synth 8-5587] ROM size for "start_mdio" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "drive_mdio" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "int_data_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:128]
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm'
INFO: [Synth 8-802] inferred FSM for state register 'emc_addr_ps_reg' in module 'axi_emc_native_interface'
INFO: [Synth 8-802] inferred FSM for state register 'crnt_state_reg' in module 'mem_state_machine'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-802] inferred FSM for state register 'icap_nstate_cs_reg' in module 'icap_statemachine_shared'
INFO: [Synth 8-5544] ROM "abort_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "count_enable_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "icap_we_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized1'
INFO: [Synth 8-802] inferred FSM for state register 'scl_state_reg' in module 'iic_control'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'iic_control'
INFO: [Synth 8-5544] ROM "scl_cout" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm'
INFO: [Synth 8-802] inferred FSM for state register 'gen_axi.write_cs_reg' in module 'axi_crossbar_v2_1_21_decerr_slave'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized2'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized2'
INFO: [Synth 8-802] inferred FSM for state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' in module 'qspi_mode_0_module'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_10_cmd_decode'
INFO: [Synth 8-802] inferred FSM for state register 'wr_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine'
INFO: [Synth 8-802] inferred FSM for state register 'rd_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
READ_TX_FIFO | 0001 | 0001
AXI_WR_ADDR | 0010 | 0010
AXI_WR_DATA | 0100 | 0100
AXI_WR_RESPONSE | 1000 | 1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_write_axi'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_10_read_axi'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment'
INFO: [Synth 8-5546] ROM "ctrl_code" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'FullModeTransceiver_RX_STARTUP_FSM'
INFO: [Synth 8-5544] ROM "gtrxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "mmcm_reset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "CPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "RXDFEAGCHOLD" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'FullModeTransceiver_TX_STARTUP_FSM'
INFO: [Synth 8-5544] ROM "TXUSERRDY" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gttxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "MMCM_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "tx_fsm_reset_done_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "QPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE7 | 000000000000001 | 0000
iSTATE6 | 000000000000010 | 0001
iSTATE2 | 000000000000100 | 0010
iSTATE | 000000000001000 | 0011
iSTATE0 | 000000000010000 | 0100
iSTATE13 | 000000000100000 | 0101
iSTATE11 | 000000001000000 | 0110
iSTATE9 | 000000010000000 | 0111
iSTATE10 | 000000100000000 | 1000
iSTATE8 | 000001000000000 | 1001
iSTATE5 | 000010000000000 | 1010
iSTATE3 | 000100000000000 | 1011
iSTATE4 | 001000000000000 | 1100
iSTATE1 | 010000000000000 | 1101
iSTATE12 | 100000000000000 | 1110
*
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'idelay_reset_cnt_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_support_resets'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 0010 | 00
set_data | 1000 | 01
init | 0100 | 10
poll | 0001 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'mdio_access_sm_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
startup | 000000000000000000000001 | 00000
change_speed | 000000000000000000000010 | 00001
mdio_rd | 000000000000000000000100 | 00010
mdio_poll_check | 000000000000000000001000 | 00011
mdio_1g | 000000000000000000010000 | 00100
mdio_10_100 | 000000000000000000100000 | 00101
mdio_rgmii_rd | 000000000000000001000000 | 00110
mdio_rgmii_rd_poll | 000000000000000010000000 | 00111
mdio_rgmii | 000000000000000100000000 | 01000
mdio_delay_rd | 000000000000001000000000 | 01001
mdio_delay_rd_poll | 000000000000010000000000 | 01010
mdio_delay | 000000000000100000000000 | 01011
mdio_restart | 000000000001000000000000 | 01100
mdio_loopback | 000000000010000000000000 | 01101
mdio_stats | 000000000100000000000000 | 01110
mdio_stats_poll_check | 000000001000000000000000 | 01111
reset_mac_rx | 000000010000000000000000 | 10000
reset_mac_tx | 000000100000000000000000 | 10001
cnfg_mdio | 000001000000000000000000 | 10010
cnfg_flow | 000010000000000000000000 | 10011
cnfg_lo_addr | 000100000000000000000000 | 10101
cnfg_hi_addr | 001000000000000000000000 | 10110
cnfg_filter | 010000000000000000000000 | 10100
check_speed | 100000000000000000000000 | 10111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'axi_state_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
st_idle | 0000010 | 000
st_first | 1000000 | 001
st_hdr | 0100000 | 010
st_prebody | 0010000 | 011
st_body | 0001000 | 100
st_done | 0000100 | 101
st_gap | 0000001 | 110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
st_idle | 100000 | 000
st_hdr | 001000 | 001
st_addr | 010000 | 010
st_bus_cycle | 000010 | 011
st_rmw_1 | 000100 | 100
st_rmw_2 | 000001 | 101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 0000001 | 000
rd_last | 0000010 | 010
rd | 0000100 | 001
wr | 0001000 | 011
wr_wait | 0010000 | 100
wr_last | 0100000 | 110
resp | 1000000 | 111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'emc_addr_ps_reg' using encoding 'one-hot' in module 'axi_emc_native_interface'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 00000000000000001 | 00000
address_set | 00000000000000010 | 00010
deassert_cen | 00000000000000100 | 00011
write | 00000000000001000 | 00001
dassert_wen | 00000000000010000 | 00110
write_wait | 00000000000100000 | 01000
wait_temp | 00000000001000000 | 01001
assert_cen | 00000000010000000 | 01011
wait_write_ack | 00000000100000000 | 00111
wr_rec_period | 00000001000000000 | 01010
address_rset | 00000010000000000 | 00100
deassert_rcen | 00000100000000000 | 00101
linear_flash_sync_rd | 00001000000000000 | 01101
read | 00010000000000000 | 01100
page_read | 00100000000000000 | 01110
deassert_oen | 01000000000000000 | 01111
wait_rddata_ack | 10000000000000000 | 10000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'crnt_state_reg' using encoding 'one-hot' in module 'mem_state_machine'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized0'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 0001 | 00
RRST_IN | 0010 | 10
RRST_OUT | 0100 | 11
RRST_EXIT | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 0001 | 00
RRST_IN | 0010 | 10
RRST_OUT | 0100 | 11
RRST_EXIT | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
icap_idle | 00000000000001 | 0000
icap_abort0 | 00000000000010 | 0111
icap_write1 | 00000000000100 | 0001
icap_write3 | 00000000001000 | 0011
icap_write4 | 00000000010000 | 0100
icap_write5 | 00000000100000 | 0101
icap_write2 | 00000001000000 | 0010
icap_read1 | 00000010000000 | 0110
icap_abort1 | 00000100000000 | 1001
icap_abort2 | 00001000000000 | 1010
icap_abort3 | 00010000000000 | 1011
icap_abort4 | 00100000000000 | 1100
icap_abort_hang | 01000000000000 | 1000
done | 10000000000000 | 1101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'icap_nstate_cs_reg' using encoding 'one-hot' in module 'icap_statemachine_shared'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 0000001 | 000
header | 0100000 | 001
ack_header | 1000000 | 010
rcv_data | 0010000 | 011
ack_data | 0001000 | 100
xmit_data | 0000100 | 101
wait_ack | 0000010 | 110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'iic_control'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
scl_idle | 0000000001 | 0000
start_wait | 0000000010 | 0001
start | 0000000100 | 0010
start_edge | 0000001000 | 0011
scl_low_edge | 0000010000 | 0100
scl_low | 0000100000 | 0101
scl_high_edge | 0001000000 | 0110
scl_high | 0010000000 | 0111
stop_edge | 0100000000 | 1000
stop_wait | 1000000000 | 1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'scl_state_reg' using encoding 'one-hot' in module 'iic_control'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
SM_IDLE | 0010 | 00
SM_CMD_EN | 1000 | 01
SM_CMD_ACCEPTED | 0100 | 10
SM_DONE | 0001 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
P_WRITE_IDLE | 001 | 00
P_WRITE_DATA | 010 | 01
P_WRITE_RESP | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_axi.write_cs_reg' using encoding 'one-hot' in module 'axi_crossbar_v2_1_21_decerr_slave'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
ZERO | 1000 | 10
ONE | 0010 | 11
TWO | 0001 | 01
iSTATE | 0100 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
ZERO | 1000 | 10
ONE | 0010 | 11
TWO | 0001 | 01
iSTATE | 0100 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
ZERO | 1000 | 10
ONE | 0010 | 11
TWO | 0001 | 01
iSTATE | 0100 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized2'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 0001 | 00
RRST_IN | 0010 | 10
RRST_OUT | 0100 | 11
RRST_EXIT | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 0001 | 00
stage1_valid | 0010 | 10
both_stages_valid | 0100 | 11
stage2_valid | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized1'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 0001 | 00
RRST_IN | 0010 | 10
RRST_OUT | 0100 | 11
RRST_EXIT | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 0001 | 00
stage1_valid | 0010 | 10
both_stages_valid | 0100 | 11
stage2_valid | 1000 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized2'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 001 | 00
transfer_okay | 010 | 01
temp_transfer_okay | 100 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' using encoding 'one-hot' in module 'qspi_mode_0_module'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
READ_CMD_FIFO | 01 | 01
AXI_TRANSACTION | 10 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_cmd_decode'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RDQ_IDLE | 001 | 001
RDQ_CMD_CNT | 010 | 010
RDQ_DONE_CNT | 100 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'rd_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRQ_IDLE | 001 | 001
WRQ_CMD_CNT | 010 | 010
WRQ_DONE_CNT | 100 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'wr_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
READ_AXI | 0001 | 0001
AXI_RD_ADDR | 0010 | 0010
AXI_RD_DATA | 0100 | 0100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_read_axi'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
sm_idle | 0010 | 00
sm_read | 1000 | 01
sm_write | 0100 | 10
sm_resp | 0001 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
init | 00000000001 | 0000
assert_all_resets | 00000000010 | 0001
wait_for_pll_lock | 00000000100 | 0010
release_pll_reset | 00000001000 | 0011
verify_recclk_stable | 00000010000 | 0100
release_mmcm_reset | 00000100000 | 0101
wait_for_rxusrclk | 00001000000 | 0110
wait_reset_done | 00010000000 | 0111
do_phase_alignment | 00100000000 | 1000
monitor_data_valid | 01000000000 | 1001
fsm_done | 10000000000 | 1010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_RX_STARTUP_FSM'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
init | 0000000001 | 0000
assert_all_resets | 0000000010 | 0001
wait_for_pll_lock | 0000000100 | 0010
release_pll_reset | 0000001000 | 0011
wait_for_txoutclk | 0000010000 | 0100
release_mmcm_reset | 0000100000 | 0101
wait_for_txusrclk | 0001000000 | 0110
wait_reset_done | 0010000000 | 0111
do_phase_alignment | 0100000000 | 1000
reset_fsm_done | 1000000000 | 1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_TX_STARTUP_FSM'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:46 ; elapsed = 00:05:19 . Memory (MB): peak = 3278.910 ; gain = 822.188 ; free physical = 4952 ; free virtual = 18084
---------------------------------------------------------------------------------
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
Report RTL Partitions:
+------+-----------------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+-----------------------------------+------------+----------+
|1 |axi4_subsys__GB0 | 1| 34728|
|2 |axi4_subsys__GB1 | 1| 11187|
|3 |ROD_system__GC0 | 1| 26306|
|4 |rod_RO_Tx_exdes__GC0 | 1| 60|
|5 |aurora_64b_rx_12ch__GC0 | 1| 4942|
|6 |fex_chan_regs | 12| 7641|
|7 |channel_fifo__GC0 | 1| 3155|
|8 |channel_fifo__parameterized1__GC0 | 1| 3155|
|9 |channel_fifo__parameterized3__GC0 | 1| 3155|
|10 |channel_fifo__parameterized5__GC0 | 1| 3077|
|11 |channel_fifo__parameterized7__GC0 | 1| 3077|
|12 |channel_fifo__parameterized9__GC0 | 1| 3075|
|13 |channel_fifo__parameterized11__GC0 | 1| 3077|
|14 |channel_fifo__parameterized13__GC0 | 1| 3077|
|15 |channel_fifo__parameterized15__GC0 | 1| 3075|
|16 |channel_fifo__parameterized17__GC0 | 1| 3075|
|17 |channel_fifo__parameterized19__GC0 | 1| 3075|
|18 |channel_fifo__parameterized21__GC0 | 1| 3075|
|19 |input_fifos__GC0 | 1| 5921|
|20 |tob_processor | 1| 27088|
|21 |packet_processor__GCB1 | 1| 17380|
|22 |packet_processor__GCB2 | 1| 2620|
|23 |packet_processor__GCB3 | 1| 10041|
|24 |top_rod_efex__GC0 | 1| 21087|
+------+-----------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
2 Input 24 Bit Adders := 1
3 Input 17 Bit Adders := 114
2 Input 16 Bit Adders := 129
2 Input 13 Bit Adders := 3
2 Input 12 Bit Adders := 50
2 Input 10 Bit Adders := 11
3 Input 9 Bit Adders := 1
2 Input 9 Bit Adders := 21
2 Input 8 Bit Adders := 62
4 Input 8 Bit Adders := 2
3 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 14
4 Input 7 Bit Adders := 8
3 Input 7 Bit Adders := 2
2 Input 6 Bit Adders := 7
4 Input 6 Bit Adders := 6
2 Input 5 Bit Adders := 85
4 Input 5 Bit Adders := 6
3 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 116
4 Input 4 Bit Adders := 12
3 Input 3 Bit Adders := 1
2 Input 3 Bit Adders := 4
2 Input 2 Bit Adders := 90
4 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 3
+---XORs :
2 Input 20 Bit XORs := 778
2 Input 16 Bit XORs := 1
4 Input 16 Bit XORs := 1
2 Input 9 Bit XORs := 1918
2 Input 8 Bit XORs := 7
2 Input 7 Bit XORs := 4
2 Input 6 Bit XORs := 2
2 Input 5 Bit XORs := 4
2 Input 4 Bit XORs := 8
2 Input 1 Bit XORs := 473
4 Input 1 Bit XORs := 66
3 Input 1 Bit XORs := 18
9 Input 1 Bit XORs := 12
21 Input 1 Bit XORs := 6
15 Input 1 Bit XORs := 6
10 Input 1 Bit XORs := 12
19 Input 1 Bit XORs := 6
14 Input 1 Bit XORs := 6
12 Input 1 Bit XORs := 6
7 Input 1 Bit XORs := 6
+---Registers :
128 Bit Registers := 10
120 Bit Registers := 1
112 Bit Registers := 1
96 Bit Registers := 2
80 Bit Registers := 3
65 Bit Registers := 2
64 Bit Registers := 78
63 Bit Registers := 24
57 Bit Registers := 1
56 Bit Registers := 1
48 Bit Registers := 5
45 Bit Registers := 2
42 Bit Registers := 3
38 Bit Registers := 1
37 Bit Registers := 29
36 Bit Registers := 1
34 Bit Registers := 1
32 Bit Registers := 559
24 Bit Registers := 10
22 Bit Registers := 1
21 Bit Registers := 1
20 Bit Registers := 23
17 Bit Registers := 3
16 Bit Registers := 167
14 Bit Registers := 1
13 Bit Registers := 33
12 Bit Registers := 46
11 Bit Registers := 1
10 Bit Registers := 52
9 Bit Registers := 99
8 Bit Registers := 170
7 Bit Registers := 55
6 Bit Registers := 33
5 Bit Registers := 111
4 Bit Registers := 313
3 Bit Registers := 18
2 Bit Registers := 223
1 Bit Registers := 6559
+---RAMs :
256K Bit RAMs := 1
64K Bit RAMs := 4
32K Bit RAMs := 1
4K Bit RAMs := 1
2K Bit RAMs := 1
512 Bit RAMs := 2
+---Muxes :
2 Input 128 Bit Muxes := 8
4 Input 128 Bit Muxes := 1
2 Input 120 Bit Muxes := 1
2 Input 112 Bit Muxes := 1
2 Input 80 Bit Muxes := 12
2 Input 64 Bit Muxes := 21
4 Input 64 Bit Muxes := 4
5 Input 64 Bit Muxes := 1
2 Input 63 Bit Muxes := 24
2 Input 56 Bit Muxes := 1
3 Input 56 Bit Muxes := 1
16 Input 48 Bit Muxes := 1
2 Input 48 Bit Muxes := 6
4 Input 48 Bit Muxes := 1
5 Input 48 Bit Muxes := 1
2 Input 42 Bit Muxes := 2
3 Input 42 Bit Muxes := 1
2 Input 38 Bit Muxes := 6
3 Input 38 Bit Muxes := 1
2 Input 37 Bit Muxes := 29
3 Input 36 Bit Muxes := 1
3 Input 34 Bit Muxes := 1
2 Input 32 Bit Muxes := 151
5 Input 32 Bit Muxes := 1
16 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 12
24 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
37 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 4
24 Input 28 Bit Muxes := 1
2 Input 24 Bit Muxes := 10
24 Input 24 Bit Muxes := 2
5 Input 24 Bit Muxes := 2
3 Input 22 Bit Muxes := 1
2 Input 20 Bit Muxes := 682
4 Input 18 Bit Muxes := 1
58 Input 17 Bit Muxes := 1
24 Input 17 Bit Muxes := 1
2 Input 16 Bit Muxes := 90
5 Input 16 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
14 Input 16 Bit Muxes := 2
4 Input 16 Bit Muxes := 1
6 Input 16 Bit Muxes := 1
18 Input 16 Bit Muxes := 1
8 Input 16 Bit Muxes := 3
15 Input 15 Bit Muxes := 1
33 Input 14 Bit Muxes := 1
2 Input 13 Bit Muxes := 51
4 Input 13 Bit Muxes := 2
8 Input 13 Bit Muxes := 3
17 Input 13 Bit Muxes := 2
2 Input 12 Bit Muxes := 50
14 Input 12 Bit Muxes := 1
5 Input 12 Bit Muxes := 1
11 Input 11 Bit Muxes := 4
2 Input 11 Bit Muxes := 24
2 Input 10 Bit Muxes := 39
10 Input 10 Bit Muxes := 4
4 Input 10 Bit Muxes := 7
3 Input 9 Bit Muxes := 3
2 Input 9 Bit Muxes := 1939
5 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 81
6 Input 8 Bit Muxes := 2
5 Input 8 Bit Muxes := 6
4 Input 8 Bit Muxes := 1
7 Input 8 Bit Muxes := 1
17 Input 8 Bit Muxes := 2
3 Input 8 Bit Muxes := 1
7 Input 7 Bit Muxes := 2
2 Input 7 Bit Muxes := 35
21 Input 7 Bit Muxes := 2
5 Input 7 Bit Muxes := 1
3 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 37
24 Input 6 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
6 Input 6 Bit Muxes := 4
5 Input 6 Bit Muxes := 2
8 Input 6 Bit Muxes := 1
7 Input 6 Bit Muxes := 2
2 Input 5 Bit Muxes := 125
17 Input 5 Bit Muxes := 6
4 Input 5 Bit Muxes := 2
6 Input 5 Bit Muxes := 4
3 Input 5 Bit Muxes := 5
5 Input 5 Bit Muxes := 1
28 Input 5 Bit Muxes := 12
27 Input 5 Bit Muxes := 1
21 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 311
3 Input 4 Bit Muxes := 17
7 Input 4 Bit Muxes := 4
5 Input 4 Bit Muxes := 9
4 Input 4 Bit Muxes := 19
6 Input 4 Bit Muxes := 1
12 Input 4 Bit Muxes := 1
16 Input 4 Bit Muxes := 1
9 Input 4 Bit Muxes := 4
2 Input 3 Bit Muxes := 37
4 Input 3 Bit Muxes := 5
3 Input 3 Bit Muxes := 2
7 Input 3 Bit Muxes := 2
14 Input 3 Bit Muxes := 1
11 Input 3 Bit Muxes := 1
6 Input 3 Bit Muxes := 1
8 Input 3 Bit Muxes := 5
13 Input 3 Bit Muxes := 1
5 Input 3 Bit Muxes := 4
9 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 276
3 Input 2 Bit Muxes := 8
5 Input 2 Bit Muxes := 5
7 Input 2 Bit Muxes := 5
4 Input 2 Bit Muxes := 49
24 Input 2 Bit Muxes := 1
6 Input 2 Bit Muxes := 2
11 Input 2 Bit Muxes := 2
13 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 2171
7 Input 1 Bit Muxes := 19
5 Input 1 Bit Muxes := 42
17 Input 1 Bit Muxes := 34
3 Input 1 Bit Muxes := 38
4 Input 1 Bit Muxes := 110
10 Input 1 Bit Muxes := 40
6 Input 1 Bit Muxes := 16
14 Input 1 Bit Muxes := 19
15 Input 1 Bit Muxes := 1
24 Input 1 Bit Muxes := 12
9 Input 1 Bit Muxes := 3
11 Input 1 Bit Muxes := 57
13 Input 1 Bit Muxes := 3
8 Input 1 Bit Muxes := 9
16 Input 1 Bit Muxes := 5
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module axi_emc_addr_gen
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
3 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 4
+---Registers :
20 Bit Registers := 1
6 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 6 Bit Muxes := 3
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 9
Module axi_emc_address_decode
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
2 Input 1 Bit Muxes := 4
Module cntr_incr_decr_addn_f
Detailed RTL Component Info :
+---Adders :
3 Input 9 Bit Adders := 1
+---Registers :
9 Bit Registers := 1
Module srl_fifo_rbu_f
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 3
Module axi_emc_v3_0_20_counter_f
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
3 Input 9 Bit Muxes := 1
2 Input 9 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module axi_emc_native_interface
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 3
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 4
4 Bit Registers := 2
2 Bit Registers := 6
1 Bit Registers := 11
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 8 Bit Muxes := 4
7 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 14
2 Input 4 Bit Muxes := 6
4 Input 3 Bit Muxes := 2
3 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
7 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 6
2 Input 1 Bit Muxes := 13
7 Input 1 Bit Muxes := 12
Module ld_arith_reg__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
+---Muxes :
2 Input 1 Bit Muxes := 8
Module ld_arith_reg
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
+---Muxes :
2 Input 1 Bit Muxes := 8
Module emc_common_v3_0_5_ipic_if
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---XORs :
2 Input 8 Bit XORs := 1
+---Registers :
32 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
14 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
5 Input 1 Bit Muxes := 1
Module mem_state_machine
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 14
+---Muxes :
58 Input 17 Bit Muxes := 1
2 Input 5 Bit Muxes := 24
17 Input 5 Bit Muxes := 3
3 Input 4 Bit Muxes := 6
2 Input 4 Bit Muxes := 4
7 Input 4 Bit Muxes := 4
5 Input 4 Bit Muxes := 2
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 36
17 Input 1 Bit Muxes := 34
Module ld_arith_reg__parameterized0__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module ld_arith_reg__parameterized1__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module ld_arith_reg__parameterized1__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module ld_arith_reg__parameterized0__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module ld_arith_reg__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module ld_arith_reg__parameterized2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 16
+---Muxes :
2 Input 1 Bit Muxes := 16
Module ld_arith_reg__parameterized1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
+---Muxes :
2 Input 1 Bit Muxes := 5
Module mem_steer
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module io_registers
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 4
4 Bit Registers := 5
1 Bit Registers := 9
+---Muxes :
2 Input 32 Bit Muxes := 2
Module EMC
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
Module axi_emc
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_address_decoder
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 29
Module axi4_subsys_xadc_wiz_0_0_slave_attachment
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
7 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 10 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 3
Module axi4_subsys_xadc_wiz_0_0_xadc_core_drp
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
11 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 20
+---Muxes :
4 Input 18 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
3 Input 1 Bit Muxes := 1
Module axi4_subsys_xadc_wiz_0_0_soft_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi4_subsys_xadc_wiz_0_0_interrupt_control
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 17
+---Registers :
17 Bit Registers := 1
1 Bit Registers := 56
+---Muxes :
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 19
Module axi4_subsys_xadc_wiz_0_0_axi_xadc
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 14
Module xsdbs_v1_0_2_xsdbs
Detailed RTL Component Info :
+---Registers :
128 Bit Registers := 1
16 Bit Registers := 2
1 Bit Registers := 1
+---Muxes :
2 Input 16 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module jtag_axi_v1_2_10_xsdb2txfifo
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module jtag_axi_v1_2_10_xsdb2txfifo__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
64 Bit Registers := 2
4 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module jtag_axi_v1_2_10_xsdb2txfifo__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
64 Bit Registers := 2
4 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module jtag_axi_v1_2_10_rxfifo2xsdb
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
16 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module jtag_axi_v1_2_10_xsdb_fifo_interface
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 2
8 Bit Registers := 1
5 Bit Registers := 2
2 Bit Registers := 2
1 Bit Registers := 14
+---Muxes :
2 Input 16 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module jtag_axi_v1_2_10_cmd_decode__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 5
Module jtag_axi_v1_2_10_cmd_decode
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 5
Module dmem
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
Module memory
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
Module xpm_cdc_gray__parameterized6__6
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 4
Module xpm_cdc_gray__parameterized6
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 4
Module rd_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
Module compare__3
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module compare
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module rd_status_flags_as
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module rd_handshaking_flags
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module rd_fwft
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 3
Module compare__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module compare__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module wr_status_flags_as
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module blk_mem_gen_prim_width
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
+---Registers :
5 Bit Registers := 2
1 Bit Registers := 8
Module memory__parameterized0
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
Module xpm_cdc_gray__parameterized6__4
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 4
Module xpm_cdc_gray__parameterized6__5
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 4
Module rd_bin_cntr__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
Module compare__7
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module compare__6
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module rd_status_flags_as__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module rd_handshaking_flags__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module rd_fwft__4
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 3
Module compare__5
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module compare__4
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
Module wr_status_flags_as__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module blk_mem_gen_prim_width__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
+---Registers :
5 Bit Registers := 2
1 Bit Registers := 8
Module memory__parameterized1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
Module xpm_cdc_gray__parameterized8__6
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 4
Module xpm_cdc_gray__parameterized8
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 4
Module rd_bin_cntr__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
Module compare__parameterized0__4
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module compare__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module rd_status_flags_as__parameterized0
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module rd_handshaking_flags__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module rd_fwft__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 3
Module compare__parameterized0__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module compare__parameterized0__3
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module wr_status_flags_as__parameterized0
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module blk_mem_gen_prim_width__parameterized0__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
+---Registers :
5 Bit Registers := 2
1 Bit Registers := 8
Module memory__parameterized1__2
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
Module xpm_cdc_gray__parameterized8__4
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 4
Module xpm_cdc_gray__parameterized8__5
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 4
Module rd_bin_cntr__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
Module compare__parameterized0__8
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module compare__parameterized0__7
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module rd_status_flags_as__parameterized0__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 1
Module rd_handshaking_flags__3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module rd_fwft__3
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 3
Module compare__parameterized0__6
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module compare__parameterized0__5
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
Module wr_status_flags_as__parameterized0__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module jtag_axi_v1_2_10_jtag_axi_engine
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 1
+---Registers :
64 Bit Registers := 2
17 Bit Registers := 1
16 Bit Registers := 6
5 Bit Registers := 2
4 Bit Registers := 5
2 Bit Registers := 2
1 Bit Registers := 43
+---Muxes :
4 Input 5 Bit Muxes := 2
4 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 9
4 Input 1 Bit Muxes := 12
Module jtag_axi_v1_2_10_write_axi
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 3
+---Registers :
64 Bit Registers := 1
9 Bit Registers := 2
8 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
5 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 2
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
5 Input 1 Bit Muxes := 7
Module jtag_axi_v1_2_10_read_axi
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
32 Bit Registers := 1
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 8 Bit Muxes := 2
4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 9
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized29__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized30__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized31__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized32__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized33__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized34__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized35__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized36__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized37__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized38__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized39__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized40__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized41__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized42__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized43__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized44__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized45__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized47__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized48__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized49__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized50__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized51__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized52__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized53__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized54__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized55__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized56__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized57__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized58__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized59__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized60__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized61__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized62__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized63__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized64__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder__parameterized1__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 39
Module slave_attachment__parameterized1__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
9 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 7
+---Muxes :
2 Input 9 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 3
Module interrupt_control__parameterized0__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 13
+---Muxes :
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 10
Module axi_iic_v2_0_23_soft_reset__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi_ipif_ssp1__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module reg_interface__1
Detailed RTL Component Info :
+---Registers :
10 Bit Registers := 8
8 Bit Registers := 3
7 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 12
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module upcnt_n__1
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module upcnt_n__2
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module shift8__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module shift8__2
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module upcnt_n__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
+---Muxes :
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module iic_control__1
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 54
+---Muxes :
10 Input 10 Bit Muxes := 1
2 Input 10 Bit Muxes := 13
3 Input 9 Bit Muxes := 1
21 Input 7 Bit Muxes := 1
2 Input 1 Bit Muxes := 37
7 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
10 Input 1 Bit Muxes := 10
Module SRL_FIFO__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module SRL_FIFO__parameterized0__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module dynamic_master__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
Module SRL_FIFO__parameterized1__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module iic__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
2 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__1
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__1
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__1
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__11
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__11
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__11
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__5
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel__5
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__5
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__5
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel__5
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__10
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__10
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__10
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__5
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel__5
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__5
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__5
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel__5
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__11
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__5
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__10
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__5
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__9
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__9
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__4
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel__4
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__4
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__4
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel__4
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__8
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__8
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__4
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel__4
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__4
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__4
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel__4
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__9
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__4
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__8
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__4
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__7
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__7
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__3
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel__3
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__3
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__3
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel__3
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__6
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__6
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__3
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel__3
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__3
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__3
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel__3
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__7
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__3
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__6
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__3
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s__3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__5
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__5
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel__2
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel__2
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__4
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__4
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__2
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__5
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__2
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__4
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__2
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__3
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__3
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 4
4 Input 2 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s_aw_channel__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
10 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
4 Input 10 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_b_channel__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__2
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 3
2 Input 9 Bit Adders := 1
+---Registers :
12 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__2
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---Registers :
12 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 3
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 8
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__1
Detailed RTL Component Info :
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_ar_channel__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_protocol_converter_v2_1_20_b2s_r_channel__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 2
Module axi_register_slice_v2_1_20_axic_register_slice__3
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__1
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__2
Detailed RTL Component Info :
+---Registers :
63 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 63 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__1
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_protocol_converter_v2_1_20_b2s__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_crossbar_v2_1_21_decerr_slave
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 7
+---Muxes :
2 Input 8 Bit Muxes := 1
3 Input 1 Bit Muxes := 9
2 Input 1 Bit Muxes := 12
Module axi_crossbar_v2_1_21_addr_arbiter__1
Detailed RTL Component Info :
+---Registers :
65 Bit Registers := 1
8 Bit Registers := 1
2 Bit Registers := 4
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 5
Module axi_crossbar_v2_1_21_addr_arbiter
Detailed RTL Component Info :
+---Registers :
65 Bit Registers := 1
8 Bit Registers := 1
2 Bit Registers := 4
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 5
Module axi_crossbar_v2_1_21_splitter__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_crossbar_v2_1_21_addr_decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 7 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module generic_baseblocks_v2_1_0_mux_enc
Detailed RTL Component Info :
+---Muxes :
2 Input 38 Bit Muxes := 3
2 Input 1 Bit Muxes := 4
Module axi_crossbar_v2_1_21_si_transactor
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__3
Detailed RTL Component Info :
+---Muxes :
2 Input 7 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__5
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module generic_baseblocks_v2_1_0_mux_enc__parameterized0
Detailed RTL Component Info :
+---Muxes :
2 Input 6 Bit Muxes := 3
2 Input 1 Bit Muxes := 4
Module axi_crossbar_v2_1_21_si_transactor__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_splitter__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 3
Module axi_crossbar_v2_1_21_addr_decoder__2
Detailed RTL Component Info :
+---Muxes :
2 Input 7 Bit Muxes := 1
Module axi_crossbar_v2_1_21_arbiter_resp
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 2
Module generic_baseblocks_v2_1_0_mux_enc__1
Detailed RTL Component Info :
+---Muxes :
2 Input 38 Bit Muxes := 3
2 Input 1 Bit Muxes := 4
Module axi_data_fifo_v2_1_19_axic_srl_fifo__3
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__4
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_si_transactor__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 5
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 16 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__1
Detailed RTL Component Info :
+---Muxes :
2 Input 7 Bit Muxes := 1
Module axi_crossbar_v2_1_21_arbiter_resp__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 2
Module generic_baseblocks_v2_1_0_mux_enc__parameterized0__1
Detailed RTL Component Info :
+---Muxes :
2 Input 6 Bit Muxes := 3
2 Input 1 Bit Muxes := 4
Module axi_data_fifo_v2_1_19_axic_srl_fifo__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_si_transactor__parameterized2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 5
+---Registers :
2 Bit Registers := 1
+---Muxes :
2 Input 16 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_splitter
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 4
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 3
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__1
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__2
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__1
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__1
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__3
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__4
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__2
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__2
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__5
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__6
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__3
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__3
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__3
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__3
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__7
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__8
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__4
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__4
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__4
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__4
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__9
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__10
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__5
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__5
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__5
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__5
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__11
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__12
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__6
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__6
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__6
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__6
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__13
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__14
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__7
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__7
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__15
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_crossbar_v2_1_21_addr_decoder__parameterized0
Detailed RTL Component Info :
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
3 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
4 Input 1 Bit Muxes := 3
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 37 Bit Muxes := 2
Module axi_crossbar_v2_1_21_crossbar
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 2 Bit Adders := 21
2 Input 1 Bit Adders := 3
+---Registers :
8 Bit Registers := 2
1 Bit Registers := 1
+---Muxes :
2 Input 64 Bit Muxes := 16
2 Input 2 Bit Muxes := 29
2 Input 1 Bit Muxes := 3
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized29
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized30
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized31
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized32
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized33
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized34
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized35
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized36
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized37
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized38
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized39
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized40
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized41
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized42
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized43
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized44
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized45
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized47
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized48
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized49
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized50
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized51
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized52
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized53
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized54
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized55
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized56
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized57
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized58
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized59
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized60
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized61
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized62
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized63
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized64
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder__parameterized1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 39
Module slave_attachment__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
9 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 7
+---Muxes :
2 Input 9 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 3
Module interrupt_control__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 8
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 13
+---Muxes :
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 10
Module axi_iic_v2_0_23_soft_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi_ipif_ssp1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module reg_interface
Detailed RTL Component Info :
+---Registers :
10 Bit Registers := 8
8 Bit Registers := 3
7 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 12
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module upcnt_n__3
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module upcnt_n
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module shift8__3
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module shift8
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module upcnt_n__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
+---Muxes :
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module iic_control
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 54
+---Muxes :
10 Input 10 Bit Muxes := 1
2 Input 10 Bit Muxes := 13
3 Input 9 Bit Muxes := 1
21 Input 7 Bit Muxes := 1
2 Input 1 Bit Muxes := 37
7 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
10 Input 1 Bit Muxes := 10
Module SRL_FIFO
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module SRL_FIFO__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module dynamic_master
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
Module SRL_FIFO__parameterized1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module iic
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
2 Input 2 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized4
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized5
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized6
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized7
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized8
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized9
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized10
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized11
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized12
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized13
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized14
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized15
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized16
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized17
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized18
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized19
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized66
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized67
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder__parameterized2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 36
Module slave_attachment__parameterized2
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
7 Bit Registers := 1
6 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 7
+---Muxes :
2 Input 7 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 3
Module cross_clk_sync_fifo_1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 12
+---Registers :
1 Bit Registers := 6
Module xpm_counter_updn__parameterized7
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized8__3
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_memory_base__parameterized1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
+---RAMs :
512 Bit RAMs := 1
Module xpm_cdc_gray__parameterized2__3
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized2__3
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_gray__parameterized3
Detailed RTL Component Info :
+---XORs :
2 Input 5 Bit XORs := 1
2 Input 1 Bit XORs := 4
+---Registers :
5 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized3__3
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module xpm_cdc_gray__parameterized2
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized2
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_gray__parameterized4
Detailed RTL Component Info :
+---XORs :
2 Input 5 Bit XORs := 1
2 Input 1 Bit XORs := 4
+---Registers :
5 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized3
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module xpm_fifo_reg_bit__10
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__11
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__12
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized9
Detailed RTL Component Info :
+---Adders :
4 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 1
Module xpm_cdc_sync_rst__parameterized0__6
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module xpm_cdc_sync_rst__parameterized0
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module xpm_fifo_rst__parameterized0__xdcDup__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
6 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 8
5 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 3
Module xpm_fifo_reg_bit__13
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized10__3
Detailed RTL Component Info :
+---Adders :
4 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
Module xpm_counter_updn__parameterized11__3
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized8
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized10
Detailed RTL Component Info :
+---Adders :
4 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
Module xpm_counter_updn__parameterized11
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_fifo_base__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
3 Input 5 Bit Adders := 2
4 Input 5 Bit Adders := 1
4 Input 4 Bit Adders := 1
+---Registers :
5 Bit Registers := 3
4 Bit Registers := 1
1 Bit Registers := 13
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 25
4 Input 2 Bit Muxes := 6
2 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 2
3 Input 1 Bit Muxes := 1
Module axi_quad_spi_v3_2_19_counter_f__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
3 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module xpm_counter_updn__parameterized7__1
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized8__1
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_memory_base__parameterized1__1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
+---RAMs :
512 Bit RAMs := 1
Module xpm_cdc_gray__parameterized2__1
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized2__1
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_gray__parameterized3__1
Detailed RTL Component Info :
+---XORs :
2 Input 5 Bit XORs := 1
2 Input 1 Bit XORs := 4
+---Registers :
5 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized3__1
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module xpm_cdc_gray__parameterized2__2
Detailed RTL Component Info :
+---XORs :
2 Input 4 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
4 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized2__2
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_gray__parameterized4__1
Detailed RTL Component Info :
+---XORs :
2 Input 5 Bit XORs := 1
2 Input 1 Bit XORs := 4
+---Registers :
5 Bit Registers := 3
Module xpm_fifo_reg_vec__parameterized3__2
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module xpm_fifo_reg_bit__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized9__1
Detailed RTL Component Info :
+---Adders :
4 Input 2 Bit Adders := 1
+---Registers :
2 Bit Registers := 1
Module xpm_cdc_sync_rst__parameterized0__4
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module xpm_cdc_sync_rst__parameterized0__5
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
Module xpm_fifo_rst__parameterized0
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
6 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 8
5 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 3
Module xpm_fifo_reg_bit__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized10__1
Detailed RTL Component Info :
+---Adders :
4 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
Module xpm_counter_updn__parameterized11__1
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized8__2
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_counter_updn__parameterized10__2
Detailed RTL Component Info :
+---Adders :
4 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
Module xpm_counter_updn__parameterized11__2
Detailed RTL Component Info :
+---Adders :
4 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module xpm_fifo_base__parameterized2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
3 Input 5 Bit Adders := 2
4 Input 5 Bit Adders := 1
4 Input 4 Bit Adders := 1
+---Registers :
5 Bit Registers := 3
4 Bit Registers := 1
1 Bit Registers := 13
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 25
4 Input 2 Bit Muxes := 6
4 Input 1 Bit Muxes := 2
2 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
Module axi_quad_spi_v3_2_19_counter_f
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
3 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module qspi_fifo_ifmodule
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 6
Module qspi_mode_0_module
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 2
+---Registers :
32 Bit Registers := 5
7 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 28
+---Muxes :
2 Input 32 Bit Muxes := 9
2 Input 7 Bit Muxes := 1
11 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 25
4 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
Module qspi_cntrl_reg
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 10
Module qspi_status_slave_sel_reg
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi_quad_spi_v3_2_19_soft_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module interrupt_control__parameterized1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 14
+---Registers :
14 Bit Registers := 1
1 Bit Registers := 19
+---Muxes :
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 16
Module qspi_core_interface
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
+---XORs :
2 Input 1 Bit XORs := 2
+---Registers :
32 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 31
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 10
Module axi_quad_spi_top
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3__2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized4__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized5__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized6__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized7__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized8__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized9__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized10__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized11__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized12__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized13__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized14__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized15__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized16__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized17__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized18__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized19__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized20
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28__1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder__parameterized0
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 27
Module slave_attachment__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
9 Bit Registers := 1
5 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 7
+---Muxes :
2 Input 9 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 3
Module xpm_counter_updn
Detailed RTL Component Info :
+---Adders :
4 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
Module xpm_counter_updn__parameterized0__1
Detailed RTL Component Info :
+---Adders :
4 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
Module xpm_memory_base
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
+---RAMs :
2K Bit RAMs := 1
Module xpm_cdc_gray__1
Detailed RTL Component Info :
+---XORs :
2 Input 6 Bit XORs := 1
2 Input 1 Bit XORs := 5
+---Registers :
6 Bit Registers := 5
Module xpm_fifo_reg_vec__1
Detailed RTL Component Info :
+---Registers :
6 Bit Registers := 1
Module xpm_cdc_gray__parameterized0__3
Detailed RTL Component Info :
+---XORs :
2 Input 7 Bit XORs := 1
2 Input 1 Bit XORs := 6
+---Registers :
7 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized0__3
Detailed RTL Component Info :
+---Registers :
7 Bit Registers := 1
Module xpm_cdc_gray
Detailed RTL Component Info :
+---XORs :
2 Input 6 Bit XORs := 1
2 Input 1 Bit XORs := 5
+---Registers :
6 Bit Registers := 5
Module xpm_fifo_reg_vec
Detailed RTL Component Info :
+---Registers :
6 Bit Registers := 1
Module xpm_cdc_gray__parameterized0
Detailed RTL Component Info :
+---XORs :
2 Input 7 Bit XORs := 1
2 Input 1 Bit XORs := 6
+---Registers :
7 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized0
Detailed RTL Component Info :
+---Registers :
7 Bit Registers := 1
Module xpm_cdc_sync_rst__6
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_sync_rst
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_fifo_rst__xdcDup__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
6 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 8
5 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 3
Module xpm_fifo_reg_bit__3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized1__1
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_counter_updn__parameterized2__1
Detailed RTL Component Info :
+---Adders :
4 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
Module xpm_counter_updn__parameterized0
Detailed RTL Component Info :
+---Adders :
4 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
Module xpm_counter_updn__parameterized1
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_counter_updn__parameterized2
Detailed RTL Component Info :
+---Adders :
4 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
Module xpm_fifo_base
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
3 Input 7 Bit Adders := 2
4 Input 6 Bit Adders := 1
+---Registers :
7 Bit Registers := 3
6 Bit Registers := 1
1 Bit Registers := 11
Module xpm_counter_updn__parameterized3
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_counter_updn__parameterized4__1
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_memory_base__parameterized0
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
+---RAMs :
4K Bit RAMs := 1
Module xpm_cdc_gray__parameterized0__1
Detailed RTL Component Info :
+---XORs :
2 Input 7 Bit XORs := 1
2 Input 1 Bit XORs := 6
+---Registers :
7 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized0__1
Detailed RTL Component Info :
+---Registers :
7 Bit Registers := 1
Module xpm_cdc_gray__parameterized1__1
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized1__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
Module xpm_cdc_gray__parameterized0__2
Detailed RTL Component Info :
+---XORs :
2 Input 7 Bit XORs := 1
2 Input 1 Bit XORs := 6
+---Registers :
7 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized0__2
Detailed RTL Component Info :
+---Registers :
7 Bit Registers := 1
Module xpm_cdc_gray__parameterized1
Detailed RTL Component Info :
+---XORs :
2 Input 8 Bit XORs := 1
2 Input 1 Bit XORs := 7
+---Registers :
8 Bit Registers := 5
Module xpm_fifo_reg_vec__parameterized1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
Module xpm_cdc_sync_rst__4
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_cdc_sync_rst__5
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module xpm_fifo_rst
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
6 Input 5 Bit Muxes := 1
2 Input 5 Bit Muxes := 8
5 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 3
Module xpm_fifo_reg_bit__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_fifo_reg_bit__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module xpm_counter_updn__parameterized5__1
Detailed RTL Component Info :
+---Adders :
4 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
Module xpm_counter_updn__parameterized6__1
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_counter_updn__parameterized4
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_counter_updn__parameterized5
Detailed RTL Component Info :
+---Adders :
4 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
Module xpm_counter_updn__parameterized6
Detailed RTL Component Info :
+---Adders :
4 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
Module xpm_fifo_base__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
3 Input 8 Bit Adders := 2
4 Input 7 Bit Adders := 1
+---Registers :
8 Bit Registers := 3
7 Bit Registers := 1
1 Bit Registers := 11
Module axi_hwicap_v3_0_24_ipic_if
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
32 Bit Registers := 2
12 Bit Registers := 2
5 Bit Registers := 1
1 Bit Registers := 18
+---Muxes :
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module icap_statemachine_shared
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---Registers :
32 Bit Registers := 4
12 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 17
+---Muxes :
33 Input 14 Bit Muxes := 1
14 Input 12 Bit Muxes := 1
2 Input 1 Bit Muxes := 12
14 Input 1 Bit Muxes := 19
Module hwicap_shared
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 9
+---Muxes :
2 Input 1 Bit Muxes := 2
Module interrupt_control
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 4
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 9
+---Muxes :
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 6
Module axi_hwicap
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 4
Module axi_lite_ipif_v3_0_4_pselect_f
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized0
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module axi_lite_ipif_v3_0_4_pselect_f__parameterized2
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module address_decoder
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 6
Module slave_attachment
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
9 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 7
+---Muxes :
2 Input 9 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
7 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
4 Input 1 Bit Muxes := 3
Module GPIO_Core
Detailed RTL Component Info :
+---Registers :
24 Bit Registers := 3
16 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
5 Input 32 Bit Muxes := 1
2 Input 24 Bit Muxes := 3
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module axi_gpio
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 1
Module addr_sel_rom
Detailed RTL Component Info :
+---Muxes :
16 Input 48 Bit Muxes := 1
16 Input 32 Bit Muxes := 1
Module ipbus_fabric_sel
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module syncreg_r__6
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__4
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__parameterized0__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module syncreg_r__5
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__parameterized0__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module ipbus_ctrlreg_v
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
Module syncreg_r__3
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__parameterized0
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module dna_reader
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
57 Bit Registers := 1
7 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module common_IdVersion_regs
Detailed RTL Component Info :
+---Muxes :
6 Input 3 Bit Muxes := 1
Module ethernet_mac_rgmii_example_design_clocks
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ethernet_mac_rgmii_example_design_resets
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
1 Bit Registers := 7
Module ethernet_mac_rgmii_support_resets
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
+---Muxes :
15 Input 15 Bit Muxes := 1
15 Input 1 Bit Muxes := 1
Module ethernet_mac_rgmii_axi_lite_sm
Detailed RTL Component Info :
+---Registers :
37 Bit Registers := 1
32 Bit Registers := 4
21 Bit Registers := 1
17 Bit Registers := 1
12 Bit Registers := 2
8 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 20
+---Muxes :
2 Input 37 Bit Muxes := 1
2 Input 32 Bit Muxes := 4
4 Input 32 Bit Muxes := 1
24 Input 32 Bit Muxes := 1
24 Input 24 Bit Muxes := 1
2 Input 24 Bit Muxes := 3
24 Input 17 Bit Muxes := 1
2 Input 12 Bit Muxes := 10
5 Input 12 Bit Muxes := 1
24 Input 6 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 1
24 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 31
4 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 1
24 Input 1 Bit Muxes := 10
Module ipbus_clock_div
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
Module ipbus_clock_div__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
Module led_stretcher
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 1 Bit Muxes := 1
Module clocks_7s_extphy
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 8
Module udp_rarp_block
Detailed RTL Component Info :
+---Adders :
2 Input 24 Bit Adders := 1
2 Input 6 Bit Adders := 2
+---XORs :
2 Input 16 Bit XORs := 1
4 Input 16 Bit XORs := 1
+---Registers :
56 Bit Registers := 1
42 Bit Registers := 1
24 Bit Registers := 1
16 Bit Registers := 2
13 Bit Registers := 1
8 Bit Registers := 1
6 Bit Registers := 4
5 Bit Registers := 1
1 Bit Registers := 9
+---Muxes :
2 Input 56 Bit Muxes := 1
3 Input 56 Bit Muxes := 1
2 Input 42 Bit Muxes := 2
2 Input 24 Bit Muxes := 1
2 Input 16 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 3
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 7
4 Input 1 Bit Muxes := 1
Module udp_build_arp
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
48 Bit Registers := 3
13 Bit Registers := 1
8 Bit Registers := 1
6 Bit Registers := 5
1 Bit Registers := 10
+---Muxes :
2 Input 48 Bit Muxes := 5
4 Input 48 Bit Muxes := 1
2 Input 8 Bit Muxes := 2
3 Input 6 Bit Muxes := 1
6 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 11
2 Input 3 Bit Muxes := 1
6 Input 2 Bit Muxes := 2
6 Input 1 Bit Muxes := 2
2 Input 1 Bit Muxes := 9
3 Input 1 Bit Muxes := 1
Module udp_build_ping
Detailed RTL Component Info :
+---Adders :
2 Input 13 Bit Adders := 1
+---Registers :
16 Bit Registers := 3
13 Bit Registers := 7
8 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 20
+---Muxes :
2 Input 16 Bit Muxes := 10
5 Input 16 Bit Muxes := 1
2 Input 13 Bit Muxes := 11
4 Input 13 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
2 Input 6 Bit Muxes := 4
6 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
5 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 20
6 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 5
3 Input 1 Bit Muxes := 1
5 Input 1 Bit Muxes := 1
Module udp_ipaddr_block
Detailed RTL Component Info :
+---Registers :
80 Bit Registers := 3
48 Bit Registers := 1
42 Bit Registers := 1
32 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 80 Bit Muxes := 12
2 Input 1 Bit Muxes := 1
Module udp_build_payload
Detailed RTL Component Info :
+---Adders :
2 Input 13 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
16 Bit Registers := 5
13 Bit Registers := 8
8 Bit Registers := 3
1 Bit Registers := 30
+---Muxes :
2 Input 32 Bit Muxes := 4
2 Input 16 Bit Muxes := 12
3 Input 16 Bit Muxes := 1
14 Input 16 Bit Muxes := 2
4 Input 16 Bit Muxes := 1
2 Input 13 Bit Muxes := 17
2 Input 8 Bit Muxes := 6
6 Input 8 Bit Muxes := 1
5 Input 6 Bit Muxes := 1
8 Input 6 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
8 Input 3 Bit Muxes := 1
13 Input 3 Bit Muxes := 1
11 Input 2 Bit Muxes := 2
13 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 34
9 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 2
3 Input 1 Bit Muxes := 2
11 Input 1 Bit Muxes := 1
13 Input 1 Bit Muxes := 3
Module udp_build_resend
Detailed RTL Component Info :
+---Registers :
45 Bit Registers := 1
16 Bit Registers := 2
1 Bit Registers := 1
+---Muxes :
2 Input 16 Bit Muxes := 8
Module udp_build_status
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
128 Bit Registers := 1
13 Bit Registers := 1
8 Bit Registers := 1
7 Bit Registers := 5
1 Bit Registers := 11
+---Muxes :
2 Input 128 Bit Muxes := 2
2 Input 8 Bit Muxes := 2
2 Input 7 Bit Muxes := 12
2 Input 6 Bit Muxes := 2
7 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
8 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 9
8 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 3
Module udp_status_buffer
Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
128 Bit Registers := 4
16 Bit Registers := 2
8 Bit Registers := 1
5 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 13
+---Muxes :
2 Input 128 Bit Muxes := 4
4 Input 128 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 16 Bit Muxes := 4
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
2 Input 5 Bit Muxes := 3
5 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
4 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 25
4 Input 1 Bit Muxes := 2
Module udp_byte_sum__1
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 2
+---Registers :
9 Bit Registers := 5
8 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 9 Bit Muxes := 10
2 Input 8 Bit Muxes := 7
2 Input 1 Bit Muxes := 10
Module udp_do_rx_reset
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 12 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module udp_packet_parser
Detailed RTL Component Info :
+---Registers :
128 Bit Registers := 1
120 Bit Registers := 1
112 Bit Registers := 1
48 Bit Registers := 1
45 Bit Registers := 1
42 Bit Registers := 1
38 Bit Registers := 1
36 Bit Registers := 1
34 Bit Registers := 1
32 Bit Registers := 4
24 Bit Registers := 2
22 Bit Registers := 1
16 Bit Registers := 1
10 Bit Registers := 1
6 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 128 Bit Muxes := 1
2 Input 120 Bit Muxes := 1
2 Input 112 Bit Muxes := 1
2 Input 48 Bit Muxes := 1
5 Input 48 Bit Muxes := 1
3 Input 42 Bit Muxes := 1
3 Input 38 Bit Muxes := 1
3 Input 36 Bit Muxes := 1
3 Input 34 Bit Muxes := 1
2 Input 32 Bit Muxes := 4
4 Input 32 Bit Muxes := 1
2 Input 24 Bit Muxes := 2
5 Input 24 Bit Muxes := 2
3 Input 22 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
6 Input 16 Bit Muxes := 1
4 Input 10 Bit Muxes := 1
5 Input 8 Bit Muxes := 5
6 Input 8 Bit Muxes := 1
5 Input 7 Bit Muxes := 1
5 Input 6 Bit Muxes := 1
5 Input 4 Bit Muxes := 3
6 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 76
4 Input 1 Bit Muxes := 1
5 Input 1 Bit Muxes := 1
Module udp_rxram_mux
Detailed RTL Component Info :
+---Registers :
13 Bit Registers := 2
8 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 2
2 Input 1 Bit Muxes := 5
Module udp_DualPortRAM
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
+---RAMs :
32K Bit RAMs := 1
Module udp_buffer_selector
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 6
1 Bit Registers := 10
+---Muxes :
2 Input 2 Bit Muxes := 17
2 Input 1 Bit Muxes := 5
Module udp_rxram_shim
Detailed RTL Component Info :
+---Registers :
13 Bit Registers := 3
1 Bit Registers := 3
+---Muxes :
2 Input 13 Bit Muxes := 1
Module udp_DualPortRAM_rx
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 4
+---RAMs :
64K Bit RAMs := 4
+---Muxes :
4 Input 1 Bit Muxes := 4
Module udp_buffer_selector__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
+---Registers :
16 Bit Registers := 6
4 Bit Registers := 4
1 Bit Registers := 6
+---Muxes :
2 Input 16 Bit Muxes := 17
2 Input 4 Bit Muxes := 10
2 Input 1 Bit Muxes := 3
Module udp_rxtransactor_if
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
+---Muxes :
2 Input 1 Bit Muxes := 3
Module udp_DualPortRAM_tx
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 1
+---RAMs :
256K Bit RAMs := 1
+---Muxes :
4 Input 8 Bit Muxes := 1
Module udp_buffer_selector__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
+---Registers :
16 Bit Registers := 6
4 Bit Registers := 4
1 Bit Registers := 6
+---Muxes :
2 Input 16 Bit Muxes := 17
2 Input 4 Bit Muxes := 10
2 Input 1 Bit Muxes := 3
Module udp_byte_sum
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 2
+---Registers :
9 Bit Registers := 5
8 Bit Registers := 1
1 Bit Registers := 6
+---Muxes :
2 Input 9 Bit Muxes := 10
2 Input 8 Bit Muxes := 7
2 Input 1 Bit Muxes := 10
Module udp_tx_mux
Detailed RTL Component Info :
+---Adders :
2 Input 13 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
16 Bit Registers := 7
13 Bit Registers := 10
8 Bit Registers := 7
5 Bit Registers := 2
3 Bit Registers := 2
1 Bit Registers := 44
+---Muxes :
2 Input 32 Bit Muxes := 5
2 Input 16 Bit Muxes := 6
18 Input 16 Bit Muxes := 1
2 Input 13 Bit Muxes := 22
8 Input 13 Bit Muxes := 3
17 Input 13 Bit Muxes := 2
2 Input 8 Bit Muxes := 21
7 Input 8 Bit Muxes := 1
17 Input 8 Bit Muxes := 2
2 Input 5 Bit Muxes := 6
2 Input 3 Bit Muxes := 11
9 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
8 Input 1 Bit Muxes := 8
2 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 2
9 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 2
16 Input 1 Bit Muxes := 4
Module udp_txtransactor_if
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 16
4 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 16 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 16
16 Input 1 Bit Muxes := 1
Module udp_clock_crossing_if
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 10
+---Registers :
4 Bit Registers := 5
3 Bit Registers := 7
2 Bit Registers := 5
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 2
Module UDP_if
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 8 Bit Muxes := 1
Module transactor_if
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
16 Bit Registers := 2
12 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 3
7 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 3
7 Input 1 Bit Muxes := 1
Module transactor_sm
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
2 Input 8 Bit Adders := 3
+---Registers :
32 Bit Registers := 5
8 Bit Registers := 3
4 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 32 Bit Muxes := 5
3 Input 8 Bit Muxes := 1
6 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 6
2 Input 4 Bit Muxes := 1
3 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
4 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 2
6 Input 1 Bit Muxes := 1
Module transactor_cfg
Detailed RTL Component Info :
+---Registers :
128 Bit Registers := 1
+---Muxes :
2 Input 128 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized0__1
Detailed RTL Component Info :
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module ipbus_axi4_bridge
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module ipbus_example
Detailed RTL Component Info :
+---Muxes :
5 Input 3 Bit Muxes := 1
Module rod_RO_Tx_exdes
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module aurora_rx_1q_cdc_sync_exdes
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes__xdcDup__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes__xdcDup__1
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_1q_cdc_sync_exdes__10
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC__10
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes__xdcDup__2
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__9
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes__xdcDup__2
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_1q_cdc_sync_exdes__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC__9
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes__xdcDup__3
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__8
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes__xdcDup__3
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_1q_cdc_sync_exdes__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC__8
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes__xdcDup__4
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__7
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes__parameterized2
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_1q_cdc_sync_exdes__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC__7
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes__xdcDup__5
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__6
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes__xdcDup__4
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_1q_cdc_sync_exdes__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_1q_SUPPORT_RESET_LOGIC__6
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_1q_exdes
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module aurora_rx_4l_64b_cdc_sync_exdes__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 7
Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__5
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 2
Module aurora_rx_4l_64b_exdes
Detailed RTL Component Info :
+---Registers :
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 8
Module pulse_stretch
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module sume_RO_Rx_GT_FRAME_CHECK
Detailed RTL Component Info :
+---Adders :
2 Input 9 Bit Adders := 1
2 Input 7 Bit Adders := 1
+---Registers :
32 Bit Registers := 3
9 Bit Registers := 1
7 Bit Registers := 1
4 Bit Registers := 3
2 Bit Registers := 1
1 Bit Registers := 19
+---Muxes :
4 Input 32 Bit Muxes := 1
3 Input 7 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 10
Module rx_registers
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
32 Bit Registers := 4
2 Bit Registers := 1
+---Muxes :
2 Input 32 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module combined_ttc_rx
Detailed RTL Component Info :
+---Registers :
7 Bit Registers := 1
1 Bit Registers := 3
Module aurora_reset__1
Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
+---Registers :
16 Bit Registers := 1
1 Bit Registers := 12
+---Muxes :
2 Input 1 Bit Muxes := 10
5 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 1
Module pwr_on_timer
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module ipbus_fabric_sel__parameterized4
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 27
Module ipbus_reg_v__3
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__4
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__7
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__8
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__3
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__9
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__3
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module syncreg_r__10
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__4
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ipbus_reg_v__5
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__6
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__11
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__12
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__4
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__13
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__10
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__5
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module syncreg_r__14
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__11
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__6
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ipbus_reg_v__7
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module pulse_stretch__parameterized5
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ipbus_reg_v__8
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__15
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__12
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module error_counter__parameterized0__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module error_counter__parameterized0__2
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module error_counter__parameterized0__3
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module error_counter__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
Module pulse_stretch__parameterized5__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_reset
Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
+---Registers :
16 Bit Registers := 1
1 Bit Registers := 12
+---Muxes :
2 Input 1 Bit Muxes := 10
5 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 1
Module self_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module edge_error_counter
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__9
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__10
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__16
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__13
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__17
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__14
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__18
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__15
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__19
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__16
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__20
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__17
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__21
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__18
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__22
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__19
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__23
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__20
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__24
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__21
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__25
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__22
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module fex_chan_regs
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
+---Muxes :
28 Input 5 Bit Muxes := 1
Module pulse_stretch__parameterized1__3
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__1
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__1
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module pulse_stretch__parameterized1__4
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__2
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__2
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__2
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module pulse_stretch__parameterized1__5
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__3
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__3
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized3
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__3
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized3
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module pulse_stretch__parameterized1__6
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__4
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__4
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized5
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__4
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__7
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__5
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__5
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized7
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__5
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__8
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__6
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__6
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized9
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__6
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__9
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__7
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__7
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized11
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__7
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized11
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__10
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__8
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__8
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized13
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__8
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized13
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__11
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__9
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__9
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized15
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__9
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized15
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__12
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__10
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__10
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized17
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__10
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized17
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__13
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__11
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3__11
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized19
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx__11
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized19
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module pulse_stretch__parameterized1__14
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module CRC__12
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized3
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module aurora_pipe__parameterized21
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 5
9 Bit Registers := 1
1 Bit Registers := 31
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ufc_rx
Detailed RTL Component Info :
+---XORs :
4 Input 1 Bit XORs := 4
+---Registers :
16 Bit Registers := 4
4 Bit Registers := 2
1 Bit Registers := 8
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 2
Module channel_fifo__parameterized21
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
Module ipbus_fabric_sel__parameterized1
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 26
Module ipbus_fabric_sel__parameterized2
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 11
Module syncreg_r__36
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__33
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__16
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__17
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__18
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__19
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__20
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__37
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__34
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__21
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__38
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__35
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__39
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__36
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__40
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__37
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module priority_encoder
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 2
+---Muxes :
24 Input 28 Bit Muxes := 1
24 Input 24 Bit Muxes := 1
24 Input 1 Bit Muxes := 2
Module clock_test_ipbus
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
2 Input 8 Bit Adders := 1
2 Input 4 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
8 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 1 Bit Muxes := 2
Module backplane_regs
Detailed RTL Component Info :
+---Muxes :
12 Input 4 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized3
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 15
Module ipbus_reg_v__11
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__12
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__26
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__23
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__27
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__24
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__5
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__28
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__25
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__7
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ipbus_reg_v__13
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__29
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__26
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__30
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__27
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__31
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__28
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__14
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__15
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__32
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__29
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__33
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__30
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__34
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__31
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__35
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__32
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module error_counter__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
Module error_counter__2
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
Module error_counter
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
Module ttc_chan_regs
Detailed RTL Component Info :
+---Muxes :
16 Input 4 Bit Muxes := 1
Module input_fifos
Detailed RTL Component Info :
+---Muxes :
27 Input 5 Bit Muxes := 1
Module channel_mux
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
64 Bit Registers := 1
5 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 5 Bit Muxes := 2
2 Input 1 Bit Muxes := 7
Module vDFF
Detailed RTL Component Info :
+---Registers :
6 Bit Registers := 1
Module tob_timeout
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 2
Module osum_crc9d32__4
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module hdr_in_crc9
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
9 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 32 Bit Muxes := 1
Module osum_crc9d32__3
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module event_hdr_crc9__3
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module flx_CRC__1
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 147
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module event_trailer_CRC20__1
Detailed RTL Component Info :
+---Muxes :
2 Input 64 Bit Muxes := 1
Module flx_CRC
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 147
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module event_trailer_CRC20
Detailed RTL Component Info :
+---Muxes :
2 Input 64 Bit Muxes := 1
Module trailer_map__1
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 4
Module CRC__13
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module CRC__parameterized3
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 148
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module trailer_map
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
4 Bit Registers := 1
1 Bit Registers := 4
Module ev_builder
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 2
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 3
20 Bit Registers := 1
16 Bit Registers := 1
5 Bit Registers := 1
1 Bit Registers := 14
+---Muxes :
2 Input 64 Bit Muxes := 2
4 Input 64 Bit Muxes := 1
5 Input 64 Bit Muxes := 1
37 Input 32 Bit Muxes := 1
2 Input 6 Bit Muxes := 2
6 Input 6 Bit Muxes := 1
7 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 6
3 Input 5 Bit Muxes := 3
2 Input 4 Bit Muxes := 3
4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
7 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 7
Module ipbus_fabric_sel__parameterized5
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 20
Module ipbus_reg_v__23
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__24
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__48
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__45
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__6
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__49
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__46
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__7
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__50
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__47
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__25
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__51
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__48
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__52
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__49
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__8
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__53
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__50
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__9
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__54
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__51
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__26
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__27
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__28
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__55
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__52
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__56
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__53
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__8
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module syncreg_r__57
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__54
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module threshold_counter__9
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module ipbus_ctrlreg_v__parameterized0
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module syncreg_r__58
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__55
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__29
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_fabric_sel__parameterized6__3
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module ipbus_reg_v__22
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__41
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__38
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__42
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__39
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__43
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__40
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__44
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__41
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__45
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__42
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__46
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__43
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__47
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__44
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module pkt_capture_regs
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
32 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
9 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module tob_proc_regs
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
+---Registers :
8 Bit Registers := 2
+---Muxes :
21 Input 5 Bit Muxes := 1
Module dummy_chan_in__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
Module pulse_stretch__parameterized1__16
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module vDFF__parameterized1__4
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module bulk_controller__4
Detailed RTL Component Info :
+---Muxes :
2 Input 16 Bit Muxes := 1
8 Input 16 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
8 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
Module bulk_channel_mux__4
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 2
2 Input 1 Bit Muxes := 6
Module osum_crc9d32__6
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module event_hdr_crc9__5
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized7__4
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 16
Module ipbus_reg_v__31
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__32
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__66
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__63
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__10
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__67
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__64
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__33
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__68
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__65
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__69
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__66
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__11
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__70
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__67
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__15
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__71
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__68
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__34
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__35
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__43
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__72
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__69
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__73
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__70
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__90
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__87
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_fabric_sel__parameterized6__5
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module ipbus_reg_v__30
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__59
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__56
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__60
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__57
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__61
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__58
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__62
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__59
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__63
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__60
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__64
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__61
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__65
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__62
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module pkt_capture_regs__parameterized1__4
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
32 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
9 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module threshold_counter__10
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module threshold_counter__13
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module bulk_proc_regs__4
Detailed RTL Component Info :
+---Muxes :
17 Input 5 Bit Muxes := 1
Module bulk_processor
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module pulse_stretch__parameterized1__15
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module vDFF__parameterized1__3
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module bulk_controller__3
Detailed RTL Component Info :
+---Muxes :
2 Input 16 Bit Muxes := 1
8 Input 16 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
8 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
Module bulk_channel_mux__3
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 2
2 Input 1 Bit Muxes := 6
Module osum_crc9d32__5
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module event_hdr_crc9__4
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized7__3
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 16
Module ipbus_reg_v__42
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__41
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__89
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__86
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__14
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__88
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__85
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__40
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__87
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__84
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__86
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__83
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__13
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__85
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__82
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__12
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__84
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__81
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__39
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__38
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__37
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__83
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__80
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__82
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__79
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__81
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__78
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_fabric_sel__parameterized6__4
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module ipbus_reg_v__36
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__80
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__77
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__79
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__76
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__78
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__75
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__77
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__74
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__76
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__73
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__75
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__72
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__74
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__71
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module pkt_capture_regs__parameterized1__3
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
32 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
9 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module threshold_counter__12
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module threshold_counter__11
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module bulk_proc_regs__3
Detailed RTL Component Info :
+---Muxes :
17 Input 5 Bit Muxes := 1
Module bulk_processor__xdcDup__2
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module CRC
Detailed RTL Component Info :
+---XORs :
2 Input 9 Bit XORs := 137
+---Registers :
9 Bit Registers := 3
+---Muxes :
2 Input 9 Bit Muxes := 134
2 Input 1 Bit Muxes := 1
Module ro_controller
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
32 Bit Registers := 5
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 64 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
Module pulse_stretch__parameterized1__17
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module vDFF__parameterized1
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
Module bulk_controller
Detailed RTL Component Info :
+---Muxes :
2 Input 16 Bit Muxes := 1
8 Input 16 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
8 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
Module bulk_channel_mux
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 2
2 Input 1 Bit Muxes := 6
Module osum_crc9d32
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module event_hdr_crc9
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 9 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized7
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 16
Module ipbus_reg_v__45
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__46
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__98
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__95
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__16
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__99
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__96
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__47
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__100
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__97
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__101
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__98
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark__17
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__102
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__99
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module watermark
Detailed RTL Component Info :
+---Registers :
16 Bit Registers := 1
Module syncreg_r__103
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__100
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_reg_v__48
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v__49
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module ipbus_reg_v
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__104
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__101
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__105
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__102
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module ipbus_fabric_sel__parameterized6
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module ipbus_reg_v__44
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 1
Module syncreg_r__91
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__88
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__92
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__89
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__93
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__90
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__94
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__91
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__95
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__92
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__96
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__93
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module syncreg_r__97
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
1 Bit Registers := 9
Module ipbus_syncreg_v__94
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module pkt_capture_regs__parameterized1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
32 Bit Registers := 1
1 Bit Registers := 8
+---Muxes :
9 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module threshold_counter__14
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module threshold_counter
Detailed RTL Component Info :
+---Adders :
3 Input 17 Bit Adders := 2
2 Input 16 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module bulk_proc_regs
Detailed RTL Component Info :
+---Muxes :
17 Input 5 Bit Muxes := 1
Module bulk_processor__xdcDup__1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module dummy_chan_in
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
Module osum_crc9d32__7
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 3
9 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 11
4 Input 1 Bit XORs := 3
21 Input 1 Bit XORs := 1
15 Input 1 Bit XORs := 1
10 Input 1 Bit XORs := 2
19 Input 1 Bit XORs := 1
14 Input 1 Bit XORs := 1
12 Input 1 Bit XORs := 1
7 Input 1 Bit XORs := 1
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module ttc_info
Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
2 Input 12 Bit Adders := 1
+---Registers :
64 Bit Registers := 1
16 Bit Registers := 1
12 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
6 Input 1 Bit Muxes := 1
Module ipbus_fabric_sel__parameterized0
Detailed RTL Component Info :
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module pulse_stretch__parameterized1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module packet_processor
Detailed RTL Component Info :
+---Muxes :
2 Input 24 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
5 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module system_top_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module system_top_reset__parameterized1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module CRC__parameterized4
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 84
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 70
2 Input 1 Bit Muxes := 1
Module FMchannelTXctrl
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
4 Bit Registers := 3
1 Bit Registers := 11
+---Muxes :
6 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module rst_tmr
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module tx_data_mux
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module fm_axi
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module FM_example_emuram__xdcDup__1
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
1 Bit Registers := 3
Module FM_example_FIFOctrl
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
5 Input 1 Bit Muxes := 1
Module FM_channel__xdcDup__1
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
24 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 2
Module pulse_pdxx_pwxx__18
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__17
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__16
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__15
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module CRC__parameterized4__6
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 84
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 70
2 Input 1 Bit Muxes := 1
Module FMchannelTXctrl__6
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
4 Bit Registers := 3
1 Bit Registers := 11
+---Muxes :
6 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module rst_tmr__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module tx_data_mux__6
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module fm_axi__6
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module FM_example_emuram__xdcDup__2
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
1 Bit Registers := 3
Module FM_example_FIFOctrl__6
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
5 Input 1 Bit Muxes := 1
Module FM_channel__xdcDup__2
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
24 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 2
Module FullModeTransceiver_RX_STARTUP_FSM__4
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 30
+---Muxes :
11 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
11 Input 1 Bit Muxes := 14
Module FullModeTransceiver_RX_STARTUP_FSM
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 30
+---Muxes :
11 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
11 Input 1 Bit Muxes := 14
Module FullModeTransceiver_TX_STARTUP_FSM
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
1 Bit Registers := 21
+---Muxes :
10 Input 10 Bit Muxes := 1
2 Input 10 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 7
10 Input 1 Bit Muxes := 10
Module FullModeTransceiver__xdcDup__1
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
2 Input 8 Bit Adders := 1
+---Registers :
128 Bit Registers := 1
96 Bit Registers := 1
10 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 1 Bit Muxes := 2
Module pulse_pdxx_pwxx__14
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__13
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__12
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__11
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module CRC__parameterized4__5
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 84
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 70
2 Input 1 Bit Muxes := 1
Module FMchannelTXctrl__5
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
4 Bit Registers := 3
1 Bit Registers := 11
+---Muxes :
6 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module rst_tmr__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module tx_data_mux__5
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module fm_axi__5
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module FM_example_emuram__xdcDup__3
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
1 Bit Registers := 3
Module FM_example_FIFOctrl__5
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
5 Input 1 Bit Muxes := 1
Module FM_channel__xdcDup__3
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
24 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 2
Module pulse_pdxx_pwxx__10
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__9
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__8
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module pulse_pdxx_pwxx__7
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module CRC__parameterized4__4
Detailed RTL Component Info :
+---XORs :
2 Input 20 Bit XORs := 84
+---Registers :
20 Bit Registers := 3
+---Muxes :
2 Input 20 Bit Muxes := 70
2 Input 1 Bit Muxes := 1
Module FMchannelTXctrl__4
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 3
4 Bit Registers := 3
1 Bit Registers := 11
+---Muxes :
6 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module rst_tmr__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 4
Module tx_data_mux__4
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module fm_axi__4
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module FM_example_emuram
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
+---Registers :
10 Bit Registers := 1
1 Bit Registers := 3
Module FM_example_FIFOctrl__4
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
2 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
5 Input 1 Bit Muxes := 1
Module FM_channel
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
24 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 2
Module FullModeTransceiver_RX_STARTUP_FSM__2
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 30
+---Muxes :
11 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
11 Input 1 Bit Muxes := 14
Module FullModeTransceiver_RX_STARTUP_FSM__3
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 30
+---Muxes :
11 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
11 Input 1 Bit Muxes := 14
Module FullModeTransceiver_TX_STARTUP_FSM__2
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
8 Bit Registers := 2
7 Bit Registers := 1
5 Bit Registers := 1
1 Bit Registers := 21
+---Muxes :
10 Input 10 Bit Muxes := 1
2 Input 10 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 1 Bit Muxes := 7
10 Input 1 Bit Muxes := 10
Module FullModeTransceiver
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 1
2 Input 8 Bit Adders := 1
+---Registers :
128 Bit Registers := 1
96 Bit Registers := 1
10 Bit Registers := 1
8 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 1 Bit Muxes := 2
Module reset_count
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 1
1 Bit Registers := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 2880 (col length:200)
BRAMs: 2360 (col length: RAMB18 200 RAMB36 100)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3333] propagating constant 0 across sequential element (backplane/i_0/combined_ttc/\ttc_status_reg_reg[6] )
INFO: [Synth 8-3332] Sequential element (register_chan_seq[0].case_i_equal_to_0.rx_chanbond_reg_0) is unused and will be removed from module sume_RO_Rx_GT_FRAME_CHECK.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/btn_samp1_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_4/\bulk_fifo_xoff_counter/above_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_4/\bulk_fifo_xoff_counter/above_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_3/\bulk_fifo_busy_counter/above_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_3/\bulk_fifo_busy_counter/above_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_2/\tob_fifo_xoff_counter/above_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_2/\tob_fifo_xoff_counter/above_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_1/\tob_fifo_busy_counter/above_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/i_1/\tob_fifo_busy_counter/above_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/start_seq_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/rx_btn_reset_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/i_2/\gen_reg.ttc_regs/ttc_fifo_busy_counter/above_counter_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/i_2/\gen_reg.ttc_regs/ttc_fifo_busy_counter/above_counter_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\clock_status/rsync/m_q_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\clock_status/rsync/m_q_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/CTTC_link_stat_reg/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\clock_status/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/CTTC_link_stat_reg/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\clock_status/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/CTTC_link_stat_reg/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\clock_status/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[10] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_pwr_dnb_buf) is unused and will be removed from module aurora_64b_rx_12ch.
WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ref_ck_sel_buf) is unused and will be removed from module aurora_64b_rx_12ch.
WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_syncb_buf) is unused and will be removed from module aurora_64b_rx_12ch.
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[3].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[4].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[5].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[6].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[14]) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[12]) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[9]) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[15].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[14].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[13].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[12].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[11].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[10].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[9].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[8].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[7].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[6].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[5].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[0].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[1].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0.
INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SCL_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_iic__1.
INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SCL_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_iic__1.
INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SDA_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_iic__1.
INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SDA_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_iic__1.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3332] Sequential element (wrouter_aw_fifo/FSM_onehot_state_reg[2]) is unused and will be removed from module axi_crossbar_v2_1_21_wdata_router__1.
INFO: [Synth 8-3332] Sequential element (wrouter_aw_fifo/FSM_onehot_state_reg[2]) is unused and will be removed from module axi_crossbar_v2_1_21_wdata_router.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__1.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__2.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__3.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__4.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__5.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__6.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0.
INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1.
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
WARNING: [Synth 8-3917] design ROD_system__GC0 has port AXI_WSTRB[3] driven by constant 1
WARNING: [Synth 8-3917] design ROD_system__GC0 has port AXI_WSTRB[2] driven by constant 1
WARNING: [Synth 8-3917] design ROD_system__GC0 has port AXI_WSTRB[1] driven by constant 1
WARNING: [Synth 8-3917] design ROD_system__GC0 has port AXI_WSTRB[0] driven by constant 1
WARNING: [Synth 8-3917] design ROD_system__GC0 has port AXI_BREADY[0] driven by constant 1
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (reset_sync1_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (reset_sync2_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (reset_sync1_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (reset_sync2_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM.
WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:07:44 ; elapsed = 00:10:03 . Memory (MB): peak = 3278.914 ; gain = 822.191 ; free physical = 3395 ; free virtual = 16710
---------------------------------------------------------------------------------
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Preliminary Mapping Report (see note below)
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 |
|axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 |
|\ipbus/ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
|jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64X1D x 8 RAM64M x 40 |
|axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 |
|axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+------+-----------------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+-----------------------------------+------------+----------+
|1 |axi4_subsys__GB0 | 1| 24045|
|2 |axi4_subsys__GB1 | 1| 8002|
|3 |ROD_system__GC0 | 1| 15751|
|4 |rod_RO_Tx_exdes__GC0 | 1| 59|
|5 |aurora_64b_rx_12ch__GC0 | 1| 4231|
|6 |fex_chan_regs | 5| 4573|
|7 |channel_fifo__GC0 | 1| 1322|
|8 |channel_fifo__parameterized1__GC0 | 1| 1322|
|9 |channel_fifo__parameterized3__GC0 | 1| 1322|
|10 |channel_fifo__parameterized5__GC0 | 1| 1244|
|11 |channel_fifo__parameterized7__GC0 | 1| 1244|
|12 |channel_fifo__parameterized9__GC0 | 1| 1242|
|13 |channel_fifo__parameterized11__GC0 | 1| 1244|
|14 |channel_fifo__parameterized13__GC0 | 1| 1244|
|15 |channel_fifo__parameterized15__GC0 | 1| 1242|
|16 |channel_fifo__parameterized17__GC0 | 1| 1242|
|17 |channel_fifo__parameterized19__GC0 | 1| 1242|
|18 |channel_fifo__parameterized21__GC0 | 1| 1242|
|19 |input_fifos__GC0 | 1| 4446|
|20 |tob_processor | 1| 12536|
|21 |packet_processor__GCB1 | 1| 10812|
|22 |packet_processor__GCB2 | 1| 1077|
|23 |packet_processor__GCB3 | 1| 6479|
|24 |top_rod_efex__GC0 | 1| 9713|
|25 |fex_chan_regs__1 | 2| 4727|
|26 |fex_chan_regs__2 | 1| 4489|
|27 |fex_chan_regs__3 | 4| 4182|
+------+-----------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_3' to pin 'aurora_3/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_4' to pin 'aurora_4/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_5' to pin 'aurora_5/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_6' to pin 'aurora_6/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_7' to pin 'aurora_7/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_8' to pin 'aurora_8/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_9' to pin 'aurora_9/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_10' to pin 'aurora_10/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_11' to pin 'aurora_11/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_12' to pin 'aurora_12/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_13' to pin 'aurora_13/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_14' to pin 'aurora_14/aurora_module_i/clock_module_i/user_clk_buf_i/O'
INFO: [Synth 8-5819] Moved 12 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:08:01 ; elapsed = 00:10:28 . Memory (MB): peak = 3278.914 ; gain = 822.191 ; free physical = 3091 ; free virtual = 16542
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:08:21 ; elapsed = 00:10:49 . Memory (MB): peak = 3278.914 ; gain = 822.191 ; free physical = 2827 ; free virtual = 16321
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 |
|axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 |
|\ipbus/ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
|\ipbus/ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
|jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64X1D x 8 RAM64M x 40 |
|axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 |
|axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Report RTL Partitions:
+------+-----------------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+-----------------------------------+------------+----------+
|1 |axi4_subsys__GB0 | 1| 24045|
|2 |axi4_subsys__GB1 | 1| 8002|
|3 |ROD_system__GC0 | 1| 15748|
|4 |rod_RO_Tx_exdes__GC0 | 1| 59|
|5 |aurora_64b_rx_12ch__GC0 | 1| 4231|
|6 |fex_chan_regs | 5| 4573|
|7 |channel_fifo__GC0 | 1| 1322|
|8 |channel_fifo__parameterized1__GC0 | 1| 1322|
|9 |channel_fifo__parameterized3__GC0 | 1| 1322|
|10 |channel_fifo__parameterized5__GC0 | 1| 1244|
|11 |channel_fifo__parameterized7__GC0 | 1| 1244|
|12 |channel_fifo__parameterized9__GC0 | 1| 1242|
|13 |channel_fifo__parameterized11__GC0 | 1| 1244|
|14 |channel_fifo__parameterized13__GC0 | 1| 1244|
|15 |channel_fifo__parameterized15__GC0 | 1| 1242|
|16 |channel_fifo__parameterized17__GC0 | 1| 1242|
|17 |channel_fifo__parameterized19__GC0 | 1| 1242|
|18 |channel_fifo__parameterized21__GC0 | 1| 1242|
|19 |input_fifos__GC0 | 1| 4446|
|20 |tob_processor | 1| 10868|
|21 |packet_processor__GCB1 | 1| 9764|
|22 |packet_processor__GCB2 | 1| 1077|
|23 |packet_processor__GCB3 | 1| 5869|
|24 |top_rod_efex__GC0 | 1| 9713|
|25 |fex_chan_regs__1 | 2| 4727|
|26 |fex_chan_regs__2 | 1| 4489|
|27 |fex_chan_regs__3 | 4| 4182|
+------+-----------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_1/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_1/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blki_1/ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:09:01 ; elapsed = 00:11:38 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2542 ; free virtual = 16052
---------------------------------------------------------------------------------
Report RTL Partitions:
+------+-----------------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+-----------------------------------+------------+----------+
|1 |axi4_subsys__GB0 | 1| 14226|
|2 |axi4_subsys__GB1 | 1| 4860|
|3 |ROD_system__GC0 | 1| 8448|
|4 |rod_RO_Tx_exdes__GC0 | 1| 59|
|5 |aurora_64b_rx_12ch__GC0 | 1| 3776|
|6 |fex_chan_regs | 1| 2823|
|7 |channel_fifo__GC0 | 1| 910|
|8 |channel_fifo__parameterized1__GC0 | 1| 910|
|9 |channel_fifo__parameterized3__GC0 | 1| 910|
|10 |channel_fifo__parameterized5__GC0 | 1| 829|
|11 |channel_fifo__parameterized7__GC0 | 1| 829|
|12 |channel_fifo__parameterized9__GC0 | 1| 828|
|13 |channel_fifo__parameterized11__GC0 | 1| 829|
|14 |channel_fifo__parameterized13__GC0 | 1| 829|
|15 |channel_fifo__parameterized15__GC0 | 1| 828|
|16 |channel_fifo__parameterized17__GC0 | 1| 828|
|17 |channel_fifo__parameterized19__GC0 | 1| 828|
|18 |channel_fifo__parameterized21__GC0 | 1| 828|
|19 |input_fifos__GC0 | 1| 1866|
|20 |tob_processor | 1| 5092|
|21 |packet_processor__GCB1 | 1| 4702|
|22 |packet_processor__GCB2 | 1| 427|
|23 |packet_processor__GCB3 | 1| 2868|
|24 |top_rod_efex__GC0 | 1| 6391|
|25 |fex_chan_regs__1 | 1| 2828|
|26 |fex_chan_regs__2 | 1| 2747|
|27 |fex_chan_regs__3 | 1| 2752|
|28 |fex_chan_regs__4 | 1| 2823|
|29 |fex_chan_regs__5 | 1| 2823|
|30 |fex_chan_regs__6 | 1| 2823|
|31 |fex_chan_regs__7 | 1| 2823|
|32 |fex_chan_regs__8 | 1| 2828|
|33 |fex_chan_regs__9 | 1| 2752|
|34 |fex_chan_regs__10 | 1| 2752|
|35 |fex_chan_regs__11 | 1| 2752|
+------+-----------------------------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[15] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[14] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[13] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[12] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[11] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[10] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[9] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[8] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[7] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[6] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[5] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[4] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[3] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[2] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[1] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[0] to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg_reg to handle IOB=TRUE attribute
INFO: [Synth 8-5365] Flop reset_reg_reg is being inverted and renamed to reset_reg_reg_inv.
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_write] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [0] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [1] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [2] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [3] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [4] because some of its loads are not in same hierarchy as its driver
INFO: [Synth 8-5777] Ignored max_fanout on net ipb_rst because some of its loads are not in same hierarchy as its driver
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff3_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff3_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[36] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[35] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[34] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[33] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[32] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[31] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[30] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[29] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[28] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[27] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[26] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[25] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[24] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[23] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[22] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[21] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[20] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[19] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[18] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[17] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[16] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[15] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[14] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[13] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[12] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[11] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[10] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[9] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[8] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[7] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[6] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[5] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[4] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[3] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[2] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[1] to constant 0
WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[0] to constant 0
WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt0_cpllrefclklost_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt0_cpllreset_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r2_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[7] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[6] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[5] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[4] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[3] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[2] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[1] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[0] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/gt_reset_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_vio_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/gtreset_vio_i_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[63] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[62] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[61] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[60] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[59] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[58] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[57] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[56] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[55] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[54] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[53] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[52] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[51] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[50] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[49] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[48] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[47] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[46] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[45] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[44] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[43] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[42] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[41] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[40] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[39] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[38] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[37] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[36] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[35] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[34] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[33] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[32] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[31] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[30] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[29] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[28] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[27] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[26] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[25] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[24] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[23] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[22] to constant 0
WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[21] to constant 0
INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385]
WARNING: [Synth 8-5410] Found another clock driver \ipbus_blk/clkin1_buf :O [/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:1004]
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:09:22 ; elapsed = 00:12:01 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2477 ; free virtual = 16058
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:09:23 ; elapsed = 00:12:02 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2477 ; free virtual = 16057
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:29 ; elapsed = 00:12:08 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2450 ; free virtual = 16031
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:09:30 ; elapsed = 00:12:09 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2449 ; free virtual = 16030
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:09:31 ; elapsed = 00:12:10 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2433 ; free virtual = 16014
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:09:32 ; elapsed = 00:12:11 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2429 ; free virtual = 16010
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+--------------------+--------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+--------------------+--------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|FullModeTransceiver | cpllpd_wait_reg[95] | 96 | 2 | NO | NO | YES | 0 | 6 |
|FullModeTransceiver | cpllreset_wait_reg[127] | 128 | 2 | NO | NO | YES | 0 | 8 |
|top_rod_efex | ipbus_blk/ipbus/trimac_fifo_block/axi_lite_controller/count_shift_reg[20] | 21 | 1 | NO | NO | YES | 0 | 1 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/IPADDR/pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/resend/pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[37]__0 | 23 | 1 | YES | NO | YES | 0 | 1 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[13]__0 | 12 | 1 | YES | NO | YES | 1 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[27]__1 | 6 | 4 | YES | NO | YES | 4 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[11]__1 | 8 | 1 | YES | NO | YES | 1 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[41] | 12 | 1 | YES | NO | YES | 1 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[19] | 16 | 1 | YES | NO | YES | 1 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[35]__0 | 23 | 1 | YES | NO | YES | 0 | 1 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[11]__0 | 10 | 2 | YES | NO | YES | 2 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/pkt_mask_reg[9]__2 | 10 | 1 | YES | NO | YES | 1 | 0 |
|top_rod_efex | ipbus_blk/ipbus/ipbus/udp_if/rx_packet_parser/primary_mode.pkt_data_reg[111] | 10 | 4 | YES | NO | YES | 4 | 0 |
+--------------------+--------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Dynamic Shift Register Report:
+------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | INFERRED_GEN.data_reg[255] | 33 | 33 | 0 | 264 | 132 | 66 | 0 |
|dsrl__1 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 |
|dsrl__2 | memory_reg[31] | 3 | 3 | 0 | 3 | 0 | 0 | 0 |
+------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+------+-----------------------+----------+
| |BlackBox name |Instances |
+------+-----------------------+----------+
|1 |MGT_combined_ttc_rx | 1|
|2 |vio_ttc | 1|
|3 |ila_2 | 1|
|4 |aurora_rx_4l_64b | 6|
|5 |aurora_rx_1q | 6|
|6 |rod_RO_Tx | 1|
|7 |vio_0 | 1|
|8 |ila_1 | 1|
|9 |vio_RO_CTL_test | 1|
|10 |axis_input_fifo | 6|
|11 |aurora_fifo_in_ila | 7|
|12 |aurora_fifo_out_ila | 14|
|13 |data_fifo_vio | 7|
|14 |clock_cross_fifo | 18|
|15 |chan_map_ila | 1|
|16 |bulk_ila | 3|
|17 |bulk_data_fifo | 3|
|18 |rod_ROctrl_mux_ila | 1|
|19 |ttc_header_fifo | 2|
|20 |ila_bulk_ttc | 1|
|21 |ila_ttc_in | 1|
|22 |ila_ttc_out | 1|
|23 |event_builder_fifo | 2|
|24 |event_fifo_ila | 1|
|25 |ppmux_ila | 1|
|26 |fifo1KB_34bit | 4|
|27 |DPram_32b | 4|
|28 |vio_fullmode_reset | 4|
|29 |fm_status_fifo | 4|
|30 |ila_fullmode | 4|
|31 |ila_mgtfsm | 2|
|32 |clk_wiz_240 | 2|
|33 |axis_dwidth_64_32 | 4|
|34 |axis_data_fifo_0 | 4|
|35 |ila_fifo | 4|
|36 |packet_processor_clock | 1|
|37 |vio_top | 1|
|38 |axi_ch0 | 2|
|39 |pp_ctrl_vio | 1|
|40 |backplane_control_ila | 1|
|41 |rgmii_rx_fifo_2 | 1|
|42 |ethernet_mac_rgmii | 1|
+------+-----------------------+----------+
Report Cell Usage:
+------+-------------------------------+------+
| |Cell |Count |
+------+-------------------------------+------+
|1 |DPram_32b_bbox_136 | 1|
|2 |DPram_32b_bbox_136__4 | 1|
|3 |DPram_32b_bbox_136__5 | 1|
|4 |DPram_32b_bbox_136__6 | 1|
|5 |MGT_combined_ttc_rx_bbox_62 | 1|
|6 |aurora_fifo_in_ila_bbox_103 | 1|
|7 |aurora_fifo_in_ila_bbox_109 | 1|
|8 |aurora_fifo_in_ila_bbox_71 | 1|
|9 |aurora_fifo_in_ila_bbox_77 | 1|
|10 |aurora_fifo_in_ila_bbox_83 | 1|
|11 |aurora_fifo_in_ila_bbox_89 | 1|
|12 |aurora_fifo_in_ila_bbox_95 | 1|
|13 |aurora_fifo_out_ila_bbox_104 | 1|
|14 |aurora_fifo_out_ila_bbox_105 | 1|
|15 |aurora_fifo_out_ila_bbox_110 | 1|
|16 |aurora_fifo_out_ila_bbox_111 | 1|
|17 |aurora_fifo_out_ila_bbox_72 | 1|
|18 |aurora_fifo_out_ila_bbox_73 | 1|
|19 |aurora_fifo_out_ila_bbox_78 | 1|
|20 |aurora_fifo_out_ila_bbox_79 | 1|
|21 |aurora_fifo_out_ila_bbox_84 | 1|
|22 |aurora_fifo_out_ila_bbox_85 | 1|
|23 |aurora_fifo_out_ila_bbox_90 | 1|
|24 |aurora_fifo_out_ila_bbox_91 | 1|
|25 |aurora_fifo_out_ila_bbox_96 | 1|
|26 |aurora_fifo_out_ila_bbox_97 | 1|
|27 |aurora_rx_1q_bbox_55 | 1|
|28 |aurora_rx_1q_bbox_55__10 | 1|
|29 |aurora_rx_1q_bbox_55__6 | 1|
|30 |aurora_rx_1q_bbox_55__7 | 1|
|31 |aurora_rx_1q_bbox_55__8 | 1|
|32 |aurora_rx_1q_bbox_55__9 | 1|
|33 |aurora_rx_4l_64b_bbox_56 | 1|
|34 |aurora_rx_4l_64b_bbox_56__5 | 1|
|35 |aurora_rx_4l_64b_bbox_56__6 | 1|
|36 |aurora_rx_4l_64b_bbox_56__7 | 1|
|37 |aurora_rx_4l_64b_bbox_56__8 | 1|
|38 |aurora_rx_4l_64b_bbox_57 | 1|
|39 |axi_ch0_bbox_65 | 1|
|40 |axi_ch0_bbox_66 | 1|
|41 |axis_data_fifo_0_bbox_141 | 1|
|42 |axis_data_fifo_0_bbox_141__4 | 1|
|43 |axis_data_fifo_0_bbox_141__5 | 1|
|44 |axis_data_fifo_0_bbox_141__6 | 1|
|45 |axis_dwidth_64_32_bbox_140 | 1|
|46 |axis_dwidth_64_32_bbox_140__4 | 1|
|47 |axis_dwidth_64_32_bbox_140__5 | 1|
|48 |axis_dwidth_64_32_bbox_140__6 | 1|
|49 |axis_input_fifo_bbox_69 | 1|
|50 |axis_input_fifo_bbox_70 | 1|
|51 |axis_input_fifo_bbox_75 | 1|
|52 |axis_input_fifo_bbox_76 | 1|
|53 |axis_input_fifo_bbox_81 | 1|
|54 |axis_input_fifo_bbox_82 | 1|
|55 |backplane_control_ila_bbox_143 | 1|
|56 |bulk_data_fifo_bbox_131 | 1|
|57 |bulk_data_fifo_bbox_131__3 | 1|
|58 |bulk_data_fifo_bbox_131__4 | 1|
|59 |bulk_ila_bbox_130 | 1|
|60 |bulk_ila_bbox_130__3 | 1|
|61 |bulk_ila_bbox_130__4 | 1|
|62 |chan_map_ila_bbox_68 | 1|
|63 |clk_wiz_240_bbox_133 | 1|
|64 |clk_wiz_240_bbox_133__2 | 1|
|65 |clock_cross_fifo_bbox_100 | 1|
|66 |clock_cross_fifo_bbox_101 | 1|
|67 |clock_cross_fifo_bbox_102 | 1|
|68 |clock_cross_fifo_bbox_107 | 1|
|69 |clock_cross_fifo_bbox_108 | 1|
|70 |clock_cross_fifo_bbox_113 | 1|
|71 |clock_cross_fifo_bbox_114 | 1|
|72 |clock_cross_fifo_bbox_115 | 1|
|73 |clock_cross_fifo_bbox_116 | 1|
|74 |clock_cross_fifo_bbox_117 | 1|
|75 |clock_cross_fifo_bbox_118 | 1|
|76 |clock_cross_fifo_bbox_119 | 1|
|77 |clock_cross_fifo_bbox_120 | 1|
|78 |clock_cross_fifo_bbox_87 | 1|
|79 |clock_cross_fifo_bbox_88 | 1|
|80 |clock_cross_fifo_bbox_93 | 1|
|81 |clock_cross_fifo_bbox_94 | 1|
|82 |clock_cross_fifo_bbox_99 | 1|
|83 |data_fifo_vio_bbox_106 | 1|
|84 |data_fifo_vio_bbox_112 | 1|
|85 |data_fifo_vio_bbox_74 | 1|
|86 |data_fifo_vio_bbox_80 | 1|
|87 |data_fifo_vio_bbox_86 | 1|
|88 |data_fifo_vio_bbox_92 | 1|
|89 |data_fifo_vio_bbox_98 | 1|
|90 |ethernet_mac_rgmii_bbox_53 | 1|
|91 |event_builder_fifo_bbox_121 | 1|
|92 |event_builder_fifo_bbox_123 | 1|
|93 |event_fifo_ila_bbox_122 | 1|
|94 |fifo1KB_34bit_bbox_134 | 1|
|95 |fifo1KB_34bit_bbox_134__4 | 1|
|96 |fifo1KB_34bit_bbox_134__5 | 1|
|97 |fifo1KB_34bit_bbox_134__6 | 1|
|98 |fm_status_fifo_bbox_137 | 1|
|99 |fm_status_fifo_bbox_137__4 | 1|
|100 |fm_status_fifo_bbox_137__5 | 1|
|101 |fm_status_fifo_bbox_137__6 | 1|
|102 |ila_1_bbox_60 | 1|
|103 |ila_2_bbox_64 | 1|
|104 |ila_bulk_ttc_bbox_127 | 1|
|105 |ila_fifo_bbox_142 | 1|
|106 |ila_fifo_bbox_142__4 | 1|
|107 |ila_fifo_bbox_142__5 | 1|
|108 |ila_fifo_bbox_142__6 | 1|
|109 |ila_fullmode_bbox_138 | 1|
|110 |ila_fullmode_bbox_138__4 | 1|
|111 |ila_fullmode_bbox_138__5 | 1|
|112 |ila_fullmode_bbox_138__6 | 1|
|113 |ila_mgtfsm_bbox_139 | 1|
|114 |ila_mgtfsm_bbox_139__2 | 1|
|115 |ila_ttc_in_bbox_128 | 1|
|116 |ila_ttc_out_bbox_129 | 1|
|117 |packet_processor_clock_bbox_51 | 1|
|118 |pp_ctrl_vio_bbox_67 | 1|
|119 |ppmux_ila_bbox_124 | 1|
|120 |rgmii_rx_fifo_2_bbox_54 | 1|
|121 |rod_RO_Tx_bbox_58 | 1|
|122 |rod_ROctrl_mux_ila_bbox_132 | 1|
|123 |ttc_header_fifo_bbox_125 | 1|
|124 |ttc_header_fifo_bbox_126 | 1|
|125 |vio_0_bbox_59 | 1|
|126 |vio_RO_CTL_test_bbox_61 | 1|
|127 |vio_fullmode_reset_bbox_135 | 1|
|128 |vio_fullmode_reset_bbox_135__4 | 1|
|129 |vio_fullmode_reset_bbox_135__5 | 1|
|130 |vio_fullmode_reset_bbox_135__6 | 1|
|131 |vio_top_bbox_52 | 1|
|132 |vio_ttc_bbox_63 | 1|
|133 |BUFG | 15|
|134 |BUFGCE | 4|
|135 |BUFH | 6|
|136 |CARRY4 | 3282|
|137 |DNA_PORT | 1|
|138 |GTHE2_CHANNEL | 4|
|139 |GTHE2_COMMON | 18|
|140 |IBUFDS_GTE2 | 8|
|141 |ICAPE2 | 1|
|142 |IDELAYCTRL | 1|
|143 |LUT1 | 4032|
|144 |LUT2 | 4703|
|145 |LUT3 | 4431|
|146 |LUT4 | 5604|
|147 |LUT5 | 5444|
|148 |LUT6 | 11096|
|149 |MMCME2_ADV | 1|
|150 |MULT_AND | 27|
|151 |MUXCY | 27|
|152 |MUXCY_L | 18|
|153 |MUXF7 | 1412|
|154 |MUXF8 | 409|
|155 |RAM32M | 12|
|156 |RAM64M | 40|
|157 |RAM64X1D | 8|
|158 |RAMB18E1 | 1|
|159 |RAMB18E1_1 | 2|
|160 |RAMB36E1 | 2|
|161 |RAMB36E1_1 | 1|
|162 |RAMB36E1_2 | 16|
|163 |SRL16 | 2|
|164 |SRL16E | 51|
|165 |SRLC32E | 524|
|166 |STARTUPE2 | 1|
|167 |XADC | 1|
|168 |XORCY | 57|
|169 |FD | 248|
|170 |FDCE | 5367|
|171 |FDPE | 88|
|172 |FDR | 443|
|173 |FDRE | 40637|
|174 |FDSE | 1620|
|175 |IBUF | 130|
|176 |IBUFDS | 1|
|177 |IBUFG | 1|
|178 |IOBUF | 24|
|179 |OBUF | 50|
|180 |OBUFT | 1|
+------+-------------------------------+------+
Report Instance Areas:
+------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------+------+
| |Instance |Module |Cells |
+------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------+------+
|1 |top | | 97656|
|2 | backplane |aurora_64b_rx_12ch | 4862|
|3 | combined_ttc |combined_ttc_rx | 454|
|4 | sume_RO_Rx_support_i |sume_RO_Rx_support | 92|
|5 | gt_usrclk_source |sume_RO_Rx_GT_USRCLK_SOURCE | 1|
|6 | gt0_frame_check |sume_RO_Rx_GT_FRAME_CHECK | 208|
|7 | inst_regs |rx_registers | 137|
|8 | aurora_10 |aurora_rx_4l_64b_exdes__parameterized2 | 351|
|9 | aurora_module_i |aurora_rx_4l_64b_support__parameterized1 | 253|
|10 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_1375 | 1|
|11 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1376 | 20|
|12 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_1377 | 8|
|13 | aurora_11 |aurora_rx_1q_exdes__xdcDup__5 | 351|
|14 | aurora_module_i |aurora_rx_1q_support__xdcDup__5 | 253|
|15 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_1371 | 1|
|16 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_1372 | 20|
|17 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_1374 | 8|
|18 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_1373 | 1|
|19 | aurora_12 |aurora_rx_4l_64b_exdes__xdcDup__4 | 353|
|20 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__4 | 255|
|21 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_1367 | 1|
|22 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1368 | 20|
|23 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_1370 | 8|
|24 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_1369 | 2|
|25 | aurora_13 |aurora_rx_1q_exdes | 351|
|26 | aurora_module_i |aurora_rx_1q_support | 253|
|27 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_1363 | 1|
|28 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_1364 | 20|
|29 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_1366 | 8|
|30 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_1365 | 1|
|31 | aurora_14 |aurora_rx_4l_64b_exdes | 353|
|32 | aurora_module_i |aurora_rx_4l_64b_support | 255|
|33 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_1359 | 1|
|34 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1360 | 20|
|35 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_1362 | 8|
|36 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_1361 | 2|
|37 | aurora_3 |aurora_rx_1q_exdes__xdcDup__1 | 359|
|38 | aurora_module_i |aurora_rx_1q_support__xdcDup__1 | 253|
|39 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_1355 | 1|
|40 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_1356 | 20|
|41 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_1358 | 8|
|42 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_1357 | 1|
|43 | aurora_4 |aurora_rx_4l_64b_exdes__xdcDup__1 | 353|
|44 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__1 | 255|
|45 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_1351 | 1|
|46 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1352 | 20|
|47 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_1354 | 8|
|48 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_1353 | 2|
|49 | aurora_5 |aurora_rx_1q_exdes__xdcDup__2 | 359|
|50 | aurora_module_i |aurora_rx_1q_support__xdcDup__2 | 253|
|51 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_1347 | 1|
|52 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_1348 | 20|
|53 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_1350 | 8|
|54 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_1349 | 1|
|55 | aurora_6 |aurora_rx_4l_64b_exdes__xdcDup__2 | 353|
|56 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__2 | 255|
|57 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_1343 | 1|
|58 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_1344 | 20|
|59 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_1346 | 8|
|60 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_1345 | 2|
|61 | aurora_7 |aurora_rx_1q_exdes__xdcDup__3 | 351|
|62 | aurora_module_i |aurora_rx_1q_support__xdcDup__3 | 253|
|63 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_1339 | 1|
|64 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_1340 | 20|
|65 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_1342 | 8|
|66 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_1341 | 1|
|67 | aurora_8 |aurora_rx_4l_64b_exdes__xdcDup__3 | 353|
|68 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__3 | 255|
|69 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE | 1|
|70 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC | 20|
|71 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes | 8|
|72 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper | 2|
|73 | aurora_9 |aurora_rx_1q_exdes__xdcDup__4 | 351|
|74 | aurora_module_i |aurora_rx_1q_support__xdcDup__4 | 253|
|75 | clock_module_i |aurora_rx_1q_CLOCK_MODULE | 1|
|76 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC | 20|
|77 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes | 8|
|78 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper | 1|
|79 | pulse_stretcher |pulse_stretch | 18|
|80 | pwer_on_rst |pwr_on_timer | 81|
|81 | readout_ctrl |rod_RO_Tx_exdes | 63|
|82 | rod_RO_Tx_support_i |rod_RO_Tx_support | 51|
|83 | gt_usrclk_source |rod_RO_Tx_GT_USRCLK_SOURCE | 1|
|84 | event_builder |packet_processor | 59044|
|85 | fifo_layer |input_fifos | 45949|
|86 | ch0 |channel_fifo | 3737|
|87 | \gen_reg.status_regs |fex_chan_regs__4 | 2827|
|88 | Aurora_channel_control_reg |ipbus_reg_v_1277 | 102|
|89 | Aurora_channel_disable_reg |ipbus_reg_v_1278 | 36|
|90 | Aurora_channel_status_reg |ipbus_syncreg_v_1279 | 47|
|91 | rsync |syncreg_r_1338 | 44|
|92 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_1280 | 53|
|93 | rsync |syncreg_r_1337 | 50|
|94 | Aurora_self_reset_count_reg |ipbus_syncreg_v_1281 | 51|
|95 | rsync |syncreg_r_1336 | 48|
|96 | Bulk_fifo_control_reg |ipbus_reg_v_1282 | 35|
|97 | FEX_Busy_timer_reset_reg |ipbus_reg_v_1283 | 41|
|98 | Fex_busy_status_reg |ipbus_syncreg_v_1284 | 28|
|99 | rsync |syncreg_r_1335 | 25|
|100 | Fex_busy_timer_0_reg |ipbus_syncreg_v_1285 | 51|
|101 | rsync |syncreg_r_1334 | 49|
|102 | Fex_busy_timer_1_reg |ipbus_syncreg_v_1286 | 83|
|103 | rsync |syncreg_r_1333 | 80|
|104 | Fex_busy_timer_2_reg |ipbus_syncreg_v_1287 | 50|
|105 | rsync |syncreg_r_1332 | 47|
|106 | Fex_busy_timer_3_reg |ipbus_syncreg_v_1288 | 52|
|107 | rsync |syncreg_r_1331 | 50|
|108 | Fex_busy_timer_4_reg |ipbus_syncreg_v_1289 | 50|
|109 | rsync |syncreg_r_1330 | 47|
|110 | Fex_busy_timer_5_reg |ipbus_syncreg_v_1290 | 138|
|111 | rsync |syncreg_r_1329 | 135|
|112 | Frame_error_counter |error_counter__parameterized0_1291 | 9|
|113 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_1292 | 122|
|114 | rsync |syncreg_r_1328 | 119|
|115 | Tob_fifo_control_reg |ipbus_reg_v_1293 | 66|
|116 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_1294 | 52|
|117 | rsync |syncreg_r_1327 | 50|
|118 | Tob_fifo_reset_reg |ipbus_reg_v_1295 | 36|
|119 | Tob_fifo_status_reg |ipbus_syncreg_v_1296 | 61|
|120 | rsync |syncreg_r_1326 | 58|
|121 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_1297 | 78|
|122 | rsync |syncreg_r_1325 | 75|
|123 | UFC_Busy_control_reg |ipbus_reg_v_1298 | 34|
|124 | UFC_msg_crc_error_reg |ipbus_syncreg_v_1299 | 93|
|125 | rsync |syncreg_r_1324 | 90|
|126 | aurora_reset_pulse |pulse_stretch__parameterized5_1300 | 14|
|127 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_1301 | 51|
|128 | rsync |syncreg_r_1323 | 49|
|129 | bulk_fifo_busy_counter |threshold_counter_1302 | 111|
|130 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_1303 | 80|
|131 | rsync |syncreg_r_1322 | 78|
|132 | bulk_fifo_reset_reg |ipbus_reg_v_1304 | 38|
|133 | bulk_fifo_status_reg |ipbus_syncreg_v_1305 | 64|
|134 | rsync |syncreg_r_1321 | 61|
|135 | bulk_fifo_watermark |watermark_1306 | 34|
|136 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_1307 | 50|
|137 | rsync |syncreg_r_1320 | 48|
|138 | bulk_fifo_xoff_counter |threshold_counter_1308 | 110|
|139 | chan_len_err_counter |edge_error_counter_1309 | 10|
|140 | chan_reset |channel_init_1310 | 249|
|141 | reset_timer |aurora_reset_1317 | 113|
|142 | self_reset_inst |self_reset_1318 | 121|
|143 | stretcher |pulse_stretch__parameterized5_1319 | 15|
|144 | hard_error_counter |error_counter__parameterized0_1311 | 9|
|145 | header_crc_err_counter |error_counter__parameterized0_1312 | 9|
|146 | soft_error_counter |error_counter__parameterized0_1313 | 9|
|147 | tob_fifo_busy_counter |threshold_counter_1314 | 110|
|148 | tob_fifo_watermark |watermark_1315 | 34|
|149 | tob_fifo_xoff_counter |threshold_counter_1316 | 110|
|150 | pulse_stretcher |pulse_stretch__parameterized1__3 | 22|
|151 | input_pipe |aurora_pipe | 510|
|152 | crc_gen |CRC_1275 | 98|
|153 | pulse_stretcher |pulse_stretch__parameterized3_1276 | 15|
|154 | ufc_receiver |ufc_rx__1 | 91|
|155 | ch1 |channel_fifo__parameterized1 | 3737|
|156 | \gen_reg.status_regs |fex_chan_regs__5 | 2827|
|157 | Aurora_channel_control_reg |ipbus_reg_v_1213 | 102|
|158 | Aurora_channel_disable_reg |ipbus_reg_v_1214 | 36|
|159 | Aurora_channel_status_reg |ipbus_syncreg_v_1215 | 47|
|160 | rsync |syncreg_r_1274 | 44|
|161 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_1216 | 53|
|162 | rsync |syncreg_r_1273 | 50|
|163 | Aurora_self_reset_count_reg |ipbus_syncreg_v_1217 | 51|
|164 | rsync |syncreg_r_1272 | 48|
|165 | Bulk_fifo_control_reg |ipbus_reg_v_1218 | 35|
|166 | FEX_Busy_timer_reset_reg |ipbus_reg_v_1219 | 41|
|167 | Fex_busy_status_reg |ipbus_syncreg_v_1220 | 28|
|168 | rsync |syncreg_r_1271 | 25|
|169 | Fex_busy_timer_0_reg |ipbus_syncreg_v_1221 | 51|
|170 | rsync |syncreg_r_1270 | 49|
|171 | Fex_busy_timer_1_reg |ipbus_syncreg_v_1222 | 83|
|172 | rsync |syncreg_r_1269 | 80|
|173 | Fex_busy_timer_2_reg |ipbus_syncreg_v_1223 | 50|
|174 | rsync |syncreg_r_1268 | 47|
|175 | Fex_busy_timer_3_reg |ipbus_syncreg_v_1224 | 52|
|176 | rsync |syncreg_r_1267 | 50|
|177 | Fex_busy_timer_4_reg |ipbus_syncreg_v_1225 | 50|
|178 | rsync |syncreg_r_1266 | 47|
|179 | Fex_busy_timer_5_reg |ipbus_syncreg_v_1226 | 138|
|180 | rsync |syncreg_r_1265 | 135|
|181 | Frame_error_counter |error_counter__parameterized0_1227 | 9|
|182 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_1228 | 122|
|183 | rsync |syncreg_r_1264 | 119|
|184 | Tob_fifo_control_reg |ipbus_reg_v_1229 | 66|
|185 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_1230 | 52|
|186 | rsync |syncreg_r_1263 | 50|
|187 | Tob_fifo_reset_reg |ipbus_reg_v_1231 | 36|
|188 | Tob_fifo_status_reg |ipbus_syncreg_v_1232 | 61|
|189 | rsync |syncreg_r_1262 | 58|
|190 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_1233 | 78|
|191 | rsync |syncreg_r_1261 | 75|
|192 | UFC_Busy_control_reg |ipbus_reg_v_1234 | 34|
|193 | UFC_msg_crc_error_reg |ipbus_syncreg_v_1235 | 93|
|194 | rsync |syncreg_r_1260 | 90|
|195 | aurora_reset_pulse |pulse_stretch__parameterized5_1236 | 14|
|196 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_1237 | 51|
|197 | rsync |syncreg_r_1259 | 49|
|198 | bulk_fifo_busy_counter |threshold_counter_1238 | 111|
|199 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_1239 | 80|
|200 | rsync |syncreg_r_1258 | 78|
|201 | bulk_fifo_reset_reg |ipbus_reg_v_1240 | 38|
|202 | bulk_fifo_status_reg |ipbus_syncreg_v_1241 | 64|
|203 | rsync |syncreg_r_1257 | 61|
|204 | bulk_fifo_watermark |watermark_1242 | 34|
|205 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_1243 | 50|
|206 | rsync |syncreg_r_1256 | 48|
|207 | bulk_fifo_xoff_counter |threshold_counter_1244 | 110|
|208 | chan_len_err_counter |edge_error_counter_1245 | 10|
|209 | chan_reset |channel_init_1246 | 249|
|210 | reset_timer |aurora_reset_1253 | 113|
|211 | self_reset_inst |self_reset_1254 | 121|
|212 | stretcher |pulse_stretch__parameterized5_1255 | 15|
|213 | hard_error_counter |error_counter__parameterized0_1247 | 9|
|214 | header_crc_err_counter |error_counter__parameterized0_1248 | 9|
|215 | soft_error_counter |error_counter__parameterized0_1249 | 9|
|216 | tob_fifo_busy_counter |threshold_counter_1250 | 110|
|217 | tob_fifo_watermark |watermark_1251 | 34|
|218 | tob_fifo_xoff_counter |threshold_counter_1252 | 110|
|219 | pulse_stretcher |pulse_stretch__parameterized1__4 | 22|
|220 | input_pipe |aurora_pipe__parameterized1 | 510|
|221 | crc_gen |CRC_1211 | 98|
|222 | pulse_stretcher |pulse_stretch__parameterized3_1212 | 15|
|223 | ufc_receiver |ufc_rx__2 | 91|
|224 | ch2 |channel_fifo__parameterized3 | 3737|
|225 | \gen_reg.status_regs |fex_chan_regs__6 | 2827|
|226 | Aurora_channel_control_reg |ipbus_reg_v_1149 | 102|
|227 | Aurora_channel_disable_reg |ipbus_reg_v_1150 | 36|
|228 | Aurora_channel_status_reg |ipbus_syncreg_v_1151 | 47|
|229 | rsync |syncreg_r_1210 | 44|
|230 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_1152 | 53|
|231 | rsync |syncreg_r_1209 | 50|
|232 | Aurora_self_reset_count_reg |ipbus_syncreg_v_1153 | 51|
|233 | rsync |syncreg_r_1208 | 48|
|234 | Bulk_fifo_control_reg |ipbus_reg_v_1154 | 35|
|235 | FEX_Busy_timer_reset_reg |ipbus_reg_v_1155 | 41|
|236 | Fex_busy_status_reg |ipbus_syncreg_v_1156 | 28|
|237 | rsync |syncreg_r_1207 | 25|
|238 | Fex_busy_timer_0_reg |ipbus_syncreg_v_1157 | 51|
|239 | rsync |syncreg_r_1206 | 49|
|240 | Fex_busy_timer_1_reg |ipbus_syncreg_v_1158 | 83|
|241 | rsync |syncreg_r_1205 | 80|
|242 | Fex_busy_timer_2_reg |ipbus_syncreg_v_1159 | 50|
|243 | rsync |syncreg_r_1204 | 47|
|244 | Fex_busy_timer_3_reg |ipbus_syncreg_v_1160 | 52|
|245 | rsync |syncreg_r_1203 | 50|
|246 | Fex_busy_timer_4_reg |ipbus_syncreg_v_1161 | 50|
|247 | rsync |syncreg_r_1202 | 47|
|248 | Fex_busy_timer_5_reg |ipbus_syncreg_v_1162 | 138|
|249 | rsync |syncreg_r_1201 | 135|
|250 | Frame_error_counter |error_counter__parameterized0_1163 | 9|
|251 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_1164 | 122|
|252 | rsync |syncreg_r_1200 | 119|
|253 | Tob_fifo_control_reg |ipbus_reg_v_1165 | 66|
|254 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_1166 | 52|
|255 | rsync |syncreg_r_1199 | 50|
|256 | Tob_fifo_reset_reg |ipbus_reg_v_1167 | 36|
|257 | Tob_fifo_status_reg |ipbus_syncreg_v_1168 | 61|
|258 | rsync |syncreg_r_1198 | 58|
|259 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_1169 | 78|
|260 | rsync |syncreg_r_1197 | 75|
|261 | UFC_Busy_control_reg |ipbus_reg_v_1170 | 34|
|262 | UFC_msg_crc_error_reg |ipbus_syncreg_v_1171 | 93|
|263 | rsync |syncreg_r_1196 | 90|
|264 | aurora_reset_pulse |pulse_stretch__parameterized5_1172 | 14|
|265 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_1173 | 51|
|266 | rsync |syncreg_r_1195 | 49|
|267 | bulk_fifo_busy_counter |threshold_counter_1174 | 111|
|268 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_1175 | 80|
|269 | rsync |syncreg_r_1194 | 78|
|270 | bulk_fifo_reset_reg |ipbus_reg_v_1176 | 38|
|271 | bulk_fifo_status_reg |ipbus_syncreg_v_1177 | 64|
|272 | rsync |syncreg_r_1193 | 61|
|273 | bulk_fifo_watermark |watermark_1178 | 34|
|274 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_1179 | 50|
|275 | rsync |syncreg_r_1192 | 48|
|276 | bulk_fifo_xoff_counter |threshold_counter_1180 | 110|
|277 | chan_len_err_counter |edge_error_counter_1181 | 10|
|278 | chan_reset |channel_init_1182 | 249|
|279 | reset_timer |aurora_reset_1189 | 113|
|280 | self_reset_inst |self_reset_1190 | 121|
|281 | stretcher |pulse_stretch__parameterized5_1191 | 15|
|282 | hard_error_counter |error_counter__parameterized0_1183 | 9|
|283 | header_crc_err_counter |error_counter__parameterized0_1184 | 9|
|284 | soft_error_counter |error_counter__parameterized0_1185 | 9|
|285 | tob_fifo_busy_counter |threshold_counter_1186 | 110|
|286 | tob_fifo_watermark |watermark_1187 | 34|
|287 | tob_fifo_xoff_counter |threshold_counter_1188 | 110|
|288 | pulse_stretcher |pulse_stretch__parameterized1__5 | 22|
|289 | input_pipe |aurora_pipe__parameterized3 | 510|
|290 | crc_gen |CRC_1147 | 98|
|291 | pulse_stretcher |pulse_stretch__parameterized3_1148 | 15|
|292 | ufc_receiver |ufc_rx__3 | 91|
|293 | ch3 |channel_fifo__parameterized5 | 3740|
|294 | \gen_reg.status_regs |fex_chan_regs__7 | 2827|
|295 | Aurora_channel_control_reg |ipbus_reg_v_1085 | 102|
|296 | Aurora_channel_disable_reg |ipbus_reg_v_1086 | 36|
|297 | Aurora_channel_status_reg |ipbus_syncreg_v_1087 | 47|
|298 | rsync |syncreg_r_1146 | 44|
|299 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_1088 | 53|
|300 | rsync |syncreg_r_1145 | 50|
|301 | Aurora_self_reset_count_reg |ipbus_syncreg_v_1089 | 51|
|302 | rsync |syncreg_r_1144 | 48|
|303 | Bulk_fifo_control_reg |ipbus_reg_v_1090 | 35|
|304 | FEX_Busy_timer_reset_reg |ipbus_reg_v_1091 | 41|
|305 | Fex_busy_status_reg |ipbus_syncreg_v_1092 | 28|
|306 | rsync |syncreg_r_1143 | 25|
|307 | Fex_busy_timer_0_reg |ipbus_syncreg_v_1093 | 51|
|308 | rsync |syncreg_r_1142 | 49|
|309 | Fex_busy_timer_1_reg |ipbus_syncreg_v_1094 | 83|
|310 | rsync |syncreg_r_1141 | 80|
|311 | Fex_busy_timer_2_reg |ipbus_syncreg_v_1095 | 50|
|312 | rsync |syncreg_r_1140 | 47|
|313 | Fex_busy_timer_3_reg |ipbus_syncreg_v_1096 | 52|
|314 | rsync |syncreg_r_1139 | 50|
|315 | Fex_busy_timer_4_reg |ipbus_syncreg_v_1097 | 50|
|316 | rsync |syncreg_r_1138 | 47|
|317 | Fex_busy_timer_5_reg |ipbus_syncreg_v_1098 | 138|
|318 | rsync |syncreg_r_1137 | 135|
|319 | Frame_error_counter |error_counter__parameterized0_1099 | 9|
|320 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_1100 | 122|
|321 | rsync |syncreg_r_1136 | 119|
|322 | Tob_fifo_control_reg |ipbus_reg_v_1101 | 66|
|323 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_1102 | 52|
|324 | rsync |syncreg_r_1135 | 50|
|325 | Tob_fifo_reset_reg |ipbus_reg_v_1103 | 36|
|326 | Tob_fifo_status_reg |ipbus_syncreg_v_1104 | 61|
|327 | rsync |syncreg_r_1134 | 58|
|328 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_1105 | 78|
|329 | rsync |syncreg_r_1133 | 75|
|330 | UFC_Busy_control_reg |ipbus_reg_v_1106 | 34|
|331 | UFC_msg_crc_error_reg |ipbus_syncreg_v_1107 | 93|
|332 | rsync |syncreg_r_1132 | 90|
|333 | aurora_reset_pulse |pulse_stretch__parameterized5_1108 | 14|
|334 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_1109 | 51|
|335 | rsync |syncreg_r_1131 | 49|
|336 | bulk_fifo_busy_counter |threshold_counter_1110 | 111|
|337 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_1111 | 80|
|338 | rsync |syncreg_r_1130 | 78|
|339 | bulk_fifo_reset_reg |ipbus_reg_v_1112 | 38|
|340 | bulk_fifo_status_reg |ipbus_syncreg_v_1113 | 64|
|341 | rsync |syncreg_r_1129 | 61|
|342 | bulk_fifo_watermark |watermark_1114 | 34|
|343 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_1115 | 50|
|344 | rsync |syncreg_r_1128 | 48|
|345 | bulk_fifo_xoff_counter |threshold_counter_1116 | 110|
|346 | chan_len_err_counter |edge_error_counter_1117 | 10|
|347 | chan_reset |channel_init_1118 | 249|
|348 | reset_timer |aurora_reset_1125 | 113|
|349 | self_reset_inst |self_reset_1126 | 121|
|350 | stretcher |pulse_stretch__parameterized5_1127 | 15|
|351 | hard_error_counter |error_counter__parameterized0_1119 | 9|
|352 | header_crc_err_counter |error_counter__parameterized0_1120 | 9|
|353 | soft_error_counter |error_counter__parameterized0_1121 | 9|
|354 | tob_fifo_busy_counter |threshold_counter_1122 | 110|
|355 | tob_fifo_watermark |watermark_1123 | 34|
|356 | tob_fifo_xoff_counter |threshold_counter_1124 | 110|
|357 | pulse_stretcher |pulse_stretch__parameterized1__6 | 22|
|358 | input_pipe |aurora_pipe__parameterized5 | 510|
|359 | crc_gen |CRC_1083 | 98|
|360 | pulse_stretcher |pulse_stretch__parameterized3_1084 | 15|
|361 | ufc_receiver |ufc_rx__4 | 91|
|362 | ch4 |channel_fifo__parameterized7 | 3741|
|363 | \gen_reg.status_regs |fex_chan_regs__8 | 2828|
|364 | Aurora_channel_control_reg |ipbus_reg_v_1021 | 92|
|365 | Aurora_channel_disable_reg |ipbus_reg_v_1022 | 44|
|366 | Aurora_channel_status_reg |ipbus_syncreg_v_1023 | 47|
|367 | rsync |syncreg_r_1082 | 44|
|368 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_1024 | 52|
|369 | rsync |syncreg_r_1081 | 49|
|370 | Aurora_self_reset_count_reg |ipbus_syncreg_v_1025 | 79|
|371 | rsync |syncreg_r_1080 | 76|
|372 | Bulk_fifo_control_reg |ipbus_reg_v_1026 | 35|
|373 | FEX_Busy_timer_reset_reg |ipbus_reg_v_1027 | 65|
|374 | Fex_busy_status_reg |ipbus_syncreg_v_1028 | 25|
|375 | rsync |syncreg_r_1079 | 22|
|376 | Fex_busy_timer_0_reg |ipbus_syncreg_v_1029 | 52|
|377 | rsync |syncreg_r_1078 | 50|
|378 | Fex_busy_timer_1_reg |ipbus_syncreg_v_1030 | 82|
|379 | rsync |syncreg_r_1077 | 80|
|380 | Fex_busy_timer_2_reg |ipbus_syncreg_v_1031 | 54|
|381 | rsync |syncreg_r_1076 | 51|
|382 | Fex_busy_timer_3_reg |ipbus_syncreg_v_1032 | 52|
|383 | rsync |syncreg_r_1075 | 49|
|384 | Fex_busy_timer_4_reg |ipbus_syncreg_v_1033 | 52|
|385 | rsync |syncreg_r_1074 | 49|
|386 | Fex_busy_timer_5_reg |ipbus_syncreg_v_1034 | 89|
|387 | rsync |syncreg_r_1073 | 86|
|388 | Frame_error_counter |error_counter__parameterized0_1035 | 9|
|389 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_1036 | 161|
|390 | rsync |syncreg_r_1072 | 158|
|391 | Tob_fifo_control_reg |ipbus_reg_v_1037 | 39|
|392 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_1038 | 57|
|393 | rsync |syncreg_r_1071 | 54|
|394 | Tob_fifo_reset_reg |ipbus_reg_v_1039 | 64|
|395 | Tob_fifo_status_reg |ipbus_syncreg_v_1040 | 61|
|396 | rsync |syncreg_r_1070 | 58|
|397 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_1041 | 66|
|398 | rsync |syncreg_r_1069 | 63|
|399 | UFC_Busy_control_reg |ipbus_reg_v_1042 | 34|
|400 | UFC_msg_crc_error_reg |ipbus_syncreg_v_1043 | 53|
|401 | rsync |syncreg_r_1068 | 50|
|402 | aurora_reset_pulse |pulse_stretch__parameterized5_1044 | 14|
|403 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_1045 | 50|
|404 | rsync |syncreg_r_1067 | 47|
|405 | bulk_fifo_busy_counter |threshold_counter_1046 | 111|
|406 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_1047 | 82|
|407 | rsync |syncreg_r_1066 | 79|
|408 | bulk_fifo_reset_reg |ipbus_reg_v_1048 | 37|
|409 | bulk_fifo_status_reg |ipbus_syncreg_v_1049 | 64|
|410 | rsync |syncreg_r_1065 | 61|
|411 | bulk_fifo_watermark |watermark_1050 | 34|
|412 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_1051 | 51|
|413 | rsync |syncreg_r_1064 | 48|
|414 | bulk_fifo_xoff_counter |threshold_counter_1052 | 110|
|415 | chan_len_err_counter |edge_error_counter_1053 | 10|
|416 | chan_reset |channel_init_1054 | 252|
|417 | reset_timer |aurora_reset_1061 | 116|
|418 | self_reset_inst |self_reset_1062 | 121|
|419 | stretcher |pulse_stretch__parameterized5_1063 | 15|
|420 | hard_error_counter |error_counter__parameterized0_1055 | 9|
|421 | header_crc_err_counter |error_counter__parameterized0_1056 | 9|
|422 | soft_error_counter |error_counter__parameterized0_1057 | 9|
|423 | tob_fifo_busy_counter |threshold_counter_1058 | 110|
|424 | tob_fifo_watermark |watermark_1059 | 34|
|425 | tob_fifo_xoff_counter |threshold_counter_1060 | 110|
|426 | pulse_stretcher |pulse_stretch__parameterized1__7 | 22|
|427 | input_pipe |aurora_pipe__parameterized7 | 510|
|428 | crc_gen |CRC_1019 | 98|
|429 | pulse_stretcher |pulse_stretch__parameterized3_1020 | 15|
|430 | ufc_receiver |ufc_rx__5 | 91|
|431 | ch6 |channel_fifo__parameterized11 | 3741|
|432 | \gen_reg.status_regs |fex_chan_regs__1 | 2828|
|433 | Aurora_channel_control_reg |ipbus_reg_v_957 | 92|
|434 | Aurora_channel_disable_reg |ipbus_reg_v_958 | 44|
|435 | Aurora_channel_status_reg |ipbus_syncreg_v_959 | 47|
|436 | rsync |syncreg_r_1018 | 44|
|437 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_960 | 52|
|438 | rsync |syncreg_r_1017 | 49|
|439 | Aurora_self_reset_count_reg |ipbus_syncreg_v_961 | 79|
|440 | rsync |syncreg_r_1016 | 76|
|441 | Bulk_fifo_control_reg |ipbus_reg_v_962 | 35|
|442 | FEX_Busy_timer_reset_reg |ipbus_reg_v_963 | 65|
|443 | Fex_busy_status_reg |ipbus_syncreg_v_964 | 25|
|444 | rsync |syncreg_r_1015 | 22|
|445 | Fex_busy_timer_0_reg |ipbus_syncreg_v_965 | 52|
|446 | rsync |syncreg_r_1014 | 50|
|447 | Fex_busy_timer_1_reg |ipbus_syncreg_v_966 | 82|
|448 | rsync |syncreg_r_1013 | 80|
|449 | Fex_busy_timer_2_reg |ipbus_syncreg_v_967 | 54|
|450 | rsync |syncreg_r_1012 | 51|
|451 | Fex_busy_timer_3_reg |ipbus_syncreg_v_968 | 52|
|452 | rsync |syncreg_r_1011 | 49|
|453 | Fex_busy_timer_4_reg |ipbus_syncreg_v_969 | 52|
|454 | rsync |syncreg_r_1010 | 49|
|455 | Fex_busy_timer_5_reg |ipbus_syncreg_v_970 | 89|
|456 | rsync |syncreg_r_1009 | 86|
|457 | Frame_error_counter |error_counter__parameterized0_971 | 9|
|458 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_972 | 161|
|459 | rsync |syncreg_r_1008 | 158|
|460 | Tob_fifo_control_reg |ipbus_reg_v_973 | 39|
|461 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_974 | 57|
|462 | rsync |syncreg_r_1007 | 54|
|463 | Tob_fifo_reset_reg |ipbus_reg_v_975 | 64|
|464 | Tob_fifo_status_reg |ipbus_syncreg_v_976 | 61|
|465 | rsync |syncreg_r_1006 | 58|
|466 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_977 | 66|
|467 | rsync |syncreg_r_1005 | 63|
|468 | UFC_Busy_control_reg |ipbus_reg_v_978 | 34|
|469 | UFC_msg_crc_error_reg |ipbus_syncreg_v_979 | 53|
|470 | rsync |syncreg_r_1004 | 50|
|471 | aurora_reset_pulse |pulse_stretch__parameterized5_980 | 14|
|472 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_981 | 50|
|473 | rsync |syncreg_r_1003 | 47|
|474 | bulk_fifo_busy_counter |threshold_counter_982 | 111|
|475 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_983 | 82|
|476 | rsync |syncreg_r_1002 | 79|
|477 | bulk_fifo_reset_reg |ipbus_reg_v_984 | 37|
|478 | bulk_fifo_status_reg |ipbus_syncreg_v_985 | 64|
|479 | rsync |syncreg_r_1001 | 61|
|480 | bulk_fifo_watermark |watermark_986 | 34|
|481 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_987 | 51|
|482 | rsync |syncreg_r_1000 | 48|
|483 | bulk_fifo_xoff_counter |threshold_counter_988 | 110|
|484 | chan_len_err_counter |edge_error_counter_989 | 10|
|485 | chan_reset |channel_init_990 | 252|
|486 | reset_timer |aurora_reset_997 | 116|
|487 | self_reset_inst |self_reset_998 | 121|
|488 | stretcher |pulse_stretch__parameterized5_999 | 15|
|489 | hard_error_counter |error_counter__parameterized0_991 | 9|
|490 | header_crc_err_counter |error_counter__parameterized0_992 | 9|
|491 | soft_error_counter |error_counter__parameterized0_993 | 9|
|492 | tob_fifo_busy_counter |threshold_counter_994 | 110|
|493 | tob_fifo_watermark |watermark_995 | 34|
|494 | tob_fifo_xoff_counter |threshold_counter_996 | 110|
|495 | pulse_stretcher |pulse_stretch__parameterized1__9 | 22|
|496 | input_pipe |aurora_pipe__parameterized11 | 510|
|497 | crc_gen |CRC_955 | 98|
|498 | pulse_stretcher |pulse_stretch__parameterized3_956 | 15|
|499 | ufc_receiver |ufc_rx__7 | 91|
|500 | ch7 |channel_fifo__parameterized13 | 3740|
|501 | \gen_reg.status_regs |fex_chan_regs | 2827|
|502 | Aurora_channel_control_reg |ipbus_reg_v_893 | 102|
|503 | Aurora_channel_disable_reg |ipbus_reg_v_894 | 36|
|504 | Aurora_channel_status_reg |ipbus_syncreg_v_895 | 47|
|505 | rsync |syncreg_r_954 | 44|
|506 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_896 | 53|
|507 | rsync |syncreg_r_953 | 50|
|508 | Aurora_self_reset_count_reg |ipbus_syncreg_v_897 | 51|
|509 | rsync |syncreg_r_952 | 48|
|510 | Bulk_fifo_control_reg |ipbus_reg_v_898 | 35|
|511 | FEX_Busy_timer_reset_reg |ipbus_reg_v_899 | 41|
|512 | Fex_busy_status_reg |ipbus_syncreg_v_900 | 28|
|513 | rsync |syncreg_r_951 | 25|
|514 | Fex_busy_timer_0_reg |ipbus_syncreg_v_901 | 51|
|515 | rsync |syncreg_r_950 | 49|
|516 | Fex_busy_timer_1_reg |ipbus_syncreg_v_902 | 83|
|517 | rsync |syncreg_r_949 | 80|
|518 | Fex_busy_timer_2_reg |ipbus_syncreg_v_903 | 50|
|519 | rsync |syncreg_r_948 | 47|
|520 | Fex_busy_timer_3_reg |ipbus_syncreg_v_904 | 52|
|521 | rsync |syncreg_r_947 | 50|
|522 | Fex_busy_timer_4_reg |ipbus_syncreg_v_905 | 50|
|523 | rsync |syncreg_r_946 | 47|
|524 | Fex_busy_timer_5_reg |ipbus_syncreg_v_906 | 138|
|525 | rsync |syncreg_r_945 | 135|
|526 | Frame_error_counter |error_counter__parameterized0_907 | 9|
|527 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_908 | 122|
|528 | rsync |syncreg_r_944 | 119|
|529 | Tob_fifo_control_reg |ipbus_reg_v_909 | 66|
|530 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_910 | 52|
|531 | rsync |syncreg_r_943 | 50|
|532 | Tob_fifo_reset_reg |ipbus_reg_v_911 | 36|
|533 | Tob_fifo_status_reg |ipbus_syncreg_v_912 | 61|
|534 | rsync |syncreg_r_942 | 58|
|535 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_913 | 78|
|536 | rsync |syncreg_r_941 | 75|
|537 | UFC_Busy_control_reg |ipbus_reg_v_914 | 34|
|538 | UFC_msg_crc_error_reg |ipbus_syncreg_v_915 | 93|
|539 | rsync |syncreg_r_940 | 90|
|540 | aurora_reset_pulse |pulse_stretch__parameterized5_916 | 14|
|541 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_917 | 51|
|542 | rsync |syncreg_r_939 | 49|
|543 | bulk_fifo_busy_counter |threshold_counter_918 | 111|
|544 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_919 | 80|
|545 | rsync |syncreg_r_938 | 78|
|546 | bulk_fifo_reset_reg |ipbus_reg_v_920 | 38|
|547 | bulk_fifo_status_reg |ipbus_syncreg_v_921 | 64|
|548 | rsync |syncreg_r_937 | 61|
|549 | bulk_fifo_watermark |watermark_922 | 34|
|550 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_923 | 50|
|551 | rsync |syncreg_r_936 | 48|
|552 | bulk_fifo_xoff_counter |threshold_counter_924 | 110|
|553 | chan_len_err_counter |edge_error_counter_925 | 10|
|554 | chan_reset |channel_init_926 | 249|
|555 | reset_timer |aurora_reset_933 | 113|
|556 | self_reset_inst |self_reset_934 | 121|
|557 | stretcher |pulse_stretch__parameterized5_935 | 15|
|558 | hard_error_counter |error_counter__parameterized0_927 | 9|
|559 | header_crc_err_counter |error_counter__parameterized0_928 | 9|
|560 | soft_error_counter |error_counter__parameterized0_929 | 9|
|561 | tob_fifo_busy_counter |threshold_counter_930 | 110|
|562 | tob_fifo_watermark |watermark_931 | 34|
|563 | tob_fifo_xoff_counter |threshold_counter_932 | 110|
|564 | pulse_stretcher |pulse_stretch__parameterized1__10 | 22|
|565 | input_pipe |aurora_pipe__parameterized13 | 510|
|566 | crc_gen |CRC_891 | 98|
|567 | pulse_stretcher |pulse_stretch__parameterized3_892 | 15|
|568 | ufc_receiver |ufc_rx__8 | 91|
|569 | \gen_reg.registers |backplane_regs | 700|
|570 | Bulk_fifo_busy_threshold_reg |ipbus_reg_v_875 | 33|
|571 | Bulk_fifo_xoff_threshold_reg |ipbus_reg_v_876 | 56|
|572 | Time_count_value |ipbus_syncreg_v_877 | 53|
|573 | rsync |syncreg_r_890 | 50|
|574 | Tob_fifo_busy_threshold_reg |ipbus_reg_v_878 | 65|
|575 | Tob_fifo_xoff_threshold_reg |ipbus_reg_v_879 | 33|
|576 | backplane_control_reg |ipbus_reg_v_880 | 64|
|577 | channel_disable |ipbus_reg_v_881 | 106|
|578 | channel_map |ipbus_syncreg_v_882 | 31|
|579 | rsync |syncreg_r_889 | 28|
|580 | clk_tester |clock_test_ipbus | 84|
|581 | clock_status |ipbus_syncreg_v_883 | 53|
|582 | rsync |syncreg_r_888 | 50|
|583 | first_last_chan |ipbus_syncreg_v_884 | 37|
|584 | rsync |syncreg_r_887 | 34|
|585 | first_last_encode |priority_encoder | 10|
|586 | ro_ctrl_status |ipbus_syncreg_v_885 | 28|
|587 | rsync |syncreg_r_886 | 25|
|588 | ch10 |channel_fifo__parameterized19 | 3581|
|589 | \gen_reg.status_regs |fex_chan_regs__11 | 2752|
|590 | Aurora_channel_control_reg |ipbus_reg_v_813 | 39|
|591 | Aurora_channel_disable_reg |ipbus_reg_v_814 | 33|
|592 | Aurora_channel_status_reg |ipbus_syncreg_v_815 | 46|
|593 | rsync |syncreg_r_874 | 44|
|594 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_816 | 84|
|595 | rsync |syncreg_r_873 | 82|
|596 | Aurora_self_reset_count_reg |ipbus_syncreg_v_817 | 51|
|597 | rsync |syncreg_r_872 | 49|
|598 | Bulk_fifo_control_reg |ipbus_reg_v_818 | 36|
|599 | FEX_Busy_timer_reset_reg |ipbus_reg_v_819 | 39|
|600 | Fex_busy_status_reg |ipbus_syncreg_v_820 | 27|
|601 | rsync |syncreg_r_871 | 25|
|602 | Fex_busy_timer_0_reg |ipbus_syncreg_v_821 | 93|
|603 | rsync |syncreg_r_870 | 91|
|604 | Fex_busy_timer_1_reg |ipbus_syncreg_v_822 | 52|
|605 | rsync |syncreg_r_869 | 50|
|606 | Fex_busy_timer_2_reg |ipbus_syncreg_v_823 | 50|
|607 | rsync |syncreg_r_868 | 48|
|608 | Fex_busy_timer_3_reg |ipbus_syncreg_v_824 | 50|
|609 | rsync |syncreg_r_867 | 48|
|610 | Fex_busy_timer_4_reg |ipbus_syncreg_v_825 | 117|
|611 | rsync |syncreg_r_866 | 115|
|612 | Fex_busy_timer_5_reg |ipbus_syncreg_v_826 | 52|
|613 | rsync |syncreg_r_865 | 50|
|614 | Frame_error_counter |error_counter__parameterized0_827 | 9|
|615 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_828 | 52|
|616 | rsync |syncreg_r_864 | 50|
|617 | Tob_fifo_control_reg |ipbus_reg_v_829 | 34|
|618 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_830 | 128|
|619 | rsync |syncreg_r_863 | 126|
|620 | Tob_fifo_reset_reg |ipbus_reg_v_831 | 36|
|621 | Tob_fifo_status_reg |ipbus_syncreg_v_832 | 54|
|622 | rsync |syncreg_r_862 | 52|
|623 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_833 | 55|
|624 | rsync |syncreg_r_861 | 53|
|625 | UFC_Busy_control_reg |ipbus_reg_v_834 | 66|
|626 | UFC_msg_crc_error_reg |ipbus_syncreg_v_835 | 50|
|627 | rsync |syncreg_r_860 | 48|
|628 | aurora_reset_pulse |pulse_stretch__parameterized5_836 | 14|
|629 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_837 | 51|
|630 | rsync |syncreg_r_859 | 49|
|631 | bulk_fifo_busy_counter |threshold_counter_838 | 109|
|632 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_839 | 41|
|633 | rsync |syncreg_r_858 | 39|
|634 | bulk_fifo_reset_reg |ipbus_reg_v_840 | 98|
|635 | bulk_fifo_status_reg |ipbus_syncreg_v_841 | 53|
|636 | rsync |syncreg_r_857 | 51|
|637 | bulk_fifo_watermark |watermark_842 | 25|
|638 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_843 | 95|
|639 | rsync |syncreg_r_856 | 93|
|640 | bulk_fifo_xoff_counter |threshold_counter_844 | 109|
|641 | chan_len_err_counter |edge_error_counter_845 | 10|
|642 | chan_reset |channel_init_846 | 259|
|643 | reset_timer |aurora_reset_853 | 123|
|644 | self_reset_inst |self_reset_854 | 121|
|645 | stretcher |pulse_stretch__parameterized5_855 | 15|
|646 | hard_error_counter |error_counter__parameterized0_847 | 9|
|647 | header_crc_err_counter |error_counter__parameterized0_848 | 9|
|648 | soft_error_counter |error_counter__parameterized0_849 | 9|
|649 | tob_fifo_busy_counter |threshold_counter_850 | 109|
|650 | tob_fifo_watermark |watermark_851 | 25|
|651 | tob_fifo_xoff_counter |threshold_counter_852 | 109|
|652 | pulse_stretcher |pulse_stretch__parameterized1__13 | 22|
|653 | ufc_receiver |ufc_rx__11 | 91|
|654 | input_pipe |aurora_pipe__parameterized19 | 517|
|655 | crc_gen |CRC_811 | 97|
|656 | pulse_stretcher |pulse_stretch__parameterized3_812 | 15|
|657 | ch11 |channel_fifo__parameterized21 | 3583|
|658 | \gen_reg.status_regs |fex_chan_regs__3 | 2752|
|659 | Aurora_channel_control_reg |ipbus_reg_v_749 | 39|
|660 | Aurora_channel_disable_reg |ipbus_reg_v_750 | 33|
|661 | Aurora_channel_status_reg |ipbus_syncreg_v_751 | 46|
|662 | rsync |syncreg_r_810 | 44|
|663 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_752 | 84|
|664 | rsync |syncreg_r_809 | 82|
|665 | Aurora_self_reset_count_reg |ipbus_syncreg_v_753 | 51|
|666 | rsync |syncreg_r_808 | 49|
|667 | Bulk_fifo_control_reg |ipbus_reg_v_754 | 36|
|668 | FEX_Busy_timer_reset_reg |ipbus_reg_v_755 | 39|
|669 | Fex_busy_status_reg |ipbus_syncreg_v_756 | 27|
|670 | rsync |syncreg_r_807 | 25|
|671 | Fex_busy_timer_0_reg |ipbus_syncreg_v_757 | 93|
|672 | rsync |syncreg_r_806 | 91|
|673 | Fex_busy_timer_1_reg |ipbus_syncreg_v_758 | 52|
|674 | rsync |syncreg_r_805 | 50|
|675 | Fex_busy_timer_2_reg |ipbus_syncreg_v_759 | 50|
|676 | rsync |syncreg_r_804 | 48|
|677 | Fex_busy_timer_3_reg |ipbus_syncreg_v_760 | 50|
|678 | rsync |syncreg_r_803 | 48|
|679 | Fex_busy_timer_4_reg |ipbus_syncreg_v_761 | 117|
|680 | rsync |syncreg_r_802 | 115|
|681 | Fex_busy_timer_5_reg |ipbus_syncreg_v_762 | 52|
|682 | rsync |syncreg_r_801 | 50|
|683 | Frame_error_counter |error_counter__parameterized0_763 | 9|
|684 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_764 | 52|
|685 | rsync |syncreg_r_800 | 50|
|686 | Tob_fifo_control_reg |ipbus_reg_v_765 | 34|
|687 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_766 | 128|
|688 | rsync |syncreg_r_799 | 126|
|689 | Tob_fifo_reset_reg |ipbus_reg_v_767 | 36|
|690 | Tob_fifo_status_reg |ipbus_syncreg_v_768 | 54|
|691 | rsync |syncreg_r_798 | 52|
|692 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_769 | 55|
|693 | rsync |syncreg_r_797 | 53|
|694 | UFC_Busy_control_reg |ipbus_reg_v_770 | 66|
|695 | UFC_msg_crc_error_reg |ipbus_syncreg_v_771 | 50|
|696 | rsync |syncreg_r_796 | 48|
|697 | aurora_reset_pulse |pulse_stretch__parameterized5_772 | 14|
|698 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_773 | 51|
|699 | rsync |syncreg_r_795 | 49|
|700 | bulk_fifo_busy_counter |threshold_counter_774 | 109|
|701 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_775 | 41|
|702 | rsync |syncreg_r_794 | 39|
|703 | bulk_fifo_reset_reg |ipbus_reg_v_776 | 98|
|704 | bulk_fifo_status_reg |ipbus_syncreg_v_777 | 53|
|705 | rsync |syncreg_r_793 | 51|
|706 | bulk_fifo_watermark |watermark_778 | 25|
|707 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_779 | 95|
|708 | rsync |syncreg_r_792 | 93|
|709 | bulk_fifo_xoff_counter |threshold_counter_780 | 109|
|710 | chan_len_err_counter |edge_error_counter_781 | 10|
|711 | chan_reset |channel_init_782 | 259|
|712 | reset_timer |aurora_reset_789 | 123|
|713 | self_reset_inst |self_reset_790 | 121|
|714 | stretcher |pulse_stretch__parameterized5_791 | 15|
|715 | hard_error_counter |error_counter__parameterized0_783 | 9|
|716 | header_crc_err_counter |error_counter__parameterized0_784 | 9|
|717 | soft_error_counter |error_counter__parameterized0_785 | 9|
|718 | tob_fifo_busy_counter |threshold_counter_786 | 109|
|719 | tob_fifo_watermark |watermark_787 | 25|
|720 | tob_fifo_xoff_counter |threshold_counter_788 | 109|
|721 | pulse_stretcher |pulse_stretch__parameterized1__14 | 22|
|722 | ufc_receiver |ufc_rx | 91|
|723 | input_pipe |aurora_pipe__parameterized21 | 517|
|724 | crc_gen |CRC_747 | 97|
|725 | pulse_stretcher |pulse_stretch__parameterized3_748 | 15|
|726 | ch5 |channel_fifo__parameterized9 | 3613|
|727 | \gen_reg.status_regs |fex_chan_regs__2 | 2750|
|728 | Aurora_channel_control_reg |ipbus_reg_v_685 | 39|
|729 | Aurora_channel_disable_reg |ipbus_reg_v_686 | 40|
|730 | Aurora_channel_status_reg |ipbus_syncreg_v_687 | 68|
|731 | rsync |syncreg_r_746 | 65|
|732 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_688 | 51|
|733 | rsync |syncreg_r_745 | 48|
|734 | Aurora_self_reset_count_reg |ipbus_syncreg_v_689 | 54|
|735 | rsync |syncreg_r_744 | 51|
|736 | Bulk_fifo_control_reg |ipbus_reg_v_690 | 77|
|737 | FEX_Busy_timer_reset_reg |ipbus_reg_v_691 | 41|
|738 | Fex_busy_status_reg |ipbus_syncreg_v_692 | 31|
|739 | rsync |syncreg_r_743 | 28|
|740 | Fex_busy_timer_0_reg |ipbus_syncreg_v_693 | 91|
|741 | rsync |syncreg_r_742 | 89|
|742 | Fex_busy_timer_1_reg |ipbus_syncreg_v_694 | 52|
|743 | rsync |syncreg_r_741 | 49|
|744 | Fex_busy_timer_2_reg |ipbus_syncreg_v_695 | 52|
|745 | rsync |syncreg_r_740 | 49|
|746 | Fex_busy_timer_3_reg |ipbus_syncreg_v_696 | 80|
|747 | rsync |syncreg_r_739 | 77|
|748 | Fex_busy_timer_4_reg |ipbus_syncreg_v_697 | 56|
|749 | rsync |syncreg_r_738 | 53|
|750 | Fex_busy_timer_5_reg |ipbus_syncreg_v_698 | 50|
|751 | rsync |syncreg_r_737 | 47|
|752 | Frame_error_counter |error_counter__parameterized0_699 | 9|
|753 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_700 | 50|
|754 | rsync |syncreg_r_736 | 47|
|755 | Tob_fifo_control_reg |ipbus_reg_v_701 | 45|
|756 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_702 | 61|
|757 | rsync |syncreg_r_735 | 59|
|758 | Tob_fifo_reset_reg |ipbus_reg_v_703 | 39|
|759 | Tob_fifo_status_reg |ipbus_syncreg_v_704 | 54|
|760 | rsync |syncreg_r_734 | 51|
|761 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_705 | 67|
|762 | rsync |syncreg_r_733 | 64|
|763 | UFC_Busy_control_reg |ipbus_reg_v_706 | 92|
|764 | UFC_msg_crc_error_reg |ipbus_syncreg_v_707 | 114|
|765 | rsync |syncreg_r_732 | 111|
|766 | aurora_reset_pulse |pulse_stretch__parameterized5_708 | 14|
|767 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_709 | 88|
|768 | rsync |syncreg_r_731 | 85|
|769 | bulk_fifo_busy_counter |threshold_counter_710 | 109|
|770 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_711 | 48|
|771 | rsync |syncreg_r_730 | 45|
|772 | bulk_fifo_reset_reg |ipbus_reg_v_712 | 39|
|773 | bulk_fifo_status_reg |ipbus_syncreg_v_713 | 53|
|774 | rsync |syncreg_r_729 | 50|
|775 | bulk_fifo_watermark |watermark_714 | 25|
|776 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_715 | 54|
|777 | rsync |syncreg_r_728 | 52|
|778 | bulk_fifo_xoff_counter |threshold_counter_716 | 108|
|779 | chan_len_err_counter |edge_error_counter_717 | 10|
|780 | chan_reset |channel_init_718 | 252|
|781 | reset_timer |aurora_reset_725 | 116|
|782 | self_reset_inst |self_reset_726 | 121|
|783 | stretcher |pulse_stretch__parameterized5_727 | 15|
|784 | hard_error_counter |error_counter__parameterized0_719 | 9|
|785 | header_crc_err_counter |error_counter__parameterized0_720 | 9|
|786 | soft_error_counter |error_counter__parameterized0_721 | 9|
|787 | tob_fifo_busy_counter |threshold_counter_722 | 108|
|788 | tob_fifo_watermark |watermark_723 | 25|
|789 | tob_fifo_xoff_counter |threshold_counter_724 | 108|
|790 | pulse_stretcher |pulse_stretch__parameterized1__8 | 22|
|791 | ufc_receiver |ufc_rx__6 | 91|
|792 | input_pipe |aurora_pipe__parameterized9 | 517|
|793 | crc_gen |CRC_683 | 97|
|794 | pulse_stretcher |pulse_stretch__parameterized3_684 | 15|
|795 | ch8 |channel_fifo__parameterized15 | 3584|
|796 | \gen_reg.status_regs |fex_chan_regs__9 | 2752|
|797 | Aurora_channel_control_reg |ipbus_reg_v_621 | 39|
|798 | Aurora_channel_disable_reg |ipbus_reg_v_622 | 33|
|799 | Aurora_channel_status_reg |ipbus_syncreg_v_623 | 46|
|800 | rsync |syncreg_r_682 | 44|
|801 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_624 | 84|
|802 | rsync |syncreg_r_681 | 82|
|803 | Aurora_self_reset_count_reg |ipbus_syncreg_v_625 | 51|
|804 | rsync |syncreg_r_680 | 49|
|805 | Bulk_fifo_control_reg |ipbus_reg_v_626 | 36|
|806 | FEX_Busy_timer_reset_reg |ipbus_reg_v_627 | 39|
|807 | Fex_busy_status_reg |ipbus_syncreg_v_628 | 27|
|808 | rsync |syncreg_r_679 | 25|
|809 | Fex_busy_timer_0_reg |ipbus_syncreg_v_629 | 93|
|810 | rsync |syncreg_r_678 | 91|
|811 | Fex_busy_timer_1_reg |ipbus_syncreg_v_630 | 52|
|812 | rsync |syncreg_r_677 | 50|
|813 | Fex_busy_timer_2_reg |ipbus_syncreg_v_631 | 50|
|814 | rsync |syncreg_r_676 | 48|
|815 | Fex_busy_timer_3_reg |ipbus_syncreg_v_632 | 50|
|816 | rsync |syncreg_r_675 | 48|
|817 | Fex_busy_timer_4_reg |ipbus_syncreg_v_633 | 117|
|818 | rsync |syncreg_r_674 | 115|
|819 | Fex_busy_timer_5_reg |ipbus_syncreg_v_634 | 52|
|820 | rsync |syncreg_r_673 | 50|
|821 | Frame_error_counter |error_counter__parameterized0_635 | 9|
|822 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_636 | 52|
|823 | rsync |syncreg_r_672 | 50|
|824 | Tob_fifo_control_reg |ipbus_reg_v_637 | 34|
|825 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_638 | 128|
|826 | rsync |syncreg_r_671 | 126|
|827 | Tob_fifo_reset_reg |ipbus_reg_v_639 | 36|
|828 | Tob_fifo_status_reg |ipbus_syncreg_v_640 | 54|
|829 | rsync |syncreg_r_670 | 52|
|830 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_641 | 55|
|831 | rsync |syncreg_r_669 | 53|
|832 | UFC_Busy_control_reg |ipbus_reg_v_642 | 66|
|833 | UFC_msg_crc_error_reg |ipbus_syncreg_v_643 | 50|
|834 | rsync |syncreg_r_668 | 48|
|835 | aurora_reset_pulse |pulse_stretch__parameterized5_644 | 14|
|836 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_645 | 51|
|837 | rsync |syncreg_r_667 | 49|
|838 | bulk_fifo_busy_counter |threshold_counter_646 | 109|
|839 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_647 | 41|
|840 | rsync |syncreg_r_666 | 39|
|841 | bulk_fifo_reset_reg |ipbus_reg_v_648 | 98|
|842 | bulk_fifo_status_reg |ipbus_syncreg_v_649 | 53|
|843 | rsync |syncreg_r_665 | 51|
|844 | bulk_fifo_watermark |watermark_650 | 25|
|845 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_651 | 95|
|846 | rsync |syncreg_r_664 | 93|
|847 | bulk_fifo_xoff_counter |threshold_counter_652 | 109|
|848 | chan_len_err_counter |edge_error_counter_653 | 10|
|849 | chan_reset |channel_init_654 | 259|
|850 | reset_timer |aurora_reset_661 | 123|
|851 | self_reset_inst |self_reset_662 | 121|
|852 | stretcher |pulse_stretch__parameterized5_663 | 15|
|853 | hard_error_counter |error_counter__parameterized0_655 | 9|
|854 | header_crc_err_counter |error_counter__parameterized0_656 | 9|
|855 | soft_error_counter |error_counter__parameterized0_657 | 9|
|856 | tob_fifo_busy_counter |threshold_counter_658 | 109|
|857 | tob_fifo_watermark |watermark_659 | 25|
|858 | tob_fifo_xoff_counter |threshold_counter_660 | 109|
|859 | pulse_stretcher |pulse_stretch__parameterized1__11 | 22|
|860 | ufc_receiver |ufc_rx__9 | 91|
|861 | input_pipe |aurora_pipe__parameterized15 | 517|
|862 | crc_gen |CRC_619 | 97|
|863 | pulse_stretcher |pulse_stretch__parameterized3_620 | 15|
|864 | ch9 |channel_fifo__parameterized17 | 3680|
|865 | \gen_reg.status_regs |fex_chan_regs__10 | 2752|
|866 | Aurora_channel_control_reg |ipbus_reg_v_563 | 39|
|867 | Aurora_channel_disable_reg |ipbus_reg_v_564 | 33|
|868 | Aurora_channel_status_reg |ipbus_syncreg_v_565 | 46|
|869 | rsync |syncreg_r_618 | 44|
|870 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_566 | 84|
|871 | rsync |syncreg_r_617 | 82|
|872 | Aurora_self_reset_count_reg |ipbus_syncreg_v_567 | 51|
|873 | rsync |syncreg_r_616 | 49|
|874 | Bulk_fifo_control_reg |ipbus_reg_v_568 | 36|
|875 | FEX_Busy_timer_reset_reg |ipbus_reg_v_569 | 39|
|876 | Fex_busy_status_reg |ipbus_syncreg_v_570 | 27|
|877 | rsync |syncreg_r_615 | 25|
|878 | Fex_busy_timer_0_reg |ipbus_syncreg_v_571 | 93|
|879 | rsync |syncreg_r_614 | 91|
|880 | Fex_busy_timer_1_reg |ipbus_syncreg_v_572 | 52|
|881 | rsync |syncreg_r_613 | 50|
|882 | Fex_busy_timer_2_reg |ipbus_syncreg_v_573 | 50|
|883 | rsync |syncreg_r_612 | 48|
|884 | Fex_busy_timer_3_reg |ipbus_syncreg_v_574 | 50|
|885 | rsync |syncreg_r_611 | 48|
|886 | Fex_busy_timer_4_reg |ipbus_syncreg_v_575 | 117|
|887 | rsync |syncreg_r_610 | 115|
|888 | Fex_busy_timer_5_reg |ipbus_syncreg_v_576 | 52|
|889 | rsync |syncreg_r_609 | 50|
|890 | Frame_error_counter |error_counter__parameterized0 | 9|
|891 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_577 | 52|
|892 | rsync |syncreg_r_608 | 50|
|893 | Tob_fifo_control_reg |ipbus_reg_v_578 | 34|
|894 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_579 | 128|
|895 | rsync |syncreg_r_607 | 126|
|896 | Tob_fifo_reset_reg |ipbus_reg_v_580 | 36|
|897 | Tob_fifo_status_reg |ipbus_syncreg_v_581 | 54|
|898 | rsync |syncreg_r_606 | 52|
|899 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_582 | 55|
|900 | rsync |syncreg_r_605 | 53|
|901 | UFC_Busy_control_reg |ipbus_reg_v_583 | 66|
|902 | UFC_msg_crc_error_reg |ipbus_syncreg_v_584 | 50|
|903 | rsync |syncreg_r_604 | 48|
|904 | aurora_reset_pulse |pulse_stretch__parameterized5 | 14|
|905 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_585 | 51|
|906 | rsync |syncreg_r_603 | 49|
|907 | bulk_fifo_busy_counter |threshold_counter_586 | 109|
|908 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_587 | 41|
|909 | rsync |syncreg_r_602 | 39|
|910 | bulk_fifo_reset_reg |ipbus_reg_v_588 | 98|
|911 | bulk_fifo_status_reg |ipbus_syncreg_v_589 | 53|
|912 | rsync |syncreg_r_601 | 51|
|913 | bulk_fifo_watermark |watermark_590 | 25|
|914 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_591 | 95|
|915 | rsync |syncreg_r_600 | 93|
|916 | bulk_fifo_xoff_counter |threshold_counter_592 | 109|
|917 | chan_len_err_counter |edge_error_counter | 10|
|918 | chan_reset |channel_init | 259|
|919 | reset_timer |aurora_reset | 123|
|920 | self_reset_inst |self_reset | 121|
|921 | stretcher |pulse_stretch__parameterized5_599 | 15|
|922 | hard_error_counter |error_counter__parameterized0_593 | 9|
|923 | header_crc_err_counter |error_counter__parameterized0_594 | 9|
|924 | soft_error_counter |error_counter__parameterized0_595 | 9|
|925 | tob_fifo_busy_counter |threshold_counter_596 | 109|
|926 | tob_fifo_watermark |watermark_597 | 25|
|927 | tob_fifo_xoff_counter |threshold_counter_598 | 109|
|928 | pulse_stretcher |pulse_stretch__parameterized1__12 | 22|
|929 | ufc_receiver |ufc_rx__10 | 91|
|930 | input_pipe |aurora_pipe__parameterized17 | 517|
|931 | crc_gen |CRC_562 | 97|
|932 | pulse_stretcher |pulse_stretch__parameterized3 | 15|
|933 | \gen_reg.ttc_regs |ttc_chan_regs | 973|
|934 | BCN_reg |ipbus_syncreg_v_533 | 33|
|935 | rsync |syncreg_r_561 | 31|
|936 | CTTC_link_stat_reg |ipbus_syncreg_v_534 | 51|
|937 | rsync |syncreg_r_560 | 49|
|938 | L1ID_Value_reg |ipbus_syncreg_v_535 | 50|
|939 | rsync |syncreg_r_559 | 48|
|940 | TTC_control_reg |ipbus_reg_v_536 | 91|
|941 | TTC_fifo_busy_Count_reg |ipbus_syncreg_v_537 | 92|
|942 | rsync |syncreg_r_558 | 90|
|943 | TTC_fifo_busy_threshold_reg |ipbus_reg_v_538 | 90|
|944 | TTC_fifo_control_reg |ipbus_reg_v_539 | 50|
|945 | TTC_fifo_fill_level_reg |ipbus_syncreg_v_540 | 44|
|946 | rsync |syncreg_r_557 | 42|
|947 | TTC_fifo_status_reg |ipbus_syncreg_v_541 | 20|
|948 | rsync |syncreg_r_556 | 18|
|949 | TTC_reset_register |ipbus_reg_v_542 | 62|
|950 | crc_err_counter |error_counter | 19|
|951 | disperity_err_counter |error_counter_543 | 19|
|952 | event_count_reg |ipbus_syncreg_v_544 | 43|
|953 | rsync |syncreg_r_555 | 40|
|954 | orbit_reg |ipbus_syncreg_v_545 | 50|
|955 | rsync |syncreg_r_554 | 45|
|956 | packet_header_info |ipbus_reg_v_546 | 45|
|957 | table_err_counter |error_counter_547 | 19|
|958 | total_event_count_msb |ipbus_syncreg_v_548 | 24|
|959 | rsync |syncreg_r_553 | 22|
|960 | total_event_count_reg |ipbus_syncreg_v_549 | 58|
|961 | rsync |syncreg_r_552 | 56|
|962 | ttc_fifo_busy_counter |threshold_counter_550 | 41|
|963 | ttc_fifo_watermark |watermark_551 | 21|
|964 | bulk_2 |bulk_processor | 2347|
|965 | stretcher |pulse_stretch__parameterized1__16 | 22|
|966 | controller |bulk_controller__4 | 15|
|967 | state_reg |vDFF__parameterized1_532 | 15|
|968 | status_regs |bulk_proc_regs__4 | 1736|
|969 | bulk_stage_busy_counter |threshold_counter_487 | 86|
|970 | bulk_stage_xoff_counter |threshold_counter_488 | 85|
|971 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v_489 | 38|
|972 | rsync |syncreg_r_531 | 36|
|973 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v_490 | 66|
|974 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v_491 | 38|
|975 | \gen_regs.Full_mode_control_reg |ipbus_reg_v_492 | 57|
|976 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v_493 | 62|
|977 | rsync |syncreg_r_530 | 60|
|978 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v_494 | 26|
|979 | rsync |syncreg_r_529 | 24|
|980 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v_495 | 50|
|981 | rsync |syncreg_r_528 | 48|
|982 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v_496 | 39|
|983 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v_497 | 48|
|984 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v_498 | 132|
|985 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v_499 | 49|
|986 | rsync |syncreg_r_527 | 47|
|987 | \gen_regs.event_fifo_watermark |watermark_500 | 34|
|988 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v_501 | 48|
|989 | rsync |syncreg_r_526 | 46|
|990 | \gen_regs.fm_fifo_watermark |watermark_502 | 17|
|991 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v_503 | 29|
|992 | rsync |syncreg_r_525 | 27|
|993 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v_504 | 41|
|994 | rsync |syncreg_r_524 | 39|
|995 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1_505 | 692|
|996 | Capture_Control_reg |ipbus_reg_v_509 | 66|
|997 | Capture_status_reg |ipbus_syncreg_v_510 | 23|
|998 | rsync |syncreg_r_523 | 21|
|999 | Header_0_reg |ipbus_syncreg_v_511 | 67|
|1000 | rsync |syncreg_r_522 | 65|
|1001 | Header_1_reg |ipbus_syncreg_v_512 | 63|
|1002 | rsync |syncreg_r_521 | 61|
|1003 | Header_2_reg |ipbus_syncreg_v_513 | 62|
|1004 | rsync |syncreg_r_520 | 60|
|1005 | pkt_count_reg |ipbus_syncreg_v_514 | 67|
|1006 | rsync |syncreg_r_519 | 65|
|1007 | trailer_0_reg |ipbus_syncreg_v_515 | 60|
|1008 | rsync |syncreg_r_518 | 58|
|1009 | trailer_1_reg |ipbus_syncreg_v_516 | 68|
|1010 | rsync |syncreg_r_517 | 65|
|1011 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v_506 | 57|
|1012 | rsync |syncreg_r_508 | 55|
|1013 | \gen_regs.stage_fifo_watermark |watermark_507 | 34|
|1014 | event_header_crc |event_hdr_crc9_484 | 99|
|1015 | hdr_chk_crc |osum_crc9d32_486 | 87|
|1016 | input_mux |bulk_channel_mux_485 | 252|
|1017 | bulk_1 |bulk_processor__xdcDup__2 | 2347|
|1018 | stretcher |pulse_stretch__parameterized1__15 | 22|
|1019 | controller |bulk_controller__3 | 15|
|1020 | state_reg |vDFF__parameterized1_483 | 15|
|1021 | status_regs |bulk_proc_regs__3 | 1736|
|1022 | bulk_stage_busy_counter |threshold_counter_438 | 86|
|1023 | bulk_stage_xoff_counter |threshold_counter_439 | 85|
|1024 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v_440 | 38|
|1025 | rsync |syncreg_r_482 | 36|
|1026 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v_441 | 66|
|1027 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v_442 | 38|
|1028 | \gen_regs.Full_mode_control_reg |ipbus_reg_v_443 | 57|
|1029 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v_444 | 62|
|1030 | rsync |syncreg_r_481 | 60|
|1031 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v_445 | 26|
|1032 | rsync |syncreg_r_480 | 24|
|1033 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v_446 | 50|
|1034 | rsync |syncreg_r_479 | 48|
|1035 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v_447 | 39|
|1036 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v_448 | 48|
|1037 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v_449 | 132|
|1038 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v_450 | 49|
|1039 | rsync |syncreg_r_478 | 47|
|1040 | \gen_regs.event_fifo_watermark |watermark_451 | 34|
|1041 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v_452 | 48|
|1042 | rsync |syncreg_r_477 | 46|
|1043 | \gen_regs.fm_fifo_watermark |watermark_453 | 17|
|1044 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v_454 | 29|
|1045 | rsync |syncreg_r_476 | 27|
|1046 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v_455 | 41|
|1047 | rsync |syncreg_r_475 | 39|
|1048 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1_456 | 692|
|1049 | Capture_Control_reg |ipbus_reg_v_460 | 66|
|1050 | Capture_status_reg |ipbus_syncreg_v_461 | 23|
|1051 | rsync |syncreg_r_474 | 21|
|1052 | Header_0_reg |ipbus_syncreg_v_462 | 67|
|1053 | rsync |syncreg_r_473 | 65|
|1054 | Header_1_reg |ipbus_syncreg_v_463 | 63|
|1055 | rsync |syncreg_r_472 | 61|
|1056 | Header_2_reg |ipbus_syncreg_v_464 | 62|
|1057 | rsync |syncreg_r_471 | 60|
|1058 | pkt_count_reg |ipbus_syncreg_v_465 | 67|
|1059 | rsync |syncreg_r_470 | 65|
|1060 | trailer_0_reg |ipbus_syncreg_v_466 | 60|
|1061 | rsync |syncreg_r_469 | 58|
|1062 | trailer_1_reg |ipbus_syncreg_v_467 | 68|
|1063 | rsync |syncreg_r_468 | 65|
|1064 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v_457 | 57|
|1065 | rsync |syncreg_r_459 | 55|
|1066 | \gen_regs.stage_fifo_watermark |watermark_458 | 34|
|1067 | event_header_crc |event_hdr_crc9_435 | 99|
|1068 | hdr_chk_crc |osum_crc9d32_437 | 87|
|1069 | input_mux |bulk_channel_mux_436 | 252|
|1070 | readout_controller |ro_controller | 437|
|1071 | ro_crc |CRC | 167|
|1072 | bulk_0 |bulk_processor__xdcDup__1 | 2347|
|1073 | stretcher |pulse_stretch__parameterized1__17 | 22|
|1074 | controller |bulk_controller | 15|
|1075 | state_reg |vDFF__parameterized1 | 15|
|1076 | status_regs |bulk_proc_regs | 1736|
|1077 | bulk_stage_busy_counter |threshold_counter_391 | 86|
|1078 | bulk_stage_xoff_counter |threshold_counter_392 | 85|
|1079 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v_393 | 38|
|1080 | rsync |syncreg_r_434 | 36|
|1081 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v_394 | 66|
|1082 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v_395 | 38|
|1083 | \gen_regs.Full_mode_control_reg |ipbus_reg_v_396 | 57|
|1084 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v_397 | 62|
|1085 | rsync |syncreg_r_433 | 60|
|1086 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v_398 | 26|
|1087 | rsync |syncreg_r_432 | 24|
|1088 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v_399 | 50|
|1089 | rsync |syncreg_r_431 | 48|
|1090 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v_400 | 39|
|1091 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v_401 | 48|
|1092 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v_402 | 132|
|1093 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v_403 | 49|
|1094 | rsync |syncreg_r_430 | 47|
|1095 | \gen_regs.event_fifo_watermark |watermark_404 | 34|
|1096 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v_405 | 48|
|1097 | rsync |syncreg_r_429 | 46|
|1098 | \gen_regs.fm_fifo_watermark |watermark_406 | 17|
|1099 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v_407 | 29|
|1100 | rsync |syncreg_r_428 | 27|
|1101 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v_408 | 41|
|1102 | rsync |syncreg_r_427 | 39|
|1103 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1 | 692|
|1104 | Capture_Control_reg |ipbus_reg_v_412 | 66|
|1105 | Capture_status_reg |ipbus_syncreg_v_413 | 23|
|1106 | rsync |syncreg_r_426 | 21|
|1107 | Header_0_reg |ipbus_syncreg_v_414 | 67|
|1108 | rsync |syncreg_r_425 | 65|
|1109 | Header_1_reg |ipbus_syncreg_v_415 | 63|
|1110 | rsync |syncreg_r_424 | 61|
|1111 | Header_2_reg |ipbus_syncreg_v_416 | 62|
|1112 | rsync |syncreg_r_423 | 60|
|1113 | pkt_count_reg |ipbus_syncreg_v_417 | 67|
|1114 | rsync |syncreg_r_422 | 65|
|1115 | trailer_0_reg |ipbus_syncreg_v_418 | 60|
|1116 | rsync |syncreg_r_421 | 58|
|1117 | trailer_1_reg |ipbus_syncreg_v_419 | 68|
|1118 | rsync |syncreg_r_420 | 65|
|1119 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v_409 | 57|
|1120 | rsync |syncreg_r_411 | 55|
|1121 | \gen_regs.stage_fifo_watermark |watermark_410 | 34|
|1122 | event_header_crc |event_hdr_crc9_389 | 99|
|1123 | hdr_chk_crc |osum_crc9d32_390 | 87|
|1124 | input_mux |bulk_channel_mux | 252|
|1125 | ttc_input |ttc_info | 390|
|1126 | cttc_crc |osum_crc9d32_388 | 81|
|1127 | bkpln_rst_pulse_stretcher |pulse_stretch__parameterized1 | 23|
|1128 | fabric |ipbus_fabric_sel__parameterized0 | 1|
|1129 | tob_processor_0 |tob_processor | 5187|
|1130 | input_mux |channel_mux | 547|
|1131 | event_builder_0 |ev_builder | 2402|
|1132 | state_reg |vDFF | 6|
|1133 | event_trailer_crc |event_trailer_CRC20__1 | 298|
|1134 | crc_block |flx_CRC_387 | 298|
|1135 | chan_trailer_crc |event_trailer_CRC20 | 325|
|1136 | crc_block |flx_CRC | 325|
|1137 | channel_header_crc |hdr_in_crc9 | 114|
|1138 | hdr_chk_crc |osum_crc9d32_386 | 62|
|1139 | dbg_crc20_gen |CRC__parameterized3 | 324|
|1140 | dbg_crc9_gen |CRC__14 | 54|
|1141 | dbg_trailer_err_map |trailer_map | 165|
|1142 | event_header_crc |event_hdr_crc9 | 95|
|1143 | hdr_chk_crc |osum_crc9d32 | 82|
|1144 | evnt_trailer_err_map |trailer_map_385 | 69|
|1145 | timeout |tob_timeout | 92|
|1146 | \gen_reg.status_regs |tob_proc_regs | 2120|
|1147 | Event_fifo_control_reg |ipbus_reg_v | 85|
|1148 | Event_fifo_reset_reg |ipbus_reg_v_338 | 39|
|1149 | Full_mode_control_reg |ipbus_reg_v_339 | 45|
|1150 | Tob_stage_busy_Count_reg |ipbus_syncreg_v_340 | 57|
|1151 | rsync |syncreg_r_384 | 55|
|1152 | Tob_stage_fifo_status_reg |ipbus_syncreg_v_341 | 27|
|1153 | rsync |syncreg_r_383 | 24|
|1154 | Tob_stage_xoff_Count_reg |ipbus_syncreg_v_342 | 73|
|1155 | rsync |syncreg_r_382 | 70|
|1156 | Tob_staging_fifo_resets_reg |ipbus_reg_v_343 | 72|
|1157 | Tob_timeout_reg |ipbus_ctrlreg_v__parameterized0 | 65|
|1158 | debug_fifo_fill_level_reg |ipbus_syncreg_v_344 | 54|
|1159 | rsync |syncreg_r_381 | 51|
|1160 | debug_fifo_watermark |watermark | 34|
|1161 | error_count_register |ipbus_syncreg_v_345 | 37|
|1162 | rsync |syncreg_r_380 | 35|
|1163 | event_fifo_fill_level_reg |ipbus_syncreg_v_346 | 52|
|1164 | rsync |syncreg_r_379 | 49|
|1165 | event_fifo_watermark |watermark_347 | 34|
|1166 | fm_L1id_reg |ipbus_syncreg_v_348 | 48|
|1167 | rsync |syncreg_r_378 | 45|
|1168 | fm_fifo_watermark |watermark_349 | 34|
|1169 | full_mode_status_reg |ipbus_syncreg_v_350 | 29|
|1170 | rsync |syncreg_r_377 | 26|
|1171 | fullmode_fifo_fill_level_reg |ipbus_syncreg_v_351 | 44|
|1172 | rsync |syncreg_r_376 | 42|
|1173 | packet_capture |pkt_capture_regs | 692|
|1174 | Capture_Control_reg |ipbus_reg_v_361 | 40|
|1175 | Capture_status_reg |ipbus_syncreg_v_362 | 24|
|1176 | rsync |syncreg_r_375 | 21|
|1177 | Header_0_reg |ipbus_syncreg_v_363 | 49|
|1178 | rsync |syncreg_r_374 | 46|
|1179 | Header_1_reg |ipbus_syncreg_v_364 | 85|
|1180 | rsync |syncreg_r_373 | 82|
|1181 | Header_2_reg |ipbus_syncreg_v_365 | 50|
|1182 | rsync |syncreg_r_372 | 47|
|1183 | pkt_count_reg |ipbus_syncreg_v_366 | 125|
|1184 | rsync |syncreg_r_371 | 122|
|1185 | trailer_0_reg |ipbus_syncreg_v_367 | 52|
|1186 | rsync |syncreg_r_370 | 49|
|1187 | trailer_1_reg |ipbus_syncreg_v_368 | 52|
|1188 | rsync |syncreg_r_369 | 49|
|1189 | stage_fifo_fill_level_reg |ipbus_syncreg_v_352 | 89|
|1190 | rsync |syncreg_r_360 | 86|
|1191 | stage_fifo_watermark |watermark_353 | 34|
|1192 | tob_proc_reset_reg |ipbus_reg_v_354 | 38|
|1193 | tob_proc_status |ipbus_syncreg_v_355 | 61|
|1194 | rsync |syncreg_r_359 | 58|
|1195 | tob_stage_busy_counter |threshold_counter | 84|
|1196 | tob_stage_xoff_counter |threshold_counter_356 | 84|
|1197 | tob_staging_control_reg |ipbus_reg_v_357 | 38|
|1198 | tob_staging_thresholds_reg |ipbus_reg_v_358 | 119|
|1199 | chan_in_gen |dummy_chan_in__1 | 17|
|1200 | reset_top |system_top_reset | 83|
|1201 | phy_reset |system_top_reset__parameterized1 | 82|
|1202 | fm_interface_1 |Full_Mode_Tx__xdcDup__1 | 2538|
|1203 | chan_0 |FM_channel__xdcDup__1 | 868|
|1204 | u5 |FMchannelTXctrl | 371|
|1205 | crc20_0 |CRC__parameterized4_335 | 246|
|1206 | eop_space_trig |pulse_pdxx_pwxx_336 | 4|
|1207 | sop_space_trig |pulse_pdxx_pwxx_337 | 13|
|1208 | u7 |FIFO34to34b__xdcDup__1 | 42|
|1209 | reset_timer |rst_tmr | 127|
|1210 | ram0 |FM_example_emuram__xdcDup__1 | 88|
|1211 | ctl0 |FM_example_FIFOctrl | 95|
|1212 | axi_interface |fm_axi_333 | 4|
|1213 | data_mux |tx_data_mux_334 | 34|
|1214 | chan_1 |FM_channel__xdcDup__2 | 867|
|1215 | u5 |FMchannelTXctrl__6 | 371|
|1216 | crc20_0 |CRC__parameterized4_330 | 246|
|1217 | eop_space_trig |pulse_pdxx_pwxx_331 | 4|
|1218 | sop_space_trig |pulse_pdxx_pwxx_332 | 13|
|1219 | u7 |FIFO34to34b__xdcDup__2 | 42|
|1220 | reset_timer |rst_tmr__6 | 127|
|1221 | ram0 |FM_example_emuram__xdcDup__2 | 88|
|1222 | ctl0 |FM_example_FIFOctrl__6 | 95|
|1223 | axi_interface |fm_axi_328 | 4|
|1224 | data_mux |tx_data_mux_329 | 34|
|1225 | u0 |FullModeTransceiver__xdcDup__1 | 798|
|1226 | \g_gt_channel[0].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__4 | 247|
|1227 | sync_CPLLLOCK |FullModeTransceiver_sync_block_321 | 10|
|1228 | sync_RXRESETDONE |FullModeTransceiver_sync_block_322 | 6|
|1229 | sync_data_valid |FullModeTransceiver_sync_block_323 | 8|
|1230 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_324 | 8|
|1231 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_325 | 6|
|1232 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_326 | 6|
|1233 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_327 | 6|
|1234 | \g_gt_channel[1].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM | 247|
|1235 | sync_CPLLLOCK |FullModeTransceiver_sync_block_314 | 10|
|1236 | sync_RXRESETDONE |FullModeTransceiver_sync_block_315 | 6|
|1237 | sync_data_valid |FullModeTransceiver_sync_block_316 | 8|
|1238 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_317 | 8|
|1239 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_318 | 6|
|1240 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_319 | 6|
|1241 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_320 | 6|
|1242 | txresetfsm_i |FullModeTransceiver_TX_STARTUP_FSM | 230|
|1243 | sync_QPLLLOCK |FullModeTransceiver_sync_block_308 | 13|
|1244 | sync_TXRESETDONE |FullModeTransceiver_sync_block_309 | 6|
|1245 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_310 | 8|
|1246 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_311 | 6|
|1247 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_312 | 6|
|1248 | sync_tx_fsm_reset_done_int |FullModeTransceiver_sync_block_313 | 6|
|1249 | fm_interface_2 |Full_Mode_Tx | 2553|
|1250 | chan_0 |FM_channel__xdcDup__3 | 868|
|1251 | u5 |FMchannelTXctrl__5 | 371|
|1252 | crc20_0 |CRC__parameterized4_305 | 246|
|1253 | eop_space_trig |pulse_pdxx_pwxx_306 | 4|
|1254 | sop_space_trig |pulse_pdxx_pwxx_307 | 13|
|1255 | u7 |FIFO34to34b__xdcDup__3 | 42|
|1256 | reset_timer |rst_tmr__5 | 127|
|1257 | ram0 |FM_example_emuram__xdcDup__3 | 88|
|1258 | ctl0 |FM_example_FIFOctrl__5 | 95|
|1259 | axi_interface |fm_axi_303 | 4|
|1260 | data_mux |tx_data_mux_304 | 34|
|1261 | chan_1 |FM_channel | 882|
|1262 | u5 |FMchannelTXctrl__4 | 386|
|1263 | crc20_0 |CRC__parameterized4 | 246|
|1264 | eob_space_trig |pulse_pdxx_pwxx | 3|
|1265 | eop_space_trig |pulse_pdxx_pwxx_300 | 4|
|1266 | sob_space_trig |pulse_pdxx_pwxx_301 | 11|
|1267 | sop_space_trig |pulse_pdxx_pwxx_302 | 8|
|1268 | u7 |FIFO34to34b | 42|
|1269 | reset_timer |rst_tmr__4 | 127|
|1270 | ram0 |FM_example_emuram | 88|
|1271 | ctl0 |FM_example_FIFOctrl__4 | 95|
|1272 | axi_interface |fm_axi | 4|
|1273 | data_mux |tx_data_mux | 34|
|1274 | u0 |FullModeTransceiver | 798|
|1275 | \g_gt_channel[0].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__2 | 247|
|1276 | sync_CPLLLOCK |FullModeTransceiver_sync_block_293 | 10|
|1277 | sync_RXRESETDONE |FullModeTransceiver_sync_block_294 | 6|
|1278 | sync_data_valid |FullModeTransceiver_sync_block_295 | 8|
|1279 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_296 | 8|
|1280 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_297 | 6|
|1281 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_298 | 6|
|1282 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_299 | 6|
|1283 | \g_gt_channel[1].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__3 | 247|
|1284 | sync_CPLLLOCK |FullModeTransceiver_sync_block_286 | 10|
|1285 | sync_RXRESETDONE |FullModeTransceiver_sync_block_287 | 6|
|1286 | sync_data_valid |FullModeTransceiver_sync_block_288 | 8|
|1287 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_289 | 8|
|1288 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_290 | 6|
|1289 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_291 | 6|
|1290 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_292 | 6|
|1291 | txresetfsm_i |FullModeTransceiver_TX_STARTUP_FSM__2 | 230|
|1292 | sync_QPLLLOCK |FullModeTransceiver_sync_block | 13|
|1293 | sync_TXRESETDONE |FullModeTransceiver_sync_block_281 | 6|
|1294 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_282 | 8|
|1295 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_283 | 6|
|1296 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_284 | 6|
|1297 | sync_tx_fsm_reset_done_int |FullModeTransceiver_sync_block_285 | 6|
|1298 | Bulk_0_64_32 |packet_fifo__xdcDup__1 | 200|
|1299 | Bulk_1_64_32 |packet_fifo__xdcDup__2 | 200|
|1300 | Bulk_2_64_32 |packet_fifo__xdcDup__3 | 200|
|1301 | pp_out_fifo_6432 |packet_fifo | 200|
|1302 | ipbus_blk |ROD_system | 27415|
|1303 | axi4_subsys |axi4_subsys_wrapper | 19106|
|1304 | axi4_subsys_i |axi4_subsys | 19097|
|1305 | axi_emc_0 |axi4_subsys_axi_emc_0_0 | 1477|
|1306 | U0 |axi_emc | 1477|
|1307 | AXI_EMC_NATIVE_INTERFACE_I |axi_emc_native_interface | 903|
|1308 | AXI_EMC_ADDRESS_DECODE_INSTANCE_I |axi_emc_address_decode | 52|
|1309 | AXI_EMC_ADDR_GEN_INSTANCE_I |axi_emc_addr_gen | 100|
|1310 | RDATA_FIFO_I |srl_fifo_rbu_f | 536|
|1311 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f | 35|
|1312 | DYNSHREG_F_I |dynshreg_f | 495|
|1313 | EMC_CTRL_I |EMC | 541|
|1314 | ADDR_COUNTER_MUX_I |addr_counter_mux | 40|
|1315 | COUNTERS_I |counters | 143|
|1316 | THZCNT_I |ld_arith_reg__parameterized1 | 28|
|1317 | TLZCNT_I |ld_arith_reg__parameterized1_278 | 31|
|1318 | TRDCNT_I |ld_arith_reg__parameterized0 | 27|
|1319 | TWPHCNT_I |ld_arith_reg__parameterized1_279 | 28|
|1320 | TWRCNT_I |ld_arith_reg__parameterized0_280 | 29|
|1321 | IO_REGISTERS_I |io_registers | 110|
|1322 | IPIC_IF_I |emc_common_v3_0_5_ipic_if | 72|
|1323 | BURST_CNT |ld_arith_reg | 33|
|1324 | MEM_STATE_MACHINE_I |mem_state_machine | 109|
|1325 | MEM_STEER_I |mem_steer | 67|
|1326 | xadc_wiz_0 |axi4_subsys_xadc_wiz_0_0 | 441|
|1327 | U0 |axi4_subsys_xadc_wiz_0_0_axi_xadc | 441|
|1328 | AXI_LITE_IPIF_I |axi4_subsys_xadc_wiz_0_0_axi_lite_ipif | 189|
|1329 | I_SLAVE_ATTACHMENT |axi4_subsys_xadc_wiz_0_0_slave_attachment | 189|
|1330 | I_DECODER |axi4_subsys_xadc_wiz_0_0_address_decoder | 133|
|1331 | AXI_XADC_CORE_I |axi4_subsys_xadc_wiz_0_0_xadc_core_drp | 77|
|1332 | \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I |axi4_subsys_xadc_wiz_0_0_interrupt_control | 102|
|1333 | SOFT_RESET_I |axi4_subsys_xadc_wiz_0_0_soft_reset | 39|
|1334 | jtag_axi_0 |axi4_subsys_jtag_axi_0_0 | 2435|
|1335 | U0 |jtag_axi_v1_2_10_jtag_axi | 2435|
|1336 | axi_bridge_u |jtag_axi_v1_2_10_axi_bridge | 261|
|1337 | read_axi_full_u |jtag_axi_v1_2_10_read_axi | 128|
|1338 | write_axi_full_u |jtag_axi_v1_2_10_write_axi | 133|
|1339 | jtag_axi_engine_u |jtag_axi_v1_2_10_jtag_axi_engine | 2174|
|1340 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 247|
|1341 | cmd_decode_rd_channel |jtag_axi_v1_2_10_cmd_decode | 9|
|1342 | cmd_decode_wr_channel |jtag_axi_v1_2_10_cmd_decode_254 | 9|
|1343 | rd_cmd_fifo_i |fifo_generator_v13_2_5__parameterized1 | 188|
|1344 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized1 | 188|
|1345 | \gconvfifo.rf |fifo_generator_top__parameterized1 | 188|
|1346 | \grf.rf |fifo_generator_ramfifo__parameterized1 | 188|
|1347 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__parameterized0 | 46|
|1348 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized8__4 | 22|
|1349 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized8__5 | 22|
|1350 | \gntv_or_sync_fifo.gl0.rd |rd_logic__parameterized0_264 | 35|
|1351 | \gr1.gr1_int.rfwft |rd_fwft_275 | 19|
|1352 | \gras.rsts |rd_status_flags_as__parameterized0_276 | 2|
|1353 | rpntr |rd_bin_cntr__parameterized0_277 | 14|
|1354 | \gntv_or_sync_fifo.gl0.wr |wr_logic__parameterized0_265 | 23|
|1355 | \gwas.wsts |wr_status_flags_as__parameterized0_273 | 3|
|1356 | wpntr |wr_bin_cntr__parameterized0_274 | 20|
|1357 | \gntv_or_sync_fifo.mem |memory__parameterized1_266 | 84|
|1358 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4__parameterized1_267 | 19|
|1359 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth__parameterized0_268 | 19|
|1360 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top__parameterized0_269 | 19|
|1361 | \valid.cstr |blk_mem_gen_generic_cstr__parameterized0_270 | 19|
|1362 | \ramloop[0].ram.r |blk_mem_gen_prim_width__parameterized0_271 | 19|
|1363 | \prim_noinit.ram |blk_mem_gen_prim_wrapper__parameterized0_272 | 1|
|1364 | rx_fifo_i |fifo_generator_v13_2_5__parameterized0 | 242|
|1365 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized0 | 242|
|1366 | \gconvfifo.rf |fifo_generator_top__parameterized0 | 242|
|1367 | \grf.rf |fifo_generator_ramfifo__parameterized0 | 242|
|1368 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 96|
|1369 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized6__4 | 46|
|1370 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized6__5 | 46|
|1371 | \gntv_or_sync_fifo.gl0.rd |rd_logic_257 | 54|
|1372 | \gr1.gr1_int.rfwft |rd_fwft_261 | 17|
|1373 | \gras.rsts |rd_status_flags_as_262 | 2|
|1374 | rpntr |rd_bin_cntr_263 | 35|
|1375 | \gntv_or_sync_fifo.gl0.wr |wr_logic_258 | 40|
|1376 | \gwas.wsts |wr_status_flags_as_259 | 2|
|1377 | wpntr |wr_bin_cntr_260 | 38|
|1378 | \gntv_or_sync_fifo.mem |memory__parameterized0 | 52|
|1379 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4 | 20|
|1380 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 20|
|1381 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 20|
|1382 | \valid.cstr |blk_mem_gen_generic_cstr | 20|
|1383 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 20|
|1384 | \prim_noinit.ram |blk_mem_gen_prim_wrapper | 2|
|1385 | tx_fifo_i |fifo_generator_v13_2_5 | 335|
|1386 | inst_fifo_gen |fifo_generator_v13_2_5_synth | 335|
|1387 | \gconvfifo.rf |fifo_generator_top | 335|
|1388 | \grf.rf |fifo_generator_ramfifo | 335|
|1389 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__xdcDup__1 | 110|
|1390 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized6__6 | 46|
|1391 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized6 | 46|
|1392 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 42|
|1393 | \gr1.gr1_int.rfwft |rd_fwft_256 | 15|
|1394 | \gras.rsts |rd_status_flags_as | 2|
|1395 | rpntr |rd_bin_cntr | 25|
|1396 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 39|
|1397 | \gwas.wsts |wr_status_flags_as | 2|
|1398 | wpntr |wr_bin_cntr | 37|
|1399 | \gntv_or_sync_fifo.mem |memory | 144|
|1400 | \gdm.dm_gen.dm |dmem | 112|
|1401 | u_xsdb_fifo_interface |jtag_axi_v1_2_10_xsdb_fifo_interface | 614|
|1402 | rxfifo2xsdb_i |jtag_axi_v1_2_10_rxfifo2xsdb | 132|
|1403 | xsdb2read_cmdfifo |jtag_axi_v1_2_10_xsdb2txfifo__parameterized0 | 143|
|1404 | xsdb2txfifo_i |jtag_axi_v1_2_10_xsdb2txfifo | 76|
|1405 | xsdb2write_cmdfifo |jtag_axi_v1_2_10_xsdb2txfifo__parameterized0_255 | 143|
|1406 | wr_cmd_fifo_i |fifo_generator_v13_2_5__parameterized1__xdcDup__1 | 179|
|1407 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized1__xdcDup__1 | 179|
|1408 | \gconvfifo.rf |fifo_generator_top__parameterized1__xdcDup__1 | 179|
|1409 | \grf.rf |fifo_generator_ramfifo__parameterized1__xdcDup__1 | 179|
|1410 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__parameterized0__xdcDup__1 | 46|
|1411 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized8__6 | 22|
|1412 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized8 | 22|
|1413 | \gntv_or_sync_fifo.gl0.rd |rd_logic__parameterized0 | 37|
|1414 | \gr1.gr1_int.rfwft |rd_fwft | 21|
|1415 | \gras.rsts |rd_status_flags_as__parameterized0 | 2|
|1416 | rpntr |rd_bin_cntr__parameterized0 | 14|
|1417 | \gntv_or_sync_fifo.gl0.wr |wr_logic__parameterized0 | 23|
|1418 | \gwas.wsts |wr_status_flags_as__parameterized0 | 3|
|1419 | wpntr |wr_bin_cntr__parameterized0 | 20|
|1420 | \gntv_or_sync_fifo.mem |memory__parameterized1 | 73|
|1421 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4__parameterized1 | 19|
|1422 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth__parameterized0 | 19|
|1423 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top__parameterized0 | 19|
|1424 | \valid.cstr |blk_mem_gen_generic_cstr__parameterized0 | 19|
|1425 | \ramloop[0].ram.r |blk_mem_gen_prim_width__parameterized0 | 19|
|1426 | \prim_noinit.ram |blk_mem_gen_prim_wrapper__parameterized0 | 1|
|1427 | axi_iic_0 |axi4_subsys_axi_iic_0_0 | 882|
|1428 | U0 |axi_iic__1 | 882|
|1429 | X_IIC |iic_231 | 882|
|1430 | DYN_MASTER_I |dynamic_master_232 | 33|
|1431 | FILTER_I |filter_233 | 11|
|1432 | SCL_DEBOUNCE |debounce_250 | 6|
|1433 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_253 | 6|
|1434 | SDA_DEBOUNCE |debounce_251 | 5|
|1435 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_252 | 5|
|1436 | IIC_CONTROL_I |iic_control_234 | 285|
|1437 | BITCNT |upcnt_n__parameterized0_245 | 15|
|1438 | CLKCNT |upcnt_n_246 | 34|
|1439 | I2CDATA_REG |shift8_247 | 18|
|1440 | I2CHEADER_REG |shift8_248 | 23|
|1441 | SETUP_CNT |upcnt_n_249 | 25|
|1442 | READ_FIFO_I |SRL_FIFO__parameterized0_235 | 32|
|1443 | REG_INTERFACE_I |reg_interface_236 | 200|
|1444 | WRITE_FIFO_CTRL_I |SRL_FIFO__parameterized1_237 | 21|
|1445 | WRITE_FIFO_I |SRL_FIFO_238 | 33|
|1446 | X_AXI_IPIF_SSP1 |axi_ipif_ssp1_239 | 263|
|1447 | AXI_LITE_IPIF_I |axi_lite_ipif__parameterized1_240 | 215|
|1448 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized1_243 | 215|
|1449 | I_DECODER |address_decoder__parameterized1_244 | 101|
|1450 | X_INTERRUPT_CONTROL |interrupt_control__parameterized0_241 | 31|
|1451 | X_SOFT_RESET |axi_iic_v2_0_23_soft_reset_242 | 13|
|1452 | axi_interconnect_0 |axi4_subsys_axi_interconnect_0_0 | 9002|
|1453 | xbar |axi4_subsys_xbar_0 | 2630|
|1454 | inst |axi_crossbar_v2_1_21_axi_crossbar | 2630|
|1455 | \gen_samd.crossbar_samd |axi_crossbar_v2_1_21_crossbar | 2630|
|1456 | addr_arbiter_ar |axi_crossbar_v2_1_21_addr_arbiter | 235|
|1457 | \gen_arbiter.mux_mesg |generic_baseblocks_v2_1_0_mux_enc__parameterized2_230 | 58|
|1458 | addr_arbiter_aw |axi_crossbar_v2_1_21_addr_arbiter_174 | 279|
|1459 | \gen_arbiter.mux_mesg |generic_baseblocks_v2_1_0_mux_enc__parameterized2 | 58|
|1460 | \gen_decerr_slave.decerr_slave_inst |axi_crossbar_v2_1_21_decerr_slave | 49|
|1461 | \gen_master_slots[0].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux | 55|
|1462 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_228 | 54|
|1463 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_229 | 1|
|1464 | \gen_master_slots[0].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1 | 146|
|1465 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_226 | 20|
|1466 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_227 | 126|
|1467 | \gen_master_slots[1].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_175 | 55|
|1468 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_224 | 54|
|1469 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_225 | 1|
|1470 | \gen_master_slots[1].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_176 | 141|
|1471 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_222 | 18|
|1472 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_223 | 123|
|1473 | \gen_master_slots[2].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_177 | 55|
|1474 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_220 | 54|
|1475 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_221 | 1|
|1476 | \gen_master_slots[2].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_178 | 147|
|1477 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_218 | 20|
|1478 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_219 | 127|
|1479 | \gen_master_slots[3].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_179 | 55|
|1480 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_216 | 54|
|1481 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_217 | 1|
|1482 | \gen_master_slots[3].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_180 | 144|
|1483 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_214 | 19|
|1484 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_215 | 125|
|1485 | \gen_master_slots[4].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_181 | 52|
|1486 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_212 | 51|
|1487 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_213 | 1|
|1488 | \gen_master_slots[4].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_182 | 146|
|1489 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_210 | 20|
|1490 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_211 | 126|
|1491 | \gen_master_slots[5].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_183 | 52|
|1492 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_208 | 51|
|1493 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_209 | 1|
|1494 | \gen_master_slots[5].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_184 | 145|
|1495 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_206 | 20|
|1496 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_207 | 125|
|1497 | \gen_master_slots[6].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_185 | 52|
|1498 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0 | 51|
|1499 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_205 | 1|
|1500 | \gen_master_slots[6].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_186 | 148|
|1501 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_203 | 20|
|1502 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_204 | 128|
|1503 | \gen_master_slots[7].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux__parameterized0 | 16|
|1504 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1 | 15|
|1505 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_202 | 1|
|1506 | \gen_master_slots[7].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_187 | 64|
|1507 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9 | 17|
|1508 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10 | 47|
|1509 | \gen_slave_slots[0].gen_si_read.si_transactor_ar |axi_crossbar_v2_1_21_si_transactor | 129|
|1510 | \gen_single_thread.mux_resp_single_thread |generic_baseblocks_v2_1_0_mux_enc_201 | 105|
|1511 | \gen_slave_slots[0].gen_si_write.si_transactor_aw |axi_crossbar_v2_1_21_si_transactor__parameterized0 | 28|
|1512 | \gen_single_thread.mux_resp_single_thread |generic_baseblocks_v2_1_0_mux_enc__parameterized0_200 | 7|
|1513 | \gen_slave_slots[0].gen_si_write.splitter_aw_si |axi_crossbar_v2_1_21_splitter | 7|
|1514 | \gen_slave_slots[0].gen_si_write.wdata_router_w |axi_crossbar_v2_1_21_wdata_router | 66|
|1515 | wrouter_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo_195 | 66|
|1516 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_196 | 6|
|1517 | \gen_srls[0].gen_rep[1].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_197 | 5|
|1518 | \gen_srls[0].gen_rep[2].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_198 | 2|
|1519 | \gen_srls[0].gen_rep[3].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_199 | 8|
|1520 | \gen_slave_slots[1].gen_si_read.si_transactor_ar |axi_crossbar_v2_1_21_si_transactor__parameterized1 | 185|
|1521 | \gen_multi_thread.arbiter_resp_inst |axi_crossbar_v2_1_21_arbiter_resp_194 | 119|
|1522 | \gen_multi_thread.mux_resp_multi_thread |generic_baseblocks_v2_1_0_mux_enc | 40|
|1523 | \gen_slave_slots[1].gen_si_write.si_transactor_aw |axi_crossbar_v2_1_21_si_transactor__parameterized2 | 89|
|1524 | \gen_multi_thread.arbiter_resp_inst |axi_crossbar_v2_1_21_arbiter_resp | 55|
|1525 | \gen_multi_thread.mux_resp_multi_thread |generic_baseblocks_v2_1_0_mux_enc__parameterized0 | 8|
|1526 | \gen_slave_slots[1].gen_si_write.splitter_aw_si |axi_crossbar_v2_1_21_splitter_188 | 7|
|1527 | \gen_slave_slots[1].gen_si_write.wdata_router_w |axi_crossbar_v2_1_21_wdata_router_189 | 49|
|1528 | wrouter_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo | 49|
|1529 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl | 2|
|1530 | \gen_srls[0].gen_rep[1].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_191 | 2|
|1531 | \gen_srls[0].gen_rep[2].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_192 | 2|
|1532 | \gen_srls[0].gen_rep[3].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_193 | 8|
|1533 | splitter_aw_mi |axi_crossbar_v2_1_21_splitter_190 | 3|
|1534 | m01_couplers |m01_couplers_imp_FF3AZQ | 1062|
|1535 | auto_pc |axi4_subsys_auto_pc_0 | 1062|
|1536 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_151 | 1062|
|1537 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_152 | 1062|
|1538 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_153 | 177|
|1539 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_170 | 19|
|1540 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_171 | 156|
|1541 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_172 | 69|
|1542 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_173 | 81|
|1543 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_154 | 72|
|1544 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_168 | 53|
|1545 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_169 | 15|
|1546 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_155 | 519|
|1547 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_164 | 193|
|1548 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_165 | 187|
|1549 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_166 | 20|
|1550 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_167 | 119|
|1551 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_156 | 190|
|1552 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_160 | 28|
|1553 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_161 | 152|
|1554 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_162 | 68|
|1555 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_163 | 80|
|1556 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_157 | 103|
|1557 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_158 | 61|
|1558 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_159 | 18|
|1559 | m02_couplers |m02_couplers_imp_L8N2BP | 1062|
|1560 | auto_pc |axi4_subsys_auto_pc_1 | 1062|
|1561 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_128 | 1062|
|1562 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_129 | 1062|
|1563 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_130 | 177|
|1564 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_147 | 19|
|1565 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_148 | 156|
|1566 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_149 | 69|
|1567 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_150 | 81|
|1568 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_131 | 72|
|1569 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_145 | 53|
|1570 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_146 | 15|
|1571 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_132 | 519|
|1572 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_141 | 193|
|1573 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_142 | 187|
|1574 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_143 | 20|
|1575 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_144 | 119|
|1576 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_133 | 190|
|1577 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_137 | 28|
|1578 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_138 | 152|
|1579 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_139 | 68|
|1580 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_140 | 80|
|1581 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_134 | 103|
|1582 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_135 | 61|
|1583 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_136 | 18|
|1584 | m03_couplers |m03_couplers_imp_1MMZOD7 | 1062|
|1585 | auto_pc |axi4_subsys_auto_pc_2 | 1062|
|1586 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_105 | 1062|
|1587 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_106 | 1062|
|1588 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_107 | 177|
|1589 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_124 | 19|
|1590 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_125 | 156|
|1591 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_126 | 69|
|1592 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_127 | 81|
|1593 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_108 | 72|
|1594 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_122 | 53|
|1595 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_123 | 15|
|1596 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_109 | 519|
|1597 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_118 | 193|
|1598 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_119 | 187|
|1599 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_120 | 20|
|1600 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_121 | 119|
|1601 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_110 | 190|
|1602 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_114 | 28|
|1603 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_115 | 152|
|1604 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_116 | 68|
|1605 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_117 | 80|
|1606 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_111 | 103|
|1607 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_112 | 61|
|1608 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_113 | 18|
|1609 | m04_couplers |m04_couplers_imp_1FSUCEB | 1062|
|1610 | auto_pc |axi4_subsys_auto_pc_3 | 1062|
|1611 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_82 | 1062|
|1612 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_83 | 1062|
|1613 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_84 | 177|
|1614 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_101 | 19|
|1615 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_102 | 156|
|1616 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_103 | 69|
|1617 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_104 | 81|
|1618 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_85 | 72|
|1619 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_99 | 53|
|1620 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_100 | 15|
|1621 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_86 | 519|
|1622 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_95 | 193|
|1623 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_96 | 187|
|1624 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_97 | 20|
|1625 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_98 | 119|
|1626 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_87 | 190|
|1627 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_91 | 28|
|1628 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_92 | 152|
|1629 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_93 | 68|
|1630 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_94 | 80|
|1631 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_88 | 103|
|1632 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_89 | 61|
|1633 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_90 | 18|
|1634 | m05_couplers |m05_couplers_imp_ADRT99 | 1062|
|1635 | auto_pc |axi4_subsys_auto_pc_4 | 1062|
|1636 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_59 | 1062|
|1637 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_60 | 1062|
|1638 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_61 | 177|
|1639 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_78 | 19|
|1640 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_79 | 156|
|1641 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_80 | 69|
|1642 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_81 | 81|
|1643 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_62 | 72|
|1644 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_76 | 53|
|1645 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_77 | 15|
|1646 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_63 | 519|
|1647 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_72 | 193|
|1648 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_73 | 187|
|1649 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_74 | 20|
|1650 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_75 | 119|
|1651 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_64 | 190|
|1652 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_68 | 28|
|1653 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_69 | 152|
|1654 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_70 | 68|
|1655 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_71 | 80|
|1656 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_65 | 103|
|1657 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_66 | 61|
|1658 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_67 | 18|
|1659 | m06_couplers |m06_couplers_imp_Q7JFB2 | 1062|
|1660 | auto_pc |axi4_subsys_auto_pc_5 | 1062|
|1661 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter | 1062|
|1662 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s | 1062|
|1663 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel | 177|
|1664 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm | 19|
|1665 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_56 | 156|
|1666 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_57 | 69|
|1667 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_58 | 81|
|1668 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel | 72|
|1669 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1 | 53|
|1670 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2 | 15|
|1671 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice | 519|
|1672 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice | 193|
|1673 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_55 | 187|
|1674 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1 | 20|
|1675 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2 | 119|
|1676 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel | 190|
|1677 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm | 28|
|1678 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator | 152|
|1679 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd | 68|
|1680 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd | 80|
|1681 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel | 103|
|1682 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo | 61|
|1683 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0 | 18|
|1684 | s00_couplers |s00_couplers_imp_IY3DNS | 0|
|1685 | auto_pc |axi4_subsys_auto_pc_6 | 0|
|1686 | axi_iic_1 |axi4_subsys_axi_iic_1_0 | 882|
|1687 | U0 |axi_iic | 882|
|1688 | X_IIC |iic | 882|
|1689 | DYN_MASTER_I |dynamic_master | 33|
|1690 | FILTER_I |filter | 11|
|1691 | SCL_DEBOUNCE |debounce | 6|
|1692 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_54 | 6|
|1693 | SDA_DEBOUNCE |debounce_52 | 5|
|1694 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_53 | 5|
|1695 | IIC_CONTROL_I |iic_control | 285|
|1696 | BITCNT |upcnt_n__parameterized0 | 15|
|1697 | CLKCNT |upcnt_n | 34|
|1698 | I2CDATA_REG |shift8 | 18|
|1699 | I2CHEADER_REG |shift8_50 | 23|
|1700 | SETUP_CNT |upcnt_n_51 | 25|
|1701 | READ_FIFO_I |SRL_FIFO__parameterized0 | 32|
|1702 | REG_INTERFACE_I |reg_interface | 200|
|1703 | WRITE_FIFO_CTRL_I |SRL_FIFO__parameterized1 | 21|
|1704 | WRITE_FIFO_I |SRL_FIFO | 33|
|1705 | X_AXI_IPIF_SSP1 |axi_ipif_ssp1 | 263|
|1706 | AXI_LITE_IPIF_I |axi_lite_ipif__parameterized1 | 215|
|1707 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized1 | 215|
|1708 | I_DECODER |address_decoder__parameterized1 | 101|
|1709 | X_INTERRUPT_CONTROL |interrupt_control__parameterized0 | 31|
|1710 | X_SOFT_RESET |axi_iic_v2_0_23_soft_reset | 13|
|1711 | axi_quad_spi_0 |axi4_subsys_axi_quad_spi_0_0 | 1614|
|1712 | U0 |axi_quad_spi | 1614|
|1713 | \NO_DUAL_QUAD_MODE.QSPI_NORMAL |axi_quad_spi_top | 1614|
|1714 | \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I |axi_lite_ipif__parameterized2 | 213|
|1715 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized2 | 213|
|1716 | I_DECODER |address_decoder__parameterized2 | 124|
|1717 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized4 | 1|
|1718 | \MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized14 | 1|
|1719 | \MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized15 | 1|
|1720 | \MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized16 | 1|
|1721 | \MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized17 | 1|
|1722 | \MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized18 | 1|
|1723 | \MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized5 | 1|
|1724 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized6 | 1|
|1725 | \MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized7 | 1|
|1726 | \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized8 | 1|
|1727 | \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized9 | 1|
|1728 | \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized10 | 1|
|1729 | \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized11 | 1|
|1730 | \MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized12 | 1|
|1731 | \MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized13 | 1|
|1732 | \MEM_DECODE_GEN[1].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized21 | 1|
|1733 | \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized23 | 1|
|1734 | \MEM_DECODE_GEN[1].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized24 | 1|
|1735 | \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized27 | 1|
|1736 | \MEM_DECODE_GEN[2].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized21_46 | 1|
|1737 | \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized23_47 | 1|
|1738 | \MEM_DECODE_GEN[2].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized24_48 | 1|
|1739 | \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized27_49 | 1|
|1740 | \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I |qspi_core_interface | 1398|
|1741 | \FIFO_EXISTS.RX_FIFO_II |xpm_fifo_async__parameterized3 | 364|
|1742 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized1 | 364|
|1743 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized1 | 70|
|1744 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized2__3 | 18|
|1745 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized3 | 33|
|1746 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized2 | 18|
|1747 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized4 | 23|
|1748 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized7_34 | 8|
|1749 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized2_35 | 12|
|1750 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_36 | 9|
|1751 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized2_37 | 7|
|1752 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_38 | 7|
|1753 | \gen_fwft.rdpp1_inst |xpm_counter_updn__parameterized9_39 | 10|
|1754 | rdp_inst |xpm_counter_updn__parameterized10_40 | 25|
|1755 | rdpp1_inst |xpm_counter_updn__parameterized11_41 | 8|
|1756 | rst_d1_inst |xpm_fifo_reg_bit_42 | 2|
|1757 | wrp_inst |xpm_counter_updn__parameterized10_43 | 12|
|1758 | wrpp1_inst |xpm_counter_updn__parameterized11_44 | 8|
|1759 | wrpp2_inst |xpm_counter_updn__parameterized8_45 | 8|
|1760 | xpm_fifo_rst_inst |xpm_fifo_rst__parameterized0__xdcDup__1 | 46|
|1761 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__parameterized0__6 | 2|
|1762 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__parameterized0 | 2|
|1763 | CONTROL_REG_I |qspi_cntrl_reg | 15|
|1764 | \FIFO_EXISTS.CLK_CROSS_I |cross_clk_sync_fifo_1 | 83|
|1765 | \FIFO_EXISTS.FIFO_IF_MODULE_I |qspi_fifo_ifmodule | 9|
|1766 | \FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC |cdc_sync__parameterized6 | 3|
|1767 | \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC |cdc_sync__parameterized6_28 | 3|
|1768 | \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I |axi_quad_spi_v3_2_19_counter_f | 9|
|1769 | \FIFO_EXISTS.TX_FIFO_II |async_fifo_fg__parameterized1 | 375|
|1770 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async__parameterized5 | 366|
|1771 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized2 | 366|
|1772 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized1__1 | 70|
|1773 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized2__1 | 18|
|1774 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized3__1 | 33|
|1775 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized2__2 | 18|
|1776 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized4__1 | 23|
|1777 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized7 | 8|
|1778 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized2 | 13|
|1779 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized3 | 9|
|1780 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized2_29 | 7|
|1781 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_30 | 7|
|1782 | \gen_fwft.rdpp1_inst |xpm_counter_updn__parameterized9 | 10|
|1783 | rdp_inst |xpm_counter_updn__parameterized10 | 25|
|1784 | rdpp1_inst |xpm_counter_updn__parameterized11 | 8|
|1785 | rst_d1_inst |xpm_fifo_reg_bit_31 | 3|
|1786 | wrp_inst |xpm_counter_updn__parameterized10_32 | 12|
|1787 | wrpp1_inst |xpm_counter_updn__parameterized11_33 | 8|
|1788 | wrpp2_inst |xpm_counter_updn__parameterized8 | 8|
|1789 | xpm_fifo_rst_inst |xpm_fifo_rst__parameterized0 | 46|
|1790 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__parameterized0__4 | 2|
|1791 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__parameterized0__5 | 2|
|1792 | INTERRUPT_CONTROL_I |interrupt_control__parameterized1 | 33|
|1793 | \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I |qspi_mode_0_module | 364|
|1794 | RESET_SYNC_AXI_SPI_CLK_INST |reset_sync_module | 3|
|1795 | SOFT_RESET_I |axi_quad_spi_v3_2_19_soft_reset | 39|
|1796 | \STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I |qspi_status_slave_sel_reg | 3|
|1797 | axi_hwicap_0 |axi4_subsys_axi_hwicap_0_0 | 1913|
|1798 | U0 |axi_hwicap | 1913|
|1799 | \ICAP_SHARED.HWICAP_CTRL_I |hwicap_shared | 1643|
|1800 | GEN_BUS2ICAP_RESET |cdc_sync__parameterized3 | 4|
|1801 | IPIC_IF_I |axi_hwicap_v3_0_24_ipic_if | 1341|
|1802 | BUS2ICAP_SIZE_REGISTER_PROCESS |cdc_sync__parameterized1 | 48|
|1803 | FIFO_RST_CDC_PROCESS |cdc_sync__parameterized5 | 5|
|1804 | ICAP2BUS_STATUS_REGISTER_PROCESS |cdc_sync__parameterized2 | 128|
|1805 | ICAP2PLB_SYNCH1 |cdc_sync__parameterized3_7 | 4|
|1806 | ICAP2PLB_SYNCH2 |cdc_sync__parameterized3_8 | 6|
|1807 | ICAP2PLB_SYNCH3 |cdc_sync__parameterized3_9 | 4|
|1808 | ICAP2PLB_SYNCH4 |cdc_sync__parameterized3_10 | 4|
|1809 | ICAP2PLB_SYNCH5 |cdc_sync__parameterized1_11 | 48|
|1810 | PLB2ICAP_SYNCH1 |cdc_sync__parameterized3_12 | 6|
|1811 | PLB2ICAP_SYNCH2 |cdc_sync__parameterized3_13 | 5|
|1812 | PLB2ICAP_SYNCH3 |cdc_sync__parameterized3_14 | 6|
|1813 | \RD_FIFO.RDDATA_FIFO_I |async_fifo_fg__parameterized0 | 504|
|1814 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async__parameterized1 | 497|
|1815 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized0 | 497|
|1816 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized0 | 2|
|1817 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized0__1 | 47|
|1818 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized1__1 | 54|
|1819 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized0__2 | 47|
|1820 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized1 | 54|
|1821 | \gae_rptr_p2.rdpp2_inst |xpm_counter_updn__parameterized4 | 15|
|1822 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized3 | 15|
|1823 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized0_21 | 18|
|1824 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized1 | 8|
|1825 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized0_22 | 26|
|1826 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized1_23 | 18|
|1827 | rdp_inst |xpm_counter_updn__parameterized5 | 18|
|1828 | rdpp1_inst |xpm_counter_updn__parameterized6 | 15|
|1829 | rst_d1_inst |xpm_fifo_reg_bit_24 | 3|
|1830 | wrp_inst |xpm_counter_updn__parameterized5_25 | 28|
|1831 | wrpp1_inst |xpm_counter_updn__parameterized6_26 | 24|
|1832 | wrpp2_inst |xpm_counter_updn__parameterized4_27 | 15|
|1833 | xpm_fifo_rst_inst |xpm_fifo_rst | 48|
|1834 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__4 | 4|
|1835 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__5 | 4|
|1836 | \RD_FIFO.RDFULL_SYNCH |cdc_sync__parameterized4 | 4|
|1837 | \WRFIFO.WRDATA_FIFO_I |async_fifo_fg | 447|
|1838 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async | 440|
|1839 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base | 440|
|1840 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base | 2|
|1841 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__1 | 40|
|1842 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized0__3 | 47|
|1843 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray | 40|
|1844 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized0 | 47|
|1845 | \gae_rptr_p2.rdpp2_inst |xpm_counter_updn__parameterized0 | 13|
|1846 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn | 17|
|1847 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec | 9|
|1848 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized0 | 7|
|1849 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec_16 | 23|
|1850 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized0_17 | 16|
|1851 | rdp_inst |xpm_counter_updn__parameterized1 | 16|
|1852 | rdpp1_inst |xpm_counter_updn__parameterized2 | 13|
|1853 | rst_d1_inst |xpm_fifo_reg_bit | 4|
|1854 | wrp_inst |xpm_counter_updn__parameterized1_18 | 24|
|1855 | wrpp1_inst |xpm_counter_updn__parameterized2_19 | 21|
|1856 | wrpp2_inst |xpm_counter_updn__parameterized0_20 | 16|
|1857 | xpm_fifo_rst_inst |xpm_fifo_rst__xdcDup__1 | 47|
|1858 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__6 | 4|
|1859 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst | 4|
|1860 | \WRFIFO.WREMPTY_SYNCH |cdc_sync__parameterized3_15 | 5|
|1861 | icap_statemachine_I1 |icap_statemachine_shared | 289|
|1862 | INTERRUPT_CONTROL_I |interrupt_control | 19|
|1863 | XI4_LITE_I |axi_lite_ipif__parameterized0 | 217|
|1864 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized0 | 217|
|1865 | I_DECODER |address_decoder__parameterized0 | 130|
|1866 | axi_gpio_0 |axi4_subsys_axi_gpio_0_0 | 451|
|1867 | U0 |axi_gpio | 451|
|1868 | AXI_LITE_IPIF_I |axi_lite_ipif | 147|
|1869 | I_SLAVE_ATTACHMENT |slave_attachment | 147|
|1870 | I_DECODER |address_decoder | 71|
|1871 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f | 1|
|1872 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized1 | 1|
|1873 | gpio_core_1 |GPIO_Core | 269|
|1874 | \Dual.INPUT_DOUBLE_REGS5 |cdc_sync__parameterized0 | 96|
|1875 | common_regs |common_IdVersion_regs | 233|
|1876 | Xmlversion |ipbus_syncreg_v__parameterized0 | 30|
|1877 | rsync |syncreg_r_6 | 28|
|1878 | buildversion |ipbus_syncreg_v__parameterized0_2 | 31|
|1879 | rsync |syncreg_r_5 | 29|
|1880 | dna_regs |ipbus_syncreg_v__parameterized0_3 | 49|
|1881 | rsync |syncreg_r_4 | 47|
|1882 | fpga_dna |dna_reader | 108|
|1883 | module_id_reg |ipbus_syncreg_v | 15|
|1884 | rsync |syncreg_r | 13|
|1885 | ipbus |ipbus_rod | 8059|
|1886 | clocks |clocks_7s_extphy | 102|
|1887 | clkdiv |ipbus_clock_div | 43|
|1888 | stretch |led_stretcher | 53|
|1889 | clkdiv |ipbus_clock_div_1 | 30|
|1890 | example_clocks |ethernet_mac_rgmii_example_design_clocks | 20|
|1891 | lock_sync |ethernet_mac_rgmii_sync_block | 5|
|1892 | mmcm_reset_gen |ethernet_mac_rgmii_reset_sync | 5|
|1893 | clock_generator |ethernet_mac_rgmii_clk_wiz | 6|
|1894 | example_resets |ethernet_mac_rgmii_example_design_resets | 47|
|1895 | dcm_sync |ethernet_mac_rgmii_sync_block__2 | 5|
|1896 | glbl_reset_gen |ethernet_mac_rgmii_reset_sync__4 | 5|
|1897 | axi_lite_reset_gen |ethernet_mac_rgmii_reset_sync__5 | 5|
|1898 | gtx_reset_gen |ethernet_mac_rgmii_reset_sync__6 | 5|
|1899 | chk_reset_gen |ethernet_mac_rgmii_reset_sync__7 | 5|
|1900 | ipbus |ipbus_ctrl | 7314|
|1901 | trans |transactor | 869|
|1902 | cfg |transactor_cfg | 1|
|1903 | iface |transactor_if | 359|
|1904 | sm |transactor_sm | 495|
|1905 | udp_if |UDP_if | 6442|
|1906 | ipbus_rx_ram |udp_DualPortRAM_rx | 8|
|1907 | IPADDR |udp_ipaddr_block | 588|
|1908 | clock_crossing_if |udp_clock_crossing_if | 85|
|1909 | internal_ram |udp_DualPortRAM | 1|
|1910 | internal_ram_selector |udp_buffer_selector | 28|
|1911 | internal_ram_shim |udp_rxram_shim | 55|
|1912 | ipbus_tx_ram |udp_DualPortRAM_tx | 18|
|1913 | payload |udp_build_payload | 537|
|1914 | \primary_mode.ARP |udp_build_arp | 355|
|1915 | \primary_mode.RARP_block |udp_rarp_block | 389|
|1916 | \primary_mode.ping |udp_build_ping | 302|
|1917 | resend |udp_build_resend | 131|
|1918 | rx_byte_sum |udp_byte_sum | 106|
|1919 | rx_packet_parser |udp_packet_parser | 906|
|1920 | rx_ram_mux |udp_rxram_mux | 49|
|1921 | rx_ram_selector |udp_buffer_selector__parameterized0 | 165|
|1922 | rx_reset_block |udp_do_rx_reset | 26|
|1923 | rx_transactor |udp_rxtransactor_if | 7|
|1924 | status |udp_build_status | 340|
|1925 | status_buffer |udp_status_buffer | 738|
|1926 | tx_byte_sum |udp_byte_sum_0 | 94|
|1927 | tx_main |udp_tx_mux | 811|
|1928 | tx_ram_selector |udp_buffer_selector__parameterized1 | 256|
|1929 | tx_transactor |udp_txtransactor_if | 434|
|1930 | slaves |ipbus_example | 4|
|1931 | slave3 |ipbus_axi4_bridge | 4|
|1932 | trimac_fifo_block |eth_7s_rgmii | 572|
|1933 | rx_mac_reset_gen |ethernet_mac_rgmii_reset_sync__2 | 5|
|1934 | tx_mac_reset_gen |ethernet_mac_rgmii_reset_sync__3 | 5|
|1935 | axi_lite_controller |ethernet_mac_rgmii_axi_lite_sm | 327|
|1936 | update_speed_sync_inst |ethernet_mac_rgmii_sync_block__1 | 5|
|1937 | trimac_sup_block |ethernet_mac_rgmii_support | 159|
|1938 | tri_mode_ethernet_mac_support_resets_i |ethernet_mac_rgmii_support_resets | 23|
|1939 | idelayctrl_reset_gen |ethernet_mac_rgmii_reset_sync__1 | 5|
|1940 | spi_pwr |reset_count | 13|
+------+-------------------------------------------------------------------------------------+--------------------------------------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:09:32 ; elapsed = 00:12:11 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 2425 ; free virtual = 16007
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 6944 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:08:42 ; elapsed = 00:11:16 . Memory (MB): peak = 3286.914 ; gain = 563.633 ; free physical = 3746 ; free virtual = 17328
Synthesis Optimization Complete : Time (s): cpu = 00:09:36 ; elapsed = 00:12:14 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 3766 ; free virtual = 17328
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3286.914 ; gain = 0.000 ; free physical = 3684 ; free virtual = 17246
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
INFO: [Netlist 29-17] Analyzing 6040 Unisim elements for replacement
WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-35] Removing redundant IBUF, ipbus_blk/clkin1_buf, from the path connected to top-level port: CLK_125_pin
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. backplane/reset_buf
Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers.
WARNING: [Constraints 18-549] Could not create 'DRIVE' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'DRIVE' is ignored by Vivado but preserved inside the database.
Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port.
WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database.
Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port.
WARNING: [Constraints 18-549] Could not create 'SLEW' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database.
Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port.
INFO: [Chipscope 16-324] Core: ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0 UUID: 72643ffe-b86c-5856-9378-79d72128bd92
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ce_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rnw_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rpn_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3286.914 ; gain = 0.000 ; free physical = 3658 ; free virtual = 17226
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 826 instances were transformed.
(MUXCY,XORCY) => CARRY4: 18 instances
BUFGCE => BUFGCTRL: 4 instances
FD => FDRE: 248 instances
FDR => FDRE: 443 instances
IOBUF => IOBUF (IBUF, OBUFT): 24 instances
MULT_AND => LUT2: 27 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 12 instances
RAM64M => RAM64M (RAMD64E(x4)): 40 instances
RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances
SRL16 => SRL16E: 2 instances
INFO: [Common 17-83] Releasing license: Synthesis
1990 Infos, 1236 Warnings, 12 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:10:26 ; elapsed = 00:13:42 . Memory (MB): peak = 3286.914 ; gain = 830.191 ; free physical = 3871 ; free virtual = 17438
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3286.914 ; gain = 0.000 ; free physical = 3867 ; free virtual = 17435
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/top_rod_efex.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 3286.914 ; gain = 0.000 ; free physical = 3774 ; free virtual = 17358
INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_synth.rpt -pb top_rod_efex_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu May 6 00:24:56 2021...