Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date             : Thu Mar  4 18:20:32 2021
| Host             : hog-efex1.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command          : report_power -file top_rod_jfex_power_routed.rpt -pb top_rod_jfex_power_summary_routed.pb -rpx top_rod_jfex_power_routed.rpx
| Design           : top_rod_jfex
| Device           : xc7vx550tffg1927-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 10.267       |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 9.754        |
| Device Static (W)        | 0.513        |
| Effective TJA (C/W)      | 0.8          |
| Max Ambient (C)          | 76.3         |
| Junction Temperature (C) | 33.7         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     1.179 |       88 |       --- |             --- |
| Slice Logic              |     0.163 |   423111 |       --- |             --- |
|   LUT as Logic           |     0.121 |   120012 |    346400 |           34.65 |
|   Register               |     0.015 |   225599 |    692800 |           32.56 |
|   CARRY4                 |     0.012 |     9839 |    108300 |            9.08 |
|   Others                 |     0.006 |    23711 |       --- |             --- |
|   LUT as Shift Register  |     0.006 |    12475 |    174200 |            7.16 |
|   LUT as Distributed RAM |     0.002 |     1813 |    174200 |            1.04 |
|   F7/F8 Muxes            |    <0.001 |     2611 |    433200 |            0.60 |
|   BUFG                   |    <0.001 |        2 |        32 |            6.25 |
| Signals                  |     0.240 |   326473 |       --- |             --- |
| Block RAM                |     0.232 |    314.5 |      1180 |           26.65 |
| MMCM                     |     0.463 |        4 |        20 |           20.00 |
| I/O                      |     0.065 |      103 |       600 |           17.17 |
| GTH                      |     7.412 |       30 |       --- |             --- |
| XADC                     |    <0.001 |        1 |       --- |             --- |
| Static Power             |     0.513 |          |           |                 |
| Total                    |    10.267 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     2.830 |       2.551 |      0.279 |
| Vccaux    |       1.800 |     0.330 |       0.274 |      0.056 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.019 |       0.018 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.037 |       0.018 |      0.019 |
| MGTAVcc   |       1.000 |     4.181 |       4.122 |      0.058 |
| MGTAVtt   |       1.200 |     2.098 |       2.083 |      0.015 |
| MGTVccaux |       1.800 |     0.020 |       0.020 |      0.000 |
| MGTZVccl  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZAVcc  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZVcch  |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 0.8                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 1.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                                                           | Domain                                                                                                                                    | Constraint (ns) |
+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
| CLK_125_pin                                                                                                                                     | CLK_125_pin                                                                                                                               |             8.0 |
| CLK_40_pin                                                                                                                                      | CLK_40                                                                                                                                    |            25.0 |
| CLK_40_pin                                                                                                                                      | CLK_40_pin_P                                                                                                                              |            25.0 |
| FM_TXOUTCLK                                                                                                                                     | fm_interface_1/u0/I                                                                                                                       |             4.2 |
| FM_TXOUTCLK_2                                                                                                                                   | fm_interface_2/u0/I                                                                                                                       |             4.2 |
| GT_REFCLK112                                                                                                                                    | GTCLK_q112_c0p                                                                                                                            |             6.2 |
| GT_REFCLK115                                                                                                                                    | GTCLK_q115_c0p                                                                                                                            |             6.2 |
| GT_REFCLK118                                                                                                                                    | GTCLK_q118_c0p                                                                                                                            |             6.2 |
| GT_REFCLK211                                                                                                                                    | GTCLK_q211_c0p                                                                                                                            |             6.2 |
| GT_REFCLK214                                                                                                                                    | GTCLK_q214_c0p                                                                                                                            |             6.2 |
| GT_REFCLK217                                                                                                                                    | GTCLK_q217_c0p                                                                                                                            |             6.2 |
| GT_REFCLK219                                                                                                                                    | GTCLK_q219_c0p                                                                                                                            |             6.2 |
| GT_REFCLK_C1_218                                                                                                                                | GTCLK_q218_c1p                                                                                                                            |             4.2 |
| backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK    | backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK | backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK    | backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK | backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK    | backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK    |             6.2 |
| backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK | backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK |             6.2 |
| backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK     | backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK  | backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK  |             6.2 |
| backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK     | backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK     | backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK     | backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK     |             6.2 |
| backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK  | backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK  |             6.2 |
| backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK            | backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK            |             6.2 |
| backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/TXOUTCLK  | backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/TX_OUT_CLK  |             6.2 |
| backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gthe2_i/RXOUTCLK                  | backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/MGT_combined_ttc_rx_i/gt0_MGT_combined_ttc_rx_i/gt0_rxoutclk_out            |             6.2 |
| backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/TXOUTCLK                                     | backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gt0_txoutclk_out                               |             6.2 |
| clk240_clk_wiz_240                                                                                                                              | fm_interface_1/clk_blk/inst/clk240_clk_wiz_240                                                                                            |             4.2 |
| clk240_clk_wiz_240_1                                                                                                                            | fm_interface_2/clk_blk/inst/clk240_clk_wiz_240                                                                                            |             4.2 |
| clk40                                                                                                                                           | fm_interface_1/clk_blk/inst/clk40_clk_wiz_240                                                                                             |            10.0 |
| clk40_2                                                                                                                                         | fm_interface_2/clk_blk/inst/clk40_clk_wiz_240                                                                                             |            10.0 |
| clkfbout                                                                                                                                        | ipbus_blk/ipbus/example_clocks/clock_generator/clkfbout                                                                                   |             8.0 |
| clkfbout_clk_wiz_240                                                                                                                            | fm_interface_1/clk_blk/inst/clkfbout_clk_wiz_240                                                                                          |            25.0 |
| clkfbout_clk_wiz_240_1                                                                                                                          | fm_interface_2/clk_blk/inst/clkfbout_clk_wiz_240                                                                                          |            25.0 |
| clkfbout_packet_processor_clock                                                                                                                 | proc_clock_gen/inst/clkfbout_packet_processor_clock                                                                                       |            25.0 |
| clkout0                                                                                                                                         | ipbus_blk/ipbus/example_clocks/clock_generator/clkout0                                                                                    |             8.0 |
| clkout1                                                                                                                                         | ipbus_blk/ipbus/example_clocks/clock_generator/clkout1                                                                                    |            10.0 |
| clkout2                                                                                                                                         | ipbus_blk/ipbus/example_clocks/clock_generator/clkout2                                                                                    |             5.0 |
| clkout3                                                                                                                                         | ipbus_blk/ipbus/example_clocks/clock_generator/clkout3                                                                                    |            32.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK                                                      | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/tck_bs                                                                      |            33.0 |
| pp_clock_packet_processor_clock                                                                                                                 | proc_clock_gen/inst/pp_clock_packet_processor_clock                                                                                       |             6.2 |
| rgmii_rxc                                                                                                                                       | rgmii_rxc                                                                                                                                 |             8.0 |
| user_clk_out_0                                                                                                                                  | backplane/aurora_s13_l1/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_1                                                                                                                                  | backplane/aurora_s13_l2/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_10                                                                                                                                 | backplane/aurora_s5_l4/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_11                                                                                                                                 | backplane/aurora_s5_l3/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_12                                                                                                                                 | backplane/aurora_s4_l1/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_13                                                                                                                                 | backplane/aurora_s4_l2/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_14                                                                                                                                 | backplane/aurora_s4_l4/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_15                                                                                                                                 | backplane/aurora_s4_l3/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_16                                                                                                                                 | backplane/aurora_s8_l1/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_17                                                                                                                                 | backplane/aurora_s8_l2/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_18                                                                                                                                 | backplane/aurora_s8_l4/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_19                                                                                                                                 | backplane/aurora_s8_l3/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_2                                                                                                                                  | backplane/aurora_s13_l4/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_20                                                                                                                                 | backplane/aurora_s12_l1/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_21                                                                                                                                 | backplane/aurora_s12_l2/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_22                                                                                                                                 | backplane/aurora_s12_l4/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_23                                                                                                                                 | backplane/aurora_s12_l3/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_3                                                                                                                                  | backplane/aurora_s13_l3/aurora_module_i/clock_module_i/CLK                                                                                |             6.2 |
| user_clk_out_4                                                                                                                                  | backplane/aurora_s9_l1/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_5                                                                                                                                  | backplane/aurora_s9_l2/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_6                                                                                                                                  | backplane/aurora_s9_l4/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_7                                                                                                                                  | backplane/aurora_s9_l3/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_8                                                                                                                                  | backplane/aurora_s5_l1/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
| user_clk_out_9                                                                                                                                  | backplane/aurora_s5_l2/aurora_module_i/clock_module_i/CLK                                                                                 |             6.2 |
+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------------------------------+-----------+
| Name                               | Power (W) |
+------------------------------------+-----------+
| top_rod_jfex                       |     9.754 |
|   Bulk_0_64_32                     |     0.033 |
|     ILA_packet_fifo                |     0.024 |
|       U0                           |     0.024 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.008 |
|       inst                         |     0.008 |
|   Bulk_1_64_32                     |     0.035 |
|     ILA_packet_fifo                |     0.025 |
|       U0                           |     0.025 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.009 |
|       inst                         |     0.009 |
|   Bulk_2_64_32                     |     0.034 |
|     ILA_packet_fifo                |     0.024 |
|       U0                           |     0.024 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.008 |
|       inst                         |     0.008 |
|   ILA_axi_slot4_l1                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot4_l2                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot4_l3                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot4_l4                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot5_l1                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot5_l2                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot5_l3                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   ILA_axi_slot5_l4                 |     0.007 |
|     U0                             |     0.007 |
|       ila_core_inst                |     0.007 |
|   backplane                        |     7.141 |
|     aurora_s12_l1                  |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s12_l2                  |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s12_l3                  |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s12_l4                  |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s13_l1                  |     0.273 |
|       aurora_module_i              |     0.273 |
|     aurora_s13_l2                  |     0.274 |
|       aurora_module_i              |     0.273 |
|     aurora_s13_l3                  |     0.273 |
|       aurora_module_i              |     0.273 |
|     aurora_s13_l4                  |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s4_l1                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s4_l2                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s4_l3                   |     0.275 |
|       aurora_module_i              |     0.275 |
|     aurora_s4_l4                   |     0.275 |
|       aurora_module_i              |     0.275 |
|     aurora_s5_l1                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s5_l2                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s5_l3                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s5_l4                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s8_l1                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s8_l2                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s8_l3                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s8_l4                   |     0.274 |
|       aurora_module_i              |     0.274 |
|     aurora_s9_l1                   |     0.284 |
|       aurora_module_i              |     0.274 |
|       debug1.jfex_low_ila          |     0.010 |
|     aurora_s9_l2                   |     0.284 |
|       aurora_module_i              |     0.274 |
|       debug1.jfex_low_ila          |     0.010 |
|     aurora_s9_l3                   |     0.284 |
|       aurora_module_i              |     0.274 |
|       debug1.jfex_low_ila          |     0.010 |
|     aurora_s9_l4                   |     0.283 |
|       aurora_module_i              |     0.273 |
|       debug1.jfex_low_ila          |     0.010 |
|     channel_reset                  |     0.001 |
|     combined_ttc                   |     0.268 |
|       gt0_frame_check              |     0.003 |
|       ila_rx2_inst                 |     0.022 |
|       inst_regs                    |     0.004 |
|       sume_RO_Rx_support_i         |     0.239 |
|     ila_dwidth_conv                |     0.011 |
|       U0                           |     0.011 |
|     ila_dwidth_conv_s9_l1          |     0.009 |
|       U0                           |     0.009 |
|     ila_dwidth_conv_s9_l3          |     0.010 |
|       U0                           |     0.010 |
|     readout_ctrl                   |     0.204 |
|       ila_tx0_inst                 |     0.005 |
|       rod_RO_Tx_support_i          |     0.198 |
|   bkpln_control_ila                |     0.005 |
|     U0                             |     0.005 |
|       ila_core_inst                |     0.005 |
|   dbg_hub                          |     0.006 |
|     inst                           |     0.006 |
|       BSCANID.u_xsdbm_id           |     0.006 |
|   event_builder                    |     0.916 |
|     bulk_0                         |     0.019 |
|       bulkl_proc_probe             |     0.010 |
|       event_header_crc             |     0.001 |
|       status_regs                  |     0.006 |
|     bulk_1                         |     0.019 |
|       bulkl_proc_probe             |     0.010 |
|       event_header_crc             |     0.001 |
|       status_regs                  |     0.006 |
|     bulk_2                         |     0.019 |
|       bulkl_proc_probe             |     0.010 |
|       event_header_crc             |     0.001 |
|       status_regs                  |     0.006 |
|     fifo_layer                     |     0.714 |
|       ch0                          |     0.060 |
|       ch1                          |     0.061 |
|       ch10                         |     0.020 |
|       ch11                         |     0.020 |
|       ch2                          |     0.060 |
|       ch3                          |     0.046 |
|       ch4                          |     0.045 |
|       ch5                          |     0.020 |
|       ch6                          |     0.045 |
|       ch7                          |     0.046 |
|       ch8                          |     0.020 |
|       ch9                          |     0.020 |
|       gen_jfex_chan.ch12           |     0.020 |
|       gen_jfex_chan.ch13           |     0.021 |
|       gen_jfex_chan.ch14           |     0.021 |
|       gen_jfex_chan.ch15           |     0.021 |
|       gen_jfex_chan.ch16           |     0.020 |
|       gen_jfex_chan.ch17           |     0.020 |
|       gen_jfex_chan.ch18           |     0.020 |
|       gen_jfex_chan.ch19           |     0.020 |
|       gen_jfex_chan.ch20           |     0.020 |
|       gen_jfex_chan.ch21           |     0.020 |
|       gen_jfex_chan.ch22           |     0.020 |
|       gen_jfex_chan.ch23           |     0.020 |
|       gen_reg.channel_map_ila      |     0.005 |
|       gen_reg.registers            |     0.001 |
|       gen_reg.ttc_regs             |     0.004 |
|     readout_controller             |     0.045 |
|       readout_ctrl_ila2            |     0.024 |
|       ro_crc                       |     0.009 |
|     tob_processor_0                |     0.059 |
|       event_builder_0              |     0.039 |
|       gen_reg.status_regs          |     0.007 |
|       input_mux                    |     0.005 |
|       input_mux_ila                |     0.008 |
|     ttc_input                      |     0.042 |
|       bulk_ttc_fifo                |     0.009 |
|       ila_bulk_ttc_fifo            |     0.006 |
|       ila_ttc_fifo_in              |     0.008 |
|       ila_ttc_fifo_out             |     0.007 |
|       ttc_fifo                     |     0.009 |
|   fm_interface_1                   |     0.531 |
|     chan_0                         |     0.035 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.009 |
|       ram0                         |     0.005 |
|       u5                           |     0.009 |
|       u7                           |     0.007 |
|     chan_1                         |     0.035 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.009 |
|       ram0                         |     0.005 |
|       u5                           |     0.009 |
|       u7                           |     0.007 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     u0                             |     0.343 |
|       g_gt_channel[0].rxresetfsm_i |     0.001 |
|       g_gt_channel[1].rxresetfsm_i |     0.001 |
|       ila_resetfsm                 |     0.005 |
|       txresetfsm_i                 |     0.002 |
|   fm_interface_2                   |     0.531 |
|     chan_0                         |     0.037 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.010 |
|       ram0                         |     0.005 |
|       u5                           |     0.011 |
|       u7                           |     0.007 |
|     chan_1                         |     0.031 |
|       L1ID_fifo                    |     0.002 |
|       ila_fm                       |     0.009 |
|       ram0                         |     0.005 |
|       u5                           |     0.007 |
|       u7                           |     0.006 |
|     clk_blk                        |     0.118 |
|       inst                         |     0.118 |
|     u0                             |     0.345 |
|       g_gt_channel[0].rxresetfsm_i |     0.002 |
|       g_gt_channel[1].rxresetfsm_i |     0.002 |
|       ila_resetfsm                 |     0.005 |
|       txresetfsm_i                 |     0.002 |
|   ipbus_blk                        |     0.294 |
|     axi4_subsys                    |     0.025 |
|       axi4_subsys_i                |     0.024 |
|     ipbus                          |     0.268 |
|       clocks                       |     0.002 |
|       example_clocks               |     0.109 |
|       ipbus                        |     0.068 |
|       trimac_fifo_block            |     0.088 |
|   pp_out_fifo_6432                 |     0.036 |
|     ILA_packet_fifo                |     0.025 |
|       U0                           |     0.025 |
|     data_width_conv                |     0.001 |
|       inst                         |     0.001 |
|     main_fifo                      |     0.009 |
|       inst                         |     0.009 |
|   proc_clock_gen                   |     0.123 |
|     inst                           |     0.123 |
+------------------------------------+-----------+


