diff --git a/IP/bkpln_efex/clock_test_ila/clock_test_ila.xci b/IP/bkpln_efex/clock_test_ila/clock_test_ila.xci index 5fdbb94..78a844f 100644 --- a/IP/bkpln_efex/clock_test_ila/clock_test_ila.xci +++ b/IP/bkpln_efex/clock_test_ila/clock_test_ila.xci @@ -76,7 +76,7 @@ 2019 2 1 - 4 + 3 AXI4 1 0 @@ -105,7 +105,7 @@ 0 Native 1 - 4 + 3 1 0 8 @@ -846,7 +846,7 @@ 1 1 0 - 8 + 1 1 0 1 @@ -3237,7 +3237,6 @@ - diff --git a/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci b/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci index bde36d4..beefd54 100644 --- a/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci +++ b/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.xci @@ -78,7 +78,7 @@ 1 14 AXI4 - 32 + 1 0 0 virtex7 diff --git a/IP/packet_processor/ila_self_reset/ila_self_reset.xci b/IP/packet_processor/ila_self_reset/ila_self_reset.xci index 43bfa08..8a7a848 100644 --- a/IP/packet_processor/ila_self_reset/ila_self_reset.xci +++ b/IP/packet_processor/ila_self_reset/ila_self_reset.xci @@ -78,7 +78,7 @@ 1 6 AXI4 - 32 + 1 0 0 virtex7 diff --git a/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci b/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci index a78ef20..df8317b 100644 --- a/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci +++ b/IP/packet_processor/ttc_regs_ila/ttc_regs_ila.xci @@ -78,7 +78,7 @@ 1 6 AXI4 - 32 + 1 0 0 virtex7