*** Running vivado with args -log top_rod_efex.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_rod_efex.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_efex.tcl -notrace source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] Found modified *.bd files: BD/axi4_subsys.bd, will restore them... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 413233A, will use most recent tag v0.2.6. As this is an official tag, patch will be incremented to 7. INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.2.6-14-g413233a... INFO: [Hog:Msg-0] Opening project rod_efex... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1840.148 ; gain = 252.977 ; free physical = 1869 ; free virtual = 21164 INFO: [Hog:Msg-0] Checking rod_efex list files... INFO: [Hog:Msg-0] List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Top_new//rod_efex/hog.conf matches project. Nothing to do INFO: [Hog:Msg-0] List files and hog.conf match project. All ok! INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for 413233a is: v0.2.6-14-g413233a INFO: [Hog:Msg-0] Found last SHA for rod_efex: 413233a INFO: [Hog:Msg-0] The commit in which project rod_efex was last modified is 413233a, that is 1 commits older than current commit c5b6390. INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml and replacing placeholders with xml version 00020006... INFO: [Hog:CopyXMLsFromListFile-0] 19 lines read from ./Top//rod_efex/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRod_common_IdVersion.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplane.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBackplaneRegisters.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodBulkProc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodChannel.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlash.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashChip.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodFlashSectors.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodGpio.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodHwicap.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodI2C.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodInfrastructure.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodPktCaptureRegisters.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodProcessor.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTobProc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodTTCRegisters.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/xml/L1CaloHubRodXadcMeasurements.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 19 file/s copied INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRod.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRod.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRod_common_IdVersion.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRod_common_IdVersion.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBackplane.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBackplane.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBackplaneRegisters.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBackplaneRegisters.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodBulkProc.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodBulkProc.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodChannel.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodChannel.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlash.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlashChip.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodFlashSectors.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodGpio.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodHwicap.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodI2C.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodInfrastructure.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodPktCaptureRegisters.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodPktCaptureRegisters.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodProcessor.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodProcessor.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodTobProc.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodTobProc.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/xml/L1CaloHubRodTTCRegisters.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_decode/ipbus_decode_L1CaloHubRodTTCRegisters.vhd match. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodXadc.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloHubRodXadcMeasurements.xml as no VHDL file was specified. INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 10/09/2021 at 00:01:42 Firmware date and time: '09092021', '00224821' Global SHA: 413233a, VER: 0.2.7 Constraints SHA: 2A14E22, VER: 0.1.16 IPbus XML SHA: 76E5CF5, VER: 0.2.6 Top SHA: D6ADB1E, VER: 0.1.17 Hog SHA: 30B4E38, VER: 4.16.2 --- Libraries --- rod_efex SHA: 413233A, VER: 0.2.7 --- External Libraries --- ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2021.2-2 in .gitlab-ci.yml. INFO: [Hog:Msg-0] All done. Command: synth_design -top top_rod_efex -part xc7vx550tffg1927-2 -fanout_limit 400 -directive PerformanceOptimized -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3066 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:53 . Memory (MB): peak = 2488.320 ; gain = 200.715 ; free physical = 1143 ; free virtual = 20463 --------------------------------------------------------------------------------- WARNING: [Synth 8-2048] function gpo_bit_used does not always return a value [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1139] WARNING: [Synth 8-1090] 'jtag_axi_v1_2_10_jtag_axi' is not compiled in library jtag_axi [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:57] INFO: [Synth 8-638] synthesizing module 'top_rod_efex' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:333] Parameter Module_ID bound to: 32'b01000000000000000000000011101101 Parameter GLOBAL_DATE bound to: 32'b00001001000010010010000000100001 Parameter GLOBAL_TIME bound to: 32'b00000000001000100100100000100001 Parameter GLOBAL_VER bound to: 32'b00000000000000100000000000000111 Parameter GLOBAL_SHA bound to: 32'b00000100000100110010001100111010 Parameter TOP_VER bound to: 32'b00000000000000010000000000010001 Parameter TOP_SHA bound to: 32'b00001101011010101101101100011110 Parameter CON_VER bound to: 32'b00000000000000010000000000010000 Parameter CON_SHA bound to: 32'b00000010101000010100111000100010 Parameter HOG_VER bound to: 32'b00000100000100000000000000000010 Parameter HOG_SHA bound to: 32'b00000011000010110100111000111000 Parameter XML_SHA bound to: 32'b00000111011011100101110011110101 Parameter XML_VER bound to: 32'b00000000000000100000000000000110 Parameter ROD_EFEX_SHA bound to: 32'b00000100000100110010001100111010 Parameter ROD_EFEX_VER bound to: 32'b00000000000000100000000000000111 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter tob_0_flx_bp_link bound to: 0 - type: integer Parameter bulk_0_flx_bp_link bound to: 1 - type: integer Parameter bulk_1_flx_bp_link bound to: 2 - type: integer Parameter bulk_2_flx_bp_link bound to: 3 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter max_count bound to: 32'b00000000000000001111111111111111 INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:8' bound to instance 'reset_top' of component 'system_top_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1834] INFO: [Synth 8-638] synthesizing module 'system_top_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21] Parameter max_count bound to: 65535 - type: integer INFO: [Synth 8-256] done synthesizing module 'system_top_reset' (1#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21] Parameter max_count bound to: 32'b00000010011000100101101000000000 INFO: [Synth 8-3491] module 'system_top_reset' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:8' bound to instance 'phy_reset' of component 'system_top_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1853] INFO: [Synth 8-638] synthesizing module 'system_top_reset__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21] Parameter max_count bound to: 40000000 - type: integer INFO: [Synth 8-256] done synthesizing module 'system_top_reset__parameterized1' (1#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/system_top_reset.vhd:21] INFO: [Synth 8-3491] module 'packet_processor_clock' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/packet_processor_clock_stub.vhdl:5' bound to instance 'proc_clock_gen' of component 'packet_processor_clock' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1872] INFO: [Synth 8-638] synthesizing module 'packet_processor_clock' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/packet_processor_clock_stub.vhdl:15] INFO: [Synth 8-3491] module 'vio_top' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_top_stub.vhdl:5' bound to instance 'top_vio' of component 'vio_top' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1884] INFO: [Synth 8-638] synthesizing module 'vio_top' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_top_stub.vhdl:26] WARNING: [Synth 8-5640] Port 'pkt_clk' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:357] WARNING: [Synth 8-5640] Port 'pkt_aresetn' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:357] WARNING: [Synth 8-5640] Port 'rod_gp_led' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:357] WARNING: [Synth 8-5640] Port 'fp_gp_led_b' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:357] Parameter GLOBAL_DATE bound to: 151592993 - type: integer Parameter GLOBAL_TIME bound to: 2246689 - type: integer Parameter GLOBAL_VER bound to: 131079 - type: integer Parameter GLOBAL_SHA bound to: 68363066 - type: integer Parameter TOP_VER bound to: 65553 - type: integer Parameter TOP_SHA bound to: 225106718 - type: integer Parameter CON_VER bound to: 65552 - type: integer Parameter CON_SHA bound to: 44125730 - type: integer Parameter HOG_VER bound to: 68157442 - type: integer Parameter HOG_SHA bound to: 51072568 - type: integer Parameter XML_SHA bound to: 124673269 - type: integer Parameter XML_VER bound to: 131078 - type: integer Parameter ROD_EFEX_SHA bound to: 68363066 - type: integer Parameter ROD_EFEX_VER bound to: 131079 - type: integer Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter Module_ID bound to: 1073742061 - type: integer Parameter BuildTimeAndDate bound to: 151592993 - type: integer Parameter FirmwareVersion bound to: 68363066 - type: integer INFO: [Synth 8-3491] module 'ROD_system' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:40' bound to instance 'ipbus_blk' of component 'ROD_system' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1907] INFO: [Synth 8-638] synthesizing module 'ROD_system' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:207] Parameter GLOBAL_DATE bound to: 151592993 - type: integer Parameter GLOBAL_TIME bound to: 2246689 - type: integer Parameter GLOBAL_VER bound to: 131079 - type: integer Parameter GLOBAL_SHA bound to: 68363066 - type: integer Parameter TOP_VER bound to: 65553 - type: integer Parameter TOP_SHA bound to: 225106718 - type: integer Parameter CON_VER bound to: 65552 - type: integer Parameter CON_SHA bound to: 44125730 - type: integer Parameter HOG_VER bound to: 68157442 - type: integer Parameter HOG_SHA bound to: 51072568 - type: integer Parameter XML_SHA bound to: 124673269 - type: integer Parameter XML_VER bound to: 131078 - type: integer Parameter ROD_EFEX_SHA bound to: 68363066 - type: integer Parameter ROD_EFEX_VER bound to: 131079 - type: integer Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter Module_ID bound to: 1073742061 - type: integer Parameter BuildTimeAndDate bound to: 151592993 - type: integer Parameter FirmwareVersion bound to: 68363066 - type: integer INFO: [Synth 8-3491] module 'addr_sel_rom' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:59' bound to instance 'address_sel' of component 'addr_sel_rom' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:562] INFO: [Synth 8-638] synthesizing module 'addr_sel_rom' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:69] INFO: [Synth 8-256] done synthesizing module 'addr_sel_rom' (2#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/addr_sel_rom.vhd:69] INFO: [Synth 8-3491] module 'vio_ip_address' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_ip_address_stub.vhdl:5' bound to instance 'ip_addr_probe' of component 'vio_ip_address' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:578] INFO: [Synth 8-638] synthesizing module 'vio_ip_address' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_ip_address_stub.vhdl:16] Parameter GLOBAL_DATE bound to: 151592993 - type: integer Parameter GLOBAL_TIME bound to: 2246689 - type: integer Parameter GLOBAL_VER bound to: 131079 - type: integer Parameter GLOBAL_SHA bound to: 68363066 - type: integer Parameter TOP_VER bound to: 65553 - type: integer Parameter TOP_SHA bound to: 225106718 - type: integer Parameter CON_VER bound to: 65552 - type: integer Parameter CON_SHA bound to: 44125730 - type: integer Parameter HOG_VER bound to: 68157442 - type: integer Parameter HOG_SHA bound to: 51072568 - type: integer Parameter XML_SHA bound to: 124673269 - type: integer Parameter XML_VER bound to: 131078 - type: integer Parameter ROD_EFEX_SHA bound to: 68363066 - type: integer Parameter ROD_EFEX_VER bound to: 131079 - type: integer Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden_rod bound to: 0 - type: integer Parameter Module_ID bound to: 1073742061 - type: integer Parameter BuildTimeAndDate bound to: 151592993 - type: integer Parameter FirmwareVersion bound to: 68363066 - type: integer INFO: [Synth 8-3491] module 'common_IdVersion_regs' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:37' bound to instance 'common_regs' of component 'common_IdVersion_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:603] INFO: [Synth 8-638] synthesizing module 'common_IdVersion_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:80] Parameter GLOBAL_DATE bound to: 151592993 - type: integer Parameter GLOBAL_TIME bound to: 2246689 - type: integer Parameter GLOBAL_VER bound to: 131079 - type: integer Parameter GLOBAL_SHA bound to: 68363066 - type: integer Parameter TOP_VER bound to: 65553 - type: integer Parameter TOP_SHA bound to: 225106718 - type: integer Parameter CON_VER bound to: 65552 - type: integer Parameter CON_SHA bound to: 44125730 - type: integer Parameter HOG_VER bound to: 68157442 - type: integer Parameter HOG_SHA bound to: 51072568 - type: integer Parameter XML_SHA bound to: 124673269 - type: integer Parameter XML_VER bound to: 131078 - type: integer Parameter ROD_EFEX_SHA bound to: 68363066 - type: integer Parameter ROD_EFEX_VER bound to: 131079 - type: integer Parameter ROD_JFEX_SHA bound to: 32'b00000000000000000000000000001100 Parameter ROD_JFEX_VER bound to: 32'b00000000000000000000000000001101 Parameter jfex_rod bound to: 0 - type: integer Parameter efex_rod bound to: 1 - type: integer Parameter golden bound to: 0 - type: integer Parameter Module_ID bound to: 1073742061 - type: integer Parameter BuildTimeAndDate bound to: 151592993 - type: integer Parameter FirmwareVersion bound to: 68363066 - type: integer WARNING: [Synth 8-3819] Generic 'golden_rod' not present in instantiated entity will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:603] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 6 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (3#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82] INFO: [Synth 8-638] synthesizing module 'syncreg_r' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58] Parameter SIZE bound to: 32 - type: integer INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-5534] Detected attribute (* async_reg = "yes" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:60] INFO: [Synth 8-256] done synthesizing module 'syncreg_r' (4#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/syncreg_r.vhd:58] INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:142] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:143] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:155] INFO: [Synth 8-638] synthesizing module 'ipbus_syncreg_v__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:66] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:67] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:68] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:82] INFO: [Synth 8-256] done synthesizing module 'ipbus_syncreg_v__parameterized0' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_syncreg_v.vhd:74] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:224] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:226] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:244] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:246] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (6#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:258] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:260] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:287] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:289] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:303] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:305] INFO: [Synth 8-3491] module 'dna_reader' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:30' bound to instance 'fpga_dna' of component 'dna_reader' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:309] INFO: [Synth 8-638] synthesizing module 'dna_reader' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38] Parameter SIM_DNA_VALUE bound to: 60'b000100100011010001010110011110001001101010111100110111100010 INFO: [Synth 8-113] binding component instance 'DNA_PORT_inst' to cell 'DNA_PORT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:67] WARNING: [Synth 8-614] signal 'reset_reg' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:84] INFO: [Synth 8-256] done synthesizing module 'dna_reader' (7#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_reader.vhd:38] INFO: [Synth 8-3491] module 'dna_decoder' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:34' bound to instance 'fpga_dna_decode' of component 'dna_decoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:316] INFO: [Synth 8-638] synthesizing module 'dna_decoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:46] INFO: [Synth 8-256] done synthesizing module 'dna_decoder' (8#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dna_decoder.vhd:46] INFO: [Synth 8-256] done synthesizing module 'common_IdVersion_regs' (9#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/common_IdVersion_regs.vhd:80] INFO: [Synth 8-3491] module 'ipbus_rod' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:139' bound to instance 'ipbus' of component 'ipbus_rod' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:650] INFO: [Synth 8-638] synthesizing module 'ipbus_rod' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:214] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_clocks' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:60' bound to instance 'example_clocks' of component 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:679] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_clocks' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79] Parameter CE_TYPE bound to: SYNC - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'bufg_clkin1' to cell 'BUFGCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:154] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'lock_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:157] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84] Parameter INITIALISE bound to: 1'b0 Parameter DEPTH bound to: 5 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg0' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:113] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:126] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:138] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:150] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:162] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_sync_block' (10#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:84] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'mmcm_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:178] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87] Parameter INITIALISE bound to: 1'b1 Parameter DEPTH bound to: 5 - type: integer Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_PRE_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync0' to cell 'FDPE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:109] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_PRE_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync1' to cell 'FDPE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:121] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_PRE_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync2' to cell 'FDPE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:133] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_PRE_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync3' to cell 'FDPE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:145] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_PRE_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync4' to cell 'FDPE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:157] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_reset_sync' (11#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:87] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_clk_wiz' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:71' bound to instance 'clock_generator' of component 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:190] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_clk_wiz' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT1_DIVIDE bound to: 10 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT3_DIVIDE bound to: 32 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter REF_JITTER2 bound to: 0.000000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCME2_ADV' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:122] Parameter CE_TYPE bound to: SYNC - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:201] Parameter CE_TYPE bound to: SYNC - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'clkout2_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:207] Parameter CE_TYPE bound to: SYNC - type: string Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_I_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: ULTRASCALE - type: string Parameter STARTUP_SYNC bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'clkout3_buf' to cell 'BUFGCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:213] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:219] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_clk_wiz' (12#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_clk_wiz.vhd:86] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_clocks' (13#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_clocks.vhd:79] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_example_design_resets' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:57' bound to instance 'example_resets' of component 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:711] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_example_design_resets' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'dcm_sync' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:131] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'glbl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:145] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'axi_lite_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:159] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'gtx_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:187] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'chk_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:219] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_example_design_resets' (14#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_example_design_resets.vhd:84] INFO: [Synth 8-3491] module 'eth_7s_rgmii' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:94' bound to instance 'trimac_fifo_block' of component 'eth_7s_rgmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:903] INFO: [Synth 8-638] synthesizing module 'eth_7s_rgmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212] WARNING: [Synth 8-5640] Port 'rx_statistics_vector' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220] WARNING: [Synth 8-5640] Port 'rx_statistics_valid' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220] WARNING: [Synth 8-5640] Port 'tx_statistics_vector' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220] WARNING: [Synth 8-5640] Port 'tx_statistics_valid' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:220] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:68' bound to instance 'trimac_sup_block' of component 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:528] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_support_resets' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:62' bound to instance 'tri_mode_ethernet_mac_support_resets_i' of component 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:284] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_support_resets' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'idelayctrl_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:108] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support_resets' (15#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support_resets.vhd:72] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-113] binding component instance 'tri_mode_ethernet_mac_idelayctrl_common_i' to cell 'IDELAYCTRL' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:295] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:5' bound to instance 'tri_mode_ethernet_mac_i' of component 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:309] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ethernet_mac_rgmii_stub.vhdl:67] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_support' (16#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_support.vhd:164] INFO: [Synth 8-3491] module 'rgmii_rx_fifo_2' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:5' bound to instance 'trimac_read_fifo_2' of component 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:642] INFO: [Synth 8-638] synthesizing module 'rgmii_rx_fifo_2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/rgmii_rx_fifo_2_stub.vhdl:26] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'rx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:684] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_reset_sync' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_reset_sync.vhd:67' bound to instance 'tx_mac_reset_gen' of component 'ethernet_mac_rgmii_reset_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:692] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_axi_lite_sm' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:69' bound to instance 'axi_lite_controller' of component 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:761] INFO: [Synth 8-638] synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105] INFO: [Synth 8-3491] module 'ethernet_mac_rgmii_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/common/ethernet_mac_rgmii_sync_block.vhd:67' bound to instance 'update_speed_sync_inst' of component 'ethernet_mac_rgmii_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:278] INFO: [Synth 8-256] done synthesizing module 'ethernet_mac_rgmii_axi_lite_sm' (17#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ethernet_mac_rgmii_axi_lite_sm.vhd:105] WARNING: [Synth 8-3848] Net tx_axis_fifo_tready in module/entity eth_7s_rgmii does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:138] WARNING: [Synth 8-3848] Net rx_fifo_overflow in module/entity eth_7s_rgmii does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:206] INFO: [Synth 8-256] done synthesizing module 'eth_7s_rgmii' (18#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/eth_7s_rgmii.vhd:212] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:30] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (19#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_clock_div.vhd:24] INFO: [Synth 8-638] synthesizing module 'led_stretcher' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25] Parameter WIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'led_stretcher' (20#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/led_stretcher.vhd:25] WARNING: [Synth 8-6014] Unused sequential element rctr_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:133] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (21#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/clocks_7s_rod.vhd:50] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:67] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:61] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:62] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_if_flat.vhd:65] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'udp_rarp_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:24] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:55] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:56] WARNING: [Synth 8-6014] Unused sequential element pkt_data_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:112] WARNING: [Synth 8-6014] Unused sequential element addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:145] WARNING: [Synth 8-6014] Unused sequential element tick_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:164] WARNING: [Synth 8-6014] Unused sequential element t_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:195] WARNING: [Synth 8-6014] Unused sequential element rarp_req_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:220] INFO: [Synth 8-256] done synthesizing module 'udp_rarp_block' (22#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rarp_block.vhd:24] INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:28] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:45] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:47] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:81] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:82] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:225] INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (23#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_arp.vhd:28] INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:31] WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:54] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:114] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:115] WARNING: [Synth 8-6014] Unused sequential element ping_we_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:179] WARNING: [Synth 8-6014] Unused sequential element clr_sum_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:251] WARNING: [Synth 8-6014] Unused sequential element int_valid_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:252] WARNING: [Synth 8-6014] Unused sequential element int_data_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:253] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:351] INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (24#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_ping.vhd:31] INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd:30] INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_block' (25#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd:30] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:33] WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:60] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:63] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:115] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:116] WARNING: [Synth 8-6014] Unused sequential element next_low_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:409] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:486] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (26#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_payload.vhd:33] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_resend.vhd:23] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (27#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_resend.vhd:23] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:28] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:43] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:97] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:98] WARNING: [Synth 8-6014] Unused sequential element request_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:183] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:247] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (28#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_build_status.vhd:28] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:49] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer WARNING: [Synth 8-6014] Unused sequential element bufsize_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:101] WARNING: [Synth 8-6014] Unused sequential element nbuf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:102] WARNING: [Synth 8-6014] Unused sequential element new_event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:149] WARNING: [Synth 8-6014] Unused sequential element async_ready_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:150] WARNING: [Synth 8-6014] Unused sequential element rarp_arp_ping_ipbus_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:156] WARNING: [Synth 8-6014] Unused sequential element payload_status_resend_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:158] WARNING: [Synth 8-6014] Unused sequential element got_event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:239] WARNING: [Synth 8-6014] Unused sequential element event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:240] INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (29#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_status_buffer.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_byte_sum.vhd:25] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (30#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_byte_sum.vhd:25] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_do_rx_reset.vhd:20] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (31#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_do_rx_reset.vhd:20] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_packet_parser.vhd:37] Parameter IPBUSPORT bound to: 16'b1100001101010001 Parameter SECONDARYPORT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (32#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_packet_parser.vhd:37] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:56] WARNING: [Synth 8-6014] Unused sequential element rxram_dropped_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:74] WARNING: [Synth 8-6014] Unused sequential element rxram_end_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:97] WARNING: [Synth 8-6014] Unused sequential element rxram_send_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:98] WARNING: [Synth 8-6014] Unused sequential element dia_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:154] WARNING: [Synth 8-6014] Unused sequential element addra_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:155] WARNING: [Synth 8-6014] Unused sequential element wea_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:156] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (33#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_mux.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram.vhd:22] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (34#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 1 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (35#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_shim.vhd:30] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (36#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxram_shim.vhd:30] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:22] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:36] WARNING: [Synth 8-6014] Unused sequential element byte4_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:56] WARNING: [Synth 8-6014] Unused sequential element byte3_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:57] WARNING: [Synth 8-6014] Unused sequential element byte2_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:58] WARNING: [Synth 8-6014] Unused sequential element byte1_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (37#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_rx.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 4 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (37#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:23] WARNING: [Synth 8-6014] Unused sequential element rxpayload_dropped_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:35] WARNING: [Synth 8-6014] Unused sequential element pkt_rcvd_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:36] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (38#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_rxtransactor_if_simple.vhd:23] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:22] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:57] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (39#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_dualportram_tx.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 4 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:154] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (39#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:52] Parameter INTERNAL_ONLY bound to: 1'b0 WARNING: [Synth 8-6014] Unused sequential element low_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:139] WARNING: [Synth 8-6014] Unused sequential element next_mac_tx_buf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:171] WARNING: [Synth 8-6014] Unused sequential element default_mode.ipbus_out_valid_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:675] INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (40#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_tx_mux.vhd:52] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:35] Parameter BUFWIDTH bound to: 4 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_resend_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:64] WARNING: [Synth 8-6014] Unused sequential element req_not_found_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:65] WARNING: [Synth 8-6014] Unused sequential element resend_buf_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:66] INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (41#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd:35] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:43] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:48] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:49] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (42#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:43] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (43#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_if_flat.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor.vhd:34] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_if.vhd:31] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (44#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_if.vhd:31] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_sm.vhd:39] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (45#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_sm.vhd:39] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_cfg.vhd:27] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (46#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor_cfg.vhd:27] INFO: [Synth 8-256] done synthesizing module 'transactor' (47#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/transactor.vhd:34] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (48#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd:67] INFO: [Synth 8-638] synthesizing module 'ipbus_example' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (48#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] INFO: [Synth 8-638] synthesizing module 'ipbus_axi4_bridge' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66] INFO: [Synth 8-256] done synthesizing module 'ipbus_axi4_bridge' (49#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_axi4_bridge.vhd:66] WARNING: [Synth 8-3848] Net nuke in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:33] WARNING: [Synth 8-3848] Net soft_rst in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:34] WARNING: [Synth 8-3848] Net userled in module/entity ipbus_example does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:35] INFO: [Synth 8-256] done synthesizing module 'ipbus_example' (50#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ipbus_example.vhd:60] WARNING: [Synth 8-3848] Net tx_axis_fifo_tvalid in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:537] WARNING: [Synth 8-3848] Net tx_axis_fifo_tdata in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:535] WARNING: [Synth 8-3848] Net tx_axis_fifo_tlast in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:538] WARNING: [Synth 8-3848] Net pause_val in module/entity ipbus_rod does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:565] INFO: [Synth 8-256] done synthesizing module 'ipbus_rod' (51#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/example_design/ipbus_rod.vhd:214] INFO: [Synth 8-3491] module 'axi4_subsys_wrapper' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:14' bound to instance 'axi4_subsys' of component 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:721] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_wrapper' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80] INFO: [Synth 8-3491] module 'axi4_subsys' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4596' bound to instance 'axi4_subsys_i' of component 'axi4_subsys' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:231] INFO: [Synth 8-638] synthesizing module 'axi4_subsys' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4667] INFO: [Synth 8-3491] module 'axi4_subsys_axi_emc_0_0' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:59' bound to instance 'axi_emc_0' of component 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:5341] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_emc_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_emc_inst - type: string Parameter C_AXI_CLK_PERIOD_PS bound to: 30769 - type: integer Parameter C_LFLASH_PERIOD_PS bound to: 30769 - type: integer Parameter C_LINEAR_FLASH_SYNC_BURST bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_PORT_DIFF bound to: 0 - type: integer Parameter C_S_AXI_REG_ADDR_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_REG_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_EN_REG bound to: 0 - type: integer Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer Parameter C_S_AXI_MEM0_BASEADDR bound to: 32'b01100000000000000000000000000000 Parameter C_S_AXI_MEM0_HIGHADDR bound to: 32'b01111111111111111111111111111111 Parameter C_S_AXI_MEM1_BASEADDR bound to: 32'b10110000000000000000000000000000 Parameter C_S_AXI_MEM1_HIGHADDR bound to: 32'b10111111111111111111111111111111 Parameter C_S_AXI_MEM2_BASEADDR bound to: 32'b11000000000000000000000000000000 Parameter C_S_AXI_MEM2_HIGHADDR bound to: 32'b11001111111111111111111111111111 Parameter C_S_AXI_MEM3_BASEADDR bound to: 32'b11010000000000000000000000000000 Parameter C_S_AXI_MEM3_HIGHADDR bound to: 32'b11011111111111111111111111111111 Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_MEM0_TYPE bound to: 1 - type: integer Parameter C_MEM1_TYPE bound to: 0 - type: integer Parameter C_MEM2_TYPE bound to: 0 - type: integer Parameter C_MEM3_TYPE bound to: 0 - type: integer Parameter C_MEM0_WIDTH bound to: 32 - type: integer Parameter C_MEM1_WIDTH bound to: 16 - type: integer Parameter C_MEM2_WIDTH bound to: 16 - type: integer Parameter C_MEM3_WIDTH bound to: 16 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_PAGE_SIZE bound to: 16 - type: integer Parameter C_MEM_A_MSB bound to: 31 - type: integer Parameter C_MEM_A_LSB bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_0 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_1 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_2 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_3 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer INFO: [Synth 8-3491] module 'axi_emc' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3428' bound to instance 'U0' of component 'axi_emc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:373] INFO: [Synth 8-638] synthesizing module 'axi_emc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3738] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_emc_inst - type: string Parameter C_AXI_CLK_PERIOD_PS bound to: 30769 - type: integer Parameter C_LFLASH_PERIOD_PS bound to: 30769 - type: integer Parameter C_LINEAR_FLASH_SYNC_BURST bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_PORT_DIFF bound to: 0 - type: integer Parameter C_S_AXI_REG_ADDR_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_REG_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_EN_REG bound to: 0 - type: integer Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer Parameter C_S_AXI_MEM0_BASEADDR bound to: 1610612736 - type: integer Parameter C_S_AXI_MEM0_HIGHADDR bound to: 2147483647 - type: integer Parameter C_S_AXI_MEM1_BASEADDR bound to: -1342177280 - type: integer Parameter C_S_AXI_MEM1_HIGHADDR bound to: -1073741825 - type: integer Parameter C_S_AXI_MEM2_BASEADDR bound to: -1073741824 - type: integer Parameter C_S_AXI_MEM2_HIGHADDR bound to: -805306369 - type: integer Parameter C_S_AXI_MEM3_BASEADDR bound to: -805306368 - type: integer Parameter C_S_AXI_MEM3_HIGHADDR bound to: -536870913 - type: integer Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_MEM0_TYPE bound to: 1 - type: integer Parameter C_MEM1_TYPE bound to: 0 - type: integer Parameter C_MEM2_TYPE bound to: 0 - type: integer Parameter C_MEM3_TYPE bound to: 0 - type: integer Parameter C_MEM0_WIDTH bound to: 32 - type: integer Parameter C_MEM1_WIDTH bound to: 16 - type: integer Parameter C_MEM2_WIDTH bound to: 16 - type: integer Parameter C_MEM3_WIDTH bound to: 16 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_PAGE_SIZE bound to: 16 - type: integer Parameter C_MEM_A_MSB bound to: 31 - type: integer Parameter C_MEM_A_LSB bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_0 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_1 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_2 bound to: 0 - type: integer Parameter C_PARITY_TYPE_MEM_3 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4175] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4214] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4215] INFO: [Synth 8-638] synthesizing module 'axi_emc_native_interface' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1827] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_ID_WIDTH bound to: 2 - type: integer Parameter C_S_AXI_MEM0_BASEADDR bound to: 1610612736 - type: integer Parameter C_S_AXI_MEM0_HIGHADDR bound to: 2147483647 - type: integer Parameter C_S_AXI_MEM1_BASEADDR bound to: -1342177280 - type: integer Parameter C_S_AXI_MEM1_HIGHADDR bound to: -1073741825 - type: integer Parameter C_S_AXI_MEM2_BASEADDR bound to: -1073741824 - type: integer Parameter C_S_AXI_MEM2_HIGHADDR bound to: -805306369 - type: integer Parameter C_S_AXI_MEM3_BASEADDR bound to: -805306368 - type: integer Parameter C_S_AXI_MEM3_HIGHADDR bound to: -536870913 - type: integer Parameter AXI_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111 Parameter AXI_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000001 Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_emc_addr_gen' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:614] Parameter C_S_AXI_MEM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MEM_DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi_emc_addr_gen' (52#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:614] INFO: [Synth 8-638] synthesizing module 'axi_emc_address_decode' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1250] Parameter C_S_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_ADDR_DECODE_BITS bound to: 32 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000001 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-256] done synthesizing module 'axi_emc_address_decode' (53#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1250] INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697] Parameter C_DWIDTH bound to: 33 - type: integer Parameter C_DEPTH bound to: 256 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143] Parameter C_SIZE bound to: 9 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (54#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:143] INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397] Parameter C_DEPTH bound to: 256 - type: integer Parameter C_DWIDTH bound to: 33 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (55#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:397] INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (56#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/51ce/hdl/lib_srl_fifo_v1_0_rfs.vhd:697] INFO: [Synth 8-638] synthesizing module 'axi_emc_v3_0_20_counter_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:241] Parameter C_NUM_BITS bound to: 8 - type: integer Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_emc_v3_0_20_counter_f' (57#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:241] WARNING: [Synth 8-6014] Unused sequential element last_rd_data_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:2434] WARNING: [Synth 8-6014] Unused sequential element single_transfer_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:2452] INFO: [Synth 8-256] done synthesizing module 'axi_emc_native_interface' (58#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:1827] INFO: [Synth 8-638] synthesizing module 'EMC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:8233] Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_IPIF_DWIDTH bound to: 32 - type: integer Parameter C_IPIF_AWIDTH bound to: 32 - type: integer Parameter C_PAGE_SIZE bound to: 16 - type: integer Parameter C_MEM0_BASEADDR bound to: 1610612736 - type: integer Parameter C_MEM0_HIGHADDR bound to: 2147483647 - type: integer Parameter C_MEM1_BASEADDR bound to: -1342177280 - type: integer Parameter C_MEM1_HIGHADDR bound to: -1073741825 - type: integer Parameter C_MEM2_BASEADDR bound to: -1073741824 - type: integer Parameter C_MEM2_HIGHADDR bound to: -805306369 - type: integer Parameter C_MEM3_BASEADDR bound to: -805306368 - type: integer Parameter C_MEM3_HIGHADDR bound to: -536870913 - type: integer Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_0 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_1 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_2 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_3 bound to: 0 - type: integer Parameter C_MEM0_WIDTH bound to: 32 - type: integer Parameter C_MEM1_WIDTH bound to: 16 - type: integer Parameter C_MEM2_WIDTH bound to: 16 - type: integer Parameter C_MEM3_WIDTH bound to: 16 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_MEM0_TYPE bound to: 1 - type: integer Parameter C_MEM1_TYPE bound to: 0 - type: integer Parameter C_MEM2_TYPE bound to: 0 - type: integer Parameter C_MEM3_TYPE bound to: 0 - type: integer Parameter C_PARITY_TYPE_0 bound to: 0 - type: integer Parameter C_PARITY_TYPE_1 bound to: 0 - type: integer Parameter C_PARITY_TYPE_2 bound to: 0 - type: integer Parameter C_PARITY_TYPE_3 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer Parameter C_BUS_CLOCK_PERIOD_PS bound to: 30769 - type: integer Parameter C_SYNCH_MEM_0 bound to: 0 - type: integer Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TAVDV_PS_MEM_0 bound to: 120000 - type: integer Parameter C_TPACC_PS_FLASH_0 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_0 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_0 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_0 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_0 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_0 bound to: 27000 - type: integer Parameter C_SYNCH_MEM_1 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_1 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_1 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_1 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_1 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_1 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_1 bound to: 27000 - type: integer Parameter C_SYNCH_MEM_2 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_2 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_2 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_2 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_2 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_2 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_2 bound to: 27000 - type: integer Parameter C_SYNCH_MEM_3 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer Parameter C_TCEDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TAVDV_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TPACC_PS_FLASH_3 bound to: 25000 - type: integer Parameter C_THZCE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_THZOE_PS_MEM_3 bound to: 7000 - type: integer Parameter C_TWC_PS_MEM_3 bound to: 15000 - type: integer Parameter C_TWP_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TWPH_PS_MEM_3 bound to: 12000 - type: integer Parameter C_TLZWE_PS_MEM_3 bound to: 0 - type: integer Parameter C_WR_REC_TIME_MEM_3 bound to: 27000 - type: integer INFO: [Synth 8-638] synthesizing module 'emc_common_v3_0_5_ipic_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:580] Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'ld_arith_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] Parameter C_ADD_SUB_NOT bound to: 0 - type: bool Parameter C_REG_WIDTH bound to: 8 - type: integer Parameter C_RESET_VALUE bound to: 8'b00000000 Parameter C_LD_WIDTH bound to: 8 - type: integer Parameter C_LD_OFFSET bound to: 0 - type: integer Parameter C_AD_WIDTH bound to: 1 - type: integer Parameter C_AD_OFFSET bound to: 0 - type: integer INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-6157] synthesizing module 'MULT_AND' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867] INFO: [Synth 8-6155] done synthesizing module 'MULT_AND' (59#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-6157] synthesizing module 'MUXCY' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878] INFO: [Synth 8-6155] done synthesizing module 'MUXCY' (60#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-6157] synthesizing module 'XORCY' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303] INFO: [Synth 8-6155] done synthesizing module 'XORCY' (61#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDRE' (62#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg' (63#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] WARNING: [Synth 8-6014] Unused sequential element bus2ip_mem_cs_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:668] WARNING: [Synth 8-6014] Unused sequential element pr_state_wait_temp_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:669] INFO: [Synth 8-256] done synthesizing module 'emc_common_v3_0_5_ipic_if' (64#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:580] INFO: [Synth 8-638] synthesizing module 'mem_state_machine' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2190] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'READ_COMPLETE_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3114] WARNING: [Synth 8-6014] Unused sequential element mem_cen_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3179] WARNING: [Synth 8-6014] Unused sequential element mem_oen_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3180] WARNING: [Synth 8-6014] Unused sequential element mem_wen_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3181] WARNING: [Synth 8-6014] Unused sequential element addr_cnt_ce_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3208] WARNING: [Synth 8-6014] Unused sequential element addr_cnt_rst_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3209] WARNING: [Synth 8-6014] Unused sequential element Bus2IP_RdReq_d2_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3258] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d1_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3304] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d2_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3305] WARNING: [Synth 8-6014] Unused sequential element last_addr1_d3_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3306] WARNING: [Synth 8-3848] Net addressData_strobe_cmb in module/entity mem_state_machine does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2238] INFO: [Synth 8-256] done synthesizing module 'mem_state_machine' (65#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:2190] INFO: [Synth 8-638] synthesizing module 'addr_counter_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4461] Parameter C_ADDR_CNTR_WIDTH bound to: 2 - type: integer Parameter C_IPIF_AWIDTH bound to: 32 - type: integer Parameter C_IPIF_DWIDTH bound to: 32 - type: integer Parameter C_ADDR_OFFSET bound to: 2 - type: integer Parameter PARITY_TYPE_MEMORY bound to: 0 - type: integer Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'ADDRESS_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4556] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'BEN_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4573] WARNING: [Synth 8-3848] Net Addr_align in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4436] WARNING: [Synth 8-3848] Net par_error_addr in module/entity addr_counter_mux does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4444] INFO: [Synth 8-256] done synthesizing module 'addr_counter_mux' (66#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:4461] INFO: [Synth 8-638] synthesizing module 'counters' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1669] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] Parameter C_ADD_SUB_NOT bound to: 0 - type: bool Parameter C_REG_WIDTH bound to: 5 - type: integer Parameter C_RESET_VALUE bound to: 5'b11111 Parameter C_LD_WIDTH bound to: 5 - type: integer Parameter C_LD_OFFSET bound to: 0 - type: integer Parameter C_AD_WIDTH bound to: 1 - type: integer Parameter C_AD_OFFSET bound to: 0 - type: integer INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328] INFO: [Synth 8-6157] synthesizing module 'FDSE' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844] Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDSE' (67#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDSE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13844' bound to instance 'FDSE_i1' of component 'FDSE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:328] INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized0' (67#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] Parameter C_ADD_SUB_NOT bound to: 0 - type: bool Parameter C_REG_WIDTH bound to: 5 - type: integer Parameter C_RESET_VALUE bound to: 5'b00000 Parameter C_LD_WIDTH bound to: 5 - type: integer Parameter C_LD_OFFSET bound to: 0 - type: integer Parameter C_AD_WIDTH bound to: 1 - type: integer Parameter C_AD_OFFSET bound to: 0 - type: integer INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Synth 8-3491] module 'MUXCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42878' bound to instance 'MUXCY_i1' of component 'MUXCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:291] INFO: [Synth 8-3491] module 'XORCY' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:82303' bound to instance 'XORCY_i1' of component 'XORCY' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:302] INFO: [Synth 8-3491] module 'FDRE' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13708' bound to instance 'FDRE_i1' of component 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:318] INFO: [Synth 8-3491] module 'MULT_AND' declared at '/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42867' bound to instance 'MULT_AND_i1' of component 'MULT_AND' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:281] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized1' (67#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] INFO: [Synth 8-638] synthesizing module 'ld_arith_reg__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] Parameter C_ADD_SUB_NOT bound to: 0 - type: bool Parameter C_REG_WIDTH bound to: 16 - type: integer Parameter C_RESET_VALUE bound to: 16'b1111111111111111 Parameter C_LD_WIDTH bound to: 16 - type: integer Parameter C_LD_OFFSET bound to: 0 - type: integer Parameter C_AD_WIDTH bound to: 1 - type: integer Parameter C_AD_OFFSET bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'ld_arith_reg__parameterized2' (67#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:161] INFO: [Synth 8-256] done synthesizing module 'counters' (68#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1669] INFO: [Synth 8-638] synthesizing module 'select_param' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3633] Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_PAGE_SIZE bound to: 16 - type: integer Parameter C_GLOBAL_SYNC_MEM bound to: 0 - type: integer Parameter C_SYNCH_MEM_0 bound to: 0 - type: integer Parameter C_SYNCH_MEM_1 bound to: 1 - type: integer Parameter C_SYNCH_MEM_2 bound to: 1 - type: integer Parameter C_SYNCH_MEM_3 bound to: 1 - type: integer Parameter C_MEM0_WIDTH bound to: 32 - type: integer Parameter C_MEM1_WIDTH bound to: 16 - type: integer Parameter C_MEM2_WIDTH bound to: 16 - type: integer Parameter C_MEM3_WIDTH bound to: 16 - type: integer Parameter C_PAGEMODE_FLASH bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_0 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_1 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_2 bound to: 0 - type: integer Parameter C_PAGEMODE_FLASH_3 bound to: 0 - type: integer Parameter PARITY_TYPE_MEMORY bound to: 0 - type: integer Parameter C_PARITY_TYPE_0 bound to: 0 - type: integer Parameter C_PARITY_TYPE_1 bound to: 0 - type: integer Parameter C_PARITY_TYPE_2 bound to: 0 - type: integer Parameter C_PARITY_TYPE_3 bound to: 0 - type: integer Parameter C_IPIF_AWIDTH bound to: 32 - type: integer Parameter C_IPIF_DWIDTH bound to: 32 - type: integer Parameter C_SYNCH_PIPEDELAY_0 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_1 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_2 bound to: 1 - type: integer Parameter C_SYNCH_PIPEDELAY_3 bound to: 1 - type: integer Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_0 bound to: 0 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_1 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_2 bound to: 1 - type: integer Parameter C_INCLUDE_DATAWIDTH_MATCHING_3 bound to: 1 - type: integer Parameter TRDCNT_0 bound to: 5'b00100 Parameter TRDCNT_1 bound to: 5'b00001 Parameter TRDCNT_2 bound to: 5'b00001 Parameter TRDCNT_3 bound to: 5'b00001 Parameter THZCNT_0 bound to: 5'b00001 Parameter THZCNT_1 bound to: 5'b00001 Parameter THZCNT_2 bound to: 5'b00001 Parameter THZCNT_3 bound to: 5'b00001 Parameter TWRCNT_0 bound to: 5'b00000 Parameter TWRCNT_1 bound to: 5'b00000 Parameter TWRCNT_2 bound to: 5'b00000 Parameter TWRCNT_3 bound to: 5'b00000 Parameter TWPHCNT_0 bound to: 5'b00001 Parameter TWPHCNT_1 bound to: 5'b00001 Parameter TWPHCNT_2 bound to: 5'b00001 Parameter TWPHCNT_3 bound to: 5'b00001 Parameter TPACC_0 bound to: 5'b00001 Parameter TPACC_1 bound to: 5'b00001 Parameter TPACC_2 bound to: 5'b00001 Parameter TPACC_3 bound to: 5'b00001 Parameter TLZCNT_0 bound to: 5'b00001 Parameter TLZCNT_1 bound to: 5'b00001 Parameter TLZCNT_2 bound to: 5'b00001 Parameter TLZCNT_3 bound to: 5'b00001 Parameter TP_WR_REC_CNT_0 bound to: 16'b0000000000000001 Parameter TP_WR_REC_CNT_1 bound to: 16'b0000000000000001 Parameter TP_WR_REC_CNT_2 bound to: 16'b0000000000000001 Parameter TP_WR_REC_CNT_3 bound to: 16'b0000000000000001 INFO: [Synth 8-256] done synthesizing module 'select_param' (69#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:3633] INFO: [Synth 8-638] synthesizing module 'mem_steer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5345] Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_MIN_MEM_WIDTH bound to: 8 - type: integer Parameter C_IPIF_DWIDTH bound to: 32 - type: integer Parameter C_IPIF_AWIDTH bound to: 32 - type: integer Parameter C_PARITY_TYPE_MEMORY bound to: 0 - type: integer Parameter C_ADDR_CNTR_WIDTH bound to: 2 - type: integer Parameter C_GLOBAL_DATAWIDTH_MATCH bound to: 0 - type: integer Parameter C_GLOBAL_SYNC_MEM bound to: 0 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6024] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RDACK_PIPE_ASYNC' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6024] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6087] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'AALIGN_PIPE' to cell 'FDR' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6087] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'WRDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6111] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:7120] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RDDATA_REG' to cell 'FDRE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:7120] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 WARNING: [Synth 8-6014] Unused sequential element mem_dqt_parity_t_d_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:6961] WARNING: [Synth 8-3848] Net write_data_parity_cmb in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5368] WARNING: [Synth 8-3848] Net MemSteer_Mem_DQ_prty_T in module/entity mem_steer does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5305] INFO: [Synth 8-256] done synthesizing module 'mem_steer' (70#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:5345] INFO: [Synth 8-638] synthesizing module 'io_registers' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1226] Parameter C_INCLUDE_NEGEDGE_IOREGS bound to: 0 - type: integer Parameter C_IPIF_AWIDTH bound to: 32 - type: integer Parameter C_MAX_MEM_WIDTH bound to: 32 - type: integer Parameter C_NUM_BANKS_MEM bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex6 - type: string INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1245] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1248] INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1249] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1249] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1250] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1251] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1252] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1253] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1254] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1255] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1256] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1257] INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1265] INFO: [Synth 8-256] done synthesizing module 'io_registers' (71#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:1226] INFO: [Synth 8-256] done synthesizing module 'EMC' (72#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ea80/hdl/emc_common_v3_0_vh_rfs.vhd:8233] WARNING: [Synth 8-6014] Unused sequential element mem_wait_io_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4262] WARNING: [Synth 8-6014] Unused sequential element or_reduced_rdce_d1_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:6329] WARNING: [Synth 8-6014] Unused sequential element bus2ip_wrreq_reg_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:6330] WARNING: [Synth 8-3848] Net mem_cre_int in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:4214] WARNING: [Synth 8-3848] Net cfgclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3668] WARNING: [Synth 8-3848] Net cfgmclk in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3669] WARNING: [Synth 8-3848] Net eos in module/entity axi_emc does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3670] INFO: [Synth 8-256] done synthesizing module 'axi_emc' (73#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/d985/hdl/axi_emc_v3_0_vh_rfs.vhd:3738] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_emc_0_0' (74#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/synth/axi4_subsys_axi_emc_0_0.vhd:119] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_gpio_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_GPIO_WIDTH bound to: 16 - type: integer Parameter C_GPIO2_WIDTH bound to: 24 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 1 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000001111111100000000 Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_GPIO_WIDTH bound to: 16 - type: integer Parameter C_GPIO2_WIDTH bound to: 24 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 1 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 65280 - type: integer Parameter C_TRI_DEFAULT bound to: -1 - type: integer Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] Parameter C_BUS_AWIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b00 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f' (75#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b01 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized0' (75#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b10 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized1' (75#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b11 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized2' (75#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder' (76#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (77#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (78#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] Parameter C_DW bound to: 32 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_GPIO_WIDTH bound to: 16 - type: integer Parameter C_GPIO2_WIDTH bound to: 24 - type: integer Parameter C_MAX_GPIO_WIDTH bound to: 24 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 65280 - type: integer Parameter C_TRI_DEFAULT bound to: -1 - type: integer Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 1 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:835] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 0 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 16 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (79#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 0 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 24 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized0' (79#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G1.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:690] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:719] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (80#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (81#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/f71e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_gpio_0_0' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/synth/axi4_subsys_axi_gpio_0_0.vhd:85] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_hwicap_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_ICAP_EXTERNAL bound to: 1 - type: integer Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer Parameter C_ENABLE_ASYNC bound to: 0 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer Parameter C_ICAP_WIDTH_S bound to: X32 - type: string Parameter C_DEVICE_ID bound to: 32'b00000100001000100100000010010011 Parameter C_MODE bound to: 0 - type: integer Parameter C_NOREAD bound to: 0 - type: integer Parameter C_SIMULATION bound to: 2 - type: integer Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_OPERATION bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_hwicap' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4084] Parameter C_ENABLE_ASYNC bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer Parameter C_ICAP_WIDTH_S bound to: X32 - type: string Parameter C_DEVICE_ID bound to: 69353619 - type: integer Parameter C_MODE bound to: 0 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_OPERATION bound to: 0 - type: integer Parameter C_NOREAD bound to: 0 - type: integer Parameter C_SIMULATION bound to: 2 - type: integer Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer Parameter C_ICAP_EXTERNAL bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 16 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111 Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111 Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000 Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 16 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] Parameter C_BUS_AWIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111 Parameter C_ARD_NUM_CE_ARRAY bound to: 64'b0000000000000000000000000001000000000000000000000000000000001000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_BAR bound to: 9'b000000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized3' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized4' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized5' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized6' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized7' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized8' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized9' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized10' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized11' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized12' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized13' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized14' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized15' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized16' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized17' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized18' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized19' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_BAR bound to: 9'b100000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized20' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized21' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized22' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized23' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized24' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized25' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized26' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized27' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized28' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized0' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized0' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized0' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'hwicap_shared' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3444] Parameter ICAP_DWIDTH bound to: 32 - type: integer Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer Parameter C_SAXI_DWIDTH bound to: 32 - type: integer Parameter C_SIMULATION bound to: 2 - type: integer Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer Parameter C_ICAP_WIDTH bound to: X32 - type: string Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_MODE bound to: 0 - type: integer Parameter C_ICAP_EXTERNAL bound to: 0 - type: integer Parameter C_OPERATION bound to: 0 - type: integer Parameter C_NOREAD bound to: 0 - type: integer Parameter C_ENABLE_ASYNC bound to: 0 - type: integer Parameter C_DEVICE_ID bound to: 69353619 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi_hwicap_v3_0_24_ipic_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:216] Parameter C_ENABLE_ASYNC bound to: 0 - type: integer Parameter C_MODE bound to: 0 - type: integer Parameter C_NOREAD bound to: 0 - type: integer Parameter C_INCLUDE_STARTUP bound to: 1 - type: integer Parameter C_SAXI_DWIDTH bound to: 32 - type: integer Parameter C_WRITE_FIFO_DEPTH bound to: 64 - type: integer Parameter C_READ_FIFO_DEPTH bound to: 128 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter ICAP_DWIDTH bound to: 32 - type: integer Parameter C_BRAM_SRL_FIFO_TYPE bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 0 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 12 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized1' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 0 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 32 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized2' (82#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 64 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer Parameter C_HAS_RD_ACK bound to: 1 - type: integer Parameter C_HAS_RD_COUNT bound to: 1 - type: integer Parameter C_HAS_RD_ERR bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 1 - type: integer Parameter C_HAS_WR_COUNT bound to: 1 - type: integer Parameter C_HAS_WR_ERR bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_RD_COUNT_WIDTH bound to: 7 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer Parameter C_USE_BLOCKMEM bound to: 1 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_COUNT_WIDTH bound to: 7 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 4 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029] Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 64 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 7 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 64 - type: integer Parameter FIFO_SIZE bound to: 2048 - type: integer Parameter WR_WIDTH_LOG bound to: 5 - type: integer Parameter WR_DEPTH_LOG bound to: 6 - type: integer Parameter WR_PNTR_WIDTH bound to: 6 - type: integer Parameter RD_PNTR_WIDTH bound to: 6 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 10 - type: integer Parameter PE_THRESH_ADJ bound to: 10 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 61 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 61 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 7 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 7 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 6 - type: integer Parameter RESET_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (83#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 6 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (83#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 6 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 6 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 64 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 6 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 6 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 6 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 6 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (84#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 6 - type: integer INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (85#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] Parameter REG_WIDTH bound to: 6 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (86#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (86#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] Parameter REG_WIDTH bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (86#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1574] INFO: [Synth 8-5534] Detected attribute (* fsm_safe_state = "default_state" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1580] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1111] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (87#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (88#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1506] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790] Parameter RST_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (89#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1790] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (89#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 6 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (89#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (90#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (91#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg' (92#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 32 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized3' (92#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 128 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer Parameter C_HAS_RD_ACK bound to: 1 - type: integer Parameter C_HAS_RD_COUNT bound to: 1 - type: integer Parameter C_HAS_RD_ERR bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 1 - type: integer Parameter C_HAS_WR_COUNT bound to: 1 - type: integer Parameter C_HAS_WR_ERR bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_RD_COUNT_WIDTH bound to: 8 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer Parameter C_USE_BLOCKMEM bound to: 1 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_COUNT_WIDTH bound to: 8 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 4 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029] Parameter FIFO_MEMORY_TYPE bound to: block - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: std - type: string Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 4 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 0 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 2 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 128 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 0 - type: integer Parameter FIFO_READ_LATENCY bound to: 1 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 8 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 4 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 2 - type: integer Parameter RD_MODE bound to: 0 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 128 - type: integer Parameter FIFO_SIZE bound to: 4096 - type: integer Parameter WR_WIDTH_LOG bound to: 5 - type: integer Parameter WR_DEPTH_LOG bound to: 7 - type: integer Parameter WR_PNTR_WIDTH bound to: 7 - type: integer Parameter RD_PNTR_WIDTH bound to: 7 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 10 - type: integer Parameter PE_THRESH_ADJ bound to: 10 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 125 - type: integer Parameter PE_THRESH_MIN bound to: 3 - type: integer Parameter PE_THRESH_MAX bound to: 125 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 8 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 8 - type: integer Parameter RD_LATENCY bound to: 1 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized4' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized4' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized0' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 4096 - type: integer Parameter MEMORY_PRIMITIVE bound to: 2 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 7 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 7 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 1 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: block - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 128 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 7 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 7 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 7 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 7 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: no - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized0' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] Parameter REG_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized1' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1768] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized5' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized5' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized6' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] Parameter COUNTER_WIDTH bound to: 7 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized6' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1742] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (92#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2029] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized0' (92#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 32 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized4' (92#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 12 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized5' (92#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg WARNING: [Synth 8-3848] Net Status_read in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:186] WARNING: [Synth 8-3848] Net CFGCLK in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:197] WARNING: [Synth 8-3848] Net CFGMCLK in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:198] WARNING: [Synth 8-3848] Net PREQ in module/entity axi_hwicap_v3_0_24_ipic_if does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:199] INFO: [Synth 8-256] done synthesizing module 'axi_hwicap_v3_0_24_ipic_if' (93#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:216] INFO: [Synth 8-638] synthesizing module 'icap_statemachine_shared' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2160] Parameter ICAP_DWIDTH bound to: 32 - type: integer Parameter C_MODE bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2119] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2124] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2132] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2133] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2139] INFO: [Synth 8-256] done synthesizing module 'icap_statemachine_shared' (94#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:2160] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'hwicap_shared' (95#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:3444] INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 128'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (96#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'axi_hwicap' (97#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6a13/hdl/axi_hwicap_v3_0_vh_rfs.vhd:4084] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_hwicap_0_0' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/synth/axi4_subsys_axi_hwicap_0_0.vhd:93] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-638] synthesizing module 'axi_iic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6870] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-638] synthesizing module 'iic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6187] Parameter C_NUM_IIC_REGS bound to: 18 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-638] synthesizing module 'axi_ipif_ssp1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5661] Parameter C_NUM_IIC_REGS bound to: 18 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] Parameter C_BUS_AWIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000000100000000000000000000000000010010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized29' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized30' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized31' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized32' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized33' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized34' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized35' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized36' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized37' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized38' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized39' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized40' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized41' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized42' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized43' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized44' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 7 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_BAR bound to: 9'b001000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized45' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 1 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_BAR bound to: 9'b100000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized46' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized47' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized48' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized49' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized50' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized51' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized52' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized52' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized53' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized53' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized54' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b00111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized54' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized55' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized55' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized56' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized56' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized57' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized57' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized58' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized58' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized59' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized59' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized60' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized60' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized61' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized61' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized62' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b01111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized62' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized63' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b10000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized63' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized64' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 5 - type: integer Parameter C_BAR bound to: 5'b10001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized64' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized1' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized1' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized1' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 256'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized0' (98#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] INFO: [Synth 8-638] synthesizing module 'axi_iic_v2_0_23_soft_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:141] Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer Parameter C_RESET_WIDTH bound to: 4 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'axi_iic_v2_0_23_soft_reset' (99#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:141] INFO: [Synth 8-256] done synthesizing module 'axi_ipif_ssp1' (100#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5661] INFO: [Synth 8-638] synthesizing module 'reg_interface' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1677] Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_TX_FIFO_EXIST bound to: 1 - type: bool Parameter C_TX_FIFO_BITS bound to: 4 - type: integer Parameter C_RC_FIFO_EXIST bound to: 1 - type: bool Parameter C_RC_FIFO_BITS bound to: 4 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_SIZE bound to: 10 - type: integer Parameter C_NUM_IIC_REGS bound to: 18 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'reg_interface' (101#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1677] INFO: [Synth 8-638] synthesizing module 'filter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:4985] Parameter SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter SDA_INERTIAL_DELAY bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'debounce' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1307] Parameter C_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_DEFAULT bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'debounce' (102#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:1307] INFO: [Synth 8-256] done synthesizing module 'filter' (103#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:4985] INFO: [Synth 8-638] synthesizing module 'iic_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:2908] Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_SIZE bound to: 10 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740] Parameter C_SIZE bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (104#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740] INFO: [Synth 8-638] synthesizing module 'shift8' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:897] INFO: [Synth 8-256] done synthesizing module 'shift8' (105#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:897] INFO: [Synth 8-638] synthesizing module 'upcnt_n__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740] Parameter C_SIZE bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'upcnt_n__parameterized0' (105#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:740] INFO: [Synth 8-256] done synthesizing module 'iic_control' (106#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:2908] INFO: [Synth 8-638] synthesizing module 'SRL_FIFO' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] Parameter C_DATA_BITS bound to: 8 - type: integer Parameter C_DEPTH bound to: 4 - type: integer Parameter C_XON bound to: 0 - type: bool INFO: [Synth 8-6157] synthesizing module 'FDR' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13695] Parameter INIT bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDR' (107#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:13695] INFO: [Synth 8-6157] synthesizing module 'MUXCY_L' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42903] INFO: [Synth 8-6155] done synthesizing module 'MUXCY_L' (108#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42903] INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77965] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (109#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77965] INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO' (110#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] Parameter C_DATA_BITS bound to: 8 - type: integer Parameter C_DEPTH bound to: 4 - type: integer Parameter C_XON bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized0' (110#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] INFO: [Synth 8-638] synthesizing module 'dynamic_master' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5204] INFO: [Synth 8-256] done synthesizing module 'dynamic_master' (111#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:5204] INFO: [Synth 8-638] synthesizing module 'SRL_FIFO__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] Parameter C_DATA_BITS bound to: 2 - type: integer Parameter C_DEPTH bound to: 4 - type: integer Parameter C_XON bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'SRL_FIFO__parameterized1' (111#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:449] INFO: [Synth 8-256] done synthesizing module 'iic' (112#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6187] INFO: [Synth 8-256] done synthesizing module 'axi_iic' (113#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b41e/hdl/axi_iic_v2_0_vh_rfs.vhd:6870] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_0_0' (114#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/synth/axi4_subsys_axi_iic_0_0.vhd:91] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_iic_1_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_IIC_FREQ bound to: 32000 - type: integer Parameter C_TEN_BIT_ADR bound to: 0 - type: integer Parameter C_GPO_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 32500000 - type: integer Parameter C_SCL_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_INERTIAL_DELAY bound to: 0 - type: integer Parameter C_SDA_LEVEL bound to: 1 - type: integer Parameter C_SMBUS_PMBUS_HOST bound to: 0 - type: integer Parameter C_DEFAULT_VALUE bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_iic_1_0' (115#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/synth/axi4_subsys_axi_iic_1_0.vhd:91] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_interconnect_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2823] INFO: [Synth 8-638] synthesizing module 'm00_couplers_imp_1AOY6T4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:93] INFO: [Synth 8-256] done synthesizing module 'm00_couplers_imp_1AOY6T4' (116#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:93] INFO: [Synth 8-638] synthesizing module 'm01_couplers_imp_FF3AZQ' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:270] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_M_AXI_PROTOCOL bound to: 2 - type: integer Parameter C_S_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_IGNORE_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_TRANSLATION_MODE bound to: 2 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_AXILITE_SIZE bound to: 3'b010 Parameter P_INCR bound to: 2'b01 Parameter P_DECERR bound to: 2'b11 Parameter P_SLVERR bound to: 2'b10 Parameter P_PROTECTION bound to: 1 - type: integer Parameter P_CONVERSION bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226] Parameter C_S_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_aw_channel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971] Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_cmd_translator' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464] Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter P_AXBURST_FIXED bound to: 2'b00 Parameter P_AXBURST_INCR bound to: 2'b01 Parameter P_AXBURST_WRAP bound to: 2'b10 INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_incr_cmd' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092] Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_incr_cmd' (117#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3092] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wrap_cmd' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902] Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter L_AXI_ADDR_LOW_BIT bound to: 12 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wrap_cmd' (118#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2902] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_cmd_translator' (119#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3464] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224] Parameter SM_IDLE bound to: 2'b00 Parameter SM_CMD_EN bound to: 2'b01 Parameter SM_CMD_ACCEPTED bound to: 2'b10 Parameter SM_DONE_WAIT bound to: 2'b11 INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3277] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm' (120#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3224] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_aw_channel' (121#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3971] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_b_channel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606] Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter LP_RESP_OKAY bound to: 2'b00 Parameter LP_RESP_EXOKAY bound to: 2'b01 Parameter LP_RESP_SLVERROR bound to: 2'b10 Parameter LP_RESP_DECERR bound to: 2'b11 Parameter P_WIDTH bound to: 10 - type: integer Parameter P_DEPTH bound to: 4 - type: integer Parameter P_AWIDTH bound to: 2 - type: integer Parameter P_RWIDTH bound to: 2 - type: integer Parameter P_RDEPTH bound to: 4 - type: integer Parameter P_RAWIDTH bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] Parameter C_WIDTH bound to: 10 - type: integer Parameter C_AWIDTH bound to: 2 - type: integer Parameter C_DEPTH bound to: 4 - type: integer Parameter C_EMPTY bound to: 2'b11 Parameter C_EMPTY_PRE bound to: 2'b00 Parameter C_FULL bound to: 2'b10 Parameter C_FULL_PRE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo' (122#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] Parameter C_WIDTH bound to: 2 - type: integer Parameter C_AWIDTH bound to: 2 - type: integer Parameter C_DEPTH bound to: 4 - type: integer Parameter C_EMPTY bound to: 2'b11 Parameter C_EMPTY_PRE bound to: 2'b00 Parameter C_FULL bound to: 2'b10 Parameter C_FULL_PRE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0' (122#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_b_channel' (123#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3606] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_ar_channel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082] Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334] Parameter SM_IDLE bound to: 2'b00 Parameter SM_CMD_EN bound to: 2'b01 Parameter SM_CMD_ACCEPTED bound to: 2'b10 Parameter SM_DONE bound to: 2'b11 INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3395] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' (124#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3334] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_ar_channel' (125#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4082] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_r_channel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811] Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter P_WIDTH bound to: 3 - type: integer Parameter P_DEPTH bound to: 32 - type: integer Parameter P_AWIDTH bound to: 5 - type: integer Parameter P_D_WIDTH bound to: 34 - type: integer Parameter P_D_DEPTH bound to: 32 - type: integer Parameter P_D_AWIDTH bound to: 5 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] Parameter C_WIDTH bound to: 34 - type: integer Parameter C_AWIDTH bound to: 5 - type: integer Parameter C_DEPTH bound to: 32 - type: integer Parameter C_EMPTY bound to: 5'b11111 Parameter C_EMPTY_PRE bound to: 5'b00000 Parameter C_FULL bound to: 5'b11110 Parameter C_FULL_PRE bound to: 5'b11010 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1' (125#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] Parameter C_WIDTH bound to: 3 - type: integer Parameter C_AWIDTH bound to: 5 - type: integer Parameter C_DEPTH bound to: 32 - type: integer Parameter C_EMPTY bound to: 5'b11111 Parameter C_EMPTY_PRE bound to: 5'b00000 Parameter C_FULL bound to: 5'b11110 Parameter C_FULL_PRE bound to: 5'b11010 INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2' (125#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2816] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s_r_channel' (126#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3811] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 1 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 1 - type: integer Parameter C_REG_CONFIG_AR bound to: 1 - type: integer Parameter C_REG_CONFIG_R bound to: 1 - type: integer Parameter C_RESERVE_MODE bound to: 0 - type: integer Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter P_FORWARD bound to: 0 - type: integer Parameter P_RESPONSE bound to: 1 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 63 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 63 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (127#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 63 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 63 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 55 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 59 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 63 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 63 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (128#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 63 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice' (129#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 37 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized0' (129#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 4 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized1' (129#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 37 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized2' (129#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704] WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_AXI_PROTOCOL bound to: 2 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 0 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 0 - type: integer Parameter C_REG_CONFIG_AR bound to: 0 - type: integer Parameter C_REG_CONFIG_R bound to: 0 - type: integer Parameter C_RESERVE_MODE bound to: 0 - type: integer Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer Parameter P_FORWARD bound to: 0 - type: integer Parameter P_RESPONSE bound to: 1 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_WID_INDEX bound to: 36 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_RID_INDEX bound to: 34 - type: integer Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] Parameter C_AXI_PROTOCOL bound to: 2 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_WID_INDEX bound to: 36 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_RID_INDEX bound to: 34 - type: integer Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] Parameter C_AXI_PROTOCOL bound to: 2 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 35 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 36 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 2 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 35 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 34 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWID_INDEX bound to: 35 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 35 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 35 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARID_INDEX bound to: 35 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 35 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 35 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 35 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 35 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_WID_INDEX bound to: 36 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 36 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 36 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 0 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 2 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 2 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 0 - type: integer Parameter G_AXI_RID_INDEX bound to: 34 - type: integer Parameter G_AXI_RID_WIDTH bound to: 0 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 34 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 34 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 35 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized3' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 36 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized4' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 2 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized5' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex6 - type: string Parameter C_DATA_WIDTH bound to: 34 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized6' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized0' (130#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704] WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_b2s' (131#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4226] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter' (132#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_0' (133#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_0/synth/axi4_subsys_auto_pc_0.v:58] INFO: [Synth 8-256] done synthesizing module 'm01_couplers_imp_FF3AZQ' (134#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:270] INFO: [Synth 8-638] synthesizing module 'm02_couplers_imp_L8N2BP' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:587] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:58] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_1' (135#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_1/synth/axi4_subsys_auto_pc_1.v:58] INFO: [Synth 8-256] done synthesizing module 'm02_couplers_imp_L8N2BP' (136#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:587] INFO: [Synth 8-638] synthesizing module 'm03_couplers_imp_1MMZOD7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:904] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:58] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_2' (137#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_2/synth/axi4_subsys_auto_pc_2.v:58] INFO: [Synth 8-256] done synthesizing module 'm03_couplers_imp_1MMZOD7' (138#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:904] INFO: [Synth 8-638] synthesizing module 'm04_couplers_imp_1FSUCEB' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1221] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:58] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_3' (139#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_3/synth/axi4_subsys_auto_pc_3.v:58] INFO: [Synth 8-256] done synthesizing module 'm04_couplers_imp_1FSUCEB' (140#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1221] INFO: [Synth 8-638] synthesizing module 'm05_couplers_imp_ADRT99' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1538] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:58] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_4' (141#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_4/synth/axi4_subsys_auto_pc_4.v:58] INFO: [Synth 8-256] done synthesizing module 'm05_couplers_imp_ADRT99' (142#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1538] INFO: [Synth 8-638] synthesizing module 'm06_couplers_imp_Q7JFB2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1855] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:58] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_5' (143#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_5/synth/axi4_subsys_auto_pc_5.v:58] INFO: [Synth 8-256] done synthesizing module 'm06_couplers_imp_Q7JFB2' (144#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:1855] INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_IY3DNS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2168] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_auto_pc_6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_M_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_PROTOCOL bound to: 2 - type: integer Parameter C_IGNORE_ID bound to: 1 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_TRANSLATION_MODE bound to: 2 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_AXILITE_SIZE bound to: 3'b010 Parameter P_INCR bound to: 2'b01 Parameter P_DECERR bound to: 2'b11 Parameter P_SLVERR bound to: 2'b10 Parameter P_PROTECTION bound to: 1 - type: integer Parameter P_CONVERSION bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_20_axi_protocol_converter__parameterized0' (144#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/c4a6/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4808] INFO: [Synth 8-6155] done synthesizing module 'axi4_subsys_auto_pc_6' (145#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_auto_pc_6/synth/axi4_subsys_auto_pc_6.v:58] INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_IY3DNS' (146#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2168] INFO: [Synth 8-638] synthesizing module 's01_couplers_imp_1OXAPVA' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2487] INFO: [Synth 8-256] done synthesizing module 's01_couplers_imp_1OXAPVA' (147#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2487] INFO: [Synth 8-6157] synthesizing module 'axi4_subsys_xbar_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xbar_0/synth/axi4_subsys_xbar_0.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_axi_crossbar' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4884] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer Parameter C_NUM_MASTER_SLOTS bound to: 7 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_M_AXI_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_M_AXI_ADDR_WIDTH bound to: 224'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000011101 Parameter C_S_AXI_BASE_ID bound to: 64'b0000000000000000000000000000001000000000000000000000000000000000 Parameter C_S_AXI_THREAD_ID_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000000 Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_M_AXI_WRITE_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_M_AXI_READ_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_R_REGISTER bound to: 0 - type: integer Parameter C_S_AXI_SINGLE_THREAD bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter C_S_AXI_WRITE_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010 Parameter C_S_AXI_READ_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010 Parameter C_M_AXI_WRITE_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter C_M_AXI_READ_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter C_S_AXI_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_CONNECTIVITY_MODE bound to: 1 - type: integer Parameter P_ONES bound to: 65'b11111111111111111111111111111111111111111111111111111111111111111 Parameter P_S_AXI_BASE_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 Parameter P_S_AXI_HIGH_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000 Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_AXILITE_SIZE bound to: 3'b010 Parameter P_INCR bound to: 2'b01 Parameter P_M_AXI_SUPPORTS_WRITE bound to: 7'b1111111 Parameter P_M_AXI_SUPPORTS_READ bound to: 7'b1111111 Parameter P_S_AXI_SUPPORTS_WRITE bound to: 2'b11 Parameter P_S_AXI_SUPPORTS_READ bound to: 2'b11 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_RANGE_CHECK bound to: 1 - type: integer Parameter P_ADDR_DECODE bound to: 1 - type: integer Parameter P_M_AXI_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter P_LEN bound to: 8 - type: integer Parameter P_LOCK bound to: 1 - type: integer Parameter P_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_crossbar' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:2239] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer Parameter C_NUM_MASTER_SLOTS bound to: 7 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_M_AXI_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_M_AXI_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_S_AXI_BASE_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 Parameter C_S_AXI_HIGH_ID bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000 Parameter C_S_AXI_THREAD_ID_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000000 Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_S_AXI_SUPPORTS_WRITE bound to: 2'b11 Parameter C_S_AXI_SUPPORTS_READ bound to: 2'b11 Parameter C_M_AXI_SUPPORTS_WRITE bound to: 7'b1111111 Parameter C_M_AXI_SUPPORTS_READ bound to: 7'b1111111 Parameter C_M_AXI_WRITE_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_M_AXI_READ_CONNECTIVITY bound to: 224'b00000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_S_AXI_SINGLE_THREAD bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter C_S_AXI_WRITE_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010 Parameter C_S_AXI_READ_ACCEPTANCE bound to: 64'b0000000000000000000000000000001000000000000000000000000000000010 Parameter C_M_AXI_WRITE_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter C_M_AXI_READ_ISSUING bound to: 224'b00000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter C_S_AXI_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_M_AXI_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_RANGE_CHECK bound to: 1 - type: integer Parameter C_ADDR_DECODE bound to: 1 - type: integer Parameter C_W_ISSUE_WIDTH bound to: 256'b0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter C_R_ISSUE_WIDTH bound to: 256'b0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter C_W_ACCEPT_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000001 Parameter C_R_ACCEPT_WIDTH bound to: 64'b0000000000000000000000000000000100000000000000000000000000000001 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_WRITE bound to: 0 - type: integer Parameter P_READ bound to: 1 - type: integer Parameter P_NUM_MASTER_SLOTS_LOG bound to: 3 - type: integer Parameter P_NUM_SLAVE_SLOTS_LOG bound to: 1 - type: integer Parameter P_AXI_WID_WIDTH bound to: 1 - type: integer Parameter P_ST_AWMESG_WIDTH bound to: 11 - type: integer Parameter P_AA_AWMESG_WIDTH bound to: 65 - type: integer Parameter P_ST_ARMESG_WIDTH bound to: 11 - type: integer Parameter P_AA_ARMESG_WIDTH bound to: 65 - type: integer Parameter P_ST_BMESG_WIDTH bound to: 3 - type: integer Parameter P_ST_RMESG_WIDTH bound to: 35 - type: integer Parameter P_WR_WMESG_WIDTH bound to: 38 - type: integer Parameter P_BYPASS bound to: 0 - type: integer Parameter P_FWD_REV bound to: 1 - type: integer Parameter P_SIMPLE bound to: 7 - type: integer Parameter P_M_AXI_SUPPORTS_READ bound to: 8'b11111111 Parameter P_M_AXI_SUPPORTS_WRITE bound to: 8'b11111111 Parameter P_M_AXI_WRITE_CONNECTIVITY bound to: 256'b1111111111111111111111111111111100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter P_M_AXI_READ_CONNECTIVITY bound to: 256'b1111111111111111111111111111111100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter P_S_AXI_WRITE_CONNECTIVITY bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter P_S_AXI_READ_CONNECTIVITY bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter P_M_AXI_READ_ISSUING bound to: 256'b0000000000000000000000000000000100000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter P_M_AXI_WRITE_ISSUING bound to: 256'b0000000000000000000000000000000100000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter P_DECERR bound to: 2'b11 INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SI bound to: 0 - type: integer Parameter C_DIR bound to: 1 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_NUM_M bound to: 7 - type: integer Parameter C_NUM_M_LOG bound to: 3 - type: integer Parameter C_ACCEPTANCE bound to: 2 - type: integer Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_THREAD_ID_WIDTH bound to: 0 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AMESG_WIDTH bound to: 11 - type: integer Parameter C_RMESG_WIDTH bound to: 35 - type: integer Parameter C_BASE_ID bound to: 2'b00 Parameter C_HIGH_ID bound to: 2'b00 Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_TARGET_QUAL bound to: 7'b1111111 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_RANGE_CHECK bound to: 1 - type: integer Parameter C_ADDR_DECODE bound to: 1 - type: integer Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_WRITE bound to: 0 - type: integer Parameter P_READ bound to: 1 - type: integer Parameter P_RMUX_MESG_WIDTH bound to: 38 - type: integer Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer Parameter P_NONSECURE_BIT bound to: 1 - type: integer Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer Parameter P_M_AXILITE bound to: 7'b0000000 Parameter P_FIXED bound to: 2'b00 Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer Parameter P_NUM_ID_VAL bound to: 1 - type: integer Parameter P_NUM_THREADS bound to: 1 - type: integer Parameter P_M_SECURE_MASK bound to: 7'b0000000 INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_addr_decoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_TARGETS bound to: 7 - type: integer Parameter C_NUM_TARGETS_LOG bound to: 3 - type: integer Parameter C_NUM_RANGES bound to: 1 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_TARGET_ENC bound to: 1 - type: integer Parameter C_TARGET_HOT bound to: 1 - type: integer Parameter C_REGION_ENC bound to: 1 - type: integer Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_TARGET_QUAL bound to: 8'b01111111 Parameter C_RESOLUTION bound to: 2 - type: integer Parameter C_COMPARATOR_THRESHOLD bound to: 6 - type: integer INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b011000000000000000000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_carry_and' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] Parameter C_FAMILY bound to: rtl - type: string INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_carry_and' (148#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:62] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010000000000000000000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized0' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010000001000000000000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized1' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010000001000000100000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized2' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010001001010000000000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized3' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010000000010000000000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized4' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] Parameter C_FAMILY bound to: rtl - type: string Parameter C_VALUE bound to: 30'b010001001010000100000000000000 Parameter C_DATA_WIDTH bound to: 30 - type: integer Parameter C_BITS_PER_LUT bound to: 6 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_comparator_static__parameterized5' (149#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2133] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_addr_decoder' (150#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 8 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter C_USE_FULL bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_ndeep_srl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:1135] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_A_WIDTH bound to: 2 - type: integer Parameter P_SRLASIZE bound to: 5 - type: integer Parameter P_SRLDEPTH bound to: 32 - type: integer Parameter P_NUMSRLS bound to: 1 - type: integer Parameter P_SHIFT_DEPTH bound to: 4 - type: integer INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78115] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (151#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78115] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_ndeep_srl' (152#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:1135] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo' (153#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_RATIO bound to: 8 - type: integer Parameter C_SEL_WIDTH bound to: 3 - type: integer Parameter C_DATA_WIDTH bound to: 38 - type: integer INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42989] INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (154#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:42989] INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc' (155#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor' (156#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SI bound to: 0 - type: integer Parameter C_DIR bound to: 0 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_NUM_M bound to: 7 - type: integer Parameter C_NUM_M_LOG bound to: 3 - type: integer Parameter C_ACCEPTANCE bound to: 2 - type: integer Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_THREAD_ID_WIDTH bound to: 0 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AMESG_WIDTH bound to: 11 - type: integer Parameter C_RMESG_WIDTH bound to: 3 - type: integer Parameter C_BASE_ID bound to: 2'b00 Parameter C_HIGH_ID bound to: 2'b00 Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_TARGET_QUAL bound to: 7'b1111111 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_RANGE_CHECK bound to: 1 - type: integer Parameter C_ADDR_DECODE bound to: 1 - type: integer Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_WRITE bound to: 0 - type: integer Parameter P_READ bound to: 1 - type: integer Parameter P_RMUX_MESG_WIDTH bound to: 6 - type: integer Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer Parameter P_NONSECURE_BIT bound to: 1 - type: integer Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer Parameter P_M_AXILITE bound to: 7'b0000000 Parameter P_FIXED bound to: 2'b00 Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer Parameter P_NUM_ID_VAL bound to: 1 - type: integer Parameter P_NUM_THREADS bound to: 1 - type: integer Parameter P_M_SECURE_MASK bound to: 7'b0000000 INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_RATIO bound to: 8 - type: integer Parameter C_SEL_WIDTH bound to: 3 - type: integer Parameter C_DATA_WIDTH bound to: 6 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized0' (156#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized0' (156#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_splitter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] Parameter C_NUM_M bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_splitter' (157#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4461] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_wdata_router' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4736] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_WMESG_WIDTH bound to: 38 - type: integer Parameter C_NUM_MASTER_SLOTS bound to: 8 - type: integer Parameter C_SELECT_WIDTH bound to: 4 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 4 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer Parameter C_USE_FULL bound to: 1 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer Parameter ZERO bound to: 2'b10 Parameter ONE bound to: 2'b11 Parameter TWO bound to: 2'b01 INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' (158#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_wdata_router' (159#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4736] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SI bound to: 1 - type: integer Parameter C_DIR bound to: 1 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_NUM_M bound to: 7 - type: integer Parameter C_NUM_M_LOG bound to: 3 - type: integer Parameter C_ACCEPTANCE bound to: 2 - type: integer Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_THREAD_ID_WIDTH bound to: 1 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AMESG_WIDTH bound to: 11 - type: integer Parameter C_RMESG_WIDTH bound to: 35 - type: integer Parameter C_BASE_ID bound to: 2'b10 Parameter C_HIGH_ID bound to: 2'b11 Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_TARGET_QUAL bound to: 7'b1111111 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_RANGE_CHECK bound to: 1 - type: integer Parameter C_ADDR_DECODE bound to: 1 - type: integer Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_WRITE bound to: 0 - type: integer Parameter P_READ bound to: 1 - type: integer Parameter P_RMUX_MESG_WIDTH bound to: 38 - type: integer Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer Parameter P_NONSECURE_BIT bound to: 1 - type: integer Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer Parameter P_M_AXILITE bound to: 7'b0000000 Parameter P_FIXED bound to: 2'b00 Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer Parameter P_NUM_ID_VAL bound to: 2 - type: integer Parameter P_NUM_THREADS bound to: 2 - type: integer Parameter P_M_SECURE_MASK bound to: 7'b0000000 INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_arbiter_resp' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:1025] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_S bound to: 8 - type: integer Parameter C_NUM_S_LOG bound to: 3 - type: integer Parameter C_GRANT_ENC bound to: 1 - type: integer Parameter C_GRANT_HOT bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_arbiter_resp' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:1025] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized1' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SI bound to: 1 - type: integer Parameter C_DIR bound to: 0 - type: integer Parameter C_NUM_ADDR_RANGES bound to: 1 - type: integer Parameter C_NUM_M bound to: 7 - type: integer Parameter C_NUM_M_LOG bound to: 3 - type: integer Parameter C_ACCEPTANCE bound to: 2 - type: integer Parameter C_ACCEPTANCE_LOG bound to: 1 - type: integer Parameter C_ID_WIDTH bound to: 2 - type: integer Parameter C_THREAD_ID_WIDTH bound to: 1 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AMESG_WIDTH bound to: 11 - type: integer Parameter C_RMESG_WIDTH bound to: 3 - type: integer Parameter C_BASE_ID bound to: 2'b10 Parameter C_HIGH_ID bound to: 2'b11 Parameter C_BASE_ADDR bound to: 448'b0000000000000000000000000000000001000100101000010000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000100000010000000000000000000000000000000000000000000000000100000010000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 448'b0000000000000000000000000000000001000100101000011111111111111111000000000000000000000000000000000100000000100000111111111111111100000000000000000000000000000000010001001010000011111111111111110000000000000000000000000000000001000000100000011111111111111111000000000000000000000000000000000100000010000000111111111111111100000000000000000000000000000000010000000000000011111111111111110000000000000000000000000000000001111111111111111111111111111111 Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_TARGET_QUAL bound to: 7'b1111111 Parameter C_M_AXI_SECURE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_RANGE_CHECK bound to: 1 - type: integer Parameter C_ADDR_DECODE bound to: 1 - type: integer Parameter C_ERR_MODE bound to: 224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter C_DEBUG bound to: 1 - type: integer Parameter P_WRITE bound to: 0 - type: integer Parameter P_READ bound to: 1 - type: integer Parameter P_RMUX_MESG_WIDTH bound to: 6 - type: integer Parameter P_AXILITE_ERRMODE bound to: 1 - type: integer Parameter P_NONSECURE_BIT bound to: 1 - type: integer Parameter P_NUM_M_LOG_M1 bound to: 3 - type: integer Parameter P_M_AXILITE bound to: 7'b0000000 Parameter P_FIXED bound to: 2'b00 Parameter P_NUM_M_DE_LOG bound to: 3 - type: integer Parameter P_THREAD_ID_WIDTH_M1 bound to: 1 - type: integer Parameter P_NUM_ID_VAL bound to: 2 - type: integer Parameter P_NUM_THREADS bound to: 2 - type: integer Parameter P_M_SECURE_MASK bound to: 7'b0000000 INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_si_transactor__parameterized2' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3800] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_addr_decoder__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_TARGETS bound to: 2 - type: integer Parameter C_NUM_TARGETS_LOG bound to: 1 - type: integer Parameter C_NUM_RANGES bound to: 1 - type: integer Parameter C_ADDR_WIDTH bound to: 2 - type: integer Parameter C_TARGET_ENC bound to: 1 - type: integer Parameter C_TARGET_HOT bound to: 1 - type: integer Parameter C_REGION_ENC bound to: 0 - type: integer Parameter C_BASE_ADDR bound to: 128'b00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 Parameter C_HIGH_ADDR bound to: 128'b00000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000000 Parameter C_TARGET_QUAL bound to: 3'b011 Parameter C_RESOLUTION bound to: 0 - type: integer Parameter C_COMPARATOR_THRESHOLD bound to: 6 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_addr_decoder__parameterized0' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:794] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 8 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer Parameter C_USE_FULL bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:698] INFO: [Synth 8-6157] synthesizing module 'axi_crossbar_v2_1_21_wdata_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4561] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_WMESG_WIDTH bound to: 38 - type: integer Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer Parameter C_SELECT_WIDTH bound to: 1 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 1 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 1 - type: integer Parameter C_USE_FULL bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer Parameter ZERO bound to: 2'b10 Parameter ONE bound to: 2'b11 Parameter TWO bound to: 2'b01 INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:889] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] Parameter C_FAMILY bound to: rtl - type: string Parameter C_RATIO bound to: 2 - type: integer Parameter C_SEL_WIDTH bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 38 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_mux_enc__parameterized1' (160#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v:2452] INFO: [Synth 8-6155] done synthesizing module 'axi_crossbar_v2_1_21_wdata_mux' (161#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:4561] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_20_axi_register_slice__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:3704] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 0 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 7 - type: integer Parameter C_REG_CONFIG_AR bound to: 0 - type: integer Parameter C_REG_CONFIG_R bound to: 1 - type: integer Parameter C_RESERVE_MODE bound to: 0 - type: integer Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter P_FORWARD bound to: 0 - type: integer Parameter P_RESPONSE bound to: 1 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 32 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 32 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized1' (161#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 1 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 32 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 32 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 22 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 1 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 4 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 7 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 9 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 13 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 21 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 22 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 24 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 28 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 32 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 32 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 2 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 4 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 4 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 2 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 37 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized1' (161#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized7' (161#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 37 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_20_axic_register_slice__parameterized8' (161#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1476] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 4 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 37 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 8 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer Parameter C_USE_FULL bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_WMESG_WIDTH bound to: 38 - type: integer Parameter C_NUM_SLAVE_SLOTS bound to: 2 - type: integer Parameter C_SELECT_WIDTH bound to: 1 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_WIDTH bound to: 1 - type: integer Parameter C_MAX_CTRL_FANOUT bound to: 33 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 0 - type: integer Parameter C_USE_FULL bound to: 0 - type: integer Parameter P_FIFO_DEPTH_LOG bound to: 2 - type: integer Parameter P_EMPTY bound to: 2'b11 Parameter P_ALMOSTEMPTY bound to: 2'b00 Parameter P_ALMOSTFULL_TEMP bound to: 3'b110 Parameter P_ALMOSTFULL bound to: 2'b10 Parameter P_NUM_REPS bound to: 1 - type: integer Parameter ZERO bound to: 2'b10 Parameter ONE bound to: 2'b11 Parameter TWO bound to: 2'b01 INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/60de/hdl/axi_data_fifo_v2_1_vl_rfs.v:986] WARNING: [Synth 8-7023] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_20_axi_register_slice' has 93 connections declared, but only 92 given [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3122] Parameter C_AXI_ID_WIDTH bound to: 2 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_RESP bound to: 3 - type: integer Parameter P_WRITE_IDLE bound to: 2'b00 Parameter P_WRITE_DATA bound to: 2'b01 Parameter P_WRITE_RESP bound to: 2'b10 Parameter P_READ_IDLE bound to: 1'b0 Parameter P_READ_DATA bound to: 1'b1 Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/6b0d/hdl/axi_crossbar_v2_1_vl_rfs.v:3633] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_NUM_S bound to: 2 - type: integer Parameter C_NUM_S_LOG bound to: 1 - type: integer Parameter C_NUM_M bound to: 8 - type: integer Parameter C_MESG_WIDTH bound to: 65 - type: integer Parameter C_ARB_PRIORITY bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter P_PRIO_MASK bound to: 2'b00 Parameter C_FAMILY bound to: rtl - type: string Parameter C_RATIO bound to: 2 - type: integer Parameter C_SEL_WIDTH bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 65 - type: integer Parameter C_FAMILY bound to: rtl - type: string Parameter C_RATIO bound to: 2 - type: integer Parameter C_SEL_WIDTH bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_interconnect_0_0' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:2823] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_axi_quad_spi_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: 32'b11111111111111111111111111111111 Parameter C_S_AXI4_HIGHADDR bound to: 32'b00000000000000000000000000000000 Parameter C_LSB_STUP bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_quad_spi' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36696] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_top' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34957] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000001111100 Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 20 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'slave_attachment__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000 Parameter C_IPIF_ABUS_WIDTH bound to: 7 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 124 - type: integer Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 20 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'address_decoder__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] Parameter C_BUS_AWIDTH bound to: 7 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 124 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized65' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 1 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b0000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized65' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized66' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b1000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized66' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized67' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b1100000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif_v3_0_4_pselect_f__parameterized67' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder__parameterized2' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment__parameterized2' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif__parameterized2' (167#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'qspi_core_interface' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19201] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter Async_Clk bound to: 0 - type: integer Parameter C_NUM_CE_SIGNALS bound to: 32 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 0 - type: integer Parameter C_FIFO_EXIST bound to: 1 - type: integer Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_OCCUPANCY_NUM_BITS bound to: 4 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'reset_sync_module' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2426] Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'reset_sync_module' (168#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2426] INFO: [Synth 8-638] synthesizing module 'cross_clk_sync_fifo_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:14937] Parameter C_FAMILY bound to: virtex7 - type: string Parameter Async_Clk bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cross_clk_sync_fifo_1' (169#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:14937] Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 0 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 16 - type: integer Parameter FIFO_SIZE bound to: 512 - type: integer Parameter WR_WIDTH_LOG bound to: 5 - type: integer Parameter WR_DEPTH_LOG bound to: 4 - type: integer Parameter WR_PNTR_WIDTH bound to: 4 - type: integer Parameter RD_PNTR_WIDTH bound to: 4 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 8 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 11 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 11 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 5 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 5 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 Parameter COUNTER_WIDTH bound to: 4 - type: integer Parameter RESET_VALUE bound to: 3 - type: integer Parameter COUNTER_WIDTH bound to: 4 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 512 - type: integer Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 32 - type: integer Parameter READ_DATA_WIDTH_A bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 32 - type: integer Parameter ADDR_WIDTH_A bound to: 4 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 32 - type: integer Parameter READ_DATA_WIDTH_B bound to: 32 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 32 - type: integer Parameter ADDR_WIDTH_B bound to: 4 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 32 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 16 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 32 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 32 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 4 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 4 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 4 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 4 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 32 - type: integer Parameter rstb_loop_iter bound to: 32 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 32 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:484] INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_ecc = "no_ecc" *) on RAM gen_wr_a.gen_word_narrow.mem_reg Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 4 - type: integer Parameter REG_WIDTH bound to: 4 - type: integer Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 5 - type: integer Parameter REG_WIDTH bound to: 5 - type: integer Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 5 - type: integer INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246] Parameter COUNTER_WIDTH bound to: 2 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 Parameter COUNTER_WIDTH bound to: 5 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 4 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-638] synthesizing module 'cdc_sync__parameterized6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 1 - type: integer Parameter C_MTBF_STAGES bound to: 2 - type: integer Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'cdc_sync__parameterized6' (169#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_19_counter_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:669] Parameter C_NUM_BITS bound to: 4 - type: integer Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_19_counter_f' (170#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:669] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 16 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer Parameter C_HAS_RD_ACK bound to: 1 - type: integer Parameter C_HAS_RD_COUNT bound to: 1 - type: integer Parameter C_HAS_RD_ERR bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 1 - type: integer Parameter C_HAS_WR_COUNT bound to: 1 - type: integer Parameter C_HAS_WR_ERR bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_RD_COUNT_WIDTH bound to: 5 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer Parameter C_USE_BLOCKMEM bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_COUNT_WIDTH bound to: 5 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter WRITE_DATA_WIDTH bound to: 32 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 32 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 0 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 16 - type: integer Parameter FIFO_SIZE bound to: 512 - type: integer Parameter WR_WIDTH_LOG bound to: 5 - type: integer Parameter WR_DEPTH_LOG bound to: 4 - type: integer Parameter WR_PNTR_WIDTH bound to: 4 - type: integer Parameter RD_PNTR_WIDTH bound to: 4 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 8 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 11 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 11 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 5 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 5 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg__parameterized1' (170#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a5cb/hdl/lib_fifo_v1_0_rfs.vhd:255] INFO: [Synth 8-638] synthesizing module 'qspi_fifo_ifmodule' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13461] Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_fifo_ifmodule' (171#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13461] INFO: [Synth 8-638] synthesizing module 'qspi_occupancy_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:3647] Parameter C_OCCUPANCY_NUM_BITS bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_occupancy_reg' (172#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:3647] INFO: [Synth 8-638] synthesizing module 'qspi_mode_0_module' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:8775] Parameter C_SCK_RATIO bound to: 16 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 32 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SUB_FAMILY bound to: virtex7 - type: string Parameter C_FIFO_EXIST bound to: 1 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b1 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'qspi_mode_0_module' (173#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:8775] INFO: [Synth 8-638] synthesizing module 'qspi_cntrl_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13816] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'qspi_cntrl_reg' (174#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:13816] INFO: [Synth 8-638] synthesizing module 'qspi_status_slave_sel_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2658] Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_status_slave_sel_reg' (175#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:2658] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_19_soft_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:874] Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer Parameter C_RESET_WIDTH bound to: 16 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_19_soft_reset' (176#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:874] INFO: [Synth 8-638] synthesizing module 'interrupt_control__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'interrupt_control__parameterized1' (176#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg WARNING: [Synth 8-3848] Net cfgclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19178] WARNING: [Synth 8-3848] Net cfgmclk in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19179] WARNING: [Synth 8-3848] Net eos in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19180] WARNING: [Synth 8-3848] Net preq in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19181] WARNING: [Synth 8-3848] Net di in module/entity qspi_core_interface does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19182] INFO: [Synth 8-256] done synthesizing module 'qspi_core_interface' (177#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:19201] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg WARNING: [Synth 8-3848] Net s_axi4_awready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34848] WARNING: [Synth 8-3848] Net s_axi4_wready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34856] WARNING: [Synth 8-3848] Net s_axi4_bid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34860] WARNING: [Synth 8-3848] Net s_axi4_bresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34861] WARNING: [Synth 8-3848] Net s_axi4_bvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34862] WARNING: [Synth 8-3848] Net s_axi4_arready in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34876] WARNING: [Synth 8-3848] Net s_axi4_rid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34880] WARNING: [Synth 8-3848] Net s_axi4_rdata in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34881] WARNING: [Synth 8-3848] Net s_axi4_rresp in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34882] WARNING: [Synth 8-3848] Net s_axi4_rlast in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34883] WARNING: [Synth 8-3848] Net s_axi4_rvalid in module/entity axi_quad_spi_top does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34884] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_top' (178#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:34957] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg WARNING: [Synth 8-3848] Net io0_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36639] WARNING: [Synth 8-3848] Net io0_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36640] WARNING: [Synth 8-3848] Net io1_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36643] WARNING: [Synth 8-3848] Net io1_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36644] WARNING: [Synth 8-3848] Net io2_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36649] WARNING: [Synth 8-3848] Net io2_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36650] WARNING: [Synth 8-3848] Net io3_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36653] WARNING: [Synth 8-3848] Net io3_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36654] WARNING: [Synth 8-3848] Net ss_1_o in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36669] WARNING: [Synth 8-3848] Net ss_1_t in module/entity axi_quad_spi does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36670] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi' (179#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/58f3/hdl/axi_quad_spi_v3_2_rfs.vhd:36696] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_axi_quad_spi_0_0' (180#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/synth/axi4_subsys_axi_quad_spi_0_0.vhd:97] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_jtag_axi_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103] Parameter RD_TXN_QUEUE_LENGTH bound to: 1 - type: integer Parameter WR_TXN_QUEUE_LENGTH bound to: 1 - type: integer Parameter M_AXI_ID_WIDTH bound to: 1 - type: integer Parameter M_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter FAMILY bound to: virtex7 - type: string Parameter M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter M_HAS_BURST bound to: 1 - type: integer Parameter PROTOCOL bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_jtag_axi_0_0' (218#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/synth/axi4_subsys_jtag_axi_0_0.vhd:103] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100] Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_INCLUDE_INTR bound to: 1 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235] Parameter C_INSTANCE bound to: axi4_subsys_xadc_wiz_0_0_axi_xadc - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_INCLUDE_INTR bound to: 1 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000001111111111 Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_IPIF_ABUS_WIDTH bound to: 11 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer Parameter C_USE_WSTRB bound to: 1 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176] Parameter C_BUS_AWIDTH bound to: 10 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 1023 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001111111111 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 5 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b0000000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b0001000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] Parameter C_AB bound to: 1 - type: integer Parameter C_AW bound to: 10 - type: integer Parameter C_BAR bound to: 10'b1000000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized25' (219#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_pselect_f.vhd:167] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_address_decoder' (220#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_address_decoder.vhd:176] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:381] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' (221#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_slave_attachment.vhd:227] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_lite_ipif' (222#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_axi_lite_ipif.vhd:241] Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter CE_NUMBERS bound to: 9 - type: integer Parameter IP_INTR_NUM bound to: 17 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string Parameter MUX_ADDR_NO bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186] Parameter C_S_AXI_ADDR_WIDTH bound to: 11 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter CE_NUMBERS bound to: 9 - type: integer Parameter IP_INTR_NUM bound to: 17 - type: integer Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string Parameter MUX_ADDR_NO bound to: 5 - type: integer Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0010000110100000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0111111100000001 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101011111100100 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1100101000110011 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101001011000110 Parameter INIT_56 bound to: 16'b1001010101010101 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0101000100010001 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_xadc_core_drp' (223#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_xadc_core_drp.vhd:186] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142] Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer Parameter C_RESET_WIDTH bound to: 16 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_soft_reset' (224#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_soft_reset.vhd:142] INFO: [Synth 8-638] synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 544'b0000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_interrupt_control' (225#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/axi4_subsys_xadc_wiz_0_0_interrupt_control.vhd:240] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0_axi_xadc' (226#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0_axi_xadc.vhd:235] INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_xadc_wiz_0_0' (227#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.vhd:100] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'axi4_subsys' (228#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/synth/axi4_subsys.vhd:4667] Parameter DEVICE_ID bound to: 28'b0011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'axi4_subsys_wrapper' (230#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/axi4_subsys_wrapper.vhd:80] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'common_regs'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:603] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'address_sel'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:562] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ipbus'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:650] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg WARNING: [Synth 8-3848] Net ipb_clk_i in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:545] WARNING: [Synth 8-3848] Net rod_gp_led in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:148] WARNING: [Synth 8-3848] Net FP_GP_LED_B in module/entity ROD_system does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:149] INFO: [Synth 8-256] done synthesizing module 'ROD_system' (231#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:207] INFO: [Synth 8-638] synthesizing module 'aurora_64b_rx_12ch' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:339] Parameter CLKCM_CFG bound to: TRUE - type: string Parameter CLKRCV_TRST bound to: TRUE - type: string Parameter CLKSWING_CFG bound to: 2'b11 Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:100] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:119] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:120] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:121] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:122] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:123] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:138] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:155] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:156] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:157] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:164] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:165] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:170] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:171] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:178] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:179] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:180] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:182] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:213] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:222] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:223] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:224] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:225] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:226] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:155] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_CLOCK_MODULE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_CLOCK_MODULE' (234#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_clock_module.vhd:85] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:94] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_cdc_sync_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:300] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:302] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:303] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:304] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:305] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:306] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:307] WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:135] WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_1q_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:143] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_cdc_sync_exdes' (235#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_SUPPORT_RESET_LOGIC' (236#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support_reset_logic.vhd:81] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q_gt_common_wrapper' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_gt_common_wrapper' (237#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_gt_common_wrapper.vhd:84] INFO: [Synth 8-638] synthesizing module 'aurora_rx_1q' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/aurora_rx_1q_stub.vhdl:70] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_support' (238#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_support.vhd:155] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:735] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_1q_exdes' (239#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_1q/aurora_rx_1q_exdes.vhd:100] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:125] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:126] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:127] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:128] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:129] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:144] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:161] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:162] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:163] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:170] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:171] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:176] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:178] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:184] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:185] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:186] INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:188] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:219] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:228] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:229] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:230] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:231] INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:232] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_CLOCK_MODULE' (241#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_clock_module.vhd:85] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81] INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:94] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:300] INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net prmry_ack in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:135] WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity aurora_rx_4l_64b_cdc_sync_exdes does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:143] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_cdc_sync_exdes' (242#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_SUPPORT_RESET_LOGIC' (243#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support_reset_logic.vhd:81] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_gt_common_wrapper' (244#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_gt_common_wrapper.vhd:93] INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/aurora_rx_4l_64b_stub.vhdl:75] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support' (245#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:745] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes' (246#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 0 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107] Parameter USE_COMMON_BLOCK bound to: 0 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'aurora_rx_4l_64b_support__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154] Parameter USE_COMMON_BLOCK bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_support__parameterized1' (246#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/support/aurora_rx_4l_64b_support.vhd:154] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'aurora_module_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:745] INFO: [Synth 8-256] done synthesizing module 'aurora_rx_4l_64b_exdes__parameterized2' (246#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_rx_4l_64b/aurora_rx_4l_64b_exdes.vhd:107] Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool Parameter USE_COMMON_BLOCK bound to: 1 - type: integer Parameter USE_CORE_TRAFFIC bound to: 0 - type: integer Parameter USE_CHIPSCOPE bound to: 0 - type: bool WARNING: [Synth 8-5640] Port 'ck_pwr_dnb' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'ref_ck_sel' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'ck_syncb' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'gttx_reset_in' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'gtrx_reset_in' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'cpll_reset_in' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] WARNING: [Synth 8-5640] Port 'qpll_reset_in' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:521] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:147] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_GT_USRCLK_SOURCE' (247#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_gt_usrclk_source.vhd:87] INFO: [Synth 8-638] synthesizing module 'rod_RO_Tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/rod_RO_Tx_stub.vhdl:51] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_support' (248#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_support.vhd:147] INFO: [Synth 8-638] synthesizing module 'vio_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_0_stub.vhdl:14] INFO: [Synth 8-638] synthesizing module 'ila_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_1_stub.vhdl:14] WARNING: [Synth 8-5640] Port 'probe_out1' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:357] INFO: [Synth 8-638] synthesizing module 'vio_RO_CTL_test' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_RO_CTL_test_stub.vhdl:20] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rod_RO_Tx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:613] INFO: [Synth 8-256] done synthesizing module 'rod_RO_Tx_exdes' (250#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/rod_ro_tx_exdes.vhd:158] Parameter COUNTER_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch' (251#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] INFO: [Synth 8-638] synthesizing module 'combined_ttc_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:91] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 1 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:156] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_USRCLK_SOURCE' (252#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_usrclk_source.vhd:87] WARNING: [Synth 8-5640] Port 'gt0_rxoutclkfabric_out' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:163] INFO: [Synth 8-638] synthesizing module 'MGT_combined_ttc_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/MGT_combined_ttc_rx_stub.vhdl:53] WARNING: [Synth 8-3848] Net GT0_DRPDO_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:143] WARNING: [Synth 8-3848] Net GT0_DRPRDY_COMMON_OUT in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:145] WARNING: [Synth 8-3848] Net gt0_qplloutclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:371] WARNING: [Synth 8-3848] Net gt0_qplloutrefclk_i in module/entity sume_RO_Rx_support does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:372] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_support' (253#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_support.vhd:156] Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RXCTRL_WIDTH bound to: 4 - type: integer Parameter WORDS_IN_BRAM bound to: 512 - type: integer Parameter CHANBOND_SEQ_LEN bound to: 1 - type: integer Parameter COMMA_DOUBLE bound to: 16'b0000010010111100 Parameter START_OF_PACKET_CHAR bound to: 32'b10100101000011110000010110111100 INFO: [Synth 8-638] synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124] Parameter RX_DATA_WIDTH bound to: 32 - type: integer Parameter RXCTRL_WIDTH bound to: 4 - type: integer Parameter WORDS_IN_BRAM bound to: 512 - type: integer Parameter CHANBOND_SEQ_LEN bound to: 1 - type: integer Parameter COMMA_DOUBLE bound to: 16'b0000010010111100 Parameter START_OF_PACKET_CHAR bound to: -1525742148 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:712] WARNING: [Synth 8-3848] Net slip_assert_r in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:171] WARNING: [Synth 8-3848] Net input_to_chanbond_reg_i in module/entity sume_RO_Rx_GT_FRAME_CHECK does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:189] INFO: [Synth 8-256] done synthesizing module 'sume_RO_Rx_GT_FRAME_CHECK' (254#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/sume_ro_rx_gt_frame_check.vhd:124] INFO: [Synth 8-638] synthesizing module 'vio_ttc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_ttc_stub.vhdl:14] INFO: [Synth 8-638] synthesizing module 'ila_2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_2_stub.vhdl:24] INFO: [Synth 8-638] synthesizing module 'rx_registers' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:48] INFO: [Synth 8-256] done synthesizing module 'rx_registers' (255#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/rx_registers.vhd:48] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gt0_frame_check'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:744] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'inst_regs'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:893] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'sume_RO_Rx_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:599] WARNING: [Synth 8-3848] Net gt0_cpllrefclklost_i in module/entity combined_ttc_rx does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:358] INFO: [Synth 8-256] done synthesizing module 'combined_ttc_rx' (256#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/combined_ttc/hdl/combined_ttc_rx.vhd:91] INFO: [Synth 8-638] synthesizing module 'aurora_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'aurora_reset' (257#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'pwr_on_timer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45] Parameter max_count bound to: 32'b00000000000000111111111111111111 INFO: [Synth 8-256] done synthesizing module 'pwr_on_timer' (258#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/pwr_on_timer.vhd:45] INFO: [Synth 8-256] done synthesizing module 'aurora_64b_rx_12ch' (259#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bkpln_efex/hdl/aurora_efex/aurora_64b_rx_12ch.vhd:339] INFO: [Synth 8-638] synthesizing module 'axi_ch0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/axi_ch0_stub.vhdl:17] INFO: [Synth 8-638] synthesizing module 'pp_ctrl_vio' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/pp_ctrl_vio_stub.vhdl:18] WARNING: [Synth 8-5640] Port 'aurora_user_clock_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_user_clock_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_stat_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'aurora_chan_control_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 'bp_data_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tvalid_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tlast_23' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_12' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_13' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_14' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_15' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_16' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_17' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_18' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_19' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_20' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_21' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] WARNING: [Synth 8-5640] Port 's_axis_tready_22' is missing in component declaration [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:863] INFO: [Common 17-14] Message 'Synth 8-5640' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter jfex bound to: 0 - type: integer Parameter sim bound to: 0 - type: integer Parameter tob_0_flx_bp_link bound to: 0 - type: integer Parameter bulk_0_flx_bp_link bound to: 1 - type: integer Parameter bulk_1_flx_bp_link bound to: 2 - type: integer Parameter bulk_2_flx_bp_link bound to: 3 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter bp_width bound to: 64 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_processor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:514] Parameter SIM bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter tob_0_flx_bp_link bound to: 0 - type: integer Parameter bulk_0_flx_bp_link bound to: 1 - type: integer Parameter bulk_1_flx_bp_link bound to: 2 - type: integer Parameter bulk_2_flx_bp_link bound to: 3 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter header_width bound to: 64 - type: integer Parameter event_width bound to: 64 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized1' (259#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'input_fifos' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1069] Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter efex bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 26 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (259#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] INFO: [Synth 8-638] synthesizing module 'backplane_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:76] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 11 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (259#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:186] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:187] INFO: [Synth 8-638] synthesizing module 'ipbus_reg_v' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] Parameter N_REG bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_reg_v' (260#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_reg_v.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:300] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:301] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:335] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:336] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:355] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:356] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:377] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:378] WARNING: [Synth 8-614] signal 'chan_dis' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:397] WARNING: [Synth 8-614] signal 'backplane_control' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:424] INFO: [Synth 8-638] synthesizing module 'priority_encoder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43] INFO: [Synth 8-256] done synthesizing module 'priority_encoder' (261#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/priority_encoder.vhd:43] Parameter COUNTER_WIDTH_40 bound to: 8 - type: integer Parameter reset_count bound to: 16'b0000001111111111 Parameter count_40_term bound to: 8'b01000101 Parameter count_160_term bound to: 8'b01000101 INFO: [Synth 8-638] synthesizing module 'clock_test_ipbus' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81] Parameter COUNTER_WIDTH_40 bound to: 8 - type: integer Parameter reset_count bound to: 16'b0000001111111111 Parameter count_40_term bound to: 8'b01000101 Parameter count_160_term bound to: 8'b01000101 INFO: [Synth 8-256] done synthesizing module 'clock_test_ipbus' (262#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/clock_test_ipbus.vhd:81] WARNING: [Synth 8-3848] Net proc_soft_reset in module/entity backplane_regs does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:53] WARNING: [Synth 8-3848] Net backplane_ttc_control in module/entity backplane_regs does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:72] INFO: [Synth 8-256] done synthesizing module 'backplane_regs' (263#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/backplane_regs.vhd:76] INFO: [Synth 8-638] synthesizing module 'chan_map_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/chan_map_ila_stub.vhdl:15] INFO: [Synth 8-638] synthesizing module 'ttc_chan_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:74] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 17 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (263#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:196] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:197] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:220] INFO: [Synth 8-638] synthesizing module 'watermark' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49] Parameter watermark_width bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'watermark' (264#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watermark.vhd:49] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:257] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:258] INFO: [Synth 8-638] synthesizing module 'threshold_counter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] INFO: [Synth 8-256] done synthesizing module 'threshold_counter' (265#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/threshold_counter.vhd:43] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:284] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:285] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:313] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:314] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:330] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:331] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:358] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:359] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:407] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:408] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:424] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:425] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:442] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:443] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:463] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:464] WARNING: [Synth 8-614] signal 'run_event_count_reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:475] INFO: [Synth 8-638] synthesizing module 'error_counter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] Parameter cwidth bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'error_counter' (266#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] INFO: [Synth 8-256] done synthesizing module 'ttc_chan_regs' (267#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_chan_regs.vhd:74] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'CRC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-256] done synthesizing module 'CRC' (268#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized3' (268#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] INFO: [Synth 8-256] done synthesizing module 'aurora_pipe' (269#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] INFO: [Synth 8-638] synthesizing module 'clock_cross_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/clock_cross_fifo_stub.vhdl:26] INFO: [Synth 8-638] synthesizing module 'aurora_fifo_in_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/aurora_fifo_in_ila_stub.vhdl:25] INFO: [Synth 8-638] synthesizing module 'aurora_fifo_out_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/aurora_fifo_out_ila_stub.vhdl:22] INFO: [Synth 8-638] synthesizing module 'data_fifo_vio' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/data_fifo_vio_stub.vhdl:14] INFO: [Synth 8-638] synthesizing module 'ufc_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:68] INFO: [Synth 8-256] done synthesizing module 'ufc_rx' (270#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ufc_rx.vhd:68] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'fex_chan_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:124] Parameter COUNTER_WIDTH bound to: 5 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 24 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (270#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:347] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:348] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:376] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:377] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:413] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:440] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:441] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:501] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:502] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:525] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:526] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:564] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:565] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:592] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:593] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized5' (270#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:674] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:675] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:704] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:705] INFO: [Synth 8-638] synthesizing module 'error_counter__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] Parameter cwidth bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'error_counter__parameterized0' (270#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/error_counter.vhd:52] WARNING: [Synth 8-614] signal 'master_reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:775] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56] Parameter jfex bound to: 0 - type: integer Parameter COUNTER_WIDTH bound to: 5 - type: integer Parameter GAP_WIDTH bound to: 20 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'self_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66] Parameter GAP_WIDTH bound to: 20 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'self_reset' (271#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/self_reset.vhd:66] INFO: [Synth 8-256] done synthesizing module 'channel_init' (272#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_init.vhd:56] Parameter cwidth bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'edge_error_counter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] Parameter cwidth bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'edge_error_counter' (273#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:897] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:898] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:919] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:920] WARNING: [Synth 8-614] signal 'pp_clock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:925] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:953] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:954] WARNING: [Synth 8-614] signal 'pp_clock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:959] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1122] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1123] WARNING: [Synth 8-614] signal 'pp_clock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1130] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1155] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1156] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1172] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:1173] INFO: [Synth 8-256] done synthesizing module 'fex_chan_regs' (274#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/fex_chan_regs.vhd:124] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:926] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'pulse_stretcher'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:493] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ufc_receiver'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:905] INFO: [Synth 8-256] done synthesizing module 'channel_fifo' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized1' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508] INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized1' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized3' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508] INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized3' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized5' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_pipe'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:508] INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized5' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000100 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized7' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized7' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000101 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized9' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized9' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized11' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized11' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000110 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized11' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized11' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized13' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized13' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000000111 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized13' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized13' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized15' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized15' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001000 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized15' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized15' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized17' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized17' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001001 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized17' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized17' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized19' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized19' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001010 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:198] WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:223] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized19' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized19' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_fifo__parameterized21' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 0 - type: integer Parameter axi_fifo bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter length_lsb bound to: 20 - type: integer Parameter length_msb bound to: 31 - type: integer Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 INFO: [Synth 8-638] synthesizing module 'aurora_pipe__parameterized21' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter channel_num bound to: 12'b000000001011 Parameter lmem bound to: 4'b0000 Parameter max_packet_length bound to: 16'b0000001011111111 WARNING: [Synth 8-614] signal 'reset' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pkt_len_violation_i' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'aurora_chan_stat' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] WARNING: [Synth 8-614] signal 'pipe_lock' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:170] INFO: [Common 17-14] Message 'Synth 8-614' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter COUNTER_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'aurora_pipe__parameterized21' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/aurora_pipe.vhd:64] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'channel_fifo__parameterized21' (275#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_fifo.vhd:154] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gen_reg.registers'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1286] WARNING: [Synth 8-3848] Net aurora_chan_control_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:584] WARNING: [Synth 8-3848] Net tob_s_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:587] WARNING: [Synth 8-3848] Net tob_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:592] WARNING: [Synth 8-3848] Net tob_m_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:593] WARNING: [Synth 8-3848] Net tob_m_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:595] WARNING: [Synth 8-3848] Net tob_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:596] WARNING: [Synth 8-3848] Net tob_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:597] WARNING: [Synth 8-3848] Net hdr_crc_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:598] WARNING: [Synth 8-3848] Net comb_error_tag_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:599] WARNING: [Synth 8-3848] Net calo_m_tvalid_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:602] WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:603] WARNING: [Synth 8-3848] Net calo_s_axis_tready_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:605] WARNING: [Synth 8-3848] Net calo_m_axis_tdata_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:606] WARNING: [Synth 8-3848] Net calo_header_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:607] WARNING: [Synth 8-3848] Net calo_tail_marker_12 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:608] WARNING: [Synth 8-3848] Net aurora_chan_control_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:624] WARNING: [Synth 8-3848] Net tob_s_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:627] WARNING: [Synth 8-3848] Net tob_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:632] WARNING: [Synth 8-3848] Net tob_m_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:633] WARNING: [Synth 8-3848] Net tob_m_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:635] WARNING: [Synth 8-3848] Net tob_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:636] WARNING: [Synth 8-3848] Net tob_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:637] WARNING: [Synth 8-3848] Net hdr_crc_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:638] WARNING: [Synth 8-3848] Net comb_error_tag_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:639] WARNING: [Synth 8-3848] Net calo_m_tvalid_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:642] WARNING: [Synth 8-3848] Net calo_m_fifo_tlast_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:643] WARNING: [Synth 8-3848] Net calo_s_axis_tready_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:645] WARNING: [Synth 8-3848] Net calo_m_axis_tdata_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:646] WARNING: [Synth 8-3848] Net calo_header_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:647] WARNING: [Synth 8-3848] Net calo_tail_marker_13 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:648] WARNING: [Synth 8-3848] Net aurora_chan_control_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:665] WARNING: [Synth 8-3848] Net tob_s_tready_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:668] WARNING: [Synth 8-3848] Net tob_m_tvalid_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:673] WARNING: [Synth 8-3848] Net tob_m_tlast_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:674] WARNING: [Synth 8-3848] Net tob_m_tdata_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:676] WARNING: [Synth 8-3848] Net tob_header_marker_14 in module/entity input_fifos does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:677] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'input_fifos' (276#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/input_fifos.vhd:1069] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4228] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4233] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4238] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:4243] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'tob_processor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:360] Parameter sim bound to: 0 - type: integer Parameter jfex bound to: 0 - type: integer Parameter timeout_1_default bound to: 16'b0000010000000000 Parameter timeout_n_default bound to: 16'b0000000000110000 Parameter wdog_thresh_default bound to: 16'b0010000000000000 Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter header_width bound to: 64 - type: integer Parameter event_width bound to: 64 - type: integer INFO: [Synth 8-638] synthesizing module 'channel_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:329] Parameter bp_width bound to: 64 - type: integer Parameter n bound to: 5 - type: integer Parameter m bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'onehot_dec' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] Parameter n bound to: 5 - type: integer Parameter m bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'onehot_dec' (277#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] INFO: [Synth 8-256] done synthesizing module 'channel_mux' (278#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/channel_mux.vhd:329] Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter event_width bound to: 64 - type: integer Parameter header_width bound to: 64 - type: integer INFO: [Synth 8-638] synthesizing module 'ev_builder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:183] Parameter jfex bound to: 0 - type: integer Parameter bp_width bound to: 64 - type: integer Parameter event_width bound to: 64 - type: integer Parameter header_width bound to: 64 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:602] Parameter n bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'vDFF' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64] Parameter n bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'vDFF' (279#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64] INFO: [Synth 8-638] synthesizing module 'event_builder_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/event_builder_fifo_stub.vhdl:25] INFO: [Synth 8-638] synthesizing module 'event_fifo_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/event_fifo_ila_stub.vhdl:26] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1531] INFO: [Synth 8-638] synthesizing module 'tob_timeout' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:56] INFO: [Synth 8-256] done synthesizing module 'tob_timeout' (280#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_timeout.vhd:56] INFO: [Synth 8-638] synthesizing module 'hdr_in_crc9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39] INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (281#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/osum_crc9d32.vhd:39] INFO: [Synth 8-256] done synthesizing module 'hdr_in_crc9' (282#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/hdr_in_crc9.vhd:50] INFO: [Synth 8-638] synthesizing module 'event_hdr_crc9' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61] INFO: [Synth 8-256] done synthesizing module 'event_hdr_crc9' (283#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_hdr_crc9.vhd:61] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'event_trailer_CRC20' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:58] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010010011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'flx_CRC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010010011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'flx_CRC' (284#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/flx_CRC20.vhd:34] INFO: [Synth 8-256] done synthesizing module 'event_trailer_CRC20' (285#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/event_trailer_CRC20.vhd:58] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'trailer_map' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:59] Parameter jfex bound to: 0 - type: integer Parameter n bound to: 4 - type: integer Parameter m bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'onehot_dec__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] Parameter n bound to: 4 - type: integer Parameter m bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'onehot_dec__parameterized1' (285#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/onehot_dec.vhd:47] WARNING: [Synth 8-3936] Found unconnected internal register 'current_chan_del_reg' and it is trimmed from '5' to '4' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:107] INFO: [Synth 8-256] done synthesizing module 'trailer_map' (286#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/trailer_map.vhd:59] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2137] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'CRC__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b11000001101011001111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized3' (286#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter jfex bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2266] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2270] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2275] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2280] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2285] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2336] INFO: [Synth 8-638] synthesizing module 'ila_ev_builder' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_ev_builder_stub.vhdl:37] Parameter overflow_clock_count bound to: 8'b00001111 INFO: [Synth 8-638] synthesizing module 'watchdog' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watchdog.vhd:44] Parameter overflow_clock_count bound to: 8'b00001111 INFO: [Synth 8-256] done synthesizing module 'watchdog' (287#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/watchdog.vhd:44] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_trailer_crc'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1875] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'state_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:609] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'dbg_trailer_err_map'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2225] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'evnt_trailer_err_map'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1951] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'timeout'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1636] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_trailer_crc'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1890] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_header_crc'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:1851] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'wdog_timer'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:2447] INFO: [Synth 8-256] done synthesizing module 'ev_builder' (288#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ev_builder.vhd:183] Parameter timeout_1_default bound to: 16'b0000010000000000 Parameter timeout_n_default bound to: 16'b0000000000110000 Parameter wdog_thresh_default bound to: 16'b0010000000000000 INFO: [Synth 8-638] synthesizing module 'tob_proc_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:84] Parameter timeout_1_default bound to: 16'b0000010000000000 Parameter timeout_n_default bound to: 16'b0000000000110000 Parameter wdog_thresh_default bound to: 16'b0010000000000000 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 23 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (288#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:258] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:259] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:294] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:295] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:329] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:330] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:364] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:365] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:386] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:387] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:421] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:422] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:473] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:474] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:540] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:541] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:564] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:565] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:594] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:595] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (288#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'default_reg_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/default_reg_ila_stub.vhdl:16] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:676] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:677] Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] Parameter packet_version bound to: 3'b001 Parameter sim bound to: 0 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized6' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 8 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized6' (288#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:114] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:115] INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs' (289#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (289#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_ctrlreg_v.vhd:68] Parameter cwidth bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'edge_error_counter__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] Parameter cwidth bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'edge_error_counter__parameterized1' (289#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/edge_error_counter.vhd:53] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Tob_timeout_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:612] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'wdog_overflow_counter'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:805] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'watchdog_overflow_count_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:782] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'wdog_threshold_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:759] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'watchdog_control_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:747] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'packet_capture'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:698] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'error_count_register'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:664] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Tob_stage_xoff_Count_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:582] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Tob_stage_busy_Count_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:552] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Tob_stage_fifo_status_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:528] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tob_staging_control_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:497] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tob_staging_thresholds_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:483] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_L1id_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:461] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fullmode_fifo_fill_level_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:409] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'stage_fifo_fill_level_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:374] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Full_mode_control_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:343] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'tob_proc_status'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:317] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'debug_fifo_fill_level_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:282] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_fifo_fill_level_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:246] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'Event_fifo_control_reg'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:225] INFO: [Synth 8-256] done synthesizing module 'tob_proc_regs' (290#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_proc_regs.vhd:84] INFO: [Synth 8-638] synthesizing module 'dummy_chan_in' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47] INFO: [Synth 8-256] done synthesizing module 'dummy_chan_in' (291#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/dummy_chan_in.vhd:47] INFO: [Synth 8-638] synthesizing module 'ppmux_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ppmux_ila_stub.vhdl:22] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'input_mux'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:898] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'chan_in_gen'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:1332] INFO: [Synth 8-256] done synthesizing module 'tob_processor' (292#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/tob_processor.vhd:360] INFO: [Synth 8-638] synthesizing module 'ttc_info' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:96] INFO: [Synth 8-638] synthesizing module 'ttc_header_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ttc_header_fifo_stub.vhdl:24] INFO: [Synth 8-638] synthesizing module 'ila_bulk_ttc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_bulk_ttc_stub.vhdl:26] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:518] INFO: [Synth 8-638] synthesizing module 'ila_ttc_in' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_ttc_in_stub.vhdl:29] INFO: [Synth 8-638] synthesizing module 'ila_ttc_out' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_ttc_out_stub.vhdl:19] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'cttc_crc'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:505] INFO: [Synth 8-256] done synthesizing module 'ttc_info' (293#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/ttc_info.vhd:96] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_processor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:166] Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/bulk_ila_stub.vhdl:21] INFO: [Synth 8-638] synthesizing module 'bulk_data_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/bulk_data_fifo_stub.vhdl:25] Parameter COUNTER_WIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_controller' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:79] Parameter n bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'vDFF__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64] Parameter n bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'vDFF__parameterized1' (293#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/ff.vhd:64] INFO: [Synth 8-256] done synthesizing module 'bulk_controller' (294#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_controller.vhd:79] Parameter bp_width bound to: 64 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_channel_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:310] Parameter bp_width bound to: 64 - type: integer Parameter n bound to: 5 - type: integer Parameter m bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_onehot' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46] Parameter n bound to: 5 - type: integer Parameter m bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'bulk_onehot' (295#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_onehot.vhd:46] INFO: [Synth 8-256] done synthesizing module 'bulk_channel_mux' (296#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_channel_mux.vhd:310] Parameter SIM bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'bulk_proc_regs' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:79] Parameter SIM bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter NSLV bound to: 16 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized7' (296#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/slaves/ipbus_fabric_sel.vhd:55] Parameter sim bound to: 1 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'pkt_capture_regs__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] Parameter packet_version bound to: 3'b001 Parameter sim bound to: 1 - type: integer Parameter debug bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'pkt_capture_regs__parameterized1' (296#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pkt_capture_regs.vhd:39] INFO: [Synth 8-256] done synthesizing module 'bulk_proc_regs' (297#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_proc_regs.vhd:79] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'controller'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:745] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'status_regs'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:1117] INFO: [Synth 8-256] done synthesizing module 'bulk_processor' (298#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/bulk_processor/hdl/bulk_processor.vhd:166] Parameter sim bound to: 0 - type: integer Parameter sim bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ro_controller' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:50] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'rod_ROctrl_mux_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/rod_ROctrl_mux_ila_stub.vhdl:19] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ro_crc'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:179] INFO: [Synth 8-256] done synthesizing module 'ro_controller' (299#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/readout_ctrl/hdl/ro_controller.vhd:50] INFO: [Synth 8-256] done synthesizing module 'packet_processor' (300#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/packet_processor.vhd:514] Parameter DEBUG bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'Full_Mode_Tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:122] Parameter DEBUG bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'clk_wiz_240' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/clk_wiz_240_stub.vhdl:16] Parameter debug bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FM_channel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:121] Parameter debug bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FMchannelTXctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35] INFO: [Synth 8-638] synthesizing module 'pulse_pdxx_pwxx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25] Parameter pd bound to: 0 - type: integer Parameter pw bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_pdxx_pwxx' (301#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/pulse_pdxx_pwxx.vhd:25] INFO: [Synth 8-638] synthesizing module 'CRC__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] Parameter Nbits bound to: 32 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC__parameterized4' (301#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/crc.vhd:32] INFO: [Synth 8-256] done synthesizing module 'FMchannelTXctrl' (302#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FMchannelTXctrl.vhd:35] INFO: [Synth 8-638] synthesizing module 'FIFO34to34b' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29] INFO: [Synth 8-638] synthesizing module 'fifo1KB_34bit' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/fifo1KB_34bit_stub.vhdl:22] INFO: [Synth 8-256] done synthesizing module 'FIFO34to34b' (303#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FIFO34to34b.vhd:29] INFO: [Synth 8-638] synthesizing module 'vio_fullmode_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/vio_fullmode_reset_stub.vhdl:23] INFO: [Synth 8-638] synthesizing module 'rst_tmr' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47] INFO: [Synth 8-256] done synthesizing module 'rst_tmr' (304#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/rst_tmr.vhd:47] INFO: [Synth 8-638] synthesizing module 'tx_data_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:57] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:62] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:67] INFO: [Synth 8-256] done synthesizing module 'tx_data_mux' (305#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/tx_data_mux.vhd:53] INFO: [Synth 8-638] synthesizing module 'fm_axi' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51] INFO: [Synth 8-256] done synthesizing module 'fm_axi' (306#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/fm_axi.vhd:51] INFO: [Synth 8-638] synthesizing module 'FM_example_emuram' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22] INFO: [Synth 8-638] synthesizing module 'DPram_32b' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/DPram_32b_stub.vhdl:21] INFO: [Synth 8-256] done synthesizing module 'FM_example_emuram' (307#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_emuram.vhd:22] INFO: [Synth 8-638] synthesizing module 'FM_example_FIFOctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26] INFO: [Synth 8-256] done synthesizing module 'FM_example_FIFOctrl' (308#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/FM_example_FIFOctrl.vhd:26] INFO: [Synth 8-638] synthesizing module 'fm_status_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/fm_status_fifo_stub.vhdl:21] INFO: [Synth 8-638] synthesizing module 'ila_fullmode' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_fullmode_stub.vhdl:14] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_timer'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:701] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ctl0'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:858] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ram0'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:802] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u7'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:564] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u5'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:551] INFO: [Synth 8-256] done synthesizing module 'FM_channel' (309#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:121] Parameter debug bound to: 1 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FM_channel__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:121] Parameter debug bound to: 1 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'axi_ila_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/axi_ila_1_stub.vhdl:26] INFO: [Synth 8-638] synthesizing module 'debug_ila_ed1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/debug_ila_ed1_stub.vhdl:32] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'data_mux'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:718] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_interface'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:738] INFO: [Synth 8-256] done synthesizing module 'FM_channel__parameterized1' (309#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/FM_channel.vhd:121] Parameter NUM_LINKS bound to: 2 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter USE_GREFCLK bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49] Parameter NUM_LINKS bound to: 2 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter USE_GREFCLK bound to: 0 - type: bool Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:462] Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 2 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0 Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b00 Parameter RXPI_CFG2 bound to: 2'b00 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b1 Parameter RXPI_CFG5 bound to: 1'b1 Parameter RXPI_CFG6 bound to: 3'b001 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 10 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b01 Parameter RX_CM_TRIM bound to: 4'b0000 Parameter RX_DATA_WIDTH bound to: 20 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b010 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 10 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386] Parameter INITIALISE bound to: 6'b000000 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter INIT bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_sync_block' (310#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:1386] Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_RX_STARTUP_FSM' (311#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:623] Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 1 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 9 - type: integer Parameter CLK_COR_MIN_LAT bound to: 7 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 2 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0 Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: TRUE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b00 Parameter RXPI_CFG2 bound to: 2'b00 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b1 Parameter RXPI_CFG5 bound to: 1'b1 Parameter RXPI_CFG6 bound to: 3'b001 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: OFF - type: string Parameter RXSYNC_MULTILANE bound to: 1'b0 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 10 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b01 Parameter RX_CM_TRIM bound to: 4'b0000 Parameter RX_DATA_WIDTH bound to: 20 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b010 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXREC - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b111 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b0 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 10 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 25 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 0 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver_TX_STARTUP_FSM' (312#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver_reset_fsm.vhd:51] INFO: [Synth 8-638] synthesizing module 'ila_mgtfsm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_mgtfsm_stub.vhdl:20] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'txresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1902] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[1].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1819] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'g_gt_channel[0].rxresetfsm_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:1819] INFO: [Synth 8-256] done synthesizing module 'FullModeTransceiver' (313#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/example_design_virtex7/fullmodetransceiver.vhd:49] Parameter COUNTER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'pulse_stretch__parameterized7' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] Parameter COUNTER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'pulse_stretch__parameterized7' (313#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/packet_processor/hdl/pulse_stretch.vhd:49] INFO: [Synth 8-256] done synthesizing module 'Full_Mode_Tx' (314#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/fullmode/hdl/new_rod/Full_Mode_Tx.vhd:122] Parameter DEBUG bound to: 0 - type: integer Parameter GTX_TRANSCEIVERS bound to: 0 - type: bool Parameter NUM_LINKS bound to: 2 - type: integer Parameter RECOVER_CLK_FROM_RX_GBT bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'packet_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:63] INFO: [Synth 8-638] synthesizing module 'axis_dwidth_64_32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/axis_dwidth_64_32_stub.vhdl:21] INFO: [Synth 8-638] synthesizing module 'axis_data_fifo_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/axis_data_fifo_0_stub.vhdl:25] INFO: [Synth 8-638] synthesizing module 'ila_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/ila_fifo_stub.vhdl:25] INFO: [Synth 8-256] done synthesizing module 'packet_fifo' (315#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/packet_fifo.vhd:63] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'reset_count' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48] Parameter COUNTER_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'reset_count' (317#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/reset_count.vhd:48] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-638] synthesizing module 'backplane_control_ila' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/.Xil/Vivado-1435-hog-vm0.cern.ch/realtime/backplane_control_ila_stub.vhdl:13] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'backplane'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2095] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_interface_2'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2909] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'fm_interface_1'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2858] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'event_builder'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:2527] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'reset_top'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1834] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'phy_reset'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:1853] INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "no" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* rw_addr_collision = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-5772] Detected attribute (* ram_optimization = "yes" *) on RAM gen_wr_a.gen_word_narrow.mem_reg INFO: [Synth 8-256] done synthesizing module 'top_rod_efex' (318#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/hdl/top_rod_efex.vhd:333] WARNING: [Synth 8-3331] design FullModeTransceiver_TX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design FullModeTransceiver_RX_STARTUP_FSM has unconnected port QPLLREFCLKLOST WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][19] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][18] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][17] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][16] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][15] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][14] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][13] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][12] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][11] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][10] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][9] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][8] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][7] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][6] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][5] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][4] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][3] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][2] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][1] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[0][0] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][19] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][18] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][17] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][16] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][15] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][14] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][13] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][12] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][11] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][10] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][9] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][8] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][7] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][6] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][5] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][4] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][3] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][2] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][1] WARNING: [Synth 8-3331] design FullModeTransceiver has unconnected port rxdata_out[1][0] WARNING: [Synth 8-3331] design FM_channel__parameterized1 has unconnected port app_clk_in WARNING: [Synth 8-3331] design FM_channel has unconnected port app_clk_in WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[15] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[14] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[13] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[12] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[11] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[10] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[9] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[8] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[7] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[6] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[5] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[4] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[3] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_0[2] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[15] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[14] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[13] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[12] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[11] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[10] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[9] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[8] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[7] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[6] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[5] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[4] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[3] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_stat_1[2] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port flx_bp_240_0 WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port flx_bp_240_1 WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[31] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[30] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[29] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[28] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[27] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[26] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[25] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[24] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[23] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[22] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[21] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[20] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[19] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[18] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[17] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[16] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[15] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[14] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[13] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[12] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[11] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[10] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[9] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[8] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[7] WARNING: [Synth 8-3331] design Full_Mode_Tx has unconnected port full_mode_ctrl_0[6] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:01:58 ; elapsed = 00:03:15 . Memory (MB): peak = 3036.840 ; gain = 749.234 ; free physical = 827 ; free virtual = 20161 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:05 ; elapsed = 00:03:22 . Memory (MB): peak = 3036.840 ; gain = 749.234 ; free physical = 913 ; free virtual = 20246 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:05 ; elapsed = 00:03:22 . Memory (MB): peak = 3036.840 ; gain = 749.234 ; free physical = 913 ; free virtual = 20246 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3036.840 ; gain = 0.000 ; free physical = 722 ; free virtual = 20056 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1510 Unisim elements for replacement WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/backplane_control_ila/backplane_control_ila_in_context.xdc] for cell 'bkpln_control_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/backplane_control_ila/backplane_control_ila_in_context.xdc] for cell 'bkpln_control_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo/ila_fifo_in_context.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_0_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_1_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'Bulk_2_64_32/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0/axis_data_fifo_0_in_context.xdc] for cell 'pp_out_fifo_6432/main_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_0_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_1_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'Bulk_2_64_32/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32/axis_dwidth_64_32_in_context.xdc] for cell 'pp_out_fifo_6432/data_width_conv' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_1/u0/ila_resetfsm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_2/u0/ila_resetfsm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm/ila_mgtfsm_in_context.xdc] for cell 'fm_interface_2/u0/ila_resetfsm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/debug_ila_ed1/debug_ila_ed1_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/debug_ila_ed1/debug_ila_ed1_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/debug_ila_ed1/debug_ila_ed1_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/debug_ila_ed1/debug_ila_ed1_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_0/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_1/chan_1/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_0/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_0/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_fm' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode/ila_fullmode_in_context.xdc] for cell 'fm_interface_2/chan_1/ila_fm' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo/fm_status_fifo_in_context.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset/vio_fullmode_reset_in_context.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit/fifo1KB_34bit_in_context.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/axi_ila_1/axi_ila_1_in_context.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/axi_ila_1/axi_ila_1_in_context.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/axi_ila_1/axi_ila_1_in_context.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/axi_ila_1/axi_ila_1_in_context.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_1/clk_blk' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_2/clk_blk' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240/clk_wiz_240_in_context.xdc] for cell 'fm_interface_2/clk_blk' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila_in_context.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_0/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_1/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo/bulk_data_fifo_in_context.xdc] for cell 'event_builder/bulk_2/data_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila/bulk_ila_in_context.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out/ila_ttc_out_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in/ila_ttc_in_in_context.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc/ila_bulk_ttc_in_context.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo/ttc_header_fifo_in_context.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila/ppmux_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila/ppmux_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/default_reg_ila/default_reg_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/default_reg_ila/default_reg_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_ev_builder/ila_ev_builder_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_ev_builder/ila_ev_builder_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo/event_builder_fifo_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila/event_fifo_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila/event_fifo_ila_in_context.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio/data_fifo_vio_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila/aurora_fifo_out_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila/aurora_fifo_in_ila_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo/clock_cross_fifo_in_context.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/chan_map_ila/chan_map_ila_in_context.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/chan_map_ila/chan_map_ila_in_context.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio/pp_ctrl_vio_in_context.xdc] for cell 'vio_pp_ctrl' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio/pp_ctrl_vio_in_context.xdc] for cell 'vio_pp_ctrl' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot4' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot4' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot5' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0/axi_ch0_in_context.xdc] for cell 'ILA_axi_slot5' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2/ila_2_in_context.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/data_fifo_vio_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc/data_fifo_vio_in_context.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx/MGT_combined_ttc_rx_in_context.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test/vio_RO_CTL_test_in_context.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test/vio_RO_CTL_test_in_context.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1/ila_1_in_context.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0/data_fifo_vio_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0/data_fifo_vio_in_context.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx/rod_RO_Tx_in_context.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b/aurora_rx_4l_64b_in_context.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q/aurora_rx_1q_in_context.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2/rgmii_rx_fifo_2_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii/ethernet_mac_rgmii_in_context.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top/vio_top_in_context.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock/packet_processor_clock_in_context.xdc] for cell 'proc_clock_gen' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_0/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_1/chan_1/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_0/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_0/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_1/ram0/RAM_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b/DPram_32b_in_context.xdc] for cell 'fm_interface_2/chan_1/ram0/RAM_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address/vio_ip_address_in_context.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address/vio_ip_address_in_context.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_5/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_6/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_7/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_8/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_9/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0/gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/GEN_BUS2ICAP_RESET/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/BUS2ICAP_SIZE_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/FIFO_RST_CDC_PROCESS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2BUS_STATUS_REGISTER_PROCESS/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2PLB_SYNCH1/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/ICAP2PLB_SYNCH2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/Q' is not a valid endpoint. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] WARNING: [Vivado 12-508] No pins matched 'fm_interface_1/clk_blk/inst/mmcm_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:62] WARNING: [Vivado 12-508] No pins matched 'fm_interface_2/clk_blk/inst/mmcm_adv_inst/CLKOUT0'. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:72] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_rod_efex_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_rod_efex_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_rod_efex_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3292.363 ; gain = 0.000 ; free physical = 416 ; free virtual = 19750 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1267 instances were transformed. BUFGCE => BUFGCTRL: 4 instances FD => FDRE: 336 instances FDP => FDPE: 8 instances FDR => FDRE: 762 instances FDRSE => FDRSE (FDRE, LUT4, VCC): 44 instances IBUFG => IBUF: 1 instance IOBUF => IOBUF (IBUF, OBUFT): 24 instances MULT_AND => LUT2: 62 instances MUXCY_L => MUXCY: 24 instances SRL16 => SRL16E: 2 instances Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3292.367 ; gain = 0.004 ; free physical = 413 ; free virtual = 19748 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_slot4' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ILA_axi_slot5' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'bkpln_control_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'vio_pp_ctrl' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_0_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_1_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/ILA_packet_fifo' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/data_width_conv' at clock pin 'aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'Bulk_2_64_32/main_fifo' at clock pin 'm_axis_aclk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/combined_ttc/ila_rx2_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/readout_ctrl/ila_tx0_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'backplane/readout_ctrl/vio_RO_ctrl_inst' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_0/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_0/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_1/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_1/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_2/bulkl_proc_probe' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/bulk_2/data_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/gen_reg.channel_map_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila' at clock pin 'clk' is different from the actual clock period '3.187', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo' at clock pin 'm_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/readout_controller/readout_ctrl_ila2' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/input_mux_ila' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/debug_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/event_fifo' at clock pin 's_axis_aclk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/bulk_ttc_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_bulk_ttc_fifo' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_ttc_fifo_in' at clock pin 'clk' is different from the actual clock period '6.237', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ila_ttc_fifo_out' at clock pin 'clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'event_builder/ttc_input/ttc_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'fm_interface_1/clk_blk' at clock pin 'clk_in1' is different from the actual clock period '24.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_0/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/chan_1/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_1/u0/ila_resetfsm' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '25.000' specified during out-of-context synthesis of instance 'fm_interface_2/clk_blk' at clock pin 'clk_in1' is different from the actual clock period '24.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_0/u7/FIFO34b' at clock pin 'rd_clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/L1ID_fifo' at clock pin 'rd_clk' is different from the actual clock period '4.990', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/ila_fm' at clock pin 'clk' is different from the actual clock period '4.170', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/vio_fm_reset' at clock pin 'clk' is different from the actual clock period '9.970', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'fm_interface_2/chan_1/ram0/RAM_0' at clock pin 'clka' is different from the actual clock period '4.170', this can lead to different synthesis results. INFO: [Common 17-14] Message 'Timing 38-316' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:03:07 ; elapsed = 00:04:34 . Memory (MB): peak = 3292.367 ; gain = 1004.762 ; free physical = 842 ; free virtual = 20177 --------------------------------------------------------------------------------- INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 1 processes. Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\WRFIFO.WRDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I /IPIC_IF_I/\RD_FIFO.RDDATA_FIFO_I /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:03:09 ; elapsed = 00:04:36 . Memory (MB): peak = 3296.285 ; gain = 1008.680 ; free physical = 801 ; free virtual = 20136 --------------------------------------------------------------------------------- INFO: [Synth 8-5545] ROM "mac_addr" won't be mapped to RAM because address size (56) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "revision" won't be mapped to RAM because address size (56) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "serial_num" won't be mapped to RAM because address size (56) is larger than maximum supported(25) INFO: [Synth 8-802] inferred FSM for state register 'idelay_reset_cnt_reg' in module 'ethernet_mac_rgmii_support_resets' INFO: [Synth 8-5544] ROM "idelayctrl_reset" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "idelay_reset_cnt" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'axi_state_reg' in module 'ethernet_mac_rgmii_axi_lite_sm' INFO: [Synth 8-802] inferred FSM for state register 'mdio_access_sm_reg' in module 'ethernet_mac_rgmii_axi_lite_sm' INFO: [Synth 8-5587] ROM size for "start_mdio" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "drive_mdio" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "int_data_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/ipbus_core/udp_clock_crossing_if.vhd:128] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'emc_addr_ps_reg' in module 'axi_emc_native_interface' INFO: [Synth 8-802] inferred FSM for state register 'crnt_state_reg' in module 'mem_state_machine' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'icap_nstate_cs_reg' in module 'icap_statemachine_shared' INFO: [Synth 8-5544] ROM "abort_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "count_enable_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "icap_we_ns" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'scl_state_reg' in module 'iic_control' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'iic_control' INFO: [Synth 8-5544] ROM "scl_cout" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' INFO: [Synth 8-802] inferred FSM for state register 'gen_axi.write_cs_reg' in module 'axi_crossbar_v2_1_21_decerr_slave' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment__parameterized2' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized2' INFO: [Synth 8-802] inferred FSM for state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' in module 'qspi_mode_0_module' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_10_cmd_decode' INFO: [Synth 8-802] inferred FSM for state register 'wr_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine' INFO: [Synth 8-802] inferred FSM for state register 'rd_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_TX_FIFO | 0001 | 0001 AXI_WR_ADDR | 0010 | 0010 AXI_WR_DATA | 0100 | 0100 AXI_WR_RESPONSE | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_write_axi' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'jtag_axi_v1_2_10_read_axi' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' INFO: [Synth 8-5546] ROM "ctrl_code" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'FullModeTransceiver_RX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "gtrxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "mmcm_reset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "CPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "RXDFEAGCHOLD" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'FullModeTransceiver_TX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "TXUSERRDY" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "gttxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MMCM_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "tx_fsm_reset_done_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "QPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE7 | 000000000000001 | 0000 iSTATE6 | 000000000000010 | 0001 iSTATE2 | 000000000000100 | 0010 iSTATE | 000000000001000 | 0011 iSTATE0 | 000000000010000 | 0100 iSTATE13 | 000000000100000 | 0101 iSTATE11 | 000000001000000 | 0110 iSTATE9 | 000000010000000 | 0111 iSTATE10 | 000000100000000 | 1000 iSTATE8 | 000001000000000 | 1001 iSTATE5 | 000010000000000 | 1010 iSTATE3 | 000100000000000 | 1011 iSTATE4 | 001000000000000 | 1100 iSTATE1 | 010000000000000 | 1101 iSTATE12 | 100000000000000 | 1110 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'idelay_reset_cnt_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_support_resets' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0010 | 00 set_data | 1000 | 01 init | 0100 | 10 poll | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'mdio_access_sm_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- startup | 000000000000000000000001 | 00000 change_speed | 000000000000000000000010 | 00001 mdio_rd | 000000000000000000000100 | 00010 mdio_poll_check | 000000000000000000001000 | 00011 mdio_1g | 000000000000000000010000 | 00100 mdio_10_100 | 000000000000000000100000 | 00101 mdio_rgmii_rd | 000000000000000001000000 | 00110 mdio_rgmii_rd_poll | 000000000000000010000000 | 00111 mdio_rgmii | 000000000000000100000000 | 01000 mdio_delay_rd | 000000000000001000000000 | 01001 mdio_delay_rd_poll | 000000000000010000000000 | 01010 mdio_delay | 000000000000100000000000 | 01011 mdio_restart | 000000000001000000000000 | 01100 mdio_loopback | 000000000010000000000000 | 01101 mdio_stats | 000000000100000000000000 | 01110 mdio_stats_poll_check | 000000001000000000000000 | 01111 reset_mac_rx | 000000010000000000000000 | 10000 reset_mac_tx | 000000100000000000000000 | 10001 cnfg_mdio | 000001000000000000000000 | 10010 cnfg_flow | 000010000000000000000000 | 10011 cnfg_lo_addr | 000100000000000000000000 | 10101 cnfg_hi_addr | 001000000000000000000000 | 10110 cnfg_filter | 010000000000000000000000 | 10100 check_speed | 100000000000000000000000 | 10111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'axi_state_reg' using encoding 'one-hot' in module 'ethernet_mac_rgmii_axi_lite_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000001 | 000 rd_last | 0000010 | 010 rd | 0000100 | 001 wr | 0001000 | 011 wr_wait | 0010000 | 100 wr_last | 0100000 | 110 resp | 1000000 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'emc_addr_ps_reg' using encoding 'one-hot' in module 'axi_emc_native_interface' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000000000000001 | 00000 address_set | 00000000000000010 | 00010 deassert_cen | 00000000000000100 | 00011 write | 00000000000001000 | 00001 dassert_wen | 00000000000010000 | 00110 write_wait | 00000000000100000 | 01000 wait_temp | 00000000001000000 | 01001 assert_cen | 00000000010000000 | 01011 wait_write_ack | 00000000100000000 | 00111 wr_rec_period | 00000001000000000 | 01010 address_rset | 00000010000000000 | 00100 deassert_rcen | 00000100000000000 | 00101 linear_flash_sync_rd | 00001000000000000 | 01101 read | 00010000000000000 | 01100 page_read | 00100000000000000 | 01110 deassert_oen | 01000000000000000 | 01111 wait_rddata_ack | 10000000000000000 | 10000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'crnt_state_reg' using encoding 'one-hot' in module 'mem_state_machine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized0' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- icap_idle | 00000000000001 | 0000 icap_abort0 | 00000000000010 | 0111 icap_write1 | 00000000000100 | 0001 icap_write3 | 00000000001000 | 0011 icap_write4 | 00000000010000 | 0100 icap_write5 | 00000000100000 | 0101 icap_write2 | 00000001000000 | 0010 icap_read1 | 00000010000000 | 0110 icap_abort1 | 00000100000000 | 1001 icap_abort2 | 00001000000000 | 1010 icap_abort3 | 00010000000000 | 1011 icap_abort4 | 00100000000000 | 1100 icap_abort_hang | 01000000000000 | 1000 done | 10000000000000 | 1101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'icap_nstate_cs_reg' using encoding 'one-hot' in module 'icap_statemachine_shared' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000001 | 000 header | 0100000 | 001 ack_header | 1000000 | 010 rcv_data | 0010000 | 011 ack_data | 0001000 | 100 xmit_data | 0000100 | 101 wait_ack | 0000010 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'iic_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- scl_idle | 0000000001 | 0000 start_wait | 0000000010 | 0001 start | 0000000100 | 0010 start_edge | 0000001000 | 0011 scl_low_edge | 0000010000 | 0100 scl_low | 0000100000 | 0101 scl_high_edge | 0001000000 | 0110 scl_high | 0010000000 | 0111 stop_edge | 0100000000 | 1000 stop_wait | 1000000000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'scl_state_reg' using encoding 'one-hot' in module 'iic_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- SM_IDLE | 0010 | 00 SM_CMD_EN | 1000 | 01 SM_CMD_ACCEPTED | 0100 | 10 SM_DONE | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- P_WRITE_IDLE | 001 | 00 P_WRITE_DATA | 010 | 01 P_WRITE_RESP | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_axi.write_cs_reg' using encoding 'one-hot' in module 'axi_crossbar_v2_1_21_decerr_slave' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 1000 | 10 ONE | 0010 | 11 TWO | 0001 | 01 iSTATE | 0100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment__parameterized2' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 0001 | 00 stage1_valid | 0010 | 10 both_stages_valid | 0100 | 11 stage2_valid | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RRST_IDLE | 0001 | 00 RRST_IN | 0010 | 10 RRST_OUT | 0100 | 11 RRST_EXIT | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 0001 | 00 stage1_valid | 0010 | 10 both_stages_valid | 0100 | 11 stage2_valid | 1000 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'one-hot' in module 'xpm_fifo_base__parameterized2' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 transfer_okay | 010 | 01 temp_transfer_okay | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' using encoding 'one-hot' in module 'qspi_mode_0_module' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_CMD_FIFO | 01 | 01 AXI_TRANSACTION | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_cmd_decode' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * RDQ_IDLE | 001 | 001 RDQ_CMD_CNT | 010 | 010 RDQ_DONE_CNT | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'rd_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRQ_IDLE | 001 | 001 WRQ_CMD_CNT | 010 | 010 WRQ_DONE_CNT | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'wr_done_state_reg' in module 'jtag_axi_v1_2_10_jtag_axi_engine' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * READ_AXI | 0001 | 0001 AXI_RD_ADDR | 0010 | 0010 AXI_RD_DATA | 0100 | 0100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'jtag_axi_v1_2_10_read_axi' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- sm_idle | 0010 | 00 sm_read | 1000 | 01 sm_write | 0100 | 10 sm_resp | 0001 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'axi4_subsys_xadc_wiz_0_0_slave_attachment' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 00000000001 | 0000 assert_all_resets | 00000000010 | 0001 wait_for_pll_lock | 00000000100 | 0010 release_pll_reset | 00000001000 | 0011 verify_recclk_stable | 00000010000 | 0100 release_mmcm_reset | 00000100000 | 0101 wait_for_rxusrclk | 00001000000 | 0110 wait_reset_done | 00010000000 | 0111 do_phase_alignment | 00100000000 | 1000 monitor_data_valid | 01000000000 | 1001 fsm_done | 10000000000 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_RX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000000001 | 0000 assert_all_resets | 0000000010 | 0001 wait_for_pll_lock | 0000000100 | 0010 release_pll_reset | 0000001000 | 0011 wait_for_txoutclk | 0000010000 | 0100 release_mmcm_reset | 0000100000 | 0101 wait_for_txusrclk | 0001000000 | 0110 wait_reset_done | 0010000000 | 0111 do_phase_alignment | 0100000000 | 1000 reset_fsm_done | 1000000000 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'one-hot' in module 'FullModeTransceiver_TX_STARTUP_FSM' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:43 ; elapsed = 00:05:18 . Memory (MB): peak = 3296.285 ; gain = 1008.680 ; free physical = 194 ; free virtual = 19407 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE Report RTL Partitions: +------+-----------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------+------------+----------+ |1 |axi4_subsys__GB0 | 1| 34756| |2 |axi4_subsys__GB1 | 1| 11187| |3 |ROD_system__GC0 | 1| 29610| |4 |rod_RO_Tx_exdes__GC0 | 1| 60| |5 |aurora_64b_rx_12ch__GC0 | 1| 4942| |6 |fex_chan_regs | 12| 6311| |7 |channel_fifo__GC0 | 1| 3116| |8 |channel_fifo__parameterized1__GC0 | 1| 3116| |9 |channel_fifo__parameterized3__GC0 | 1| 3116| |10 |channel_fifo__parameterized5__GC0 | 1| 3116| |11 |channel_fifo__parameterized7__GC0 | 1| 3114| |12 |channel_fifo__parameterized9__GC0 | 1| 3114| |13 |channel_fifo__parameterized11__GC0 | 1| 3114| |14 |channel_fifo__parameterized13__GC0 | 1| 3114| |15 |channel_fifo__parameterized15__GC0 | 1| 3114| |16 |channel_fifo__parameterized17__GC0 | 1| 3114| |17 |channel_fifo__parameterized19__GC0 | 1| 3114| |18 |channel_fifo__parameterized21__GC0 | 1| 3114| |19 |input_fifos__GC0 | 1| 6093| |20 |tob_processor | 1| 27877| |21 |packet_processor__GCB1 | 1| 16896| |22 |packet_processor__GCB2 | 1| 2620| |23 |packet_processor__GCB3 | 1| 9861| |24 |top_rod_efex__GC0 | 1| 21192| +------+-----------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 24 Bit Adders := 1 3 Input 17 Bit Adders := 57 2 Input 16 Bit Adders := 72 2 Input 13 Bit Adders := 3 2 Input 12 Bit Adders := 50 2 Input 10 Bit Adders := 11 3 Input 9 Bit Adders := 1 2 Input 9 Bit Adders := 21 2 Input 8 Bit Adders := 63 4 Input 8 Bit Adders := 2 3 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 14 4 Input 7 Bit Adders := 8 3 Input 7 Bit Adders := 2 2 Input 6 Bit Adders := 7 4 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 85 4 Input 5 Bit Adders := 6 3 Input 5 Bit Adders := 4 2 Input 4 Bit Adders := 140 4 Input 4 Bit Adders := 12 3 Input 3 Bit Adders := 1 2 Input 3 Bit Adders := 6 2 Input 2 Bit Adders := 90 4 Input 2 Bit Adders := 2 2 Input 1 Bit Adders := 3 +---XORs : 2 Input 20 Bit XORs := 778 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 2 Input 9 Bit XORs := 1918 2 Input 8 Bit XORs := 7 2 Input 7 Bit XORs := 4 2 Input 6 Bit XORs := 2 2 Input 5 Bit XORs := 4 2 Input 4 Bit XORs := 8 2 Input 1 Bit XORs := 473 4 Input 1 Bit XORs := 66 3 Input 1 Bit XORs := 18 9 Input 1 Bit XORs := 12 21 Input 1 Bit XORs := 6 15 Input 1 Bit XORs := 6 10 Input 1 Bit XORs := 12 19 Input 1 Bit XORs := 6 14 Input 1 Bit XORs := 6 12 Input 1 Bit XORs := 6 7 Input 1 Bit XORs := 6 +---Registers : 128 Bit Registers := 10 120 Bit Registers := 1 112 Bit Registers := 1 96 Bit Registers := 2 80 Bit Registers := 3 65 Bit Registers := 2 64 Bit Registers := 82 63 Bit Registers := 24 57 Bit Registers := 1 56 Bit Registers := 1 48 Bit Registers := 5 45 Bit Registers := 2 42 Bit Registers := 3 38 Bit Registers := 1 37 Bit Registers := 29 36 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 533 24 Bit Registers := 6 22 Bit Registers := 1 21 Bit Registers := 1 20 Bit Registers := 23 17 Bit Registers := 3 16 Bit Registers := 167 14 Bit Registers := 1 13 Bit Registers := 33 12 Bit Registers := 47 11 Bit Registers := 1 10 Bit Registers := 52 9 Bit Registers := 99 8 Bit Registers := 171 7 Bit Registers := 55 6 Bit Registers := 33 5 Bit Registers := 113 4 Bit Registers := 337 3 Bit Registers := 20 2 Bit Registers := 223 1 Bit Registers := 6287 +---RAMs : 256K Bit RAMs := 1 64K Bit RAMs := 4 32K Bit RAMs := 1 4K Bit RAMs := 1 2K Bit RAMs := 1 512 Bit RAMs := 2 +---Muxes : 2 Input 128 Bit Muxes := 8 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 112 Bit Muxes := 1 2 Input 80 Bit Muxes := 12 2 Input 64 Bit Muxes := 21 4 Input 64 Bit Muxes := 4 5 Input 64 Bit Muxes := 1 2 Input 63 Bit Muxes := 24 2 Input 56 Bit Muxes := 1 3 Input 56 Bit Muxes := 1 19 Input 48 Bit Muxes := 1 2 Input 48 Bit Muxes := 6 4 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 2 Input 42 Bit Muxes := 2 3 Input 42 Bit Muxes := 1 2 Input 38 Bit Muxes := 6 3 Input 38 Bit Muxes := 1 2 Input 37 Bit Muxes := 29 3 Input 36 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 40 Input 33 Bit Muxes := 1 2 Input 32 Bit Muxes := 152 5 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 12 24 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 4 24 Input 28 Bit Muxes := 1 2 Input 24 Bit Muxes := 10 24 Input 24 Bit Muxes := 2 5 Input 24 Bit Muxes := 2 3 Input 22 Bit Muxes := 1 2 Input 20 Bit Muxes := 682 4 Input 18 Bit Muxes := 1 58 Input 17 Bit Muxes := 1 24 Input 17 Bit Muxes := 1 2 Input 16 Bit Muxes := 90 5 Input 16 Bit Muxes := 1 3 Input 16 Bit Muxes := 1 14 Input 16 Bit Muxes := 2 4 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 3 15 Input 15 Bit Muxes := 1 33 Input 14 Bit Muxes := 1 2 Input 13 Bit Muxes := 51 4 Input 13 Bit Muxes := 2 8 Input 13 Bit Muxes := 3 17 Input 13 Bit Muxes := 2 2 Input 12 Bit Muxes := 50 14 Input 12 Bit Muxes := 1 5 Input 12 Bit Muxes := 1 11 Input 11 Bit Muxes := 4 2 Input 11 Bit Muxes := 24 2 Input 10 Bit Muxes := 39 10 Input 10 Bit Muxes := 4 4 Input 10 Bit Muxes := 7 3 Input 9 Bit Muxes := 3 2 Input 9 Bit Muxes := 1939 5 Input 9 Bit Muxes := 2 2 Input 8 Bit Muxes := 87 24 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 2 5 Input 8 Bit Muxes := 6 4 Input 8 Bit Muxes := 1 7 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 1 7 Input 7 Bit Muxes := 2 2 Input 7 Bit Muxes := 35 21 Input 7 Bit Muxes := 2 5 Input 7 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 37 24 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 3 6 Input 6 Bit Muxes := 4 5 Input 6 Bit Muxes := 2 8 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 126 17 Input 5 Bit Muxes := 6 4 Input 5 Bit Muxes := 3 6 Input 5 Bit Muxes := 4 3 Input 5 Bit Muxes := 4 5 Input 5 Bit Muxes := 2 25 Input 5 Bit Muxes := 12 18 Input 5 Bit Muxes := 1 27 Input 5 Bit Muxes := 1 24 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 311 3 Input 4 Bit Muxes := 17 7 Input 4 Bit Muxes := 4 5 Input 4 Bit Muxes := 9 4 Input 4 Bit Muxes := 19 6 Input 4 Bit Muxes := 1 12 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 4 2 Input 3 Bit Muxes := 37 4 Input 3 Bit Muxes := 5 3 Input 3 Bit Muxes := 2 7 Input 3 Bit Muxes := 3 14 Input 3 Bit Muxes := 1 11 Input 3 Bit Muxes := 1 24 Input 3 Bit Muxes := 1 8 Input 3 Bit Muxes := 5 13 Input 3 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 9 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 278 3 Input 2 Bit Muxes := 8 5 Input 2 Bit Muxes := 5 7 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 49 24 Input 2 Bit Muxes := 1 6 Input 2 Bit Muxes := 2 11 Input 2 Bit Muxes := 2 13 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 2170 7 Input 1 Bit Muxes := 19 5 Input 1 Bit Muxes := 42 17 Input 1 Bit Muxes := 34 3 Input 1 Bit Muxes := 38 4 Input 1 Bit Muxes := 110 10 Input 1 Bit Muxes := 40 6 Input 1 Bit Muxes := 16 14 Input 1 Bit Muxes := 19 15 Input 1 Bit Muxes := 1 24 Input 1 Bit Muxes := 12 9 Input 1 Bit Muxes := 3 11 Input 1 Bit Muxes := 57 13 Input 1 Bit Muxes := 3 8 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module axi_emc_addr_gen Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 3 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 4 +---Registers : 20 Bit Registers := 1 6 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 6 Bit Muxes := 3 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 9 Module axi_emc_address_decode Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 4 Module cntr_incr_decr_addn_f Detailed RTL Component Info : +---Adders : 3 Input 9 Bit Adders := 1 +---Registers : 9 Bit Registers := 1 Module srl_fifo_rbu_f Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 3 Module axi_emc_v3_0_20_counter_f Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 3 Input 9 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module axi_emc_native_interface Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 3 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 4 4 Bit Registers := 2 2 Bit Registers := 6 1 Bit Registers := 11 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 4 7 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 14 2 Input 4 Bit Muxes := 6 4 Input 3 Bit Muxes := 2 3 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 6 2 Input 1 Bit Muxes := 13 7 Input 1 Bit Muxes := 12 Module ld_arith_reg__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 +---Muxes : 2 Input 1 Bit Muxes := 8 Module ld_arith_reg Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 +---Muxes : 2 Input 1 Bit Muxes := 8 Module emc_common_v3_0_5_ipic_if Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---XORs : 2 Input 8 Bit XORs := 1 +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 14 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 1 Module mem_state_machine Detailed RTL Component Info : +---Registers : 1 Bit Registers := 14 +---Muxes : 58 Input 17 Bit Muxes := 1 2 Input 5 Bit Muxes := 24 17 Input 5 Bit Muxes := 3 3 Input 4 Bit Muxes := 6 2 Input 4 Bit Muxes := 4 7 Input 4 Bit Muxes := 4 5 Input 4 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 36 17 Input 1 Bit Muxes := 34 Module ld_arith_reg__parameterized0__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module ld_arith_reg__parameterized1__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module ld_arith_reg__parameterized1__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module ld_arith_reg__parameterized0__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module ld_arith_reg__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module ld_arith_reg__parameterized2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 16 +---Muxes : 2 Input 1 Bit Muxes := 16 Module ld_arith_reg__parameterized1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 5 +---Muxes : 2 Input 1 Bit Muxes := 5 Module mem_steer Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module io_registers Detailed RTL Component Info : +---Registers : 32 Bit Registers := 4 4 Bit Registers := 5 1 Bit Registers := 9 +---Muxes : 2 Input 32 Bit Muxes := 2 Module EMC Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module axi_emc Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized0 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized3 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized4 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized5 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized6 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized7 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized8 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized9 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized10 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized11 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized12 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized13 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized14 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized15 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized16 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized17 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized18 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized19 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized20 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized21 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized22 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized23 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_pselect_f__parameterized24 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_address_decoder Detailed RTL Component Info : +---Registers : 1 Bit Registers := 29 Module axi4_subsys_xadc_wiz_0_0_slave_attachment Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 7 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 3 +---Muxes : 2 Input 10 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 3 Module axi4_subsys_xadc_wiz_0_0_xadc_core_drp Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 11 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 20 +---Muxes : 4 Input 18 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 1 Module axi4_subsys_xadc_wiz_0_0_soft_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module axi4_subsys_xadc_wiz_0_0_interrupt_control Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 17 +---Registers : 17 Bit Registers := 1 1 Bit Registers := 56 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 19 Module axi4_subsys_xadc_wiz_0_0_axi_xadc Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 14 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 16 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module jtag_axi_v1_2_10_xsdb2txfifo Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module jtag_axi_v1_2_10_xsdb2txfifo__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 64 Bit Registers := 2 4 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module jtag_axi_v1_2_10_xsdb2txfifo__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 64 Bit Registers := 2 4 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module jtag_axi_v1_2_10_rxfifo2xsdb Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module jtag_axi_v1_2_10_xsdb_fifo_interface Detailed RTL Component Info : +---Registers : 16 Bit Registers := 2 8 Bit Registers := 1 5 Bit Registers := 2 2 Bit Registers := 2 1 Bit Registers := 14 +---Muxes : 2 Input 16 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 Module jtag_axi_v1_2_10_cmd_decode__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 5 Module jtag_axi_v1_2_10_cmd_decode Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 5 Module dmem Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 Module memory Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 Module xpm_cdc_gray__parameterized6__6 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 4 Module xpm_cdc_gray__parameterized6 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 4 Module rd_bin_cntr Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 Module compare__3 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module compare Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module rd_status_flags_as Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module rd_handshaking_flags Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rd_fwft Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 Module wr_bin_cntr Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 3 Module compare__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module compare__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module wr_status_flags_as Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module blk_mem_gen_prim_width Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 2 +---Registers : 5 Bit Registers := 2 1 Bit Registers := 8 Module memory__parameterized0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 Module xpm_cdc_gray__parameterized6__4 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 4 Module xpm_cdc_gray__parameterized6__5 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 4 Module rd_bin_cntr__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 Module compare__7 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module compare__6 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module rd_status_flags_as__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module rd_handshaking_flags__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rd_fwft__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 Module wr_bin_cntr__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 3 Module compare__5 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module compare__4 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 Module wr_status_flags_as__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module blk_mem_gen_prim_width__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 2 +---Registers : 5 Bit Registers := 2 1 Bit Registers := 8 Module memory__parameterized1 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 1 Module xpm_cdc_gray__parameterized8__6 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 4 Module xpm_cdc_gray__parameterized8 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 4 Module rd_bin_cntr__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 2 Module compare__parameterized0__4 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module compare__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module rd_status_flags_as__parameterized0 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module rd_handshaking_flags__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rd_fwft__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 Module wr_bin_cntr__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 3 Module compare__parameterized0__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module compare__parameterized0__3 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module wr_status_flags_as__parameterized0 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module blk_mem_gen_prim_width__parameterized0__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 2 +---Registers : 5 Bit Registers := 2 1 Bit Registers := 8 Module memory__parameterized1__2 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 1 Module xpm_cdc_gray__parameterized8__4 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 4 Module xpm_cdc_gray__parameterized8__5 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 4 Module rd_bin_cntr__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 2 Module compare__parameterized0__8 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module compare__parameterized0__7 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module rd_status_flags_as__parameterized0__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 1 Module rd_handshaking_flags__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rd_fwft__3 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 Module wr_bin_cntr__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 3 Module compare__parameterized0__6 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module compare__parameterized0__5 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module wr_status_flags_as__parameterized0__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module jtag_axi_v1_2_10_jtag_axi_engine Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 4 2 Input 4 Bit Adders := 1 +---Registers : 64 Bit Registers := 2 17 Bit Registers := 1 16 Bit Registers := 6 5 Bit Registers := 2 4 Bit Registers := 5 2 Bit Registers := 2 1 Bit Registers := 43 +---Muxes : 4 Input 5 Bit Muxes := 2 4 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 2 2 Input 2 Bit Muxes := 4 2 Input 1 Bit Muxes := 9 4 Input 1 Bit Muxes := 12 Module jtag_axi_v1_2_10_write_axi Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 3 +---Registers : 64 Bit Registers := 1 9 Bit Registers := 2 8 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 5 Input 9 Bit Muxes := 2 2 Input 8 Bit Muxes := 2 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 7 Module jtag_axi_v1_2_10_read_axi Detailed RTL Component Info : +---Registers : 64 Bit Registers := 1 32 Bit Registers := 1 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 9 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized29__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized30__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized31__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized32__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized33__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized34__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized35__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized36__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized37__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized38__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized39__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized40__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized41__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized42__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized43__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized44__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized45__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized47__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized48__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized49__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized50__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized51__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized52__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized53__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized54__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized55__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized56__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized57__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized58__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized59__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized60__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized61__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized62__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized63__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized64__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module address_decoder__parameterized1__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 39 Module slave_attachment__parameterized1__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 9 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 5 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 Module interrupt_control__parameterized0__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 10 Module axi_iic_v2_0_23_soft_reset__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module axi_ipif_ssp1__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module reg_interface__1 Detailed RTL Component Info : +---Registers : 10 Bit Registers := 8 8 Bit Registers := 3 7 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module upcnt_n__1 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 +---Muxes : 2 Input 10 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module upcnt_n__2 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 +---Muxes : 2 Input 10 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module shift8__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module shift8__2 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module upcnt_n__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module iic_control__1 Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 54 +---Muxes : 10 Input 10 Bit Muxes := 1 2 Input 10 Bit Muxes := 13 3 Input 9 Bit Muxes := 1 21 Input 7 Bit Muxes := 1 2 Input 1 Bit Muxes := 37 7 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 1 10 Input 1 Bit Muxes := 10 Module SRL_FIFO__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module SRL_FIFO__parameterized0__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module dynamic_master__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 8 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module SRL_FIFO__parameterized1__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module iic__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 2 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__1 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__1 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__1 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__11 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__11 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__5 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel__5 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__5 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__5 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel__5 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__10 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__10 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__5 Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel__5 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__5 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__5 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel__5 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__11 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__10 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__5 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__9 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__9 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel__4 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__4 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__4 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel__4 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__8 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__8 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__4 Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__4 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__4 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__9 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__8 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__4 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__7 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__7 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__3 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel__3 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel__3 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__6 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__6 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__3 Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel__3 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__3 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__3 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel__3 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__7 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__6 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__3 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__5 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__5 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel__2 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel__2 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__4 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__4 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__2 Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__2 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__2 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__5 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__4 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__2 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__3 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__3 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 4 4 Input 2 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s_aw_channel__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 10 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 4 Input 10 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_b_channel__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 Module axi_protocol_converter_v2_1_20_b2s_incr_cmd__2 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 3 2 Input 9 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_wrap_cmd__2 Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 12 Bit Registers := 2 5 Bit Registers := 1 4 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_cmd_translator__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm__1 Detailed RTL Component Info : +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_ar_channel__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_protocol_converter_v2_1_20_b2s_r_channel__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 2 Module axi_register_slice_v2_1_20_axic_register_slice__3 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized1__1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__2 Detailed RTL Component Info : +---Registers : 63 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 63 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized2__1 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_protocol_converter_v2_1_20_b2s__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_crossbar_v2_1_21_decerr_slave Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 7 +---Muxes : 2 Input 8 Bit Muxes := 1 3 Input 1 Bit Muxes := 9 2 Input 1 Bit Muxes := 12 Module axi_crossbar_v2_1_21_addr_arbiter__1 Detailed RTL Component Info : +---Registers : 65 Bit Registers := 1 8 Bit Registers := 1 2 Bit Registers := 4 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 5 Module axi_crossbar_v2_1_21_addr_arbiter Detailed RTL Component Info : +---Registers : 65 Bit Registers := 1 8 Bit Registers := 1 2 Bit Registers := 4 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 5 Module axi_crossbar_v2_1_21_splitter__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_crossbar_v2_1_21_addr_decoder Detailed RTL Component Info : +---Muxes : 2 Input 7 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module generic_baseblocks_v2_1_0_mux_enc Detailed RTL Component Info : +---Muxes : 2 Input 38 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module axi_crossbar_v2_1_21_si_transactor Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__3 Detailed RTL Component Info : +---Muxes : 2 Input 7 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__5 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module generic_baseblocks_v2_1_0_mux_enc__parameterized0 Detailed RTL Component Info : +---Muxes : 2 Input 6 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module axi_crossbar_v2_1_21_si_transactor__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_splitter__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 3 Module axi_crossbar_v2_1_21_addr_decoder__2 Detailed RTL Component Info : +---Muxes : 2 Input 7 Bit Muxes := 1 Module axi_crossbar_v2_1_21_arbiter_resp Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 Module generic_baseblocks_v2_1_0_mux_enc__1 Detailed RTL Component Info : +---Muxes : 2 Input 38 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module axi_data_fifo_v2_1_19_axic_srl_fifo__3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__4 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_si_transactor__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 5 +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 3 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__1 Detailed RTL Component Info : +---Muxes : 2 Input 7 Bit Muxes := 1 Module axi_crossbar_v2_1_21_arbiter_resp__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 Module generic_baseblocks_v2_1_0_mux_enc__parameterized0__1 Detailed RTL Component Info : +---Muxes : 2 Input 6 Bit Muxes := 3 2 Input 1 Bit Muxes := 4 Module axi_data_fifo_v2_1_19_axic_srl_fifo__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_si_transactor__parameterized2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 5 +---Registers : 2 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 3 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_splitter Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 3 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__1 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__2 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__1 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__3 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__4 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__2 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__5 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__6 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__3 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__3 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__7 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__8 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__4 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__4 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__4 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__9 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__10 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__5 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__5 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__5 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__11 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__12 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0__6 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__6 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__6 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__13 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__14 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9__7 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10__7 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0__15 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_crossbar_v2_1_21_addr_decoder__parameterized0 Detailed RTL Component Info : +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_srl_fifo__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 3 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 3 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized9 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module axi_register_slice_v2_1_20_axic_register_slice__parameterized10 Detailed RTL Component Info : +---Registers : 37 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 37 Bit Muxes := 2 Module axi_crossbar_v2_1_21_crossbar Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 2 Bit Adders := 21 2 Input 1 Bit Adders := 3 +---Registers : 8 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 64 Bit Muxes := 16 2 Input 2 Bit Muxes := 29 2 Input 1 Bit Muxes := 3 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized29 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized30 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized31 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized32 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized33 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized34 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized35 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized36 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized37 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized38 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized39 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized40 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized41 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized42 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized43 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized44 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized45 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized47 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized48 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized49 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized50 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized51 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized52 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized53 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized54 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized55 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized56 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized57 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized58 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized59 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized60 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized61 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized62 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized63 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized64 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module address_decoder__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 39 Module slave_attachment__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 9 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 5 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 Module interrupt_control__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 8 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 10 Module axi_iic_v2_0_23_soft_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module axi_ipif_ssp1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module reg_interface Detailed RTL Component Info : +---Registers : 10 Bit Registers := 8 8 Bit Registers := 3 7 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module upcnt_n__3 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 +---Muxes : 2 Input 10 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module upcnt_n Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 +---Muxes : 2 Input 10 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module shift8__3 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module shift8 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module upcnt_n__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 +---Muxes : 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module iic_control Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 54 +---Muxes : 10 Input 10 Bit Muxes := 1 2 Input 10 Bit Muxes := 13 3 Input 9 Bit Muxes := 1 21 Input 7 Bit Muxes := 1 2 Input 1 Bit Muxes := 37 7 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 1 10 Input 1 Bit Muxes := 10 Module SRL_FIFO Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module SRL_FIFO__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module dynamic_master Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 8 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module SRL_FIFO__parameterized1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module iic Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 2 Input 2 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized4 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized5 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized6 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized7 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized8 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized9 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized10 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized11 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized12 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized13 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized14 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized15 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized16 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized17 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized18 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized19 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized66 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized67 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module address_decoder__parameterized2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 36 Module slave_attachment__parameterized2 Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 7 Bit Registers := 1 6 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 7 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 Module cross_clk_sync_fifo_1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 12 +---Registers : 1 Bit Registers := 6 Module xpm_counter_updn__parameterized7 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized8__3 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_memory_base__parameterized1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 +---RAMs : 512 Bit RAMs := 1 Module xpm_cdc_gray__parameterized2__3 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized2__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_gray__parameterized3 Detailed RTL Component Info : +---XORs : 2 Input 5 Bit XORs := 1 2 Input 1 Bit XORs := 4 +---Registers : 5 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized3__3 Detailed RTL Component Info : +---Registers : 5 Bit Registers := 1 Module xpm_cdc_gray__parameterized2 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_gray__parameterized4 Detailed RTL Component Info : +---XORs : 2 Input 5 Bit XORs := 1 2 Input 1 Bit XORs := 4 +---Registers : 5 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized3 Detailed RTL Component Info : +---Registers : 5 Bit Registers := 1 Module xpm_fifo_reg_bit__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized9 Detailed RTL Component Info : +---Adders : 4 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 Module xpm_cdc_sync_rst__parameterized0__6 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module xpm_cdc_sync_rst__parameterized0 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module xpm_fifo_rst__parameterized0__xdcDup__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module xpm_fifo_reg_bit__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized10__3 Detailed RTL Component Info : +---Adders : 4 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 Module xpm_counter_updn__parameterized11__3 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized8 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized10 Detailed RTL Component Info : +---Adders : 4 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 Module xpm_counter_updn__parameterized11 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_fifo_base__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 3 Input 5 Bit Adders := 2 4 Input 5 Bit Adders := 1 4 Input 4 Bit Adders := 1 +---Registers : 5 Bit Registers := 3 4 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 25 4 Input 2 Bit Muxes := 6 2 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 1 Module axi_quad_spi_v3_2_19_counter_f__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 3 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module xpm_counter_updn__parameterized7__1 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized8__1 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_memory_base__parameterized1__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 +---RAMs : 512 Bit RAMs := 1 Module xpm_cdc_gray__parameterized2__1 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized2__1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_gray__parameterized3__1 Detailed RTL Component Info : +---XORs : 2 Input 5 Bit XORs := 1 2 Input 1 Bit XORs := 4 +---Registers : 5 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized3__1 Detailed RTL Component Info : +---Registers : 5 Bit Registers := 1 Module xpm_cdc_gray__parameterized2__2 Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized2__2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_gray__parameterized4__1 Detailed RTL Component Info : +---XORs : 2 Input 5 Bit XORs := 1 2 Input 1 Bit XORs := 4 +---Registers : 5 Bit Registers := 3 Module xpm_fifo_reg_vec__parameterized3__2 Detailed RTL Component Info : +---Registers : 5 Bit Registers := 1 Module xpm_fifo_reg_bit__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized9__1 Detailed RTL Component Info : +---Adders : 4 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 Module xpm_cdc_sync_rst__parameterized0__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module xpm_cdc_sync_rst__parameterized0__5 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module xpm_fifo_rst__parameterized0 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module xpm_fifo_reg_bit__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized10__1 Detailed RTL Component Info : +---Adders : 4 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 Module xpm_counter_updn__parameterized11__1 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized8__2 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_counter_updn__parameterized10__2 Detailed RTL Component Info : +---Adders : 4 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 Module xpm_counter_updn__parameterized11__2 Detailed RTL Component Info : +---Adders : 4 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module xpm_fifo_base__parameterized2 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 3 Input 5 Bit Adders := 2 4 Input 5 Bit Adders := 1 4 Input 4 Bit Adders := 1 +---Registers : 5 Bit Registers := 3 4 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 25 4 Input 2 Bit Muxes := 6 4 Input 1 Bit Muxes := 2 2 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 1 Module axi_quad_spi_v3_2_19_counter_f Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 3 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module qspi_fifo_ifmodule Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module qspi_mode_0_module Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 2 +---Registers : 32 Bit Registers := 5 7 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 28 +---Muxes : 2 Input 32 Bit Muxes := 9 2 Input 7 Bit Muxes := 1 11 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 25 4 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 Module qspi_cntrl_reg Detailed RTL Component Info : +---Registers : 1 Bit Registers := 10 Module qspi_status_slave_sel_reg Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module axi_quad_spi_v3_2_19_soft_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module interrupt_control__parameterized1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 14 +---Registers : 14 Bit Registers := 1 1 Bit Registers := 19 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 16 Module qspi_core_interface Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 2 +---Registers : 32 Bit Registers := 1 4 Bit Registers := 2 1 Bit Registers := 31 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 10 Module axi_quad_spi_top Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized3__2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized4__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized5__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized6__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized7__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized8__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized9__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized10__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized11__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized12__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized13__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized14__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized15__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized16__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized17__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized18__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized19__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized20 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized21__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized22__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized23__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized24__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized25__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized26__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized27__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized28__1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module address_decoder__parameterized0 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 27 Module slave_attachment__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 9 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 5 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 Module xpm_counter_updn Detailed RTL Component Info : +---Adders : 4 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 Module xpm_counter_updn__parameterized0__1 Detailed RTL Component Info : +---Adders : 4 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 Module xpm_memory_base Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 2K Bit RAMs := 1 Module xpm_cdc_gray__1 Detailed RTL Component Info : +---XORs : 2 Input 6 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 6 Bit Registers := 5 Module xpm_fifo_reg_vec__1 Detailed RTL Component Info : +---Registers : 6 Bit Registers := 1 Module xpm_cdc_gray__parameterized0__3 Detailed RTL Component Info : +---XORs : 2 Input 7 Bit XORs := 1 2 Input 1 Bit XORs := 6 +---Registers : 7 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized0__3 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 Module xpm_cdc_gray Detailed RTL Component Info : +---XORs : 2 Input 6 Bit XORs := 1 2 Input 1 Bit XORs := 5 +---Registers : 6 Bit Registers := 5 Module xpm_fifo_reg_vec Detailed RTL Component Info : +---Registers : 6 Bit Registers := 1 Module xpm_cdc_gray__parameterized0 Detailed RTL Component Info : +---XORs : 2 Input 7 Bit XORs := 1 2 Input 1 Bit XORs := 6 +---Registers : 7 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized0 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 Module xpm_cdc_sync_rst__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_sync_rst Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_fifo_rst__xdcDup__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module xpm_fifo_reg_bit__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized1__1 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_counter_updn__parameterized2__1 Detailed RTL Component Info : +---Adders : 4 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 Module xpm_counter_updn__parameterized0 Detailed RTL Component Info : +---Adders : 4 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 Module xpm_counter_updn__parameterized1 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_counter_updn__parameterized2 Detailed RTL Component Info : +---Adders : 4 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 Module xpm_fifo_base Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 3 Input 7 Bit Adders := 2 4 Input 6 Bit Adders := 1 +---Registers : 7 Bit Registers := 3 6 Bit Registers := 1 1 Bit Registers := 11 Module xpm_counter_updn__parameterized3 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_counter_updn__parameterized4__1 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_memory_base__parameterized0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 +---RAMs : 4K Bit RAMs := 1 Module xpm_cdc_gray__parameterized0__1 Detailed RTL Component Info : +---XORs : 2 Input 7 Bit XORs := 1 2 Input 1 Bit XORs := 6 +---Registers : 7 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized0__1 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 Module xpm_cdc_gray__parameterized1__1 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized1__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 Module xpm_cdc_gray__parameterized0__2 Detailed RTL Component Info : +---XORs : 2 Input 7 Bit XORs := 1 2 Input 1 Bit XORs := 6 +---Registers : 7 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized0__2 Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 Module xpm_cdc_gray__parameterized1 Detailed RTL Component Info : +---XORs : 2 Input 8 Bit XORs := 1 2 Input 1 Bit XORs := 7 +---Registers : 8 Bit Registers := 5 Module xpm_fifo_reg_vec__parameterized1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 Module xpm_cdc_sync_rst__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_cdc_sync_rst__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module xpm_fifo_rst Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 6 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 8 5 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 3 Module xpm_fifo_reg_bit__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_fifo_reg_bit__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module xpm_counter_updn__parameterized5__1 Detailed RTL Component Info : +---Adders : 4 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 Module xpm_counter_updn__parameterized6__1 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_counter_updn__parameterized4 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_counter_updn__parameterized5 Detailed RTL Component Info : +---Adders : 4 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 Module xpm_counter_updn__parameterized6 Detailed RTL Component Info : +---Adders : 4 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 Module xpm_fifo_base__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 3 Input 8 Bit Adders := 2 4 Input 7 Bit Adders := 1 +---Registers : 8 Bit Registers := 3 7 Bit Registers := 1 1 Bit Registers := 11 Module axi_hwicap_v3_0_24_ipic_if Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 2 12 Bit Registers := 2 5 Bit Registers := 1 1 Bit Registers := 18 +---Muxes : 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module icap_statemachine_shared Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 4 12 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 17 +---Muxes : 33 Input 14 Bit Muxes := 1 14 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 14 Input 1 Bit Muxes := 19 Module hwicap_shared Detailed RTL Component Info : +---Registers : 1 Bit Registers := 9 +---Muxes : 2 Input 1 Bit Muxes := 2 Module interrupt_control Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 2 Input 32 Bit Muxes := 3 2 Input 1 Bit Muxes := 6 Module axi_hwicap Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 4 Module axi_lite_ipif_v3_0_4_pselect_f Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized0 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized1 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module axi_lite_ipif_v3_0_4_pselect_f__parameterized2 Detailed RTL Component Info : +---Muxes : 2 Input 1 Bit Muxes := 1 Module address_decoder Detailed RTL Component Info : +---Registers : 1 Bit Registers := 6 Module slave_attachment Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 7 +---Muxes : 2 Input 9 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 5 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 3 Module GPIO_Core Detailed RTL Component Info : +---Registers : 24 Bit Registers := 3 16 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 5 Input 32 Bit Muxes := 1 2 Input 24 Bit Muxes := 3 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module axi_gpio Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_sel Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 6 Module syncreg_r__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__parameterized0__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module syncreg_r__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__parameterized0__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_ctrlreg_v Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 Module syncreg_r__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__parameterized0 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module syncreg_r__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module dna_reader Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 57 Bit Registers := 1 7 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module dna_decoder Detailed RTL Component Info : +---Muxes : 19 Input 48 Bit Muxes := 1 24 Input 8 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 24 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 Module common_IdVersion_regs Detailed RTL Component Info : +---Muxes : 7 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 Module ethernet_mac_rgmii_example_design_clocks Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ethernet_mac_rgmii_example_design_resets Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 7 Module ethernet_mac_rgmii_support_resets Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 15 Input 15 Bit Muxes := 1 15 Input 1 Bit Muxes := 1 Module ethernet_mac_rgmii_axi_lite_sm Detailed RTL Component Info : +---Registers : 37 Bit Registers := 1 32 Bit Registers := 4 21 Bit Registers := 1 17 Bit Registers := 1 12 Bit Registers := 2 8 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 20 +---Muxes : 2 Input 37 Bit Muxes := 1 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 24 Input 32 Bit Muxes := 1 24 Input 24 Bit Muxes := 1 2 Input 24 Bit Muxes := 3 24 Input 17 Bit Muxes := 1 2 Input 12 Bit Muxes := 10 5 Input 12 Bit Muxes := 1 24 Input 6 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 1 24 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 31 4 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 1 24 Input 1 Bit Muxes := 10 Module ipbus_clock_div Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 Module ipbus_clock_div__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 Module led_stretcher Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 7 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 1 Bit Muxes := 1 Module clocks_7s_extphy Detailed RTL Component Info : +---Registers : 1 Bit Registers := 8 Module udp_rarp_block Detailed RTL Component Info : +---Adders : 2 Input 24 Bit Adders := 1 2 Input 6 Bit Adders := 2 +---XORs : 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 +---Registers : 56 Bit Registers := 1 42 Bit Registers := 1 24 Bit Registers := 1 16 Bit Registers := 2 13 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 4 5 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 2 Input 56 Bit Muxes := 1 3 Input 56 Bit Muxes := 1 2 Input 42 Bit Muxes := 2 2 Input 24 Bit Muxes := 1 2 Input 16 Bit Muxes := 4 2 Input 8 Bit Muxes := 1 2 Input 6 Bit Muxes := 3 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 1 Module udp_build_arp Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 48 Bit Registers := 3 13 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 5 1 Bit Registers := 10 +---Muxes : 2 Input 48 Bit Muxes := 5 4 Input 48 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 3 Input 6 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 11 2 Input 3 Bit Muxes := 1 6 Input 2 Bit Muxes := 2 6 Input 1 Bit Muxes := 2 2 Input 1 Bit Muxes := 9 3 Input 1 Bit Muxes := 1 Module udp_build_ping Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 +---Registers : 16 Bit Registers := 3 13 Bit Registers := 7 8 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 20 +---Muxes : 2 Input 16 Bit Muxes := 10 5 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 11 4 Input 13 Bit Muxes := 2 2 Input 8 Bit Muxes := 3 2 Input 6 Bit Muxes := 4 6 Input 6 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 5 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 20 6 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 5 3 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 Module udp_ipaddr_block Detailed RTL Component Info : +---Registers : 80 Bit Registers := 3 48 Bit Registers := 1 42 Bit Registers := 1 32 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 80 Bit Muxes := 12 2 Input 1 Bit Muxes := 1 Module udp_build_payload Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 5 13 Bit Registers := 8 8 Bit Registers := 3 1 Bit Registers := 30 +---Muxes : 2 Input 32 Bit Muxes := 4 2 Input 16 Bit Muxes := 12 3 Input 16 Bit Muxes := 1 14 Input 16 Bit Muxes := 2 4 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 17 2 Input 8 Bit Muxes := 6 6 Input 8 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 13 Input 3 Bit Muxes := 1 11 Input 2 Bit Muxes := 2 13 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 34 9 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 2 11 Input 1 Bit Muxes := 1 13 Input 1 Bit Muxes := 3 Module udp_build_resend Detailed RTL Component Info : +---Registers : 45 Bit Registers := 1 16 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 8 Module udp_build_status Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 13 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 5 1 Bit Registers := 11 +---Muxes : 2 Input 128 Bit Muxes := 2 2 Input 8 Bit Muxes := 2 2 Input 7 Bit Muxes := 12 2 Input 6 Bit Muxes := 2 7 Input 6 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 9 8 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 3 Module udp_status_buffer Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 128 Bit Registers := 4 16 Bit Registers := 2 8 Bit Registers := 1 5 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 128 Bit Muxes := 4 4 Input 128 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 16 Bit Muxes := 4 2 Input 8 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 2 Input 5 Bit Muxes := 3 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 25 4 Input 1 Bit Muxes := 2 Module udp_byte_sum__1 Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 5 8 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 9 Bit Muxes := 10 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 10 Module udp_do_rx_reset Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module udp_packet_parser Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 120 Bit Registers := 1 112 Bit Registers := 1 48 Bit Registers := 1 45 Bit Registers := 1 42 Bit Registers := 1 38 Bit Registers := 1 36 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 4 24 Bit Registers := 2 22 Bit Registers := 1 16 Bit Registers := 1 10 Bit Registers := 1 6 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 31 +---Muxes : 2 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 112 Bit Muxes := 1 2 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 3 Input 42 Bit Muxes := 1 3 Input 38 Bit Muxes := 1 3 Input 36 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 24 Bit Muxes := 2 5 Input 24 Bit Muxes := 2 3 Input 22 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 4 Input 10 Bit Muxes := 1 5 Input 8 Bit Muxes := 5 6 Input 8 Bit Muxes := 1 5 Input 7 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 5 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 76 4 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 Module udp_rxram_mux Detailed RTL Component Info : +---Registers : 13 Bit Registers := 2 8 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 3 Bit Muxes := 2 5 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 Module udp_DualPortRAM Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module udp_buffer_selector Detailed RTL Component Info : +---Registers : 2 Bit Registers := 6 1 Bit Registers := 10 +---Muxes : 2 Input 2 Bit Muxes := 17 2 Input 1 Bit Muxes := 5 Module udp_rxram_shim Detailed RTL Component Info : +---Registers : 13 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 2 Input 13 Bit Muxes := 1 Module udp_DualPortRAM_rx Detailed RTL Component Info : +---Registers : 8 Bit Registers := 4 +---RAMs : 64K Bit RAMs := 4 +---Muxes : 4 Input 1 Bit Muxes := 4 Module udp_buffer_selector__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 6 4 Bit Registers := 4 1 Bit Registers := 6 +---Muxes : 2 Input 16 Bit Muxes := 17 2 Input 4 Bit Muxes := 10 2 Input 1 Bit Muxes := 3 Module udp_rxtransactor_if Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 3 Module udp_DualPortRAM_tx Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 +---Muxes : 4 Input 8 Bit Muxes := 1 Module udp_buffer_selector__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 6 4 Bit Registers := 4 1 Bit Registers := 6 +---Muxes : 2 Input 16 Bit Muxes := 17 2 Input 4 Bit Muxes := 10 2 Input 1 Bit Muxes := 3 Module udp_byte_sum Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 5 8 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 9 Bit Muxes := 10 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 10 Module udp_tx_mux Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 7 13 Bit Registers := 10 8 Bit Registers := 7 5 Bit Registers := 2 3 Bit Registers := 2 1 Bit Registers := 44 +---Muxes : 2 Input 32 Bit Muxes := 5 2 Input 16 Bit Muxes := 6 18 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 22 8 Input 13 Bit Muxes := 3 17 Input 13 Bit Muxes := 2 2 Input 8 Bit Muxes := 21 7 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 2 2 Input 5 Bit Muxes := 6 2 Input 3 Bit Muxes := 11 9 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 8 Input 1 Bit Muxes := 8 2 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 2 9 Input 1 Bit Muxes := 2 5 Input 1 Bit Muxes := 2 16 Input 1 Bit Muxes := 4 Module udp_txtransactor_if Detailed RTL Component Info : +---Registers : 16 Bit Registers := 16 4 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 16 Input 1 Bit Muxes := 1 Module udp_clock_crossing_if Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 10 +---Registers : 4 Bit Registers := 5 3 Bit Registers := 7 2 Bit Registers := 5 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 3 Bit Muxes := 2 Module UDP_if Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 8 Bit Muxes := 1 Module transactor_if Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 7 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 3 7 Input 1 Bit Muxes := 1 Module transactor_sm Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 8 Bit Adders := 3 +---Registers : 32 Bit Registers := 5 8 Bit Registers := 3 4 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 5 3 Input 8 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 6 2 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 6 Input 1 Bit Muxes := 1 Module transactor_cfg Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 +---Muxes : 2 Input 128 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized0__1 Detailed RTL Component Info : +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module ipbus_axi4_bridge Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 1 Bit Muxes := 2 Module ipbus_example Detailed RTL Component Info : +---Muxes : 5 Input 3 Bit Muxes := 1 Module rod_RO_Tx_exdes Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module aurora_rx_1q_cdc_sync_exdes Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes__xdcDup__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes__xdcDup__1 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_1q_cdc_sync_exdes__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC__10 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes__xdcDup__2 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__9 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes__xdcDup__2 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_1q_cdc_sync_exdes__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC__9 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes__xdcDup__3 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__8 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes__xdcDup__3 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_1q_cdc_sync_exdes__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC__8 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes__xdcDup__4 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__7 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes__parameterized2 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_1q_cdc_sync_exdes__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC__7 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes__xdcDup__5 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes__xdcDup__4 Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_1q_cdc_sync_exdes__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_1q_SUPPORT_RESET_LOGIC__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_1q_exdes Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module aurora_rx_4l_64b_cdc_sync_exdes__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module aurora_rx_4l_64b_SUPPORT_RESET_LOGIC__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 Module aurora_rx_4l_64b_exdes Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 8 Module pulse_stretch Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 6 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module sume_RO_Rx_GT_FRAME_CHECK Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 1 2 Input 7 Bit Adders := 1 +---Registers : 32 Bit Registers := 3 9 Bit Registers := 1 7 Bit Registers := 1 4 Bit Registers := 3 2 Bit Registers := 1 1 Bit Registers := 19 +---Muxes : 4 Input 32 Bit Muxes := 1 3 Input 7 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 10 Module rx_registers Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 32 Bit Registers := 4 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module combined_ttc_rx Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 1 Bit Registers := 3 Module aurora_reset__1 Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 1 Bit Muxes := 10 5 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 Module pwr_on_timer Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module ipbus_fabric_sel__parameterized4 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 24 Module ipbus_reg_v__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__3 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__3 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module syncreg_r__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__4 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_reg_v__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__4 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__5 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module syncreg_r__15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__6 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_reg_v__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module pulse_stretch__parameterized5 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_reg_v__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__16 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module error_counter__parameterized0__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module error_counter__parameterized0__2 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module error_counter__parameterized0__3 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module error_counter__parameterized0__4 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module error_counter__parameterized0__5 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module error_counter__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 Module pulse_stretch__parameterized5__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_reset Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 1 Bit Muxes := 10 5 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 Module self_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module edge_error_counter Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__18 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__20 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__18 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__22 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__23 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__20 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module fex_chan_regs Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 25 Input 5 Bit Muxes := 1 Module pulse_stretch__parameterized1__3 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__1 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__1 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__4 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__2 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__2 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized1 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__2 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__5 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__3 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__3 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized3 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__3 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__6 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__4 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__4 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized5 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__4 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__7 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__5 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__5 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized7 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__5 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__8 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__6 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__6 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized9 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__6 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__9 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__7 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__7 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized11 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__7 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__10 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__8 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__8 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized13 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__8 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__11 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__9 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__9 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized15 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__9 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__12 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__10 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__10 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized17 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__10 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__13 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__11 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3__11 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized19 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx__11 Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module pulse_stretch__parameterized1__14 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module CRC__12 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized3 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module aurora_pipe__parameterized21 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 5 9 Bit Registers := 1 1 Bit Registers := 36 +---Muxes : 2 Input 1 Bit Muxes := 3 Module ufc_rx Detailed RTL Component Info : +---XORs : 4 Input 1 Bit XORs := 4 +---Registers : 16 Bit Registers := 4 4 Bit Registers := 2 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module channel_fifo__parameterized21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 5 Module ipbus_fabric_sel__parameterized1 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 26 Module ipbus_fabric_sel__parameterized2 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 11 Module syncreg_r__35 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__32 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__18 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__20 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__36 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__33 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__22 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__37 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__34 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__38 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__35 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__39 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__36 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module priority_encoder Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 +---Muxes : 24 Input 28 Bit Muxes := 1 24 Input 24 Bit Muxes := 1 24 Input 1 Bit Muxes := 2 Module clock_test_ipbus Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 4 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module backplane_regs Detailed RTL Component Info : +---Muxes : 12 Input 4 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 17 Module ipbus_reg_v__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__24 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__25 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__22 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__5 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__26 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__23 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__7 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module syncreg_r__27 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__24 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__28 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__25 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__29 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__26 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__30 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__27 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__16 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__31 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__28 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__32 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__29 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__33 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__30 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__34 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__31 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module error_counter__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 Module error_counter__2 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 Module error_counter Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 Module ttc_chan_regs Detailed RTL Component Info : +---Muxes : 18 Input 5 Bit Muxes := 1 Module input_fifos Detailed RTL Component Info : +---Muxes : 27 Input 5 Bit Muxes := 1 Module channel_mux Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 64 Bit Registers := 1 5 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 7 Module vDFF Detailed RTL Component Info : +---Registers : 6 Bit Registers := 1 Module tob_timeout Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 2 Module osum_crc9d32__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module hdr_in_crc9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module osum_crc9d32__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module event_hdr_crc9__3 Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module flx_CRC__1 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 147 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module event_trailer_CRC20__1 Detailed RTL Component Info : +---Muxes : 2 Input 64 Bit Muxes := 1 Module flx_CRC Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 147 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module event_trailer_CRC20 Detailed RTL Component Info : +---Muxes : 2 Input 64 Bit Muxes := 1 Module trailer_map__1 Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module CRC__13 Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module CRC__parameterized3 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 148 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module trailer_map Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 5 Module watchdog Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 8 Bit Muxes := 5 Module ev_builder Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 2 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 3 20 Bit Registers := 1 16 Bit Registers := 1 5 Bit Registers := 3 1 Bit Registers := 17 +---Muxes : 2 Input 64 Bit Muxes := 2 4 Input 64 Bit Muxes := 1 5 Input 64 Bit Muxes := 1 40 Input 33 Bit Muxes := 1 2 Input 6 Bit Muxes := 2 6 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 2 2 Input 5 Bit Muxes := 7 3 Input 5 Bit Muxes := 2 4 Input 5 Bit Muxes := 1 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 4 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 Module ipbus_fabric_sel__parameterized5 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 23 Module ipbus_reg_v__24 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__25 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__47 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__44 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__6 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__48 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__45 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__7 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__49 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__46 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__26 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__50 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__47 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__51 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__48 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__8 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__52 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__49 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__9 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__53 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__50 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__27 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__28 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__29 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__54 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__51 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__55 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__52 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__8 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module syncreg_r__56 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__53 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module threshold_counter__9 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_ctrlreg_v__parameterized0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module syncreg_r__57 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__54 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__30 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_fabric_sel__parameterized6__3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module ipbus_reg_v__23 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__40 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__37 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__41 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__38 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__42 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__39 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__43 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__40 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__44 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__41 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__45 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__42 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__46 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__43 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module pkt_capture_regs Detailed RTL Component Info : +---Registers : 64 Bit Registers := 2 32 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 9 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_reg_v__31 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_ctrlreg_v__parameterized1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module syncreg_r__58 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__55 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module edge_error_counter__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module tob_proc_regs Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 +---Registers : 8 Bit Registers := 2 +---Muxes : 24 Input 5 Bit Muxes := 1 Module dummy_chan_in__1 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module pulse_stretch__parameterized1__16 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module vDFF__parameterized1__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module bulk_controller__4 Detailed RTL Component Info : +---Muxes : 2 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 8 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 Module bulk_channel_mux__4 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 6 Module osum_crc9d32__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module event_hdr_crc9__5 Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized7__4 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 Module ipbus_reg_v__33 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__34 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__66 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__63 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__10 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__67 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__64 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__35 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__68 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__65 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__69 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__66 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__11 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__70 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__67 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__15 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__71 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__68 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__36 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__37 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__45 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__72 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__69 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__73 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__70 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__90 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__87 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_fabric_sel__parameterized6__5 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module ipbus_reg_v__32 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__59 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__56 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__60 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__57 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__61 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__58 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__62 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__59 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__63 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__60 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__64 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__61 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__65 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__62 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module pkt_capture_regs__parameterized1__4 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 2 32 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 9 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module threshold_counter__10 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module threshold_counter__13 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module bulk_proc_regs__4 Detailed RTL Component Info : +---Muxes : 17 Input 5 Bit Muxes := 1 Module bulk_processor Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module pulse_stretch__parameterized1__15 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module vDFF__parameterized1__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module bulk_controller__3 Detailed RTL Component Info : +---Muxes : 2 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 8 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 Module bulk_channel_mux__3 Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 6 Module osum_crc9d32__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module event_hdr_crc9__4 Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized7__3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 Module ipbus_reg_v__44 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__43 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__89 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__86 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__14 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__88 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__85 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__42 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__87 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__84 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__86 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__83 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__13 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__85 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__82 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__12 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__84 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__81 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__41 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__40 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__39 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__83 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__80 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__82 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__79 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__81 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__78 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_fabric_sel__parameterized6__4 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module ipbus_reg_v__38 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__80 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__77 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__79 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__76 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__78 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__75 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__77 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__74 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__76 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__73 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__75 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__72 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__74 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__71 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module pkt_capture_regs__parameterized1__3 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 2 32 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 9 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module threshold_counter__12 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module threshold_counter__11 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module bulk_proc_regs__3 Detailed RTL Component Info : +---Muxes : 17 Input 5 Bit Muxes := 1 Module bulk_processor__xdcDup__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module CRC Detailed RTL Component Info : +---XORs : 2 Input 9 Bit XORs := 137 +---Registers : 9 Bit Registers := 3 +---Muxes : 2 Input 9 Bit Muxes := 134 2 Input 1 Bit Muxes := 1 Module ro_controller Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 32 Bit Registers := 5 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 64 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 Module pulse_stretch__parameterized1__17 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module vDFF__parameterized1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module bulk_controller Detailed RTL Component Info : +---Muxes : 2 Input 16 Bit Muxes := 1 8 Input 16 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 8 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 Module bulk_channel_mux Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 6 Module osum_crc9d32 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module event_hdr_crc9 Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized7 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 Module ipbus_reg_v__47 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__48 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__98 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__95 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__16 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__99 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__96 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__49 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__100 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__97 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__101 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__98 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark__17 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__102 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__99 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module watermark Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 Module syncreg_r__103 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__100 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_reg_v__50 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v__51 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_reg_v Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__104 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__101 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__105 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__102 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module ipbus_fabric_sel__parameterized6 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module ipbus_reg_v__46 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 1 Module syncreg_r__91 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__88 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__92 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__89 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__93 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__90 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__94 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__91 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__95 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__92 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__96 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__93 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module syncreg_r__97 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 1 Bit Registers := 9 Module ipbus_syncreg_v__94 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module pkt_capture_regs__parameterized1 Detailed RTL Component Info : +---Registers : 64 Bit Registers := 2 32 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 9 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module threshold_counter__14 Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module threshold_counter Detailed RTL Component Info : +---Adders : 3 Input 17 Bit Adders := 1 2 Input 16 Bit Adders := 1 +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module bulk_proc_regs Detailed RTL Component Info : +---Muxes : 17 Input 5 Bit Muxes := 1 Module bulk_processor__xdcDup__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module dummy_chan_in Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 5 Bit Muxes := 3 2 Input 1 Bit Muxes := 2 Module osum_crc9d32__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module ttc_info Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 12 Bit Adders := 1 +---Registers : 64 Bit Registers := 1 16 Bit Registers := 1 12 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 6 Input 1 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized0 Detailed RTL Component Info : +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module pulse_stretch__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module packet_processor Detailed RTL Component Info : +---Muxes : 2 Input 24 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 5 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module system_top_reset Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module system_top_reset__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module CRC__parameterized4 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 84 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 70 2 Input 1 Bit Muxes := 1 Module FMchannelTXctrl Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 4 Bit Registers := 3 1 Bit Registers := 11 +---Muxes : 6 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module rst_tmr Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module tx_data_mux Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module fm_axi Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module FM_example_emuram__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 1 Bit Registers := 3 Module FM_example_FIFOctrl Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 1 Module FM_channel__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 2 Module pulse_pdxx_pwxx__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module CRC__parameterized4__4 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 84 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 70 2 Input 1 Bit Muxes := 1 Module FMchannelTXctrl__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 4 Bit Registers := 3 1 Bit Registers := 11 +---Muxes : 6 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module rst_tmr__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module tx_data_mux__4 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module fm_axi__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module FM_example_emuram__xdcDup__2 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 1 Bit Registers := 3 Module FM_example_FIFOctrl__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 1 Module FM_channel__parameterized1__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 2 Module FullModeTransceiver_RX_STARTUP_FSM__4 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 30 +---Muxes : 11 Input 11 Bit Muxes := 1 2 Input 11 Bit Muxes := 6 2 Input 8 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 11 Input 1 Bit Muxes := 14 Module FullModeTransceiver_RX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 30 +---Muxes : 11 Input 11 Bit Muxes := 1 2 Input 11 Bit Muxes := 6 2 Input 8 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 11 Input 1 Bit Muxes := 14 Module FullModeTransceiver_TX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 10 Input 10 Bit Muxes := 1 2 Input 10 Bit Muxes := 4 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 10 Input 1 Bit Muxes := 10 Module FullModeTransceiver__xdcDup__1 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 2 Input 8 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 96 Bit Registers := 1 10 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 1 Bit Muxes := 2 Module pulse_stretch__parameterized7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module Full_Mode_Tx__xdcDup__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module pulse_pdxx_pwxx__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module CRC__parameterized4__3 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 84 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 70 2 Input 1 Bit Muxes := 1 Module FMchannelTXctrl__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 4 Bit Registers := 3 1 Bit Registers := 11 +---Muxes : 6 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module rst_tmr__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module tx_data_mux__3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module fm_axi__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module FM_example_emuram__xdcDup__3 Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 1 Bit Registers := 3 Module FM_example_FIFOctrl__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 1 Module FM_channel Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 2 Module pulse_pdxx_pwxx__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module pulse_pdxx_pwxx__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module CRC__parameterized4__2 Detailed RTL Component Info : +---XORs : 2 Input 20 Bit XORs := 84 +---Registers : 20 Bit Registers := 3 +---Muxes : 2 Input 20 Bit Muxes := 70 2 Input 1 Bit Muxes := 1 Module FMchannelTXctrl__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 4 Bit Registers := 3 1 Bit Registers := 11 +---Muxes : 6 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module rst_tmr__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 4 Module tx_data_mux__2 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module fm_axi__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module FM_example_emuram Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 +---Registers : 10 Bit Registers := 1 1 Bit Registers := 3 Module FM_example_FIFOctrl__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 2 +---Muxes : 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 1 Module FM_channel__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 2 Module FullModeTransceiver_RX_STARTUP_FSM__2 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 30 +---Muxes : 11 Input 11 Bit Muxes := 1 2 Input 11 Bit Muxes := 6 2 Input 8 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 11 Input 1 Bit Muxes := 14 Module FullModeTransceiver_RX_STARTUP_FSM__3 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 30 +---Muxes : 11 Input 11 Bit Muxes := 1 2 Input 11 Bit Muxes := 6 2 Input 8 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 13 11 Input 1 Bit Muxes := 14 Module FullModeTransceiver_TX_STARTUP_FSM__2 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 1 Bit Registers := 21 +---Muxes : 10 Input 10 Bit Muxes := 1 2 Input 10 Bit Muxes := 4 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 10 Input 1 Bit Muxes := 10 Module FullModeTransceiver Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 1 2 Input 8 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 96 Bit Registers := 1 10 Bit Registers := 1 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 1 Bit Muxes := 2 Module pulse_stretch__parameterized7__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module Full_Mode_Tx Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module packet_fifo__xdcDup__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module packet_fifo__xdcDup__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module packet_fifo__xdcDup__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module packet_fifo Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module reset_count Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 5 Bit Registers := 1 1 Bit Registers := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3333] propagating constant 0 across sequential element (backplane/i_0/combined_ttc/\ttc_status_reg_reg[6] ) INFO: [Synth 8-3332] Sequential element (register_chan_seq[0].case_i_equal_to_0.rx_chanbond_reg_0) is unused and will be removed from module sume_RO_Rx_GT_FRAME_CHECK. INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/btn_samp1_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Aurora_channel_status_reg/rsync/m_q_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\data_integrity_status_reg/rsync/m_q_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\bulk_fifo_status_reg/rsync/m_q_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\Tob_fifo_status_reg/rsync/m_q_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/start_seq_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (fex_chan_regs:/\chan_reset/reset_timer/rx_btn_reset_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/CTTC_link_stat_reg/rsync/m_q_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/CTTC_link_stat_reg/rsync/m_q_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.ttc_regs/TTC_fifo_status_reg/rsync/m_q_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (event_builder/fifo_layer/i_0/\gen_reg.registers /\first_last_chan/rsync/m_q_reg[6] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_pwr_dnb_buf) is unused and will be removed from module aurora_64b_rx_12ch. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ref_ck_sel_buf) is unused and will be removed from module aurora_64b_rx_12ch. WARNING: [Synth 8-3332] Sequential element (readout_ctrl/ck_syncb_buf) is unused and will be removed from module aurora_64b_rx_12ch. INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '63' to '55' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/BD/ipshared/72d4/hdl/axi_register_slice_v2_1_vl_rfs.v:1709] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/IPIC_IF_I/BURST_CNT_RDACK/PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[3].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[4].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[5].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[6].READ_COMPLETE_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[14]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[12]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STATE_MACHINE_I/FSM_onehot_crnt_state_reg[9]) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/TPACCCNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[15].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[14].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[13].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[12].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[11].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[10].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[9].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[8].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[7].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[6].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[5].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[4].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[3].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[2].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[1].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/COUNTERS_I/T_WRREC_CNT_I/PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[0].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (U0/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[1].AALIGN_PIPE) is unused and will be removed from module axi4_subsys_axi_emc_0_0. INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SCL_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_iic__1. INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SCL_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_iic__1. INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SDA_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_iic__1. INFO: [Synth 8-3332] Sequential element (X_IIC/FILTER_I/SDA_DEBOUNCE/INPUT_DOUBLE_REGS/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_iic__1. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3332] Sequential element (wrouter_aw_fifo/FSM_onehot_state_reg[2]) is unused and will be removed from module axi_crossbar_v2_1_21_wdata_router__1. INFO: [Synth 8-3332] Sequential element (wrouter_aw_fifo/FSM_onehot_state_reg[2]) is unused and will be removed from module axi_crossbar_v2_1_21_wdata_router. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__1. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__2. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__3. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__4. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__5. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0__6. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0. INFO: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[2]) is unused and will be removed from module axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5545] ROM "fpga_dna_decode/revision" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "fpga_dna_decode/serial_num" won't be mapped to RAM because address size (55) is larger than maximum supported(25) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-3332] Sequential element (trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_support_resets_i/FSM_onehot_idelay_reset_cnt_reg[14]) is unused and will be removed from module ipbus_rod. INFO: [Synth 8-3332] Sequential element (trimac_fifo_block/axi_lite_controller/FSM_onehot_axi_state_reg[13]) is unused and will be removed from module ipbus_rod. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (reset_sync1_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (reset_sync2_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM__4. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg3) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg4) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg5) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_QPLLLOCK/data_sync_reg6) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (reset_sync1_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (reset_sync2_rx) is unused and will be removed from module FullModeTransceiver_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module FullModeTransceiver_TX_STARTUP_FSM. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:07:36 ; elapsed = 00:09:51 . Memory (MB): peak = 3296.293 ; gain = 1008.688 ; free physical = 295 ; free virtual = 19117 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |ipbus/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ |jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64X1D x 8 RAM64M x 40 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------+------------+----------+ |1 |axi4_subsys__GB0 | 1| 24045| |2 |axi4_subsys__GB1 | 1| 8002| |3 |ROD_system__GC0 | 1| 16643| |4 |rod_RO_Tx_exdes__GC0 | 1| 59| |5 |aurora_64b_rx_12ch__GC0 | 1| 4231| |6 |fex_chan_regs | 4| 3867| |7 |channel_fifo__GC0 | 1| 1284| |8 |channel_fifo__parameterized1__GC0 | 1| 1284| |9 |channel_fifo__parameterized3__GC0 | 1| 1284| |10 |channel_fifo__parameterized5__GC0 | 1| 1284| |11 |channel_fifo__parameterized7__GC0 | 1| 1286| |12 |channel_fifo__parameterized9__GC0 | 1| 1286| |13 |channel_fifo__parameterized11__GC0 | 1| 1286| |14 |channel_fifo__parameterized13__GC0 | 1| 1286| |15 |channel_fifo__parameterized15__GC0 | 1| 1286| |16 |channel_fifo__parameterized17__GC0 | 1| 1286| |17 |channel_fifo__parameterized19__GC0 | 1| 1286| |18 |channel_fifo__parameterized21__GC0 | 1| 1286| |19 |input_fifos__GC0 | 1| 4742| |20 |tob_processor | 1| 13749| |21 |packet_processor__GCB1 | 1| 11578| |22 |packet_processor__GCB2 | 1| 1077| |23 |packet_processor__GCB3 | 1| 5708| |24 |top_rod_efex__GC0 | 1| 9819| |25 |fex_chan_regs__1 | 3| 3737| |26 |fex_chan_regs__2 | 5| 3719| +------+-----------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_3' to pin 'aurora_3/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_4' to pin 'aurora_4/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_5' to pin 'aurora_5/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_6' to pin 'aurora_6/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_7' to pin 'aurora_7/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_8' to pin 'aurora_8/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_9' to pin 'aurora_9/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_10' to pin 'aurora_10/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_11' to pin 'aurora_11/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_12' to pin 'aurora_12/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_13' to pin 'aurora_13/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5578] Moved timing constraint from pin 'user_clk_out_14' to pin 'aurora_14/aurora_module_i/clock_module_i/user_clk_buf_i/O' INFO: [Synth 8-5819] Moved 12 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:07:53 ; elapsed = 00:10:15 . Memory (MB): peak = 3296.293 ; gain = 1008.688 ; free physical = 126 ; free virtual = 18993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:08:21 ; elapsed = 00:10:44 . Memory (MB): peak = 3296.293 ; gain = 1008.688 ; free physical = 189 ; free virtual = 18951 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 64 x 32(NO_CHANGE) | W | | 64 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |axi_hwicap_0/U0/\ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(NO_CHANGE) | | R | Port A and B | 1 | 0 | |ipbus/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |ipbus/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ |jtag_axi_0/U0 | jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 256 x 32 | RAM64X1D x 8 RAM64M x 40 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | |axi_quad_spi_0/U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | Implied | 16 x 32 | RAM32M x 6 | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+---------------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------+------------+----------+ |1 |axi4_subsys__GB0 | 1| 24045| |2 |axi4_subsys__GB1 | 1| 8002| |3 |ROD_system__GC0 | 1| 16638| |4 |rod_RO_Tx_exdes__GC0 | 1| 59| |5 |aurora_64b_rx_12ch__GC0 | 1| 4231| |6 |fex_chan_regs | 4| 3867| |7 |channel_fifo__GC0 | 1| 1284| |8 |channel_fifo__parameterized1__GC0 | 1| 1284| |9 |channel_fifo__parameterized3__GC0 | 1| 1284| |10 |channel_fifo__parameterized5__GC0 | 1| 1284| |11 |channel_fifo__parameterized7__GC0 | 1| 1286| |12 |channel_fifo__parameterized9__GC0 | 1| 1286| |13 |channel_fifo__parameterized11__GC0 | 1| 1286| |14 |channel_fifo__parameterized13__GC0 | 1| 1286| |15 |channel_fifo__parameterized15__GC0 | 1| 1286| |16 |channel_fifo__parameterized17__GC0 | 1| 1286| |17 |channel_fifo__parameterized19__GC0 | 1| 1286| |18 |channel_fifo__parameterized21__GC0 | 1| 1286| |19 |input_fifos__GC0 | 1| 4742| |20 |tob_processor | 1| 12066| |21 |packet_processor__GCB1 | 1| 10528| |22 |packet_processor__GCB2 | 1| 1077| |23 |packet_processor__GCB3 | 1| 5706| |24 |top_rod_efex__GC0 | 1| 9819| |25 |fex_chan_regs__1 | 3| 3737| |26 |fex_chan_regs__2 | 5| 3719| +------+-----------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_1/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/i_1/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/i_0/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:09:08 ; elapsed = 00:11:42 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 176 ; free virtual = 18782 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------------------------+------------+----------+ |1 |axi4_subsys__GB0 | 1| 14226| |2 |axi4_subsys__GB1 | 1| 4860| |3 |ROD_system__GC0 | 1| 8690| |4 |rod_RO_Tx_exdes__GC0 | 1| 59| |5 |aurora_64b_rx_12ch__GC0 | 1| 3776| |6 |fex_chan_regs | 1| 2348| |7 |channel_fifo__GC0 | 1| 859| |8 |channel_fifo__parameterized1__GC0 | 1| 859| |9 |channel_fifo__parameterized3__GC0 | 1| 859| |10 |channel_fifo__parameterized5__GC0 | 1| 859| |11 |channel_fifo__parameterized7__GC0 | 1| 858| |12 |channel_fifo__parameterized9__GC0 | 1| 858| |13 |channel_fifo__parameterized11__GC0 | 1| 858| |14 |channel_fifo__parameterized13__GC0 | 1| 858| |15 |channel_fifo__parameterized15__GC0 | 1| 858| |16 |channel_fifo__parameterized17__GC0 | 1| 858| |17 |channel_fifo__parameterized19__GC0 | 1| 858| |18 |channel_fifo__parameterized21__GC0 | 1| 858| |19 |input_fifos__GC0 | 1| 1995| |20 |tob_processor | 1| 5523| |21 |packet_processor__GCB1 | 1| 4762| |22 |packet_processor__GCB2 | 1| 427| |23 |packet_processor__GCB3 | 1| 2921| |24 |top_rod_efex__GC0 | 1| 6487| |25 |fex_chan_regs__1 | 1| 2291| |26 |fex_chan_regs__2 | 1| 2278| |27 |fex_chan_regs__5 | 1| 2348| |28 |fex_chan_regs__6 | 1| 2348| |29 |fex_chan_regs__7 | 1| 2348| |30 |fex_chan_regs__8 | 1| 2291| |31 |fex_chan_regs__9 | 1| 2291| |32 |fex_chan_regs__10 | 1| 2278| |33 |fex_chan_regs__11 | 1| 2278| |34 |fex_chan_regs__12 | 1| 2278| |35 |fex_chan_regs__13 | 1| 2278| +------+-----------------------------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[15] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[14] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[13] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[12] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[11] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[10] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[9] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[8] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[7] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[6] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[5] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[4] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[3] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[2] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[1] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[0] to handle IOB=TRUE attribute INFO: [Synth 8-4163] Replicating register \U0/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg_reg to handle IOB=TRUE attribute INFO: [Synth 8-5777] Ignored max_fanout on net rst_ipb because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_write] because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [0] because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [1] because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [2] because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5777] Ignored max_fanout on net \ipbw_backplane[ipb_addr] [4] because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-5365] Flop reset_reg_reg is being inverted and renamed to reset_reg_reg_inv. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/wr_cmd_fifowren_axi_ff3_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin jtag_axi_engine_u/rd_cmd_fifowren_axi_ff3_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin U0:sl_iport0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt0_cpllrefclklost_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt0_cpllreset_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin readout_ctrl/gt_txfsmresetdone_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/err_count_i_inferred:in0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/gt_reset_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/sysreset_vio_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/gtreset_vio_i_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[63] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[62] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[61] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[60] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[59] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[58] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[57] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[56] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[55] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[54] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[53] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[52] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[51] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[50] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[49] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[48] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[47] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[46] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[45] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[44] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[43] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[42] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[41] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[40] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[39] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[38] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[37] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin aurora_3/rx_d_i_inferred:in0[21] to constant 0 INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:379] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:399] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:385] WARNING: [Synth 8-5410] Found another clock driver clkin1_buf:O [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/hdl/new/ROD_system.vhd:1053] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:09:29 ; elapsed = 00:12:07 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 141 ; free virtual = 18787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:09:30 ; elapsed = 00:12:07 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 141 ; free virtual = 18787 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:36 ; elapsed = 00:12:14 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 131 ; free virtual = 18778 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:09:36 ; elapsed = 00:12:14 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 131 ; free virtual = 18778 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:09:38 ; elapsed = 00:12:16 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 119 ; free virtual = 18766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:09:38 ; elapsed = 00:12:16 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 119 ; free virtual = 18766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +--------------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +--------------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ipbus_rod | trimac_fifo_block/axi_lite_controller/count_shift_reg[20] | 21 | 1 | NO | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/IPADDR/pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/resend/pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[37]__0 | 23 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[13]__0 | 12 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[27]__1 | 6 | 4 | YES | NO | YES | 4 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[11]__1 | 8 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[41] | 12 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[19] | 16 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[35]__0 | 23 | 1 | YES | NO | YES | 0 | 1 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[11]__0 | 10 | 2 | YES | NO | YES | 2 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[9]__2 | 10 | 1 | YES | NO | YES | 1 | 0 | |ipbus_rod | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_data_reg[111] | 10 | 4 | YES | NO | YES | 4 | 0 | |FullModeTransceiver | cpllpd_wait_reg[95] | 96 | 2 | NO | NO | YES | 0 | 6 | |FullModeTransceiver | cpllreset_wait_reg[127] | 128 | 2 | NO | NO | YES | 0 | 8 | +--------------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Dynamic Shift Register Report: +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | INFERRED_GEN.data_reg[255] | 33 | 33 | 0 | 264 | 132 | 66 | 0 | |dsrl__1 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 | |dsrl__2 | memory_reg[31] | 3 | 3 | 0 | 3 | 0 | 0 | 0 | +------------+----------------------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+-----------------------+----------+ | |BlackBox name |Instances | +------+-----------------------+----------+ |1 |rgmii_rx_fifo_2 | 1| |2 |ethernet_mac_rgmii | 1| |3 |vio_ip_address | 1| |4 |MGT_combined_ttc_rx | 1| |5 |vio_ttc | 1| |6 |ila_2 | 1| |7 |aurora_rx_4l_64b | 6| |8 |aurora_rx_1q | 6| |9 |rod_RO_Tx | 1| |10 |vio_0 | 1| |11 |ila_1 | 1| |12 |vio_RO_CTL_test | 1| |13 |clock_cross_fifo | 24| |14 |aurora_fifo_in_ila | 4| |15 |aurora_fifo_out_ila | 8| |16 |data_fifo_vio | 4| |17 |chan_map_ila | 1| |18 |bulk_ila | 3| |19 |bulk_data_fifo | 3| |20 |rod_ROctrl_mux_ila | 1| |21 |ttc_header_fifo | 2| |22 |ila_bulk_ttc | 1| |23 |ila_ttc_in | 1| |24 |ila_ttc_out | 1| |25 |event_builder_fifo | 2| |26 |event_fifo_ila | 1| |27 |ila_ev_builder | 1| |28 |default_reg_ila | 1| |29 |ppmux_ila | 1| |30 |fifo1KB_34bit | 4| |31 |DPram_32b | 4| |32 |vio_fullmode_reset | 4| |33 |fm_status_fifo | 4| |34 |ila_fullmode | 4| |35 |axi_ila_1 | 2| |36 |debug_ila_ed1 | 2| |37 |ila_mgtfsm | 2| |38 |clk_wiz_240 | 2| |39 |axis_dwidth_64_32 | 4| |40 |axis_data_fifo_0 | 4| |41 |ila_fifo | 4| |42 |packet_processor_clock | 1| |43 |vio_top | 1| |44 |axi_ch0 | 2| |45 |pp_ctrl_vio | 1| |46 |backplane_control_ila | 1| +------+-----------------------+----------+ Report Cell Usage: +------+-------------------------------+------+ | |Cell |Count | +------+-------------------------------+------+ |1 |DPram_32b_bbox_119 | 1| |2 |DPram_32b_bbox_119__4 | 1| |3 |DPram_32b_bbox_119__5 | 1| |4 |DPram_32b_bbox_119__6 | 1| |5 |MGT_combined_ttc_rx_bbox_55 | 1| |6 |aurora_fifo_in_ila_bbox_64 | 1| |7 |aurora_fifo_in_ila_bbox_70 | 1| |8 |aurora_fifo_in_ila_bbox_76 | 1| |9 |aurora_fifo_in_ila_bbox_82 | 1| |10 |aurora_fifo_out_ila_bbox_65 | 1| |11 |aurora_fifo_out_ila_bbox_66 | 1| |12 |aurora_fifo_out_ila_bbox_71 | 1| |13 |aurora_fifo_out_ila_bbox_72 | 1| |14 |aurora_fifo_out_ila_bbox_77 | 1| |15 |aurora_fifo_out_ila_bbox_78 | 1| |16 |aurora_fifo_out_ila_bbox_83 | 1| |17 |aurora_fifo_out_ila_bbox_84 | 1| |18 |aurora_rx_1q_bbox_48 | 1| |19 |aurora_rx_1q_bbox_48__10 | 1| |20 |aurora_rx_1q_bbox_48__6 | 1| |21 |aurora_rx_1q_bbox_48__7 | 1| |22 |aurora_rx_1q_bbox_48__8 | 1| |23 |aurora_rx_1q_bbox_48__9 | 1| |24 |aurora_rx_4l_64b_bbox_49 | 1| |25 |aurora_rx_4l_64b_bbox_49__5 | 1| |26 |aurora_rx_4l_64b_bbox_49__6 | 1| |27 |aurora_rx_4l_64b_bbox_49__7 | 1| |28 |aurora_rx_4l_64b_bbox_49__8 | 1| |29 |aurora_rx_4l_64b_bbox_50 | 1| |30 |axi_ch0_bbox_58 | 1| |31 |axi_ch0_bbox_59 | 1| |32 |axi_ila_1_bbox_122 | 1| |33 |axi_ila_1_bbox_122__2 | 1| |34 |axis_data_fifo_0_bbox_129 | 1| |35 |axis_data_fifo_0_bbox_129__4 | 1| |36 |axis_data_fifo_0_bbox_129__5 | 1| |37 |axis_data_fifo_0_bbox_129__6 | 1| |38 |axis_dwidth_64_32_bbox_128 | 1| |39 |axis_dwidth_64_32_bbox_128__4 | 1| |40 |axis_dwidth_64_32_bbox_128__5 | 1| |41 |axis_dwidth_64_32_bbox_128__6 | 1| |42 |backplane_control_ila_bbox_131 | 1| |43 |bulk_data_fifo_bbox_114 | 1| |44 |bulk_data_fifo_bbox_114__3 | 1| |45 |bulk_data_fifo_bbox_114__4 | 1| |46 |bulk_ila_bbox_113 | 1| |47 |bulk_ila_bbox_113__3 | 1| |48 |bulk_ila_bbox_113__4 | 1| |49 |chan_map_ila_bbox_61 | 1| |50 |clk_wiz_240_bbox_116 | 1| |51 |clk_wiz_240_bbox_116__2 | 1| |52 |clock_cross_fifo_bbox_100 | 1| |53 |clock_cross_fifo_bbox_101 | 1| |54 |clock_cross_fifo_bbox_62 | 1| |55 |clock_cross_fifo_bbox_63 | 1| |56 |clock_cross_fifo_bbox_68 | 1| |57 |clock_cross_fifo_bbox_69 | 1| |58 |clock_cross_fifo_bbox_74 | 1| |59 |clock_cross_fifo_bbox_75 | 1| |60 |clock_cross_fifo_bbox_80 | 1| |61 |clock_cross_fifo_bbox_81 | 1| |62 |clock_cross_fifo_bbox_86 | 1| |63 |clock_cross_fifo_bbox_87 | 1| |64 |clock_cross_fifo_bbox_88 | 1| |65 |clock_cross_fifo_bbox_89 | 1| |66 |clock_cross_fifo_bbox_90 | 1| |67 |clock_cross_fifo_bbox_91 | 1| |68 |clock_cross_fifo_bbox_92 | 1| |69 |clock_cross_fifo_bbox_93 | 1| |70 |clock_cross_fifo_bbox_94 | 1| |71 |clock_cross_fifo_bbox_95 | 1| |72 |clock_cross_fifo_bbox_96 | 1| |73 |clock_cross_fifo_bbox_97 | 1| |74 |clock_cross_fifo_bbox_98 | 1| |75 |clock_cross_fifo_bbox_99 | 1| |76 |data_fifo_vio_bbox_67 | 1| |77 |data_fifo_vio_bbox_73 | 1| |78 |data_fifo_vio_bbox_79 | 1| |79 |data_fifo_vio_bbox_85 | 1| |80 |debug_ila_ed1_bbox_126 | 1| |81 |debug_ila_ed1_bbox_126__2 | 1| |82 |default_reg_ila_bbox_106 | 1| |83 |ethernet_mac_rgmii_bbox_46 | 1| |84 |event_builder_fifo_bbox_102 | 1| |85 |event_builder_fifo_bbox_104 | 1| |86 |event_fifo_ila_bbox_103 | 1| |87 |fifo1KB_34bit_bbox_117 | 1| |88 |fifo1KB_34bit_bbox_117__4 | 1| |89 |fifo1KB_34bit_bbox_117__5 | 1| |90 |fifo1KB_34bit_bbox_117__6 | 1| |91 |fm_status_fifo_bbox_120 | 1| |92 |fm_status_fifo_bbox_120__2 | 1| |93 |fm_status_fifo_bbox_124 | 1| |94 |fm_status_fifo_bbox_124__2 | 1| |95 |ila_1_bbox_53 | 1| |96 |ila_2_bbox_57 | 1| |97 |ila_bulk_ttc_bbox_110 | 1| |98 |ila_ev_builder_bbox_105 | 1| |99 |ila_fifo_bbox_130 | 1| |100 |ila_fifo_bbox_130__4 | 1| |101 |ila_fifo_bbox_130__5 | 1| |102 |ila_fifo_bbox_130__6 | 1| |103 |ila_fullmode_bbox_121 | 1| |104 |ila_fullmode_bbox_121__2 | 1| |105 |ila_fullmode_bbox_125 | 1| |106 |ila_fullmode_bbox_125__2 | 1| |107 |ila_mgtfsm_bbox_127 | 1| |108 |ila_mgtfsm_bbox_127__2 | 1| |109 |ila_ttc_in_bbox_111 | 1| |110 |ila_ttc_out_bbox_112 | 1| |111 |packet_processor_clock_bbox_43 | 1| |112 |pp_ctrl_vio_bbox_60 | 1| |113 |ppmux_ila_bbox_107 | 1| |114 |rgmii_rx_fifo_2_bbox_47 | 1| |115 |rod_RO_Tx_bbox_51 | 1| |116 |rod_ROctrl_mux_ila_bbox_115 | 1| |117 |ttc_header_fifo_bbox_108 | 1| |118 |ttc_header_fifo_bbox_109 | 1| |119 |vio_0_bbox_52 | 1| |120 |vio_RO_CTL_test_bbox_54 | 1| |121 |vio_fullmode_reset_bbox_118 | 1| |122 |vio_fullmode_reset_bbox_118__2 | 1| |123 |vio_fullmode_reset_bbox_123 | 1| |124 |vio_fullmode_reset_bbox_123__2 | 1| |125 |vio_ip_address_bbox_45 | 1| |126 |vio_top_bbox_44 | 1| |127 |vio_ttc_bbox_56 | 1| |128 |BUFG | 15| |129 |BUFGCE | 4| |130 |BUFH | 6| |131 |CARRY4 | 2447| |132 |DNA_PORT | 1| |133 |GTHE2_CHANNEL | 4| |134 |GTHE2_COMMON | 18| |135 |IBUFDS_GTE2 | 8| |136 |ICAPE2 | 1| |137 |IDELAYCTRL | 1| |138 |LUT1 | 3654| |139 |LUT2 | 3739| |140 |LUT3 | 4659| |141 |LUT4 | 6175| |142 |LUT5 | 5342| |143 |LUT6 | 11208| |144 |MMCME2_ADV | 1| |145 |MULT_AND | 27| |146 |MUXCY | 27| |147 |MUXCY_L | 18| |148 |MUXF7 | 1440| |149 |MUXF8 | 76| |150 |RAM32M | 12| |151 |RAM64M | 40| |152 |RAM64X1D | 8| |153 |RAMB18E1 | 1| |154 |RAMB18E1_1 | 2| |155 |RAMB36E1 | 2| |156 |RAMB36E1_1 | 1| |157 |RAMB36E1_2 | 16| |158 |SRL16 | 2| |159 |SRL16E | 51| |160 |SRLC32E | 524| |161 |STARTUPE2 | 1| |162 |XADC | 1| |163 |XORCY | 57| |164 |FD | 248| |165 |FDCE | 4135| |166 |FDPE | 100| |167 |FDR | 443| |168 |FDRE | 38882| |169 |FDSE | 1656| |170 |IBUF | 138| |171 |IBUFDS | 1| |172 |IBUFG | 1| |173 |IOBUF | 24| |174 |OBUF | 50| |175 |OBUFT | 1| +------+-------------------------------+------+ Report Instance Areas: +------+-------------------------------------------------------------------------------------+---------------------------------------------------------------------+------+ | |Instance |Module |Cells | +------+-------------------------------------------------------------------------------------+---------------------------------------------------------------------+------+ |1 |top | | 92845| |2 | ipbus_blk |ROD_system | 27721| |3 | address_sel |addr_sel_rom | 17| |4 | common_regs |common_IdVersion_regs | 475| |5 | Xmlversion |ipbus_syncreg_v__parameterized0 | 41| |6 | rsync |syncreg_r_1237 | 39| |7 | buildversion |ipbus_syncreg_v__parameterized0_1229 | 31| |8 | rsync |syncreg_r_1236 | 28| |9 | dna_regs |ipbus_syncreg_v__parameterized0_1230 | 62| |10 | rsync |syncreg_r_1235 | 60| |11 | fpga_dna |dna_reader | 259| |12 | module_id_reg |ipbus_syncreg_v_1231 | 40| |13 | rsync |syncreg_r_1234 | 38| |14 | serial_num_reg |ipbus_syncreg_v_1232 | 39| |15 | rsync |syncreg_r_1233 | 37| |16 | ipbus |ipbus_rod | 8042| |17 | clocks |clocks_7s_extphy | 101| |18 | clkdiv |ipbus_clock_div | 43| |19 | stretch |led_stretcher | 53| |20 | clkdiv |ipbus_clock_div_1228 | 30| |21 | example_clocks |ethernet_mac_rgmii_example_design_clocks | 20| |22 | lock_sync |ethernet_mac_rgmii_sync_block | 5| |23 | mmcm_reset_gen |ethernet_mac_rgmii_reset_sync | 5| |24 | clock_generator |ethernet_mac_rgmii_clk_wiz | 6| |25 | example_resets |ethernet_mac_rgmii_example_design_resets | 47| |26 | dcm_sync |ethernet_mac_rgmii_sync_block__2 | 5| |27 | glbl_reset_gen |ethernet_mac_rgmii_reset_sync__4 | 5| |28 | axi_lite_reset_gen |ethernet_mac_rgmii_reset_sync__5 | 5| |29 | gtx_reset_gen |ethernet_mac_rgmii_reset_sync__6 | 5| |30 | chk_reset_gen |ethernet_mac_rgmii_reset_sync__7 | 5| |31 | ipbus |ipbus_ctrl | 7302| |32 | trans |transactor | 805| |33 | cfg |transactor_cfg | 1| |34 | iface |transactor_if | 371| |35 | sm |transactor_sm | 419| |36 | udp_if |UDP_if | 6494| |37 | ipbus_rx_ram |udp_DualPortRAM_rx | 8| |38 | IPADDR |udp_ipaddr_block | 581| |39 | clock_crossing_if |udp_clock_crossing_if | 85| |40 | internal_ram |udp_DualPortRAM | 1| |41 | internal_ram_selector |udp_buffer_selector | 28| |42 | internal_ram_shim |udp_rxram_shim | 55| |43 | ipbus_tx_ram |udp_DualPortRAM_tx | 18| |44 | payload |udp_build_payload | 537| |45 | \primary_mode.ARP |udp_build_arp | 355| |46 | \primary_mode.RARP_block |udp_rarp_block | 453| |47 | \primary_mode.ping |udp_build_ping | 302| |48 | resend |udp_build_resend | 131| |49 | rx_byte_sum |udp_byte_sum | 106| |50 | rx_packet_parser |udp_packet_parser | 906| |51 | rx_ram_mux |udp_rxram_mux | 49| |52 | rx_ram_selector |udp_buffer_selector__parameterized0 | 165| |53 | rx_reset_block |udp_do_rx_reset | 26| |54 | rx_transactor |udp_rxtransactor_if | 7| |55 | status |udp_build_status | 340| |56 | status_buffer |udp_status_buffer | 738| |57 | tx_byte_sum |udp_byte_sum_1227 | 94| |58 | tx_main |udp_tx_mux | 810| |59 | tx_ram_selector |udp_buffer_selector__parameterized1 | 253| |60 | tx_transactor |udp_txtransactor_if | 433| |61 | slaves |ipbus_example | 4| |62 | slave3 |ipbus_axi4_bridge | 4| |63 | trimac_fifo_block |eth_7s_rgmii | 568| |64 | rx_mac_reset_gen |ethernet_mac_rgmii_reset_sync__2 | 5| |65 | tx_mac_reset_gen |ethernet_mac_rgmii_reset_sync__3 | 5| |66 | axi_lite_controller |ethernet_mac_rgmii_axi_lite_sm | 322| |67 | update_speed_sync_inst |ethernet_mac_rgmii_sync_block__1 | 5| |68 | trimac_sup_block |ethernet_mac_rgmii_support | 160| |69 | tri_mode_ethernet_mac_support_resets_i |ethernet_mac_rgmii_support_resets | 23| |70 | idelayctrl_reset_gen |ethernet_mac_rgmii_reset_sync__1 | 5| |71 | axi4_subsys |axi4_subsys_wrapper | 19107| |72 | axi4_subsys_i |axi4_subsys | 19097| |73 | axi_emc_0 |axi4_subsys_axi_emc_0_0 | 1477| |74 | U0 |axi_emc | 1477| |75 | AXI_EMC_NATIVE_INTERFACE_I |axi_emc_native_interface | 903| |76 | AXI_EMC_ADDRESS_DECODE_INSTANCE_I |axi_emc_address_decode | 52| |77 | AXI_EMC_ADDR_GEN_INSTANCE_I |axi_emc_addr_gen | 100| |78 | RDATA_FIFO_I |srl_fifo_rbu_f | 536| |79 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f | 35| |80 | DYNSHREG_F_I |dynshreg_f | 495| |81 | EMC_CTRL_I |EMC | 541| |82 | ADDR_COUNTER_MUX_I |addr_counter_mux | 40| |83 | COUNTERS_I |counters | 143| |84 | THZCNT_I |ld_arith_reg__parameterized1 | 28| |85 | TLZCNT_I |ld_arith_reg__parameterized1_1224 | 31| |86 | TRDCNT_I |ld_arith_reg__parameterized0 | 27| |87 | TWPHCNT_I |ld_arith_reg__parameterized1_1225 | 28| |88 | TWRCNT_I |ld_arith_reg__parameterized0_1226 | 29| |89 | IO_REGISTERS_I |io_registers | 110| |90 | IPIC_IF_I |emc_common_v3_0_5_ipic_if | 72| |91 | BURST_CNT |ld_arith_reg | 33| |92 | MEM_STATE_MACHINE_I |mem_state_machine | 109| |93 | MEM_STEER_I |mem_steer | 67| |94 | xadc_wiz_0 |axi4_subsys_xadc_wiz_0_0 | 441| |95 | U0 |axi4_subsys_xadc_wiz_0_0_axi_xadc | 441| |96 | AXI_LITE_IPIF_I |axi4_subsys_xadc_wiz_0_0_axi_lite_ipif | 189| |97 | I_SLAVE_ATTACHMENT |axi4_subsys_xadc_wiz_0_0_slave_attachment | 189| |98 | I_DECODER |axi4_subsys_xadc_wiz_0_0_address_decoder | 133| |99 | AXI_XADC_CORE_I |axi4_subsys_xadc_wiz_0_0_xadc_core_drp | 77| |100 | \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I |axi4_subsys_xadc_wiz_0_0_interrupt_control | 102| |101 | SOFT_RESET_I |axi4_subsys_xadc_wiz_0_0_soft_reset | 39| |102 | jtag_axi_0 |axi4_subsys_jtag_axi_0_0 | 2435| |103 | U0 |jtag_axi_v1_2_10_jtag_axi | 2435| |104 | axi_bridge_u |jtag_axi_v1_2_10_axi_bridge | 261| |105 | read_axi_full_u |jtag_axi_v1_2_10_read_axi | 128| |106 | write_axi_full_u |jtag_axi_v1_2_10_write_axi | 133| |107 | jtag_axi_engine_u |jtag_axi_v1_2_10_jtag_axi_engine | 2174| |108 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 247| |109 | cmd_decode_rd_channel |jtag_axi_v1_2_10_cmd_decode | 9| |110 | cmd_decode_wr_channel |jtag_axi_v1_2_10_cmd_decode_1200 | 9| |111 | rd_cmd_fifo_i |fifo_generator_v13_2_5__parameterized1 | 188| |112 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized1 | 188| |113 | \gconvfifo.rf |fifo_generator_top__parameterized1 | 188| |114 | \grf.rf |fifo_generator_ramfifo__parameterized1 | 188| |115 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__parameterized0 | 46| |116 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized8__4 | 22| |117 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized8__5 | 22| |118 | \gntv_or_sync_fifo.gl0.rd |rd_logic__parameterized0_1210 | 35| |119 | \gr1.gr1_int.rfwft |rd_fwft_1221 | 19| |120 | \gras.rsts |rd_status_flags_as__parameterized0_1222 | 2| |121 | rpntr |rd_bin_cntr__parameterized0_1223 | 14| |122 | \gntv_or_sync_fifo.gl0.wr |wr_logic__parameterized0_1211 | 23| |123 | \gwas.wsts |wr_status_flags_as__parameterized0_1219 | 3| |124 | wpntr |wr_bin_cntr__parameterized0_1220 | 20| |125 | \gntv_or_sync_fifo.mem |memory__parameterized1_1212 | 84| |126 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4__parameterized1_1213 | 19| |127 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth__parameterized0_1214 | 19| |128 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top__parameterized0_1215 | 19| |129 | \valid.cstr |blk_mem_gen_generic_cstr__parameterized0_1216 | 19| |130 | \ramloop[0].ram.r |blk_mem_gen_prim_width__parameterized0_1217 | 19| |131 | \prim_noinit.ram |blk_mem_gen_prim_wrapper__parameterized0_1218 | 1| |132 | rx_fifo_i |fifo_generator_v13_2_5__parameterized0 | 242| |133 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized0 | 242| |134 | \gconvfifo.rf |fifo_generator_top__parameterized0 | 242| |135 | \grf.rf |fifo_generator_ramfifo__parameterized0 | 242| |136 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 96| |137 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized6__4 | 46| |138 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized6__5 | 46| |139 | \gntv_or_sync_fifo.gl0.rd |rd_logic_1203 | 54| |140 | \gr1.gr1_int.rfwft |rd_fwft_1207 | 17| |141 | \gras.rsts |rd_status_flags_as_1208 | 2| |142 | rpntr |rd_bin_cntr_1209 | 35| |143 | \gntv_or_sync_fifo.gl0.wr |wr_logic_1204 | 40| |144 | \gwas.wsts |wr_status_flags_as_1205 | 2| |145 | wpntr |wr_bin_cntr_1206 | 38| |146 | \gntv_or_sync_fifo.mem |memory__parameterized0 | 52| |147 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4 | 20| |148 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 20| |149 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 20| |150 | \valid.cstr |blk_mem_gen_generic_cstr | 20| |151 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 20| |152 | \prim_noinit.ram |blk_mem_gen_prim_wrapper | 2| |153 | tx_fifo_i |fifo_generator_v13_2_5 | 335| |154 | inst_fifo_gen |fifo_generator_v13_2_5_synth | 335| |155 | \gconvfifo.rf |fifo_generator_top | 335| |156 | \grf.rf |fifo_generator_ramfifo | 335| |157 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__xdcDup__1 | 110| |158 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized6__6 | 46| |159 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized6 | 46| |160 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 42| |161 | \gr1.gr1_int.rfwft |rd_fwft_1202 | 15| |162 | \gras.rsts |rd_status_flags_as | 2| |163 | rpntr |rd_bin_cntr | 25| |164 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 39| |165 | \gwas.wsts |wr_status_flags_as | 2| |166 | wpntr |wr_bin_cntr | 37| |167 | \gntv_or_sync_fifo.mem |memory | 144| |168 | \gdm.dm_gen.dm |dmem | 112| |169 | u_xsdb_fifo_interface |jtag_axi_v1_2_10_xsdb_fifo_interface | 614| |170 | rxfifo2xsdb_i |jtag_axi_v1_2_10_rxfifo2xsdb | 132| |171 | xsdb2read_cmdfifo |jtag_axi_v1_2_10_xsdb2txfifo__parameterized0 | 143| |172 | xsdb2txfifo_i |jtag_axi_v1_2_10_xsdb2txfifo | 76| |173 | xsdb2write_cmdfifo |jtag_axi_v1_2_10_xsdb2txfifo__parameterized0_1201 | 143| |174 | wr_cmd_fifo_i |fifo_generator_v13_2_5__parameterized1__xdcDup__1 | 179| |175 | inst_fifo_gen |fifo_generator_v13_2_5_synth__parameterized1__xdcDup__1 | 179| |176 | \gconvfifo.rf |fifo_generator_top__parameterized1__xdcDup__1 | 179| |177 | \grf.rf |fifo_generator_ramfifo__parameterized1__xdcDup__1 | 179| |178 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs__parameterized0__xdcDup__1 | 46| |179 | wr_pntr_cdc_inst |xpm_cdc_gray__parameterized8__6 | 22| |180 | rd_pntr_cdc_inst |xpm_cdc_gray__parameterized8 | 22| |181 | \gntv_or_sync_fifo.gl0.rd |rd_logic__parameterized0 | 37| |182 | \gr1.gr1_int.rfwft |rd_fwft | 21| |183 | \gras.rsts |rd_status_flags_as__parameterized0 | 2| |184 | rpntr |rd_bin_cntr__parameterized0 | 14| |185 | \gntv_or_sync_fifo.gl0.wr |wr_logic__parameterized0 | 23| |186 | \gwas.wsts |wr_status_flags_as__parameterized0 | 3| |187 | wpntr |wr_bin_cntr__parameterized0 | 20| |188 | \gntv_or_sync_fifo.mem |memory__parameterized1 | 73| |189 | \gbm.gbmg.gbmga.ngecc.bmg |blk_mem_gen_v8_4_4__parameterized1 | 19| |190 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth__parameterized0 | 19| |191 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top__parameterized0 | 19| |192 | \valid.cstr |blk_mem_gen_generic_cstr__parameterized0 | 19| |193 | \ramloop[0].ram.r |blk_mem_gen_prim_width__parameterized0 | 19| |194 | \prim_noinit.ram |blk_mem_gen_prim_wrapper__parameterized0 | 1| |195 | axi_iic_0 |axi4_subsys_axi_iic_0_0 | 882| |196 | U0 |axi_iic__1 | 882| |197 | X_IIC |iic_1177 | 882| |198 | DYN_MASTER_I |dynamic_master_1178 | 33| |199 | FILTER_I |filter_1179 | 11| |200 | SCL_DEBOUNCE |debounce_1196 | 6| |201 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_1199 | 6| |202 | SDA_DEBOUNCE |debounce_1197 | 5| |203 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_1198 | 5| |204 | IIC_CONTROL_I |iic_control_1180 | 285| |205 | BITCNT |upcnt_n__parameterized0_1191 | 15| |206 | CLKCNT |upcnt_n_1192 | 34| |207 | I2CDATA_REG |shift8_1193 | 18| |208 | I2CHEADER_REG |shift8_1194 | 23| |209 | SETUP_CNT |upcnt_n_1195 | 25| |210 | READ_FIFO_I |SRL_FIFO__parameterized0_1181 | 32| |211 | REG_INTERFACE_I |reg_interface_1182 | 200| |212 | WRITE_FIFO_CTRL_I |SRL_FIFO__parameterized1_1183 | 21| |213 | WRITE_FIFO_I |SRL_FIFO_1184 | 33| |214 | X_AXI_IPIF_SSP1 |axi_ipif_ssp1_1185 | 263| |215 | AXI_LITE_IPIF_I |axi_lite_ipif__parameterized1_1186 | 215| |216 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized1_1189 | 215| |217 | I_DECODER |address_decoder__parameterized1_1190 | 101| |218 | X_INTERRUPT_CONTROL |interrupt_control__parameterized0_1187 | 31| |219 | X_SOFT_RESET |axi_iic_v2_0_23_soft_reset_1188 | 13| |220 | axi_interconnect_0 |axi4_subsys_axi_interconnect_0_0 | 9002| |221 | xbar |axi4_subsys_xbar_0 | 2630| |222 | inst |axi_crossbar_v2_1_21_axi_crossbar | 2630| |223 | \gen_samd.crossbar_samd |axi_crossbar_v2_1_21_crossbar | 2630| |224 | addr_arbiter_ar |axi_crossbar_v2_1_21_addr_arbiter | 235| |225 | \gen_arbiter.mux_mesg |generic_baseblocks_v2_1_0_mux_enc__parameterized2_1176 | 58| |226 | addr_arbiter_aw |axi_crossbar_v2_1_21_addr_arbiter_1120 | 279| |227 | \gen_arbiter.mux_mesg |generic_baseblocks_v2_1_0_mux_enc__parameterized2 | 58| |228 | \gen_decerr_slave.decerr_slave_inst |axi_crossbar_v2_1_21_decerr_slave | 49| |229 | \gen_master_slots[0].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux | 55| |230 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1174 | 54| |231 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1175 | 1| |232 | \gen_master_slots[0].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1 | 146| |233 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1172 | 20| |234 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1173 | 126| |235 | \gen_master_slots[1].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1121 | 55| |236 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1170 | 54| |237 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1171 | 1| |238 | \gen_master_slots[1].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1122 | 141| |239 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1168 | 18| |240 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1169 | 123| |241 | \gen_master_slots[2].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1123 | 55| |242 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1166 | 54| |243 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1167 | 1| |244 | \gen_master_slots[2].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1124 | 147| |245 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1164 | 20| |246 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1165 | 127| |247 | \gen_master_slots[3].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1125 | 55| |248 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1162 | 54| |249 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1163 | 1| |250 | \gen_master_slots[3].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1126 | 144| |251 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1160 | 19| |252 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1161 | 125| |253 | \gen_master_slots[4].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1127 | 52| |254 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1158 | 51| |255 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1159 | 1| |256 | \gen_master_slots[4].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1128 | 146| |257 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1156 | 20| |258 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1157 | 126| |259 | \gen_master_slots[5].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1129 | 52| |260 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0_1154 | 51| |261 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1155 | 1| |262 | \gen_master_slots[5].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1130 | 145| |263 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1152 | 20| |264 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1153 | 125| |265 | \gen_master_slots[6].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux_1131 | 52| |266 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized0 | 51| |267 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1151 | 1| |268 | \gen_master_slots[6].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1132 | 148| |269 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9_1149 | 20| |270 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10_1150 | 128| |271 | \gen_master_slots[7].gen_mi_write.wdata_mux_w |axi_crossbar_v2_1_21_wdata_mux__parameterized0 | 16| |272 | \gen_wmux.wmux_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo__parameterized1 | 15| |273 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1148 | 1| |274 | \gen_master_slots[7].reg_slice_mi |axi_register_slice_v2_1_20_axi_register_slice__parameterized1_1133 | 64| |275 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized9 | 17| |276 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized10 | 47| |277 | \gen_slave_slots[0].gen_si_read.si_transactor_ar |axi_crossbar_v2_1_21_si_transactor | 129| |278 | \gen_single_thread.mux_resp_single_thread |generic_baseblocks_v2_1_0_mux_enc_1147 | 105| |279 | \gen_slave_slots[0].gen_si_write.si_transactor_aw |axi_crossbar_v2_1_21_si_transactor__parameterized0 | 28| |280 | \gen_single_thread.mux_resp_single_thread |generic_baseblocks_v2_1_0_mux_enc__parameterized0_1146 | 7| |281 | \gen_slave_slots[0].gen_si_write.splitter_aw_si |axi_crossbar_v2_1_21_splitter | 7| |282 | \gen_slave_slots[0].gen_si_write.wdata_router_w |axi_crossbar_v2_1_21_wdata_router | 66| |283 | wrouter_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo_1141 | 66| |284 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1142 | 6| |285 | \gen_srls[0].gen_rep[1].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1143 | 5| |286 | \gen_srls[0].gen_rep[2].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1144 | 2| |287 | \gen_srls[0].gen_rep[3].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1145 | 8| |288 | \gen_slave_slots[1].gen_si_read.si_transactor_ar |axi_crossbar_v2_1_21_si_transactor__parameterized1 | 185| |289 | \gen_multi_thread.arbiter_resp_inst |axi_crossbar_v2_1_21_arbiter_resp_1140 | 119| |290 | \gen_multi_thread.mux_resp_multi_thread |generic_baseblocks_v2_1_0_mux_enc | 40| |291 | \gen_slave_slots[1].gen_si_write.si_transactor_aw |axi_crossbar_v2_1_21_si_transactor__parameterized2 | 89| |292 | \gen_multi_thread.arbiter_resp_inst |axi_crossbar_v2_1_21_arbiter_resp | 55| |293 | \gen_multi_thread.mux_resp_multi_thread |generic_baseblocks_v2_1_0_mux_enc__parameterized0 | 8| |294 | \gen_slave_slots[1].gen_si_write.splitter_aw_si |axi_crossbar_v2_1_21_splitter_1134 | 7| |295 | \gen_slave_slots[1].gen_si_write.wdata_router_w |axi_crossbar_v2_1_21_wdata_router_1135 | 49| |296 | wrouter_aw_fifo |axi_data_fifo_v2_1_19_axic_reg_srl_fifo | 49| |297 | \gen_srls[0].gen_rep[0].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl | 2| |298 | \gen_srls[0].gen_rep[1].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1137 | 2| |299 | \gen_srls[0].gen_rep[2].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1138 | 2| |300 | \gen_srls[0].gen_rep[3].srl_nx1 |axi_data_fifo_v2_1_19_ndeep_srl_1139 | 8| |301 | splitter_aw_mi |axi_crossbar_v2_1_21_splitter_1136 | 3| |302 | m01_couplers |m01_couplers_imp_FF3AZQ | 1062| |303 | auto_pc |axi4_subsys_auto_pc_0 | 1062| |304 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_1097 | 1062| |305 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_1098 | 1062| |306 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_1099 | 177| |307 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_1116 | 19| |308 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1117 | 156| |309 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1118 | 69| |310 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1119 | 81| |311 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_1100 | 72| |312 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_1114 | 53| |313 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_1115 | 15| |314 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_1101 | 519| |315 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_1110 | 193| |316 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1111 | 187| |317 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_1112 | 20| |318 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_1113 | 119| |319 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_1102 | 190| |320 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_1106 | 28| |321 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1107 | 152| |322 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1108 | 68| |323 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1109 | 80| |324 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_1103 | 103| |325 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_1104 | 61| |326 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_1105 | 18| |327 | m02_couplers |m02_couplers_imp_L8N2BP | 1062| |328 | auto_pc |axi4_subsys_auto_pc_1 | 1062| |329 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_1074 | 1062| |330 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_1075 | 1062| |331 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_1076 | 177| |332 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_1093 | 19| |333 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1094 | 156| |334 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1095 | 69| |335 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1096 | 81| |336 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_1077 | 72| |337 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_1091 | 53| |338 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_1092 | 15| |339 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_1078 | 519| |340 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_1087 | 193| |341 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1088 | 187| |342 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_1089 | 20| |343 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_1090 | 119| |344 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_1079 | 190| |345 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_1083 | 28| |346 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1084 | 152| |347 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1085 | 68| |348 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1086 | 80| |349 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_1080 | 103| |350 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_1081 | 61| |351 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_1082 | 18| |352 | m03_couplers |m03_couplers_imp_1MMZOD7 | 1062| |353 | auto_pc |axi4_subsys_auto_pc_2 | 1062| |354 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_1051 | 1062| |355 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_1052 | 1062| |356 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_1053 | 177| |357 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_1070 | 19| |358 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1071 | 156| |359 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1072 | 69| |360 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1073 | 81| |361 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_1054 | 72| |362 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_1068 | 53| |363 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_1069 | 15| |364 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_1055 | 519| |365 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_1064 | 193| |366 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1065 | 187| |367 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_1066 | 20| |368 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_1067 | 119| |369 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_1056 | 190| |370 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_1060 | 28| |371 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1061 | 152| |372 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1062 | 68| |373 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1063 | 80| |374 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_1057 | 103| |375 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_1058 | 61| |376 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_1059 | 18| |377 | m04_couplers |m04_couplers_imp_1FSUCEB | 1062| |378 | auto_pc |axi4_subsys_auto_pc_3 | 1062| |379 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_1028 | 1062| |380 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_1029 | 1062| |381 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_1030 | 177| |382 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_1047 | 19| |383 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1048 | 156| |384 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1049 | 69| |385 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1050 | 81| |386 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_1031 | 72| |387 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_1045 | 53| |388 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_1046 | 15| |389 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_1032 | 519| |390 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_1041 | 193| |391 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1042 | 187| |392 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_1043 | 20| |393 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_1044 | 119| |394 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_1033 | 190| |395 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_1037 | 28| |396 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1038 | 152| |397 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1039 | 68| |398 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1040 | 80| |399 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_1034 | 103| |400 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_1035 | 61| |401 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_1036 | 18| |402 | m05_couplers |m05_couplers_imp_ADRT99 | 1062| |403 | auto_pc |axi4_subsys_auto_pc_4 | 1062| |404 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter_1005 | 1062| |405 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s_1006 | 1062| |406 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel_1007 | 177| |407 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm_1024 | 19| |408 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1025 | 156| |409 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1026 | 69| |410 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1027 | 81| |411 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel_1008 | 72| |412 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1_1022 | 53| |413 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2_1023 | 15| |414 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice_1009 | 519| |415 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice_1018 | 193| |416 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1019 | 187| |417 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1_1020 | 20| |418 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2_1021 | 119| |419 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel_1010 | 190| |420 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm_1014 | 28| |421 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1015 | 152| |422 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1016 | 68| |423 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1017 | 80| |424 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel_1011 | 103| |425 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo_1012 | 61| |426 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0_1013 | 18| |427 | m06_couplers |m06_couplers_imp_Q7JFB2 | 1062| |428 | auto_pc |axi4_subsys_auto_pc_5 | 1062| |429 | inst |axi_protocol_converter_v2_1_20_axi_protocol_converter | 1062| |430 | \gen_axilite.gen_b2s_conv.axilite_b2s |axi_protocol_converter_v2_1_20_b2s | 1062| |431 | \RD.ar_channel_0 |axi_protocol_converter_v2_1_20_b2s_ar_channel | 177| |432 | ar_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_rd_cmd_fsm | 19| |433 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator_1002 | 156| |434 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd_1003 | 69| |435 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd_1004 | 81| |436 | \RD.r_channel_0 |axi_protocol_converter_v2_1_20_b2s_r_channel | 72| |437 | rd_data_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized1 | 53| |438 | transaction_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized2 | 15| |439 | SI_REG |axi_register_slice_v2_1_20_axi_register_slice | 519| |440 | \ar.ar_pipe |axi_register_slice_v2_1_20_axic_register_slice | 193| |441 | \aw.aw_pipe |axi_register_slice_v2_1_20_axic_register_slice_1001 | 187| |442 | \b.b_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized1 | 20| |443 | \r.r_pipe |axi_register_slice_v2_1_20_axic_register_slice__parameterized2 | 119| |444 | \WR.aw_channel_0 |axi_protocol_converter_v2_1_20_b2s_aw_channel | 190| |445 | aw_cmd_fsm_0 |axi_protocol_converter_v2_1_20_b2s_wr_cmd_fsm | 28| |446 | cmd_translator_0 |axi_protocol_converter_v2_1_20_b2s_cmd_translator | 152| |447 | incr_cmd_0 |axi_protocol_converter_v2_1_20_b2s_incr_cmd | 68| |448 | wrap_cmd_0 |axi_protocol_converter_v2_1_20_b2s_wrap_cmd | 80| |449 | \WR.b_channel_0 |axi_protocol_converter_v2_1_20_b2s_b_channel | 103| |450 | bid_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo | 61| |451 | bresp_fifo_0 |axi_protocol_converter_v2_1_20_b2s_simple_fifo__parameterized0 | 18| |452 | s00_couplers |s00_couplers_imp_IY3DNS | 0| |453 | auto_pc |axi4_subsys_auto_pc_6 | 0| |454 | axi_iic_1 |axi4_subsys_axi_iic_1_0 | 882| |455 | U0 |axi_iic | 882| |456 | X_IIC |iic | 882| |457 | DYN_MASTER_I |dynamic_master | 33| |458 | FILTER_I |filter | 11| |459 | SCL_DEBOUNCE |debounce | 6| |460 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_1000 | 6| |461 | SDA_DEBOUNCE |debounce_998 | 5| |462 | INPUT_DOUBLE_REGS |cdc_sync__parameterized3_999 | 5| |463 | IIC_CONTROL_I |iic_control | 285| |464 | BITCNT |upcnt_n__parameterized0 | 15| |465 | CLKCNT |upcnt_n | 34| |466 | I2CDATA_REG |shift8 | 18| |467 | I2CHEADER_REG |shift8_996 | 23| |468 | SETUP_CNT |upcnt_n_997 | 25| |469 | READ_FIFO_I |SRL_FIFO__parameterized0 | 32| |470 | REG_INTERFACE_I |reg_interface | 200| |471 | WRITE_FIFO_CTRL_I |SRL_FIFO__parameterized1 | 21| |472 | WRITE_FIFO_I |SRL_FIFO | 33| |473 | X_AXI_IPIF_SSP1 |axi_ipif_ssp1 | 263| |474 | AXI_LITE_IPIF_I |axi_lite_ipif__parameterized1 | 215| |475 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized1 | 215| |476 | I_DECODER |address_decoder__parameterized1 | 101| |477 | X_INTERRUPT_CONTROL |interrupt_control__parameterized0 | 31| |478 | X_SOFT_RESET |axi_iic_v2_0_23_soft_reset | 13| |479 | axi_quad_spi_0 |axi4_subsys_axi_quad_spi_0_0 | 1614| |480 | U0 |axi_quad_spi | 1614| |481 | \NO_DUAL_QUAD_MODE.QSPI_NORMAL |axi_quad_spi_top | 1614| |482 | \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I |axi_lite_ipif__parameterized2 | 213| |483 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized2 | 213| |484 | I_DECODER |address_decoder__parameterized2 | 124| |485 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized4 | 1| |486 | \MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized14 | 1| |487 | \MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized15 | 1| |488 | \MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized16 | 1| |489 | \MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized17 | 1| |490 | \MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized18 | 1| |491 | \MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized5 | 1| |492 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized6 | 1| |493 | \MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized7 | 1| |494 | \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized8 | 1| |495 | \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized9 | 1| |496 | \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized10 | 1| |497 | \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized11 | 1| |498 | \MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized12 | 1| |499 | \MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized13 | 1| |500 | \MEM_DECODE_GEN[1].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized21 | 1| |501 | \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized23 | 1| |502 | \MEM_DECODE_GEN[1].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized24 | 1| |503 | \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized27 | 1| |504 | \MEM_DECODE_GEN[2].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized21_992 | 1| |505 | \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized23_993 | 1| |506 | \MEM_DECODE_GEN[2].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized24_994 | 1| |507 | \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized27_995 | 1| |508 | \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I |qspi_core_interface | 1398| |509 | \FIFO_EXISTS.RX_FIFO_II |xpm_fifo_async__parameterized3 | 364| |510 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized1 | 364| |511 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized1 | 70| |512 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized2__3 | 18| |513 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized3 | 33| |514 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized2 | 18| |515 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized4 | 23| |516 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized7_980 | 8| |517 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized2_981 | 12| |518 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_982 | 9| |519 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized2_983 | 7| |520 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_984 | 7| |521 | \gen_fwft.rdpp1_inst |xpm_counter_updn__parameterized9_985 | 10| |522 | rdp_inst |xpm_counter_updn__parameterized10_986 | 25| |523 | rdpp1_inst |xpm_counter_updn__parameterized11_987 | 8| |524 | rst_d1_inst |xpm_fifo_reg_bit_988 | 2| |525 | wrp_inst |xpm_counter_updn__parameterized10_989 | 12| |526 | wrpp1_inst |xpm_counter_updn__parameterized11_990 | 8| |527 | wrpp2_inst |xpm_counter_updn__parameterized8_991 | 8| |528 | xpm_fifo_rst_inst |xpm_fifo_rst__parameterized0__xdcDup__1 | 46| |529 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__parameterized0__6 | 2| |530 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__parameterized0 | 2| |531 | CONTROL_REG_I |qspi_cntrl_reg | 15| |532 | \FIFO_EXISTS.CLK_CROSS_I |cross_clk_sync_fifo_1 | 83| |533 | \FIFO_EXISTS.FIFO_IF_MODULE_I |qspi_fifo_ifmodule | 9| |534 | \FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC |cdc_sync__parameterized6 | 3| |535 | \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC |cdc_sync__parameterized6_974 | 3| |536 | \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I |axi_quad_spi_v3_2_19_counter_f | 9| |537 | \FIFO_EXISTS.TX_FIFO_II |async_fifo_fg__parameterized1 | 375| |538 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async__parameterized5 | 366| |539 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized2 | 366| |540 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized1__1 | 70| |541 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized2__1 | 18| |542 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized3__1 | 33| |543 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized2__2 | 18| |544 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized4__1 | 23| |545 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized7 | 8| |546 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized2 | 13| |547 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized3 | 9| |548 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized2_975 | 7| |549 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized3_976 | 7| |550 | \gen_fwft.rdpp1_inst |xpm_counter_updn__parameterized9 | 10| |551 | rdp_inst |xpm_counter_updn__parameterized10 | 25| |552 | rdpp1_inst |xpm_counter_updn__parameterized11 | 8| |553 | rst_d1_inst |xpm_fifo_reg_bit_977 | 3| |554 | wrp_inst |xpm_counter_updn__parameterized10_978 | 12| |555 | wrpp1_inst |xpm_counter_updn__parameterized11_979 | 8| |556 | wrpp2_inst |xpm_counter_updn__parameterized8 | 8| |557 | xpm_fifo_rst_inst |xpm_fifo_rst__parameterized0 | 46| |558 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__parameterized0__4 | 2| |559 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__parameterized0__5 | 2| |560 | INTERRUPT_CONTROL_I |interrupt_control__parameterized1 | 33| |561 | \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I |qspi_mode_0_module | 364| |562 | RESET_SYNC_AXI_SPI_CLK_INST |reset_sync_module | 3| |563 | SOFT_RESET_I |axi_quad_spi_v3_2_19_soft_reset | 39| |564 | \STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I |qspi_status_slave_sel_reg | 3| |565 | axi_hwicap_0 |axi4_subsys_axi_hwicap_0_0 | 1913| |566 | U0 |axi_hwicap | 1913| |567 | \ICAP_SHARED.HWICAP_CTRL_I |hwicap_shared | 1643| |568 | GEN_BUS2ICAP_RESET |cdc_sync__parameterized3 | 4| |569 | IPIC_IF_I |axi_hwicap_v3_0_24_ipic_if | 1341| |570 | BUS2ICAP_SIZE_REGISTER_PROCESS |cdc_sync__parameterized1 | 48| |571 | FIFO_RST_CDC_PROCESS |cdc_sync__parameterized5 | 5| |572 | ICAP2BUS_STATUS_REGISTER_PROCESS |cdc_sync__parameterized2 | 128| |573 | ICAP2PLB_SYNCH1 |cdc_sync__parameterized3_953 | 4| |574 | ICAP2PLB_SYNCH2 |cdc_sync__parameterized3_954 | 6| |575 | ICAP2PLB_SYNCH3 |cdc_sync__parameterized3_955 | 4| |576 | ICAP2PLB_SYNCH4 |cdc_sync__parameterized3_956 | 4| |577 | ICAP2PLB_SYNCH5 |cdc_sync__parameterized1_957 | 48| |578 | PLB2ICAP_SYNCH1 |cdc_sync__parameterized3_958 | 6| |579 | PLB2ICAP_SYNCH2 |cdc_sync__parameterized3_959 | 5| |580 | PLB2ICAP_SYNCH3 |cdc_sync__parameterized3_960 | 6| |581 | \RD_FIFO.RDDATA_FIFO_I |async_fifo_fg__parameterized0 | 504| |582 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async__parameterized1 | 497| |583 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base__parameterized0 | 497| |584 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base__parameterized0 | 2| |585 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__parameterized0__1 | 47| |586 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized1__1 | 54| |587 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray__parameterized0__2 | 47| |588 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized1 | 54| |589 | \gae_rptr_p2.rdpp2_inst |xpm_counter_updn__parameterized4 | 15| |590 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn__parameterized3 | 15| |591 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec__parameterized0_967 | 18| |592 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized1 | 8| |593 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec__parameterized0_968 | 26| |594 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized1_969 | 18| |595 | rdp_inst |xpm_counter_updn__parameterized5 | 18| |596 | rdpp1_inst |xpm_counter_updn__parameterized6 | 15| |597 | rst_d1_inst |xpm_fifo_reg_bit_970 | 3| |598 | wrp_inst |xpm_counter_updn__parameterized5_971 | 28| |599 | wrpp1_inst |xpm_counter_updn__parameterized6_972 | 24| |600 | wrpp2_inst |xpm_counter_updn__parameterized4_973 | 15| |601 | xpm_fifo_rst_inst |xpm_fifo_rst | 48| |602 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__4 | 4| |603 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst__5 | 4| |604 | \RD_FIFO.RDFULL_SYNCH |cdc_sync__parameterized4 | 4| |605 | \WRFIFO.WRDATA_FIFO_I |async_fifo_fg | 447| |606 | \xpm_fifo_instance.xpm_fifo_async_inst |xpm_fifo_async | 440| |607 | \gnuram_async_fifo.xpm_fifo_base_inst |xpm_fifo_base | 440| |608 | \gen_sdpram.xpm_memory_base_inst |xpm_memory_base | 2| |609 | \gen_cdc_pntr.wr_pntr_cdc_inst |xpm_cdc_gray__1 | 40| |610 | \gen_cdc_pntr.wr_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized0__3 | 47| |611 | \gen_cdc_pntr.rd_pntr_cdc_inst |xpm_cdc_gray | 40| |612 | \gen_cdc_pntr.rd_pntr_cdc_dc_inst |xpm_cdc_gray__parameterized0 | 47| |613 | \gae_rptr_p2.rdpp2_inst |xpm_counter_updn__parameterized0 | 13| |614 | \gaf_wptr_p3.wrpp3_inst |xpm_counter_updn | 17| |615 | \gen_cdc_pntr.rpw_gray_reg |xpm_fifo_reg_vec | 9| |616 | \gen_cdc_pntr.rpw_gray_reg_dc |xpm_fifo_reg_vec__parameterized0 | 7| |617 | \gen_cdc_pntr.wpr_gray_reg |xpm_fifo_reg_vec_962 | 23| |618 | \gen_cdc_pntr.wpr_gray_reg_dc |xpm_fifo_reg_vec__parameterized0_963 | 16| |619 | rdp_inst |xpm_counter_updn__parameterized1 | 16| |620 | rdpp1_inst |xpm_counter_updn__parameterized2 | 13| |621 | rst_d1_inst |xpm_fifo_reg_bit | 4| |622 | wrp_inst |xpm_counter_updn__parameterized1_964 | 24| |623 | wrpp1_inst |xpm_counter_updn__parameterized2_965 | 21| |624 | wrpp2_inst |xpm_counter_updn__parameterized0_966 | 16| |625 | xpm_fifo_rst_inst |xpm_fifo_rst__xdcDup__1 | 47| |626 | \gen_rst_ic.wrst_rd_inst |xpm_cdc_sync_rst__6 | 4| |627 | \gen_rst_ic.rrst_wr_inst |xpm_cdc_sync_rst | 4| |628 | \WRFIFO.WREMPTY_SYNCH |cdc_sync__parameterized3_961 | 5| |629 | icap_statemachine_I1 |icap_statemachine_shared | 289| |630 | INTERRUPT_CONTROL_I |interrupt_control | 19| |631 | XI4_LITE_I |axi_lite_ipif__parameterized0 | 217| |632 | I_SLAVE_ATTACHMENT |slave_attachment__parameterized0 | 217| |633 | I_DECODER |address_decoder__parameterized0 | 130| |634 | axi_gpio_0 |axi4_subsys_axi_gpio_0_0 | 451| |635 | U0 |axi_gpio | 451| |636 | AXI_LITE_IPIF_I |axi_lite_ipif | 147| |637 | I_SLAVE_ATTACHMENT |slave_attachment | 147| |638 | I_DECODER |address_decoder | 71| |639 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f | 1| |640 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |axi_lite_ipif_v3_0_4_pselect_f__parameterized1 | 1| |641 | gpio_core_1 |GPIO_Core | 269| |642 | \Dual.INPUT_DOUBLE_REGS5 |cdc_sync__parameterized0 | 96| |643 | backplane |aurora_64b_rx_12ch | 4862| |644 | combined_ttc |combined_ttc_rx | 454| |645 | sume_RO_Rx_support_i |sume_RO_Rx_support | 92| |646 | gt_usrclk_source |sume_RO_Rx_GT_USRCLK_SOURCE | 1| |647 | gt0_frame_check |sume_RO_Rx_GT_FRAME_CHECK | 208| |648 | inst_regs |rx_registers | 137| |649 | aurora_10 |aurora_rx_4l_64b_exdes__parameterized2 | 351| |650 | aurora_module_i |aurora_rx_4l_64b_support__parameterized1 | 253| |651 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_950 | 1| |652 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_951 | 20| |653 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_952 | 8| |654 | aurora_11 |aurora_rx_1q_exdes__xdcDup__5 | 351| |655 | aurora_module_i |aurora_rx_1q_support__xdcDup__5 | 253| |656 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_946 | 1| |657 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_947 | 20| |658 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_949 | 8| |659 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_948 | 1| |660 | aurora_12 |aurora_rx_4l_64b_exdes__xdcDup__4 | 353| |661 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__4 | 255| |662 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_942 | 1| |663 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_943 | 20| |664 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_945 | 8| |665 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_944 | 2| |666 | aurora_13 |aurora_rx_1q_exdes | 351| |667 | aurora_module_i |aurora_rx_1q_support | 253| |668 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_938 | 1| |669 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_939 | 20| |670 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_941 | 8| |671 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_940 | 1| |672 | aurora_14 |aurora_rx_4l_64b_exdes | 353| |673 | aurora_module_i |aurora_rx_4l_64b_support | 255| |674 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_934 | 1| |675 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_935 | 20| |676 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_937 | 8| |677 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_936 | 2| |678 | aurora_3 |aurora_rx_1q_exdes__xdcDup__1 | 359| |679 | aurora_module_i |aurora_rx_1q_support__xdcDup__1 | 253| |680 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_930 | 1| |681 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_931 | 20| |682 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_933 | 8| |683 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_932 | 1| |684 | aurora_4 |aurora_rx_4l_64b_exdes__xdcDup__1 | 353| |685 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__1 | 255| |686 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_926 | 1| |687 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_927 | 20| |688 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_929 | 8| |689 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_928 | 2| |690 | aurora_5 |aurora_rx_1q_exdes__xdcDup__2 | 359| |691 | aurora_module_i |aurora_rx_1q_support__xdcDup__2 | 253| |692 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_922 | 1| |693 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_923 | 20| |694 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_925 | 8| |695 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_924 | 1| |696 | aurora_6 |aurora_rx_4l_64b_exdes__xdcDup__2 | 353| |697 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__2 | 255| |698 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE_918 | 1| |699 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC_919 | 20| |700 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes_921 | 8| |701 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper_920 | 2| |702 | aurora_7 |aurora_rx_1q_exdes__xdcDup__3 | 351| |703 | aurora_module_i |aurora_rx_1q_support__xdcDup__3 | 253| |704 | clock_module_i |aurora_rx_1q_CLOCK_MODULE_914 | 1| |705 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC_915 | 20| |706 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes_917 | 8| |707 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper_916 | 1| |708 | aurora_8 |aurora_rx_4l_64b_exdes__xdcDup__3 | 353| |709 | aurora_module_i |aurora_rx_4l_64b_support__xdcDup__3 | 255| |710 | clock_module_i |aurora_rx_4l_64b_CLOCK_MODULE | 1| |711 | support_reset_logic_i |aurora_rx_4l_64b_SUPPORT_RESET_LOGIC | 20| |712 | gt_rst_r_cdc_sync |aurora_rx_4l_64b_cdc_sync_exdes | 8| |713 | \use_common.gt_common_support |aurora_rx_4l_64b_gt_common_wrapper | 2| |714 | aurora_9 |aurora_rx_1q_exdes__xdcDup__4 | 351| |715 | aurora_module_i |aurora_rx_1q_support__xdcDup__4 | 253| |716 | clock_module_i |aurora_rx_1q_CLOCK_MODULE | 1| |717 | support_reset_logic_i |aurora_rx_1q_SUPPORT_RESET_LOGIC | 20| |718 | gt_rst_r_cdc_sync |aurora_rx_1q_cdc_sync_exdes | 8| |719 | \use_common.gt_common_support |aurora_rx_1q_gt_common_wrapper | 1| |720 | pulse_stretcher |pulse_stretch | 18| |721 | pwer_on_rst |pwr_on_timer | 81| |722 | readout_ctrl |rod_RO_Tx_exdes | 63| |723 | rod_RO_Tx_support_i |rod_RO_Tx_support | 51| |724 | gt_usrclk_source |rod_RO_Tx_GT_USRCLK_SOURCE | 1| |725 | event_builder |packet_processor | 53948| |726 | fifo_layer |input_fifos | 40282| |727 | ch0 |channel_fifo | 3287| |728 | \gen_reg.status_regs |fex_chan_regs__5 | 2348| |729 | Aurora_autoreset_disable |ipbus_reg_v_857 | 33| |730 | Aurora_channel_control_reg |ipbus_reg_v_858 | 43| |731 | Aurora_channel_status_reg |ipbus_syncreg_v_859 | 71| |732 | rsync |syncreg_r_913 | 69| |733 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_860 | 83| |734 | rsync |syncreg_r_912 | 81| |735 | Aurora_self_reset_count_reg |ipbus_syncreg_v_861 | 51| |736 | rsync |syncreg_r_911 | 49| |737 | Bulk_fifo_control_reg |ipbus_reg_v_862 | 36| |738 | FEX_Busy_timer_reset_reg |ipbus_reg_v_863 | 87| |739 | Fex_busy_status_reg |ipbus_syncreg_v_864 | 38| |740 | rsync |syncreg_r_910 | 36| |741 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_865 | 52| |742 | rsync |syncreg_r_909 | 50| |743 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_866 | 51| |744 | rsync |syncreg_r_908 | 49| |745 | Frame_error_counter |error_counter__parameterized0_867 | 9| |746 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_868 | 52| |747 | rsync |syncreg_r_907 | 50| |748 | Tob_fifo_control_reg |ipbus_reg_v_869 | 37| |749 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_870 | 149| |750 | rsync |syncreg_r_906 | 147| |751 | Tob_fifo_reset_reg |ipbus_reg_v_871 | 36| |752 | Tob_fifo_status_reg |ipbus_syncreg_v_872 | 63| |753 | rsync |syncreg_r_905 | 61| |754 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_873 | 52| |755 | rsync |syncreg_r_904 | 50| |756 | UFC_Busy_control_reg |ipbus_reg_v_874 | 33| |757 | UFC_msg_crc_error_reg |ipbus_syncreg_v_875 | 50| |758 | rsync |syncreg_r_903 | 48| |759 | aurora_reset_pulse |pulse_stretch__parameterized5_876 | 14| |760 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_877 | 51| |761 | rsync |syncreg_r_902 | 49| |762 | bulk_fifo_busy_counter |threshold_counter_878 | 90| |763 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_879 | 51| |764 | rsync |syncreg_r_901 | 49| |765 | bulk_fifo_reset_reg |ipbus_reg_v_880 | 68| |766 | bulk_fifo_status_reg |ipbus_syncreg_v_881 | 61| |767 | rsync |syncreg_r_900 | 59| |768 | bulk_fifo_watermark |watermark_882 | 34| |769 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_883 | 111| |770 | rsync |syncreg_r_899 | 109| |771 | bulk_fifo_xoff_counter |threshold_counter_884 | 90| |772 | chan_len_err_counter |edge_error_counter_885 | 10| |773 | chan_reset |channel_init_886 | 259| |774 | reset_timer |aurora_reset_896 | 123| |775 | self_reset_inst |self_reset_897 | 121| |776 | stretcher |pulse_stretch__parameterized5_898 | 15| |777 | data_integrity_status_reg |ipbus_syncreg_v_887 | 26| |778 | rsync |syncreg_r_895 | 24| |779 | hard_error_counter |error_counter__parameterized0_888 | 9| |780 | header_crc_err_counter |error_counter__parameterized0_889 | 9| |781 | protocol_error_counter |error_counter__parameterized0_890 | 9| |782 | soft_error_counter |error_counter__parameterized0_891 | 9| |783 | tob_fifo_busy_counter |threshold_counter_892 | 90| |784 | tob_fifo_watermark |watermark_893 | 34| |785 | tob_fifo_xoff_counter |threshold_counter_894 | 90| |786 | pulse_stretcher |pulse_stretch__parameterized1__3 | 22| |787 | input_pipe |aurora_pipe | 537| |788 | crc_gen |CRC_855 | 98| |789 | pulse_stretcher |pulse_stretch__parameterized3_856 | 18| |790 | ufc_receiver |ufc_rx__1 | 90| |791 | ch1 |channel_fifo__parameterized1 | 3287| |792 | \gen_reg.status_regs |fex_chan_regs__6 | 2348| |793 | Aurora_autoreset_disable |ipbus_reg_v_798 | 33| |794 | Aurora_channel_control_reg |ipbus_reg_v_799 | 43| |795 | Aurora_channel_status_reg |ipbus_syncreg_v_800 | 71| |796 | rsync |syncreg_r_854 | 69| |797 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_801 | 83| |798 | rsync |syncreg_r_853 | 81| |799 | Aurora_self_reset_count_reg |ipbus_syncreg_v_802 | 51| |800 | rsync |syncreg_r_852 | 49| |801 | Bulk_fifo_control_reg |ipbus_reg_v_803 | 36| |802 | FEX_Busy_timer_reset_reg |ipbus_reg_v_804 | 87| |803 | Fex_busy_status_reg |ipbus_syncreg_v_805 | 38| |804 | rsync |syncreg_r_851 | 36| |805 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_806 | 52| |806 | rsync |syncreg_r_850 | 50| |807 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_807 | 51| |808 | rsync |syncreg_r_849 | 49| |809 | Frame_error_counter |error_counter__parameterized0_808 | 9| |810 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_809 | 52| |811 | rsync |syncreg_r_848 | 50| |812 | Tob_fifo_control_reg |ipbus_reg_v_810 | 37| |813 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_811 | 149| |814 | rsync |syncreg_r_847 | 147| |815 | Tob_fifo_reset_reg |ipbus_reg_v_812 | 36| |816 | Tob_fifo_status_reg |ipbus_syncreg_v_813 | 63| |817 | rsync |syncreg_r_846 | 61| |818 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_814 | 52| |819 | rsync |syncreg_r_845 | 50| |820 | UFC_Busy_control_reg |ipbus_reg_v_815 | 33| |821 | UFC_msg_crc_error_reg |ipbus_syncreg_v_816 | 50| |822 | rsync |syncreg_r_844 | 48| |823 | aurora_reset_pulse |pulse_stretch__parameterized5_817 | 14| |824 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_818 | 51| |825 | rsync |syncreg_r_843 | 49| |826 | bulk_fifo_busy_counter |threshold_counter_819 | 90| |827 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_820 | 51| |828 | rsync |syncreg_r_842 | 49| |829 | bulk_fifo_reset_reg |ipbus_reg_v_821 | 68| |830 | bulk_fifo_status_reg |ipbus_syncreg_v_822 | 61| |831 | rsync |syncreg_r_841 | 59| |832 | bulk_fifo_watermark |watermark_823 | 34| |833 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_824 | 111| |834 | rsync |syncreg_r_840 | 109| |835 | bulk_fifo_xoff_counter |threshold_counter_825 | 90| |836 | chan_len_err_counter |edge_error_counter_826 | 10| |837 | chan_reset |channel_init_827 | 259| |838 | reset_timer |aurora_reset_837 | 123| |839 | self_reset_inst |self_reset_838 | 121| |840 | stretcher |pulse_stretch__parameterized5_839 | 15| |841 | data_integrity_status_reg |ipbus_syncreg_v_828 | 26| |842 | rsync |syncreg_r_836 | 24| |843 | hard_error_counter |error_counter__parameterized0_829 | 9| |844 | header_crc_err_counter |error_counter__parameterized0_830 | 9| |845 | protocol_error_counter |error_counter__parameterized0_831 | 9| |846 | soft_error_counter |error_counter__parameterized0_832 | 9| |847 | tob_fifo_busy_counter |threshold_counter_833 | 90| |848 | tob_fifo_watermark |watermark_834 | 34| |849 | tob_fifo_xoff_counter |threshold_counter_835 | 90| |850 | pulse_stretcher |pulse_stretch__parameterized1__4 | 22| |851 | input_pipe |aurora_pipe__parameterized1 | 537| |852 | crc_gen |CRC_796 | 98| |853 | pulse_stretcher |pulse_stretch__parameterized3_797 | 18| |854 | ufc_receiver |ufc_rx__2 | 90| |855 | ch2 |channel_fifo__parameterized3 | 3287| |856 | \gen_reg.status_regs |fex_chan_regs__7 | 2348| |857 | Aurora_autoreset_disable |ipbus_reg_v_739 | 33| |858 | Aurora_channel_control_reg |ipbus_reg_v_740 | 43| |859 | Aurora_channel_status_reg |ipbus_syncreg_v_741 | 71| |860 | rsync |syncreg_r_795 | 69| |861 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_742 | 83| |862 | rsync |syncreg_r_794 | 81| |863 | Aurora_self_reset_count_reg |ipbus_syncreg_v_743 | 51| |864 | rsync |syncreg_r_793 | 49| |865 | Bulk_fifo_control_reg |ipbus_reg_v_744 | 36| |866 | FEX_Busy_timer_reset_reg |ipbus_reg_v_745 | 87| |867 | Fex_busy_status_reg |ipbus_syncreg_v_746 | 38| |868 | rsync |syncreg_r_792 | 36| |869 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_747 | 52| |870 | rsync |syncreg_r_791 | 50| |871 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_748 | 51| |872 | rsync |syncreg_r_790 | 49| |873 | Frame_error_counter |error_counter__parameterized0_749 | 9| |874 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_750 | 52| |875 | rsync |syncreg_r_789 | 50| |876 | Tob_fifo_control_reg |ipbus_reg_v_751 | 37| |877 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_752 | 149| |878 | rsync |syncreg_r_788 | 147| |879 | Tob_fifo_reset_reg |ipbus_reg_v_753 | 36| |880 | Tob_fifo_status_reg |ipbus_syncreg_v_754 | 63| |881 | rsync |syncreg_r_787 | 61| |882 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_755 | 52| |883 | rsync |syncreg_r_786 | 50| |884 | UFC_Busy_control_reg |ipbus_reg_v_756 | 33| |885 | UFC_msg_crc_error_reg |ipbus_syncreg_v_757 | 50| |886 | rsync |syncreg_r_785 | 48| |887 | aurora_reset_pulse |pulse_stretch__parameterized5_758 | 14| |888 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_759 | 51| |889 | rsync |syncreg_r_784 | 49| |890 | bulk_fifo_busy_counter |threshold_counter_760 | 90| |891 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_761 | 51| |892 | rsync |syncreg_r_783 | 49| |893 | bulk_fifo_reset_reg |ipbus_reg_v_762 | 68| |894 | bulk_fifo_status_reg |ipbus_syncreg_v_763 | 61| |895 | rsync |syncreg_r_782 | 59| |896 | bulk_fifo_watermark |watermark_764 | 34| |897 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_765 | 111| |898 | rsync |syncreg_r_781 | 109| |899 | bulk_fifo_xoff_counter |threshold_counter_766 | 90| |900 | chan_len_err_counter |edge_error_counter_767 | 10| |901 | chan_reset |channel_init_768 | 259| |902 | reset_timer |aurora_reset_778 | 123| |903 | self_reset_inst |self_reset_779 | 121| |904 | stretcher |pulse_stretch__parameterized5_780 | 15| |905 | data_integrity_status_reg |ipbus_syncreg_v_769 | 26| |906 | rsync |syncreg_r_777 | 24| |907 | hard_error_counter |error_counter__parameterized0_770 | 9| |908 | header_crc_err_counter |error_counter__parameterized0_771 | 9| |909 | protocol_error_counter |error_counter__parameterized0_772 | 9| |910 | soft_error_counter |error_counter__parameterized0_773 | 9| |911 | tob_fifo_busy_counter |threshold_counter_774 | 90| |912 | tob_fifo_watermark |watermark_775 | 34| |913 | tob_fifo_xoff_counter |threshold_counter_776 | 90| |914 | pulse_stretcher |pulse_stretch__parameterized1__5 | 22| |915 | input_pipe |aurora_pipe__parameterized3 | 537| |916 | crc_gen |CRC_737 | 98| |917 | pulse_stretcher |pulse_stretch__parameterized3_738 | 18| |918 | ufc_receiver |ufc_rx__3 | 90| |919 | ch3 |channel_fifo__parameterized5 | 3287| |920 | \gen_reg.status_regs |fex_chan_regs | 2348| |921 | Aurora_autoreset_disable |ipbus_reg_v_680 | 33| |922 | Aurora_channel_control_reg |ipbus_reg_v_681 | 43| |923 | Aurora_channel_status_reg |ipbus_syncreg_v_682 | 71| |924 | rsync |syncreg_r_736 | 69| |925 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_683 | 83| |926 | rsync |syncreg_r_735 | 81| |927 | Aurora_self_reset_count_reg |ipbus_syncreg_v_684 | 51| |928 | rsync |syncreg_r_734 | 49| |929 | Bulk_fifo_control_reg |ipbus_reg_v_685 | 36| |930 | FEX_Busy_timer_reset_reg |ipbus_reg_v_686 | 87| |931 | Fex_busy_status_reg |ipbus_syncreg_v_687 | 38| |932 | rsync |syncreg_r_733 | 36| |933 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_688 | 52| |934 | rsync |syncreg_r_732 | 50| |935 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_689 | 51| |936 | rsync |syncreg_r_731 | 49| |937 | Frame_error_counter |error_counter__parameterized0_690 | 9| |938 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_691 | 52| |939 | rsync |syncreg_r_730 | 50| |940 | Tob_fifo_control_reg |ipbus_reg_v_692 | 37| |941 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_693 | 149| |942 | rsync |syncreg_r_729 | 147| |943 | Tob_fifo_reset_reg |ipbus_reg_v_694 | 36| |944 | Tob_fifo_status_reg |ipbus_syncreg_v_695 | 63| |945 | rsync |syncreg_r_728 | 61| |946 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_696 | 52| |947 | rsync |syncreg_r_727 | 50| |948 | UFC_Busy_control_reg |ipbus_reg_v_697 | 33| |949 | UFC_msg_crc_error_reg |ipbus_syncreg_v_698 | 50| |950 | rsync |syncreg_r_726 | 48| |951 | aurora_reset_pulse |pulse_stretch__parameterized5_699 | 14| |952 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_700 | 51| |953 | rsync |syncreg_r_725 | 49| |954 | bulk_fifo_busy_counter |threshold_counter_701 | 90| |955 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_702 | 51| |956 | rsync |syncreg_r_724 | 49| |957 | bulk_fifo_reset_reg |ipbus_reg_v_703 | 68| |958 | bulk_fifo_status_reg |ipbus_syncreg_v_704 | 61| |959 | rsync |syncreg_r_723 | 59| |960 | bulk_fifo_watermark |watermark_705 | 34| |961 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_706 | 111| |962 | rsync |syncreg_r_722 | 109| |963 | bulk_fifo_xoff_counter |threshold_counter_707 | 90| |964 | chan_len_err_counter |edge_error_counter_708 | 10| |965 | chan_reset |channel_init_709 | 259| |966 | reset_timer |aurora_reset_719 | 123| |967 | self_reset_inst |self_reset_720 | 121| |968 | stretcher |pulse_stretch__parameterized5_721 | 15| |969 | data_integrity_status_reg |ipbus_syncreg_v_710 | 26| |970 | rsync |syncreg_r_718 | 24| |971 | hard_error_counter |error_counter__parameterized0_711 | 9| |972 | header_crc_err_counter |error_counter__parameterized0_712 | 9| |973 | protocol_error_counter |error_counter__parameterized0_713 | 9| |974 | soft_error_counter |error_counter__parameterized0_714 | 9| |975 | tob_fifo_busy_counter |threshold_counter_715 | 90| |976 | tob_fifo_watermark |watermark_716 | 34| |977 | tob_fifo_xoff_counter |threshold_counter_717 | 90| |978 | pulse_stretcher |pulse_stretch__parameterized1__6 | 22| |979 | input_pipe |aurora_pipe__parameterized5 | 537| |980 | crc_gen |CRC_678 | 98| |981 | pulse_stretcher |pulse_stretch__parameterized3_679 | 18| |982 | ufc_receiver |ufc_rx__4 | 90| |983 | \gen_reg.registers |backplane_regs | 720| |984 | Bulk_fifo_busy_threshold_reg |ipbus_reg_v_662 | 99| |985 | Bulk_fifo_xoff_threshold_reg |ipbus_reg_v_663 | 53| |986 | Time_count_value |ipbus_syncreg_v_664 | 53| |987 | rsync |syncreg_r_677 | 51| |988 | Tob_fifo_busy_threshold_reg |ipbus_reg_v_665 | 33| |989 | Tob_fifo_xoff_threshold_reg |ipbus_reg_v_666 | 33| |990 | backplane_control_reg |ipbus_reg_v_667 | 38| |991 | channel_disable |ipbus_reg_v_668 | 79| |992 | channel_map |ipbus_syncreg_v_669 | 42| |993 | rsync |syncreg_r_676 | 40| |994 | clk_tester |clock_test_ipbus | 97| |995 | clock_status |ipbus_syncreg_v_670 | 83| |996 | rsync |syncreg_r_675 | 81| |997 | first_last_chan |ipbus_syncreg_v_671 | 29| |998 | rsync |syncreg_r_674 | 27| |999 | first_last_encode |priority_encoder | 10| |1000 | ro_ctrl_status |ipbus_syncreg_v_672 | 25| |1001 | rsync |syncreg_r_673 | 23| |1002 | ch10 |channel_fifo__parameterized19 | 3137| |1003 | \gen_reg.status_regs |fex_chan_regs__13 | 2278| |1004 | Aurora_autoreset_disable |ipbus_reg_v_605 | 33| |1005 | Aurora_channel_control_reg |ipbus_reg_v_606 | 43| |1006 | Aurora_channel_status_reg |ipbus_syncreg_v_607 | 79| |1007 | rsync |syncreg_r_661 | 77| |1008 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_608 | 83| |1009 | rsync |syncreg_r_660 | 81| |1010 | Aurora_self_reset_count_reg |ipbus_syncreg_v_609 | 51| |1011 | rsync |syncreg_r_659 | 49| |1012 | Bulk_fifo_control_reg |ipbus_reg_v_610 | 36| |1013 | FEX_Busy_timer_reset_reg |ipbus_reg_v_611 | 87| |1014 | Fex_busy_status_reg |ipbus_syncreg_v_612 | 38| |1015 | rsync |syncreg_r_658 | 36| |1016 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_613 | 52| |1017 | rsync |syncreg_r_657 | 50| |1018 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_614 | 51| |1019 | rsync |syncreg_r_656 | 49| |1020 | Frame_error_counter |error_counter__parameterized0_615 | 9| |1021 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_616 | 52| |1022 | rsync |syncreg_r_655 | 50| |1023 | Tob_fifo_control_reg |ipbus_reg_v_617 | 37| |1024 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_618 | 117| |1025 | rsync |syncreg_r_654 | 115| |1026 | Tob_fifo_reset_reg |ipbus_reg_v_619 | 36| |1027 | Tob_fifo_status_reg |ipbus_syncreg_v_620 | 56| |1028 | rsync |syncreg_r_653 | 54| |1029 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_621 | 52| |1030 | rsync |syncreg_r_652 | 50| |1031 | UFC_Busy_control_reg |ipbus_reg_v_622 | 33| |1032 | UFC_msg_crc_error_reg |ipbus_syncreg_v_623 | 50| |1033 | rsync |syncreg_r_651 | 48| |1034 | aurora_reset_pulse |pulse_stretch__parameterized5_624 | 14| |1035 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_625 | 51| |1036 | rsync |syncreg_r_650 | 49| |1037 | bulk_fifo_busy_counter |threshold_counter_626 | 88| |1038 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_627 | 43| |1039 | rsync |syncreg_r_649 | 41| |1040 | bulk_fifo_reset_reg |ipbus_reg_v_628 | 84| |1041 | bulk_fifo_status_reg |ipbus_syncreg_v_629 | 54| |1042 | rsync |syncreg_r_648 | 52| |1043 | bulk_fifo_watermark |watermark_630 | 26| |1044 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_631 | 95| |1045 | rsync |syncreg_r_647 | 93| |1046 | bulk_fifo_xoff_counter |threshold_counter_632 | 88| |1047 | chan_len_err_counter |edge_error_counter_633 | 10| |1048 | chan_reset |channel_init_634 | 259| |1049 | reset_timer |aurora_reset_644 | 123| |1050 | self_reset_inst |self_reset_645 | 121| |1051 | stretcher |pulse_stretch__parameterized5_646 | 15| |1052 | data_integrity_status_reg |ipbus_syncreg_v_635 | 26| |1053 | rsync |syncreg_r_643 | 24| |1054 | hard_error_counter |error_counter__parameterized0_636 | 9| |1055 | header_crc_err_counter |error_counter__parameterized0_637 | 9| |1056 | protocol_error_counter |error_counter__parameterized0_638 | 9| |1057 | soft_error_counter |error_counter__parameterized0_639 | 9| |1058 | tob_fifo_busy_counter |threshold_counter_640 | 88| |1059 | tob_fifo_watermark |watermark_641 | 26| |1060 | tob_fifo_xoff_counter |threshold_counter_642 | 88| |1061 | pulse_stretcher |pulse_stretch__parameterized1__13 | 22| |1062 | ufc_receiver |ufc_rx__11 | 90| |1063 | input_pipe |aurora_pipe__parameterized19 | 544| |1064 | crc_gen |CRC_603 | 97| |1065 | pulse_stretcher |pulse_stretch__parameterized3_604 | 18| |1066 | ch11 |channel_fifo__parameterized21 | 3162| |1067 | \gen_reg.status_regs |fex_chan_regs__2 | 2278| |1068 | Aurora_autoreset_disable |ipbus_reg_v_546 | 33| |1069 | Aurora_channel_control_reg |ipbus_reg_v_547 | 43| |1070 | Aurora_channel_status_reg |ipbus_syncreg_v_548 | 79| |1071 | rsync |syncreg_r_602 | 77| |1072 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_549 | 83| |1073 | rsync |syncreg_r_601 | 81| |1074 | Aurora_self_reset_count_reg |ipbus_syncreg_v_550 | 51| |1075 | rsync |syncreg_r_600 | 49| |1076 | Bulk_fifo_control_reg |ipbus_reg_v_551 | 36| |1077 | FEX_Busy_timer_reset_reg |ipbus_reg_v_552 | 87| |1078 | Fex_busy_status_reg |ipbus_syncreg_v_553 | 38| |1079 | rsync |syncreg_r_599 | 36| |1080 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_554 | 52| |1081 | rsync |syncreg_r_598 | 50| |1082 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_555 | 51| |1083 | rsync |syncreg_r_597 | 49| |1084 | Frame_error_counter |error_counter__parameterized0_556 | 9| |1085 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_557 | 52| |1086 | rsync |syncreg_r_596 | 50| |1087 | Tob_fifo_control_reg |ipbus_reg_v_558 | 37| |1088 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_559 | 117| |1089 | rsync |syncreg_r_595 | 115| |1090 | Tob_fifo_reset_reg |ipbus_reg_v_560 | 36| |1091 | Tob_fifo_status_reg |ipbus_syncreg_v_561 | 56| |1092 | rsync |syncreg_r_594 | 54| |1093 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_562 | 52| |1094 | rsync |syncreg_r_593 | 50| |1095 | UFC_Busy_control_reg |ipbus_reg_v_563 | 33| |1096 | UFC_msg_crc_error_reg |ipbus_syncreg_v_564 | 50| |1097 | rsync |syncreg_r_592 | 48| |1098 | aurora_reset_pulse |pulse_stretch__parameterized5_565 | 14| |1099 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_566 | 51| |1100 | rsync |syncreg_r_591 | 49| |1101 | bulk_fifo_busy_counter |threshold_counter_567 | 88| |1102 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_568 | 43| |1103 | rsync |syncreg_r_590 | 41| |1104 | bulk_fifo_reset_reg |ipbus_reg_v_569 | 84| |1105 | bulk_fifo_status_reg |ipbus_syncreg_v_570 | 54| |1106 | rsync |syncreg_r_589 | 52| |1107 | bulk_fifo_watermark |watermark_571 | 26| |1108 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_572 | 95| |1109 | rsync |syncreg_r_588 | 93| |1110 | bulk_fifo_xoff_counter |threshold_counter_573 | 88| |1111 | chan_len_err_counter |edge_error_counter_574 | 10| |1112 | chan_reset |channel_init_575 | 259| |1113 | reset_timer |aurora_reset_585 | 123| |1114 | self_reset_inst |self_reset_586 | 121| |1115 | stretcher |pulse_stretch__parameterized5_587 | 15| |1116 | data_integrity_status_reg |ipbus_syncreg_v_576 | 26| |1117 | rsync |syncreg_r_584 | 24| |1118 | hard_error_counter |error_counter__parameterized0_577 | 9| |1119 | header_crc_err_counter |error_counter__parameterized0_578 | 9| |1120 | protocol_error_counter |error_counter__parameterized0_579 | 9| |1121 | soft_error_counter |error_counter__parameterized0_580 | 9| |1122 | tob_fifo_busy_counter |threshold_counter_581 | 88| |1123 | tob_fifo_watermark |watermark_582 | 26| |1124 | tob_fifo_xoff_counter |threshold_counter_583 | 88| |1125 | pulse_stretcher |pulse_stretch__parameterized1__14 | 22| |1126 | ufc_receiver |ufc_rx | 90| |1127 | input_pipe |aurora_pipe__parameterized21 | 544| |1128 | crc_gen |CRC_544 | 97| |1129 | pulse_stretcher |pulse_stretch__parameterized3_545 | 18| |1130 | ch4 |channel_fifo__parameterized7 | 3174| |1131 | \gen_reg.status_regs |fex_chan_regs__8 | 2291| |1132 | Aurora_autoreset_disable |ipbus_reg_v_486 | 33| |1133 | Aurora_channel_control_reg |ipbus_reg_v_487 | 43| |1134 | Aurora_channel_status_reg |ipbus_syncreg_v_488 | 75| |1135 | rsync |syncreg_r_543 | 73| |1136 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_489 | 83| |1137 | rsync |syncreg_r_542 | 81| |1138 | Aurora_self_reset_count_reg |ipbus_syncreg_v_490 | 51| |1139 | rsync |syncreg_r_541 | 49| |1140 | Bulk_fifo_control_reg |ipbus_reg_v_491 | 36| |1141 | FEX_Busy_timer_reset_reg |ipbus_reg_v_492 | 87| |1142 | Fex_busy_status_reg |ipbus_syncreg_v_493 | 38| |1143 | rsync |syncreg_r_540 | 36| |1144 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_494 | 52| |1145 | rsync |syncreg_r_539 | 50| |1146 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_495 | 51| |1147 | rsync |syncreg_r_538 | 49| |1148 | Frame_error_counter |error_counter__parameterized0_496 | 9| |1149 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_497 | 52| |1150 | rsync |syncreg_r_537 | 50| |1151 | Tob_fifo_control_reg |ipbus_reg_v_498 | 37| |1152 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_499 | 117| |1153 | rsync |syncreg_r_536 | 115| |1154 | Tob_fifo_reset_reg |ipbus_reg_v_500 | 36| |1155 | Tob_fifo_status_reg |ipbus_syncreg_v_501 | 56| |1156 | rsync |syncreg_r_535 | 54| |1157 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_502 | 52| |1158 | rsync |syncreg_r_534 | 50| |1159 | UFC_Busy_control_reg |ipbus_reg_v_503 | 33| |1160 | UFC_msg_crc_error_reg |ipbus_syncreg_v_504 | 50| |1161 | rsync |syncreg_r_533 | 48| |1162 | aurora_reset_pulse |pulse_stretch__parameterized5_505 | 14| |1163 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_506 | 51| |1164 | rsync |syncreg_r_532 | 49| |1165 | bulk_fifo_busy_counter |threshold_counter_507 | 88| |1166 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_508 | 43| |1167 | rsync |syncreg_r_531 | 41| |1168 | bulk_fifo_reset_reg |ipbus_reg_v_509 | 84| |1169 | bulk_fifo_status_reg |ipbus_syncreg_v_510 | 54| |1170 | rsync |syncreg_r_530 | 52| |1171 | bulk_fifo_watermark |watermark_511 | 26| |1172 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_512 | 95| |1173 | rsync |syncreg_r_529 | 93| |1174 | bulk_fifo_xoff_counter |threshold_counter_513 | 88| |1175 | chan_len_err_counter |edge_error_counter_514 | 10| |1176 | chan_reset |channel_init_515 | 259| |1177 | reset_timer |aurora_reset_526 | 123| |1178 | self_reset_inst |self_reset_527 | 121| |1179 | stretcher |pulse_stretch__parameterized5_528 | 15| |1180 | data_integrity_status_reg |ipbus_syncreg_v_516 | 34| |1181 | rsync |syncreg_r_525 | 32| |1182 | hard_error_counter |error_counter__parameterized0_517 | 9| |1183 | header_crc_err_counter |error_counter__parameterized0_518 | 9| |1184 | odd_word_counter |error_counter__parameterized0_519 | 9| |1185 | protocol_error_counter |error_counter__parameterized0_520 | 9| |1186 | soft_error_counter |error_counter__parameterized0_521 | 9| |1187 | tob_fifo_busy_counter |threshold_counter_522 | 88| |1188 | tob_fifo_watermark |watermark_523 | 26| |1189 | tob_fifo_xoff_counter |threshold_counter_524 | 88| |1190 | pulse_stretcher |pulse_stretch__parameterized1__7 | 22| |1191 | ufc_receiver |ufc_rx__5 | 90| |1192 | input_pipe |aurora_pipe__parameterized7 | 544| |1193 | crc_gen |CRC_484 | 97| |1194 | pulse_stretcher |pulse_stretch__parameterized3_485 | 18| |1195 | ch5 |channel_fifo__parameterized9 | 3171| |1196 | \gen_reg.status_regs |fex_chan_regs__9 | 2291| |1197 | Aurora_autoreset_disable |ipbus_reg_v_426 | 33| |1198 | Aurora_channel_control_reg |ipbus_reg_v_427 | 43| |1199 | Aurora_channel_status_reg |ipbus_syncreg_v_428 | 75| |1200 | rsync |syncreg_r_483 | 73| |1201 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_429 | 83| |1202 | rsync |syncreg_r_482 | 81| |1203 | Aurora_self_reset_count_reg |ipbus_syncreg_v_430 | 51| |1204 | rsync |syncreg_r_481 | 49| |1205 | Bulk_fifo_control_reg |ipbus_reg_v_431 | 36| |1206 | FEX_Busy_timer_reset_reg |ipbus_reg_v_432 | 87| |1207 | Fex_busy_status_reg |ipbus_syncreg_v_433 | 38| |1208 | rsync |syncreg_r_480 | 36| |1209 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_434 | 52| |1210 | rsync |syncreg_r_479 | 50| |1211 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_435 | 51| |1212 | rsync |syncreg_r_478 | 49| |1213 | Frame_error_counter |error_counter__parameterized0_436 | 9| |1214 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_437 | 52| |1215 | rsync |syncreg_r_477 | 50| |1216 | Tob_fifo_control_reg |ipbus_reg_v_438 | 37| |1217 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_439 | 117| |1218 | rsync |syncreg_r_476 | 115| |1219 | Tob_fifo_reset_reg |ipbus_reg_v_440 | 36| |1220 | Tob_fifo_status_reg |ipbus_syncreg_v_441 | 56| |1221 | rsync |syncreg_r_475 | 54| |1222 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_442 | 52| |1223 | rsync |syncreg_r_474 | 50| |1224 | UFC_Busy_control_reg |ipbus_reg_v_443 | 33| |1225 | UFC_msg_crc_error_reg |ipbus_syncreg_v_444 | 50| |1226 | rsync |syncreg_r_473 | 48| |1227 | aurora_reset_pulse |pulse_stretch__parameterized5_445 | 14| |1228 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_446 | 51| |1229 | rsync |syncreg_r_472 | 49| |1230 | bulk_fifo_busy_counter |threshold_counter_447 | 88| |1231 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_448 | 43| |1232 | rsync |syncreg_r_471 | 41| |1233 | bulk_fifo_reset_reg |ipbus_reg_v_449 | 84| |1234 | bulk_fifo_status_reg |ipbus_syncreg_v_450 | 54| |1235 | rsync |syncreg_r_470 | 52| |1236 | bulk_fifo_watermark |watermark_451 | 26| |1237 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_452 | 95| |1238 | rsync |syncreg_r_469 | 93| |1239 | bulk_fifo_xoff_counter |threshold_counter_453 | 88| |1240 | chan_len_err_counter |edge_error_counter_454 | 10| |1241 | chan_reset |channel_init_455 | 259| |1242 | reset_timer |aurora_reset_466 | 123| |1243 | self_reset_inst |self_reset_467 | 121| |1244 | stretcher |pulse_stretch__parameterized5_468 | 15| |1245 | data_integrity_status_reg |ipbus_syncreg_v_456 | 34| |1246 | rsync |syncreg_r_465 | 32| |1247 | hard_error_counter |error_counter__parameterized0_457 | 9| |1248 | header_crc_err_counter |error_counter__parameterized0_458 | 9| |1249 | odd_word_counter |error_counter__parameterized0_459 | 9| |1250 | protocol_error_counter |error_counter__parameterized0_460 | 9| |1251 | soft_error_counter |error_counter__parameterized0_461 | 9| |1252 | tob_fifo_busy_counter |threshold_counter_462 | 88| |1253 | tob_fifo_watermark |watermark_463 | 26| |1254 | tob_fifo_xoff_counter |threshold_counter_464 | 88| |1255 | pulse_stretcher |pulse_stretch__parameterized1__8 | 22| |1256 | ufc_receiver |ufc_rx__6 | 90| |1257 | input_pipe |aurora_pipe__parameterized9 | 544| |1258 | crc_gen |CRC_424 | 97| |1259 | pulse_stretcher |pulse_stretch__parameterized3_425 | 18| |1260 | ch6 |channel_fifo__parameterized11 | 3151| |1261 | \gen_reg.status_regs |fex_chan_regs__1 | 2291| |1262 | Aurora_autoreset_disable |ipbus_reg_v_366 | 33| |1263 | Aurora_channel_control_reg |ipbus_reg_v_367 | 43| |1264 | Aurora_channel_status_reg |ipbus_syncreg_v_368 | 75| |1265 | rsync |syncreg_r_423 | 73| |1266 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_369 | 83| |1267 | rsync |syncreg_r_422 | 81| |1268 | Aurora_self_reset_count_reg |ipbus_syncreg_v_370 | 51| |1269 | rsync |syncreg_r_421 | 49| |1270 | Bulk_fifo_control_reg |ipbus_reg_v_371 | 36| |1271 | FEX_Busy_timer_reset_reg |ipbus_reg_v_372 | 87| |1272 | Fex_busy_status_reg |ipbus_syncreg_v_373 | 38| |1273 | rsync |syncreg_r_420 | 36| |1274 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_374 | 52| |1275 | rsync |syncreg_r_419 | 50| |1276 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_375 | 51| |1277 | rsync |syncreg_r_418 | 49| |1278 | Frame_error_counter |error_counter__parameterized0_376 | 9| |1279 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_377 | 52| |1280 | rsync |syncreg_r_417 | 50| |1281 | Tob_fifo_control_reg |ipbus_reg_v_378 | 37| |1282 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_379 | 117| |1283 | rsync |syncreg_r_416 | 115| |1284 | Tob_fifo_reset_reg |ipbus_reg_v_380 | 36| |1285 | Tob_fifo_status_reg |ipbus_syncreg_v_381 | 56| |1286 | rsync |syncreg_r_415 | 54| |1287 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_382 | 52| |1288 | rsync |syncreg_r_414 | 50| |1289 | UFC_Busy_control_reg |ipbus_reg_v_383 | 33| |1290 | UFC_msg_crc_error_reg |ipbus_syncreg_v_384 | 50| |1291 | rsync |syncreg_r_413 | 48| |1292 | aurora_reset_pulse |pulse_stretch__parameterized5_385 | 14| |1293 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_386 | 51| |1294 | rsync |syncreg_r_412 | 49| |1295 | bulk_fifo_busy_counter |threshold_counter_387 | 88| |1296 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_388 | 43| |1297 | rsync |syncreg_r_411 | 41| |1298 | bulk_fifo_reset_reg |ipbus_reg_v_389 | 84| |1299 | bulk_fifo_status_reg |ipbus_syncreg_v_390 | 54| |1300 | rsync |syncreg_r_410 | 52| |1301 | bulk_fifo_watermark |watermark_391 | 26| |1302 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_392 | 95| |1303 | rsync |syncreg_r_409 | 93| |1304 | bulk_fifo_xoff_counter |threshold_counter_393 | 88| |1305 | chan_len_err_counter |edge_error_counter_394 | 10| |1306 | chan_reset |channel_init_395 | 259| |1307 | reset_timer |aurora_reset_406 | 123| |1308 | self_reset_inst |self_reset_407 | 121| |1309 | stretcher |pulse_stretch__parameterized5_408 | 15| |1310 | data_integrity_status_reg |ipbus_syncreg_v_396 | 34| |1311 | rsync |syncreg_r_405 | 32| |1312 | hard_error_counter |error_counter__parameterized0_397 | 9| |1313 | header_crc_err_counter |error_counter__parameterized0_398 | 9| |1314 | odd_word_counter |error_counter__parameterized0_399 | 9| |1315 | protocol_error_counter |error_counter__parameterized0_400 | 9| |1316 | soft_error_counter |error_counter__parameterized0_401 | 9| |1317 | tob_fifo_busy_counter |threshold_counter_402 | 88| |1318 | tob_fifo_watermark |watermark_403 | 26| |1319 | tob_fifo_xoff_counter |threshold_counter_404 | 88| |1320 | pulse_stretcher |pulse_stretch__parameterized1__9 | 22| |1321 | ufc_receiver |ufc_rx__7 | 90| |1322 | input_pipe |aurora_pipe__parameterized11 | 544| |1323 | crc_gen |CRC_364 | 97| |1324 | pulse_stretcher |pulse_stretch__parameterized3_365 | 18| |1325 | ch7 |channel_fifo__parameterized13 | 3197| |1326 | \gen_reg.status_regs |fex_chan_regs__10 | 2278| |1327 | Aurora_autoreset_disable |ipbus_reg_v_307 | 33| |1328 | Aurora_channel_control_reg |ipbus_reg_v_308 | 43| |1329 | Aurora_channel_status_reg |ipbus_syncreg_v_309 | 79| |1330 | rsync |syncreg_r_363 | 77| |1331 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_310 | 83| |1332 | rsync |syncreg_r_362 | 81| |1333 | Aurora_self_reset_count_reg |ipbus_syncreg_v_311 | 51| |1334 | rsync |syncreg_r_361 | 49| |1335 | Bulk_fifo_control_reg |ipbus_reg_v_312 | 36| |1336 | FEX_Busy_timer_reset_reg |ipbus_reg_v_313 | 87| |1337 | Fex_busy_status_reg |ipbus_syncreg_v_314 | 38| |1338 | rsync |syncreg_r_360 | 36| |1339 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_315 | 52| |1340 | rsync |syncreg_r_359 | 50| |1341 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_316 | 51| |1342 | rsync |syncreg_r_358 | 49| |1343 | Frame_error_counter |error_counter__parameterized0_317 | 9| |1344 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_318 | 52| |1345 | rsync |syncreg_r_357 | 50| |1346 | Tob_fifo_control_reg |ipbus_reg_v_319 | 37| |1347 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_320 | 117| |1348 | rsync |syncreg_r_356 | 115| |1349 | Tob_fifo_reset_reg |ipbus_reg_v_321 | 36| |1350 | Tob_fifo_status_reg |ipbus_syncreg_v_322 | 56| |1351 | rsync |syncreg_r_355 | 54| |1352 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_323 | 52| |1353 | rsync |syncreg_r_354 | 50| |1354 | UFC_Busy_control_reg |ipbus_reg_v_324 | 33| |1355 | UFC_msg_crc_error_reg |ipbus_syncreg_v_325 | 50| |1356 | rsync |syncreg_r_353 | 48| |1357 | aurora_reset_pulse |pulse_stretch__parameterized5_326 | 14| |1358 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_327 | 51| |1359 | rsync |syncreg_r_352 | 49| |1360 | bulk_fifo_busy_counter |threshold_counter_328 | 88| |1361 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_329 | 43| |1362 | rsync |syncreg_r_351 | 41| |1363 | bulk_fifo_reset_reg |ipbus_reg_v_330 | 84| |1364 | bulk_fifo_status_reg |ipbus_syncreg_v_331 | 54| |1365 | rsync |syncreg_r_350 | 52| |1366 | bulk_fifo_watermark |watermark_332 | 26| |1367 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_333 | 95| |1368 | rsync |syncreg_r_349 | 93| |1369 | bulk_fifo_xoff_counter |threshold_counter_334 | 88| |1370 | chan_len_err_counter |edge_error_counter_335 | 10| |1371 | chan_reset |channel_init_336 | 259| |1372 | reset_timer |aurora_reset_346 | 123| |1373 | self_reset_inst |self_reset_347 | 121| |1374 | stretcher |pulse_stretch__parameterized5_348 | 15| |1375 | data_integrity_status_reg |ipbus_syncreg_v_337 | 26| |1376 | rsync |syncreg_r_345 | 24| |1377 | hard_error_counter |error_counter__parameterized0_338 | 9| |1378 | header_crc_err_counter |error_counter__parameterized0_339 | 9| |1379 | protocol_error_counter |error_counter__parameterized0_340 | 9| |1380 | soft_error_counter |error_counter__parameterized0_341 | 9| |1381 | tob_fifo_busy_counter |threshold_counter_342 | 88| |1382 | tob_fifo_watermark |watermark_343 | 26| |1383 | tob_fifo_xoff_counter |threshold_counter_344 | 88| |1384 | pulse_stretcher |pulse_stretch__parameterized1__10 | 22| |1385 | ufc_receiver |ufc_rx__8 | 90| |1386 | input_pipe |aurora_pipe__parameterized13 | 544| |1387 | crc_gen |CRC_305 | 97| |1388 | pulse_stretcher |pulse_stretch__parameterized3_306 | 18| |1389 | ch8 |channel_fifo__parameterized15 | 3162| |1390 | \gen_reg.status_regs |fex_chan_regs__11 | 2278| |1391 | Aurora_autoreset_disable |ipbus_reg_v_248 | 33| |1392 | Aurora_channel_control_reg |ipbus_reg_v_249 | 43| |1393 | Aurora_channel_status_reg |ipbus_syncreg_v_250 | 79| |1394 | rsync |syncreg_r_304 | 77| |1395 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_251 | 83| |1396 | rsync |syncreg_r_303 | 81| |1397 | Aurora_self_reset_count_reg |ipbus_syncreg_v_252 | 51| |1398 | rsync |syncreg_r_302 | 49| |1399 | Bulk_fifo_control_reg |ipbus_reg_v_253 | 36| |1400 | FEX_Busy_timer_reset_reg |ipbus_reg_v_254 | 87| |1401 | Fex_busy_status_reg |ipbus_syncreg_v_255 | 38| |1402 | rsync |syncreg_r_301 | 36| |1403 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_256 | 52| |1404 | rsync |syncreg_r_300 | 50| |1405 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_257 | 51| |1406 | rsync |syncreg_r_299 | 49| |1407 | Frame_error_counter |error_counter__parameterized0_258 | 9| |1408 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_259 | 52| |1409 | rsync |syncreg_r_298 | 50| |1410 | Tob_fifo_control_reg |ipbus_reg_v_260 | 37| |1411 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_261 | 117| |1412 | rsync |syncreg_r_297 | 115| |1413 | Tob_fifo_reset_reg |ipbus_reg_v_262 | 36| |1414 | Tob_fifo_status_reg |ipbus_syncreg_v_263 | 56| |1415 | rsync |syncreg_r_296 | 54| |1416 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_264 | 52| |1417 | rsync |syncreg_r_295 | 50| |1418 | UFC_Busy_control_reg |ipbus_reg_v_265 | 33| |1419 | UFC_msg_crc_error_reg |ipbus_syncreg_v_266 | 50| |1420 | rsync |syncreg_r_294 | 48| |1421 | aurora_reset_pulse |pulse_stretch__parameterized5_267 | 14| |1422 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_268 | 51| |1423 | rsync |syncreg_r_293 | 49| |1424 | bulk_fifo_busy_counter |threshold_counter_269 | 88| |1425 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_270 | 43| |1426 | rsync |syncreg_r_292 | 41| |1427 | bulk_fifo_reset_reg |ipbus_reg_v_271 | 84| |1428 | bulk_fifo_status_reg |ipbus_syncreg_v_272 | 54| |1429 | rsync |syncreg_r_291 | 52| |1430 | bulk_fifo_watermark |watermark_273 | 26| |1431 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_274 | 95| |1432 | rsync |syncreg_r_290 | 93| |1433 | bulk_fifo_xoff_counter |threshold_counter_275 | 88| |1434 | chan_len_err_counter |edge_error_counter_276 | 10| |1435 | chan_reset |channel_init_277 | 259| |1436 | reset_timer |aurora_reset_287 | 123| |1437 | self_reset_inst |self_reset_288 | 121| |1438 | stretcher |pulse_stretch__parameterized5_289 | 15| |1439 | data_integrity_status_reg |ipbus_syncreg_v_278 | 26| |1440 | rsync |syncreg_r_286 | 24| |1441 | hard_error_counter |error_counter__parameterized0_279 | 9| |1442 | header_crc_err_counter |error_counter__parameterized0_280 | 9| |1443 | protocol_error_counter |error_counter__parameterized0_281 | 9| |1444 | soft_error_counter |error_counter__parameterized0_282 | 9| |1445 | tob_fifo_busy_counter |threshold_counter_283 | 88| |1446 | tob_fifo_watermark |watermark_284 | 26| |1447 | tob_fifo_xoff_counter |threshold_counter_285 | 88| |1448 | pulse_stretcher |pulse_stretch__parameterized1__11 | 22| |1449 | ufc_receiver |ufc_rx__9 | 90| |1450 | input_pipe |aurora_pipe__parameterized15 | 544| |1451 | crc_gen |CRC_246 | 97| |1452 | pulse_stretcher |pulse_stretch__parameterized3_247 | 18| |1453 | ch9 |channel_fifo__parameterized17 | 3139| |1454 | \gen_reg.status_regs |fex_chan_regs__12 | 2278| |1455 | Aurora_autoreset_disable |ipbus_reg_v_195 | 33| |1456 | Aurora_channel_control_reg |ipbus_reg_v_196 | 43| |1457 | Aurora_channel_status_reg |ipbus_syncreg_v_197 | 79| |1458 | rsync |syncreg_r_245 | 77| |1459 | Aurora_channel_up_timer_reg |ipbus_syncreg_v_198 | 83| |1460 | rsync |syncreg_r_244 | 81| |1461 | Aurora_self_reset_count_reg |ipbus_syncreg_v_199 | 51| |1462 | rsync |syncreg_r_243 | 49| |1463 | Bulk_fifo_control_reg |ipbus_reg_v_200 | 36| |1464 | FEX_Busy_timer_reset_reg |ipbus_reg_v_201 | 87| |1465 | Fex_busy_status_reg |ipbus_syncreg_v_202 | 38| |1466 | rsync |syncreg_r_242 | 36| |1467 | Fex_raw_busy_timer_reg |ipbus_syncreg_v_203 | 52| |1468 | rsync |syncreg_r_241 | 50| |1469 | Fex_tob_busy_timer_reg |ipbus_syncreg_v_204 | 51| |1470 | rsync |syncreg_r_240 | 49| |1471 | Frame_error_counter |error_counter__parameterized0 | 9| |1472 | Tob_fifo_busy_Count_reg |ipbus_syncreg_v_205 | 52| |1473 | rsync |syncreg_r_239 | 50| |1474 | Tob_fifo_control_reg |ipbus_reg_v_206 | 37| |1475 | Tob_fifo_fill_level_reg |ipbus_syncreg_v_207 | 117| |1476 | rsync |syncreg_r_238 | 115| |1477 | Tob_fifo_reset_reg |ipbus_reg_v_208 | 36| |1478 | Tob_fifo_status_reg |ipbus_syncreg_v_209 | 56| |1479 | rsync |syncreg_r_237 | 54| |1480 | Tob_fifo_xoff_Count_reg |ipbus_syncreg_v_210 | 52| |1481 | rsync |syncreg_r_236 | 50| |1482 | UFC_Busy_control_reg |ipbus_reg_v_211 | 33| |1483 | UFC_msg_crc_error_reg |ipbus_syncreg_v_212 | 50| |1484 | rsync |syncreg_r_235 | 48| |1485 | aurora_reset_pulse |pulse_stretch__parameterized5 | 14| |1486 | bulk_fifo_busy_Count_reg |ipbus_syncreg_v_213 | 51| |1487 | rsync |syncreg_r_234 | 49| |1488 | bulk_fifo_busy_counter |threshold_counter_214 | 88| |1489 | bulk_fifo_fill_level_reg |ipbus_syncreg_v_215 | 43| |1490 | rsync |syncreg_r_233 | 41| |1491 | bulk_fifo_reset_reg |ipbus_reg_v_216 | 84| |1492 | bulk_fifo_status_reg |ipbus_syncreg_v_217 | 54| |1493 | rsync |syncreg_r_232 | 52| |1494 | bulk_fifo_watermark |watermark_218 | 26| |1495 | bulk_fifo_xoff_Count_reg |ipbus_syncreg_v_219 | 95| |1496 | rsync |syncreg_r_231 | 93| |1497 | bulk_fifo_xoff_counter |threshold_counter_220 | 88| |1498 | chan_len_err_counter |edge_error_counter | 10| |1499 | chan_reset |channel_init | 259| |1500 | reset_timer |aurora_reset | 123| |1501 | self_reset_inst |self_reset | 121| |1502 | stretcher |pulse_stretch__parameterized5_230 | 15| |1503 | data_integrity_status_reg |ipbus_syncreg_v_221 | 26| |1504 | rsync |syncreg_r_229 | 24| |1505 | hard_error_counter |error_counter__parameterized0_222 | 9| |1506 | header_crc_err_counter |error_counter__parameterized0_223 | 9| |1507 | protocol_error_counter |error_counter__parameterized0_224 | 9| |1508 | soft_error_counter |error_counter__parameterized0_225 | 9| |1509 | tob_fifo_busy_counter |threshold_counter_226 | 88| |1510 | tob_fifo_watermark |watermark_227 | 26| |1511 | tob_fifo_xoff_counter |threshold_counter_228 | 88| |1512 | pulse_stretcher |pulse_stretch__parameterized1__12 | 22| |1513 | ufc_receiver |ufc_rx__10 | 90| |1514 | input_pipe |aurora_pipe__parameterized17 | 544| |1515 | crc_gen |CRC_194 | 97| |1516 | pulse_stretcher |pulse_stretch__parameterized3 | 18| |1517 | \gen_reg.ttc_regs |ttc_chan_regs | 1037| |1518 | BCN_reg |ipbus_syncreg_v_162 | 41| |1519 | rsync |syncreg_r_193 | 39| |1520 | CTTC_link_stat_reg |ipbus_syncreg_v_163 | 54| |1521 | rsync |syncreg_r_192 | 52| |1522 | L1ID_Value_reg |ipbus_syncreg_v_164 | 73| |1523 | rsync |syncreg_r_191 | 71| |1524 | TTC_control_reg |ipbus_reg_v_165 | 33| |1525 | TTC_fifo_busy_Count_reg |ipbus_syncreg_v_166 | 70| |1526 | rsync |syncreg_r_190 | 68| |1527 | TTC_fifo_busy_threshold_reg |ipbus_reg_v_167 | 69| |1528 | TTC_fifo_control_reg |ipbus_reg_v_168 | 65| |1529 | TTC_fifo_fill_level_reg |ipbus_syncreg_v_169 | 38| |1530 | rsync |syncreg_r_189 | 36| |1531 | TTC_fifo_status_reg |ipbus_syncreg_v_170 | 21| |1532 | rsync |syncreg_r_188 | 19| |1533 | TTC_reset_register |ipbus_reg_v_171 | 50| |1534 | bcn_adjust_reg |ipbus_reg_v_172 | 36| |1535 | crc_err_counter |error_counter | 19| |1536 | disperity_err_counter |error_counter_173 | 19| |1537 | event_count_reg |ipbus_syncreg_v_174 | 43| |1538 | rsync |syncreg_r_187 | 41| |1539 | felix_backpressure_reg |ipbus_syncreg_v_175 | 67| |1540 | rsync |syncreg_r_186 | 65| |1541 | orbit_reg |ipbus_syncreg_v_176 | 42| |1542 | rsync |syncreg_r_185 | 40| |1543 | packet_header_info |ipbus_reg_v_177 | 57| |1544 | table_err_counter |error_counter_178 | 19| |1545 | total_event_count_msb |ipbus_syncreg_v_179 | 29| |1546 | rsync |syncreg_r_184 | 27| |1547 | total_event_count_reg |ipbus_syncreg_v_180 | 70| |1548 | rsync |syncreg_r_183 | 68| |1549 | ttc_fifo_busy_counter |threshold_counter_181 | 50| |1550 | ttc_fifo_watermark |watermark_182 | 21| |1551 | bulk_2 |bulk_processor | 2377| |1552 | stretcher |pulse_stretch__parameterized1__16 | 22| |1553 | controller |bulk_controller__4 | 15| |1554 | state_reg |vDFF__parameterized1_161 | 15| |1555 | event_header_crc |event_hdr_crc9__5 | 100| |1556 | hdr_chk_crc |osum_crc9d32_160 | 85| |1557 | status_regs |bulk_proc_regs__4 | 1763| |1558 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v__33 | 33| |1559 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v__34 | 34| |1560 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v__63 | 49| |1561 | rsync |syncreg_r_159 | 47| |1562 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v__64 | 27| |1563 | rsync |syncreg_r_158 | 25| |1564 | \gen_regs.Full_mode_control_reg |ipbus_reg_v__35 | 33| |1565 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v__65 | 35| |1566 | rsync |syncreg_r_157 | 33| |1567 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v__66 | 49| |1568 | rsync |syncreg_r_156 | 47| |1569 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v__67 | 33| |1570 | rsync |syncreg_r_155 | 31| |1571 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v__68 | 49| |1572 | rsync |syncreg_r_154 | 47| |1573 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v__36 | 33| |1574 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v__37 | 33| |1575 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v__45 | 34| |1576 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v__69 | 22| |1577 | rsync |syncreg_r_153 | 20| |1578 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v__70 | 49| |1579 | rsync |syncreg_r_152 | 47| |1580 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v__87 | 49| |1581 | rsync |syncreg_r_151 | 47| |1582 | bulk_stage_busy_counter |threshold_counter_138 | 91| |1583 | bulk_stage_xoff_counter |threshold_counter_139 | 90| |1584 | \gen_regs.event_fifo_watermark |watermark_140 | 35| |1585 | \gen_regs.fm_fifo_watermark |watermark_141 | 18| |1586 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1_142 | 721| |1587 | Capture_Control_reg |ipbus_reg_v__32 | 34| |1588 | Capture_status_reg |ipbus_syncreg_v__56 | 22| |1589 | rsync |syncreg_r_150 | 20| |1590 | Header_0_reg |ipbus_syncreg_v__57 | 46| |1591 | rsync |syncreg_r_149 | 44| |1592 | Header_1_reg |ipbus_syncreg_v__58 | 49| |1593 | rsync |syncreg_r_148 | 47| |1594 | Header_2_reg |ipbus_syncreg_v__59 | 49| |1595 | rsync |syncreg_r_147 | 47| |1596 | trailer_0_reg |ipbus_syncreg_v__60 | 49| |1597 | rsync |syncreg_r_146 | 47| |1598 | trailer_1_reg |ipbus_syncreg_v__61 | 49| |1599 | rsync |syncreg_r_145 | 47| |1600 | pkt_count_reg |ipbus_syncreg_v__62 | 49| |1601 | rsync |syncreg_r_144 | 47| |1602 | \gen_regs.stage_fifo_watermark |watermark_143 | 35| |1603 | input_mux |bulk_channel_mux_137 | 254| |1604 | bulk_1 |bulk_processor__xdcDup__2 | 2377| |1605 | stretcher |pulse_stretch__parameterized1__15 | 22| |1606 | controller |bulk_controller__3 | 15| |1607 | state_reg |vDFF__parameterized1_136 | 15| |1608 | event_header_crc |event_hdr_crc9__4 | 100| |1609 | hdr_chk_crc |osum_crc9d32_135 | 85| |1610 | status_regs |bulk_proc_regs__3 | 1763| |1611 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v__44 | 33| |1612 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v__43 | 34| |1613 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v__86 | 49| |1614 | rsync |syncreg_r_134 | 47| |1615 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v__85 | 27| |1616 | rsync |syncreg_r_133 | 25| |1617 | \gen_regs.Full_mode_control_reg |ipbus_reg_v__42 | 33| |1618 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v__84 | 35| |1619 | rsync |syncreg_r_132 | 33| |1620 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v__83 | 49| |1621 | rsync |syncreg_r_131 | 47| |1622 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v__82 | 33| |1623 | rsync |syncreg_r_130 | 31| |1624 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v__81 | 49| |1625 | rsync |syncreg_r_129 | 47| |1626 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v__41 | 33| |1627 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v__40 | 33| |1628 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v__39 | 34| |1629 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v__80 | 22| |1630 | rsync |syncreg_r_128 | 20| |1631 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v__79 | 49| |1632 | rsync |syncreg_r_127 | 47| |1633 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v__78 | 49| |1634 | rsync |syncreg_r_126 | 47| |1635 | bulk_stage_busy_counter |threshold_counter_113 | 91| |1636 | bulk_stage_xoff_counter |threshold_counter_114 | 90| |1637 | \gen_regs.event_fifo_watermark |watermark_115 | 35| |1638 | \gen_regs.fm_fifo_watermark |watermark_116 | 18| |1639 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1_117 | 721| |1640 | Capture_Control_reg |ipbus_reg_v__38 | 34| |1641 | Capture_status_reg |ipbus_syncreg_v__77 | 22| |1642 | rsync |syncreg_r_125 | 20| |1643 | Header_0_reg |ipbus_syncreg_v__76 | 46| |1644 | rsync |syncreg_r_124 | 44| |1645 | Header_1_reg |ipbus_syncreg_v__75 | 49| |1646 | rsync |syncreg_r_123 | 47| |1647 | Header_2_reg |ipbus_syncreg_v__74 | 49| |1648 | rsync |syncreg_r_122 | 47| |1649 | trailer_0_reg |ipbus_syncreg_v__73 | 49| |1650 | rsync |syncreg_r_121 | 47| |1651 | trailer_1_reg |ipbus_syncreg_v__72 | 49| |1652 | rsync |syncreg_r_120 | 47| |1653 | pkt_count_reg |ipbus_syncreg_v__71 | 49| |1654 | rsync |syncreg_r_119 | 47| |1655 | \gen_regs.stage_fifo_watermark |watermark_118 | 35| |1656 | input_mux |bulk_channel_mux_112 | 254| |1657 | readout_controller |ro_controller | 437| |1658 | ro_crc |CRC | 167| |1659 | bulk_0 |bulk_processor__xdcDup__1 | 2356| |1660 | stretcher |pulse_stretch__parameterized1__17 | 22| |1661 | controller |bulk_controller | 15| |1662 | state_reg |vDFF__parameterized1 | 15| |1663 | event_header_crc |event_hdr_crc9 | 100| |1664 | hdr_chk_crc |osum_crc9d32_111 | 85| |1665 | status_regs |bulk_proc_regs | 1782| |1666 | \gen_regs.Event_fifo_control_reg |ipbus_reg_v__47 | 33| |1667 | \gen_regs.Event_fifo_reset_reg |ipbus_reg_v__48 | 34| |1668 | \gen_regs.event_fifo_fill_level_reg |ipbus_syncreg_v__95 | 49| |1669 | rsync |syncreg_r_110 | 47| |1670 | \gen_regs.Bulk_proc_status_reg |ipbus_syncreg_v__96 | 24| |1671 | rsync |syncreg_r_109 | 22| |1672 | \gen_regs.Full_mode_control_reg |ipbus_reg_v__49 | 33| |1673 | \gen_regs.full_mode_status_reg |ipbus_syncreg_v__97 | 35| |1674 | rsync |syncreg_r_108 | 33| |1675 | \gen_regs.stage_fifo_fill_level_reg |ipbus_syncreg_v__98 | 49| |1676 | rsync |syncreg_r_107 | 47| |1677 | \gen_regs.fullmode_fifo_fill_level_reg |ipbus_syncreg_v__99 | 33| |1678 | rsync |syncreg_r_106 | 31| |1679 | \gen_regs.fm_L1id_reg |ipbus_syncreg_v__100 | 49| |1680 | rsync |syncreg_r_105 | 47| |1681 | \gen_regs.bulk_staging_thresholds_reg |ipbus_reg_v__50 | 33| |1682 | \gen_regs.bulk_staging_control_reg |ipbus_reg_v__51 | 33| |1683 | \gen_regs.bulk_staging_fifo_resets_reg |ipbus_reg_v | 34| |1684 | \gen_regs.bulk_stage_fifo_status_reg |ipbus_syncreg_v__101 | 22| |1685 | rsync |syncreg_r_104 | 20| |1686 | \gen_regs.bulk_stage_busy_Count_reg |ipbus_syncreg_v__102 | 49| |1687 | rsync |syncreg_r_103 | 47| |1688 | \gen_regs.bulk_stage_xoff_Count_reg |ipbus_syncreg_v | 49| |1689 | rsync |syncreg_r_102 | 47| |1690 | bulk_stage_busy_counter |threshold_counter_90 | 91| |1691 | bulk_stage_xoff_counter |threshold_counter_91 | 90| |1692 | \gen_regs.event_fifo_watermark |watermark_92 | 35| |1693 | \gen_regs.fm_fifo_watermark |watermark_93 | 18| |1694 | \gen_regs.packet_capture |pkt_capture_regs__parameterized1 | 737| |1695 | Capture_Control_reg |ipbus_reg_v__46 | 34| |1696 | Capture_status_reg |ipbus_syncreg_v__88 | 22| |1697 | rsync |syncreg_r_101 | 20| |1698 | Header_0_reg |ipbus_syncreg_v__89 | 46| |1699 | rsync |syncreg_r_100 | 44| |1700 | Header_1_reg |ipbus_syncreg_v__90 | 49| |1701 | rsync |syncreg_r_99 | 47| |1702 | Header_2_reg |ipbus_syncreg_v__91 | 49| |1703 | rsync |syncreg_r_98 | 47| |1704 | trailer_0_reg |ipbus_syncreg_v__92 | 49| |1705 | rsync |syncreg_r_97 | 47| |1706 | trailer_1_reg |ipbus_syncreg_v__93 | 49| |1707 | rsync |syncreg_r_96 | 47| |1708 | pkt_count_reg |ipbus_syncreg_v__94 | 49| |1709 | rsync |syncreg_r_95 | 47| |1710 | \gen_regs.stage_fifo_watermark |watermark_94 | 35| |1711 | input_mux |bulk_channel_mux | 174| |1712 | ttc_input |ttc_info | 428| |1713 | cttc_crc |osum_crc9d32__7 | 43| |1714 | bkpln_rst_pulse_stretcher |pulse_stretch__parameterized1 | 23| |1715 | fabric |ipbus_fabric_sel__parameterized0 | 1| |1716 | tob_processor_0 |tob_processor | 5651| |1717 | input_mux |channel_mux | 553| |1718 | event_builder_0 |ev_builder | 2604| |1719 | state_reg |vDFF | 6| |1720 | timeout |tob_timeout | 65| |1721 | event_header_crc |event_hdr_crc9__3 | 100| |1722 | hdr_chk_crc |osum_crc9d32_89 | 85| |1723 | event_trailer_crc |event_trailer_CRC20__1 | 298| |1724 | crc_block |flx_CRC_88 | 298| |1725 | chan_trailer_crc |event_trailer_CRC20 | 298| |1726 | crc_block |flx_CRC | 298| |1727 | evnt_trailer_err_map |trailer_map__1 | 56| |1728 | dbg_trailer_err_map |trailer_map | 55| |1729 | wdog_timer |watchdog | 51| |1730 | channel_header_crc |hdr_in_crc9 | 112| |1731 | hdr_chk_crc |osum_crc9d32 | 62| |1732 | dbg_crc20_gen |CRC__parameterized3 | 406| |1733 | dbg_crc9_gen |CRC__14 | 55| |1734 | \gen_reg.status_regs |tob_proc_regs | 2376| |1735 | Event_fifo_control_reg |ipbus_reg_v__24 | 33| |1736 | event_fifo_fill_level_reg |ipbus_syncreg_v__44 | 49| |1737 | rsync |syncreg_r_87 | 47| |1738 | debug_fifo_fill_level_reg |ipbus_syncreg_v__45 | 49| |1739 | rsync |syncreg_r_86 | 47| |1740 | tob_proc_status |ipbus_syncreg_v__46 | 31| |1741 | rsync |syncreg_r_85 | 29| |1742 | Full_mode_control_reg |ipbus_reg_v__26 | 33| |1743 | stage_fifo_fill_level_reg |ipbus_syncreg_v__48 | 49| |1744 | rsync |syncreg_r_84 | 47| |1745 | fullmode_fifo_fill_level_reg |ipbus_syncreg_v__49 | 41| |1746 | rsync |syncreg_r_83 | 39| |1747 | fm_L1id_reg |ipbus_syncreg_v__50 | 49| |1748 | rsync |syncreg_r_82 | 47| |1749 | tob_staging_thresholds_reg |ipbus_reg_v__27 | 33| |1750 | tob_staging_control_reg |ipbus_reg_v__28 | 33| |1751 | Tob_stage_fifo_status_reg |ipbus_syncreg_v__51 | 22| |1752 | rsync |syncreg_r_81 | 20| |1753 | Tob_stage_busy_Count_reg |ipbus_syncreg_v__52 | 49| |1754 | rsync |syncreg_r_80 | 47| |1755 | Tob_stage_xoff_Count_reg |ipbus_syncreg_v__53 | 49| |1756 | rsync |syncreg_r_79 | 47| |1757 | Tob_timeout_reg |ipbus_ctrlreg_v__parameterized0 | 97| |1758 | error_count_register |ipbus_syncreg_v__54 | 38| |1759 | rsync |syncreg_r_78 | 36| |1760 | packet_capture |pkt_capture_regs | 671| |1761 | Capture_Control_reg |ipbus_reg_v_63 | 35| |1762 | Capture_status_reg |ipbus_syncreg_v_64 | 24| |1763 | rsync |syncreg_r_77 | 21| |1764 | Header_0_reg |ipbus_syncreg_v_65 | 47| |1765 | rsync |syncreg_r_76 | 44| |1766 | Header_1_reg |ipbus_syncreg_v_66 | 110| |1767 | rsync |syncreg_r_75 | 107| |1768 | Header_2_reg |ipbus_syncreg_v_67 | 51| |1769 | rsync |syncreg_r_74 | 48| |1770 | pkt_count_reg |ipbus_syncreg_v_68 | 85| |1771 | rsync |syncreg_r_73 | 82| |1772 | trailer_0_reg |ipbus_syncreg_v_69 | 50| |1773 | rsync |syncreg_r_72 | 47| |1774 | trailer_1_reg |ipbus_syncreg_v_70 | 50| |1775 | rsync |syncreg_r_71 | 47| |1776 | watchdog_control_reg |ipbus_reg_v__31 | 33| |1777 | wdog_threshold_reg |ipbus_ctrlreg_v__parameterized1 | 65| |1778 | watchdog_overflow_count_reg |ipbus_syncreg_v__55 | 33| |1779 | rsync |syncreg_r_62 | 31| |1780 | wdog_overflow_counter |edge_error_counter__parameterized1 | 28| |1781 | Event_fifo_reset_reg |ipbus_reg_v__52 | 136| |1782 | Tob_staging_fifo_resets_reg |ipbus_reg_v_56 | 100| |1783 | debug_fifo_watermark |watermark | 34| |1784 | event_fifo_watermark |watermark_57 | 34| |1785 | fm_fifo_watermark |watermark_58 | 34| |1786 | full_mode_status_reg |ipbus_syncreg_v__103 | 61| |1787 | rsync |syncreg_r | 57| |1788 | stage_fifo_watermark |watermark_59 | 34| |1789 | tob_proc_reset_reg |ipbus_reg_v_60 | 102| |1790 | tob_stage_busy_counter |threshold_counter | 91| |1791 | tob_stage_xoff_counter |threshold_counter_61 | 90| |1792 | chan_in_gen |dummy_chan_in__1 | 17| |1793 | reset_top |system_top_reset | 83| |1794 | phy_reset |system_top_reset__parameterized1 | 82| |1795 | fm_interface_1 |Full_Mode_Tx__xdcDup__1 | 2586| |1796 | chan_0 |FM_channel__xdcDup__1 | 876| |1797 | u5 |FMchannelTXctrl | 371| |1798 | crc20_0 |CRC__parameterized4_53 | 246| |1799 | eop_space_trig |pulse_pdxx_pwxx_54 | 4| |1800 | sop_space_trig |pulse_pdxx_pwxx_55 | 13| |1801 | u7 |FIFO34to34b__xdcDup__1 | 42| |1802 | reset_timer |rst_tmr | 127| |1803 | ram0 |FM_example_emuram__xdcDup__1 | 88| |1804 | ctl0 |FM_example_FIFOctrl | 95| |1805 | axi_interface |fm_axi_51 | 4| |1806 | data_mux |tx_data_mux_52 | 34| |1807 | chan_1 |FM_channel__parameterized1__xdcDup__1 | 895| |1808 | u5 |FMchannelTXctrl__4 | 386| |1809 | crc20_0 |CRC__parameterized4_46 | 246| |1810 | eob_space_trig |pulse_pdxx_pwxx_47 | 3| |1811 | eop_space_trig |pulse_pdxx_pwxx_48 | 4| |1812 | sob_space_trig |pulse_pdxx_pwxx_49 | 11| |1813 | sop_space_trig |pulse_pdxx_pwxx_50 | 8| |1814 | u7 |FIFO34to34b__xdcDup__2 | 42| |1815 | reset_timer |rst_tmr__4 | 127| |1816 | data_mux |tx_data_mux__4 | 35| |1817 | axi_interface |fm_axi__4 | 6| |1818 | ram0 |FM_example_emuram__xdcDup__2 | 88| |1819 | ctl0 |FM_example_FIFOctrl__4 | 95| |1820 | u0 |FullModeTransceiver__xdcDup__1 | 798| |1821 | \g_gt_channel[0].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__4 | 247| |1822 | sync_CPLLLOCK |FullModeTransceiver_sync_block_39 | 10| |1823 | sync_RXRESETDONE |FullModeTransceiver_sync_block_40 | 6| |1824 | sync_data_valid |FullModeTransceiver_sync_block_41 | 8| |1825 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_42 | 8| |1826 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_43 | 6| |1827 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_44 | 6| |1828 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_45 | 6| |1829 | \g_gt_channel[1].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM | 247| |1830 | sync_CPLLLOCK |FullModeTransceiver_sync_block_32 | 10| |1831 | sync_RXRESETDONE |FullModeTransceiver_sync_block_33 | 6| |1832 | sync_data_valid |FullModeTransceiver_sync_block_34 | 8| |1833 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_35 | 8| |1834 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_36 | 6| |1835 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_37 | 6| |1836 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_38 | 6| |1837 | txresetfsm_i |FullModeTransceiver_TX_STARTUP_FSM | 230| |1838 | sync_QPLLLOCK |FullModeTransceiver_sync_block_26 | 13| |1839 | sync_TXRESETDONE |FullModeTransceiver_sync_block_27 | 6| |1840 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_28 | 8| |1841 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_29 | 6| |1842 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_30 | 6| |1843 | sync_tx_fsm_reset_done_int |FullModeTransceiver_sync_block_31 | 6| |1844 | busy_stretcher |pulse_stretch__parameterized7_25 | 9| |1845 | fm_interface_2 |Full_Mode_Tx | 2585| |1846 | chan_0 |FM_channel | 876| |1847 | u5 |FMchannelTXctrl__3 | 371| |1848 | crc20_0 |CRC__parameterized4_22 | 246| |1849 | eop_space_trig |pulse_pdxx_pwxx_23 | 4| |1850 | sop_space_trig |pulse_pdxx_pwxx_24 | 13| |1851 | u7 |FIFO34to34b__xdcDup__3 | 42| |1852 | reset_timer |rst_tmr__3 | 127| |1853 | ram0 |FM_example_emuram__xdcDup__3 | 88| |1854 | ctl0 |FM_example_FIFOctrl__3 | 95| |1855 | axi_interface |fm_axi | 4| |1856 | data_mux |tx_data_mux | 34| |1857 | chan_1 |FM_channel__parameterized1 | 895| |1858 | u5 |FMchannelTXctrl__2 | 386| |1859 | crc20_0 |CRC__parameterized4 | 246| |1860 | eob_space_trig |pulse_pdxx_pwxx | 3| |1861 | eop_space_trig |pulse_pdxx_pwxx_19 | 4| |1862 | sob_space_trig |pulse_pdxx_pwxx_20 | 11| |1863 | sop_space_trig |pulse_pdxx_pwxx_21 | 8| |1864 | u7 |FIFO34to34b | 42| |1865 | reset_timer |rst_tmr__2 | 127| |1866 | data_mux |tx_data_mux__2 | 35| |1867 | axi_interface |fm_axi__2 | 6| |1868 | ram0 |FM_example_emuram | 88| |1869 | ctl0 |FM_example_FIFOctrl__2 | 95| |1870 | u0 |FullModeTransceiver | 798| |1871 | \g_gt_channel[0].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__2 | 247| |1872 | sync_CPLLLOCK |FullModeTransceiver_sync_block_12 | 10| |1873 | sync_RXRESETDONE |FullModeTransceiver_sync_block_13 | 6| |1874 | sync_data_valid |FullModeTransceiver_sync_block_14 | 8| |1875 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_15 | 8| |1876 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_16 | 6| |1877 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_17 | 6| |1878 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_18 | 6| |1879 | \g_gt_channel[1].rxresetfsm_i |FullModeTransceiver_RX_STARTUP_FSM__3 | 247| |1880 | sync_CPLLLOCK |FullModeTransceiver_sync_block_5 | 10| |1881 | sync_RXRESETDONE |FullModeTransceiver_sync_block_6 | 6| |1882 | sync_data_valid |FullModeTransceiver_sync_block_7 | 8| |1883 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_8 | 8| |1884 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_9 | 6| |1885 | sync_rx_fsm_reset_done_int |FullModeTransceiver_sync_block_10 | 6| |1886 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_11 | 6| |1887 | txresetfsm_i |FullModeTransceiver_TX_STARTUP_FSM__2 | 230| |1888 | sync_QPLLLOCK |FullModeTransceiver_sync_block | 13| |1889 | sync_TXRESETDONE |FullModeTransceiver_sync_block_0 | 6| |1890 | sync_mmcm_lock_reclocked |FullModeTransceiver_sync_block_1 | 8| |1891 | sync_run_phase_alignment_int |FullModeTransceiver_sync_block_2 | 6| |1892 | sync_time_out_wait_bypass |FullModeTransceiver_sync_block_3 | 6| |1893 | sync_tx_fsm_reset_done_int |FullModeTransceiver_sync_block_4 | 6| |1894 | busy_stretcher |pulse_stretch__parameterized7 | 9| |1895 | Bulk_0_64_32 |packet_fifo__xdcDup__1 | 173| |1896 | Bulk_1_64_32 |packet_fifo__xdcDup__2 | 173| |1897 | Bulk_2_64_32 |packet_fifo__xdcDup__3 | 173| |1898 | pp_out_fifo_6432 |packet_fifo | 173| |1899 | spi_pwr |reset_count | 13| +------+-------------------------------------------------------------------------------------+---------------------------------------------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:09:38 ; elapsed = 00:12:16 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 118 ; free virtual = 18766 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 6833 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:08:49 ; elapsed = 00:11:23 . Memory (MB): peak = 3304.289 ; gain = 761.156 ; free physical = 1424 ; free virtual = 20074 Synthesis Optimization Complete : Time (s): cpu = 00:09:43 ; elapsed = 00:12:21 . Memory (MB): peak = 3304.289 ; gain = 1016.684 ; free physical = 1444 ; free virtual = 20074 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3304.289 ; gain = 0.000 ; free physical = 1390 ; free virtual = 20020 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4900 Unisim elements for replacement WARNING: [Netlist 29-432] The IBUFG primitive 'ipbus_blk/clkin1_buf' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/bufg_clkin1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout1_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout2_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'ipbus_blk/ipbus/example_clocks/clock_generator/clkout3_buf' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. ipbus_blk/clkin1_buf Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. backplane/reset_buf Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design. INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 8 OBUFs to IO ports without IO buffers. WARNING: [Constraints 18-549] Could not create 'DRIVE' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'DRIVE' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'SLEW' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. INFO: [Chipscope 16-324] Core: ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0 UUID: 72643ffe-b86c-5856-9378-79d72128bd92 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ce_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rnw_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rpn_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3304.289 ; gain = 0.000 ; free physical = 1307 ; free virtual = 19959 INFO: [Project 1-111] Unisim Transformation Summary: A total of 826 instances were transformed. (MUXCY,XORCY) => CARRY4: 18 instances BUFGCE => BUFGCTRL: 4 instances FD => FDRE: 248 instances FDR => FDRE: 443 instances IOBUF => IOBUF (IBUF, OBUFT): 24 instances MULT_AND => LUT2: 27 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 12 instances RAM64M => RAM64M (RAMD64E(x4)): 40 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances SRL16 => SRL16E: 2 instances INFO: [Common 17-83] Releasing license: Synthesis 2052 Infos, 1267 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:10:29 ; elapsed = 00:13:45 . Memory (MB): peak = 3304.289 ; gain = 1042.004 ; free physical = 1505 ; free virtual = 20157 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3304.289 ; gain = 0.000 ; free physical = 1505 ; free virtual = 20157 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/synth_1/top_rod_efex.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 3304.289 ; gain = 0.000 ; free physical = 1493 ; free virtual = 20161 INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_synth.rpt -pb top_rod_efex_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Fri Sep 10 00:16:16 2021...