<!-- ROD TOB processor address table -->
<!-- Defines ROD_tob_processor register block container -->
<node fwinfo="endpoint;width=5">

  <!-- <node id="TobProc" address="0x0" description="TOB processor Registers"> -->
    
	<node id="event_fifo_control" permission="rw"   address="0x0" description="event fifo control bits" fwinfo="endpoint;width=0">
		<node id="Busy_enable" 	mask="0x1" description="Enable action on busy threshold exceeded" />
		<node id="Xoff_enable"	mask="0x2" description="Enable action on xoff threshold exceeded" />
		</node>
		
	<node id="Event_fifo_reset" permission="w"   address="0x1" description="TOB fifo reset bits(pulse reg)" fwinfo="endpoint;width=0">
		<node id="Event_fifo_reset" 		mask="0x1" description="Reset and purge the event fifo" />
		<node id="Event_watermark_reset"	mask="0x2" description="Reset the event fifo watermark" />
		<node id="Debug_fifo_reset" 		mask="0x10" description="Reset and purge the debug fifo" />
		<node id="Debug_watermark_reset"	mask="0x20" description="Reset the debug fifo watermark" />
		<node id="Stage_fifo_reset"         mask="0x40" description="Reset the stage fifo" />
		<node id="Stage_watermark_reset"    mask="0x80" description="Reset the stage fifo watermark" />
		<node id="fm_watermark_reset"       mask="0x100" description="Reset the stage fifo watermark" />
		<node id="fm_status_reset"          mask="0x200" description="Reset the full mode status reg" />
		</node>	
		
	<node id="Event_fifo_fill_level"  	permission="r"  address="0x2" description="Event fifo fill level" fwinfo="endpoint;width=0">
		<node id="Event_fifo_level" 		mask="0x0000FFFF" description="TOB fifo current level" />
		<node id="Event_fifo_watermark" 	mask="0xFFFF0000" description="TOB fifo watermark" />
	</node>	
	
	<node id="Debug_fifo_fill_level"  	permission="r"  address="0x3" description="Debug fifo fill level" fwinfo="endpoint;width=0">
		<node id="Debug_fifo_level" 		mask="0x0000FFFF" description="Debug fifo current level" />
		<node id="Debug_fifo_watermark" 	mask="0xFFFF0000" description="Debug fifo watermark" />
	</node>	
	
	<node id="Tob_proc_status"  	permission="r"  address="0x4" description="Tob Processor Status" fwinfo="endpoint;width=0">
		<node id="Current_chan" 		    mask="0x000000FF" description="Channel being processed" />
		<node id="Current_state"	        mask="0x0000FF00" description="Processor microcode state" />
		<node id="Header_mark" 		        mask="0x00010000" description="Header mark coming from input mux" />
		<node id="Header_fifo_valid"	    mask="0x00020000" description="An Event Header is in the Header FIFO" />
		<node id="Header_crc_error"	        mask="0x00040000" description="Header crc error mark from input mux" />
		<node id="TTC_crc_error"	        mask="0x00080000" description="TTC crc error mark out of fifo" />
	</node>	
		
		
	<node id="Full_mode_control"  	permission="rw"  address="0x5" description="controls for associated full mode output" fwinfo="endpoint;width=0">
		<node id="Soft_reset" 				mask="0x1" description="soft reset the interface - must be set back to zero" />
		<node id="Enable_playout" 			mask="0x2" description="turn on playout memory" />
		<node id="Set_busy" 			    mask="0x4" description="set busy output" />	
		<node id="LEMO" 	  		    	mask="0x8" description="set LEMO output" />	
		<node id="flx_bp_enable" 	  		mask="0x10" description="enable felix backpressure" />	
	</node>	
	
	<node id="Full_mode_status"  	permission="r"  address="0x6" description="status of associated full mode output" fwinfo="endpoint;width=0">	
		<node id="QPLL_lock" 	   			mask="0x1" description="QPLL is locked" />
		<node id="MGT_reset_done" 		    mask="0x2" description="Reset is done" />	
		<node id="Fifo_full" 				mask="0x4" description="sticky bit that needs a reset" />
		<node id="Fifo_fill_level" 			mask="0xFF0000" description="FM tx fifo fill level" />
		<node id="packet_meter" 	        mask="0xFF000000" description="rolling packet counter" />
	</node>	
	
	<node id="Full_mode_L1ID"  	permission="r"  address="0x7" description="last L1ID sent from the Full Mode interface" fwinfo="endpoint;width=0"/>	
		
	
	
	<node id="TOB_Staging_fifo_level"  	permission="r"  address="0x8" description="Debug fifo fill level" fwinfo="endpoint;width=0">
		<node id="Stage_fifo_level" 		mask="0x0000FFFF" description="Debug fifo current level" />
		<node id="Stage_fifo_watermark" 	mask="0xFFFF0000" description="Debug fifo watermark" />
	</node>	
	
	<node id="Full_mode_fifo_level"  	permission="r"  address="0x9" description="Debug fifo fill level" fwinfo="endpoint;width=0">
		<node id="FM_fifo_level" 		mask="0x0000FFFF" description="Debug fifo current level" />
		<node id="FM_fifo_watermark" 	mask="0xFFFF0000" description="Debug fifo watermark" />
	</node>	
	
	
	<!--   <TOB Staging FIFO Status and Control>  -->
	<node id="Tob_staging_fifo_thresholds" permission="rw"   address="0xA" description="TOB output fifo busy thresholds" fwinfo="endpoint;width=0">
		<node id="Busy_threshold" 	mask="0x0000FFFF" description="Enable action on busy threshold exceeded" />
		<node id="Xoff_threshold"	mask="0xFFFF0000" description="Enable action on xoff threshold exceeded" />
		</node>
		
	<node id="Tob_staging_fifo_control" permission="rw"   address="0xB" description="TOB fifo control bits" fwinfo="endpoint;width=0">
		<node id="Busy_enable" 	mask="0x1" description="Enable action on busy threshold exceeded" />
		<node id="Xoff_enable"	mask="0x2" description="Enable action on xoff threshold exceeded" />
		<node id="Force_busy"	mask="0x10" description="Force activation of Busy to Felix" />
		</node>	
		
	<node id="Tob_staging_fifo_resets" permission="rw"   address="0xC" description="TOB staging fifo reset bits(pulse reg)" fwinfo="endpoint;width=0">
		<node id="stage_fifo_reset" 	mask="0x1" description="Reset and purge the tob fifo" />
		<node id="stage_busy_thresh_reset"	mask="0x2" description="Reset the tob busy threshold exceeded count" />
		<node id="stage_xoff_thresh_reset"	mask="0x4" description="Reset the tob xoff threshold exceeded count" />
		</node>	
		
	<node id="Tob_staging_fifo_status" permission="r"   address="0xD" description="TOB fifo status bits" fwinfo="endpoint;width=0">
		<node id="Stage_fifo_full" mask="0x1" description="TOB fifo is currently overrun" />
		<node id="Stage_fifo_busy"	mask="0x2" description="TOB fifo level is currently above the busy threshold" />
		<node id="Stage_fifo_xoff"	mask="0x4" description="TOB fifo level is currently above the xoff threshold" />
	</node>	
				
	
	<node id="Tob_staging_fifo_busy_Count"  	permission="r"  address="0xE" description="TOB Staging FIFO Busy Threshold Exceeded Counter" fwinfo="endpoint;width=0"/>
    <node id="Tob_staging_fifo_xoff_Count"  	permission="r"  address="0xF" description="TOB Staging FIFO Busy Threshold Exceeded Counter" fwinfo="endpoint;width=0"/>

	<node id="Tob_timeout_values" permission="rw"   address="0x10" description="TOB timeout values" fwinfo="endpoint;width=0">
		<node id="timeout_1"        mask="0x0000FFFF" description="Timeout waiting for first channel" />
		<node id="timeout_n"	    mask="0xFFFF0000" description="Timeout waiting for subsequent channels" />
	</node>	
	
	<!--   <address "0x11" is also used by the register above>  -->
	
	<node id="Tob_error_count" permission="r"   address="0x12" description="TOB timeout values" fwinfo="endpoint;width=0">
		<node id="crc9_count"       mask="0x000000FF" description="CRC9 header errors" />
		<node id="crc20_count"	    mask="0x0000FF00" description="CRC20 payload errors" />
		<node id="crc20_err_chan"	mask="0x00FF0000" description="last channel with CRC20 error" />
	</node>	
	
	<node id="Tob_error_reset" permission="w"   address="0x13" description="Reset Error Bits" fwinfo="endpoint;width=0">
		<node id="clr_crc9_count"         mask="0x00000001" description="Clear the CRC9 counter" />
		<node id="clr_crc20_count"	      mask="0x00000002" description="Clear the CRC20 counter" />
		<node id="clr_w_dog_count"	      mask="0x00000004" description="Clear the Watchdog incident counter" />
	</node>	
	
	
	<node id="Watchdog_control" permission="rw"   address="0x14" description="Watchdog timer control" fwinfo="endpoint;width=0">
		<node id="disable"        mask="0x00000001" description="Disable watchdog timer" />
	</node>	
	
	<node id="Watchdog_threshold_value" permission="rw"   address="0x15" description="Watchdog overflow threshold" fwinfo="endpoint;width=0">
		<node id="threshold"     mask="0x0000FFFF" description="Number of processor clocks allocated to one complete event before timeout" />
	</node>	
	
	<node id="Watchdog_Overflow_Count"  permission="r"  address="0x16" description="Number of Watchdog Resets" fwinfo="endpoint;width=0"/>
	
		
	<node id="pkt_capture_regs" address="0x18" description="registers for all channels" module="file://L1CaloHubRodPktCaptureRegisters.xml"/>
	

	
</node>
