*** Running vivado with args -log top_rod_jfex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_jfex.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_jfex.tcl -notrace Command: link_design -top top_rod_jfex -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0.dcp' for cell 'ILA_axi_chan_12' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/backplane_control_ila.dcp' for cell 'bkpln_control_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.dcp' for cell 'top_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/pp_ctrl_vio/pp_ctrl_vio.dcp' for cell 'vio_pp_ctrl' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_wconv.dcp' for cell 'backplane/ila_dwidth_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/dwidth_convert/dwidth_convert.dcp' for cell 'backplane/width_conver_s12_l1' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.dcp' for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_jfex_aurora_low.dcp' for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'backplane/combined_ttc/ila_rx2_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'backplane/combined_ttc/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.dcp' for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila.dcp' for cell 'event_builder/bulk_0/bulkl_proc_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/chan_map_ila.dcp' for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/aurora_fifo_out_ila.dcp' for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.dcp' for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/aurora_fifo_in_ila.dcp' for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila.dcp' for cell 'event_builder/tob_processor_0/input_mux_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/default_reg_ila.dcp' for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.dcp' for cell 'fm_interface_1/clk_blk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'fm_interface_1/chan_0/L1ID_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode.dcp' for cell 'fm_interface_1/chan_0/ila_fm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'fm_interface_1/chan_0/vio_fm_reset' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'fm_interface_1/chan_0/ram0/RAM_0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'fm_interface_1/chan_0/u7/FIFO34b' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/axi_ila_1.dcp' for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/debug_ila_ed1.dcp' for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3074.992 ; gain = 0.000 ; free physical = 7358 ; free virtual = 27360 INFO: [Netlist 29-17] Analyzing 23124 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-549] Could not create 'SLEW' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DRIVE' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'DRIVE' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 INFO: [Chipscope 16-324] Core: ILA_axi_chan_12 UUID: dcdeb61e-6ff2-53ed-912b-8720e2c6f786 INFO: [Chipscope 16-324] Core: ILA_axi_chan_13 UUID: 545886ab-3467-5aa7-ab8e-c2b5c112b031 INFO: [Chipscope 16-324] Core: ILA_axi_chan_14 UUID: 3ac06453-4ad2-5c3b-9899-d2afc28cd875 INFO: [Chipscope 16-324] Core: ILA_axi_chan_15 UUID: 0def4d34-0993-5355-a23b-021ba3122909 INFO: [Chipscope 16-324] Core: ILA_axi_chan_4 UUID: 243986b7-10ae-5076-b31e-1a5deb5ff3c8 INFO: [Chipscope 16-324] Core: ILA_axi_chan_5 UUID: e6ea15cd-0e46-5889-bdc8-03e3748b4bf9 INFO: [Chipscope 16-324] Core: ILA_axi_chan_6 UUID: 20f4843a-ad73-5961-871c-7eb485b4f283 INFO: [Chipscope 16-324] Core: ILA_axi_chan_7 UUID: 1e2160fa-1e88-5cff-8e4b-c4c62d282b50 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l1/debug1.jfex_low_ila UUID: 65d4eedf-565a-5bee-bf36-4362dc7788c7 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l2/debug1.jfex_low_ila UUID: b2b12b08-a8e0-5271-99d0-0e6b7df3f98c INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l3/debug1.jfex_low_ila UUID: 58302d4d-07b7-51d5-9232-3595a0a49523 INFO: [Chipscope 16-324] Core: backplane/aurora_s13_l4/debug1.jfex_low_ila UUID: 891aa488-6d6c-50b0-96af-e020ae7b0be1 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l1/debug1.jfex_low_ila UUID: 04cd6e7b-99da-55a0-b0e0-b013b12358d5 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l2/debug1.jfex_low_ila UUID: a96fbe40-17e9-5834-9b96-53e8ed51c472 INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l3/debug1.jfex_low_ila UUID: b2cc214f-f3f7-5971-826c-370224df996d INFO: [Chipscope 16-324] Core: backplane/aurora_s4_l4/debug1.jfex_low_ila UUID: 065f8364-c5d0-5df8-a4e1-cc50acf2f4b0 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l1/debug1.jfex_low_ila UUID: 6d6db0f5-ca52-5ac5-a98f-d2b4e2dbf366 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l2/debug1.jfex_low_ila UUID: 42142ce3-3551-5822-b2cc-efd714d41dd1 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l3/debug1.jfex_low_ila UUID: d30a25d7-ad28-5360-8429-663c00857183 INFO: [Chipscope 16-324] Core: backplane/aurora_s9_l4/debug1.jfex_low_ila UUID: f93e8422-449b-5731-9968-7c1265d0ef9a INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv UUID: a9367127-e949-5f06-9c24-f9d2193076cd INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s13_l2 UUID: b9386b0a-ea93-5920-aa7f-bd9910bf8036 INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s9_l1 UUID: 3f7bd968-bdec-5070-86ca-655cc56e294c INFO: [Chipscope 16-324] Core: backplane/ila_dwidth_conv_s9_l3 UUID: a3f79918-b294-52f3-bede-916493340664 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_RO_ctrl_inst UUID: 76a3beb1-890b-57f1-8968-8c8b4f7e3dd4 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b INFO: [Chipscope 16-324] Core: bkpln_control_ila UUID: e5321dce-5940-5962-94e8-6db7829555a0 INFO: [Chipscope 16-324] Core: event_builder/bulk_0/bulkl_proc_probe UUID: 7d9dc169-40d5-56ff-9a38-42ad7dd0b67d INFO: [Chipscope 16-324] Core: event_builder/bulk_1/bulkl_proc_probe UUID: 48639c55-d7f5-5b3f-bf8a-c3e17dffdced INFO: [Chipscope 16-324] Core: event_builder/bulk_2/bulkl_proc_probe UUID: f79c214c-778a-503c-82e0-558ccd7036de INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila UUID: 7293eb51-4970-503e-beee-62947dc9fd3b INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio UUID: 9feffab9-d8c8-5c84-80c3-bf2cf1318f87 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila UUID: b9fc1ed3-d8de-568a-bb5b-944bc2ede627 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila UUID: ad3f5b40-d484-5a88-8770-26b33ec59661 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila UUID: 2edb69e1-0b10-58cc-a5f3-44f0ab14bd74 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio UUID: c2c1ce07-4536-5363-8562-52d9d6a7c8f9 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila UUID: 49bdef97-4b31-59f0-8f8f-efe2c766df88 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila UUID: 38118b7f-1714-5158-a7d1-eb1b23c9d15e INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila UUID: d58c791c-90c5-5326-aee6-f8e7df62bdf8 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio UUID: 5add6678-6d2c-5a32-85f4-4dfb01dd4c8a INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila UUID: 8a2cc330-5831-55eb-9304-8e31e3065166 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila UUID: 09a6304d-b68d-52b7-96b3-c94d877508b6 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila UUID: 9a9c1655-46ca-5d45-ac44-9d2795e43faa INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio UUID: 716cabb2-a7d1-502b-864c-531925e15c65 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila UUID: 51bedd17-229e-5503-9f13-68015ea4398f INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila UUID: 3dfe948f-e8e1-5109-99ad-b55b5352269a INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila UUID: f2dacd4d-90ac-5961-a53d-619bfee64cdf INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio UUID: 7a22ce6a-0cfe-5884-8274-9a8c29f956b1 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila UUID: 0f381770-7687-5ee1-b02d-be51f8868775 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila UUID: b8809af5-28d1-5d4e-8a13-03533d4b2503 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila UUID: 7fd0677d-e6bf-5b61-aed4-f8dba0489f87 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio UUID: 77106ad3-b237-593f-864b-a17b4b12fbd2 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila UUID: 0fabbc06-76f2-533c-ad08-a5b2c20e5954 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila UUID: f0474686-58b4-5a5f-9b69-2591b61a2403 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila UUID: ec779436-0c2d-5949-85d4-1344ef5d1ab4 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio UUID: 06ee865a-842e-5e21-aa50-0e1b99aae73d INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila UUID: b69c8210-f4cf-5831-8503-72bbbb8c3540 INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila UUID: e432efce-dd18-5a40-a618-8ce6e622c8cf INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila UUID: 6828f53b-6d9d-5c6a-b964-f8b861f8200d INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio UUID: 3867c47c-0568-5173-89f4-394ab6b60e8a INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila UUID: f30ca6de-eb22-52d4-9850-cd0004597f0b INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila UUID: 027a0038-1ad0-58c3-94d9-f18ae6cc7b1e INFO: [Chipscope 16-324] Core: event_builder/fifo_layer/gen_reg.channel_map_ila UUID: 86f9fa1d-5c4c-58ce-93e2-f78484960244 INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_event_fifo UUID: 2d4141be-dbbe-5502-9616-cd358067f2ea INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila UUID: 1dd88742-1c2c-500e-b484-0986411f857c INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/input_mux_ila UUID: b512077d-1da3-504a-9240-4076ceba8348 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace UUID: 41764212-905a-5c60-8d6d-918cccb1eecb INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_ed_dbg.ila_ed UUID: f1f516b8-d4da-58f4-85cb-c9cc02198bcd INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/ila_fm UUID: 6d2436f5-9843-5197-8e19-cddbe1593602 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/vio_fm_reset UUID: 2e7b6e8a-28c2-522f-b319-a31f8d50741a INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace UUID: 45150629-1b2c-59ce-a3a0-0bee13c7bbff INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/ila_ed_dbg.ila_ed UUID: 668cfd74-38ce-581d-b1a5-0cf5fae2d424 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/ila_fm UUID: f7690143-a9e0-554d-977a-d2f37b0258d0 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/vio_fm_reset UUID: f793cc7a-6b74-5a26-9770-d018214fd2d5 INFO: [Chipscope 16-324] Core: fm_interface_2/u0/ila_resetfsm UUID: c10d06e5-8b28-51b9-aae4-8af94262c1bd INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 INFO: [Chipscope 16-324] Core: vio_pp_ctrl UUID: c06c8567-7633-5ee1-9cdc-7e2cadaf54d2 Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'bkpln_control_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'bkpln_control_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc] for cell 'bkpln_control_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc] for cell 'bkpln_control_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/axi_trace_dbg.fm_axi_trace/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/axi_trace_dbg.fm_axi_trace/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.channel_fifo_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.calo_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_out_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch0/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch1/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch2/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/ch3/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/chan_dbg.tob_fifo_in_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/fifo_layer/gen_reg.channel_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/pp_ctrl_vio/pp_ctrl_vio.xdc] for cell 'vio_pp_ctrl' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/pp_ctrl_vio/pp_ctrl_vio.xdc] for cell 'vio_pp_ctrl' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_12/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_12/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_13/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_13/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_14/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_14/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_15/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_15/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_4/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_5/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_5/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_7/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_7/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_12/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_12/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_13/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_13/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_14/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_14/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_15/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_15/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_4/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_5/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_5/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_7/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_7/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_7series'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_7series/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_7series'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_7series/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1281] Could not find module 'vio_7series'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/vio_7series/vio_7series.xdc will not be read for this module. Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s13_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s4_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l1/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l2/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l3/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_jfex_aurora_low/ila_v6_2/constraints/ila.xdc] for cell 'backplane/aurora_s9_l4/debug1.jfex_low_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s13_l2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l1/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/ila_wconv/ila_v6_2/constraints/ila.xdc] for cell 'backplane/ila_dwidth_conv_s9_l3/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] get_clocks: Time (s): cpu = 00:00:47 ; elapsed = 00:00:41 . Memory (MB): peak = 4831.910 ; gain = 1124.074 ; free physical = 5729 ; free virtual = 25744 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249500 which will be rounded to 0.250 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/rod_top.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc] WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l2/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l3/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s12_l4/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l1/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/aurora_1ln_rx_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc:65] get_pins: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5754.840 ; gain = 922.930 ; free physical = 4855 ; free virtual = 24871 Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/jfex_backplane_24ch.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc:34] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/wiz_experiment.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_jfex/xdc/wiz_experiment.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] get_pins: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5908.840 ; gain = 90.000 ; free physical = 4700 ; free virtual = 24716 Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l2/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx/aurora_1ln_rx_clocks.xdc] for cell 'backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch15/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch17/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch20/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch21/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ce_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rnw_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rpn_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6036.844 ; gain = 0.000 ; free physical = 6053 ; free virtual = 26071 INFO: [Project 1-111] Unisim Transformation Summary: A total of 9093 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 8544 instances IOBUF => IOBUF (IBUF, OBUFT): 25 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 44 instances RAM64M => RAM64M (RAMD64E(x4)): 376 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 104 instances 191 Infos, 201 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:05:24 ; elapsed = 00:06:04 . Memory (MB): peak = 6036.844 ; gain = 4206.531 ; free physical = 6053 ; free virtual = 26071 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design -directive Explore INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_LE expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6044.848 ; gain = 8.000 ; free physical = 6044 ; free virtual = 26062 Starting Cache Timing Information Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 14067d6d5 Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5600 ; free virtual = 25618 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5362 ; free virtual = 25412 Netlist sorting complete. Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.57 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5359 ; free virtual = 25409 Phase 1 Generate And Synthesize Debug Cores | Checksum: 205fb9951 Time (s): cpu = 00:03:18 ; elapsed = 00:05:32 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5357 ; free virtual = 25408 Phase 2 Retarget INFO: [Opt 31-138] Pushed 98 inverter(s) to 237 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1b371e942 Time (s): cpu = 00:04:04 ; elapsed = 00:06:18 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5780 ; free virtual = 25831 INFO: [Opt 31-389] Phase Retarget created 946 cells and removed 2346 cells INFO: [Opt 31-1021] In phase Retarget, 5430 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1729b7bcb Time (s): cpu = 00:04:20 ; elapsed = 00:06:34 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5780 ; free virtual = 25830 INFO: [Opt 31-389] Phase Constant propagation created 372 cells and removed 2953 cells INFO: [Opt 31-1021] In phase Constant propagation, 3828 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD12516) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. Phase 4 Sweep | Checksum: 189d3872e Time (s): cpu = 00:07:49 ; elapsed = 00:10:03 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5765 ; free virtual = 25815 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 12584 cells INFO: [Opt 31-1021] In phase Sweep, 46261 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 5 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 1b6021516 Time (s): cpu = 00:07:58 ; elapsed = 00:10:13 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5770 ; free virtual = 25820 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. INFO: [Opt 31-1021] In phase BUFG optimization, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1b6021516 Time (s): cpu = 00:08:05 ; elapsed = 00:10:20 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5770 ; free virtual = 25820 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: d8e99348 Time (s): cpu = 00:08:09 ; elapsed = 00:10:23 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5770 ; free virtual = 25820 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 3909 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 946 | 2346 | 5430 | | Constant propagation | 372 | 2953 | 3828 | | Sweep | 11 | 12584 | 46261 | | BUFG optimization | 0 | 1 | 2 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 3909 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5772 ; free virtual = 25822 Ending Logic Optimization Task | Checksum: 21c5d52e9 Time (s): cpu = 00:08:17 ; elapsed = 00:10:32 . Memory (MB): peak = 6044.848 ; gain = 0.000 ; free physical = 5772 ; free virtual = 25822 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.315 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst INFO: [Power 33-23] Power model is not available for DNA_PORT_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 431 BRAM(s) out of a total of 508 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 196 WE to EN ports Number of BRAM Ports augmented: 257 newly gated: 208 Total Ports: 1016 Ending PowerOpt Patch Enables Task | Checksum: 1c4b81a02 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5217 ; free virtual = 25269 Ending Power Optimization Task | Checksum: 1c4b81a02 Time (s): cpu = 00:05:09 ; elapsed = 00:04:37 . Memory (MB): peak = 7804.809 ; gain = 1759.961 ; free physical = 5579 ; free virtual = 25631 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 19a800479 Time (s): cpu = 00:01:03 ; elapsed = 00:01:04 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5548 ; free virtual = 25601 Ending Final Cleanup Task | Checksum: 19a800479 Time (s): cpu = 00:01:09 ; elapsed = 00:01:12 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5547 ; free virtual = 25599 Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69] all_fanout: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5107 ; free virtual = 25159 Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5111 ; free virtual = 25163 Ending Netlist Obfuscation Task | Checksum: 19a800479 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5111 ; free virtual = 25163 INFO: [Common 17-83] Releasing license: Implementation 247 Infos, 202 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:15:54 ; elapsed = 00:17:43 . Memory (MB): peak = 7804.809 ; gain = 1767.961 ; free physical = 5121 ; free virtual = 25174 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 5123 ; free virtual = 25175 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 7804.809 ; gain = 0.000 ; free physical = 4841 ; free virtual = 25123 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:32 ; elapsed = 00:03:35 . Memory (MB): peak = 7804.812 ; gain = 0.004 ; free physical = 4973 ; free virtual = 25133 INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_drc_opted.rpt -pb top_rod_jfex_drc_opted.pb -rpx top_rod_jfex_drc_opted.rpx Command: report_drc -file top_rod_jfex_drc_opted.rpt -pb top_rod_jfex_drc_opted.pb -rpx top_rod_jfex_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 7804.812 ; gain = 0.000 ; free physical = 4930 ; free virtual = 25091 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/RSTRAMARSTRAM (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/AS[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_LE expects both input and output buffering but the buffers are incomplete. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 22 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.16 . Memory (MB): peak = 7804.812 ; gain = 0.000 ; free physical = 4924 ; free virtual = 25085 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15895eab6 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.27 . Memory (MB): peak = 7804.812 ; gain = 0.000 ; free physical = 4923 ; free virtual = 25084 Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 7804.812 ; gain = 0.000 ; free physical = 4924 ; free virtual = 25085 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-461] A non-muxed BUFG 'backplane/user_clk_buf_i_2' is driven by another global buffer 'CLK_40_g_buffer'. Remove non-muxed BUFG if it is not desired. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137f4599f Time (s): cpu = 00:05:04 ; elapsed = 00:06:17 . Memory (MB): peak = 7824.363 ; gain = 19.551 ; free physical = 2725 ; free virtual = 22886 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 21580aefd Time (s): cpu = 00:07:24 ; elapsed = 00:08:40 . Memory (MB): peak = 9359.613 ; gain = 1554.801 ; free physical = 1976 ; free virtual = 22137 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 21580aefd Time (s): cpu = 00:07:27 ; elapsed = 00:08:43 . Memory (MB): peak = 9359.613 ; gain = 1554.801 ; free physical = 1973 ; free virtual = 22134 Phase 1 Placer Initialization | Checksum: 21580aefd Time (s): cpu = 00:07:28 ; elapsed = 00:08:45 . Memory (MB): peak = 9359.613 ; gain = 1554.801 ; free physical = 1962 ; free virtual = 22123 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1895ac42c Time (s): cpu = 00:08:14 ; elapsed = 00:09:33 . Memory (MB): peak = 9359.613 ; gain = 1554.801 ; free physical = 1757 ; free virtual = 21918 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 12646 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 3728 nets or cells. Created 1 new cell, deleted 3727 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-64] No nets found for fanout-optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-665] Processed cell event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0. 18 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 18 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 9589.996 ; gain = 0.000 ; free physical = 1717 ; free virtual = 21880 INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 9589.996 ; gain = 0.000 ; free physical = 1732 ; free virtual = 21896 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 1 | 3727 | 3728 | 0 | 1 | 00:00:12 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:04 | | Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 18 | 0 | 1 | 0 | 1 | 00:00:01 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 19 | 3727 | 3729 | 0 | 9 | 00:00:18 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1747d3eaa Time (s): cpu = 00:16:35 ; elapsed = 00:18:18 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1720 ; free virtual = 21883 Phase 2.2 Global Placement Core | Checksum: 1b7b3e582 Time (s): cpu = 00:17:38 ; elapsed = 00:19:21 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1676 ; free virtual = 21840 Phase 2 Global Placement | Checksum: 1b7b3e582 Time (s): cpu = 00:17:38 ; elapsed = 00:19:21 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1856 ; free virtual = 22019 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 14b9c01fa Time (s): cpu = 00:18:23 ; elapsed = 00:20:08 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1828 ; free virtual = 21992 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d743a18d Time (s): cpu = 00:19:43 ; elapsed = 00:21:30 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1774 ; free virtual = 21937 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1b01a83c3 Time (s): cpu = 00:19:48 ; elapsed = 00:21:36 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1772 ; free virtual = 21936 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1c3b0623b Time (s): cpu = 00:19:53 ; elapsed = 00:21:40 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1772 ; free virtual = 21935 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 267e8968b Time (s): cpu = 00:21:07 ; elapsed = 00:22:59 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1796 ; free virtual = 21960 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 1af9e8dc5 Time (s): cpu = 00:24:09 ; elapsed = 00:26:03 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1313 ; free virtual = 21476 Phase 3.6 Small Shape Detail Placement | Checksum: 1af9e8dc5 Time (s): cpu = 00:24:14 ; elapsed = 00:26:07 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1385 ; free virtual = 21549 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 13b4057bb Time (s): cpu = 00:24:33 ; elapsed = 00:26:27 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1405 ; free virtual = 21569 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 182d4de71 Time (s): cpu = 00:24:45 ; elapsed = 00:26:38 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1404 ; free virtual = 21568 Phase 3 Detail Placement | Checksum: 182d4de71 Time (s): cpu = 00:24:48 ; elapsed = 00:26:42 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1407 ; free virtual = 21570 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: c12e0452 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net ipbus_blk/ipbus/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s13_l2/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s9_l1/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s9_l3/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s4_l3/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s4_l4/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s4_l2/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s4_l1/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s9_l2/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s13_l1/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s13_l3/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s13_l4/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net backplane/aurora_s9_l4/aurora_module_i/clock_module_i/CLK, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 13 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 13, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: c12e0452 Time (s): cpu = 00:27:42 ; elapsed = 00:29:37 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1507 ; free virtual = 21671 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.523. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: efba7627 Time (s): cpu = 00:34:00 ; elapsed = 00:35:56 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1524 ; free virtual = 21688 Phase 4.1 Post Commit Optimization | Checksum: efba7627 Time (s): cpu = 00:34:04 ; elapsed = 00:35:59 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1525 ; free virtual = 21688 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: efba7627 Time (s): cpu = 00:34:08 ; elapsed = 00:36:04 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1541 ; free virtual = 21704 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: efba7627 Time (s): cpu = 00:34:13 ; elapsed = 00:36:08 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1634 ; free virtual = 21797 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9589.996 ; gain = 0.000 ; free physical = 1640 ; free virtual = 21803 Phase 4.4 Final Placement Cleanup | Checksum: 128be6054 Time (s): cpu = 00:34:16 ; elapsed = 00:36:12 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1640 ; free virtual = 21803 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 128be6054 Time (s): cpu = 00:34:19 ; elapsed = 00:36:15 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1640 ; free virtual = 21803 Ending Placer Task | Checksum: d956c693 Time (s): cpu = 00:34:19 ; elapsed = 00:36:15 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 1640 ; free virtual = 21803 INFO: [Common 17-83] Releasing license: Implementation 323 Infos, 225 Warnings, 3 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:35:01 ; elapsed = 00:36:58 . Memory (MB): peak = 9589.996 ; gain = 1785.184 ; free physical = 2080 ; free virtual = 22244 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 9589.996 ; gain = 0.000 ; free physical = 2080 ; free virtual = 22244 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 9589.996 ; gain = 0.000 ; free physical = 1359 ; free virtual = 22190 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:50 ; elapsed = 00:03:53 . Memory (MB): peak = 9590.000 ; gain = 0.004 ; free physical = 1895 ; free virtual = 22207 INFO: [runtcl-4] Executing : report_io -file top_rod_jfex_io_placed.rpt report_io: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.62 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1855 ; free virtual = 22168 INFO: [runtcl-4] Executing : report_utilization -file top_rod_jfex_utilization_placed.rpt -pb top_rod_jfex_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_jfex_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1892 ; free virtual = 22211 INFO: [runtcl-4] Executing : report_utilization -file top_rod_jfex_utilization_placed_1.rpt -pb top_rod_jfex_utilization_placed_1.pb Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1733 ; free virtual = 22052 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-19.200 | Phase 1 Physical Synthesis Initialization | Checksum: 1fd575aa8 Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1483 ; free virtual = 21802 Phase 2 SLR Crossing Optimization Phase 2 SLR Crossing Optimization | Checksum: 1fd575aa8 Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1468 ; free virtual = 21787 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.523 | TNS=-19.200 | Phase 3 Fanout Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/fifo_layer/gen_jfex_chan.ch22/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/fifo_layer/gen_jfex_chan.ch23/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 14 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n. Replicated 8 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Replicated 5 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Replicated 6 times. INFO: [Physopt 32-572] Net event_builder/bulk_0/input_mux/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]. Replicated 5 times. INFO: [Physopt 32-81] Processed net event_builder/bulk_0/input_mux/pointer[3]. Replicated 2 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/bkpln_rst_pulse_stretcher/system_reset. Replicated 4 times. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-81] Processed net event_builder/bulk_0/input_mux/Q[4]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0]. Replicated 2 times. INFO: [Physopt 32-232] Optimized 11 nets. Created 54 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 11 nets or cells. Created 54 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.378 | TNS=-7.305 | Netlist sorting complete. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.51 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1470 ; free virtual = 21789 Phase 3 Fanout Optimization | Checksum: 260942df9 Time (s): cpu = 00:02:30 ; elapsed = 00:02:31 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1470 ; free virtual = 21789 Phase 4 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 152 candidate nets for placement-based optimization. INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Re-placed instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Re-placed instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/m_axis_tready. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo_i_4__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_18. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_18_INST_0 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_3. Re-placed instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_384_447_0_2_i_1 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/dset_header_fifo_wen. Re-placed instance event_builder/ttc_input/dset_header_fifo_wen_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_1 INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[27]. Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[27] INFO: [Physopt 32-663] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_4_n_0. Re-placed instance event_builder/ttc_input/ttc_crc_ok_inferred_i_4 INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[23]. Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[23] INFO: [Physopt 32-663] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_5_n_0. Re-placed instance event_builder/ttc_input/ttc_crc_ok_inferred_i_5 INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[28]. Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[28] INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[25]. Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[25] INFO: [Physopt 32-663] Processed net vio_pp_ctrl/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/probe_out5[0]. Re-placed instance vio_pp_ctrl/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/Probe_out_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable. Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_88_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_88 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/sel0[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_86 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/RX_CHANNEL_UP_Buffer_reg_12. Re-placed instance event_builder/tob_processor_0/bulk_2_i_7 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[3]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_3 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_144_n_0. Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg_i_144 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_23_n_0. Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg_i_23 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_18_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_18 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_3_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_41_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_41 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[3]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[3] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/m_axis_tready. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo_i_4__10 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_19. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_19_INST_0 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_132_n_0. Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg_i_132 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_84_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_84 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_1. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_192_255_0_2_i_1 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_50_n_0. Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg_i_50 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_85_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_85 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[1]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[1] INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/controller_i_10_n_0. Re-placed instance event_builder/bulk_0/input_mux/controller_i_10 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_15_n_0. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_15 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[16]. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_25 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/s_tlast. Re-placed instance event_builder/bulk_0/input_mux/controller_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q_reg[0] INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/m_header_mark_n_0. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/D[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]_i_2_n_0. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_2 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_4_n_0. Did not re-place instance event_builder/bulk_0/input_mux/m_header_mark_i_4 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_16_n_0. Did not re-place instance event_builder/bulk_0/input_mux/m_header_mark_i_16 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[6]_0. Re-placed instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_128_191_0_2_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_141_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_141 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/tobsel. Did not re-place instance event_builder/tob_processor_0/event_builder_0/tobsel_reg INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/m_axis_tready. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_fifo_i_3 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1]. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/gen_sdpram.xpm_memory_base_inst_i_2 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/axis_rd_eop1. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst_i_1 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n_repN_2. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_replica_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo_i_4__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/s_tready_6. Re-placed instance event_builder/tob_processor_0/input_mux/s_tready_6_INST_0 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[6]_1. Re-placed instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_256_319_0_2_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch14/cc_int_axis_tready_i. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch14/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch14/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/s_tready_14. Re-placed instance event_builder/tob_processor_0/input_mux/s_tready_14_INST_0 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[7]_0. Re-placed instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_64_127_0_2_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[8]_0. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_448_511_0_2_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_2. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_320_383_0_2_i_1 INFO: [Physopt 32-662] Processed net backplane/combined_ttc/inst_regs/reg_3[24]. Did not re-place instance backplane/combined_ttc/inst_regs/reg_3_reg[24] INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[6]. Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[6] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_3_n_0. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_3 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_0. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_0_63_0_2_i_1 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq. Re-placed instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[37]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[37] INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/s_chan_enable_6. Re-placed instance event_builder/tob_processor_0/bulk_0_i_8 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_14_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_14 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[2]. Re-placed instance event_builder/bulk_0/input_mux/controller_i_26 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_11_n_0. Did not re-place instance event_builder/bulk_0/input_mux/m_header_mark_i_11 INFO: [Physopt 32-662] Processed net backplane/combined_ttc/inst_regs/reg_3[30]. Did not re-place instance backplane/combined_ttc/inst_regs/reg_3_reg[30] INFO: [Physopt 32-663] Processed net backplane/combined_ttc/inst_regs/reg_3[26]. Re-placed instance backplane/combined_ttc/inst_regs/reg_3_reg[26] INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[15]. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_24 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_27_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_27 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_91_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_91 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[2]. Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[32]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[32] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_15_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_15 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n_repN_6. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_replica_6 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_34_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_34 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/pointer[9]. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_51 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_1_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_1 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_10_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_10 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[0]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[2]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[2] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[2]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[4]_repN. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[4]_replica INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_13_n_0. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_13 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[11]. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_20 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/pointer[7]. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_49 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_4. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[1]_replica_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_32_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_32 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/pointer[2]. Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_44 INFO: [Physopt 32-663] Processed net event_builder/ttc_input/cttc_crc/crc_out[0]. Re-placed instance event_builder/ttc_input/cttc_crc/crc_r_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[46]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[46] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_11_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_11 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[5]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/Aurora_channel_control_reg/aurora_channel_control[29]_INST_0_i_1 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch16/m_axis_tready. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo_i_4__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch16/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/s_tready_16. Re-placed instance event_builder/tob_processor_0/input_mux/s_tready_16_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/calo_int_axis_tready. Re-placed instance event_builder/fifo_layer/ch0/calo_int_axis_tready_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/s_tready_0. Re-placed instance event_builder/bulk_0/input_mux/s_tready_0_INST_0 INFO: [Physopt 32-663] Processed net event_builder/bkpln_rst_pulse_stretcher/system_reset_repN_2. Re-placed instance event_builder/bkpln_rst_pulse_stretcher/fifo_layer_i_1_replica_2 INFO: [Physopt 32-663] Processed net System_RESET. Re-placed instance event_builder_i_1 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/pulse_stretcher/pulse_out. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch12/pulse_stretcher/pulse_out_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/pulse_in. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/pulse_stretcher_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/calo_poll_reg_i_1_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/calo_poll_reg_i_1 INFO: [Physopt 32-663] Processed net vio_pp_ctrl/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/probe_out4[0]. Re-placed instance vio_pp_ctrl/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/Probe_out_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/calo_poll_reg. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/calo_poll_reg_reg INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo_i_4__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN_3. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_5. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_5_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[1]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Re-placed instance event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch5/norm_fifo.calo_fifo_i_2__0_n_0. Re-placed instance event_builder/fifo_layer/ch5/norm_fifo.calo_fifo_i_2__0 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Re-placed instance event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/s_tready_1. Re-placed instance event_builder/bulk_1/input_mux/s_tready_1_INST_0 INFO: [Physopt 32-661] Optimized 64 nets. Re-placed 64 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 64 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 64 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.228 | TNS=-2.011 | Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1470 ; free virtual = 21790 Phase 4 Single Cell Placement Optimization | Checksum: 166eb0de3 Time (s): cpu = 00:02:57 ; elapsed = 00:02:59 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1469 ; free virtual = 21789 Phase 5 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]_repN. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[0]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/m_axis_tready. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo_i_4__9/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_18. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_18_INST_0/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]/Q INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN. Re-placed instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica/Q INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n_repN_1. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_replica_1/Q INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[63]_i_16_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[63]_i_16/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_11_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_11/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_1/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_5_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_5/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[61]_i_11_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[61]_i_11/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_11_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_11/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_1/O INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_5_n_0. Re-placed instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[32]_i_5/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_11_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_11/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_1/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_5_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[28]_i_5/O INFO: [Physopt 32-661] Optimized 8 nets. Re-placed 16 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 8 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 16 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.228 | TNS=-0.716 | Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1469 ; free virtual = 21789 Phase 5 Multi Cell Placement Optimization | Checksum: 1636ed481 Time (s): cpu = 00:03:12 ; elapsed = 00:03:14 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1469 ; free virtual = 21789 Phase 6 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-77] Pass 1. Identified 3 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[63]_i_16_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 6 Rewire | Checksum: 19ec02a64 Time (s): cpu = 00:03:15 ; elapsed = 00:03:17 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 7 Critical Cell Optimization INFO: [Physopt 32-46] Identified 3 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_INST_0_i_24_n_0. Replicated 1 times. INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[61]_i_11_n_0 was not replicated. INFO: [Physopt 32-232] Optimized 2 nets. Created 3 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 3 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.228 | TNS=-0.688 | Netlist sorting complete. Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.32 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 7 Critical Cell Optimization | Checksum: 1e3ba0be5 Time (s): cpu = 00:03:19 ; elapsed = 00:03:22 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1462 ; free virtual = 21782 Phase 8 Fanout Optimization INFO: [Physopt 32-76] Pass 1. Identified 3 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Replicated 1 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 2 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.223 | TNS=-0.646 | Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1462 ; free virtual = 21782 Phase 8 Fanout Optimization | Checksum: 2caa6723f Time (s): cpu = 00:03:29 ; elapsed = 00:03:31 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 9 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 241 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[0]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo_i_2__10_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo_i_2__10 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch19/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/s_tready_7. Re-placed instance event_builder/bulk_1/input_mux/s_tready_7_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/q[0][0]. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_control_reg/aurora_channel_control[29]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-663] Processed net fm_interface_2/u0/txresetdone_r[1]. Re-placed instance fm_interface_2/u0/txresetdone_r_inferred_i_1 INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[15].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1[0]. Did not re-place instance fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[15].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[0] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[4]_repN. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[4]_replica INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Re-placed instance event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/calo_int_axis_tready. Re-placed instance event_builder/fifo_layer/ch2/calo_int_axis_tready_inferred_i_1 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Re-placed instance event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/s_tready_2. Re-placed instance event_builder/bulk_0/input_mux/s_tready_2_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[1]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[1] INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[5]. Re-placed instance event_builder/bulk_0/input_mux/controller_i_14 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/in0[53]. Did not re-place instance event_builder/bulk_0/input_mux/fifo_s_tdata_inferred_i_11 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/fifo_s_tdata_inferred_i_95_n_0. Re-placed instance event_builder/bulk_0/input_mux/fifo_s_tdata_inferred_i_95 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[1]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/m_tlast. Did not re-place instance event_builder/bulk_1/controller/state_reg/m_tlast_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/controller_i_10_n_0. Did not re-place instance event_builder/bulk_1/input_mux/controller_i_10 INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/pointer[9]. Re-placed instance event_builder/bulk_1/input_mux/tvalid_i_18 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/s_tlast. Did not re-place instance event_builder/bulk_1/input_mux/controller_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/tvalid_i_13_n_0. Did not re-place instance event_builder/bulk_1/input_mux/tvalid_i_13 INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/tvalid_n_0. Re-placed instance event_builder/bulk_1/input_mux/tvalid INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/tvalid_i_3_n_0. Re-placed instance event_builder/bulk_1/input_mux/tvalid_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8_n_0. Did not re-place instance event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo_i_4__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n_repN_3. Re-placed instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_replica_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_6. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_6_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[3]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[3] INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/pointer[7]. Re-placed instance event_builder/bulk_1/input_mux/controller_i_27 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[4]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/m_tlast. Did not re-place instance event_builder/bulk_0/controller/state_reg/m_tlast_INST_0 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_13_n_0. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark_i_13 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/pointer[6]. Re-placed instance event_builder/bulk_0/input_mux/controller_i_24 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/controller_i_10_n_0. Re-placed instance event_builder/bulk_0/input_mux/controller_i_10 INFO: [Physopt 32-663] Processed net event_builder/bulk_0/input_mux/m_header_mark_n_0. Re-placed instance event_builder/bulk_0/input_mux/m_header_mark INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/s_tlast. Did not re-place instance event_builder/bulk_0/input_mux/controller_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_4_n_0. Did not re-place instance event_builder/bulk_0/input_mux/m_header_mark_i_4 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8_n_0. Did not re-place instance event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/Aurora_channel_control_reg/aurora_channel_control[29]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo_i_2__9_n_0. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo_i_2__9 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Re-placed instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/s_tready_6. Re-placed instance event_builder/bulk_1/input_mux/s_tready_6_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/tvalid_i_14_n_0. Re-placed instance event_builder/bulk_1/input_mux/tvalid_i_14 INFO: [Physopt 32-663] Processed net fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0]. Re-placed instance fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2 INFO: [Common 17-14] Message 'Physopt 32-663' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Physopt 32-662] Processed net Bulk_2_64_32/flx_bp_sync_1. Did not re-place instance Bulk_2_64_32/flx_bp_sync_1_reg INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[0]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net fm_interface_1/chan_0/u5/crc_kin_reg_n_0_[0]. Did not re-place instance fm_interface_1/chan_0/u5/crc_kin_reg[0] INFO: [Physopt 32-662] Processed net fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/shifted_data_in_reg[7][109]_srl8_n_0. Did not re-place instance fm_interface_1/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/shifted_data_in_reg[7][109]_srl8 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica_3 INFO: [Physopt 32-662] Processed net backplane/combined_ttc/inst_regs/reg_3[26]. Did not re-place instance backplane/combined_ttc/inst_regs/reg_3_reg[26] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[53]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[53]_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_4_n_0. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[53]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[53] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_1. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_192_255_0_2_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[36]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[36] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[4]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_14_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_14 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_17_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_17 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_68_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_68 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[4]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[4] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[3]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[3] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/m_header_mark_i_3_n_0. Did not re-place instance event_builder/bulk_0/input_mux/m_header_mark_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/pointer[3]_repN. Did not re-place instance event_builder/bulk_0/input_mux/controller_i_21_replica INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[48]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[48] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_10_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_10 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN_5. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica_5 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[32]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[32] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_15_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_15 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[29]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[29]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[29]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[29] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/any_err. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[5]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/DIn[54]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_14 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[5] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[16]_i_13_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[16]_i_13 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[2]_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_2_in[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[0]_i_2 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[5]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[5] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[63]_i_12_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[63]_i_12 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/axis_pkt_read. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.axis_pkt_read_reg INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/D[1]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[1]_i_1 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[1]_i_2_n_0. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[1]_i_2 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/controller_i_8_n_0. Did not re-place instance event_builder/bulk_0/input_mux/controller_i_8 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[1]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q_reg[1] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[50]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[50] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[18]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[18]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[18]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[18] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[3]_i_5_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[3]_i_5 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_2_in[3]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[3]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[4]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_s_reg[3] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[0]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[0] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_5_n_0. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_5 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/in0[35]. Did not re-place instance event_builder/bulk_0/input_mux/fifo_s_tdata_inferred_i_29 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/bulk_header_read_en. Did not re-place instance event_builder/ttc_input_i_1 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/load_hdr_reg. Did not re-place instance event_builder/bulk_1/controller/state_reg/load_hdr_reg_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/Q[2]. Did not re-place instance event_builder/bulk_1/controller/state_reg/Q_reg[2] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout[28]. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout[39]. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[39] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/Q[2]. Did not re-place instance event_builder/bulk_1/input_mux/chan_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[42]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[42] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_12_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_eq_inferred_i_12 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/Q[1]. Did not re-place instance event_builder/bulk_1/controller/state_reg/Q_reg[1] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/D[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]_i_2_n_0. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/DIn[52]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_20 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[0]_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_4_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_2_in[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[13]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_s_reg[12] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[9]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[9]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[9]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[9] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[31]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[31]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[31]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[31] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[2]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/load_hdr_reg. Did not re-place instance event_builder/bulk_0/controller/state_reg/load_hdr_reg_INST_0 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/shifted_data_in_reg[7][4]_srl8_n_0. Did not re-place instance event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/shifted_data_in_reg[7][4]_srl8 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[61]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[61] INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/Q[0]. Did not re-place instance event_builder/bulk_1/controller/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/ch1/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_1. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_1_INST_0 INFO: [Physopt 32-661] Optimized 84 nets. Re-placed 84 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 84 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 84 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.223 | TNS=-0.646 | Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 9 Single Cell Placement Optimization | Checksum: 146d80386 Time (s): cpu = 00:04:09 ; elapsed = 00:04:12 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 10 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 58 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 10 Multi Cell Placement Optimization | Checksum: 1de8b4d09 Time (s): cpu = 00:04:15 ; elapsed = 00:04:18 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 11 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-77] Pass 1. Identified 2 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 11 Rewire | Checksum: 196390a3b Time (s): cpu = 00:04:17 ; elapsed = 00:04:20 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1461 ; free virtual = 21781 Phase 12 Critical Cell Optimization INFO: [Physopt 32-46] Identified 1 candidate net for critical-cell optimization. INFO: [Physopt 32-572] Net event_builder/tob_processor_0/input_mux/current_chan[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 12 Critical Cell Optimization | Checksum: 1e2c70a6e Time (s): cpu = 00:04:21 ; elapsed = 00:04:24 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 13 SLR Crossing Optimization Phase 13 SLR Crossing Optimization | Checksum: 1e2c70a6e Time (s): cpu = 00:04:22 ; elapsed = 00:04:25 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 14 Fanout Optimization INFO: [Physopt 32-64] No nets found for fanout-optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 14 Fanout Optimization | Checksum: 1e2c70a6e Time (s): cpu = 00:04:27 ; elapsed = 00:04:31 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 15 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 60 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo_i_4__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_6. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_6_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[4]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/m_tlast. Did not re-place instance event_builder/bulk_0/controller/state_reg/m_tlast_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/s_tlast. Did not re-place instance event_builder/bulk_0/input_mux/controller_i_3 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8_n_0. Did not re-place instance event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/any_err. Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[5]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_10_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_10 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_2_in[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[12]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[0]_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_0_in0_in__107[13]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg_s_reg[12] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[20]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[20]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[20]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_4. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_4_INST_0 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/D[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]_i_2_n_0. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q[0]_i_2 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/controller/state_reg/Q[0]. Did not re-place instance event_builder/bulk_0/controller/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[45]_i_7_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[45]_i_7 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[45]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[45] INFO: [Physopt 32-661] Optimized 24 nets. Re-placed 24 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 24 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 24 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.223 | TNS=-0.646 | Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 15 Single Cell Placement Optimization | Checksum: 2a6638245 Time (s): cpu = 00:04:41 ; elapsed = 00:04:45 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 16 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 26 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 16 Multi Cell Placement Optimization | Checksum: 2aad3ddba Time (s): cpu = 00:04:47 ; elapsed = 00:04:50 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 17 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-241] No nets found for rewiring () optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 17 Rewire | Checksum: 2aad3ddba Time (s): cpu = 00:04:49 ; elapsed = 00:04:52 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 18 Critical Cell Optimization INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 18 Critical Cell Optimization | Checksum: 2aad3ddba Time (s): cpu = 00:04:51 ; elapsed = 00:04:54 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 19 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 19 DSP Register Optimization | Checksum: 2aad3ddba Time (s): cpu = 00:04:52 ; elapsed = 00:04:56 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 20 BRAM Register Optimization INFO: [Physopt 32-712] Optimization is not feasible on net fifo_dout[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_dout[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-665] Processed cell event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1. 30 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 30 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.223 | TNS=-0.646 | Netlist sorting complete. Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.31 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 20 BRAM Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:04:57 ; elapsed = 00:05:01 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 21 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 21 URAM Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:04:58 ; elapsed = 00:05:02 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 22 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 22 Shift Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:00 ; elapsed = 00:05:03 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 23 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 23 DSP Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:01 ; elapsed = 00:05:04 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 24 BRAM Register Optimization INFO: [Physopt 32-712] Optimization is not feasible on net fifo_dout[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_dout[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 24 BRAM Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:02 ; elapsed = 00:05:06 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 25 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 25 URAM Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:03 ; elapsed = 00:05:07 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 26 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 26 Shift Register Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:04 ; elapsed = 00:05:08 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 27 Critical Pin Optimization INFO: [Physopt 32-606] Identified 8 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 2 nets. Swapped 19 pins. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 19 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.014 | Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 27 Critical Pin Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:06 ; elapsed = 00:05:10 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 28 Very High Fanout Optimization INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 801 to 162 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 865 to 178 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 28 Very High Fanout Optimization | Checksum: 1dc8992e3 Time (s): cpu = 00:05:12 ; elapsed = 00:05:15 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 29 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 110 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch13/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_13. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_13_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo_i_4__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_6. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_6_INST_0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_4. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_4_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/any_err. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[5]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[1]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[1] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/crc_reset. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_header_crc_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/DIn[52]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_20 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/error_map[0]_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_11_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_11 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_4_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_2_in[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[37]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[37] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_141_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_141 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[3]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_14_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/L1ID_reg_eq_inferred_i_14 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_23_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_23 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_84_n_0. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_84 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[3]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/q[0][0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/DIn[10]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[10]_i_11 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/lmem[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_trailer_err_map/lmem[2]_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_2_in[10]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[10]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[11]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_s_reg[10] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net pp_out_fifo_6432/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/r1_last_reg_n_0. Did not re-place instance pp_out_fifo_6432/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/r1_last_reg INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN_4. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]_replica_4 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/data_valid. Did not re-place instance event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.gdvld_fwft.data_valid_fwft_reg INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[2]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg__0[16]. Did not re-place instance event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg__0[17]. Did not re-place instance event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg__0[18]. Did not re-place instance event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg__0[19]. Did not re-place instance event_builder/bulk_0/status_regs/gen_regs.packet_capture/pkt_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/pointer[5]. Did not re-place instance event_builder/bulk_0/input_mux/controller_i_14 INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/Q[4]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch18/cc_poll_reg. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch18/cc_poll_reg_reg INFO: [Physopt 32-662] Processed net event_builder/ttc_input/dset_header_fifo_wen. Did not re-place instance event_builder/ttc_input/dset_header_fifo_wen_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_en_1. Did not re-place instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/RAM_reg_192_255_0_2_i_1 INFO: [Physopt 32-662] Processed net backplane/combined_ttc/inst_regs/reg_3[26]. Did not re-place instance backplane/combined_ttc/inst_regs/reg_3_reg[26] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/ttc_input/ttc_crc_ok_inferred_i_4_n_0. Did not re-place instance event_builder/ttc_input/ttc_crc_ok_inferred_i_4 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tlast_pipe_reg_i_2_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tlast_pipe_reg_i_2 INFO: [Physopt 32-662] Processed net pp_out_fifo_6432/flx_bp_sync_1. Did not re-place instance pp_out_fifo_6432/flx_bp_sync_1_reg INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1[0]. Did not re-place instance fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[37]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[37]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_1_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg[11]_i_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_tdata[11]. Did not re-place instance event_builder/tob_processor_0/input_mux/m_tdata_pipe_reg_reg[11] INFO: [Physopt 32-662] Processed net event_builder/ttc_input/cttc_crc/crc_out[3]. Did not re-place instance event_builder/ttc_input/cttc_crc/crc_r_reg[3] INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1[0]. Did not re-place instance fm_interface_2/chan_1/ila_ed_dbg.ila_ed/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[5].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/aurora_channel_control[29]_INST_0_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/stretcher/counter[0]. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/stretcher/counter_reg[0] INFO: [Physopt 32-661] Optimized 32 nets. Re-placed 32 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 32 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 32 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.014 | Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 29 Single Cell Placement Optimization | Checksum: 24c75797c Time (s): cpu = 00:05:32 ; elapsed = 00:05:36 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1459 ; free virtual = 21780 Phase 30 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 32 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 30 Multi Cell Placement Optimization | Checksum: 19843db13 Time (s): cpu = 00:05:37 ; elapsed = 00:05:41 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 31 SLR Crossing Optimization Phase 31 SLR Crossing Optimization | Checksum: 19843db13 Time (s): cpu = 00:05:38 ; elapsed = 00:05:42 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1460 ; free virtual = 21780 Phase 32 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.014 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-572] Net event_builder/tob_processor_0/input_mux/current_chan[4] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net cc_int_axis_tready_i due to MARK_DEBUG attribute. INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Rewiring did not optimize the net. INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net proc_clock_gen/inst/pp_clock_packet_processor_clock. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]/Q INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i_inferred_i_1/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/cc_int_axis_tready_i. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_12_INST_0/O INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/s_tready_12. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Did not re-place instance event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_jfex_chan.ch12/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net proc_clock_gen/inst/pp_clock_packet_processor_clock. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.014 | TNS=-0.014 | Phase 32 Critical Path Optimization | Checksum: 21abaf114 Time (s): cpu = 00:05:53 ; elapsed = 00:05:57 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1459 ; free virtual = 21779 Phase 33 BRAM Enable Optimization Phase 33 BRAM Enable Optimization | Checksum: 21abaf114 Time (s): cpu = 00:05:54 ; elapsed = 00:05:58 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1458 ; free virtual = 21779 INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1472 ; free virtual = 21792 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.014 | TNS=-0.014 | Summary of Physical Synthesis Optimizations ============================================ ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Fanout | 0.150 | 11.978 | 56 | 0 | 13 | 2 | 3 | 00:01:08 | | Single Cell Placement | 0.150 | 5.294 | 0 | 0 | 204 | 0 | 4 | 00:01:39 | | Multi Cell Placement | 0.000 | 1.294 | 0 | 0 | 8 | 0 | 4 | 00:00:26 | | Rewire | 0.000 | 0.000 | 0 | 0 | 0 | 12 | 3 | 00:00:04 | | Critical Cell | 0.000 | 0.028 | 3 | 0 | 2 | 18 | 3 | 00:00:07 | | SLR Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 | | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | BRAM Register | 0.000 | 0.000 | 30 | 0 | 1 | 4 | 2 | 00:00:04 | | URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | Shift Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:01 | | Critical Pin | 0.209 | 0.632 | 0 | 0 | 2 | 0 | 1 | 00:00:01 | | Very High Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:04 | | BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:14 | | Total | 0.509 | 19.227 | 89 | 0 | 230 | 36 | 32 | 00:03:51 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1472 ; free virtual = 21792 Ending Physical Synthesis Task | Checksum: 198ca11e8 Time (s): cpu = 00:05:57 ; elapsed = 00:06:01 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1558 ; free virtual = 21878 INFO: [Common 17-83] Releasing license: Implementation 1010 Infos, 231 Warnings, 3 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:08:07 ; elapsed = 00:08:11 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1834 ; free virtual = 22155 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1834 ; free virtual = 22155 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1138 ; free virtual = 22120 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:02:48 ; elapsed = 00:03:50 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1675 ; free virtual = 22144 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: fa34dd48 ConstDB: 0 ShapeSum: e6338c5 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: bd540e0b Time (s): cpu = 00:02:49 ; elapsed = 00:02:50 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1202 ; free virtual = 21671 Post Restoration Checksum: NetGraph: 70bc78e6 NumContArr: 4c979525 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: bd540e0b Time (s): cpu = 00:02:53 ; elapsed = 00:02:54 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1205 ; free virtual = 21674 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: bd540e0b Time (s): cpu = 00:02:56 ; elapsed = 00:02:57 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1178 ; free virtual = 21646 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: bd540e0b Time (s): cpu = 00:02:57 ; elapsed = 00:02:58 . Memory (MB): peak = 9590.000 ; gain = 0.000 ; free physical = 1178 ; free virtual = 21646 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 183dd0f3d Time (s): cpu = 00:06:48 ; elapsed = 00:06:54 . Memory (MB): peak = 9594.996 ; gain = 4.996 ; free physical = 970 ; free virtual = 21439 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.153 | TNS=0.000 | WHS=-2.740 | THS=-15626.734| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 21b97a25c Time (s): cpu = 00:08:52 ; elapsed = 00:08:58 . Memory (MB): peak = 9594.996 ; gain = 4.996 ; free physical = 867 ; free virtual = 21336 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.153 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1ed74cde4 Time (s): cpu = 00:08:56 ; elapsed = 00:09:03 . Memory (MB): peak = 9594.996 ; gain = 4.996 ; free physical = 841 ; free virtual = 21310 Phase 2 Router Initialization | Checksum: 13e695e49 Time (s): cpu = 00:08:57 ; elapsed = 00:09:04 . Memory (MB): peak = 9594.996 ; gain = 4.996 ; free physical = 841 ; free virtual = 21310 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 376151 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 376151 Number of Partially Routed Nets = 0 Number of Node Overlaps = 4 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: f95fdbda Time (s): cpu = 00:11:32 ; elapsed = 00:11:40 . Memory (MB): peak = 9594.996 ; gain = 4.996 ; free physical = 799 ; free virtual = 21268 INFO: [Route 35-580] Design has 50 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6/DIADI[2]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[1]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_6/DIADI[1]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[3]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_7/DIADI[1]| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 29644 Number of Nodes with overlaps = 2129 Number of Nodes with overlaps = 440 Number of Nodes with overlaps = 62 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.170 | TNS=-0.927 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1ea4b9e9e Time (s): cpu = 00:33:54 ; elapsed = 00:34:19 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 827 ; free virtual = 21296 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 2609 Number of Nodes with overlaps = 372 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.170 | TNS=-0.882 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1f988e5bb Time (s): cpu = 00:37:08 ; elapsed = 00:37:39 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 833 ; free virtual = 21302 Phase 4 Rip-up And Reroute | Checksum: 1f988e5bb Time (s): cpu = 00:37:09 ; elapsed = 00:37:40 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 833 ; free virtual = 21302 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 13d8943c5 Time (s): cpu = 00:37:54 ; elapsed = 00:38:25 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 741 ; free virtual = 21210 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.036 | TNS=-0.042 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 1d1673ccf Time (s): cpu = 00:38:00 ; elapsed = 00:38:31 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 769 ; free virtual = 21238 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1d1673ccf Time (s): cpu = 00:38:01 ; elapsed = 00:38:32 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 769 ; free virtual = 21238 Phase 5 Delay and Skew Optimization | Checksum: 1d1673ccf Time (s): cpu = 00:38:02 ; elapsed = 00:38:33 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 769 ; free virtual = 21238 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1b43de6a6 Time (s): cpu = 00:38:51 ; elapsed = 00:39:22 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 791 ; free virtual = 21260 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.036 | TNS=-0.042 | WHS=-0.954 | THS=-18.700| Phase 6.1.2 Lut RouteThru Assignment for hold Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 123a1fca0 Time (s): cpu = 00:38:59 ; elapsed = 00:39:30 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 787 ; free virtual = 21256 Phase 6.1 Hold Fix Iter | Checksum: 123a1fca0 Time (s): cpu = 00:38:59 ; elapsed = 00:39:31 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 787 ; free virtual = 21256 Phase 6 Post Hold Fix | Checksum: 140e636ce Time (s): cpu = 00:39:01 ; elapsed = 00:39:32 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 787 ; free virtual = 21256 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 6c4d82fb Time (s): cpu = 00:40:12 ; elapsed = 00:40:44 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 787 ; free virtual = 21256 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.036 | TNS=-0.042 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 6c4d82fb Time (s): cpu = 00:40:13 ; elapsed = 00:40:45 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 787 ; free virtual = 21256 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 13.7532 % Global Horizontal Routing Utilization = 14.0792 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 95.4955%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X64Y333 -> INT_L_X64Y333 INT_R_X69Y305 -> INT_R_X69Y305 INT_L_X64Y301 -> INT_L_X64Y301 INT_R_X69Y298 -> INT_R_X69Y298 INT_L_X64Y297 -> INT_L_X64Y297 South Dir 1x1 Area, Max Cong = 91.8919%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X53Y277 -> INT_R_X53Y277 INT_R_X61Y234 -> INT_R_X61Y234 INT_R_X63Y233 -> INT_R_X63Y233 East Dir 1x1 Area, Max Cong = 88.2353%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X88Y309 -> INT_L_X88Y309 INT_R_X61Y273 -> INT_R_X61Y273 West Dir 1x1 Area, Max Cong = 82.3529%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 1 Sparse Ratio: 0.75 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 8 Route finalize | Checksum: 6c4d82fb Time (s): cpu = 00:40:17 ; elapsed = 00:40:48 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 781 ; free virtual = 21250 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 6c4d82fb Time (s): cpu = 00:40:18 ; elapsed = 00:40:49 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 777 ; free virtual = 21246 Phase 10 Depositing Routes INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l3/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s13_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s12_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y37/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l1/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l2/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s9_l4/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s4_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l3/aurora_module_i/common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l1/aurora_module_i/no_common.aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l2/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s5_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l3/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_s8_l4/aurora_module_i/aurora_1ln_rx_i/U0/gt_wrapper_i/aurora_1ln_rx_multi_gt_i/gt0_aurora_1ln_rx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1 Phase 10 Depositing Routes | Checksum: dc4caf0d Time (s): cpu = 00:40:50 ; elapsed = 00:41:22 . Memory (MB): peak = 9683.363 ; gain = 93.363 ; free physical = 765 ; free virtual = 21234 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9683.363 ; gain = 0.000 ; free physical = 489 ; free virtual = 20958 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.194. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 12271b0fe Time (s): cpu = 00:06:12 ; elapsed = 00:06:16 . Memory (MB): peak = 10539.551 ; gain = 856.188 ; free physical = 845 ; free virtual = 20893 Phase 11 Incr Placement Change | Checksum: dc4caf0d Time (s): cpu = 00:47:14 ; elapsed = 00:47:50 . Memory (MB): peak = 10541.625 ; gain = 951.625 ; free physical = 845 ; free virtual = 20893 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: 1038e1cbd Time (s): cpu = 00:48:39 ; elapsed = 00:49:16 . Memory (MB): peak = 10541.625 ; gain = 951.625 ; free physical = 637 ; free virtual = 20685 Post Restoration Checksum: NetGraph: fe6c5371 NumContArr: 8cef4db9 Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 18b5ba12a Time (s): cpu = 00:48:56 ; elapsed = 00:49:32 . Memory (MB): peak = 10541.625 ; gain = 951.625 ; free physical = 721 ; free virtual = 20769 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 18b5ba12a Time (s): cpu = 00:49:00 ; elapsed = 00:49:36 . Memory (MB): peak = 10541.625 ; gain = 951.625 ; free physical = 694 ; free virtual = 20742 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: ef914cb4 Time (s): cpu = 00:49:02 ; elapsed = 00:49:38 . Memory (MB): peak = 10541.625 ; gain = 951.625 ; free physical = 694 ; free virtual = 20742 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 14c9ca79a Time (s): cpu = 00:53:01 ; elapsed = 00:53:39 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 549 ; free virtual = 20437 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.237 | TNS=0.000 | WHS=-2.740 | THS=-15583.057| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 1284ee7dc Time (s): cpu = 00:55:06 ; elapsed = 00:55:44 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 450 ; free virtual = 20339 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.237 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 131856441 Time (s): cpu = 00:55:11 ; elapsed = 00:55:50 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 414 ; free virtual = 20302 Phase 13 Router Initialization | Checksum: 182f2fe27 Time (s): cpu = 00:55:13 ; elapsed = 00:55:52 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 440 ; free virtual = 20329 Router Utilization Summary Global Vertical Routing Utilization = 13.6961 % Global Horizontal Routing Utilization = 14.0364 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 653 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 248 Number of Partially Routed Nets = 405 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14 Initial Routing | Checksum: 13009b99a Time (s): cpu = 00:57:51 ; elapsed = 00:58:31 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 443 ; free virtual = 20332 INFO: [Route 35-580] Design has 109 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | CLK_125_pin | clkout3 |event_builder/fifo_layer/gen_jfex_chan.ch16/gen_reg.status_regs/Aurora_channel_up_timer_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 |event_builder/fifo_layer/gen_jfex_chan.ch21/gen_reg.status_regs/Aurora_channel_up_timer_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 |event_builder/fifo_layer/gen_jfex_chan.ch13/gen_reg.status_regs/Aurora_channel_up_timer_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 3954 Number of Nodes with overlaps = 1089 Number of Nodes with overlaps = 304 Number of Nodes with overlaps = 108 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.234 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 205162494 Time (s): cpu = 01:05:01 ; elapsed = 01:05:51 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 511 ; free virtual = 20399 Phase 15.2 Global Iteration 1 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 61 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.204 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 15.2 Global Iteration 1 | Checksum: 13375c9bf Time (s): cpu = 01:06:00 ; elapsed = 01:06:51 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 506 ; free virtual = 20395 Phase 15 Rip-up And Reroute | Checksum: 13375c9bf Time (s): cpu = 01:06:01 ; elapsed = 01:06:52 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 506 ; free virtual = 20395 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1 Delay CleanUp | Checksum: 13375c9bf Time (s): cpu = 01:06:02 ; elapsed = 01:06:54 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 506 ; free virtual = 20395 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: 13375c9bf Time (s): cpu = 01:06:03 ; elapsed = 01:06:55 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 506 ; free virtual = 20395 Phase 16 Delay and Skew Optimization | Checksum: 13375c9bf Time (s): cpu = 01:06:04 ; elapsed = 01:06:56 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 506 ; free virtual = 20395 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 2028d0f13 Time (s): cpu = 01:06:54 ; elapsed = 01:07:46 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 460 ; free virtual = 20348 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.232 | TNS=0.000 | WHS=-0.115 | THS=-10.068| Phase 17.1 Hold Fix Iter | Checksum: 20e20f5dc Time (s): cpu = 01:06:56 ; elapsed = 01:07:48 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 459 ; free virtual = 20347 Phase 17 Post Hold Fix | Checksum: 187669247 Time (s): cpu = 01:06:57 ; elapsed = 01:07:49 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 459 ; free virtual = 20347 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 1f840937a Time (s): cpu = 01:08:10 ; elapsed = 01:09:02 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 469 ; free virtual = 20357 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.232 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 1f840937a Time (s): cpu = 01:08:11 ; elapsed = 01:09:03 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 469 ; free virtual = 20357 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 13.7461 % Global Horizontal Routing Utilization = 14.0962 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 1f840937a Time (s): cpu = 01:08:14 ; elapsed = 01:09:06 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 465 ; free virtual = 20353 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 1f840937a Time (s): cpu = 01:08:15 ; elapsed = 01:09:07 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 461 ; free virtual = 20349 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: 223e7b8a5 Time (s): cpu = 01:08:47 ; elapsed = 01:09:39 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 480 ; free virtual = 20368 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.231 | TNS=0.000 | WHS=0.050 | THS=0.000 | INFO: [Route 35-61] The design met the timing requirement. Phase 22 Post Router Timing | Checksum: 1e91fa950 Time (s): cpu = 01:11:39 ; elapsed = 01:12:31 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 781 ; free virtual = 20682 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 01:11:40 ; elapsed = 01:12:32 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 1441 ; free virtual = 21347 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 1065 Infos, 231 Warnings, 3 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 01:13:15 ; elapsed = 01:14:10 . Memory (MB): peak = 10613.625 ; gain = 1023.625 ; free physical = 1439 ; free virtual = 21348 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 413233A, will use most recent tag v0.2.6. As this is an official tag, patch will be incremented to 7. INFO: [Hog:Msg-0] Git describe set to: v0.2.6-14-g413233a INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_jfex was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 413233A, will use most recent tag v0.2.6. As this is an official tag, patch will be incremented to 7. INFO: [Hog:Msg-0] The git SHA value 413233a will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 10613.625 ; gain = 0.000 ; free physical = 1440 ; free virtual = 21351 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 10613.625 ; gain = 0.000 ; free physical = 592 ; free virtual = 21307 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:03:00 ; elapsed = 00:04:04 . Memory (MB): peak = 10613.629 ; gain = 0.004 ; free physical = 1238 ; free virtual = 21331 INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_drc_routed.rpt -pb top_rod_jfex_drc_routed.pb -rpx top_rod_jfex_drc_routed.rpx Command: report_drc -file top_rod_jfex_drc_routed.rpt -pb top_rod_jfex_drc_routed.pb -rpx top_rod_jfex_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:02:37 ; elapsed = 00:02:40 . Memory (MB): peak = 10613.629 ; gain = 0.000 ; free physical = 1257 ; free virtual = 21353 INFO: [runtcl-4] Executing : report_methodology -file top_rod_jfex_methodology_drc_routed.rpt -pb top_rod_jfex_methodology_drc_routed.pb -rpx top_rod_jfex_methodology_drc_routed.rpx Command: report_methodology -file top_rod_jfex_methodology_drc_routed.rpt -pb top_rod_jfex_methodology_drc_routed.pb -rpx top_rod_jfex_methodology_drc_routed.rpx INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:04:51 ; elapsed = 00:05:00 . Memory (MB): peak = 10740.375 ; gain = 126.746 ; free physical = 1646 ; free virtual = 21392 INFO: [runtcl-4] Executing : report_power -file top_rod_jfex_power_routed.rpt -pb top_rod_jfex_power_summary_routed.pb -rpx top_rod_jfex_power_routed.rpx Command: report_power -file top_rod_jfex_power_routed.rpt -pb top_rod_jfex_power_summary_routed.pb -rpx top_rod_jfex_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst INFO: [Power 33-23] Power model is not available for DNA_PORT_inst INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1091 Infos, 232 Warnings, 3 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:03:54 ; elapsed = 00:03:28 . Memory (MB): peak = 10804.375 ; gain = 64.000 ; free physical = 1372 ; free virtual = 21153 INFO: [runtcl-4] Executing : report_route_status -file top_rod_jfex_route_status.rpt -pb top_rod_jfex_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_rod_jfex_timing_summary_routed.rpt -pb top_rod_jfex_timing_summary_routed.pb -rpx top_rod_jfex_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1185 ; free virtual = 20989 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_rod_jfex_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_rod_jfex_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1172 ; free virtual = 20981 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_rod_jfex_bus_skew_routed.rpt -pb top_rod_jfex_bus_skew_routed.pb -rpx top_rod_jfex_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_bus_skew: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1167 ; free virtual = 20983 INFO: [runtcl-4] Executing : report_drc -file top_rod_jfex_drc_routed_1.rpt -pb top_rod_jfex_drc_routed_1.pb -rpx top_rod_jfex_drc_routed_1.rpx Command: report_drc -file top_rod_jfex_drc_routed_1.rpt -pb top_rod_jfex_drc_routed_1.pb -rpx top_rod_jfex_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:02:04 ; elapsed = 00:02:07 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1136 ; free virtual = 20952 INFO: [runtcl-4] Executing : report_power -file top_rod_jfex_power_routed_1.rpt -pb top_rod_jfex_power_summary_routed_1.pb -rpx top_rod_jfex_power_routed_1.rpx Command: report_power -file top_rod_jfex_power_routed_1.rpt -pb top_rod_jfex_power_summary_routed_1.pb -rpx top_rod_jfex_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1103 Infos, 234 Warnings, 3 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:20 ; elapsed = 00:01:03 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1120 ; free virtual = 20960 INFO: [runtcl-4] Executing : report_timing_summary -file top_rod_jfex_timing_summary_routed_1.rpt -pb top_rod_jfex_timing_summary_routed_1.pb -rpx top_rod_jfex_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 10804.375 ; gain = 0.000 ; free physical = 1112 ; free virtual = 20954 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Fri Sep 10 03:09:10 2021... *** Running vivado with args -log top_rod_jfex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_jfex.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_jfex.tcl -notrace Command: open_checkpoint top_rod_jfex_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1550.223 ; gain = 0.000 ; free physical = 8972 ; free virtual = 28918 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2875.270 ; gain = 18.996 ; free physical = 7597 ; free virtual = 27543 INFO: [Netlist 29-17] Analyzing 23249 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 4 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 5228.527 ; gain = 470.301 ; free physical = 5423 ; free virtual = 25377 Restored from archive | CPU: 31.860000 secs | Memory: 443.745285 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 5228.527 ; gain = 470.301 ; free physical = 5423 ; free virtual = 25377 Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5228.527 ; gain = 0.000 ; free physical = 5487 ; free virtual = 25442 INFO: [Project 1-111] Unisim Transformation Summary: A total of 9086 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 8544 instances IOBUF => IOBUF (IBUF, OBUFT): 24 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 50 instances RAM64M => RAM64M (RAMD64E(x4)): 368 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 73 instances RAM64X1S => RAM64X1S (RAMS64E): 11 instances SRLC32E => SRL16E: 16 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:03:38 ; elapsed = 00:06:20 . Memory (MB): peak = 5228.527 ; gain = 3678.309 ; free physical = 5487 ; free virtual = 25441 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force top_rod_jfex.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'ethernet_mac_rgmii' (ethernet_mac_rgmii_block) was generated with multiple features: IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license. IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer ipbus_blk/axi4_subsys/spi_0_sck_iobuf/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PLBUFGOPT-1] Non-Optimal connections to BUFG: A non-muxed BUFG backplane/user_clk_buf_i_2 is driven by another global buffer CLK_40_g_buffer. Remove non-muxed BUFG if it is not desired WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/RSTRAMARSTRAM (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/AS[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 3668 net(s) have no routable loads. The problem bus(es) and/or net(s) are CHANNEL_STAT_3[3], CHANNEL_STAT_3[13], CHANNEL_STAT_3[14], CHANNEL_STAT_3[15], CHANNEL_STAT_3[16], CHANNEL_STAT_3[17], CHANNEL_STAT_3[18], CHANNEL_STAT_3[19], CHANNEL_STAT_3[20], CHANNEL_STAT_3[21], CHANNEL_STAT_3[22], CHANNEL_STAT_3[23], CHANNEL_STAT_3[24], CHANNEL_STAT_3[25], CHANNEL_STAT_3[26]... and (the first 15 of 2326 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 24 Warnings, 6 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./top_rod_jfex.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-83] Releasing license: Implementation 47 Infos, 25 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:08:13 ; elapsed = 00:08:28 . Memory (MB): peak = 6374.020 ; gain = 1145.492 ; free physical = 5233 ; free virtual = 25237 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-bitstream.tcl Post-Bitstream proj_dir /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex INFO: [Hog:Msg-0] Evaluating Git sha for rod_jfex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_jfex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 413233A, will use most recent tag v0.2.6. As this is an official tag, patch will be incremented to 7. INFO: [Hog:Msg-0] Git describe set to: v0.2.6-14-g413233a INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/bin/rod_jfex-v0.2.6-14-g413233a... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/impl_1/top_rod_jfex.bit into /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/bin/rod_jfex-v0.2.6-14-g413233a/rod_jfex-v0.2.6-14-g413233a.bit...