*** Running vivado with args -log vio_ip_address.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_ip_address.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source vio_ip_address.tcl -notrace Command: synth_design -top vio_ip_address -part xc7vx550tffg1927-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15556 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 2236.203 ; gain = 201.715 ; free physical = 7200 ; free virtual = 27103 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_ip_address' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/synth/vio_ip_address.v:59] WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_ip_address does not have driver. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/synth/vio_ip_address.v:74] INFO: [Synth 8-6155] done synthesizing module 'vio_ip_address' (6#1) [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/synth/vio_ip_address.v:59] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in4[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in5[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in6[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in7[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in8[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in9[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in10[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in11[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in12[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in13[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in14[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in15[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in16[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in17[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in18[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in19[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in20[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in21[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in22[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in23[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in24[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in25[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in26[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in27[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in28[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in29[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in30[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in31[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in32[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in33[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in34[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in35[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in36[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in37[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in38[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in39[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in40[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in41[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in42[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in43[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in44[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in45[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in46[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in47[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in48[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in49[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in50[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in51[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in52[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in53[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in54[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in55[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in56[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in57[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in58[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in59[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in60[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in61[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in62[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in63[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in64[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in65[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in66[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in67[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in68[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in69[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in70[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in71[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in72[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in73[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in74[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in75[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in76[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in77[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in78[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in79[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in80[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in81[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in82[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in83[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in84[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in85[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in86[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in87[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in88[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in89[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in90[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in91[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in92[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in93[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in94[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in95[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in96[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in97[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in98[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in99[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in100[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in101[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in102[0] WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in103[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2305.895 ; gain = 271.406 ; free physical = 7227 ; free virtual = 27132 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 2311.828 ; gain = 277.340 ; free physical = 7227 ; free virtual = 27133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 2311.828 ; gain = 277.340 ; free physical = 7227 ; free virtual = 27133 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2311.828 ; gain = 0.000 ; free physical = 7218 ; free virtual = 27123 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address_ooc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address_ooc.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2487.516 ; gain = 0.000 ; free physical = 7102 ; free virtual = 27019 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2490.484 ; gain = 2.969 ; free physical = 7103 ; free virtual = 27019 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 7189 ; free virtual = 27106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 7189 ; free virtual = 27106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 7189 ; free virtual = 27106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 7180 ; free virtual = 27097 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 2 Input 1 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 96 Bit Registers := 5 16 Bit Registers := 7 7 Bit Registers := 1 6 Bit Registers := 1 5 Bit Registers := 1 3 Bit Registers := 2 1 Bit Registers := 13 +---Muxes : 2 Input 16 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module vio_v3_0_19_probe_in_one Detailed RTL Component Info : +---Adders : 2 Input 6 Bit Adders := 1 +---Registers : 96 Bit Registers := 5 16 Bit Registers := 1 6 Bit Registers := 1 1 Bit Registers := 2 Module vio_v3_0_19_probe_width Detailed RTL Component Info : +---Adders : 2 Input 1 Bit Adders := 1 +---Registers : 16 Bit Registers := 1 1 Bit Registers := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 16 Bit Registers := 2 1 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module vio_v3_0_19_decoder Detailed RTL Component Info : +---Registers : 16 Bit Registers := 2 7 Bit Registers := 1 5 Bit Registers := 1 3 Bit Registers := 2 1 Bit Registers := 9 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module vio_v3_0_19_vio Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[0]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[10] ) INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' (FDS) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[15] ) --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:38 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 7160 ; free virtual = 27082 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:54 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6951 ; free virtual = 26880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:54 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6951 ; free virtual = 26879 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:55 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6949 ; free virtual = 26878 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 2| |2 |LUT2 | 7| |3 |LUT3 | 21| |4 |LUT4 | 205| |5 |LUT5 | 31| |6 |LUT6 | 150| |7 |FDRE | 733| +------+-----+------+ Report Instance Areas: +------+------------------------+-------------------------+------+ | |Instance |Module |Cells | +------+------------------------+-------------------------+------+ |1 |top | | 1149| |2 | inst |vio_v3_0_19_vio | 1149| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| |4 | DECODER_INST |vio_v3_0_19_decoder | 82| |5 | PROBE_IN_INST |vio_v3_0_19_probe_in_one | 801| |6 | PROBE_IN_WIDTH_INST |vio_v3_0_19_probe_width | 2| +------+------------------------+-------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6940 ; free virtual = 26869 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 289 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:53 . Memory (MB): peak = 2490.484 ; gain = 277.340 ; free physical = 6992 ; free virtual = 26921 Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2490.484 ; gain = 455.996 ; free physical = 6993 ; free virtual = 26922 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2490.484 ; gain = 0.000 ; free physical = 7057 ; free virtual = 26990 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2490.484 ; gain = 0.000 ; free physical = 6985 ; free virtual = 26918 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:03 ; elapsed = 00:01:50 . Memory (MB): peak = 2490.484 ; gain = 866.898 ; free physical = 7115 ; free virtual = 27048 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2490.484 ; gain = 0.000 ; free physical = 7115 ; free virtual = 27048 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/vio_ip_address_synth_1/vio_ip_address.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_ip_address, cache-ID = c2e2fe762cf0fc53 INFO: [Coretcl 2-1174] Renamed 5 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.500 ; gain = 0.000 ; free physical = 7107 ; free virtual = 27042 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/vio_ip_address_synth_1/vio_ip_address.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_ip_address_utilization_synth.rpt -pb vio_ip_address_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu Sep 9 23:55:56 2021...