*** Running vivado with args -log DPram_32b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DPram_32b.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source DPram_32b.tcl -notrace Command: synth_design -top DPram_32b -part xc7vx550tffg1927-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12088 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:39 . Memory (MB): peak = 2231.539 ; gain = 201.684 ; free physical = 8436 ; free virtual = 28101 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'DPram_32b' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/synth/DPram_32b.vhd:74] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_XDEVICEFAMILY bound to: virtex7 - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 2 - type: integer Parameter C_BYTE_SIZE bound to: 9 - type: integer Parameter C_ALGORITHM bound to: 1 - type: integer Parameter C_PRIM_TYPE bound to: 1 - type: integer Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer Parameter C_INIT_FILE_NAME bound to: DPram_32b.mif - type: string Parameter C_INIT_FILE bound to: DPram_32b.mem - type: string Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer Parameter C_DEFAULT_DATA bound to: 0 - type: string Parameter C_HAS_RSTA bound to: 0 - type: integer Parameter C_RST_PRIORITY_A bound to: CE - type: string Parameter C_RSTRAM_A bound to: 0 - type: integer Parameter C_INITA_VAL bound to: 0 - type: string Parameter C_HAS_ENA bound to: 0 - type: integer Parameter C_HAS_REGCEA bound to: 0 - type: integer Parameter C_USE_BYTE_WEA bound to: 0 - type: integer Parameter C_WEA_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer Parameter C_READ_WIDTH_A bound to: 32 - type: integer Parameter C_WRITE_DEPTH_A bound to: 1024 - type: integer Parameter C_READ_DEPTH_A bound to: 1024 - type: integer Parameter C_ADDRA_WIDTH bound to: 10 - type: integer Parameter C_HAS_RSTB bound to: 0 - type: integer Parameter C_RST_PRIORITY_B bound to: CE - type: string Parameter C_RSTRAM_B bound to: 0 - type: integer Parameter C_INITB_VAL bound to: 0 - type: string Parameter C_HAS_ENB bound to: 0 - type: integer Parameter C_HAS_REGCEB bound to: 0 - type: integer Parameter C_USE_BYTE_WEB bound to: 0 - type: integer Parameter C_WEB_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_B bound to: READ_FIRST - type: string Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer Parameter C_READ_WIDTH_B bound to: 32 - type: integer Parameter C_WRITE_DEPTH_B bound to: 1024 - type: integer Parameter C_READ_DEPTH_B bound to: 1024 - type: integer Parameter C_ADDRB_WIDTH bound to: 10 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 1 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_USE_SOFTECC bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_EN_ECC_PIPE bound to: 0 - type: integer Parameter C_READ_LATENCY_A bound to: 1 - type: integer Parameter C_READ_LATENCY_B bound to: 1 - type: integer Parameter C_HAS_INJECTERR bound to: 0 - type: integer Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string Parameter C_COMMON_CLK bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer Parameter C_USE_URAM bound to: 0 - type: integer Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 1 - type: string Parameter C_COUNT_18K_BRAM bound to: 0 - type: string Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 6.08305 mW - type: string INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_4' declared at '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_4' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/synth/DPram_32b.vhd:245] INFO: [Synth 8-256] done synthesizing module 'DPram_32b' (9#1) [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/synth/DPram_32b.vhd:74] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[9] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[8] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[7] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[3] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[2] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTB[0] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[3] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[2] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1] WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTB WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENB WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEB WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port INJECTDBITERR WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port INJECTSBITERR WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AClk WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_ARESETN WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWID[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWID[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWID[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWID[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[31] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[30] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[29] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[28] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[27] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[26] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[25] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[24] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[23] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[22] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[21] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[20] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[19] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[18] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[17] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[16] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[15] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[14] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[13] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[12] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[11] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[10] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[9] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[8] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWADDR[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[7] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[6] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[5] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[4] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[3] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWLEN[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWSIZE[2] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWSIZE[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWSIZE[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWBURST[1] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWBURST[0] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_AWVALID WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[31] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[30] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[29] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[28] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[27] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[26] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[25] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[24] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[23] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[22] WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_4_synth has unconnected port S_AXI_WDATA[21] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:53 ; elapsed = 00:01:45 . Memory (MB): peak = 2461.223 ; gain = 431.367 ; free physical = 8442 ; free virtual = 28108 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:53 ; elapsed = 00:01:46 . Memory (MB): peak = 2461.223 ; gain = 431.367 ; free physical = 8441 ; free virtual = 28107 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:53 ; elapsed = 00:01:46 . Memory (MB): peak = 2461.223 ; gain = 431.367 ; free physical = 8441 ; free virtual = 28107 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2461.223 ; gain = 0.000 ; free physical = 8431 ; free virtual = 28096 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/DPram_32b_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/DPram_32b_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8347 ; free virtual = 28013 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8347 ; free virtual = 28013 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:01:04 ; elapsed = 00:02:02 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8424 ; free virtual = 28090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:01:04 ; elapsed = 00:02:02 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8424 ; free virtual = 28090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/DPram_32b_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:04 ; elapsed = 00:02:02 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8424 ; free virtual = 28090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:04 ; elapsed = 00:02:02 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8426 ; free virtual = 28092 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:05 ; elapsed = 00:02:03 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8418 ; free virtual = 28092 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:13 ; elapsed = 00:02:17 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8302 ; free virtual = 27975 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:13 ; elapsed = 00:02:17 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8302 ; free virtual = 27975 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:13 ; elapsed = 00:02:17 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB36E1 | 1| +------+---------+------+ Report Instance Areas: +------+---------------------------------------------+------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------------+------------------------------+------+ |1 |top | | 1| |2 | U0 |blk_mem_gen_v8_4_4 | 1| |3 | inst_blk_mem_gen |blk_mem_gen_v8_4_4_synth | 1| |4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 1| |5 | \valid.cstr |blk_mem_gen_generic_cstr | 1| |6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| |7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| +------+---------------------------------------------+------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8301 ; free virtual = 27974 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 153 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:02:14 . Memory (MB): peak = 2525.250 ; gain = 431.367 ; free physical = 8351 ; free virtual = 28025 Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:02:21 . Memory (MB): peak = 2525.250 ; gain = 495.395 ; free physical = 8351 ; free virtual = 28025 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8413 ; free virtual = 28087 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8352 ; free virtual = 28026 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 18 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:39 ; elapsed = 00:03:07 . Memory (MB): peak = 2525.250 ; gain = 904.359 ; free physical = 8476 ; free virtual = 28150 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8476 ; free virtual = 28150 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/DPram_32b_synth_1/DPram_32b.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP DPram_32b, cache-ID = 4699fe5fa9456132 INFO: [Coretcl 2-1174] Renamed 6 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.250 ; gain = 0.000 ; free physical = 8475 ; free virtual = 28149 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/DPram_32b_synth_1/DPram_32b.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file DPram_32b_utilization_synth.rpt -pb DPram_32b_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Nov 3 23:29:06 2021...