*** Running vivado with args -log top_rod_efex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_efex.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_efex.tcl -notrace Command: link_design -top top_rod_efex -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/axi_ch0.dcp' for cell 'ILA_axi_slot4' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.dcp' for cell 'top_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.dcp' for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.dcp' for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'backplane/combined_ttc/ila_rx2_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'backplane/combined_ttc/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.dcp' for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/bulk_ila.dcp' for cell 'event_builder/bulk_0/bulkl_proc_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ppmux_ila.dcp' for cell 'event_builder/tob_processor_0/input_mux_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/event_fifo_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/default_reg_ila.dcp' for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.dcp' for cell 'fm_interface_1/clk_blk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'fm_interface_1/chan_0/L1ID_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_fullmode.dcp' for cell 'fm_interface_1/chan_0/ila_fm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'fm_interface_1/chan_0/vio_fm_reset' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'fm_interface_1/chan_0/ram0/RAM_0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'fm_interface_1/chan_0/u7/FIFO34b' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2652.000 ; gain = 0.000 ; free physical = 8295 ; free virtual = 27821 INFO: [Netlist 29-17] Analyzing 10303 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-549] Could not create 'SLEW' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DRIVE' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'DRIVE' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'ipbus_blk/axi4_subsys/spi_0_ss_iobuf_0' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 INFO: [Chipscope 16-324] Core: ILA_axi_slot4 UUID: 20490a14-d72f-506f-b0ba-f0582b5d57f1 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_RO_ctrl_inst UUID: 76a3beb1-890b-57f1-8968-8c8b4f7e3dd4 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b INFO: [Chipscope 16-324] Core: event_builder/bulk_0/bulkl_proc_probe UUID: 7d9dc169-40d5-56ff-9a38-42ad7dd0b67d INFO: [Chipscope 16-324] Core: event_builder/bulk_1/bulkl_proc_probe UUID: 48639c55-d7f5-5b3f-bf8a-c3e17dffdced INFO: [Chipscope 16-324] Core: event_builder/bulk_2/bulkl_proc_probe UUID: f79c214c-778a-503c-82e0-558ccd7036de INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_event_fifo UUID: 2d4141be-dbbe-5502-9616-cd358067f2ea INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila UUID: 1dd88742-1c2c-500e-b484-0986411f857c INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/input_mux_ila UUID: b512077d-1da3-504a-9240-4076ceba8348 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/ila_fm UUID: 6d2436f5-9843-5197-8e19-cddbe1593602 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/vio_fm_reset UUID: 2e7b6e8a-28c2-522f-b319-a31f8d50741a INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/ila_fm UUID: f7690143-a9e0-554d-977a-d2f37b0258d0 INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/vio_fm_reset UUID: f793cc7a-6b74-5a26-9770-d018214fd2d5 INFO: [Chipscope 16-324] Core: fm_interface_2/u0/ila_resetfsm UUID: c10d06e5-8b28-51b9-aae4-8af94262c1bd INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1281] Could not find module 'pp_ctrl_vio'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio.xdc will not be read for this module. Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_slot4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_slot4/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_slot4/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axi_ch0/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_slot4/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ppmux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/input_mux_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/default_reg_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/timeout_reg_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1281] Could not find module 'data_fifo_vio'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc will not be read for this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_RO_CTL_test/vio_RO_CTL_test.xdc] for cell 'backplane/readout_ctrl/vio_RO_ctrl_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/vio_top/vio_top.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] get_clocks: Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 3935.395 ; gain = 780.785 ; free physical = 7158 ; free virtual = 26683 WARNING: [Vivado 12-2489] -input_jitter contains time 0.249500 which will be rounded to 0.250 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc:57] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/clock_cross_fifo/clock_cross_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54] Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.pkt_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/tx_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/rd_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0/jtag_axi_engine_u/wr_cmd_fifo_i/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/reset_gen_ic.rstblk_ic/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_ic.af_rd_stg_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Vivado 12-3272] Current instance is the top level cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' of design 'design_1' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst_axis.tcl] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2/inst/gen_fifo.xpm_fifo_axis_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ben_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_ce_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[16] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[17] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[18] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[19] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[20] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[21] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[22] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[23] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[24] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[25] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[26] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[27] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[28] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[0] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[1] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[2] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_qwen_reg_reg[3] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rnw_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/IO_REGISTERS_I/mem_rpn_reg_reg has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[29] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[30] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/mem_a_int_reg[31] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4530.070 ; gain = 0.000 ; free physical = 7266 ; free virtual = 26794 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3177 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 2628 instances IOBUF => IOBUF (IBUF, OBUFT): 25 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 44 instances RAM64M => RAM64M (RAMD64E(x4)): 376 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 104 instances 119 Infos, 201 Warnings, 14 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:42 ; elapsed = 00:03:30 . Memory (MB): peak = 4530.070 ; gain = 2716.984 ; free physical = 7267 ; free virtual = 26794 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design -directive Explore INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_LE expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 4538.074 ; gain = 8.000 ; free physical = 7262 ; free virtual = 26789 Starting Cache Timing Information Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1c413f7bc Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7047 ; free virtual = 26575 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 6853 ; free virtual = 26389 Netlist sorting complete. Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 6852 ; free virtual = 26387 Phase 1 Generate And Synthesize Debug Cores | Checksum: 168eea1da Time (s): cpu = 00:02:34 ; elapsed = 00:04:40 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 6851 ; free virtual = 26386 Phase 2 Retarget INFO: [Opt 31-138] Pushed 49 inverter(s) to 381 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 163795b47 Time (s): cpu = 00:02:52 ; elapsed = 00:04:59 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7054 ; free virtual = 26589 INFO: [Opt 31-389] Phase Retarget created 352 cells and removed 1066 cells INFO: [Opt 31-1021] In phase Retarget, 2512 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: 1362b8f69 Time (s): cpu = 00:02:58 ; elapsed = 00:05:05 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7057 ; free virtual = 26592 INFO: [Opt 31-389] Phase Constant propagation created 372 cells and removed 1949 cells INFO: [Opt 31-1021] In phase Constant propagation, 1941 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD3085) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. Phase 4 Sweep | Checksum: 11592c813 Time (s): cpu = 00:03:59 ; elapsed = 00:06:06 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7049 ; free virtual = 26585 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 9633 cells INFO: [Opt 31-1021] In phase Sweep, 17712 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 11592c813 Time (s): cpu = 00:04:03 ; elapsed = 00:06:10 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7051 ; free virtual = 26586 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 11592c813 Time (s): cpu = 00:04:07 ; elapsed = 00:06:14 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7051 ; free virtual = 26586 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 11592c813 Time (s): cpu = 00:04:08 ; elapsed = 00:06:15 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7051 ; free virtual = 26587 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1963 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 352 | 1066 | 2512 | | Constant propagation | 372 | 1949 | 1941 | | Sweep | 11 | 9633 | 17712 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1963 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.55 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7052 ; free virtual = 26587 Ending Logic Optimization Task | Checksum: 12d2e00f9 Time (s): cpu = 00:04:13 ; elapsed = 00:06:20 . Memory (MB): peak = 4538.074 ; gain = 0.000 ; free physical = 7052 ; free virtual = 26587 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.097 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst INFO: [Power 33-23] Power model is not available for DNA_PORT_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 185 BRAM(s) out of a total of 262 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 100 WE to EN ports Number of BRAM Ports augmented: 107 newly gated: 112 Total Ports: 524 Ending PowerOpt Patch Enables Task | Checksum: 16e128140 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6751 ; free virtual = 26287 Ending Power Optimization Task | Checksum: 16e128140 Time (s): cpu = 00:02:22 ; elapsed = 00:02:10 . Memory (MB): peak = 5666.879 ; gain = 1128.805 ; free physical = 6926 ; free virtual = 26461 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 18cf407db Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6881 ; free virtual = 26417 Ending Final Cleanup Task | Checksum: 18cf407db Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6880 ; free virtual = 26415 Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69] all_fanout: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6680 ; free virtual = 26216 Finished Parsing XDC File [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6682 ; free virtual = 26217 Ending Netlist Obfuscation Task | Checksum: 18cf407db Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6682 ; free virtual = 26217 INFO: [Common 17-83] Releasing license: Implementation 173 Infos, 202 Warnings, 14 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:07:54 ; elapsed = 00:09:53 . Memory (MB): peak = 5666.879 ; gain = 1136.805 ; free physical = 6682 ; free virtual = 26218 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6682 ; free virtual = 26218 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 5666.879 ; gain = 0.000 ; free physical = 6538 ; free virtual = 26190 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:11 ; elapsed = 00:01:42 . Memory (MB): peak = 5666.883 ; gain = 0.004 ; free physical = 6601 ; free virtual = 26192 INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx Command: report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6585 ; free virtual = 26177 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/RSTRAMARSTRAM (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/AS[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port CK_SPI_LE expects both input and output buffering but the buffers are incomplete. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 22 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6580 ; free virtual = 26171 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: dfee139d Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6579 ; free virtual = 26171 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6579 ; free virtual = 26171 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c7e14696 Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6532 ; free virtual = 26127 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 242757259 Time (s): cpu = 00:02:09 ; elapsed = 00:02:11 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6162 ; free virtual = 25758 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 242757259 Time (s): cpu = 00:02:10 ; elapsed = 00:02:12 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6161 ; free virtual = 25757 Phase 1 Placer Initialization | Checksum: 242757259 Time (s): cpu = 00:02:11 ; elapsed = 00:02:13 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6153 ; free virtual = 25748 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1b1a3a162 Time (s): cpu = 00:02:33 ; elapsed = 00:02:36 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6047 ; free virtual = 25643 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 7827 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 2562 nets or cells. Created 0 new cell, deleted 2562 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-64] No nets found for fanout-optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-117] Net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I could not be optimized because driver event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 could not be replicated INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6033 ; free virtual = 25629 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 2562 | 2562 | 0 | 1 | 00:00:07 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:02 | | Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 2562 | 2562 | 0 | 9 | 00:00:09 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 14791d07c Time (s): cpu = 00:06:37 ; elapsed = 00:06:53 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6025 ; free virtual = 25620 Phase 2.2 Global Placement Core | Checksum: 1e16b8a93 Time (s): cpu = 00:06:46 ; elapsed = 00:07:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6004 ; free virtual = 25600 Phase 2 Global Placement | Checksum: 1e16b8a93 Time (s): cpu = 00:06:46 ; elapsed = 00:07:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6096 ; free virtual = 25692 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19ab8c8ba Time (s): cpu = 00:07:09 ; elapsed = 00:07:25 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6080 ; free virtual = 25676 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 188ba0380 Time (s): cpu = 00:07:55 ; elapsed = 00:08:13 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6061 ; free virtual = 25656 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1422a10a4 Time (s): cpu = 00:07:57 ; elapsed = 00:08:15 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6059 ; free virtual = 25655 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f0e1b59c Time (s): cpu = 00:08:00 ; elapsed = 00:08:18 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6058 ; free virtual = 25654 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 139a95811 Time (s): cpu = 00:08:42 ; elapsed = 00:09:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6079 ; free virtual = 25674 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: fec4a789 Time (s): cpu = 00:10:01 ; elapsed = 00:10:23 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5857 ; free virtual = 25452 Phase 3.6 Small Shape Detail Placement | Checksum: fec4a789 Time (s): cpu = 00:10:03 ; elapsed = 00:10:25 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5896 ; free virtual = 25492 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: f27b1a60 Time (s): cpu = 00:10:13 ; elapsed = 00:10:34 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5904 ; free virtual = 25500 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 12d2c499c Time (s): cpu = 00:10:19 ; elapsed = 00:10:41 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5904 ; free virtual = 25499 Phase 3 Detail Placement | Checksum: 12d2c499c Time (s): cpu = 00:10:21 ; elapsed = 00:10:42 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5905 ; free virtual = 25500 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 2a622d99 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net ipbus_blk/ipbus/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 2a622d99 Time (s): cpu = 00:11:42 ; elapsed = 00:12:05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5960 ; free virtual = 25556 INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.512. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 123ad7eb0 Time (s): cpu = 00:16:39 ; elapsed = 00:17:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5970 ; free virtual = 25566 Phase 4.1 Post Commit Optimization | Checksum: 123ad7eb0 Time (s): cpu = 00:16:41 ; elapsed = 00:17:03 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5970 ; free virtual = 25566 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 123ad7eb0 Time (s): cpu = 00:16:43 ; elapsed = 00:17:06 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5986 ; free virtual = 25582 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 123ad7eb0 Time (s): cpu = 00:16:45 ; elapsed = 00:17:08 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25627 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25627 Phase 4.4 Final Placement Cleanup | Checksum: 20f3ec458 Time (s): cpu = 00:16:46 ; elapsed = 00:17:09 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25627 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20f3ec458 Time (s): cpu = 00:16:48 ; elapsed = 00:17:11 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25627 Ending Placer Task | Checksum: 1bbb923dc Time (s): cpu = 00:16:48 ; elapsed = 00:17:11 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25627 INFO: [Common 17-83] Releasing license: Implementation 217 Infos, 224 Warnings, 14 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:17:03 ; elapsed = 00:17:27 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6224 ; free virtual = 25820 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6224 ; free virtual = 25820 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5873 ; free virtual = 25796 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:21 ; elapsed = 00:01:51 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6129 ; free virtual = 25800 INFO: [runtcl-4] Executing : report_io -file top_rod_efex_io_placed.rpt report_io: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.58 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6088 ; free virtual = 25759 INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed.rpt -pb top_rod_efex_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_efex_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.98 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6127 ; free virtual = 25801 INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed_1.rpt -pb top_rod_efex_utilization_placed_1.pb Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6061 ; free virtual = 25735 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.512 | TNS=-1052.256 | Phase 1 Physical Synthesis Initialization | Checksum: 1e7759fd6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5952 ; free virtual = 25627 Phase 2 SLR Crossing Optimization Phase 2 SLR Crossing Optimization | Checksum: 1e7759fd6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.512 | TNS=-1052.256 | Phase 3 Fanout Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 31 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 3 Fanout Optimization | Checksum: 1e7759fd6 Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 4 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Re-placed instance event_builder/fifo_layer/ch2/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]. Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__8 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Re-placed instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Re-placed instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Re-placed instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Re-placed instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Re-placed instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Re-placed instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Re-placed instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2 INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Re-placed instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Common 17-14] Message 'Physopt 32-663' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__10 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch11/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__10 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__5 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__5 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-661] Optimized 191 nets. Re-placed 191 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 191 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 191 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.183 | TNS=-1017.566 | Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 4 Single Cell Placement Optimization | Checksum: 18dc74fb6 Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 5 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__5/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 5 Multi Cell Placement Optimization | Checksum: 1b31660b0 Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5943 ; free virtual = 25618 Phase 6 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net state[0] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tvalid due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net gp_button_i due to MARK_DEBUG attribute. INFO: [Physopt 32-77] Pass 1. Identified 31 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/bulk_0/input_mux/s_tready_0. Rewired (signal push) event_builder/bulk_0/input_mux/current_chan[1] to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch0/norm_fifo.calo_fifo_i_2_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/bulk_0/input_mux/s_tready_2. Rewired (signal push) event_builder/bulk_0/input_mux/current_chan[0] to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/s_tready_5. Rewired (signal push) event_builder/tob_processor_0/input_mux/m_tready to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/CRC_reg[0]_0. Rewired (signal push) event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[18]_i_10_n_0 to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/s_tready_7. Rewired (signal push) event_builder/tob_processor_0/input_mux/m_tready to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/s_tready_0. Rewired (signal push) event_builder/tob_processor_0/input_mux/m_tready to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[14]_i_6_n_0. Rewired (signal push) event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[14]_i_9_n_0 to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/s_tready_8. Rewired (signal push) event_builder/tob_processor_0/input_mux/m_tready to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/s_tready_11. Rewired (signal push) event_builder/tob_processor_0/input_mux/m_tready to 1 loads. Replicated 0 times. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_190_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__106[11]. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_3. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[7]_i_8_n_0. Rewired (signal push) event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[9]_i_7_n_0 to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/bulk_0/input_mux/s_tready_3. Rewired (signal push) event_builder/bulk_0/input_mux/current_chan[1] to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_3_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/bulk_1/header_read_en. Rewired (signal push) event_builder/bulk_1/load_hdr_reg to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_7_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[19]_i_2_n_0. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__103[14]. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[5]_i_14_n_0. Rewired (signal push) event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[5]_i_3_n_0 to 1 loads. Replicated 0 times. INFO: [Physopt 32-232] Optimized 13 nets. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5934 ; free virtual = 25609 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.183 | TNS=-1011.651 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5934 ; free virtual = 25609 Phase 6 Rewire | Checksum: 17ce48d6b Time (s): cpu = 00:01:37 ; elapsed = 00:01:38 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5934 ; free virtual = 25609 Phase 7 Critical Cell Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[22] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[21] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[18] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[17] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[8] due to MARK_DEBUG attribute. INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 3 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 15 nets. Created 26 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 15 nets or cells. Created 26 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.160 | TNS=-975.181 | Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 7 Critical Cell Optimization | Checksum: 193714209 Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 8 Fanout Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 17 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5934 ; free virtual = 25608 Phase 8 Fanout Optimization | Checksum: 18046a279 Time (s): cpu = 00:02:16 ; elapsed = 00:02:18 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5934 ; free virtual = 25608 Phase 9 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-661] Optimized 87 nets. Re-placed 87 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 87 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 87 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.160 | TNS=-961.264 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 9 Single Cell Placement Optimization | Checksum: 206d59cc4 Time (s): cpu = 00:02:40 ; elapsed = 00:02:42 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 10 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__1/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-661] Optimized 1 net. Re-placed 2 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 2 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.160 | TNS=-960.978 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25609 Phase 10 Multi Cell Placement Optimization | Checksum: 17f8d43bb Time (s): cpu = 00:02:46 ; elapsed = 00:02:49 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25609 Phase 11 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net state[0] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tvalid due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net gp_button_i due to MARK_DEBUG attribute. INFO: [Physopt 32-77] Pass 1. Identified 14 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/bulk_0/input_mux/s_tready_0. Rewired (signal push) event_builder/bulk_0/input_mux/current_chan[0] to 1 loads. Replicated 0 times. INFO: [Physopt 32-242] Processed net event_builder/bulk_0/input_mux/s_tready_2. Rewired (signal push) event_builder/bulk_0/input_mux/current_chan[1] to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_7. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_5. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_0. Rewiring did not optimize the net. INFO: [Physopt 32-242] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN_1. Rewired (signal push) event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN to 1 loads. Replicated 0 times. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/chan_count_reg[3]. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/input_mux/s_tready_11. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 3 nets. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.160 | TNS=-960.518 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 11 Rewire | Checksum: 19d1ca135 Time (s): cpu = 00:02:52 ; elapsed = 00:02:55 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 12 Critical Cell Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[22] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[21] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[18] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[17] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[8] due to MARK_DEBUG attribute. INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-601] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Net driver event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica was replaced. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Replicated 2 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]. Replicated 2 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_6. Replicated 3 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_3. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/i___16_n_0. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 16 nets. Created 22 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 16 nets or cells. Created 22 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-938.549 | Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 12 Critical Cell Optimization | Checksum: 22f294dbf Time (s): cpu = 00:03:21 ; elapsed = 00:03:24 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 13 SLR Crossing Optimization Phase 13 SLR Crossing Optimization | Checksum: 22f294dbf Time (s): cpu = 00:03:22 ; elapsed = 00:03:25 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 14 Fanout Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 10 candidate nets for fanout optimization. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 14 Fanout Optimization | Checksum: 23d5cbe27 Time (s): cpu = 00:03:28 ; elapsed = 00:03:32 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 15 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN_1. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0_replica_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-661] Optimized 107 nets. Re-placed 107 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 107 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 107 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-914.990 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 15 Single Cell Placement Optimization | Checksum: 21964c956 Time (s): cpu = 00:03:51 ; elapsed = 00:03:55 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 16 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0_replica/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2/O INFO: [Physopt 32-661] Optimized 1 net. Re-placed 3 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 3 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-914.891 | Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 16 Multi Cell Placement Optimization | Checksum: 17d975e16 Time (s): cpu = 00:03:59 ; elapsed = 00:04:03 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5933 ; free virtual = 25608 Phase 17 Rewire INFO: [Physopt 32-246] Starting Signal Push optimization... INFO: [Physopt 32-712] Optimization is not feasible on net state[0] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tvalid due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net chan_enable due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net gp_button_i due to MARK_DEBUG attribute. INFO: [Physopt 32-77] Pass 1. Identified 7 candidate nets for rewire optimization. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/tob_processor_0/event_builder_0/m_axis_tready. Rewiring did not optimize the net. INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN_1. Rewiring did not optimize the net. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 17 Rewire | Checksum: 22b60688f Time (s): cpu = 00:04:02 ; elapsed = 00:04:07 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 18 Critical Cell Optimization WARNING: [Physopt 32-894] Found a constraint with the -through option on pin event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[22] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[21] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[18] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[17] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[16] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net fifo_s_tdata[8] due to MARK_DEBUG attribute. INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Replicated 2 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Replicated 1 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 2 times. INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch11/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Replicated 1 times. INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0. Replicated 1 times. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN_1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-232] Optimized 8 nets. Created 10 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 8 nets or cells. Created 10 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-914.467 | Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 18 Critical Cell Optimization | Checksum: 1ffd93d83 Time (s): cpu = 00:04:27 ; elapsed = 00:04:31 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 19 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 19 DSP Register Optimization | Checksum: 1ffd93d83 Time (s): cpu = 00:04:27 ; elapsed = 00:04:32 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 20 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 20 BRAM Register Optimization | Checksum: 1ffd93d83 Time (s): cpu = 00:04:28 ; elapsed = 00:04:32 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 21 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 21 URAM Register Optimization | Checksum: 1ffd93d83 Time (s): cpu = 00:04:28 ; elapsed = 00:04:33 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 22 Shift Register Optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-914.467 | Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 22 Shift Register Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:31 ; elapsed = 00:04:35 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 23 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 23 DSP Register Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:31 ; elapsed = 00:04:36 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 24 BRAM Register Optimization INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 24 BRAM Register Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:32 ; elapsed = 00:04:36 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 25 URAM Register Optimization INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 25 URAM Register Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:32 ; elapsed = 00:04:37 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 26 Shift Register Optimization INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 26 Shift Register Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:33 ; elapsed = 00:04:38 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 27 Critical Pin Optimization INFO: [Physopt 32-606] Identified 100 candidate nets for critical-pin optimization. INFO: [Physopt 32-608] Optimized 29 nets. Swapped 365 pins. INFO: [Physopt 32-775] End 1 Pass. Optimized 29 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 365 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.061 | TNS=-864.163 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 27 Critical Pin Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:34 ; elapsed = 00:04:39 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 28 Very High Fanout Optimization INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 801 to 162 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 802 to 163 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 865 to 178 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-1022] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' has -through timing constraint at pin '' or its immediate connected net. To preserve -through timing constraint its fanout number considered in optimization is changed from 866 to 179 and it is not considered a very high fanout net anymore. Please consider modifying/removing the '-through' timing constraint on the net segment or hierarchy pin. INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 28 Very High Fanout Optimization | Checksum: 195e1636c Time (s): cpu = 00:04:37 ; elapsed = 00:04:41 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 29 Single Cell Placement Optimization INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[5]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[6]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__4_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch5/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[1]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[2]. Did not re-place instance event_builder/fifo_layer/ch2/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[12]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[13]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[14]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[15]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[31]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[31] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[16]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[19]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[10]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[11]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[8]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[9]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[10]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[11] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[7]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[8] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[8]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[9] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[20]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[20] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[21]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[21] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[22]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[22] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/D[23]. Did not re-place instance event_builder/fifo_layer/ch3/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[23] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[17]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[28]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[28] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[29]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[29] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[30]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[30] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[26]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[26] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[27]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[27] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[2]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[2] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[3] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[15]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[16] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__9 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_0_repN. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__9_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[12]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[13] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[13]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[14] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[14]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[15] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[4]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[5] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[5]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[6] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[6]. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[7] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[17]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[18] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[18]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__0 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN_1. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__0_replica_1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[24]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[24] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/D[25]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[25] INFO: [Physopt 32-661] Optimized 37 nets. Re-placed 37 instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 37 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 37 existing cells INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.020 | TNS=-852.794 | Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 29 Single Cell Placement Optimization | Checksum: 1fa65b697 Time (s): cpu = 00:04:56 ; elapsed = 00:05:02 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 30 Multi Cell Placement Optimization INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica/Q INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]_replica/Q INFO: [Physopt 32-661] Optimized 0 net. Re-placed 0 instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 30 Multi Cell Placement Optimization | Checksum: 1917c8c1e Time (s): cpu = 00:05:05 ; elapsed = 00:05:11 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 31 SLR Crossing Optimization Phase 31 SLR Crossing Optimization | Checksum: 1917c8c1e Time (s): cpu = 00:05:06 ; elapsed = 00:05:11 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5932 ; free virtual = 25608 Phase 32 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.020 | TNS=-852.794 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[12] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[11]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_reg_replica/Q INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/aurora_reset_pulse/pulse_out_i_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.005 | TNS=-851.958 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[18] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/self_reset_inst/D[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__6_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.976 | TNS=-848.239 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[10] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[9]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Replicated 1 times. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.973 | TNS=-846.853 | INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.960 | TNS=-846.733 | INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.954 | TNS=-846.593 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica/Q INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__3/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch4/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__3_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch4/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.953 | TNS=-844.434 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][1]_replica_12 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][1]_replica_12/Q INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Replicated 1 times. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.940 | TNS=-843.726 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[17] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[16]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]_replica/Q INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2_replica/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch0/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.926 | TNS=-842.865 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[7] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/chan_reset/self_reset_inst/D[7]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reg_reg[0][0]/Q INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0] was not replicated. INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/Q[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Did not re-place instance event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__8/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__8_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.925 | TNS=-842.065 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][1]_replica_12 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][1]_replica_12/Q INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/backplane_control[1]_repN_12. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6_comp INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__6_comp/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-601] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Net driver event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__6_comp was replaced. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch7/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.923 | TNS=-842.405 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/reset_count_i_reg[4] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/D[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i0__0. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/reset_count_i[0]_i_1__7_comp. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-842.074 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ipbus_blk/ipbus/example_clocks/clock_generator/clkout3. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/tobsel. Did not re-place instance event_builder/tob_processor_0/event_builder_0/tobsel_reg INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/tobsel. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-841.832 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]. Replicated 4 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-841.073 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/current_chan[0]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[0] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/current_chan[0]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[0]/Q INFO: [Physopt 32-81] Processed net event_builder/bulk_0/input_mux/current_chan[0]. Replicated 2 times. INFO: [Physopt 32-735] Processed net event_builder/bulk_0/input_mux/current_chan[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-840.869 | INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[4]. Optimizations did not improve timing on the net. INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]. Replicated 2 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-840.122 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-839.780 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-840.024 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-839.735 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]_replica_3/Q INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i. Did not re-place instance event_builder/bkpln_rst_pulse_stretcher/pulse_out_i_reg INFO: [Physopt 32-735] Processed net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-839.276 | INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Replicated 4 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-838.447 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[13]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-838.255 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/current_chan[1]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[1] INFO: [Physopt 32-662] Processed net event_builder/bulk_0/input_mux/current_chan[1]. Did not re-place instance event_builder/bulk_0/input_mux/chan_count_reg[1]/Q INFO: [Physopt 32-81] Processed net event_builder/bulk_0/input_mux/current_chan[1]. Replicated 2 times. INFO: [Physopt 32-735] Processed net event_builder/bulk_0/input_mux/current_chan[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-837.543 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[13]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-837.441 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[1]_replica_1 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[1]_replica_1/Q INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Replicated 1 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-837.471 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]/Q INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Replicated 4 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-837.303 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo_i_4__1 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo_i_4__1/O INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch2/m_axis_tready was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/m_axis_tready. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-837.050 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.916 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[8]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.741 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.611 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/D[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.354 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.242 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[5] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[5]/Q INFO: [Physopt 32-712] Optimization is not feasible on net state[5] due to MARK_DEBUG attribute. INFO: [Physopt 32-712] Optimization is not feasible on net state[5] due to MARK_DEBUG attribute. INFO: [Physopt 32-571] Net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5] was not replicated. INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.128 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[13]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg[12] INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[13]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0]/Q INFO: [Physopt 32-712] Optimization is not feasible on net state[0] due to MARK_DEBUG attribute. INFO: [Physopt 32-572] Net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/m_tdata_pipe_reg_reg[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-836.024 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica/Q INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_2_INST_0 INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.913 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg_n_0_[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.798 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.746 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/m_tdata_pipe_reg_reg[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[12]_i_2_rewire INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/m_tdata_pipe_reg_reg[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[12]_i_2_rewire/O INFO: [Physopt 32-710] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in[12]. Critical path length was reduced through logic transformation on cell event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[12]_i_1_comp. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/m_tdata_pipe_reg_reg[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.660 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_4. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.616 | INFO: [Physopt 32-662] Processed net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i. Did not re-place instance event_builder/bkpln_rst_pulse_stretcher/pulse_out_i_reg INFO: [Physopt 32-662] Processed net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i. Did not re-place instance event_builder/bkpln_rst_pulse_stretcher/pulse_out_i_reg/Q INFO: [Physopt 32-572] Net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/bkpln_rst_pulse_stretcher/pulse_out_i. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count[4]_i_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count[4]_i_3/O INFO: [Physopt 32-710] Processed net event_builder/tob_processor_0/input_mux/chan_count[2]_i_1_n_0. Critical path length was reduced through logic transformation on cell event_builder/tob_processor_0/input_mux/chan_count[2]_i_1_comp. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.527 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.474 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/D[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.446 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.387 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo_i_4__4_rewire INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo_i_4__4_rewire/O INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Replicated 1 times. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch5/m_axis_tready. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.333 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.279 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[9]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg[8] INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[9]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__42[8]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[8]_i_2 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__42[8]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[8]_i_2/O INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__42[8]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.211 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch3/m_axis_tready. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.161 | INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Replicated 4 times. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.147 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[12]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg[11] INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[12]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__106[11]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.061 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_2_INST_0 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Did not re-place instance event_builder/tob_processor_0/input_mux/s_tready_2_INST_0/O INFO: [Physopt 32-710] Processed net event_builder/fifo_layer/ch2/m_axis_tready. Critical path length was reduced through logic transformation on cell event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo_i_4__1_comp. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/s_tready_2. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.059 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[4]_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-835.023 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_s_reg_n_0_[19]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.985 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1 WARNING: [Physopt 32-722] Net with MARK_DEBUG TRUE property was optimized: event_builder/tob_processor_0/event_builder_0/fifo_s_tvalid Resolution: To prevent optimization apply the following XDC constraint before phys_opt_design: set_property DONT_TOUCH TRUE [get_nets event_builder/tob_processor_0/event_builder_0/fifo_s_tvalid] INFO: [Physopt 32-710] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0. Critical path length was reduced through logic transformation on cell event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_1_comp. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.950 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.918 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/m_axis_tready_repN. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo_i_4__4_rewire_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/m_axis_tready_repN. Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo_i_4__4_rewire_replica/O INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch5/m_axis_tready_repN. Rewiring did not optimize the net. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch5/m_axis_tready_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.864 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/m_tdata_pipe_reg_reg[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.835 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.806 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0]_replica INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[0]_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count[4]_i_3 INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count[4]_i_3/O INFO: [Physopt 32-710] Processed net event_builder/tob_processor_0/input_mux/chan_count[0]_i_1_n_0. Critical path length was reduced through logic transformation on cell event_builder/tob_processor_0/input_mux/chan_count[0]_i_1_comp. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/chan_count[4]_i_3_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.780 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ipbus_blk/ipbus/example_clocks/clock_generator/clkout3. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/D[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[2]_repN_3. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.768 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.755 | INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/D[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]_replica/Q INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/input_mux/current_chan[3]_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4 INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/fifo_layer/ch2/m_axis_tready. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.715 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/input_mux/current_chan[1]_repN_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.680 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[9]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg[8] INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[9]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0] INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[0]/Q INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg[8]_i_4_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.655 | INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[18]. Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_reg[17] INFO: [Physopt 32-702] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__103[14]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.644 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.633 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__43[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.624 | INFO: [Physopt 32-735] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.616 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.616 | Phase 32 Critical Path Optimization | Checksum: 1cb209b29 Time (s): cpu = 00:06:29 ; elapsed = 00:06:35 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5928 ; free virtual = 25607 Phase 33 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.616 | INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1] was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-572] Net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1 was not replicated. Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets . INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ipbus_blk/ipbus/example_clocks/clock_generator/clkout3. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[4] INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/self_reset_inst/gap_count_reg[19]_0[3]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1] INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/reg_reg[0][1]/Q INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_autoreset_disable/Q[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/i___9_i_2__7_replica/O INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/Aurora_channel_control_reg/pulse_in_repN. Optimizations did not improve timing on the net. INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Did not re-place instance event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count[0]_i_1__7 INFO: [Physopt 32-702] Processed net event_builder/fifo_layer/ch8/gen_reg.status_regs/chan_reset/stretcher/gap_count0__1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ipbus_blk/ipbus/example_clocks/clock_generator/clkout3. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.919 | TNS=-834.616 | Phase 33 Critical Path Optimization | Checksum: 19fad5dd2 Time (s): cpu = 00:06:40 ; elapsed = 00:06:47 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5928 ; free virtual = 25607 Phase 34 BRAM Enable Optimization Phase 34 BRAM Enable Optimization | Checksum: 19fad5dd2 Time (s): cpu = 00:06:41 ; elapsed = 00:06:48 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5928 ; free virtual = 25607 INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5935 ; free virtual = 25613 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.919 | TNS=-834.616 | Summary of Physical Synthesis Optimizations ============================================ ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 36 | 3 | 00:00:24 | | Single Cell Placement | 0.370 | 83.535 | 0 | 0 | 422 | 0 | 4 | 00:01:32 | | Multi Cell Placement | 0.000 | 0.385 | 0 | 0 | 2 | 0 | 4 | 00:00:29 | | Rewire | 0.000 | 6.375 | 0 | 0 | 16 | 76 | 3 | 00:00:20 | | Critical Cell | 0.096 | 58.863 | 58 | 0 | 39 | 345 | 3 | 00:01:24 | | SLR Crossing | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 3 | 00:00:00 | | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | BRAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | URAM Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 2 | 00:00:00 | | Shift Register | 0.000 | 0.000 | 2 | 0 | 2 | 0 | 2 | 00:00:02 | | Critical Pin | 0.026 | 50.304 | 0 | 0 | 29 | 0 | 1 | 00:00:01 | | Very High Fanout | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:02 | | BRAM Enable | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.101 | 18.178 | 26 | 0 | 66 | 0 | 2 | 00:01:34 | | Total | 0.593 | 217.640 | 86 | 0 | 576 | 457 | 33 | 00:05:48 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5935 ; free virtual = 25613 Ending Physical Synthesis Task | Checksum: 1865fa449 Time (s): cpu = 00:06:42 ; elapsed = 00:06:49 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5947 ; free virtual = 25626 INFO: [Common 17-83] Releasing license: Implementation 1636 Infos, 231 Warnings, 14 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:07:44 ; elapsed = 00:07:51 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6077 ; free virtual = 25756 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6077 ; free virtual = 25756 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5744 ; free virtual = 25747 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:21 ; elapsed = 00:01:52 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 6003 ; free virtual = 25757 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Checksum: PlaceDB: e2730f34 ConstDB: 0 ShapeSum: 11fcbe7b RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d2cee3a8 Time (s): cpu = 00:02:12 ; elapsed = 00:02:13 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5598 ; free virtual = 25352 Post Restoration Checksum: NetGraph: 516526e1 NumContArr: 8169bcc7 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d2cee3a8 Time (s): cpu = 00:02:14 ; elapsed = 00:02:14 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5600 ; free virtual = 25354 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: d2cee3a8 Time (s): cpu = 00:02:15 ; elapsed = 00:02:16 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5580 ; free virtual = 25333 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: d2cee3a8 Time (s): cpu = 00:02:16 ; elapsed = 00:02:16 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5580 ; free virtual = 25333 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1642f371b Time (s): cpu = 00:04:22 ; elapsed = 00:04:26 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5482 ; free virtual = 25236 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.102 | TNS=0.000 | WHS=-2.356 | THS=-6958.268| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: ea1a830c Time (s): cpu = 00:05:17 ; elapsed = 00:05:21 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5447 ; free virtual = 25201 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.102 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 15d74b6cc Time (s): cpu = 00:05:19 ; elapsed = 00:05:24 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5440 ; free virtual = 25194 Phase 2 Router Initialization | Checksum: 16695c19e Time (s): cpu = 00:05:19 ; elapsed = 00:05:24 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5440 ; free virtual = 25194 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 180033 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 180033 Number of Partially Routed Nets = 0 Number of Node Overlaps = 6 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: f4291488 Time (s): cpu = 00:06:26 ; elapsed = 00:06:32 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5409 ; free virtual = 25163 INFO: [Route 35-580] Design has 8 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[0]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[2]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_2/DIADI[1]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[2]| | CLK_125_pin | clkout3 | ipbus_blk/ipbus/ipbus/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[2]| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 15585 Number of Nodes with overlaps = 1521 Number of Nodes with overlaps = 300 Number of Nodes with overlaps = 113 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.225 | TNS=-0.308 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1e05f85bf Time (s): cpu = 00:12:34 ; elapsed = 00:12:46 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5400 ; free virtual = 25154 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1385 Number of Nodes with overlaps = 157 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.109 | TNS=-0.163 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: e9593654 Time (s): cpu = 00:13:40 ; elapsed = 00:13:54 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5405 ; free virtual = 25159 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 1389 Number of Nodes with overlaps = 241 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.015 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1c0299d35 Time (s): cpu = 00:15:01 ; elapsed = 00:15:17 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5403 ; free virtual = 25157 Phase 4 Rip-up And Reroute | Checksum: 1c0299d35 Time (s): cpu = 00:15:02 ; elapsed = 00:15:18 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5403 ; free virtual = 25157 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1c0299d35 Time (s): cpu = 00:15:03 ; elapsed = 00:15:18 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5403 ; free virtual = 25157 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1c0299d35 Time (s): cpu = 00:15:03 ; elapsed = 00:15:19 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5403 ; free virtual = 25157 Phase 5 Delay and Skew Optimization | Checksum: 1c0299d35 Time (s): cpu = 00:15:03 ; elapsed = 00:15:19 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5403 ; free virtual = 25157 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 144686803 Time (s): cpu = 00:15:26 ; elapsed = 00:15:42 . Memory (MB): peak = 5666.883 ; gain = 0.000 ; free physical = 5398 ; free virtual = 25152 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.102 | TNS=0.000 | WHS=-1.068 | THS=-29.973| Phase 6.1.2 Lut RouteThru Assignment for hold Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: e0f5cfa8 Time (s): cpu = 00:22:18 ; elapsed = 00:22:36 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5349 ; free virtual = 25103 Phase 6.1 Hold Fix Iter | Checksum: e0f5cfa8 Time (s): cpu = 00:22:19 ; elapsed = 00:22:36 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5349 ; free virtual = 25103 Phase 6.2 Additional Hold Fix INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.517 | TNS=-3.203 | WHS=-0.115 | THS=-20.320| Phase 6.2 Additional Hold Fix | Checksum: 1b0010739 Time (s): cpu = 00:24:04 ; elapsed = 00:24:22 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5295 ; free virtual = 25049 WARNING: [Route 35-468] The router encountered 1 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are: event_builder/fifo_layer/ch6/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D Phase 6 Post Hold Fix | Checksum: 21007726e Time (s): cpu = 00:24:12 ; elapsed = 00:24:29 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5365 ; free virtual = 25119 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 1d1a09676 Time (s): cpu = 00:24:46 ; elapsed = 00:25:03 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5384 ; free virtual = 25138 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.517 | TNS=-3.203 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 1d1a09676 Time (s): cpu = 00:24:46 ; elapsed = 00:25:04 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5384 ; free virtual = 25138 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.72806 % Global Horizontal Routing Utilization = 6.50118 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 82.8829%, No Congested Regions. South Dir 1x1 Area, Max Cong = 71.1712%, No Congested Regions. East Dir 1x1 Area, Max Cong = 86.7647%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X67Y209 -> INT_R_X67Y209 INT_L_X110Y199 -> INT_L_X110Y199 INT_L_X56Y161 -> INT_L_X56Y161 West Dir 1x1 Area, Max Cong = 92.6471%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X56Y161 -> INT_L_X56Y161 INT_R_X79Y135 -> INT_R_X79Y135 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Phase 8 Route finalize | Checksum: 1d1a09676 Time (s): cpu = 00:24:48 ; elapsed = 00:25:06 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5379 ; free virtual = 25133 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1d1a09676 Time (s): cpu = 00:24:49 ; elapsed = 00:25:07 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5376 ; free virtual = 25130 Phase 10 Depositing Routes INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y2/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y3/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y2/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y23/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y22/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y21/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y20/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y3/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y27/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y26/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y37/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y4/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y5/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y6/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y1/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y3/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y24/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y25/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y6/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y28/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y29/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK1 Phase 10 Depositing Routes | Checksum: 1f253985c Time (s): cpu = 00:25:05 ; elapsed = 00:25:23 . Memory (MB): peak = 5771.879 ; gain = 104.996 ; free physical = 5372 ; free virtual = 25126 Phase 11 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5771.879 ; gain = 0.000 ; free physical = 5280 ; free virtual = 25034 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.229. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: eb96d24d Time (s): cpu = 00:03:08 ; elapsed = 00:03:10 . Memory (MB): peak = 6050.848 ; gain = 278.969 ; free physical = 5217 ; free virtual = 24971 Phase 11 Incr Placement Change | Checksum: 1f253985c Time (s): cpu = 00:28:19 ; elapsed = 00:28:38 . Memory (MB): peak = 6052.922 ; gain = 386.039 ; free physical = 5217 ; free virtual = 24971 Phase 12 Build RT Design Phase 12 Build RT Design | Checksum: 11f41c66f Time (s): cpu = 00:29:11 ; elapsed = 00:29:30 . Memory (MB): peak = 6052.922 ; gain = 386.039 ; free physical = 5119 ; free virtual = 24873 Post Restoration Checksum: NetGraph: f0e995b0 NumContArr: e35f9aba Constraints: 0 Timing: 0 Phase 13 Router Initialization Phase 13.1 Create Timer Phase 13.1 Create Timer | Checksum: 1d449306a Time (s): cpu = 00:29:18 ; elapsed = 00:29:38 . Memory (MB): peak = 6052.922 ; gain = 386.039 ; free physical = 5154 ; free virtual = 24908 Phase 13.2 Fix Topology Constraints Phase 13.2 Fix Topology Constraints | Checksum: 1d449306a Time (s): cpu = 00:29:20 ; elapsed = 00:29:40 . Memory (MB): peak = 6052.922 ; gain = 386.039 ; free physical = 5134 ; free virtual = 24888 Phase 13.3 Pre Route Cleanup Phase 13.3 Pre Route Cleanup | Checksum: 127d732ab Time (s): cpu = 00:29:21 ; elapsed = 00:29:41 . Memory (MB): peak = 6052.922 ; gain = 386.039 ; free physical = 5134 ; free virtual = 24888 Number of Nodes with overlaps = 0 Phase 13.4 Update Timing Phase 13.4 Update Timing | Checksum: 2746c9b3e Time (s): cpu = 00:31:13 ; elapsed = 00:31:33 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 5000 ; free virtual = 24754 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.170 | TNS=0.000 | WHS=-2.336 | THS=-6936.896| Phase 13.5 Update Timing for Bus Skew Phase 13.5.1 Update Timing Phase 13.5.1 Update Timing | Checksum: 19c26c388 Time (s): cpu = 00:32:10 ; elapsed = 00:32:31 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.170 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 13.5 Update Timing for Bus Skew | Checksum: 1b89eb358 Time (s): cpu = 00:32:13 ; elapsed = 00:32:33 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4952 ; free virtual = 24706 Phase 13 Router Initialization | Checksum: 24ca67a5e Time (s): cpu = 00:32:14 ; elapsed = 00:32:34 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4960 ; free virtual = 24714 Router Utilization Summary Global Vertical Routing Utilization = 6.72484 % Global Horizontal Routing Utilization = 6.49781 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 107 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 38 Number of Partially Routed Nets = 69 Number of Node Overlaps = 0 Phase 14 Initial Routing Phase 14 Initial Routing | Checksum: 1a6c62262 Time (s): cpu = 00:32:43 ; elapsed = 00:33:04 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4951 ; free virtual = 24705 INFO: [Route 35-580] Design has 76 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch0/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch2/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch10/gen_reg.status_regs/Aurora_channel_up_timer_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch1/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| | CLK_125_pin | clkout3 | event_builder/fifo_layer/ch9/gen_reg.status_regs/Aurora_self_reset_count_reg/rsync/m1_reg/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 15 Rip-up And Reroute Phase 15.1 Global Iteration 0 Number of Nodes with overlaps = 1889 Number of Nodes with overlaps = 708 Number of Nodes with overlaps = 211 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.065 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 15.1 Global Iteration 0 | Checksum: 18bbc65d9 Time (s): cpu = 00:34:53 ; elapsed = 00:35:17 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 Phase 15 Rip-up And Reroute | Checksum: 18bbc65d9 Time (s): cpu = 00:34:53 ; elapsed = 00:35:17 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 Phase 16 Delay and Skew Optimization Phase 16.1 Delay CleanUp Phase 16.1.1 Update Timing Phase 16.1.1 Update Timing | Checksum: 13bb11e75 Time (s): cpu = 00:35:15 ; elapsed = 00:35:39 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4953 ; free virtual = 24707 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.107 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 16.1 Delay CleanUp | Checksum: a1591a79 Time (s): cpu = 00:35:16 ; elapsed = 00:35:40 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 Phase 16.2 Clock Skew Optimization Phase 16.2 Clock Skew Optimization | Checksum: a1591a79 Time (s): cpu = 00:35:16 ; elapsed = 00:35:40 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 Phase 16 Delay and Skew Optimization | Checksum: a1591a79 Time (s): cpu = 00:35:17 ; elapsed = 00:35:41 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4968 ; free virtual = 24722 Phase 17 Post Hold Fix Phase 17.1 Hold Fix Iter Phase 17.1.1 Update Timing Phase 17.1.1 Update Timing | Checksum: 17146e189 Time (s): cpu = 00:35:44 ; elapsed = 00:36:08 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4978 ; free virtual = 24732 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.107 | TNS=0.000 | WHS=-0.442 | THS=-21.108| Phase 17.1 Hold Fix Iter | Checksum: 14f60724e Time (s): cpu = 00:35:49 ; elapsed = 00:36:13 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4948 ; free virtual = 24702 Phase 17 Post Hold Fix | Checksum: 1bc5956f6 Time (s): cpu = 00:35:50 ; elapsed = 00:36:14 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4947 ; free virtual = 24701 Phase 18 Timing Verification Phase 18.1 Update Timing Phase 18.1 Update Timing | Checksum: 12f0d66ed Time (s): cpu = 00:36:26 ; elapsed = 00:36:50 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4972 ; free virtual = 24726 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.107 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18 Timing Verification | Checksum: 12f0d66ed Time (s): cpu = 00:36:26 ; elapsed = 00:36:50 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4972 ; free virtual = 24726 Phase 19 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.72551 % Global Horizontal Routing Utilization = 6.49538 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 19 Route finalize | Checksum: 12f0d66ed Time (s): cpu = 00:36:28 ; elapsed = 00:36:52 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4969 ; free virtual = 24723 Phase 20 Verifying routed nets Verification completed successfully Phase 20 Verifying routed nets | Checksum: 12f0d66ed Time (s): cpu = 00:36:29 ; elapsed = 00:36:53 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4966 ; free virtual = 24720 Phase 21 Depositing Routes Phase 21 Depositing Routes | Checksum: f62f5c01 Time (s): cpu = 00:36:44 ; elapsed = 00:37:08 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 4969 ; free virtual = 24723 Phase 22 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.107 | TNS=0.000 | WHS=0.051 | THS=0.000 | INFO: [Route 35-61] The design met the timing requirement. Phase 22 Post Router Timing | Checksum: eb28cb7b Time (s): cpu = 00:38:05 ; elapsed = 00:38:29 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 5089 ; free virtual = 24843 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:38:06 ; elapsed = 00:38:30 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 5514 ; free virtual = 25268 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 1721 Infos, 232 Warnings, 14 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:38:35 ; elapsed = 00:39:00 . Memory (MB): peak = 6102.922 ; gain = 436.039 ; free physical = 5514 ; free virtual = 25268 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex... INFO: [Hog:GetVerFromSHA-0] No tag contains 24deccc, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 47E150E, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetVerFromSHA-0] No tag contains 341D2CC, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Git describe set to: v0.3.1-9-g47e150e INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_efex was modified... INFO: [Hog:GetVerFromSHA-0] No tag contains 24deccc, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 47E150E, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetVerFromSHA-0] No tag contains 341D2CC, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] The git SHA value 47e150e will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 6102.922 ; gain = 0.000 ; free physical = 5515 ; free virtual = 25269 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 6102.922 ; gain = 0.000 ; free physical = 5112 ; free virtual = 25258 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:31 ; elapsed = 00:02:04 . Memory (MB): peak = 6102.926 ; gain = 0.004 ; free physical = 5418 ; free virtual = 25263 INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_routed.rpt -pb top_rod_efex_drc_routed.pb -rpx top_rod_efex_drc_routed.rpx Command: report_drc -file top_rod_efex_drc_routed.rpt -pb top_rod_efex_drc_routed.pb -rpx top_rod_efex_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 6102.926 ; gain = 0.000 ; free physical = 5443 ; free virtual = 25287 INFO: [runtcl-4] Executing : report_methodology -file top_rod_efex_methodology_drc_routed.rpt -pb top_rod_efex_methodology_drc_routed.pb -rpx top_rod_efex_methodology_drc_routed.rpx Command: report_methodology -file top_rod_efex_methodology_drc_routed.rpt -pb top_rod_efex_methodology_drc_routed.pb -rpx top_rod_efex_methodology_drc_routed.rpx INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:22 ; elapsed = 00:02:25 . Memory (MB): peak = 6102.926 ; gain = 0.000 ; free physical = 5493 ; free virtual = 25339 INFO: [runtcl-4] Executing : report_power -file top_rod_efex_power_routed.rpt -pb top_rod_efex_power_summary_routed.pb -rpx top_rod_efex_power_routed.rpx Command: report_power -file top_rod_efex_power_routed.rpt -pb top_rod_efex_power_summary_routed.pb -rpx top_rod_efex_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUP_INCLUDE.GEN_7Series_STARTUP.STARTUPE2_inst INFO: [Power 33-23] Power model is not available for DNA_PORT_inst INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1751 Infos, 233 Warnings, 14 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:48 ; elapsed = 00:01:34 . Memory (MB): peak = 6134.922 ; gain = 31.996 ; free physical = 5378 ; free virtual = 25240 INFO: [runtcl-4] Executing : report_route_status -file top_rod_efex_route_status.rpt -pb top_rod_efex_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_rod_efex_timing_summary_routed.rpt -pb top_rod_efex_timing_summary_routed.pb -rpx top_rod_efex_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 6134.922 ; gain = 0.000 ; free physical = 5297 ; free virtual = 25171 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_rod_efex_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_rod_efex_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 6134.922 ; gain = 0.000 ; free physical = 5290 ; free virtual = 25165 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_rod_efex_bus_skew_routed.rpt -pb top_rod_efex_bus_skew_routed.pb -rpx top_rod_efex_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_routed_1.rpt -pb top_rod_efex_drc_routed_1.pb -rpx top_rod_efex_drc_routed_1.rpx Command: report_drc -file top_rod_efex_drc_routed_1.rpt -pb top_rod_efex_drc_routed_1.pb -rpx top_rod_efex_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 6134.922 ; gain = 0.000 ; free physical = 5252 ; free virtual = 25131 INFO: [runtcl-4] Executing : report_power -file top_rod_efex_power_routed_1.rpt -pb top_rod_efex_power_summary_routed_1.pb -rpx top_rod_efex_power_routed_1.rpx Command: report_power -file top_rod_efex_power_routed_1.rpt -pb top_rod_efex_power_summary_routed_1.pb -rpx top_rod_efex_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 1763 Infos, 235 Warnings, 14 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:41 ; elapsed = 00:00:32 . Memory (MB): peak = 6134.922 ; gain = 0.000 ; free physical = 5251 ; free virtual = 25146 INFO: [runtcl-4] Executing : report_timing_summary -file top_rod_efex_timing_summary_routed_1.rpt -pb top_rod_efex_timing_summary_routed_1.pb -rpx top_rod_efex_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 6134.922 ; gain = 0.000 ; free physical = 5245 ; free virtual = 25142 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Fri Nov 5 14:16:10 2021... *** Running vivado with args -log top_rod_efex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_efex.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_rod_efex.tcl -notrace Command: open_checkpoint top_rod_efex_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1595.273 ; gain = 0.000 ; free physical = 9060 ; free virtual = 28952 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2409.602 ; gain = 1.992 ; free physical = 8126 ; free virtual = 28019 INFO: [Netlist 29-17] Analyzing 10267 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3988.180 ; gain = 229.012 ; free physical = 6678 ; free virtual = 26571 Restored from archive | CPU: 14.810000 secs | Memory: 218.662231 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3988.180 ; gain = 229.012 ; free physical = 6678 ; free virtual = 26571 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3988.180 ; gain = 0.000 ; free physical = 6707 ; free virtual = 26600 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3170 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 2628 instances IOBUF => IOBUF (IBUF, OBUFT): 24 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 50 instances RAM64M => RAM64M (RAMD64E(x4)): 368 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 73 instances RAM64X1S => RAM64X1S (RAMS64E): 11 instances SRLC32E => SRL16E: 16 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:02:04 ; elapsed = 00:03:42 . Memory (MB): peak = 3988.180 ; gain = 2392.910 ; free physical = 6707 ; free virtual = 26600 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force top_rod_efex.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'ethernet_mac_rgmii' (ethernet_mac_rgmii_block) was generated with multiple features: IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license. IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer ipbus_blk/axi4_subsys/spi_0_sck_iobuf/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. WARNING: [DRC PDRC-62] SLICEM_5lutO5_B5: Dangling output pin O5 on site SLICE_X102Y197:B5LUT. For this programming the O5 output pin should have a signal. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRARDADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[5] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[6] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[1]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[7] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[2]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[8] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[3]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ADDRBWRADDR[9] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1[4]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/tmp_ram_rd_en) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENBWREN (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/RSTRAMARSTRAM (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/AS[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[2] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gpf.wrpf/gpf1.prog_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram has an input control pin fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/WEBWE[3] (net: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/E[0]) which is driven by a register (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 1711 net(s) have no routable loads. The problem bus(es) and/or net(s) are CHANNEL_STAT_3[3], CHANNEL_STAT_3[13], CHANNEL_STAT_3[14], CHANNEL_STAT_3[15], CHANNEL_STAT_3[16], CHANNEL_STAT_3[17], CHANNEL_STAT_3[18], CHANNEL_STAT_3[19], CHANNEL_STAT_3[20], CHANNEL_STAT_3[21], CHANNEL_STAT_3[22], CHANNEL_STAT_3[23], CHANNEL_STAT_4[3], CHANNEL_STAT_4[13], CHANNEL_STAT_4[14]... and (the first 15 of 647 listed). INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-165] writefirst: Synchronous clocking is detected for BRAM (ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 24 Warnings, 6 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./top_rod_efex.bit... Writing bitstream ./top_rod_efex.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Nov 5 14:24:58 2021. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 48 Infos, 25 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:04:35 ; elapsed = 00:04:44 . Memory (MB): peak = 4917.469 ; gain = 925.320 ; free physical = 6493 ; free virtual = 26446 source /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-bitstream.tcl Post-Bitstream proj_dir /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex... INFO: [Hog:GetVerFromSHA-0] No tag contains 24deccc, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 47E150E, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:GetVerFromSHA-0] No tag contains 341D2CC, will use most recent tag v0.3.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Git describe set to: v0.3.1-9-g47e150e INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.3.1-9-g47e150e... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex.bit into /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.3.1-9-g47e150e/rod_efex-v0.3.1-9-g47e150e.bit...