*** Running vivado
    with args -log top_rod_efex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_efex.tcl -notrace

WARNING: Default location for XILINX_HLS not found

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source top_rod_efex.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3020.844 ; gain = 2.020 ; free physical = 14688 ; free virtual = 49626
Command: link_design -top top_rod_efex -part xc7vx550tffg1927-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx550tffg1927-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.dcp' for cell 'top_vio'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila.dcp' for cell 'ILA_axi_chan_0/ila_crc_check'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.dcp' for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.dcp' for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'backplane/combined_ttc/ila_rx2_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'backplane/combined_ttc/vio_gt_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/bulk_ila.dcp' for cell 'event_builder/bulk_0/bulkl_proc_probe'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/event_fifo_ila/event_fifo_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/rx_time_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/error_ila.dcp' for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont.dcp' for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.dcp' for cell 'fm_interface_1/clk_blk'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'fm_interface_1/chan_0/L1ID_fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode.dcp' for cell 'fm_interface_1/chan_0/ila_fm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'fm_interface_1/chan_0/vio_fm_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'fm_interface_1/chan_0/ram0/RAM_0'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'fm_interface_1/chan_0/u7/FIFO34b'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i'
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3296.812 ; gain = 0.000 ; free physical = 13469 ; free virtual = 48407
INFO: [Netlist 29-17] Analyzing 11475 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 
INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a 
INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 
INFO: [Chipscope 16-324] Core: ILA_axi_chan_0/ila_crc_check UUID: a9e8e6ca-2b1f-5fbe-a871-91755a4a7c6e 
INFO: [Chipscope 16-324] Core: ILA_axi_chan_6/ila_crc_check UUID: 41f97370-bc3f-56dd-ab00-76683edcad5a 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 
INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 
INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b 
INFO: [Chipscope 16-324] Core: event_builder/bulk_0/bulkl_proc_probe UUID: 7d9dc169-40d5-56ff-9a38-42ad7dd0b67d 
INFO: [Chipscope 16-324] Core: event_builder/bulk_1/bulkl_proc_probe UUID: 48639c55-d7f5-5b3f-bf8a-c3e17dffdced 
INFO: [Chipscope 16-324] Core: event_builder/bulk_2/bulkl_proc_probe UUID: f79c214c-778a-503c-82e0-558ccd7036de 
INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_event_fifo UUID: 2d4141be-dbbe-5502-9616-cd358067f2ea 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time UUID: 00d8ad3a-1e81-507f-9fb8-068989d0eac6 
INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila UUID: 03337b11-edd4-554c-9722-ab13aea48bfc 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 
INFO: [Chipscope 16-324] Core: event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check UUID: 0b5e705b-49ad-5d15-9efb-ec02e926d290 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 
INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 
INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c 
INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/ila_fm UUID: 6d2436f5-9843-5197-8e19-cddbe1593602 
INFO: [Chipscope 16-324] Core: fm_interface_2/chan_0/vio_fm_reset UUID: 2e7b6e8a-28c2-522f-b319-a31f8d50741a 
INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/ila_fm UUID: f7690143-a9e0-554d-977a-d2f37b0258d0 
INFO: [Chipscope 16-324] Core: fm_interface_2/chan_1/vio_fm_reset UUID: f793cc7a-6b74-5a26-9770-d018214fd2d5 
INFO: [Chipscope 16-324] Core: fm_interface_2/u0/ila_resetfsm UUID: c10d06e5-8b28-51b9-aae4-8af94262c1bd 
INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 
INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 
INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/input_fifo/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:57]
get_clocks: Time (s): cpu = 00:00:32 ; elapsed = 00:00:23 . Memory (MB): peak = 4608.340 ; gain = 782.980 ; free physical = 10685 ; free virtual = 45624
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0'
CRITICAL WARNING: [Designutils 20-1281] Could not find module 'data_fifo_vio'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc will not be read for this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_2/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_2/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_2/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_0/ila_fm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/chan_1/ila_fm/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_2/u0/ila_resetfsm/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ch0'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/axi_ch0/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ch0'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/axi_ch0/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1281] Could not find module 'pp_ctrl_vio'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio.xdc will not be read for this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/event_fifo_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/event_fifo_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0'
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module.
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_0/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_6/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list.
INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc]
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_0/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_2/chan_1/L1ID_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_0/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_2/chan_1/u7/FIFO34b/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_2/clk_blk/inst'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports -scoped_to_current_instance ext_spi_clk]'. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0'
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:73]
INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:74]
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0'
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_2/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: fm_interface_2/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. 
     Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst 
  This will add unnecessary latency to the design. Please check the design for the following: 
 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 
 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
 [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Project 1-1714] 338 XPM XDC files have been applied to the design.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-1687] 2 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5310.984 ; gain = 0.000 ; free physical = 11558 ; free virtual = 46498
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 3713 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 3168 instances
  IOBUF => IOBUF (IBUF, OBUFT): 23 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 42 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
  RAM64M => RAM64M (RAMD64E(x4)): 380 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 96 instances

94 Infos, 128 Warnings, 16 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:03:03 ; elapsed = 00:02:45 . Memory (MB): peak = 5310.984 ; gain = 2273.914 ; free physical = 11558 ; free virtual = 46498
source /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it...
INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd...
INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found.
INFO: [Hog:Msg-0] All done
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-1540] The version limit for your license is '2022.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases.
Parsing TCL File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl]
Parsing TCL File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci
Sourcing Tcl File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx550t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5318.988 ; gain = 7.992 ; free physical = 11316 ; free virtual = 46256

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10802 ; free virtual = 45755
Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.24 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10800 ; free virtual = 45753
Phase 1 Generate And Synthesize Debug Cores | Checksum: 1a2e11f4e

Time (s): cpu = 00:02:32 ; elapsed = 00:02:33 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10800 ; free virtual = 45752

Phase 2 Retarget
INFO: [Opt 31-1287] Pulled Inverter Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 15 pins
INFO: [Opt 31-1287] Pulled Inverter ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 15 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[10]_i_3, which resulted in an inversion of 15 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/gt0_rxresetfsm_i/time_out_counter[0]_i_1 into driver instance backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/gt0_rxresetfsm_i/time_out_2ms_i_2, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter backplane/pwer_on_rst/count[31]_i_1 into driver instance backplane_i_1, which resulted in an inversion of 3 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_0/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_1/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_2/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_2/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_2/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__1, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__13, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__15, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__3, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__5, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__7, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__9, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__21, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__19, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__17, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__11, which resulted in an inversion of 4 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/readout_controller/readout_ctrl_ila2/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/readout_controller/readout_ctrl_ila2/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[15]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[6]_i_3, which resulted in an inversion of 6 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/ila_event_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/gen_reg.status_regs/l1id_capt/no_sim_regs.L1ID_Capture_Control_reg/stb[0]_i_1__3 into driver instance ipbus_blk/ipbus/ipbus/trans/sm/ipbw_Processor[ipb_write]_INST_0, which resulted in an inversion of 426 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[15]_i_1 into driver instance event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[4]_i_3, which resulted in an inversion of 6 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_ttc_fifo_in/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_ttc_fifo_in/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 13 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 15 pins
INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter fm_interface_1/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_1/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter fm_interface_1/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_1/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter fm_interface_2/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_2/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter fm_interface_2/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_2/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/AXI_EMC_NATIVE_INTERFACE_I/rnw_reg_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/AXI_EMC_NATIVE_INTERFACE_I/AXI_EMC_ADDR_GEN_INSTANCE_I/BUS2IP_ADDR_GEN_DATA_WDTH_32.bus2ip_addr_i[11]_i_3, which resulted in an inversion of 63 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/COUNTERS_I/TWRCNT_I/PERBIT_GEN[4].MULT_AND_i1_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/COUNTERS_I/TWRCNT_I/FSM_onehot_crnt_state[4]_i_3, which resulted in an inversion of 8 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_2, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_2, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.si_transactor_aw/gen_multi_thread.active_target[8]_i_1__0 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_multi_thread.active_target[8]_i_2, which resulted in an inversion of 6 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.si_transactor_aw/gen_multi_thread.active_target[9]_i_1__0 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_multi_thread.active_target[9]_i_2__0, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_2, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[6]_i_3 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[6]_i_4, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/primary_mode.IPAM_block/tick_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/primary_mode.IPAM_block/tick_counter.counter_int[23]_i_3, which resulted in an inversion of 24 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/rx_reset_block/ip_pkt.pkt_data[71]_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/rx_reset_block/build_packet.send_buf_int_i_4__1, which resulted in an inversion of 101 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/rx_transactor/ready_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/rx_transactor/history_block.event_pending_i_2, which resulted in an inversion of 132 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/tx_transactor/resend_buf[3]_i_2 into driver instance ipbus_blk/ipbus/ipbus/udp_if/tx_transactor/resend_buf[3]_i_3, which resulted in an inversion of 5 pins
INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0/ethernet_mac_rgmii_core/sync_stats_reset/async_rst0_i_1 into driver instance ipbus_blk/ipbus/example_resets/tri_mode_ethernet_mac_i_i_1, which resulted in an inversion of 1 pins
INFO: [Opt 31-1287] Pulled Inverter pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins
INFO: [Opt 31-1287] Pulled Inverter pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins
INFO: [Opt 31-138] Pushed 78 inverter(s) to 623 load pin(s).
In IDDR TRANSFORM
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: 1b4df3328

Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10635 ; free virtual = 45588
INFO: [Opt 31-389] Phase Retarget created 425 cells and removed 1861 cells
INFO: [Opt 31-1021] In phase Retarget, 2560 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
Phase 3 Constant propagation | Checksum: 11c01d250

Time (s): cpu = 00:02:55 ; elapsed = 00:02:56 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10611 ; free virtual = 45564
INFO: [Opt 31-389] Phase Constant propagation created 347 cells and removed 1662 cells
INFO: [Opt 31-1021] In phase Constant propagation, 1975 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD3804) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Phase 4 Sweep | Checksum: 1776214ac

Time (s): cpu = 00:03:34 ; elapsed = 00:03:35 . Memory (MB): peak = 5318.988 ; gain = 0.000 ; free physical = 10970 ; free virtual = 45923
INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 8653 cells
INFO: [Opt 31-1021] In phase Sweep, 19192 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
Phase 5 BUFG optimization | Checksum: 1776214ac

Time (s): cpu = 00:03:39 ; elapsed = 00:03:38 . Memory (MB): peak = 5343.000 ; gain = 24.012 ; free physical = 10970 ; free virtual = 45923
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 1776214ac

Time (s): cpu = 00:03:40 ; elapsed = 00:03:39 . Memory (MB): peak = 5343.000 ; gain = 24.012 ; free physical = 10970 ; free virtual = 45923
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/gen_reg.registers/first_last_encode/low_high.high_chan[3]_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/first_last_encode/high_low.low_chan[2]_i_3, which resulted in an inversion of 5 pins
Phase 7 Post Processing Netlist | Checksum: 1450b9e67

Time (s): cpu = 00:03:41 ; elapsed = 00:03:40 . Memory (MB): peak = 5343.000 ; gain = 24.012 ; free physical = 10964 ; free virtual = 45917
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 2094 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |             425  |            1861  |                                           2560  |
|  Constant propagation         |             347  |            1662  |                                           1975  |
|  Sweep                        |              11  |            8653  |                                          19192  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               1  |                                           2094  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.52 . Memory (MB): peak = 5343.000 ; gain = 0.000 ; free physical = 10863 ; free virtual = 45816
Ending Logic Optimization Task | Checksum: 120954f75

Time (s): cpu = 00:03:46 ; elapsed = 00:03:46 . Memory (MB): peak = 5343.000 ; gain = 24.012 ; free physical = 10863 ; free virtual = 45816
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci
Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69]
all_fanout: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 5343.000 ; gain = 0.000 ; free physical = 10604 ; free virtual = 45557
Finished Parsing XDC File [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0'

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5343.000 ; gain = 0.000 ; free physical = 10603 ; free virtual = 45556
Ending Netlist Obfuscation Task | Checksum: 120954f75

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5343.000 ; gain = 0.000 ; free physical = 10603 ; free virtual = 45556
INFO: [Common 17-83] Releasing license: Implementation
205 Infos, 128 Warnings, 16 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:17 ; elapsed = 00:04:17 . Memory (MB): peak = 5343.000 ; gain = 32.016 ; free physical = 10603 ; free virtual = 45556
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.21 . Memory (MB): peak = 5351.004 ; gain = 0.000 ; free physical = 10445 ; free virtual = 45528
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 5351.008 ; gain = 8.008 ; free physical = 10511 ; free virtual = 45530
INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx
Command: report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:01:11 ; elapsed = 00:01:12 . Memory (MB): peak = 5359.008 ; gain = 8.000 ; free physical = 9974 ; free virtual = 44993
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-1540] The version limit for your license is '2022.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5361.977 ; gain = 0.000 ; free physical = 9777 ; free virtual = 44909
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1052f4b90

Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 5361.977 ; gain = 2.957 ; free physical = 9777 ; free virtual = 44909
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5361.977 ; gain = 0.000 ; free physical = 9776 ; free virtual = 44909

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e60ecbc6

Time (s): cpu = 00:01:06 ; elapsed = 00:01:06 . Memory (MB): peak = 5388.414 ; gain = 29.395 ; free physical = 9749 ; free virtual = 44878

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1d86a07da

Time (s): cpu = 00:02:30 ; elapsed = 00:02:31 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9371 ; free virtual = 44500

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1d86a07da

Time (s): cpu = 00:02:31 ; elapsed = 00:02:32 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9349 ; free virtual = 44479
Phase 1 Placer Initialization | Checksum: 1d86a07da

Time (s): cpu = 00:02:32 ; elapsed = 00:02:33 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9323 ; free virtual = 44453

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1891dd3de

Time (s): cpu = 00:03:03 ; elapsed = 00:03:05 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9081 ; free virtual = 44211

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15f8852e1

Time (s): cpu = 00:03:32 ; elapsed = 00:03:34 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9109 ; free virtual = 44239

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 21a413368

Time (s): cpu = 00:03:33 ; elapsed = 00:03:35 . Memory (MB): peak = 5967.516 ; gain = 608.496 ; free physical = 9123 ; free virtual = 44253

Phase 2.4 Global Placement Core

Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 1 LUTNM shape to break, 9183 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 1, two critical 0, total 1, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 4007 nets or LUTs. Breaked 1 LUT, combined 4006 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6118.039 ; gain = 0.000 ; free physical = 8353 ; free virtual = 43483

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            1  |           4006  |                  4007  |           0  |           1  |  00:00:08  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:02  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            1  |           4006  |                  4007  |           0  |           9  |  00:00:12  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.1 Physical Synthesis In Placer | Checksum: aee0369d

Time (s): cpu = 00:08:48 ; elapsed = 00:08:59 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8356 ; free virtual = 43486
Phase 2.4 Global Placement Core | Checksum: 240979813

Time (s): cpu = 00:09:01 ; elapsed = 00:09:12 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8331 ; free virtual = 43460
Phase 2 Global Placement | Checksum: 240979813

Time (s): cpu = 00:09:01 ; elapsed = 00:09:12 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8436 ; free virtual = 43566

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 15fa14590

Time (s): cpu = 00:09:34 ; elapsed = 00:09:46 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8595 ; free virtual = 43725

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1625e2345

Time (s): cpu = 00:10:43 ; elapsed = 00:10:55 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8366 ; free virtual = 43496

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 15302f485

Time (s): cpu = 00:10:46 ; elapsed = 00:10:58 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8369 ; free virtual = 43499

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 13dea46b0

Time (s): cpu = 00:10:56 ; elapsed = 00:11:08 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 8368 ; free virtual = 43497

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: e18f4af9

Time (s): cpu = 00:12:12 ; elapsed = 00:12:24 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7927 ; free virtual = 43057

Phase 3.6 Small Shape Detail Placement

Phase 3.6.1 Place Remaining
Phase 3.6.1 Place Remaining | Checksum: 158b08151

Time (s): cpu = 00:14:13 ; elapsed = 00:14:27 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7325 ; free virtual = 42455
Phase 3.6 Small Shape Detail Placement | Checksum: 158b08151

Time (s): cpu = 00:14:16 ; elapsed = 00:14:29 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7393 ; free virtual = 42523

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1e018fb61

Time (s): cpu = 00:14:29 ; elapsed = 00:14:43 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7322 ; free virtual = 42452

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1c60b5976

Time (s): cpu = 00:14:45 ; elapsed = 00:14:59 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7314 ; free virtual = 42444
Phase 3 Detail Placement | Checksum: 1c60b5976

Time (s): cpu = 00:14:47 ; elapsed = 00:15:01 . Memory (MB): peak = 6118.039 ; gain = 759.020 ; free physical = 7329 ; free virtual = 42459

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 237030e3d

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.632 | TNS=-18.924 |
Phase 1 Physical Synthesis Initialization | Checksum: 185ffae9c

Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 6146.914 ; gain = 0.000 ; free physical = 7220 ; free virtual = 42350
INFO: [Place 46-33] Processed net ipbus_blk/ipbus/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1a028194f

Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 6146.914 ; gain = 0.000 ; free physical = 7228 ; free virtual = 42358
Phase 4.1.1.1 BUFG Insertion | Checksum: 237030e3d

Time (s): cpu = 00:17:17 ; elapsed = 00:17:32 . Memory (MB): peak = 6146.914 ; gain = 787.895 ; free physical = 7259 ; free virtual = 42389

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.058. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 15750f4e8

Time (s): cpu = 00:22:28 ; elapsed = 00:22:45 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7264 ; free virtual = 42394

Time (s): cpu = 00:22:28 ; elapsed = 00:22:45 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7271 ; free virtual = 42401
Phase 4.1 Post Commit Optimization | Checksum: 15750f4e8

Time (s): cpu = 00:22:30 ; elapsed = 00:22:46 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7270 ; free virtual = 42401

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 15750f4e8

Time (s): cpu = 00:22:33 ; elapsed = 00:22:49 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7470 ; free virtual = 42600

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                2x2|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                1x1|                2x2|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 15750f4e8

Time (s): cpu = 00:22:35 ; elapsed = 00:22:51 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7549 ; free virtual = 42679
Phase 4.3 Placer Reporting | Checksum: 15750f4e8

Time (s): cpu = 00:22:37 ; elapsed = 00:22:53 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7560 ; free virtual = 42690

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.914 ; gain = 0.000 ; free physical = 7561 ; free virtual = 42691

Time (s): cpu = 00:22:37 ; elapsed = 00:22:53 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7561 ; free virtual = 42691
Phase 4 Post Placement Optimization and Clean-Up | Checksum: e4b55622

Time (s): cpu = 00:22:38 ; elapsed = 00:22:55 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7561 ; free virtual = 42691
Ending Placer Task | Checksum: da539996

Time (s): cpu = 00:22:40 ; elapsed = 00:22:56 . Memory (MB): peak = 6162.914 ; gain = 803.895 ; free physical = 7560 ; free virtual = 42690
INFO: [Common 17-83] Releasing license: Implementation
246 Infos, 128 Warnings, 16 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:23:02 ; elapsed = 00:23:19 . Memory (MB): peak = 6162.914 ; gain = 803.906 ; free physical = 7814 ; free virtual = 42944
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 6162.914 ; gain = 0.000 ; free physical = 7372 ; free virtual = 42873
report_design_analysis: Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 6162.914 ; gain = 0.000 ; free physical = 7270 ; free virtual = 42771
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:26 ; elapsed = 00:01:29 . Memory (MB): peak = 6162.918 ; gain = 0.004 ; free physical = 7553 ; free virtual = 42771
INFO: [runtcl-4] Executing : report_io -file top_rod_efex_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.86 . Memory (MB): peak = 6162.918 ; gain = 0.000 ; free physical = 7497 ; free virtual = 42717
INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed.rpt -pb top_rod_efex_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_efex_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6162.918 ; gain = 0.000 ; free physical = 7553 ; free virtual = 42776
INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed_1.rpt -pb top_rod_efex_utilization_placed_1.pb
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-1540] The version limit for your license is '2022.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases.
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 88.86s |  WALL: 88.90s
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7502 ; free virtual = 42724

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.058 | TNS=-0.058 |
Phase 1 Physical Synthesis Initialization | Checksum: bf2f8f78

Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7322 ; free virtual = 42545

Phase 2 SLR Crossing Optimization
Phase 2 SLR Crossing Optimization | Checksum: bf2f8f78

Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7312 ; free virtual = 42535
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.058 | TNS=-0.058 |

Phase 3 Fanout Optimization
INFO: [Physopt 32-76] Pass 1. Identified 5 candidate nets for fanout optimization.
INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/sel_dbg_header. Replicated 1 times.
INFO: [Physopt 32-572] Net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_67_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-572] Net event_builder/tob_processor_0/input_mux/chan_count_reg[2]_2[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/ch8/input_pipe/pulse_stretcher/pulse_out_i_reg_0[0]. Replicated 1 times.
INFO: [Physopt 32-572] Net event_builder/tob_processor_0/input_mux/first_event_reg_2[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-232] Optimized 2 nets. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.058 | TNS=-0.058 |
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7312 ; free virtual = 42535
Phase 3 Fanout Optimization | Checksum: b12f7433

Time (s): cpu = 00:01:01 ; elapsed = 00:01:01 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7312 ; free virtual = 42535

Phase 4 Single Cell Placement Optimization
INFO: [Physopt 32-660] Identified 250 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[2].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo_i_1__3
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/tob_m_tready_2.  Did not re-place instance event_builder/tob_processor_0/input_mux/input_fifo_i_2__4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[1].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[1]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I.  Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count_reg[4]_4.  Did not re-place instance event_builder/tob_processor_0/input_mux/input_fifo_i_2__0
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out.  Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo_i_1__21
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0.  Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[0].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[0]
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo[11]_i_2_n_0.  Re-placed instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo[11]_i_2
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out.  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo_i_1__19
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/chan_count_reg[4]_3.  Re-placed instance event_builder/tob_processor_0/input_mux/input_fifo_i_2
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[9].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[9]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[12].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[12]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ENB_I.  Did not re-place instance event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out.  Re-placed instance event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo_i_1__15
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0.  Re-placed instance event_builder/fifo_layer/ch11/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/tob_m_tready_11.  Re-placed instance event_builder/tob_processor_0/input_mux/input_fifo_i_2__10
INFO: [Physopt 32-663] Processed net fm_interface_1/chan_1/u5/dout[8].  Re-placed instance fm_interface_1/chan_1/u5/dout_reg[8]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[11].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[11]
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0].  Re-placed instance event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch9/input_pipe/s_axis_tvalid.  Re-placed instance event_builder/fifo_layer/ch9/input_pipe/clk_cross_fifo_i_2__5
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/tob_trans.  Did not re-place instance event_builder/fifo_layer/ch9/tob_trans_reg
INFO: [Physopt 32-663] Processed net backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[44].  Re-placed instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[43]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[7]_0[0].  Did not re-place instance event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[7]_0[2].  Did not re-place instance event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/input_pipe/DIn[12].  Did not re-place instance event_builder/fifo_layer/ch8/input_pipe/axis_tdata_1_reg[44]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[7]_0[3].  Did not re-place instance event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[7]_0[4].  Did not re-place instance event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[4]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[4].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[4]
INFO: [Physopt 32-663] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[25].  Re-placed instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[30]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[18]_i_7_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[18]_i_7
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in__0[11].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_1
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_16_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_16
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__105[10].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_5
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_2_in[11].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_2
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__107[12].  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg_s_reg[11]
INFO: [Physopt 32-663] Processed net backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[57].  Re-placed instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[62]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/input_pipe/DIn[25].  Did not re-place instance event_builder/fifo_layer/ch8/input_pipe/axis_tdata_1_reg[57]
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch1/input_pipe/pkt_count[15]_i_1__0_n_0.  Re-placed instance event_builder/fifo_layer/ch1/input_pipe/pkt_count[15]_i_1__0
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_enable.  Did not re-place instance event_builder/tob_processor_0/input_mux/event_builder_0_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_88_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_88
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_100_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_100
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_i_1_n_0.  Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_i_1
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/pointer[1].  Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable_i_8
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[2].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[2]
INFO: [Physopt 32-662] Processed net backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/rx_src_rdy.  Did not re-place instance backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/RX_SRC_RDY_N_Buffer_reg
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable__2_n_0.  Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable__2
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/input_mux/pointer[2].  Re-placed instance event_builder/tob_processor_0/input_mux/m_chan_enable_i_9
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[2].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_21_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_21
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_55_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_55
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/m_chan_enable_n_0.  Did not re-place instance event_builder/tob_processor_0/input_mux/m_chan_enable
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/input_pipe/pkt_count[14].  Did not re-place instance event_builder/fifo_layer/ch1/input_pipe/pkt_count_reg[14]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch1/input_pipe/pkt_count[5].  Did not re-place instance event_builder/fifo_layer/ch1/input_pipe/pkt_count_reg[5]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_6_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_6
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[17]_i_14_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[17]_i_14
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in__0[3].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[3]_i_1
INFO: [Physopt 32-662] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[58].  Did not re-place instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[61]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__106[3].  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[3]_i_3
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__107[4].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg_s_reg[3]
INFO: [Physopt 32-663] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[21].  Re-placed instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[18]
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[20].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[19]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[16]_i_9_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[16]_i_9
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in__0[13].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[13]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[13]_i_10_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[13]_i_10
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__106[13].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[13]_i_5
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_2_in[13].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[13]_i_2
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__43[14].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_reg[13]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[18]_i_18_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[18]_i_18
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_6_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_6
INFO: [Physopt 32-663] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[24].  Re-placed instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[31]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_67_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_67
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_63_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_63
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg[17]_i_10_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg[17]_i_10
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg[4]_i_4_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg[4]_i_4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/p_2_in[4].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg[4]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_8_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_8
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/proposed_crc20[3].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/proposed_crc20_reg[3]
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/p_0_in0_in__107[5].  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/Reg_s_reg[4]
INFO: [Physopt 32-663] Processed net backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[18].  Re-placed instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[21]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/input_pipe/DIn[50].  Did not re-place instance event_builder/fifo_layer/ch8/input_pipe/axis_tdata_1_reg[18]
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__43[4].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg_reg[3]
INFO: [Physopt 32-663] Processed net backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[16].  Re-placed instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[23]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/input_pipe/DIn[48].  Did not re-place instance event_builder/fifo_layer/ch8/input_pipe/axis_tdata_1_reg[16]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_145_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_145
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_105_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_105
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_57_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_57
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/CRC[0].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc/crc_block/CRC_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_9_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_9
INFO: [Physopt 32-663] Processed net Bulk_1_64_32/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/m_axis_tdata[31].  Re-placed instance Bulk_1_64_32/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/m_axis_tdata[31]_INST_0
INFO: [Physopt 32-662] Processed net Bulk_1_64_32/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/p_0_in1_in[31].  Did not re-place instance Bulk_1_64_32/data_width_conv/inst/gen_downsizer_conversion.axisc_downsizer_0/r0_data_reg[31]
INFO: [Physopt 32-663] Processed net fm_interface_2/chan_0/data_mux/fifo34_din[31].  Re-placed instance fm_interface_2/chan_0/data_mux/u7_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/proposed_crc20[0].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/proposed_crc20_reg[0]
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[13].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[10]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[2]_i_3__0_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[2]_i_3__0
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_11_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_11
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_22_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_22
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/p_0_in__0[8].  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_1__0
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_2__0_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_2__0
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg_reg_n_0_[8].  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg_reg[8]
INFO: [Physopt 32-663] Processed net event_builder/bulk_1/controller/state_reg/m_tlast.  Re-placed instance event_builder/bulk_1/controller/state_reg/m_tlast_INST_0
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[68]_0[0].  Did not re-place instance event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[0]
INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/s_tlast.  Re-placed instance event_builder/bulk_1/input_mux/m_header_mark__0
INFO: [Physopt 32-662] Processed net event_builder/bulk_1/input_mux/m_header_mark__0_i_1_n_0.  Did not re-place instance event_builder/bulk_1/input_mux/m_header_mark__0_i_1
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_4_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_4
INFO: [Physopt 32-662] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[62].  Did not re-place instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[57]
INFO: [Physopt 32-663] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[18].  Re-placed instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[21]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_11_n_0.  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_11
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in__0[5].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[5]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[5]_i_2__0_n_0.  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[5]_i_2__0
INFO: [Physopt 32-663] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__43[6].  Re-placed instance ILA_axi_chan_6/crc_checker/payload_crc/Reg_reg[5]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/any_err.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[11]_INST_0_i_1
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata[22].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_42
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_12_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_12
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_5_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_5
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_2_in[14].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[14]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[2].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[2]_INST_0
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_97_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_97
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_0_in0_in__43[15].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg_reg[14]
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_3_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_3
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[58].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[61]
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in__0[7].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[7]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_11_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_11
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_20_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_20
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_2_in[7].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[7]_i_2
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__107[8].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_s_reg[7]
INFO: [Physopt 32-662] Processed net event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8_n_0.  Did not re-place instance event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/shifted_data_in_reg[7][69]_srl8
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[3].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[3]
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[25].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[30]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[18]_i_7_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[18]_i_7
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in__0[11].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_16_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_16
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__105[10].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_5
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_2_in[11].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_2
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__43[12].  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_reg[11]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_8_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_8
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_5_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_5
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in__0[15].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_1
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_36_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_trailer_crc_i_36
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_10_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_10
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_2_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[15]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_7_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map_i_7
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/proposed_crc20[7].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/proposed_crc20_reg[7]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__107[16].  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_s_reg[15]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__43[16].  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_reg[15]
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_4_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_4
INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/u5/crc_din_reg_n_0_[26].  Did not re-place instance fm_interface_2/chan_1/u5/crc_din_reg[26]
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[30].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[25]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata[28].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_36
INFO: [Physopt 32-663] Processed net fm_interface_2/chan_1/u5/crc20_0/Reg[13]_i_4_n_0.  Re-placed instance fm_interface_2/chan_1/u5/crc20_0/Reg[13]_i_4
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[14]_i_3_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[14]_i_3
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_9_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[11]_i_9
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[19]_i_7_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[19]_i_7
INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/u5/crc20_0/p_0_in__0[13].  Did not re-place instance fm_interface_2/chan_1/u5/crc20_0/Reg[13]_i_1
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[16]_i_4_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[16]_i_4
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_2_in[16].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[16]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[8].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[8]_INST_0
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_91_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_91
INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/u5/crc20_0/Reg[13]_i_2_n_0.  Did not re-place instance fm_interface_2/chan_1/u5/crc20_0/Reg[13]_i_2
INFO: [Physopt 32-662] Processed net fm_interface_2/chan_1/u5/crc20_0/p_0_in0_in__43[14].  Did not re-place instance fm_interface_2/chan_1/u5/crc20_0/Reg_s_reg[13]
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_0_in0_in__107[17].  Re-placed instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg_s_reg[16]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_0_in0_in__107[15].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg_s_reg[14]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_21_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_21
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[9].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[14]
INFO: [Physopt 32-662] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[44].  Did not re-place instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[43]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[5]_i_13_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[5]_i_13
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/p_0_in__0[5].  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[5]_i_1__0
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[7]_i_15_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[7]_i_15
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[7]_i_3__0_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[7]_i_3__0
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/p_2_in[5].  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[5]_i_2
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[10].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[10]
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/p_0_in0_in__54[6].  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg_reg[5]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[68]_0[0].  Did not re-place instance event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[3].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[3]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/CRC_reg[8]_0[3].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[6]_i_13
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/D[4].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[16]_i_1
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Q_reg[0].  Re-placed instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[16]_i_5
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/sel_dbg_trailer.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/debug_fifo_i_68
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/CRC_reg[3]_1.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[16]_i_12
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/dbg_crc20_gen/p_0_in0_in__40[14].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/dbg_crc9_gen/Reg[16]_i_2
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[5].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[5]
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/p_0_in0_in__107[17].  Re-placed instance event_builder/tob_processor_0/event_builder_0/dbg_crc20_gen/Reg_s_reg[16]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[3].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_3
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_17_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_17
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_50_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_50
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in__0[16].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_11_n_0.  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_11
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_3_n_0.  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_3
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in0_in__107[17].  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg_s_reg[16]
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[24].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[31]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_103_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_103
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/header_crc/DIn[56].  Re-placed instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_25
INFO: [Physopt 32-663] Processed net backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[34].  Re-placed instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[37]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[8].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[8]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch8/input_pipe/DIn[2].  Did not re-place instance event_builder/fifo_layer/ch8/input_pipe/axis_tdata_1_reg[34]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/wdog_timer/wdog_overflow.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/wdog_timer/wdog_overflow_INST_0
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/gen_reg.status_regs/wdog_fifo_reset.  Did not re-place instance event_builder/tob_processor_0/gen_reg.status_regs/wdog_fifo_reset__0
INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/s_tvalid.  Re-placed instance event_builder/bulk_1/input_mux/m_header_mark__0__3
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/RESET_stretch_i_4.  Re-placed instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/counter[3]_i_1__6
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.axis_pkt_read_reg__0.  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.axis_pkt_read_reg
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/pulse_in_5.  Did not re-place instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/counter[7]_i_4__1
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/wdog_timer/output_timer[0].  Re-placed instance event_builder/tob_processor_0/event_builder_0/wdog_timer/output_timer_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/wdog_timer/wdog_overflow_INST_0_i_1_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/wdog_timer/wdog_overflow_INST_0_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in__0[1].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[1]_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__106[1].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[1]_i_3
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_2_in[1].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[1]_i_2
INFO: [Physopt 32-663] Processed net event_builder/bulk_1/controller/state_reg/D[0].  Re-placed instance event_builder/bulk_1/controller/state_reg/Q[0]_i_1
INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/Q[0]_i_5_n_0.  Did not re-place instance event_builder/bulk_1/controller/state_reg/Q[0]_i_5
INFO: [Physopt 32-663] Processed net event_builder/bulk_1/input_mux/m_header_mark__0_i_1__3_n_0.  Re-placed instance event_builder/bulk_1/input_mux/m_header_mark__0_i_1__3
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/calo_poll_reg_reg.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/calo_poll_reg_i_1__1
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axis_tvalid.  Re-placed instance event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axis_tvalid_INST_0
INFO: [Physopt 32-662] Processed net event_builder/bulk_1/controller/state_reg/Q[0].  Did not re-place instance event_builder/bulk_1/controller/state_reg/Q_reg[0]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__43[2].  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg_reg[1]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/calo_poll_reg.  Did not re-place instance event_builder/fifo_layer/ch2/calo_poll_reg_reg
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[68]_0[0].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/chan_count_reg[2]_2[0].  Did not re-place instance event_builder/tob_processor_0/input_mux/first_event_i_1__3
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/poll_chan.  Re-placed instance event_builder/tob_processor_0/event_builder_0/poll_chan_INST_0
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/packets_read_counter[25].  Did not re-place instance event_builder/fifo_layer/ch3/packets_read_counter_reg[25]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/packets_read_counter[26].  Did not re-place instance event_builder/fifo_layer/ch3/packets_read_counter_reg[26]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/packets_read_counter[27].  Did not re-place instance event_builder/fifo_layer/ch3/packets_read_counter_reg[27]
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch3/packets_read_counter[28].  Did not re-place instance event_builder/fifo_layer/ch3/packets_read_counter_reg[28]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg/Q[5].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg/Q_reg[5]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_87_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_87
INFO: [Physopt 32-662] Processed net ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_2_n_0.  Did not re-place instance ILA_axi_chan_6/crc_checker/payload_crc/Reg[16]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/D[5].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_1
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_34_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/state_reg_i_34
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/state_reg_i_8_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/state_reg_i_8
INFO: [Physopt 32-662] Processed net backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/probe_data[139].  Did not re-place instance backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M_i_1
INFO: [Physopt 32-662] Processed net backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1[0].  Did not re-place instance backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[8].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[0]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata[21].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_43
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[15]_i_6_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[15]_i_6
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[9]_i_5_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[9]_i_5
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_2_in[9].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg[9]_i_2
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[1].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/evnt_trailer_err_map/error_map[1]_INST_0
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_98_n_0.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/fifo_s_tdata_inferred_i_98
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/p_0_in0_in__107[10].  Re-placed instance event_builder/tob_processor_0/event_builder_0/event_trailer_crc/crc_block/Reg_s_reg[9]
INFO: [Physopt 32-662] Processed net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/RX_EOF_N.  Did not re-place instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/RX_EOF_N_Buffer_reg
INFO: [Physopt 32-663] Processed net backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[26].  Re-placed instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/OUTPUT_DATA_Buffer_reg[29]
INFO: [Physopt 32-663] Processed net ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_8_n_0.  Re-placed instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[19]_i_8
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/payload_crc/p_0_in0_in__106[7].  Did not re-place instance ILA_axi_chan_0/crc_checker/payload_crc/Reg[7]_i_4
INFO: [Physopt 32-663] Processed net event_builder/tob_processor_0/event_builder_0/chan_len_cnt[11]_i_1_n_0.  Re-placed instance event_builder/tob_processor_0/event_builder_0/chan_len_cnt[11]_i_1
INFO: [Physopt 32-663] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reset.  Re-placed instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/event_builder_0_i_1
INFO: [Physopt 32-662] Processed net ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_10__0_n_0.  Did not re-place instance ILA_axi_chan_0/crc_checker/header_crc/Reg[8]_i_10__0
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/axis_data_count[7].  Did not re-place instance event_builder/fifo_layer/ch7/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[7]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/chan_len_cnt[4].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/chan_len_cnt_reg[4]
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/chan_len_cnt[5].  Did not re-place instance event_builder/tob_processor_0/event_builder_0/chan_len_cnt_reg[5]
INFO: [Physopt 32-661] Optimized 80 nets.  Re-placed 80 instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 80 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 80 existing cells
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.058 | TNS=-0.058 |
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7309 ; free virtual = 42532
Phase 4 Single Cell Placement Optimization | Checksum: 1523f7966

Time (s): cpu = 00:01:25 ; elapsed = 00:01:27 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7309 ; free virtual = 42532

Phase 5 Multi Cell Placement Optimization
INFO: [Physopt 32-660] Identified 100 candidate nets for placement-based optimization.
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/Q[2].  Did not re-place instance event_builder/tob_processor_0/input_mux/chan_count_reg[2]/Q
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo_i_1__3/O
INFO: [Physopt 32-662] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0.  Did not re-place instance event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/input_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4/O
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/input_mux/tob_m_tready_2.  Did not re-place instance event_builder/tob_processor_0/input_mux/input_fifo_i_2__4/O
INFO: [Physopt 32-662] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n.  Did not re-place instance event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg/Q
INFO: [Physopt 32-661] Optimized 0 net.  Re-placed 0 instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7309 ; free virtual = 42532
Phase 5 Multi Cell Placement Optimization | Checksum: 16a030d52

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7309 ; free virtual = 42532

Phase 6 Rewire
INFO: [Physopt 32-246] Starting Signal Push optimization...
INFO: [Physopt 32-77] Pass 1. Identified 2 candidate nets for rewire optimization.
INFO: [Physopt 32-242] Processed net event_builder/tob_processor_0/input_mux/tob_m_tready_2. Rewired (signal push) event_builder/tob_processor_0/input_mux/Q[2] to 1 loads. Replicated 0 times.
INFO: [Physopt 32-134] Processed net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out. Rewiring did not optimize the net.
INFO: [Physopt 32-232] Optimized 1 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.029 | TNS=-0.029 |
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522
Phase 6 Rewire | Checksum: be17d8bf

Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522

Phase 7 Critical Cell Optimization
INFO: [Physopt 32-46] Identified 30 candidate nets for critical-cell optimization.
INFO: [Physopt 32-81] Processed net event_builder/tob_processor_0/event_builder_0/event_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/full_n. Replicated 1 times.
INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch2/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/Q[1] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/Q[2] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/chan_count_reg[4]_4 was not replicated.
INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch6/norm_fifo.clk_cross_tob_fifo/m_axis_tready1_out was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/Q[0] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/Q[4] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/Q[3] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/chan_enable was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/event_builder_0/state_reg_i_88_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/event_builder_0/state_reg_i_100_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/m_chan_enable_i_1_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/pointer[1] was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/m_chan_enable__2_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/input_mux/pointer[0] was not replicated.
INFO: [Physopt 32-571] Net backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_pdu_datapath_i/output_mux_i/M_AXI_RX_TDATA[30] was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_4_n_0 was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/payload_crc/Reg[11]_i_9_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/tob_processor_0/event_builder_0/state_reg_i_145_n_0 was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/payload_crc/Reg[7]_i_6_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch7/input_pipe/DIn[38] was not replicated.
INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch7/input_pipe/crc_gen/Reg[6]_i_9__0_n_0 was not replicated.
INFO: [Physopt 32-571] Net event_builder/fifo_layer/ch7/input_pipe/crc_gen/Reg[7]_i_6__9_n_0 was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/payload_crc/p_0_in__0[17] was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/header_crc/s_tvalid_del_reg[0] was not replicated.
INFO: [Physopt 32-571] Net ILA_axi_chan_6/crc_checker/s_tlast_del was not replicated.
INFO: [Physopt 32-232] Optimized 1 net. Created 1 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.021 | TNS=0.000 |
Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522
Phase 7 Critical Cell Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522

Phase 8 Fanout Optimization
INFO: [Physopt 32-670] No setup violation found.  Fanout Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522
Phase 8 Fanout Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7299 ; free virtual = 42522

Phase 9 Single Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Single Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 9 Single Cell Placement Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 10 Multi Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Multi Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 10 Multi Cell Placement Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 11 Rewire
INFO: [Physopt 32-670] No setup violation found.  Rewire was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 11 Rewire | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 12 Critical Cell Optimization
INFO: [Physopt 32-670] No setup violation found.  Critical Cell Optimization was not performed.
Phase 12 Critical Cell Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 13 SLR Crossing Optimization
Phase 13 SLR Crossing Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 14 Fanout Optimization
INFO: [Physopt 32-670] No setup violation found.  Fanout Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 14 Fanout Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 15 Single Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Single Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 15 Single Cell Placement Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 16 Multi Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Multi Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 16 Multi Cell Placement Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 17 Rewire
INFO: [Physopt 32-670] No setup violation found.  Rewire was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522
Phase 17 Rewire | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 18 Critical Cell Optimization
INFO: [Physopt 32-670] No setup violation found.  Critical Cell Optimization was not performed.
Phase 18 Critical Cell Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 19 DSP Register Optimization
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
Phase 19 DSP Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 20 BRAM Register Optimization
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
Phase 20 BRAM Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 21 URAM Register Optimization
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
Phase 21 URAM Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 22 Shift Register Optimization
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
Phase 22 Shift Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 23 DSP Register Optimization
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
Phase 23 DSP Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 24 BRAM Register Optimization
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
Phase 24 BRAM Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 25 URAM Register Optimization
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
Phase 25 URAM Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 26 Shift Register Optimization
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
Phase 26 Shift Register Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 27 Critical Pin Optimization
INFO: [Physopt 32-670] No setup violation found.  Critical Pin Optimization was not performed.
Phase 27 Critical Pin Optimization | Checksum: cb1c7e62

Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7298 ; free virtual = 42522

Phase 28 Very High Fanout Optimization
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 801 to 162. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 162.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 802 to 163. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 163.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 802 to 163. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 163.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 802 to 163. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 163.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 802 to 163. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 163.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 802 to 163. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 163.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 865 to 178. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 178.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[1]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 866 to 179. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 179.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 866 to 179. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 179.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[3]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 866 to 179. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 179.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[4]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 866 to 179. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 179.
INFO: [Physopt 32-1132] Very high fanout net 'event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[5]' is not considered as a candidate in VHFN optimzation. Its physical fanout number is changed from 866 to 179. To force replication, set the FORCE_MAX_FANOUT property on the net to a number less than 179.
INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization.
INFO: [Physopt 32-81] Processed net event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/reg_reg[0][5]_0. Replicated 2 times.
INFO: [Physopt 32-232] Optimized 1 net. Created 2 new instances.
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.021 | TNS=0.000 |
Netlist sorting complete. Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520
Phase 28 Very High Fanout Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:39 ; elapsed = 00:01:40 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520

Phase 29 Single Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Single Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520
Phase 29 Single Cell Placement Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:39 ; elapsed = 00:01:40 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520

Phase 30 Multi Cell Placement Optimization
INFO: [Physopt 32-670] No setup violation found.  Multi Cell Placement Optimization was not performed.
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520
Phase 30 Multi Cell Placement Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520

Phase 31 SLR Crossing Optimization
Phase 31 SLR Crossing Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520

Phase 32 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.021 | TNS=0.000 |
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.021 | TNS=0.000 |
Phase 32 Critical Path Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:42 ; elapsed = 00:01:43 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520

Phase 33 BRAM Enable Optimization
Phase 33 BRAM Enable Optimization | Checksum: 1637d058e

Time (s): cpu = 00:01:42 ; elapsed = 00:01:43 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42520
INFO: [Physopt 32-960] Skip hold-fix as initial WHS does not violate hold threshold 250 ps
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7304 ; free virtual = 42527
INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.021 | TNS=0.000 |

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization            |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Fanout                  |          0.000  |          0.000  |            0  |              0  |                     2  |           3  |           1  |  00:00:09  |
|  Single Cell Placement   |          0.000  |          0.000  |            0  |              0  |                    80  |           0  |           1  |  00:00:26  |
|  Multi Cell Placement    |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:02  |
|  Rewire                  |          0.029  |          0.029  |            0  |              0  |                     1  |           2  |           1  |  00:00:02  |
|  Critical Cell           |          0.050  |          0.029  |            1  |              0  |                     1  |          18  |           1  |  00:00:01  |
|  SLR Crossing            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           3  |  00:00:00  |
|  DSP Register            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register          |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Critical Pin            |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Very High Fanout        |          0.000  |          0.000  |            2  |              0  |                     1  |           0  |           1  |  00:00:06  |
|  BRAM Enable             |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Path           |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:03  |
|  Total                   |          0.079  |          0.058  |            3  |              0  |                    85  |          23  |          11  |  00:00:49  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------


Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7304 ; free virtual = 42527
Ending Physical Synthesis Task | Checksum: 1ed06c0cf

Time (s): cpu = 00:01:45 ; elapsed = 00:01:46 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7304 ; free virtual = 42527
INFO: [Common 17-83] Releasing license: Implementation
612 Infos, 128 Warnings, 16 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:03:13 ; elapsed = 00:03:15 . Memory (MB): peak = 6162.926 ; gain = 0.008 ; free physical = 7451 ; free virtual = 42674
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7300 ; free virtual = 42889
report_design_analysis: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7357 ; free virtual = 42947
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:18 ; elapsed = 00:01:21 . Memory (MB): peak = 6162.926 ; gain = 0.000 ; free physical = 7633 ; free virtual = 42944
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t'
INFO: [Common 17-1540] The version limit for your license is '2022.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.

Phase 1 Build RT Design
Checksum: PlaceDB: 60613e20 ConstDB: 0 ShapeSum: e6972bfc RouteDB: 0
Post Restoration Checksum: NetGraph: 46b00e1 NumContArr: a7b2b4a8 Constraints: 0 Timing: 0
Phase 1 Build RT Design | Checksum: ac1db589

Time (s): cpu = 00:03:12 ; elapsed = 00:03:12 . Memory (MB): peak = 6352.453 ; gain = 189.527 ; free physical = 6990 ; free virtual = 42301

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: ac1db589

Time (s): cpu = 00:03:14 ; elapsed = 00:03:15 . Memory (MB): peak = 6352.453 ; gain = 189.527 ; free physical = 6966 ; free virtual = 42277

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: ac1db589

Time (s): cpu = 00:03:16 ; elapsed = 00:03:16 . Memory (MB): peak = 6352.453 ; gain = 189.527 ; free physical = 6959 ; free virtual = 42270
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2a17636ef

Time (s): cpu = 00:07:11 ; elapsed = 00:07:16 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6626 ; free virtual = 41937
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.097  | TNS=0.000  | WHS=-0.969 | THS=-20258.594|


Phase 2.4 Update Timing for Bus Skew

Phase 2.4.1 Update Timing
Phase 2.4.1 Update Timing | Checksum: 284e4ad0d

Time (s): cpu = 00:08:23 ; elapsed = 00:08:28 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6590 ; free virtual = 41901
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.097  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.4 Update Timing for Bus Skew | Checksum: 1c7170e65

Time (s): cpu = 00:08:25 ; elapsed = 00:08:31 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6584 ; free virtual = 41896

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.139056 %
  Global Horizontal Routing Utilization  = 0.229661 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 206084
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 206084
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 10

Phase 2 Router Initialization | Checksum: 1a19663d1

Time (s): cpu = 00:08:28 ; elapsed = 00:08:34 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6581 ; free virtual = 41892

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1a19663d1

Time (s): cpu = 00:08:29 ; elapsed = 00:08:34 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6581 ; free virtual = 41892
Phase 3 Initial Routing | Checksum: 25be1d714

Time (s): cpu = 00:10:00 ; elapsed = 00:10:06 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6603 ; free virtual = 41914

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 17943
 Number of Nodes with overlaps = 3664
 Number of Nodes with overlaps = 415
 Number of Nodes with overlaps = 47
 Number of Nodes with overlaps = 27
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.173 | TNS=-1.026 | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 7d6d48c1

Time (s): cpu = 00:20:08 ; elapsed = 00:20:19 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6603 ; free virtual = 42220

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1244
 Number of Nodes with overlaps = 227
 Number of Nodes with overlaps = 51
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.067 | TNS=-0.155 | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: e127297f

Time (s): cpu = 00:21:29 ; elapsed = 00:21:42 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6560 ; free virtual = 42178

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 1193
 Number of Nodes with overlaps = 243
 Number of Nodes with overlaps = 54
 Number of Nodes with overlaps = 29
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.246 | TNS=-0.951 | WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: 1399b13c4

Time (s): cpu = 00:22:30 ; elapsed = 00:22:45 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6465 ; free virtual = 42083
Phase 4 Rip-up And Reroute | Checksum: 1399b13c4

Time (s): cpu = 00:22:31 ; elapsed = 00:22:45 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6464 ; free virtual = 42082

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1c421bec7

Time (s): cpu = 00:22:57 ; elapsed = 00:23:12 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 5787 ; free virtual = 41405
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=-0.028 | WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1f9e50747

Time (s): cpu = 00:23:01 ; elapsed = 00:23:16 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 5796 ; free virtual = 41413

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1f9e50747

Time (s): cpu = 00:23:02 ; elapsed = 00:23:17 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 5791 ; free virtual = 41409
Phase 5 Delay and Skew Optimization | Checksum: 1f9e50747

Time (s): cpu = 00:23:02 ; elapsed = 00:23:17 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 5790 ; free virtual = 41407

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1cb7eb575

Time (s): cpu = 00:23:33 ; elapsed = 00:23:48 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 5797 ; free virtual = 41414
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=-0.028 | WHS=-0.601 | THS=-1042.532|

Phase 6.1 Hold Fix Iter | Checksum: 22d8cf8b2

Time (s): cpu = 00:23:59 ; elapsed = 00:24:14 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6483 ; free virtual = 42101
Phase 6 Post Hold Fix | Checksum: 14ea0c05f

Time (s): cpu = 00:24:01 ; elapsed = 00:24:16 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6482 ; free virtual = 42100

Phase 7 Timing Verification

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 1b571ce29

Time (s): cpu = 00:24:45 ; elapsed = 00:25:00 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6383 ; free virtual = 42001
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=-0.028 | WHS=N/A    | THS=N/A    |

Phase 7 Timing Verification | Checksum: 1b571ce29

Time (s): cpu = 00:24:46 ; elapsed = 00:25:01 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6375 ; free virtual = 41993

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 12.4314 %
  Global Horizontal Routing Utilization  = 11.0003 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 94.5946%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X78Y264 -> INT_L_X78Y264
   INT_R_X15Y207 -> INT_R_X15Y207
   INT_R_X73Y177 -> INT_R_X73Y177
   INT_R_X37Y155 -> INT_R_X37Y155
   INT_L_X16Y148 -> INT_L_X16Y148
South Dir 1x1 Area, Max Cong = 92.7928%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X54Y197 -> INT_L_X54Y197
   INT_L_X14Y190 -> INT_L_X14Y190
   INT_L_X46Y177 -> INT_L_X46Y177
   INT_L_X40Y153 -> INT_L_X40Y153
   INT_R_X57Y119 -> INT_R_X57Y119
East Dir 1x1 Area, Max Cong = 89.7059%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X14Y200 -> INT_L_X14Y200
   INT_L_X12Y195 -> INT_L_X12Y195
   INT_R_X25Y138 -> INT_R_X25Y138
   INT_R_X29Y138 -> INT_R_X29Y138
   INT_R_X67Y129 -> INT_R_X67Y129
West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_R_X59Y113 -> INT_R_X59Y113
   INT_R_X57Y105 -> INT_R_X57Y105
   INT_L_X56Y104 -> INT_L_X56Y104
   INT_R_X57Y103 -> INT_R_X57Y103
   INT_L_X62Y84 -> INT_L_X62Y84

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.666667 Sparse Ratio: 1
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5

Phase 8 Route finalize | Checksum: 1b571ce29

Time (s): cpu = 00:24:48 ; elapsed = 00:25:03 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6348 ; free virtual = 41966

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 1b571ce29

Time (s): cpu = 00:24:49 ; elapsed = 00:25:04 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6330 ; free virtual = 41948

Phase 10 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y2/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y3/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y2/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y0/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y23/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y22/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y21/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y20/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y3/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y27/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y26/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y8/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y36/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y37/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin fm_interface_2/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y4/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y5/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y6/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y1/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y3/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y24/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y25/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y6/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y28/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y29/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y30/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y31/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y7/GTSOUTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1
INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK1
Phase 10 Depositing Routes | Checksum: 1e297ab5e

Time (s): cpu = 00:25:13 ; elapsed = 00:25:28 . Memory (MB): peak = 7372.723 ; gain = 1209.797 ; free physical = 6113 ; free virtual = 41730

Phase 11 Incr Placement Change
Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 7372.723 ; gain = 0.000 ; free physical = 6073 ; free virtual = 41691
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.195. For the most accurate timing information please run report_timing.
Ending IncrPlace Task | Checksum: e1651d5b

Time (s): cpu = 00:04:24 ; elapsed = 00:04:26 . Memory (MB): peak = 7380.723 ; gain = 8.000 ; free physical = 5355 ; free virtual = 40974
Phase 11 Incr Placement Change | Checksum: 1e297ab5e

Time (s): cpu = 00:29:46 ; elapsed = 00:30:03 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5330 ; free virtual = 40950

Phase 12 Build RT Design
Phase 12 Build RT Design | Checksum: a7405c50

Time (s): cpu = 00:31:19 ; elapsed = 00:31:37 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5672 ; free virtual = 41292

Phase 13 Router Initialization

Phase 13.1 Fix Topology Constraints
Phase 13.1 Fix Topology Constraints | Checksum: a7405c50

Time (s): cpu = 00:31:22 ; elapsed = 00:31:40 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5651 ; free virtual = 41270

Phase 13.2 Pre Route Cleanup
Phase 13.2 Pre Route Cleanup | Checksum: 12ff20b4d

Time (s): cpu = 00:31:24 ; elapsed = 00:31:42 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5649 ; free virtual = 41268

Phase 13.3 Update Timing
Phase 13.3 Update Timing | Checksum: 19952d700

Time (s): cpu = 00:33:49 ; elapsed = 00:34:07 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5453 ; free virtual = 41072
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.173  | TNS=0.000  | WHS=-0.968 | THS=-20233.027|


Phase 13.4 Update Timing for Bus Skew

Phase 13.4.1 Update Timing
Phase 13.4.1 Update Timing | Checksum: 1880b4858

Time (s): cpu = 00:35:01 ; elapsed = 00:35:20 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5247 ; free virtual = 40867
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.173  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 13.4 Update Timing for Bus Skew | Checksum: 1ac503b9f

Time (s): cpu = 00:35:03 ; elapsed = 00:35:22 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5356 ; free virtual = 40976
Phase 13 Router Initialization | Checksum: 194faad3f

Time (s): cpu = 00:35:07 ; elapsed = 00:35:26 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5339 ; free virtual = 40959

Phase 14 Initial Routing

Phase 14.1 Global Routing
Phase 14.1 Global Routing | Checksum: 194faad3f

Time (s): cpu = 00:35:08 ; elapsed = 00:35:27 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5325 ; free virtual = 40945
Phase 14 Initial Routing | Checksum: 1fc21f4fb

Time (s): cpu = 00:35:15 ; elapsed = 00:35:34 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5346 ; free virtual = 40966
INFO: [Route 35-580] Design has 6 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+======================================================================================================================================================+======================================================================================================================================================+===========================================================================================================================================================================================================================================================================================================================================+
| Launch Setup Clock                                                                                                                                   | Launch Hold Clock                                                                                                                                    | Pin                                                                                                                                                                                                                                                                                                                                       |
+======================================================================================================================================================+======================================================================================================================================================+===========================================================================================================================================================================================================================================================================================================================================+
| backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK | backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/TXOUTCLK | event_builder/fifo_layer/ch9/norm_fifo.clk_cross_tob_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[22] |
| backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIADI[6]           |
| backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[1]           |
| backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[10]          |
| backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/TXOUTCLK             | event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[18]          |
+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 15 Rip-up And Reroute

Phase 15.1 Global Iteration 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.132 | TNS=-0.492 | WHS=N/A    | THS=N/A    |

Phase 15.1 Global Iteration 0 | Checksum: 2453a7f36

Time (s): cpu = 00:38:41 ; elapsed = 00:39:03 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5348 ; free virtual = 40968

Phase 15.2 Global Iteration 1
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.136  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 15.2 Global Iteration 1 | Checksum: e822826f

Time (s): cpu = 00:40:06 ; elapsed = 00:40:31 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5290 ; free virtual = 40910
Phase 15 Rip-up And Reroute | Checksum: e822826f

Time (s): cpu = 00:40:07 ; elapsed = 00:40:31 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5301 ; free virtual = 40920

Phase 16 Delay and Skew Optimization

Phase 16.1 Delay CleanUp
Phase 16.1 Delay CleanUp | Checksum: e822826f

Time (s): cpu = 00:40:08 ; elapsed = 00:40:32 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5302 ; free virtual = 40921

Phase 16.2 Clock Skew Optimization
Phase 16.2 Clock Skew Optimization | Checksum: e822826f

Time (s): cpu = 00:40:09 ; elapsed = 00:40:33 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5293 ; free virtual = 40913
Phase 16 Delay and Skew Optimization | Checksum: e822826f

Time (s): cpu = 00:40:09 ; elapsed = 00:40:34 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5286 ; free virtual = 40906

Phase 17 Post Hold Fix

Phase 17.1 Hold Fix Iter

Phase 17.1.1 Update Timing
Phase 17.1.1 Update Timing | Checksum: 15874e389

Time (s): cpu = 00:40:41 ; elapsed = 00:41:06 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5298 ; free virtual = 40918
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151  | TNS=0.000  | WHS=-0.601 | THS=-1018.456|

Phase 17.1 Hold Fix Iter | Checksum: 1f03e8d60

Time (s): cpu = 00:40:45 ; elapsed = 00:41:09 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5299 ; free virtual = 40918
Phase 17 Post Hold Fix | Checksum: 173ac8c3c

Time (s): cpu = 00:40:46 ; elapsed = 00:41:10 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5299 ; free virtual = 40918

Phase 18 Timing Verification

Phase 18.1 Update Timing
Phase 18.1 Update Timing | Checksum: 1a73f7b05

Time (s): cpu = 00:41:32 ; elapsed = 00:41:56 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5301 ; free virtual = 40921
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 18 Timing Verification | Checksum: 1a73f7b05

Time (s): cpu = 00:41:33 ; elapsed = 00:41:57 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5298 ; free virtual = 40917

Phase 19 Route finalize
Phase 19 Route finalize | Checksum: 1a73f7b05

Time (s): cpu = 00:41:35 ; elapsed = 00:41:59 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5304 ; free virtual = 40924

Phase 20 Verifying routed nets
Phase 20 Verifying routed nets | Checksum: 1a73f7b05

Time (s): cpu = 00:41:36 ; elapsed = 00:42:00 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5304 ; free virtual = 40924

Phase 21 Depositing Routes
Phase 21 Depositing Routes | Checksum: 1cb2dcb30

Time (s): cpu = 00:42:01 ; elapsed = 00:42:25 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5298 ; free virtual = 40918

Phase 22 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.149  | TNS=0.000  | WHS=0.050  | THS=0.000  |

Phase 22 Post Router Timing | Checksum: 1c9747875

Time (s): cpu = 00:43:54 ; elapsed = 00:44:19 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5401 ; free virtual = 41021
INFO: [Route 35-61] The design met the timing requirement.
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:43:55 ; elapsed = 00:44:20 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5819 ; free virtual = 41438
INFO: [Common 17-83] Releasing license: Implementation
696 Infos, 128 Warnings, 16 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:45:57 ; elapsed = 00:46:23 . Memory (MB): peak = 7382.797 ; gain = 1219.871 ; free physical = 5819 ; free virtual = 41438
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] Git describe set to: v0.5.17-hog7a7ee9a
INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_efex was modified...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] The git SHA value 7a7ee9a will be embedded in the binary file.
INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean.
INFO: [Hog:Msg-0] Git describe set to: v0.5.17-hog7a7ee9a
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/v1VqaazS/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.5.17-hog7a7ee9a...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
report_utilization: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 7382.797 ; gain = 0.000 ; free physical = 5853 ; free virtual = 41476