## Repository info
- Merge request number: 120
- Branch name: 110-create-phase-2-rod

## MR Description
Create projects for the phase-II rods rod_jfex_p1 and rod_efex_p2
Closes #110


## Changelog


## rod_efex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_efex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.098310       |
| TNS:          | 0.000000       |
| WHS:          | 0.050340       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_efex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    36815    |    0         |   0              |    346400        |    10.63     |   
| Slice  Registers |    51592    |    81        |   0              |    692800        |    7.45      |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    203      |    0         |   0              |    600           |    33.83     |   
                                                                                                         
## rod_efex Implementation Utilization report


                                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        --- |         --- |              ---  |             ---  |              
| Slice  LUTs      |    92313    |   0         |   0              |    346400        |    26.65     |    
| Slice  Registers |    145075   |   0         |   0              |    692800        |    20.94     |    
| Block  RAM       Tile |        414 |         0   |              0    |             1180 |         35.08
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |   111       |   0              |    600           |    18.50     |    
                                                                                                         
## rod_efex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 351a952        | 0.5.25      |
| Constraints       | cf2b43f        | 0.5.20      |
| IPbus XML         | b4fb1c8        | 0.5.18      |
| Top Directory     | 989ee7c        | 0.5.24      |
| Hog               | 712a03f        | 7.17.3      |
| **Lib:** rod_efex | 5acf2c9        | 0.5.25      |
| **Lib:** others   | d664b43        | 0.5.23      |



</details>
</p>

 
## rod_jfex


<p>
<details>
<summary>show/hide</summary> 

 ## rod_jfex Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.114715       |
| TNS:          | 0.000000       |
| WHS:          | 0.048049       |
| THS:          | 0.000000       |


 Time requirements are met.



## rod_jfex Synthesis Utilization report


                                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        ---  |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    52163    |    0         |   0              |    346400        |    15.06     |   
| Slice  Registers |    76688    |    81        |   0              |    692800        |    11.07     |   
| Block  RAM       Tile |        23.5 |         0   |              0    |             1180 |         1.99
| DSPs   |         0    |        0    |         0   |              2880 |             0.00 |             
| Bonded IOB       |    155      |    0         |   0              |    600           |    25.83     |   
                                                                                                         
## rod_jfex Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    157427   |     0         |   0              |    346400        |    45.45     |    
| Slice  Registers |    256968   |     0         |   0              |    692800        |    37.09     |    
| Block  RAM       Tile |        725.5 |         0   |              0    |             1180 |         61.48
| DSPs   |         0    |        0     |         0   |              2880 |             0.00 |              
| Bonded IOB       |    111      |     111       |   0              |    600           |    18.50     |    
                                                                                                           
## rod_jfex Version Table

| **File set**      | **Commit SHA** | **Version** |
| ---               | ---            | ---         |
| Global            | 351a952        | 0.5.25      |
| Constraints       | cf2b43f        | 0.5.20      |
| IPbus XML         | b4fb1c8        | 0.5.18      |
| Top Directory     | 1f87e68        | 0.5.15      |
| Hog               | 712a03f        | 7.17.3      |
| **Lib:** rod_jfex | cb3773b        | 0.5.25      |
| **Lib:** others   | d664b43        | 0.5.23      |



</details>
</p>