*** Running vivado with args -log top_rod_efex.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_rod_efex.tcl -notrace ****** Vivado v2022.1 (64-bit) **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022 **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source top_rod_efex.tcl -notrace Command: link_design -top top_rod_efex -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.dcp' for cell 'proc_clock_gen' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.dcp' for cell 'top_vio' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.dcp' for cell 'ttc_source_sel' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_fifo.dcp' for cell 'Bulk_0_64_32/ILA_packet_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_dwidth_64_32/axis_dwidth_64_32.dcp' for cell 'Bulk_0_64_32/data_width_conv' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/axis_data_fifo_0/axis_data_fifo_0.dcp' for cell 'Bulk_0_64_32/main_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/chan_crc_ila.dcp' for cell 'ILA_axi_chan_0/ila_crc_check' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.dcp' for cell 'alternate_cttc.fm_interface_3/clk_blk' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_2.dcp' for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_fullmode.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/DPram_32b/DPram_32b.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/ram0/RAM_0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.dcp' for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.dcp' for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.dcp' for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.dcp' for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.dcp' for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_1.dcp' for cell 'backplane/readout_ctrl/ila_tx0_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.dcp' for cell 'backplane/readout_ctrl/vio_gt_inst' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.dcp' for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_CRC.dcp' for cell 'event_builder/alt_cttc_crc/crc_check_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/bulk_ila.dcp' for cell 'event_builder/bulk_0/bulkl_proc_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bulk_processor/bulk_data_fifo/bulk_data_fifo.dcp' for cell 'event_builder/bulk_0/data_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.dcp' for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/rod_ROctrl_mux_ila.dcp' for cell 'event_builder/readout_controller/readout_ctrl_ila2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/event_builder_fifo/event_builder_fifo.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/debug_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/rx_time_ila.dcp' for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/error_ila.dcp' for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.dcp' for cell 'event_builder/ttc_input/bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_bulk_ttc.dcp' for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_ttc_in.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_in' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_ttc_out.dcp' for cell 'event_builder/ttc_input/ila_ttc_fifo_out' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_l1id_cont.dcp' for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_mgtfsm.dcp' for cell 'fm_interface_1/u0/ila_resetfsm' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.dcp' for cell 'ipbus_blk/ip_addr_probe' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/ipbus/rgmii_rx_fifo_2/rgmii_rx_fifo_2.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_read_fifo_2' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/ethernet_mac_rgmii.dcp' for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i' Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3318.773 ; gain = 0.000 ; free physical = 75780 ; free virtual = 82955 INFO: [Netlist 29-17] Analyzing 11938 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2022.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. proc_clock_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'proc_clock_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Chipscope 16-324] Core: Bulk_0_64_32/ILA_packet_fifo UUID: 63e7dc4f-a901-5f5e-8f15-f44cac18b816 INFO: [Chipscope 16-324] Core: Bulk_1_64_32/ILA_packet_fifo UUID: b894b984-cded-5bd0-92d8-292d78f9765a INFO: [Chipscope 16-324] Core: Bulk_2_64_32/ILA_packet_fifo UUID: 020d2b63-4e4e-5e2e-aab4-4c5b2d6046e9 INFO: [Chipscope 16-324] Core: ILA_axi_chan_0/ila_crc_check UUID: a9e8e6ca-2b1f-5fbe-a871-91755a4a7c6e INFO: [Chipscope 16-324] Core: ILA_axi_chan_6/ila_crc_check UUID: 41f97370-bc3f-56dd-ab00-76683edcad5a INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst UUID: 80888505-1efc-57ae-9e40-8681b86a5f8c INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst UUID: 7200d9a1-8e3d-5fc2-960c-ca771d9eec86 INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/ila_fm UUID: 8097e4b8-b92b-5960-a4df-b73ab5d6cd06 INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_0/vio_fm_reset UUID: f826ca6e-8cf4-5060-b996-19bb9a7821ab INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/ila_fm UUID: b46515df-c8ee-5943-846a-c28f4ef519d1 INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/chan_1/vio_fm_reset UUID: 2bb4310a-a09d-5a1b-b55a-16cdaed8d8de INFO: [Chipscope 16-324] Core: alternate_cttc.fm_interface_3/polarity UUID: 2cb3aefb-fa06-5db0-8650-9045388eb833 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/ila_rx2_inst UUID: f60b8007-6bf8-5822-bc32-cdf6ef756575 INFO: [Chipscope 16-324] Core: backplane/combined_ttc/vio_gt_inst UUID: a6d99938-502c-5867-8e71-028088cb558d INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/ila_tx0_inst UUID: 5af42e05-e58f-565e-bd4b-e3caf0b9b4a7 INFO: [Chipscope 16-324] Core: backplane/readout_ctrl/vio_gt_inst UUID: 0523908b-78fb-555c-8d31-f2c3c610733b INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/ila_rx2_inst UUID: 9bcc70d8-4c9f-5ec9-860b-cad2fd9e719e INFO: [Chipscope 16-324] Core: event_builder/CTTC_receiver/vio_gt_inst UUID: bc513526-9cc8-5253-83cd-9ec640d281c7 INFO: [Chipscope 16-324] Core: event_builder/alt_cttc_crc/crc_check_ila UUID: d7404ee0-8704-5433-8191-e9b8d11eb7ee INFO: [Chipscope 16-324] Core: event_builder/bulk_0/bulkl_proc_probe UUID: 7d9dc169-40d5-56ff-9a38-42ad7dd0b67d INFO: [Chipscope 16-324] Core: event_builder/bulk_1/bulkl_proc_probe UUID: 48639c55-d7f5-5b3f-bf8a-c3e17dffdced INFO: [Chipscope 16-324] Core: event_builder/bulk_2/bulkl_proc_probe UUID: f79c214c-778a-503c-82e0-558ccd7036de INFO: [Chipscope 16-324] Core: event_builder/readout_controller/readout_ctrl_ila2 UUID: 2118af16-197d-5a88-95e6-28dbf9962d95 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/State_machine_ILA UUID: b8ade747-7d7c-5fc7-9f63-b2cb50b3a6e1 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time UUID: 00d8ad3a-1e81-507f-9fb8-068989d0eac6 INFO: [Chipscope 16-324] Core: event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila UUID: 03337b11-edd4-554c-9722-ab13aea48bfc INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_bulk_ttc_fifo UUID: 54b31265-4039-519c-ae13-a6b6c7fda705 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_in UUID: 0d145367-edc8-5440-8a43-c5b7fdc60185 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/ila_ttc_fifo_out UUID: dea619c4-8196-5fc3-a887-501d70a94797 INFO: [Chipscope 16-324] Core: event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check UUID: 0b5e705b-49ad-5d15-9efb-ec02e926d290 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/ila_fm UUID: 39f68e95-8276-57e5-b2ba-d040b8bf414c INFO: [Chipscope 16-324] Core: fm_interface_1/chan_0/vio_fm_reset UUID: b602d903-de6d-5e57-92e3-814b1496a830 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/ila_fm UUID: 312b9249-01c3-5825-bad2-86e782be33e1 INFO: [Chipscope 16-324] Core: fm_interface_1/chan_1/vio_fm_reset UUID: eec5d607-63dd-55c1-a9db-2118e9215856 INFO: [Chipscope 16-324] Core: fm_interface_1/u0/ila_resetfsm UUID: 82d99aa3-751c-5dfe-85d1-97a24142969c INFO: [Chipscope 16-324] Core: ipbus_blk/ip_addr_probe UUID: d3bad9ce-591e-57bb-984d-9f6468850a46 INFO: [Chipscope 16-324] Core: pp_out_fifo_6432/ILA_packet_fifo UUID: b136e600-ef26-57f9-8e20-f80fc6236875 INFO: [Chipscope 16-324] Core: top_vio UUID: 7b2ee998-e565-566c-a490-bae90ac485a9 INFO: [Chipscope 16-324] Core: ttc_source_sel UUID: c1a2c02a-9f6d-5067-b34f-a57ba8dd1b77 Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_0/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] for cell 'fm_interface_1/chan_1/vio_fm_reset' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_out/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_out/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_bulk_ttc/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_bulk_ttc_fifo/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_in_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_in_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_ip_address/vio_ip_address.xdc] for cell 'ipbus_blk/ip_addr_probe' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_board.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/ila_mgtfsm/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/u0/ila_resetfsm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_0/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fullmode/ila_v6_2/constraints/ila_impl.xdc] for cell 'fm_interface_1/chan_1/ila_fm/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'debug_ila_ed1'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/debug_ila_ed1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_0/vio_0.xdc] for cell 'backplane/readout_ctrl/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/rod_ROctrl_mux_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/readout_controller/readout_ctrl_ila2/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xdc] for cell 'backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/readout_ctrl/ila_tx0_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_0/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_crc_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'ILA_axi_chan_6/ila_crc_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/error_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_board.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/processor_in_fifo/processor_in_fifo.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/input_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0' CRITICAL WARNING: [Designutils 20-1281] Could not find module 'data_fifo_vio'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/data_fifo_vio/data_fifo_vio.xdc will not be read for this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'chan_map_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/chan_map_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'aurora_fifo_out_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/aurora_fifo_out_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ila_ttc_in/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/ila_ttc_fifo_in/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ch0'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/axi_ch0/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ch0'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/axi_ch0/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_xadc_wiz_0_0/axi4_subsys_xadc_wiz_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/xadc_wiz_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/jtag_axi.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_1_0/axi4_subsys_axi_iic_1_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_iic_0_0/axi4_subsys_axi_iic_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_gpio_0_0/axi4_subsys_axi_gpio_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_gpio_0/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_emc_0_0/axi4_subsys_axi_emc_0_0_board.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_input_fifo'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/ila_input_fifo/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_input_fifo'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/ila_input_fifo/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/rod_jfex.gen/sources_1/ip/rx_time_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/cttc_crc_test.gen/sources_1/ip/ila_CRC/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/alt_cttc_crc/crc_check_ila/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_CTTC_rx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_ila_1'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/axi_ila_1/ila_v6_2/constraints/ila_impl.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_top/vio_top.xdc] for cell 'top_vio' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' CRITICAL WARNING: [Designutils 20-1281] Could not find module 'pp_ctrl_vio'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/pp_ctrl_vio/pp_ctrl_vio.xdc will not be read for this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_l1id_cont/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_0/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_1/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/bulk_ila/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/bulk_2/bulkl_proc_probe/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/FullMode_tx.xdc] for cell 'alternate_cttc.fm_interface_3/combined_transceiver/FullMode_tx_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' WARNING: [Vivado 12-2489] -period contains time 3.118500 which will be rounded to 3.119 to ensure it is an integer multiple of 1 picosecond [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc:72] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xdc] for cell 'backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'backplane/combined_ttc/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/ila_2/ila_v6_2/constraints/ila_impl.xdc] for cell 'event_builder/CTTC_receiver/ila_rx2_inst/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/CTTC_receiver/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'backplane/combined_ttc/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'event_builder/CTTC_receiver/vio_gt_inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'ttc_source_sel' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/vio_ttc/vio_ttc.xdc] for cell 'alternate_cttc.fm_interface_3/polarity' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc:57] get_clocks: Time (s): cpu = 00:00:29 ; elapsed = 00:00:20 . Memory (MB): peak = 4669.371 ; gain = 818.082 ; free physical = 74577 ; free virtual = 81752 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/packet_processor_clock/packet_processor_clock_board.xdc] for cell 'proc_clock_gen/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_0_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_1_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'Bulk_2_64_32/ILA_packet_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_fifo/ila_v6_2/constraints/ila_impl.xdc] for cell 'pp_out_fifo_6432/ILA_packet_fifo/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'backplane_control_ila'. The XDC file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/rod_efex/backplane_control_ila/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/rod_top.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_0/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'ILA_axi_chan_6/L1A_sync_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_10/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_4l_64b_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_run_phase_alignment_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rx_fsm_reset_done_int_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_rxpmaresetdone_rx_s_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_time_out_wait_bypass_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/hpcnt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/reset_sync_user_clk_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_0_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_1_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_2_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_aurora_lane_simplex_v5_3_i/aurora_rx_1q_hotplug_i/rx_cc_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_1q_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/support_reset_logic_i/gt_rst_r_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/link_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/core_reset_logic_i/tx_lock_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_reset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/gtrxreset_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_CPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_QPLLLOCK_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_RXRESETDONE_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_mmcm_lock_reclocked_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. WARNING: [Constraints 18-401] set_false_path: 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/gt_rxresetfsm_i/sync_pmaresetdone_fallingedge_detect_cdc_sync/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg/Q' is not a valid endpoint. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Resolution: A valid end point is a data pin of a sequential cell or a primary output or inout port. Please validate that all the objects returned by your query belong to this list. INFO: [Common 17-14] Message 'Constraints 18-401' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc:116] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/aurora_gt_12ch_1234.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc:22] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/asynchronous_clocks.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/wiz_experiment.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] WARNING: [Vivado 12-627] No clocks matched 'FM_TXOUTCLK_2'. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:81] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:81] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_clocks FM_TXOUTCLK_2]'. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:81] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-627] No clocks matched 'FM_TXOUTCLK_2'. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:84] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:84] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_clocks FM_TXOUTCLK_2]'. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc:84] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/rod_efex/xdc/FullMode.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/ROD/ipbus/xdc/ethernet_mac_rgmii_example_design.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_hwicap_0_0/axi4_subsys_axi_hwicap_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports -scoped_to_current_instance ext_spi_clk]'. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc:51] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_axi_quad_spi_0_0/axi4_subsys_axi_quad_spi_0_0_clocks.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_clocks.xdc] for cell 'backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_1q/aurora_rx_1q_clocks.xdc] for cell 'backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'alternate_cttc.fm_interface_3/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/clk_wiz_240/clk_wiz_240_late.xdc] for cell 'fm_interface_1/clk_blk/inst' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_0/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_clocks.xdc] for cell 'fm_interface_1/chan_1/u7/FIFO34b/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'alternate_cttc.fm_interface_3/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_0/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fm_status_fifo/fm_status_fifo_clocks.xdc] for cell 'fm_interface_1/chan_1/L1ID_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:30] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:53] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:54] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:73] INFO: [Vivado 12-3272] Current instance is the top level cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' of design 'design_1' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:74] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc] for cell 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/bulk_ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/packet_processor/ttc_header_fifo/ttc_header_fifo_clocks.xdc] for cell 'event_builder/ttc_input/ttc_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch0/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch1/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch10/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch11/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch2/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch3/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch4/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch5/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch6/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch7/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch8/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/aurora_in_fifo/aurora_in_fifo_clocks.xdc] for cell 'event_builder/fifo_layer/ch9/norm_fifo.no_fifo_ila.clk_cross_tob_fifo/clk_cross_fifo/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: alternate_cttc.fm_interface_3/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: alternate_cttc.fm_interface_3/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_0/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: fm_interface_1/chan_1/u7/FIFO34b/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/WRFIFO.WRDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1714] 338 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 2 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5379.016 ; gain = 0.000 ; free physical = 74715 ; free virtual = 81891 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3929 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 3384 instances IOBUF => IOBUF (IBUF, OBUFT): 23 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 42 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances RAM64M => RAM64M (RAMD64E(x4)): 380 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 96 instances 103 Infos, 130 Warnings, 20 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:35 ; elapsed = 00:02:16 . Memory (MB): peak = 5379.016 ; gain = 2335.008 ; free physical = 74715 ; free virtual = 81891 source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design -directive Explore INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx/FullMode_tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/FullMode_tx_CTTC_rx/FullMode_tx_CTTC_rx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/FullMode_tx_CTTC_rx_ex.gen/sources_1/ip/FullMode_tx_CTTC_rx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/combined_ttc/MGT_combined_ttc_rx/MGT_combined_ttc_rx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/MGT_combined_ttc_rx/tcl/v7ht.tcl] Parsing TCL File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/rod_RO_Tx.xci Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/IP/readout_ctrl/rod_RO_Tx/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5387.020 ; gain = 7.992 ; free physical = 74709 ; free virtual = 81885 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74204 ; free virtual = 81386 Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.21 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74202 ; free virtual = 81384 Phase 1 Generate And Synthesize Debug Cores | Checksum: 146b58797 Time (s): cpu = 00:02:06 ; elapsed = 00:02:04 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74202 ; free virtual = 81384 Phase 2 Retarget INFO: [Opt 31-1287] Pulled Inverter Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_0_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_0_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_1_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_1_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance Bulk_2_64_32/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance Bulk_2_64_32/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance ILA_axi_chan_0/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance ILA_axi_chan_6/ila_crc_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance alternate_cttc.fm_interface_3/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[10]_i_3, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance alternate_cttc.fm_interface_3/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance alternate_cttc.fm_interface_3/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_switch_control_i/UFC_STORAGE_SELECT_Buffer[0]_i_1 into driver instance backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/rx_ll_i/rx_ll_ufc_datapath_i/ufc_storage_count_control_i/storage_count_r[0]_i_3, which resulted in an inversion of 11 pins INFO: [Opt 31-1287] Pulled Inverter backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance backplane/combined_ttc/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[10]_i_3, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/gt0_rxresetfsm_i/time_out_counter[0]_i_1 into driver instance backplane/combined_ttc/sume_RO_Rx_support_i/cttc_Rx_init_i/U0/gt0_rxresetfsm_i/time_out_2ms_i_2, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter backplane/pwer_on_rst/count[31]_i_1 into driver instance backplane_i_1, which resulted in an inversion of 3 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/CTTC_receiver/ila_rx2_inst/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[10]_i_3, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/alt_cttc_crc/crc_check_ila/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/alt_cttc_crc/crc_check_ila/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_0/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_0/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_0/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_1/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_1/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_1/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_2/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/bulk_2/bulkl_proc_probe/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/bulk_2/data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/bulk_2/stretcher/data_fifo_i_1, which resulted in an inversion of 1 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch0/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch1/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__1, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch10/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__15, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch11/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__21, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch2/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__3, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch3/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__5, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch4/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__7, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch5/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__9, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch6/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__11, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch7/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__17, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch8/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__13, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/ch9/norm_fifo.calo_fifo/clk_cross_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/backplane_control_reg/clk_cross_fifo_i_1__19, which resulted in an inversion of 4 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/readout_controller/readout_ctrl_ila2/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/readout_controller/readout_ctrl_ila2/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/State_machine_ILA/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/debug_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/event_fifo_i_1, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/event_builder_0/ila_pkt_rx_time/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/gen_reg.status_regs/l1id_capt/no_sim_regs.L1ID_Capture_Control_reg/stb[0]_i_1__3 into driver instance ipbus_blk/ipbus/ipbus/trans/sm/ipbw_Processor[ipb_write]_INST_0, which resulted in an inversion of 418 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/tob_processor_0/gen_reg.status_regs/no_sim_regs.chan_error_mapper/error_map_ila/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 14 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[15]_i_1 into driver instance event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[4]_i_3, which resulted in an inversion of 6 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_bulk_ttc_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_ttc_fifo_in/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_ttc_fifo_in/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 13 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/ila_ttc_fifo_out/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 15 pins INFO: [Opt 31-1287] Pulled Inverter event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance event_builder/ttc_input/l1id_continuity_checker/ila_l1id_cont_check/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter fm_interface_1/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_1/chan_0/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter fm_interface_1/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance fm_interface_1/chan_1/ila_fm/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_3, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/AXI_EMC_NATIVE_INTERFACE_I/rnw_reg_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/AXI_EMC_NATIVE_INTERFACE_I/AXI_EMC_ADDR_GEN_INSTANCE_I/BUS2IP_ADDR_GEN_DATA_WDTH_32.bus2ip_addr_i[11]_i_3, which resulted in an inversion of 63 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/COUNTERS_I/TWRCNT_I/PERBIT_GEN[4].MULT_AND_i1_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_emc_0/U0/EMC_CTRL_I/COUNTERS_I/TWRCNT_I/FSM_onehot_crnt_state[4]_i_3, which resulted in an inversion of 8 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_hwicap_0/U0/ICAP_SHARED.HWICAP_CTRL_I/IPIC_IF_I/RD_FIFO.RDDATA_FIFO_I/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_0/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_2, which resulted in an inversion of 5 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_iic_1/U0/X_IIC/WRITE_FIFO_I/sr_i[0]_i_2, which resulted in an inversion of 5 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.si_transactor_aw/gen_multi_thread.active_target[8]_i_1__0 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_multi_thread.active_target[8]_i_2, which resulted in an inversion of 6 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.si_transactor_aw/gen_multi_thread.active_target[9]_i_1__0 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_multi_thread.active_target[9]_i_2__0, which resulted in an inversion of 5 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_1 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_2, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[6]_i_3 into driver instance ipbus_blk/axi4_subsys/axi4_subsys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Count[6]_i_4, which resulted in an inversion of 2 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/primary_mode.IPAM_block/tick_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/primary_mode.IPAM_block/tick_counter.counter_int[23]_i_3, which resulted in an inversion of 24 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/rx_reset_block/ip_pkt.pkt_data[71]_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/rx_reset_block/build_packet.send_buf_int_i_4__1, which resulted in an inversion of 101 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/rx_transactor/ready_i_1 into driver instance ipbus_blk/ipbus/ipbus/udp_if/rx_transactor/history_block.event_pending_i_2, which resulted in an inversion of 132 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/ipbus/udp_if/tx_transactor/resend_buf[3]_i_2 into driver instance ipbus_blk/ipbus/ipbus/udp_if/tx_transactor/resend_buf[3]_i_3, which resulted in an inversion of 5 pins INFO: [Opt 31-1287] Pulled Inverter ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0/ethernet_mac_rgmii_core/sync_stats_reset/async_rst0_i_1 into driver instance ipbus_blk/ipbus/example_resets/tri_mode_ethernet_mac_i_i_1, which resulted in an inversion of 1 pins INFO: [Opt 31-1287] Pulled Inverter pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/current_state[0]_i_1 into driver instance pp_out_fifo_6432/ILA_packet_fifo/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[9]_i_4, which resulted in an inversion of 12 pins INFO: [Opt 31-1287] Pulled Inverter pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 into driver instance pp_out_fifo_6432/main_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst//i_, which resulted in an inversion of 2 pins INFO: [Opt 31-138] Pushed 79 inverter(s) to 656 load pin(s). In IDDR TRANSFORM INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 123b96828 Time (s): cpu = 00:02:21 ; elapsed = 00:02:20 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74424 ; free virtual = 81605 INFO: [Opt 31-389] Phase Retarget created 418 cells and removed 1865 cells INFO: [Opt 31-1021] In phase Retarget, 2578 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s). Phase 3 Constant propagation | Checksum: 170abe77b Time (s): cpu = 00:02:25 ; elapsed = 00:02:23 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74427 ; free virtual = 81608 INFO: [Opt 31-389] Phase Constant propagation created 354 cells and removed 1692 cells INFO: [Opt 31-1021] In phase Constant propagation, 1986 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep INFO: [Opt 31-120] Instance event_builder/ttc_input/ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1_HD5019) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. INFO: [Opt 31-120] Instance event_builder/ttc_input/bulk_ttc_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gaf.c3 (ttc_header_fifo_compare_1) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance. Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design. Phase 4 Sweep | Checksum: baf0f358 Time (s): cpu = 00:02:47 ; elapsed = 00:02:45 . Memory (MB): peak = 5387.020 ; gain = 0.000 ; free physical = 74408 ; free virtual = 81590 INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 8684 cells INFO: [Opt 31-1021] In phase Sweep, 21147 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization Phase 5 BUFG optimization | Checksum: baf0f358 Time (s): cpu = 00:02:51 ; elapsed = 00:02:48 . Memory (MB): peak = 5411.031 ; gain = 24.012 ; free physical = 74408 ; free virtual = 81590 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: baf0f358 Time (s): cpu = 00:02:52 ; elapsed = 00:02:49 . Memory (MB): peak = 5411.031 ; gain = 24.012 ; free physical = 74409 ; free virtual = 81591 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist INFO: [Opt 31-1287] Pulled Inverter event_builder/fifo_layer/gen_reg.registers/first_last_encode/low_high.high_chan[3]_i_1 into driver instance event_builder/fifo_layer/gen_reg.registers/first_last_encode/high_low.low_chan[2]_i_3, which resulted in an inversion of 5 pins Phase 7 Post Processing Netlist | Checksum: f8fe5468 Time (s): cpu = 00:02:53 ; elapsed = 00:02:50 . Memory (MB): peak = 5411.031 ; gain = 24.012 ; free physical = 74409 ; free virtual = 81591 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 2101 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 418 | 1865 | 2578 | | Constant propagation | 354 | 1692 | 1986 | | Sweep | 11 | 8684 | 21147 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 2101 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.5 . Memory (MB): peak = 5411.031 ; gain = 0.000 ; free physical = 74411 ; free virtual = 81593 Ending Logic Optimization Task | Checksum: ea7c4184 Time (s): cpu = 00:02:57 ; elapsed = 00:02:54 . Memory (MB): peak = 5411.031 ; gain = 24.012 ; free physical = 74411 ; free virtual = 81593 Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] from IP /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/axi4_subsys_jtag_axi_0_0.xci Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc:69] all_fanout: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5411.031 ; gain = 0.000 ; free physical = 74146 ; free virtual = 81328 Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/BD/ip/axi4_subsys_jtag_axi_0_0/constraints/axi4_subsys_jtag_axi_0_0_impl.xdc] for cell 'ipbus_blk/axi4_subsys/axi4_subsys_i/jtag_axi_0/U0' Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5411.031 ; gain = 0.000 ; free physical = 74146 ; free virtual = 81328 Ending Netlist Obfuscation Task | Checksum: ea7c4184 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 5411.031 ; gain = 0.000 ; free physical = 74145 ; free virtual = 81327 INFO: [Common 17-83] Releasing license: Implementation 215 Infos, 130 Warnings, 20 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:03:36 ; elapsed = 00:03:34 . Memory (MB): peak = 5411.031 ; gain = 32.016 ; free physical = 74145 ; free virtual = 81327 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 5419.035 ; gain = 0.000 ; free physical = 73979 ; free virtual = 81295 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 5419.039 ; gain = 8.008 ; free physical = 74047 ; free virtual = 81296 INFO: [runtcl-4] Executing : report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx Command: report_drc -file top_rod_efex_drc_opted.rpt -pb top_rod_efex_drc_opted.pb -rpx top_rod_efex_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:56 ; elapsed = 00:00:57 . Memory (MB): peak = 5427.039 ; gain = 8.000 ; free physical = 73854 ; free virtual = 81104 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'Explore' directive. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5427.051 ; gain = 0.000 ; free physical = 73850 ; free virtual = 81099 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: bfded842 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 5427.051 ; gain = 0.000 ; free physical = 73849 ; free virtual = 81099 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5427.051 ; gain = 0.000 ; free physical = 73849 ; free virtual = 81099 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 52e33f74 Time (s): cpu = 00:02:05 ; elapsed = 00:02:30 . Memory (MB): peak = 5994.000 ; gain = 566.949 ; free physical = 73341 ; free virtual = 80591 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 135f95192 Time (s): cpu = 00:03:11 ; elapsed = 00:03:37 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 73068 ; free virtual = 80318 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 135f95192 Time (s): cpu = 00:03:12 ; elapsed = 00:03:38 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 73068 ; free virtual = 80318 Phase 1 Placer Initialization | Checksum: 135f95192 Time (s): cpu = 00:03:12 ; elapsed = 00:03:39 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 73057 ; free virtual = 80307 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18b01a9c8 Time (s): cpu = 00:03:35 ; elapsed = 00:04:02 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 72916 ; free virtual = 80166 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d8de146f Time (s): cpu = 00:03:55 ; elapsed = 00:04:23 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 72927 ; free virtual = 80177 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d5332539 Time (s): cpu = 00:03:56 ; elapsed = 00:04:23 . Memory (MB): peak = 6602.398 ; gain = 1175.348 ; free physical = 72927 ; free virtual = 80177 Phase 2.4 Global Placement Core Phase 2.4.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 9339 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 4055 nets or LUTs. Breaked 0 LUT, combined 4055 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6694.727 ; gain = 0.000 ; free physical = 72853 ; free virtual = 80103 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 4055 | 4055 | 0 | 1 | 00:00:06 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:02 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 4055 | 4055 | 0 | 9 | 00:00:09 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.1 Physical Synthesis In Placer | Checksum: 1f9172f7f Time (s): cpu = 00:07:57 ; elapsed = 00:08:32 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72855 ; free virtual = 80104 Phase 2.4 Global Placement Core | Checksum: 172c9e45f Time (s): cpu = 00:08:08 ; elapsed = 00:08:43 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72831 ; free virtual = 80080 Phase 2 Global Placement | Checksum: 172c9e45f Time (s): cpu = 00:08:08 ; elapsed = 00:08:43 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72938 ; free virtual = 80188 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ee5f1549 Time (s): cpu = 00:08:31 ; elapsed = 00:09:06 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72918 ; free virtual = 80168 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 178e43411 Time (s): cpu = 00:09:20 ; elapsed = 00:09:56 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72880 ; free virtual = 80130 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 19bb5f54f Time (s): cpu = 00:09:23 ; elapsed = 00:09:59 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72885 ; free virtual = 80135 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1c42e4b75 Time (s): cpu = 00:09:28 ; elapsed = 00:10:04 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72884 ; free virtual = 80134 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1fefa3fa4 Time (s): cpu = 00:10:21 ; elapsed = 00:10:57 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72884 ; free virtual = 80134 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: 19ddfeeaa Time (s): cpu = 00:11:54 ; elapsed = 00:12:31 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72612 ; free virtual = 79861 Phase 3.6 Small Shape Detail Placement | Checksum: 19ddfeeaa Time (s): cpu = 00:11:56 ; elapsed = 00:12:33 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72678 ; free virtual = 79928 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 247cd6f9f Time (s): cpu = 00:12:06 ; elapsed = 00:12:43 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72689 ; free virtual = 79939 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1af79edcb Time (s): cpu = 00:12:14 ; elapsed = 00:12:51 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72688 ; free virtual = 79938 Phase 3 Detail Placement | Checksum: 1af79edcb Time (s): cpu = 00:12:16 ; elapsed = 00:12:52 . Memory (MB): peak = 6694.727 ; gain = 1267.676 ; free physical = 72690 ; free virtual = 79939 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'ipbus_blk/ipbus/trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/U0_rgmii_rx_clk' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ethernet_mac_rgmii/synth/ethernet_mac_rgmii_clocks.xdc:29] INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1bc2103db Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.459 | TNS=-7.226 | Phase 1 Physical Synthesis Initialization | Checksum: 1d46a8d0e Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 6770.539 ; gain = 0.000 ; free physical = 72605 ; free virtual = 79855 INFO: [Place 46-33] Processed net ipbus_blk/ipbus/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 133af3c81 Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 6770.539 ; gain = 0.000 ; free physical = 72604 ; free virtual = 79854 Phase 4.1.1.1 BUFG Insertion | Checksum: 1bc2103db Time (s): cpu = 00:14:01 ; elapsed = 00:14:38 . Memory (MB): peak = 6770.539 ; gain = 1343.488 ; free physical = 72610 ; free virtual = 79860 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.057. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 17fa992f5 Time (s): cpu = 00:16:26 ; elapsed = 00:17:04 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72594 ; free virtual = 79843 Time (s): cpu = 00:16:26 ; elapsed = 00:17:04 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72602 ; free virtual = 79852 Phase 4.1 Post Commit Optimization | Checksum: 17fa992f5 Time (s): cpu = 00:16:28 ; elapsed = 00:17:06 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72602 ; free virtual = 79852 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 17fa992f5 Time (s): cpu = 00:16:30 ; elapsed = 00:17:08 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72618 ; free virtual = 79867 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 2x2| 2x2| |___________|___________________|___________________| | West| 2x2| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 17fa992f5 Time (s): cpu = 00:16:32 ; elapsed = 00:17:10 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72620 ; free virtual = 79869 Phase 4.3 Placer Reporting | Checksum: 17fa992f5 Time (s): cpu = 00:16:34 ; elapsed = 00:17:12 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72619 ; free virtual = 79869 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 6786.539 ; gain = 0.000 ; free physical = 72621 ; free virtual = 79871 Time (s): cpu = 00:16:34 ; elapsed = 00:17:12 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72621 ; free virtual = 79871 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1595943fa Time (s): cpu = 00:16:35 ; elapsed = 00:17:13 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72621 ; free virtual = 79871 Ending Placer Task | Checksum: 11ea9b6e6 Time (s): cpu = 00:16:37 ; elapsed = 00:17:15 . Memory (MB): peak = 6786.539 ; gain = 1359.488 ; free physical = 72621 ; free virtual = 79871 INFO: [Common 17-83] Releasing license: Implementation 255 Infos, 130 Warnings, 20 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:16:56 ; elapsed = 00:17:34 . Memory (MB): peak = 6786.539 ; gain = 1359.500 ; free physical = 72873 ; free virtual = 80123 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 6786.539 ; gain = 0.000 ; free physical = 72453 ; free virtual = 80087 report_design_analysis: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 6786.539 ; gain = 0.000 ; free physical = 72440 ; free virtual = 80073 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:12 ; elapsed = 00:01:12 . Memory (MB): peak = 6786.543 ; gain = 0.004 ; free physical = 72739 ; free virtual = 80080 INFO: [runtcl-4] Executing : report_io -file top_rod_efex_io_placed.rpt report_io: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6786.543 ; gain = 0.000 ; free physical = 72686 ; free virtual = 80028 INFO: [runtcl-4] Executing : report_utilization -file top_rod_efex_utilization_placed.rpt -pb top_rod_efex_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_rod_efex_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:01 . Memory (MB): peak = 6786.543 ; gain = 0.000 ; free physical = 72734 ; free virtual = 80079 Command: phys_opt_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 266 Infos, 130 Warnings, 20 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:06 . Memory (MB): peak = 6786.551 ; gain = 0.008 ; free physical = 72668 ; free virtual = 80013 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 6786.551 ; gain = 0.000 ; free physical = 72248 ; free virtual = 79977 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/impl_1/top_rod_efex_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 6786.551 ; gain = 0.000 ; free physical = 72545 ; free virtual = 79981 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: 4e3c12b1 ConstDB: 0 ShapeSum: d06da435 RouteDB: 0 Post Restoration Checksum: NetGraph: ca3dcd7a NumContArr: 7f193361 Constraints: 0 Timing: 0 Phase 1 Build RT Design | Checksum: 1495700db Time (s): cpu = 00:02:29 ; elapsed = 00:02:29 . Memory (MB): peak = 6991.602 ; gain = 160.062 ; free physical = 72259 ; free virtual = 79695 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1495700db Time (s): cpu = 00:02:31 ; elapsed = 00:02:32 . Memory (MB): peak = 6991.602 ; gain = 160.062 ; free physical = 72240 ; free virtual = 79675 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1495700db Time (s): cpu = 00:02:32 ; elapsed = 00:02:33 . Memory (MB): peak = 6991.602 ; gain = 160.062 ; free physical = 72240 ; free virtual = 79675 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 77251ede Time (s): cpu = 00:05:05 ; elapsed = 00:05:10 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72108 ; free virtual = 79544 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.062 | TNS=0.000 | WHS=-0.961 | THS=-17360.780| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 11857b2e7 Time (s): cpu = 00:06:06 ; elapsed = 00:06:10 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72069 ; free virtual = 79505 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.062 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.4 Update Timing for Bus Skew | Checksum: 80e33e8a Time (s): cpu = 00:06:08 ; elapsed = 00:06:12 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72064 ; free virtual = 79500 Router Utilization Summary Global Vertical Routing Utilization = 0.166763 % Global Horizontal Routing Utilization = 0.241743 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 212864 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 212864 Number of Partially Routed Nets = 0 Number of Node Overlaps = 6 Phase 2 Router Initialization | Checksum: 18ba4998a Time (s): cpu = 00:06:10 ; elapsed = 00:06:15 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72061 ; free virtual = 79497 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 18ba4998a Time (s): cpu = 00:06:11 ; elapsed = 00:06:15 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72061 ; free virtual = 79497 Phase 3 Initial Routing | Checksum: 9757729d Time (s): cpu = 00:07:14 ; elapsed = 00:07:19 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72029 ; free virtual = 79465 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 18298 Number of Nodes with overlaps = 1932 Number of Nodes with overlaps = 345 Number of Nodes with overlaps = 110 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.048 | TNS=-0.068 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 97b8b2f5 Time (s): cpu = 00:13:13 ; elapsed = 00:13:21 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72015 ; free virtual = 79450 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1157 Number of Nodes with overlaps = 181 Number of Nodes with overlaps = 47 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.058 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1c39957e3 Time (s): cpu = 00:14:15 ; elapsed = 00:14:24 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72011 ; free virtual = 79447 Phase 4 Rip-up And Reroute | Checksum: 1c39957e3 Time (s): cpu = 00:14:15 ; elapsed = 00:14:25 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72011 ; free virtual = 79447 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1c39957e3 Time (s): cpu = 00:14:16 ; elapsed = 00:14:26 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72011 ; free virtual = 79447 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1c39957e3 Time (s): cpu = 00:14:17 ; elapsed = 00:14:26 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72011 ; free virtual = 79447 Phase 5 Delay and Skew Optimization | Checksum: 1c39957e3 Time (s): cpu = 00:14:17 ; elapsed = 00:14:27 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72011 ; free virtual = 79447 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 129874932 Time (s): cpu = 00:14:42 ; elapsed = 00:14:52 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72008 ; free virtual = 79444 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.099 | TNS=0.000 | WHS=-0.482 | THS=-751.708| Phase 6.1.2 Lut RouteThru Assignment for hold Phase 6.1.2 Lut RouteThru Assignment for hold | Checksum: 19a622365 Time (s): cpu = 00:14:59 ; elapsed = 00:15:08 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72005 ; free virtual = 79441 Phase 6.1 Hold Fix Iter | Checksum: 19a622365 Time (s): cpu = 00:14:59 ; elapsed = 00:15:09 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72005 ; free virtual = 79441 Phase 6 Post Hold Fix | Checksum: 1abbb5c26 Time (s): cpu = 00:15:00 ; elapsed = 00:15:10 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72005 ; free virtual = 79441 Phase 7 Timing Verification Phase 7.1 Update Timing Phase 7.1 Update Timing | Checksum: 12e87d00a Time (s): cpu = 00:15:33 ; elapsed = 00:15:42 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72010 ; free virtual = 79446 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.099 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 7 Timing Verification | Checksum: 12e87d00a Time (s): cpu = 00:15:33 ; elapsed = 00:15:43 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72010 ; free virtual = 79446 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 10.7922 % Global Horizontal Routing Utilization = 10.5559 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 12e87d00a Time (s): cpu = 00:15:35 ; elapsed = 00:15:45 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72005 ; free virtual = 79441 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 12e87d00a Time (s): cpu = 00:15:36 ; elapsed = 00:15:46 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72001 ; free virtual = 79437 Phase 10 Depositing Routes INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y11/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y10/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_13/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y2/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y3/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y2/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_14/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/readout_ctrl/rod_RO_Tx_support_i/rod_RO_Tx_init_i/U0/rod_RO_Tx_i/gt0_rod_RO_Tx_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y0/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y23/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y22/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y21/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y20/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_11/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y15/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y14/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_12/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y3/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y27/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_10/aurora_module_i/no_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y26/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y35/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y34/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y33/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y32/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_9/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y8/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin alternate_cttc.fm_interface_3/combined_transceiver/common0_i/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y9/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[0].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gt_channel[1].g_gth.gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X0Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin fm_interface_1/u0/g_gthe2_common.gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X0Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y4/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y5/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y6/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_3/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y1/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y12/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y13/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_4/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y3/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y16/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y17/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y18/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y19/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_5/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y4/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y24/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y25/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_6/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y6/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt0_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y28/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt1_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y29/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt2_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y30/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.aurora_rx_1q_i/U0/gt_wrapper_i/aurora_rx_1q_multi_gt_i/gt3_aurora_rx_1q_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y31/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_7/aurora_module_i/use_common.gt_common_support/gthe2_common_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y7/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y36/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.aurora_rx_4l_64b_i/U0/gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/gthe2_i/GTREFCLK0 to physical pin GTHE2_CHANNEL_X1Y37/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin backplane/aurora_8/aurora_module_i/use_common.gt_common_support/gthe2_common_lane1_i/GTREFCLK0 to physical pin GTHE2_COMMON_X1Y9/GTNORTHREFCLK1 Phase 10 Depositing Routes | Checksum: 163e5ffbb Time (s): cpu = 00:15:54 ; elapsed = 00:16:04 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 71993 ; free virtual = 79429 Phase 11 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.098 | TNS=0.000 | WHS=0.050 | THS=0.000 | Phase 11 Post Router Timing | Checksum: 178f14394 Time (s): cpu = 00:17:21 ; elapsed = 00:17:31 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 71742 ; free virtual = 79178 INFO: [Route 35-61] The design met the timing requirement. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:17:22 ; elapsed = 00:17:32 . Memory (MB): peak = 7416.652 ; gain = 585.113 ; free physical = 72202 ; free virtual = 79638 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 335 Infos, 130 Warnings, 20 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:18:51 ; elapsed = 00:19:02 . Memory (MB): peak = 7416.652 ; gain = 630.102 ; free physical = 72203 ; free virtual = 79639 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:Msg-0] Git describe set to: v0.5.25-351A952 INFO: [Hog:Msg-0] Evaluating last git SHA in which rod_efex was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:Msg-0] The git SHA value 351a952 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for rod_efex... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Top/rod_efex clean. INFO: [Hog:Msg-0] Git describe set to: v0.5.25-351A952 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/bin/rod_efex-v0.5.25-351A952... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 7416.652 ; gain = 0.000 ; free physical = 72203 ; free virtual = 79643