*** Running vivado with args -log vio_fullmode_reset.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_fullmode_reset.tcl ****** Vivado v2022.1 (64-bit) **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022 **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source vio_fullmode_reset.tcl -notrace Command: synth_design -top vio_fullmode_reset -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 11883 WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023] WARNING: [Synth 8-9187] begin/end is required for generate-for in this mode of verilog [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/hdl/vio_v3_0_syn_rfs.v:1365] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3035.973 ; gain = 0.000 ; free physical = 70668 ; free virtual = 77537 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_fullmode_reset' [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/synth/vio_fullmode_reset.v:49] INFO: [Synth 8-6155] done synthesizing module 'vio_fullmode_reset' (0#1) [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/synth/vio_fullmode_reset.v:49] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_EFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_EFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_fullmode_reset does not have driver. [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/synth/vio_fullmode_reset.v:83] WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Read in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[15] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[14] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[13] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[12] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[11] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[10] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[9] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[8] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[7] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[6] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[5] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[4] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[3] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[2] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[1] in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_out_one is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Read in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[15] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[14] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[13] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[12] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[11] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[10] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[9] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[8] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[7] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[6] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[5] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[4] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_Data_in[3] in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_out_one__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port Bus_rst in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port Rd_probe_width in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port Internal_cnt_rst in module vio_v3_0_22_probe_width is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in8[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in9[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in10[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in11[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in12[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in13[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in14[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in15[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in16[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in17[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in18[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in19[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in20[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in21[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in22[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in23[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in24[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in25[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in26[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in27[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in28[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in29[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in30[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in31[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in32[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in33[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in34[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in35[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in36[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in37[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in38[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in39[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in40[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in41[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in42[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in43[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in44[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in45[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in46[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in47[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in48[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in49[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in50[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in51[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in52[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in53[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in54[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in55[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in56[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in57[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in58[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in59[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in60[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in61[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in62[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in63[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in64[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in65[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in66[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in67[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in68[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in69[0] in module vio_v3_0_22_vio is either unconnected or has no load WARNING: [Synth 8-7129] Port probe_in70[0] in module vio_v3_0_22_vio is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3035.973 ; gain = 0.000 ; free physical = 71749 ; free virtual = 78619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3035.973 ; gain = 0.000 ; free physical = 71735 ; free virtual = 78605 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3035.973 ; gain = 0.000 ; free physical = 71735 ; free virtual = 78605 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3035.973 ; gain = 0.000 ; free physical = 71721 ; free virtual = 78591 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset_ooc.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset_ooc.xdc] Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/vio_fullmode_reset/vio_fullmode_reset.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vio_fullmode_reset_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/vio_fullmode_reset_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.805 ; gain = 0.000 ; free physical = 71574 ; free virtual = 78446 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3187.805 ; gain = 0.000 ; free physical = 71574 ; free virtual = 78446 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71522 ; free virtual = 78394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71522 ; free virtual = 78394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71522 ; free virtual = 78394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71609 ; free virtual = 78482 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 2 Input 1 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 16 Bit Registers := 12 8 Bit Registers := 5 7 Bit Registers := 1 5 Bit Registers := 1 3 Bit Registers := 4 2 Bit Registers := 1 1 Bit Registers := 20 +---Muxes : 2 Input 16 Bit Muxes := 3 3 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 9 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71546 ; free virtual = 78423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71659 ; free virtual = 78550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71659 ; free virtual = 78550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 71655 ; free virtual = 78546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73077 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73077 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73076 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73076 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73076 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73076 ; free virtual = 79963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 2| |2 |LUT2 | 5| |3 |LUT3 | 53| |4 |LUT4 | 13| |5 |LUT5 | 13| |6 |LUT6 | 77| |7 |FDRE | 308| +------+-----+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73075 ; free virtual = 79962 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 286 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 3187.805 ; gain = 0.000 ; free physical = 73116 ; free virtual = 80003 Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3187.805 ; gain = 151.832 ; free physical = 73117 ; free virtual = 80004 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3187.805 ; gain = 0.000 ; free physical = 73382 ; free virtual = 80269 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3187.805 ; gain = 0.000 ; free physical = 73116 ; free virtual = 80005 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete, checksum: 1c235eae INFO: [Common 17-83] Releasing license: Synthesis 17 Infos, 157 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:52 ; elapsed = 00:00:49 . Memory (MB): peak = 3187.805 ; gain = 160.055 ; free physical = 72984 ; free virtual = 79873 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/vio_fullmode_reset_synth_1/vio_fullmode_reset.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_fullmode_reset, cache-ID = 26733f02502cba7e INFO: [Coretcl 2-1174] Renamed 9 cell refs. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/3zfgtUvw/0/atlas-l1calo-efex/RODFirmware/Projects/rod_efex/rod_efex.runs/vio_fullmode_reset_synth_1/vio_fullmode_reset.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_fullmode_reset_utilization_synth.rpt -pb vio_fullmode_reset_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 19:45:13 2023...