*** Running vivado with args -log dwidth_convert.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dwidth_convert.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2022.1 (64-bit) **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022 **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. source dwidth_convert.tcl -notrace create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3021.875 ; gain = 2.020 ; free physical = 38774 ; free virtual = 98788 Command: synth_design -top dwidth_convert -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 6436 WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/opt/Xilinx/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3030.098 ; gain = 0.000 ; free physical = 36521 ; free virtual = 96535 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'dwidth_convert' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/synth/dwidth_convert.v:53] INFO: [Synth 8-6157] synthesizing module 'axis_dwidth_converter_v1_1_25_axis_dwidth_converter' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_dwidth_converter_v1_1_vl_rfs.v:809] INFO: [Synth 8-6157] synthesizing module 'axis_dwidth_converter_v1_1_25_axisc_upsizer' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_dwidth_converter_v1_1_vl_rfs.v:436] INFO: [Synth 8-6155] done synthesizing module 'axis_dwidth_converter_v1_1_25_axisc_upsizer' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_dwidth_converter_v1_1_vl_rfs.v:436] INFO: [Synth 8-6157] synthesizing module 'axis_register_slice_v1_1_26_axis_register_slice' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:2837] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:809] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:809] INFO: [Synth 8-6157] synthesizing module 'axis_register_slice_v1_1_26_axisc_register_slice' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:1935] INFO: [Synth 8-6155] done synthesizing module 'axis_register_slice_v1_1_26_axisc_register_slice' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:1935] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:991] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:991] INFO: [Synth 8-6155] done synthesizing module 'axis_register_slice_v1_1_26_axis_register_slice' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:2837] INFO: [Synth 8-6157] synthesizing module 'axis_register_slice_v1_1_26_axis_register_slice__parameterized0' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:2837] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector__parameterized0' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:809] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_axis2vector__parameterized0' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:809] INFO: [Synth 8-6157] synthesizing module 'axis_register_slice_v1_1_26_axisc_register_slice__parameterized0' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:1935] INFO: [Synth 8-6155] done synthesizing module 'axis_register_slice_v1_1_26_axisc_register_slice__parameterized0' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:1935] INFO: [Synth 8-6157] synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis__parameterized0' [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:991] INFO: [Synth 8-6155] done synthesizing module 'axis_infrastructure_v1_1_0_util_vector2axis__parameterized0' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_infrastructure_v1_1_vl_rfs.v:991] INFO: [Synth 8-6155] done synthesizing module 'axis_register_slice_v1_1_26_axis_register_slice__parameterized0' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_register_slice_v1_1_vl_rfs.v:2837] INFO: [Synth 8-6155] done synthesizing module 'axis_dwidth_converter_v1_1_25_axis_dwidth_converter' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/hdl/axis_dwidth_converter_v1_1_vl_rfs.v:809] INFO: [Synth 8-6155] done synthesizing module 'dwidth_convert' (0#1) [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/synth/dwidth_convert.v:53] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ROD_JFEX_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic OTHERS_SHA WARNING: [Synth 8-7129] Port ACLK in module axis_register_slice_v1_1_26_axisc_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK2X in module axis_register_slice_v1_1_26_axisc_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axis_register_slice_v1_1_26_axisc_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLKEN in module axis_register_slice_v1_1_26_axisc_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[7] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[6] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[5] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[4] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[3] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[2] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[1] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[0] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TID[0] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TDEST[0] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[7] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[6] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[5] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[4] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[3] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[2] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[1] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[0] in module axis_infrastructure_v1_1_0_util_axis2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axis_register_slice_v1_1_26_axisc_register_slice is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK2X in module axis_register_slice_v1_1_26_axisc_register_slice is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axis_register_slice_v1_1_26_axisc_register_slice is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLKEN in module axis_register_slice_v1_1_26_axisc_register_slice is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[3] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[2] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[1] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TSTRB[0] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TID[0] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TDEST[0] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[3] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[2] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[1] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port TUSER[0] in module axis_infrastructure_v1_1_0_util_axis2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[3] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[2] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[1] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tuser[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3030.098 ; gain = 0.000 ; free physical = 37627 ; free virtual = 97642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3030.098 ; gain = 0.000 ; free physical = 37620 ; free virtual = 97635 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3030.098 ; gain = 0.000 ; free physical = 37620 ; free virtual = 97635 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3030.098 ; gain = 0.000 ; free physical = 37611 ; free virtual = 97626 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/dwidth_convert_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/dwidth_convert/dwidth_convert_ooc.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/dwidth_convert_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/dwidth_convert_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3175.930 ; gain = 0.000 ; free physical = 37315 ; free virtual = 97331 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3175.930 ; gain = 0.000 ; free physical = 37311 ; free virtual = 97327 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38051 ; free virtual = 98072 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38051 ; free virtual = 98072 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/dwidth_convert_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38051 ; free virtual = 98072 --------------------------------------------------------------------------------- INFO: [Synth 8-4490] FSM extraction disabled for register 'state_reg' through user attribute --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38019 ; free virtual = 98039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 4 Bit Registers := 9 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 9 +---Muxes : 3 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 3 2 Input 2 Bit Muxes := 5 2 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port s_axis_tstrb[3] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tstrb[2] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tstrb[1] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tstrb[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[3] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[2] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[1] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axis_tuser[0] in module axis_dwidth_converter_v1_1_25_axis_dwidth_converter is either unconnected or has no load --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38018 ; free virtual = 98042 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38188 ; free virtual = 98215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38188 ; free virtual = 98215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38197 ; free virtual = 98224 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38205 ; free virtual = 98245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38205 ; free virtual = 98245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38202 ; free virtual = 98242 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38200 ; free virtual = 98241 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38199 ; free virtual = 98239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38199 ; free virtual = 98239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 1| |2 |LUT2 | 2| |3 |LUT3 | 1| |4 |LUT4 | 3| |5 |LUT5 | 2| |6 |LUT6 | 6| |7 |FDRE | 105| +------+-----+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38199 ; free virtual = 98239 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 12 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 3175.930 ; gain = 0.000 ; free physical = 38255 ; free virtual = 98282 Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3175.930 ; gain = 145.832 ; free physical = 38255 ; free virtual = 98282 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3175.930 ; gain = 0.000 ; free physical = 38330 ; free virtual = 98367 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3175.930 ; gain = 0.000 ; free physical = 38358 ; free virtual = 98388 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete, checksum: 17630e7b INFO: [Common 17-83] Releasing license: Synthesis 36 Infos, 70 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:53 . Memory (MB): peak = 3175.930 ; gain = 154.055 ; free physical = 38589 ; free virtual = 98620 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/dwidth_convert_synth_1/dwidth_convert.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP dwidth_convert, cache-ID = 42df8a96e17abdbc INFO: [Coretcl 2-1174] Renamed 2 cell refs. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.runs/dwidth_convert_synth_1/dwidth_convert.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file dwidth_convert_utilization_synth.rpt -pb dwidth_convert_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 19:49:21 2023...